diff --git a/arch/arm/SAME54/ld/same54n19a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld similarity index 100% rename from arch/arm/SAME54/ld/same54n19a_flash.ld rename to arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld diff --git a/arch/arm/SAME54/ld/same54n19a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld similarity index 100% rename from arch/arm/SAME54/ld/same54n19a_sram.ld rename to arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld diff --git a/arch/arm/SAME54/ld/same54n20a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld similarity index 100% rename from arch/arm/SAME54/ld/same54n20a_flash.ld rename to arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld diff --git a/arch/arm/SAME54/ld/same54n20a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld similarity index 100% rename from arch/arm/SAME54/ld/same54n20a_sram.ld rename to arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld diff --git a/arch/arm/SAME54/ld/same54p19a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld similarity index 100% rename from arch/arm/SAME54/ld/same54p19a_flash.ld rename to arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld diff --git a/arch/arm/SAME54/ld/same54p19a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld similarity index 100% rename from arch/arm/SAME54/ld/same54p19a_sram.ld rename to arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld diff --git a/arch/arm/SAME54/ld/same54p20a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54p20a_flash.ld similarity index 100% rename from arch/arm/SAME54/ld/same54p20a_flash.ld rename to arch/arm/SAME54/SAME54A/ld/same54p20a_flash.ld diff --git a/arch/arm/SAME54/ld/same54p20a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54p20a_sram.ld similarity index 100% rename from arch/arm/SAME54/ld/same54p20a_sram.ld rename to arch/arm/SAME54/SAME54A/ld/same54p20a_sram.ld diff --git a/arch/arm/SAME54/mcu/inc/component-version.h b/arch/arm/SAME54/SAME54A/mcu/inc/component-version.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component-version.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component-version.h diff --git a/arch/arm/SAME54/mcu/inc/component/ac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/ac.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h diff --git a/arch/arm/SAME54/mcu/inc/component/adc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/adc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h diff --git a/arch/arm/SAME54/mcu/inc/component/aes.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/aes.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h diff --git a/arch/arm/SAME54/mcu/inc/component/can.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/can.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/can.h diff --git a/arch/arm/SAME54/mcu/inc/component/ccl.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/ccl.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h diff --git a/arch/arm/SAME54/mcu/inc/component/cmcc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/cmcc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h diff --git a/arch/arm/SAME54/mcu/inc/component/dac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/dac.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h diff --git a/arch/arm/SAME54/mcu/inc/component/dmac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/dmac.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h diff --git a/arch/arm/SAME54/mcu/inc/component/dsu.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/dsu.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/dsu.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/dsu.h diff --git a/arch/arm/SAME54/mcu/inc/component/eic.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/eic.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/eic.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/eic.h diff --git a/arch/arm/SAME54/mcu/inc/component/evsys.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/evsys.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/evsys.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/evsys.h diff --git a/arch/arm/SAME54/mcu/inc/component/freqm.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/freqm.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/freqm.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/freqm.h diff --git a/arch/arm/SAME54/mcu/inc/component/gclk.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/gclk.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/gclk.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/gclk.h diff --git a/arch/arm/SAME54/mcu/inc/component/gmac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/gmac.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/gmac.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/gmac.h diff --git a/arch/arm/SAME54/mcu/inc/component/hmatrixb.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/hmatrixb.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/hmatrixb.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/hmatrixb.h diff --git a/arch/arm/SAME54/mcu/inc/component/i2s.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/i2s.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/i2s.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/i2s.h diff --git a/arch/arm/SAME54/mcu/inc/component/icm.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/icm.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/icm.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/icm.h diff --git a/arch/arm/SAME54/mcu/inc/component/mclk.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/mclk.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/mclk.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/mclk.h diff --git a/arch/arm/SAME54/mcu/inc/component/nvmctrl.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/nvmctrl.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/nvmctrl.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/nvmctrl.h diff --git a/arch/arm/SAME54/mcu/inc/component/osc32kctrl.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/osc32kctrl.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/osc32kctrl.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/osc32kctrl.h diff --git a/arch/arm/SAME54/mcu/inc/component/oscctrl.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/oscctrl.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/oscctrl.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/oscctrl.h diff --git a/arch/arm/SAME54/mcu/inc/component/pac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/pac.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/pac.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/pac.h diff --git a/arch/arm/SAME54/mcu/inc/component/pcc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/pcc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/pcc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/pcc.h diff --git a/arch/arm/SAME54/mcu/inc/component/pdec.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/pdec.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/pdec.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/pdec.h diff --git a/arch/arm/SAME54/mcu/inc/component/pm.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/pm.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/pm.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/pm.h diff --git a/arch/arm/SAME54/mcu/inc/component/port.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/port.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/port.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/port.h diff --git a/arch/arm/SAME54/mcu/inc/component/pukcc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/pukcc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/pukcc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/pukcc.h diff --git a/arch/arm/SAME54/mcu/inc/component/qspi.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/qspi.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/qspi.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/qspi.h diff --git a/arch/arm/SAME54/mcu/inc/component/ramecc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/ramecc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h diff --git a/arch/arm/SAME54/mcu/inc/component/rstc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/rstc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/rstc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/rstc.h diff --git a/arch/arm/SAME54/mcu/inc/component/rtc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/rtc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/rtc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/rtc.h diff --git a/arch/arm/SAME54/mcu/inc/component/sdhc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/sdhc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/sdhc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/sdhc.h diff --git a/arch/arm/SAME54/mcu/inc/component/sercom.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/sercom.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h diff --git a/arch/arm/SAME54/mcu/inc/component/supc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/supc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/supc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/supc.h diff --git a/arch/arm/SAME54/mcu/inc/component/tc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/tc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/tc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/tc.h diff --git a/arch/arm/SAME54/mcu/inc/component/tcc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/tcc.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/tcc.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/tcc.h diff --git a/arch/arm/SAME54/mcu/inc/component/trng.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/trng.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/trng.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/trng.h diff --git a/arch/arm/SAME54/mcu/inc/component/usb.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/usb.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/usb.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/usb.h diff --git a/arch/arm/SAME54/mcu/inc/component/wdt.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/wdt.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/component/wdt.h rename to arch/arm/SAME54/SAME54A/mcu/inc/component/wdt.h diff --git a/arch/arm/SAME54/mcu/inc/pio/same54n19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/pio/same54n19a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h diff --git a/arch/arm/SAME54/mcu/inc/pio/same54n20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/pio/same54n20a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h diff --git a/arch/arm/SAME54/mcu/inc/pio/same54p19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/pio/same54p19a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h diff --git a/arch/arm/SAME54/mcu/inc/pio/same54p20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/pio/same54p20a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h diff --git a/arch/arm/SAME54/mcu/inc/sam.h b/arch/arm/SAME54/SAME54A/mcu/inc/sam.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/sam.h rename to arch/arm/SAME54/SAME54A/mcu/inc/sam.h diff --git a/arch/arm/SAME54/mcu/inc/same54n19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/same54n19a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h diff --git a/arch/arm/SAME54/mcu/inc/same54n20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/same54n20a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h diff --git a/arch/arm/SAME54/mcu/inc/same54p19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/same54p19a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h diff --git a/arch/arm/SAME54/mcu/inc/same54p20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/same54p20a.h rename to arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h diff --git a/arch/arm/SAME54/mcu/inc/system_same54.h b/arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h similarity index 100% rename from arch/arm/SAME54/mcu/inc/system_same54.h rename to arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h diff --git a/arch/arm/SAME54/mcu/src/startup_same54n19a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n19a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/startup_same54n19a.c rename to arch/arm/SAME54/SAME54A/mcu/src/startup_same54n19a.c diff --git a/arch/arm/SAME54/mcu/src/startup_same54n20a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n20a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/startup_same54n20a.c rename to arch/arm/SAME54/SAME54A/mcu/src/startup_same54n20a.c diff --git a/arch/arm/SAME54/mcu/src/startup_same54p19a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p19a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/startup_same54p19a.c rename to arch/arm/SAME54/SAME54A/mcu/src/startup_same54p19a.c diff --git a/arch/arm/SAME54/mcu/src/startup_same54p20a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p20a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/startup_same54p20a.c rename to arch/arm/SAME54/SAME54A/mcu/src/startup_same54p20a.c diff --git a/arch/arm/SAME54/mcu/src/system_same54n19a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54n19a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/system_same54n19a.c rename to arch/arm/SAME54/SAME54A/mcu/src/system_same54n19a.c diff --git a/arch/arm/SAME54/mcu/src/system_same54n20a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54n20a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/system_same54n20a.c rename to arch/arm/SAME54/SAME54A/mcu/src/system_same54n20a.c diff --git a/arch/arm/SAME54/mcu/src/system_same54p19a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54p19a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/system_same54p19a.c rename to arch/arm/SAME54/SAME54A/mcu/src/system_same54p19a.c diff --git a/arch/arm/SAME54/mcu/src/system_same54p20a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54p20a.c similarity index 100% rename from arch/arm/SAME54/mcu/src/system_same54p20a.c rename to arch/arm/SAME54/SAME54A/mcu/src/system_same54p20a.c diff --git a/arch/arm/SAME70/SAME70A/ld/same70j19_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70j19_flash.ld new file mode 100644 index 00000000..5e83162f --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j19_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70j19_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70j19_sram.ld new file mode 100644 index 00000000..88de6247 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j19_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70j20_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70j20_flash.ld new file mode 100644 index 00000000..31df551b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j20_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70j20_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70j20_sram.ld new file mode 100644 index 00000000..a559671e --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j20_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70j21_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70j21_flash.ld new file mode 100644 index 00000000..f3ddaab6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j21_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70j21_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70j21_sram.ld new file mode 100644 index 00000000..42e3b3d8 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70j21_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70n19_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70n19_flash.ld new file mode 100644 index 00000000..e3b44763 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n19_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70n19_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70n19_sram.ld new file mode 100644 index 00000000..6eef7c66 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n19_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70n20_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70n20_flash.ld new file mode 100644 index 00000000..9f18a1a5 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n20_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70n20_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70n20_sram.ld new file mode 100644 index 00000000..8660d1f3 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n20_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70n21_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70n21_flash.ld new file mode 100644 index 00000000..a1baca28 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n21_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70n21_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70n21_sram.ld new file mode 100644 index 00000000..e2009a68 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70n21_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70q19_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70q19_flash.ld new file mode 100644 index 00000000..4fdf89a0 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q19_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70q19_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70q19_sram.ld new file mode 100644 index 00000000..897155e3 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q19_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70q20_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70q20_flash.ld new file mode 100644 index 00000000..ae9b22ca --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q20_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70q20_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70q20_sram.ld new file mode 100644 index 00000000..81957af7 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q20_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/ld/same70q21_flash.ld b/arch/arm/SAME70/SAME70A/ld/same70q21_flash.ld new file mode 100644 index 00000000..20f2bd51 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q21_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70A/ld/same70q21_sram.ld b/arch/arm/SAME70/SAME70A/ld/same70q21_sram.ld new file mode 100644 index 00000000..99a8cccf --- /dev/null +++ b/arch/arm/SAME70/SAME70A/ld/same70q21_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component-version.h b/arch/arm/SAME70/SAME70A/mcu/inc/component-version.h new file mode 100644 index 00000000..d91c8a97 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 4 +#define COMPONENT_VERSION_MINOR 4 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 40004 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 78 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "4.4" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2020-09-24 08:34:52" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/acc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/acc.h new file mode 100644 index 00000000..88b3e04c --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/acc.h @@ -0,0 +1,215 @@ +/** + * \brief Component description for ACC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_ACC_COMPONENT_H_ +#define _SAME70_ACC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ACC */ +/* ************************************************************************** */ + +/* -------- ACC_CR : (ACC Offset: 0x00) ( /W 32) Control Register -------- */ +#define ACC_CR_SWRST_Pos _U_(0) /**< (ACC_CR) Software Reset Position */ +#define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */ +#define ACC_CR_SWRST(value) (ACC_CR_SWRST_Msk & ((value) << ACC_CR_SWRST_Pos)) +#define ACC_CR_Msk _U_(0x00000001) /**< (ACC_CR) Register Mask */ + + +/* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos _U_(0) /**< (ACC_MR) Selection for Minus Comparator Input Position */ +#define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */ +#define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)) +#define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */ +#define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */ +#define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */ +#define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_Pos _U_(4) /**< (ACC_MR) Selection For Plus Comparator Input Position */ +#define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */ +#define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)) +#define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */ +#define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */ +#define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */ +#define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */ +#define ACC_MR_ACEN_Pos _U_(8) /**< (ACC_MR) Analog Comparator Enable Position */ +#define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */ +#define ACC_MR_ACEN(value) (ACC_MR_ACEN_Msk & ((value) << ACC_MR_ACEN_Pos)) +#define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */ +#define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */ +#define ACC_MR_EDGETYP_Pos _U_(9) /**< (ACC_MR) Edge Type Position */ +#define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */ +#define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)) +#define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */ +#define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */ +#define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */ +#define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */ +#define ACC_MR_INV_Pos _U_(12) /**< (ACC_MR) Invert Comparator Output Position */ +#define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */ +#define ACC_MR_INV(value) (ACC_MR_INV_Msk & ((value) << ACC_MR_INV_Pos)) +#define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */ +#define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */ +#define ACC_MR_SELFS_Pos _U_(13) /**< (ACC_MR) Selection Of Fault Source Position */ +#define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */ +#define ACC_MR_SELFS(value) (ACC_MR_SELFS_Msk & ((value) << ACC_MR_SELFS_Pos)) +#define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */ +#define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */ +#define ACC_MR_FE_Pos _U_(14) /**< (ACC_MR) Fault Enable Position */ +#define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */ +#define ACC_MR_FE(value) (ACC_MR_FE_Msk & ((value) << ACC_MR_FE_Pos)) +#define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +#define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */ +#define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */ +#define ACC_MR_Msk _U_(0x00007777) /**< (ACC_MR) Register Mask */ + + +/* -------- ACC_IER : (ACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define ACC_IER_CE_Pos _U_(0) /**< (ACC_IER) Comparison Edge Position */ +#define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */ +#define ACC_IER_CE(value) (ACC_IER_CE_Msk & ((value) << ACC_IER_CE_Pos)) +#define ACC_IER_Msk _U_(0x00000001) /**< (ACC_IER) Register Mask */ + + +/* -------- ACC_IDR : (ACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define ACC_IDR_CE_Pos _U_(0) /**< (ACC_IDR) Comparison Edge Position */ +#define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */ +#define ACC_IDR_CE(value) (ACC_IDR_CE_Msk & ((value) << ACC_IDR_CE_Pos)) +#define ACC_IDR_Msk _U_(0x00000001) /**< (ACC_IDR) Register Mask */ + + +/* -------- ACC_IMR : (ACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define ACC_IMR_CE_Pos _U_(0) /**< (ACC_IMR) Comparison Edge Position */ +#define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */ +#define ACC_IMR_CE(value) (ACC_IMR_CE_Msk & ((value) << ACC_IMR_CE_Pos)) +#define ACC_IMR_Msk _U_(0x00000001) /**< (ACC_IMR) Register Mask */ + + +/* -------- ACC_ISR : (ACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */ +#define ACC_ISR_CE_Pos _U_(0) /**< (ACC_ISR) Comparison Edge (cleared on read) Position */ +#define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */ +#define ACC_ISR_CE(value) (ACC_ISR_CE_Msk & ((value) << ACC_ISR_CE_Pos)) +#define ACC_ISR_SCO_Pos _U_(1) /**< (ACC_ISR) Synchronized Comparator Output Position */ +#define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */ +#define ACC_ISR_SCO(value) (ACC_ISR_SCO_Msk & ((value) << ACC_ISR_SCO_Pos)) +#define ACC_ISR_MASK_Pos _U_(31) /**< (ACC_ISR) Flag Mask Position */ +#define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */ +#define ACC_ISR_MASK(value) (ACC_ISR_MASK_Msk & ((value) << ACC_ISR_MASK_Pos)) +#define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */ + + +/* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */ +#define ACC_ACR_ISEL_Pos _U_(0) /**< (ACC_ACR) Current Selection Position */ +#define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */ +#define ACC_ACR_ISEL(value) (ACC_ACR_ISEL_Msk & ((value) << ACC_ACR_ISEL_Pos)) +#define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */ +#define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */ +#define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */ +#define ACC_ACR_HYST_Pos _U_(1) /**< (ACC_ACR) Hysteresis Selection Position */ +#define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */ +#define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)) +#define ACC_ACR_Msk _U_(0x00000007) /**< (ACC_ACR) Register Mask */ + + +/* -------- ACC_WPMR : (ACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN_Pos _U_(0) /**< (ACC_WPMR) Write Protection Enable Position */ +#define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */ +#define ACC_WPMR_WPEN(value) (ACC_WPMR_WPEN_Msk & ((value) << ACC_WPMR_WPEN_Pos)) +#define ACC_WPMR_WPKEY_Pos _U_(8) /**< (ACC_WPMR) Write Protection Key Position */ +#define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */ +#define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)) +#define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */ + + +/* -------- ACC_WPSR : (ACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS_Pos _U_(0) /**< (ACC_WPSR) Write Protection Violation Status Position */ +#define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */ +#define ACC_WPSR_WPVS(value) (ACC_WPSR_WPVS_Msk & ((value) << ACC_WPSR_WPVS_Pos)) +#define ACC_WPSR_Msk _U_(0x00000001) /**< (ACC_WPSR) Register Mask */ + + +/** \brief ACC register offsets definitions */ +#define ACC_CR_REG_OFST (0x00) /**< (ACC_CR) Control Register Offset */ +#define ACC_MR_REG_OFST (0x04) /**< (ACC_MR) Mode Register Offset */ +#define ACC_IER_REG_OFST (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */ +#define ACC_IDR_REG_OFST (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */ +#define ACC_IMR_REG_OFST (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */ +#define ACC_ISR_REG_OFST (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */ +#define ACC_ACR_REG_OFST (0x94) /**< (ACC_ACR) Analog Control Register Offset */ +#define ACC_WPMR_REG_OFST (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */ +#define ACC_WPSR_REG_OFST (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ACC register API structure */ +typedef struct +{ + __O uint32_t ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[0x1C]; + __O uint32_t ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x60]; + __IO uint32_t ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */ + __I uint8_t Reserved3[0x4C]; + __IO uint32_t ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} acc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ACC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/aes.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/aes.h new file mode 100644 index 00000000..4f3d652c --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/aes.h @@ -0,0 +1,295 @@ +/** + * \brief Component description for AES + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_AES_COMPONENT_H_ +#define _SAME70_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CR : (AES Offset: 0x00) ( /W 32) Control Register -------- */ +#define AES_CR_START_Pos _U_(0) /**< (AES_CR) Start Processing Position */ +#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */ +#define AES_CR_START(value) (AES_CR_START_Msk & ((value) << AES_CR_START_Pos)) +#define AES_CR_SWRST_Pos _U_(8) /**< (AES_CR) Software Reset Position */ +#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */ +#define AES_CR_SWRST(value) (AES_CR_SWRST_Msk & ((value) << AES_CR_SWRST_Pos)) +#define AES_CR_Msk _U_(0x00000101) /**< (AES_CR) Register Mask */ + + +/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */ +#define AES_MR_CIPHER_Pos _U_(0) /**< (AES_MR) Processing Mode Position */ +#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */ +#define AES_MR_CIPHER(value) (AES_MR_CIPHER_Msk & ((value) << AES_MR_CIPHER_Pos)) +#define AES_MR_GTAGEN_Pos _U_(1) /**< (AES_MR) GCM Automatic Tag Generation Enable Position */ +#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */ +#define AES_MR_GTAGEN(value) (AES_MR_GTAGEN_Msk & ((value) << AES_MR_GTAGEN_Pos)) +#define AES_MR_DUALBUFF_Pos _U_(3) /**< (AES_MR) Dual Input Buffer Position */ +#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */ +#define AES_MR_DUALBUFF(value) (AES_MR_DUALBUFF_Msk & ((value) << AES_MR_DUALBUFF_Pos)) +#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */ +#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */ +#define AES_MR_PROCDLY_Pos _U_(4) /**< (AES_MR) Processing Delay Position */ +#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */ +#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)) +#define AES_MR_SMOD_Pos _U_(8) /**< (AES_MR) Start Mode Position */ +#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */ +#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)) +#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */ +#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */ +#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */ +#define AES_MR_KEYSIZE_Pos _U_(10) /**< (AES_MR) Key Size Position */ +#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */ +#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)) +#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */ +#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */ +#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */ +#define AES_MR_OPMOD_Pos _U_(12) /**< (AES_MR) Operating Mode Position */ +#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */ +#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)) +#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */ +#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */ +#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */ +#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */ +#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */ +#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */ +#define AES_MR_LOD_Pos _U_(15) /**< (AES_MR) Last Output Data Mode Position */ +#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */ +#define AES_MR_LOD(value) (AES_MR_LOD_Msk & ((value) << AES_MR_LOD_Pos)) +#define AES_MR_CFBS_Pos _U_(16) /**< (AES_MR) Cipher Feedback Data Size Position */ +#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */ +#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)) +#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */ +#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */ +#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */ +#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */ +#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */ +#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */ +#define AES_MR_CKEY_Pos _U_(20) /**< (AES_MR) Countermeasure Key Position */ +#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */ +#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)) +#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */ +#define AES_MR_Msk _U_(0x00F7FFFB) /**< (AES_MR) Register Mask */ + + +/* -------- AES_IER : (AES Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY_Pos _U_(0) /**< (AES_IER) Data Ready Interrupt Enable Position */ +#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */ +#define AES_IER_DATRDY(value) (AES_IER_DATRDY_Msk & ((value) << AES_IER_DATRDY_Pos)) +#define AES_IER_URAD_Pos _U_(8) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */ +#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */ +#define AES_IER_URAD(value) (AES_IER_URAD_Msk & ((value) << AES_IER_URAD_Pos)) +#define AES_IER_TAGRDY_Pos _U_(16) /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */ +#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */ +#define AES_IER_TAGRDY(value) (AES_IER_TAGRDY_Msk & ((value) << AES_IER_TAGRDY_Pos)) +#define AES_IER_Msk _U_(0x00010101) /**< (AES_IER) Register Mask */ + + +/* -------- AES_IDR : (AES Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY_Pos _U_(0) /**< (AES_IDR) Data Ready Interrupt Disable Position */ +#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */ +#define AES_IDR_DATRDY(value) (AES_IDR_DATRDY_Msk & ((value) << AES_IDR_DATRDY_Pos)) +#define AES_IDR_URAD_Pos _U_(8) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */ +#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */ +#define AES_IDR_URAD(value) (AES_IDR_URAD_Msk & ((value) << AES_IDR_URAD_Pos)) +#define AES_IDR_TAGRDY_Pos _U_(16) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */ +#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */ +#define AES_IDR_TAGRDY(value) (AES_IDR_TAGRDY_Msk & ((value) << AES_IDR_TAGRDY_Pos)) +#define AES_IDR_Msk _U_(0x00010101) /**< (AES_IDR) Register Mask */ + + +/* -------- AES_IMR : (AES Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY_Pos _U_(0) /**< (AES_IMR) Data Ready Interrupt Mask Position */ +#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */ +#define AES_IMR_DATRDY(value) (AES_IMR_DATRDY_Msk & ((value) << AES_IMR_DATRDY_Pos)) +#define AES_IMR_URAD_Pos _U_(8) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */ +#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */ +#define AES_IMR_URAD(value) (AES_IMR_URAD_Msk & ((value) << AES_IMR_URAD_Pos)) +#define AES_IMR_TAGRDY_Pos _U_(16) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */ +#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */ +#define AES_IMR_TAGRDY(value) (AES_IMR_TAGRDY_Msk & ((value) << AES_IMR_TAGRDY_Pos)) +#define AES_IMR_Msk _U_(0x00010101) /**< (AES_IMR) Register Mask */ + + +/* -------- AES_ISR : (AES Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY_Pos _U_(0) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */ +#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */ +#define AES_ISR_DATRDY(value) (AES_ISR_DATRDY_Msk & ((value) << AES_ISR_DATRDY_Pos)) +#define AES_ISR_URAD_Pos _U_(8) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAD(value) (AES_ISR_URAD_Msk & ((value) << AES_ISR_URAD_Pos)) +#define AES_ISR_URAT_Pos _U_(12) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos)) +#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */ +#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */ +#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */ +#define AES_ISR_TAGRDY_Pos _U_(16) /**< (AES_ISR) GCM Tag Ready Position */ +#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */ +#define AES_ISR_TAGRDY(value) (AES_ISR_TAGRDY_Msk & ((value) << AES_ISR_TAGRDY_Pos)) +#define AES_ISR_Msk _U_(0x0001F101) /**< (AES_ISR) Register Mask */ + + +/* -------- AES_KEYWR : (AES Offset: 0x20) ( /W 32) Key Word Register 0 -------- */ +#define AES_KEYWR_KEYW_Pos _U_(0) /**< (AES_KEYWR) Key Word Position */ +#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */ +#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)) +#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */ + + +/* -------- AES_IDATAR : (AES Offset: 0x40) ( /W 32) Input Data Register 0 -------- */ +#define AES_IDATAR_IDATA_Pos _U_(0) /**< (AES_IDATAR) Input Data Word Position */ +#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */ +#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)) +#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */ + + +/* -------- AES_ODATAR : (AES Offset: 0x50) ( R/ 32) Output Data Register 0 -------- */ +#define AES_ODATAR_ODATA_Pos _U_(0) /**< (AES_ODATAR) Output Data Position */ +#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */ +#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos)) +#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */ + + +/* -------- AES_IVR : (AES Offset: 0x60) ( /W 32) Initialization Vector Register 0 -------- */ +#define AES_IVR_IV_Pos _U_(0) /**< (AES_IVR) Initialization Vector Position */ +#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */ +#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)) +#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */ + + +/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos _U_(0) /**< (AES_AADLENR) Additional Authenticated Data Length Position */ +#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */ +#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)) +#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */ + + +/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos _U_(0) /**< (AES_CLENR) Plaintext/Ciphertext Length Position */ +#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */ +#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)) +#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */ + + +/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register 0 -------- */ +#define AES_GHASHR_GHASH_Pos _U_(0) /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */ +#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */ +#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)) +#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */ + + +/* -------- AES_TAGR : (AES Offset: 0x88) ( R/ 32) GCM Authentication Tag Word Register 0 -------- */ +#define AES_TAGR_TAG_Pos _U_(0) /**< (AES_TAGR) GCM Authentication Tag x Position */ +#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */ +#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos)) +#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */ + + +/* -------- AES_CTRR : (AES Offset: 0x98) ( R/ 32) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos _U_(0) /**< (AES_CTRR) GCM Encryption Counter Position */ +#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */ +#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos)) +#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */ + + +/* -------- AES_GCMHR : (AES Offset: 0x9C) (R/W 32) GCM H Word Register 0 -------- */ +#define AES_GCMHR_H_Pos _U_(0) /**< (AES_GCMHR) GCM H Word x Position */ +#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */ +#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)) +#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CR_REG_OFST (0x00) /**< (AES_CR) Control Register Offset */ +#define AES_MR_REG_OFST (0x04) /**< (AES_MR) Mode Register Offset */ +#define AES_IER_REG_OFST (0x10) /**< (AES_IER) Interrupt Enable Register Offset */ +#define AES_IDR_REG_OFST (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */ +#define AES_IMR_REG_OFST (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */ +#define AES_ISR_REG_OFST (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */ +#define AES_KEYWR_REG_OFST (0x20) /**< (AES_KEYWR) Key Word Register 0 Offset */ +#define AES_IDATAR_REG_OFST (0x40) /**< (AES_IDATAR) Input Data Register 0 Offset */ +#define AES_ODATAR_REG_OFST (0x50) /**< (AES_ODATAR) Output Data Register 0 Offset */ +#define AES_IVR_REG_OFST (0x60) /**< (AES_IVR) Initialization Vector Register 0 Offset */ +#define AES_AADLENR_REG_OFST (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */ +#define AES_CLENR_REG_OFST (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */ +#define AES_GHASHR_REG_OFST (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register 0 Offset */ +#define AES_TAGR_REG_OFST (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register 0 Offset */ +#define AES_CTRR_REG_OFST (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */ +#define AES_GCMHR_REG_OFST (0x9C) /**< (AES_GCMHR) GCM H Word Register 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ + __O uint32_t AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[0x08]; + __O uint32_t AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register 0 */ + __O uint32_t AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register 0 */ + __I uint32_t AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register 0 */ + __O uint32_t AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register 0 */ + __IO uint32_t AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register 0 */ + __I uint32_t AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register 0 */ + __I uint32_t AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register 0 */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_AES_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/afec.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/afec.h new file mode 100644 index 00000000..ed8a73fd --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/afec.h @@ -0,0 +1,998 @@ +/** + * \brief Component description for AFEC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_AFEC_COMPONENT_H_ +#define _SAME70_AFEC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AFEC */ +/* ************************************************************************** */ + +/* -------- AFEC_CR : (AFEC Offset: 0x00) ( /W 32) AFEC Control Register -------- */ +#define AFEC_CR_SWRST_Pos _U_(0) /**< (AFEC_CR) Software Reset Position */ +#define AFEC_CR_SWRST_Msk (_U_(0x1) << AFEC_CR_SWRST_Pos) /**< (AFEC_CR) Software Reset Mask */ +#define AFEC_CR_SWRST(value) (AFEC_CR_SWRST_Msk & ((value) << AFEC_CR_SWRST_Pos)) +#define AFEC_CR_START_Pos _U_(1) /**< (AFEC_CR) Start Conversion Position */ +#define AFEC_CR_START_Msk (_U_(0x1) << AFEC_CR_START_Pos) /**< (AFEC_CR) Start Conversion Mask */ +#define AFEC_CR_START(value) (AFEC_CR_START_Msk & ((value) << AFEC_CR_START_Pos)) +#define AFEC_CR_Msk _U_(0x00000003) /**< (AFEC_CR) Register Mask */ + + +/* -------- AFEC_MR : (AFEC Offset: 0x04) (R/W 32) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN_Pos _U_(0) /**< (AFEC_MR) Trigger Enable Position */ +#define AFEC_MR_TRGEN_Msk (_U_(0x1) << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Trigger Enable Mask */ +#define AFEC_MR_TRGEN(value) (AFEC_MR_TRGEN_Msk & ((value) << AFEC_MR_TRGEN_Pos)) +#define AFEC_MR_TRGEN_DIS_Val _U_(0x0) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN_Val _U_(0x1) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGEN_DIS (AFEC_MR_TRGEN_DIS_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. Position */ +#define AFEC_MR_TRGEN_EN (AFEC_MR_TRGEN_EN_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. Position */ +#define AFEC_MR_TRGSEL_Pos _U_(1) /**< (AFEC_MR) Trigger Selection Position */ +#define AFEC_MR_TRGSEL_Msk (_U_(0x7) << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Trigger Selection Mask */ +#define AFEC_MR_TRGSEL(value) (AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)) +#define AFEC_MR_TRGSEL_AFEC_TRIG0_Val _U_(0x0) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1_Val _U_(0x1) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2_Val _U_(0x2) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3_Val _U_(0x3) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4_Val _U_(0x4) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5_Val _U_(0x5) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6_Val _U_(0x6) /**< (AFEC_MR) Analog Comparator */ +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (AFEC_MR_TRGSEL_AFEC_TRIG0_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (AFEC_MR_TRGSEL_AFEC_TRIG1_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (AFEC_MR_TRGSEL_AFEC_TRIG2_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (AFEC_MR_TRGSEL_AFEC_TRIG3_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (AFEC_MR_TRGSEL_AFEC_TRIG4_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (AFEC_MR_TRGSEL_AFEC_TRIG5_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (AFEC_MR_TRGSEL_AFEC_TRIG6_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Analog Comparator Position */ +#define AFEC_MR_SLEEP_Pos _U_(5) /**< (AFEC_MR) Sleep Mode Position */ +#define AFEC_MR_SLEEP_Msk (_U_(0x1) << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep Mode Mask */ +#define AFEC_MR_SLEEP(value) (AFEC_MR_SLEEP_Msk & ((value) << AFEC_MR_SLEEP_Pos)) +#define AFEC_MR_SLEEP_NORMAL_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP_Val _U_(0x1) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_SLEEP_NORMAL (AFEC_MR_SLEEP_NORMAL_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. Position */ +#define AFEC_MR_SLEEP_SLEEP (AFEC_MR_SLEEP_SLEEP_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. Position */ +#define AFEC_MR_FWUP_Pos _U_(6) /**< (AFEC_MR) Fast Wake-up Position */ +#define AFEC_MR_FWUP_Msk (_U_(0x1) << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast Wake-up Mask */ +#define AFEC_MR_FWUP(value) (AFEC_MR_FWUP_Msk & ((value) << AFEC_MR_FWUP_Pos)) +#define AFEC_MR_FWUP_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON_Val _U_(0x1) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FWUP_OFF (AFEC_MR_FWUP_OFF_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. Position */ +#define AFEC_MR_FWUP_ON (AFEC_MR_FWUP_ON_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. Position */ +#define AFEC_MR_FREERUN_Pos _U_(7) /**< (AFEC_MR) Free Run Mode Position */ +#define AFEC_MR_FREERUN_Msk (_U_(0x1) << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run Mode Mask */ +#define AFEC_MR_FREERUN(value) (AFEC_MR_FREERUN_Msk & ((value) << AFEC_MR_FREERUN_Pos)) +#define AFEC_MR_FREERUN_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON_Val _U_(0x1) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_FREERUN_OFF (AFEC_MR_FREERUN_OFF_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Normal mode Position */ +#define AFEC_MR_FREERUN_ON (AFEC_MR_FREERUN_ON_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. Position */ +#define AFEC_MR_PRESCAL_Pos _U_(8) /**< (AFEC_MR) Prescaler Rate Selection Position */ +#define AFEC_MR_PRESCAL_Msk (_U_(0xFF) << AFEC_MR_PRESCAL_Pos) /**< (AFEC_MR) Prescaler Rate Selection Mask */ +#define AFEC_MR_PRESCAL(value) (AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)) +#define AFEC_MR_STARTUP_Pos _U_(16) /**< (AFEC_MR) Start-up Time Position */ +#define AFEC_MR_STARTUP_Msk (_U_(0xF) << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) Start-up Time Mask */ +#define AFEC_MR_STARTUP(value) (AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)) +#define AFEC_MR_STARTUP_SUT0_Val _U_(0x0) /**< (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8_Val _U_(0x1) /**< (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16_Val _U_(0x2) /**< (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24_Val _U_(0x3) /**< (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64_Val _U_(0x4) /**< (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80_Val _U_(0x5) /**< (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96_Val _U_(0x6) /**< (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112_Val _U_(0x7) /**< (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512_Val _U_(0x8) /**< (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576_Val _U_(0x9) /**< (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640_Val _U_(0xA) /**< (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704_Val _U_(0xB) /**< (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768_Val _U_(0xC) /**< (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832_Val _U_(0xD) /**< (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896_Val _U_(0xE) /**< (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960_Val _U_(0xF) /**< (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT0 (AFEC_MR_STARTUP_SUT0_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 0 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT8 (AFEC_MR_STARTUP_SUT8_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 8 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT16 (AFEC_MR_STARTUP_SUT16_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 16 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT24 (AFEC_MR_STARTUP_SUT24_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 24 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT64 (AFEC_MR_STARTUP_SUT64_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 64 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT80 (AFEC_MR_STARTUP_SUT80_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 80 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT96 (AFEC_MR_STARTUP_SUT96_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 96 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT112 (AFEC_MR_STARTUP_SUT112_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 112 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT512 (AFEC_MR_STARTUP_SUT512_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 512 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT576 (AFEC_MR_STARTUP_SUT576_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 576 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT640 (AFEC_MR_STARTUP_SUT640_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 640 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT704 (AFEC_MR_STARTUP_SUT704_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 704 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT768 (AFEC_MR_STARTUP_SUT768_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 768 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT832 (AFEC_MR_STARTUP_SUT832_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 832 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT896 (AFEC_MR_STARTUP_SUT896_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 896 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT960 (AFEC_MR_STARTUP_SUT960_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 960 periods of AFE clock Position */ +#define AFEC_MR_ONE_Pos _U_(23) /**< (AFEC_MR) One Position */ +#define AFEC_MR_ONE_Msk (_U_(0x1) << AFEC_MR_ONE_Pos) /**< (AFEC_MR) One Mask */ +#define AFEC_MR_ONE(value) (AFEC_MR_ONE_Msk & ((value) << AFEC_MR_ONE_Pos)) +#define AFEC_MR_TRACKTIM_Pos _U_(24) /**< (AFEC_MR) Tracking Time Position */ +#define AFEC_MR_TRACKTIM_Msk (_U_(0xF) << AFEC_MR_TRACKTIM_Pos) /**< (AFEC_MR) Tracking Time Mask */ +#define AFEC_MR_TRACKTIM(value) (AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)) +#define AFEC_MR_TRANSFER_Pos _U_(28) /**< (AFEC_MR) Transfer Period Position */ +#define AFEC_MR_TRANSFER_Msk (_U_(0x3) << AFEC_MR_TRANSFER_Pos) /**< (AFEC_MR) Transfer Period Mask */ +#define AFEC_MR_TRANSFER(value) (AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)) +#define AFEC_MR_USEQ_Pos _U_(31) /**< (AFEC_MR) User Sequence Enable Position */ +#define AFEC_MR_USEQ_Msk (_U_(0x1) << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence Enable Mask */ +#define AFEC_MR_USEQ(value) (AFEC_MR_USEQ_Msk & ((value) << AFEC_MR_USEQ_Pos)) +#define AFEC_MR_USEQ_NUM_ORDER_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER_Val _U_(0x1) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +#define AFEC_MR_USEQ_NUM_ORDER (AFEC_MR_USEQ_NUM_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. Position */ +#define AFEC_MR_USEQ_REG_ORDER (AFEC_MR_USEQ_REG_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. Position */ +#define AFEC_MR_Msk _U_(0xBF8FFFEF) /**< (AFEC_MR) Register Mask */ + + +/* -------- AFEC_EMR : (AFEC Offset: 0x08) (R/W 32) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos _U_(0) /**< (AFEC_EMR) Comparison Mode Position */ +#define AFEC_EMR_CMPMODE_Msk (_U_(0x3) << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Comparison Mode Mask */ +#define AFEC_EMR_CMPMODE(value) (AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)) +#define AFEC_EMR_CMPMODE_LOW_Val _U_(0x0) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH_Val _U_(0x1) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN_Val _U_(0x2) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT_Val _U_(0x3) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPMODE_LOW (AFEC_EMR_CMPMODE_LOW_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_HIGH (AFEC_EMR_CMPMODE_HIGH_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_IN (AFEC_EMR_CMPMODE_IN_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_EMR_CMPMODE_OUT (AFEC_EMR_CMPMODE_OUT_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_EMR_CMPSEL_Pos _U_(3) /**< (AFEC_EMR) Comparison Selected Channel Position */ +#define AFEC_EMR_CMPSEL_Msk (_U_(0x1F) << AFEC_EMR_CMPSEL_Pos) /**< (AFEC_EMR) Comparison Selected Channel Mask */ +#define AFEC_EMR_CMPSEL(value) (AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)) +#define AFEC_EMR_CMPALL_Pos _U_(9) /**< (AFEC_EMR) Compare All Channels Position */ +#define AFEC_EMR_CMPALL_Msk (_U_(0x1) << AFEC_EMR_CMPALL_Pos) /**< (AFEC_EMR) Compare All Channels Mask */ +#define AFEC_EMR_CMPALL(value) (AFEC_EMR_CMPALL_Msk & ((value) << AFEC_EMR_CMPALL_Pos)) +#define AFEC_EMR_CMPFILTER_Pos _U_(12) /**< (AFEC_EMR) Compare Event Filtering Position */ +#define AFEC_EMR_CMPFILTER_Msk (_U_(0x3) << AFEC_EMR_CMPFILTER_Pos) /**< (AFEC_EMR) Compare Event Filtering Mask */ +#define AFEC_EMR_CMPFILTER(value) (AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)) +#define AFEC_EMR_RES_Pos _U_(16) /**< (AFEC_EMR) Resolution Position */ +#define AFEC_EMR_RES_Msk (_U_(0x7) << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) Resolution Mask */ +#define AFEC_EMR_RES(value) (AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)) +#define AFEC_EMR_RES_NO_AVERAGE_Val _U_(0x0) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4_Val _U_(0x2) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16_Val _U_(0x3) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64_Val _U_(0x4) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256_Val _U_(0x5) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_RES_NO_AVERAGE (AFEC_EMR_RES_NO_AVERAGE_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). Position */ +#define AFEC_EMR_RES_OSR4 (AFEC_EMR_RES_OSR4_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). Position */ +#define AFEC_EMR_RES_OSR16 (AFEC_EMR_RES_OSR16_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). Position */ +#define AFEC_EMR_RES_OSR64 (AFEC_EMR_RES_OSR64_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). Position */ +#define AFEC_EMR_RES_OSR256 (AFEC_EMR_RES_OSR256_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). Position */ +#define AFEC_EMR_TAG_Pos _U_(24) /**< (AFEC_EMR) TAG of the AFEC_LDCR Position */ +#define AFEC_EMR_TAG_Msk (_U_(0x1) << AFEC_EMR_TAG_Pos) /**< (AFEC_EMR) TAG of the AFEC_LDCR Mask */ +#define AFEC_EMR_TAG(value) (AFEC_EMR_TAG_Msk & ((value) << AFEC_EMR_TAG_Pos)) +#define AFEC_EMR_STM_Pos _U_(25) /**< (AFEC_EMR) Single Trigger Mode Position */ +#define AFEC_EMR_STM_Msk (_U_(0x1) << AFEC_EMR_STM_Pos) /**< (AFEC_EMR) Single Trigger Mode Mask */ +#define AFEC_EMR_STM(value) (AFEC_EMR_STM_Msk & ((value) << AFEC_EMR_STM_Pos)) +#define AFEC_EMR_SIGNMODE_Pos _U_(28) /**< (AFEC_EMR) Sign Mode Position */ +#define AFEC_EMR_SIGNMODE_Msk (_U_(0x3) << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Sign Mode Mask */ +#define AFEC_EMR_SIGNMODE(value) (AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val _U_(0x0) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val _U_(0x1) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val _U_(0x2) /**< (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED_Val _U_(0x3) /**< (AFEC_EMR) All channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. Position */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (AFEC_EMR_SIGNMODE_ALL_SIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Signed conversions. Position */ +#define AFEC_EMR_Msk _U_(0x330732FB) /**< (AFEC_EMR) Register Mask */ + + +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) (R/W 32) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos _U_(0) /**< (AFEC_SEQ1R) User Sequence Number 0 Position */ +#define AFEC_SEQ1R_USCH0_Msk (_U_(0xF) << AFEC_SEQ1R_USCH0_Pos) /**< (AFEC_SEQ1R) User Sequence Number 0 Mask */ +#define AFEC_SEQ1R_USCH0(value) (AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)) +#define AFEC_SEQ1R_USCH1_Pos _U_(4) /**< (AFEC_SEQ1R) User Sequence Number 1 Position */ +#define AFEC_SEQ1R_USCH1_Msk (_U_(0xF) << AFEC_SEQ1R_USCH1_Pos) /**< (AFEC_SEQ1R) User Sequence Number 1 Mask */ +#define AFEC_SEQ1R_USCH1(value) (AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)) +#define AFEC_SEQ1R_USCH2_Pos _U_(8) /**< (AFEC_SEQ1R) User Sequence Number 2 Position */ +#define AFEC_SEQ1R_USCH2_Msk (_U_(0xF) << AFEC_SEQ1R_USCH2_Pos) /**< (AFEC_SEQ1R) User Sequence Number 2 Mask */ +#define AFEC_SEQ1R_USCH2(value) (AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)) +#define AFEC_SEQ1R_USCH3_Pos _U_(12) /**< (AFEC_SEQ1R) User Sequence Number 3 Position */ +#define AFEC_SEQ1R_USCH3_Msk (_U_(0xF) << AFEC_SEQ1R_USCH3_Pos) /**< (AFEC_SEQ1R) User Sequence Number 3 Mask */ +#define AFEC_SEQ1R_USCH3(value) (AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)) +#define AFEC_SEQ1R_USCH4_Pos _U_(16) /**< (AFEC_SEQ1R) User Sequence Number 4 Position */ +#define AFEC_SEQ1R_USCH4_Msk (_U_(0xF) << AFEC_SEQ1R_USCH4_Pos) /**< (AFEC_SEQ1R) User Sequence Number 4 Mask */ +#define AFEC_SEQ1R_USCH4(value) (AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)) +#define AFEC_SEQ1R_USCH5_Pos _U_(20) /**< (AFEC_SEQ1R) User Sequence Number 5 Position */ +#define AFEC_SEQ1R_USCH5_Msk (_U_(0xF) << AFEC_SEQ1R_USCH5_Pos) /**< (AFEC_SEQ1R) User Sequence Number 5 Mask */ +#define AFEC_SEQ1R_USCH5(value) (AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)) +#define AFEC_SEQ1R_USCH6_Pos _U_(24) /**< (AFEC_SEQ1R) User Sequence Number 6 Position */ +#define AFEC_SEQ1R_USCH6_Msk (_U_(0xF) << AFEC_SEQ1R_USCH6_Pos) /**< (AFEC_SEQ1R) User Sequence Number 6 Mask */ +#define AFEC_SEQ1R_USCH6(value) (AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)) +#define AFEC_SEQ1R_USCH7_Pos _U_(28) /**< (AFEC_SEQ1R) User Sequence Number 7 Position */ +#define AFEC_SEQ1R_USCH7_Msk (_U_(0xF) << AFEC_SEQ1R_USCH7_Pos) /**< (AFEC_SEQ1R) User Sequence Number 7 Mask */ +#define AFEC_SEQ1R_USCH7(value) (AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)) +#define AFEC_SEQ1R_Msk _U_(0xFFFFFFFF) /**< (AFEC_SEQ1R) Register Mask */ + + +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) (R/W 32) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos _U_(0) /**< (AFEC_SEQ2R) User Sequence Number 8 Position */ +#define AFEC_SEQ2R_USCH8_Msk (_U_(0xF) << AFEC_SEQ2R_USCH8_Pos) /**< (AFEC_SEQ2R) User Sequence Number 8 Mask */ +#define AFEC_SEQ2R_USCH8(value) (AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)) +#define AFEC_SEQ2R_USCH9_Pos _U_(4) /**< (AFEC_SEQ2R) User Sequence Number 9 Position */ +#define AFEC_SEQ2R_USCH9_Msk (_U_(0xF) << AFEC_SEQ2R_USCH9_Pos) /**< (AFEC_SEQ2R) User Sequence Number 9 Mask */ +#define AFEC_SEQ2R_USCH9(value) (AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)) +#define AFEC_SEQ2R_USCH10_Pos _U_(8) /**< (AFEC_SEQ2R) User Sequence Number 10 Position */ +#define AFEC_SEQ2R_USCH10_Msk (_U_(0xF) << AFEC_SEQ2R_USCH10_Pos) /**< (AFEC_SEQ2R) User Sequence Number 10 Mask */ +#define AFEC_SEQ2R_USCH10(value) (AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)) +#define AFEC_SEQ2R_USCH11_Pos _U_(12) /**< (AFEC_SEQ2R) User Sequence Number 11 Position */ +#define AFEC_SEQ2R_USCH11_Msk (_U_(0xF) << AFEC_SEQ2R_USCH11_Pos) /**< (AFEC_SEQ2R) User Sequence Number 11 Mask */ +#define AFEC_SEQ2R_USCH11(value) (AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)) +#define AFEC_SEQ2R_Msk _U_(0x0000FFFF) /**< (AFEC_SEQ2R) Register Mask */ + + +/* -------- AFEC_CHER : (AFEC Offset: 0x14) ( /W 32) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0_Pos _U_(0) /**< (AFEC_CHER) Channel 0 Enable Position */ +#define AFEC_CHER_CH0_Msk (_U_(0x1) << AFEC_CHER_CH0_Pos) /**< (AFEC_CHER) Channel 0 Enable Mask */ +#define AFEC_CHER_CH0(value) (AFEC_CHER_CH0_Msk & ((value) << AFEC_CHER_CH0_Pos)) +#define AFEC_CHER_CH1_Pos _U_(1) /**< (AFEC_CHER) Channel 1 Enable Position */ +#define AFEC_CHER_CH1_Msk (_U_(0x1) << AFEC_CHER_CH1_Pos) /**< (AFEC_CHER) Channel 1 Enable Mask */ +#define AFEC_CHER_CH1(value) (AFEC_CHER_CH1_Msk & ((value) << AFEC_CHER_CH1_Pos)) +#define AFEC_CHER_CH2_Pos _U_(2) /**< (AFEC_CHER) Channel 2 Enable Position */ +#define AFEC_CHER_CH2_Msk (_U_(0x1) << AFEC_CHER_CH2_Pos) /**< (AFEC_CHER) Channel 2 Enable Mask */ +#define AFEC_CHER_CH2(value) (AFEC_CHER_CH2_Msk & ((value) << AFEC_CHER_CH2_Pos)) +#define AFEC_CHER_CH3_Pos _U_(3) /**< (AFEC_CHER) Channel 3 Enable Position */ +#define AFEC_CHER_CH3_Msk (_U_(0x1) << AFEC_CHER_CH3_Pos) /**< (AFEC_CHER) Channel 3 Enable Mask */ +#define AFEC_CHER_CH3(value) (AFEC_CHER_CH3_Msk & ((value) << AFEC_CHER_CH3_Pos)) +#define AFEC_CHER_CH4_Pos _U_(4) /**< (AFEC_CHER) Channel 4 Enable Position */ +#define AFEC_CHER_CH4_Msk (_U_(0x1) << AFEC_CHER_CH4_Pos) /**< (AFEC_CHER) Channel 4 Enable Mask */ +#define AFEC_CHER_CH4(value) (AFEC_CHER_CH4_Msk & ((value) << AFEC_CHER_CH4_Pos)) +#define AFEC_CHER_CH5_Pos _U_(5) /**< (AFEC_CHER) Channel 5 Enable Position */ +#define AFEC_CHER_CH5_Msk (_U_(0x1) << AFEC_CHER_CH5_Pos) /**< (AFEC_CHER) Channel 5 Enable Mask */ +#define AFEC_CHER_CH5(value) (AFEC_CHER_CH5_Msk & ((value) << AFEC_CHER_CH5_Pos)) +#define AFEC_CHER_CH6_Pos _U_(6) /**< (AFEC_CHER) Channel 6 Enable Position */ +#define AFEC_CHER_CH6_Msk (_U_(0x1) << AFEC_CHER_CH6_Pos) /**< (AFEC_CHER) Channel 6 Enable Mask */ +#define AFEC_CHER_CH6(value) (AFEC_CHER_CH6_Msk & ((value) << AFEC_CHER_CH6_Pos)) +#define AFEC_CHER_CH7_Pos _U_(7) /**< (AFEC_CHER) Channel 7 Enable Position */ +#define AFEC_CHER_CH7_Msk (_U_(0x1) << AFEC_CHER_CH7_Pos) /**< (AFEC_CHER) Channel 7 Enable Mask */ +#define AFEC_CHER_CH7(value) (AFEC_CHER_CH7_Msk & ((value) << AFEC_CHER_CH7_Pos)) +#define AFEC_CHER_CH8_Pos _U_(8) /**< (AFEC_CHER) Channel 8 Enable Position */ +#define AFEC_CHER_CH8_Msk (_U_(0x1) << AFEC_CHER_CH8_Pos) /**< (AFEC_CHER) Channel 8 Enable Mask */ +#define AFEC_CHER_CH8(value) (AFEC_CHER_CH8_Msk & ((value) << AFEC_CHER_CH8_Pos)) +#define AFEC_CHER_CH9_Pos _U_(9) /**< (AFEC_CHER) Channel 9 Enable Position */ +#define AFEC_CHER_CH9_Msk (_U_(0x1) << AFEC_CHER_CH9_Pos) /**< (AFEC_CHER) Channel 9 Enable Mask */ +#define AFEC_CHER_CH9(value) (AFEC_CHER_CH9_Msk & ((value) << AFEC_CHER_CH9_Pos)) +#define AFEC_CHER_CH10_Pos _U_(10) /**< (AFEC_CHER) Channel 10 Enable Position */ +#define AFEC_CHER_CH10_Msk (_U_(0x1) << AFEC_CHER_CH10_Pos) /**< (AFEC_CHER) Channel 10 Enable Mask */ +#define AFEC_CHER_CH10(value) (AFEC_CHER_CH10_Msk & ((value) << AFEC_CHER_CH10_Pos)) +#define AFEC_CHER_CH11_Pos _U_(11) /**< (AFEC_CHER) Channel 11 Enable Position */ +#define AFEC_CHER_CH11_Msk (_U_(0x1) << AFEC_CHER_CH11_Pos) /**< (AFEC_CHER) Channel 11 Enable Mask */ +#define AFEC_CHER_CH11(value) (AFEC_CHER_CH11_Msk & ((value) << AFEC_CHER_CH11_Pos)) +#define AFEC_CHER_Msk _U_(0x00000FFF) /**< (AFEC_CHER) Register Mask */ + +#define AFEC_CHER_CH_Pos _U_(0) /**< (AFEC_CHER Position) Channel xx Enable */ +#define AFEC_CHER_CH_Msk (_U_(0xFFF) << AFEC_CHER_CH_Pos) /**< (AFEC_CHER Mask) CH */ +#define AFEC_CHER_CH(value) (AFEC_CHER_CH_Msk & ((value) << AFEC_CHER_CH_Pos)) + +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) ( /W 32) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0_Pos _U_(0) /**< (AFEC_CHDR) Channel 0 Disable Position */ +#define AFEC_CHDR_CH0_Msk (_U_(0x1) << AFEC_CHDR_CH0_Pos) /**< (AFEC_CHDR) Channel 0 Disable Mask */ +#define AFEC_CHDR_CH0(value) (AFEC_CHDR_CH0_Msk & ((value) << AFEC_CHDR_CH0_Pos)) +#define AFEC_CHDR_CH1_Pos _U_(1) /**< (AFEC_CHDR) Channel 1 Disable Position */ +#define AFEC_CHDR_CH1_Msk (_U_(0x1) << AFEC_CHDR_CH1_Pos) /**< (AFEC_CHDR) Channel 1 Disable Mask */ +#define AFEC_CHDR_CH1(value) (AFEC_CHDR_CH1_Msk & ((value) << AFEC_CHDR_CH1_Pos)) +#define AFEC_CHDR_CH2_Pos _U_(2) /**< (AFEC_CHDR) Channel 2 Disable Position */ +#define AFEC_CHDR_CH2_Msk (_U_(0x1) << AFEC_CHDR_CH2_Pos) /**< (AFEC_CHDR) Channel 2 Disable Mask */ +#define AFEC_CHDR_CH2(value) (AFEC_CHDR_CH2_Msk & ((value) << AFEC_CHDR_CH2_Pos)) +#define AFEC_CHDR_CH3_Pos _U_(3) /**< (AFEC_CHDR) Channel 3 Disable Position */ +#define AFEC_CHDR_CH3_Msk (_U_(0x1) << AFEC_CHDR_CH3_Pos) /**< (AFEC_CHDR) Channel 3 Disable Mask */ +#define AFEC_CHDR_CH3(value) (AFEC_CHDR_CH3_Msk & ((value) << AFEC_CHDR_CH3_Pos)) +#define AFEC_CHDR_CH4_Pos _U_(4) /**< (AFEC_CHDR) Channel 4 Disable Position */ +#define AFEC_CHDR_CH4_Msk (_U_(0x1) << AFEC_CHDR_CH4_Pos) /**< (AFEC_CHDR) Channel 4 Disable Mask */ +#define AFEC_CHDR_CH4(value) (AFEC_CHDR_CH4_Msk & ((value) << AFEC_CHDR_CH4_Pos)) +#define AFEC_CHDR_CH5_Pos _U_(5) /**< (AFEC_CHDR) Channel 5 Disable Position */ +#define AFEC_CHDR_CH5_Msk (_U_(0x1) << AFEC_CHDR_CH5_Pos) /**< (AFEC_CHDR) Channel 5 Disable Mask */ +#define AFEC_CHDR_CH5(value) (AFEC_CHDR_CH5_Msk & ((value) << AFEC_CHDR_CH5_Pos)) +#define AFEC_CHDR_CH6_Pos _U_(6) /**< (AFEC_CHDR) Channel 6 Disable Position */ +#define AFEC_CHDR_CH6_Msk (_U_(0x1) << AFEC_CHDR_CH6_Pos) /**< (AFEC_CHDR) Channel 6 Disable Mask */ +#define AFEC_CHDR_CH6(value) (AFEC_CHDR_CH6_Msk & ((value) << AFEC_CHDR_CH6_Pos)) +#define AFEC_CHDR_CH7_Pos _U_(7) /**< (AFEC_CHDR) Channel 7 Disable Position */ +#define AFEC_CHDR_CH7_Msk (_U_(0x1) << AFEC_CHDR_CH7_Pos) /**< (AFEC_CHDR) Channel 7 Disable Mask */ +#define AFEC_CHDR_CH7(value) (AFEC_CHDR_CH7_Msk & ((value) << AFEC_CHDR_CH7_Pos)) +#define AFEC_CHDR_CH8_Pos _U_(8) /**< (AFEC_CHDR) Channel 8 Disable Position */ +#define AFEC_CHDR_CH8_Msk (_U_(0x1) << AFEC_CHDR_CH8_Pos) /**< (AFEC_CHDR) Channel 8 Disable Mask */ +#define AFEC_CHDR_CH8(value) (AFEC_CHDR_CH8_Msk & ((value) << AFEC_CHDR_CH8_Pos)) +#define AFEC_CHDR_CH9_Pos _U_(9) /**< (AFEC_CHDR) Channel 9 Disable Position */ +#define AFEC_CHDR_CH9_Msk (_U_(0x1) << AFEC_CHDR_CH9_Pos) /**< (AFEC_CHDR) Channel 9 Disable Mask */ +#define AFEC_CHDR_CH9(value) (AFEC_CHDR_CH9_Msk & ((value) << AFEC_CHDR_CH9_Pos)) +#define AFEC_CHDR_CH10_Pos _U_(10) /**< (AFEC_CHDR) Channel 10 Disable Position */ +#define AFEC_CHDR_CH10_Msk (_U_(0x1) << AFEC_CHDR_CH10_Pos) /**< (AFEC_CHDR) Channel 10 Disable Mask */ +#define AFEC_CHDR_CH10(value) (AFEC_CHDR_CH10_Msk & ((value) << AFEC_CHDR_CH10_Pos)) +#define AFEC_CHDR_CH11_Pos _U_(11) /**< (AFEC_CHDR) Channel 11 Disable Position */ +#define AFEC_CHDR_CH11_Msk (_U_(0x1) << AFEC_CHDR_CH11_Pos) /**< (AFEC_CHDR) Channel 11 Disable Mask */ +#define AFEC_CHDR_CH11(value) (AFEC_CHDR_CH11_Msk & ((value) << AFEC_CHDR_CH11_Pos)) +#define AFEC_CHDR_Msk _U_(0x00000FFF) /**< (AFEC_CHDR) Register Mask */ + +#define AFEC_CHDR_CH_Pos _U_(0) /**< (AFEC_CHDR Position) Channel xx Disable */ +#define AFEC_CHDR_CH_Msk (_U_(0xFFF) << AFEC_CHDR_CH_Pos) /**< (AFEC_CHDR Mask) CH */ +#define AFEC_CHDR_CH(value) (AFEC_CHDR_CH_Msk & ((value) << AFEC_CHDR_CH_Pos)) + +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) ( R/ 32) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0_Pos _U_(0) /**< (AFEC_CHSR) Channel 0 Status Position */ +#define AFEC_CHSR_CH0_Msk (_U_(0x1) << AFEC_CHSR_CH0_Pos) /**< (AFEC_CHSR) Channel 0 Status Mask */ +#define AFEC_CHSR_CH0(value) (AFEC_CHSR_CH0_Msk & ((value) << AFEC_CHSR_CH0_Pos)) +#define AFEC_CHSR_CH1_Pos _U_(1) /**< (AFEC_CHSR) Channel 1 Status Position */ +#define AFEC_CHSR_CH1_Msk (_U_(0x1) << AFEC_CHSR_CH1_Pos) /**< (AFEC_CHSR) Channel 1 Status Mask */ +#define AFEC_CHSR_CH1(value) (AFEC_CHSR_CH1_Msk & ((value) << AFEC_CHSR_CH1_Pos)) +#define AFEC_CHSR_CH2_Pos _U_(2) /**< (AFEC_CHSR) Channel 2 Status Position */ +#define AFEC_CHSR_CH2_Msk (_U_(0x1) << AFEC_CHSR_CH2_Pos) /**< (AFEC_CHSR) Channel 2 Status Mask */ +#define AFEC_CHSR_CH2(value) (AFEC_CHSR_CH2_Msk & ((value) << AFEC_CHSR_CH2_Pos)) +#define AFEC_CHSR_CH3_Pos _U_(3) /**< (AFEC_CHSR) Channel 3 Status Position */ +#define AFEC_CHSR_CH3_Msk (_U_(0x1) << AFEC_CHSR_CH3_Pos) /**< (AFEC_CHSR) Channel 3 Status Mask */ +#define AFEC_CHSR_CH3(value) (AFEC_CHSR_CH3_Msk & ((value) << AFEC_CHSR_CH3_Pos)) +#define AFEC_CHSR_CH4_Pos _U_(4) /**< (AFEC_CHSR) Channel 4 Status Position */ +#define AFEC_CHSR_CH4_Msk (_U_(0x1) << AFEC_CHSR_CH4_Pos) /**< (AFEC_CHSR) Channel 4 Status Mask */ +#define AFEC_CHSR_CH4(value) (AFEC_CHSR_CH4_Msk & ((value) << AFEC_CHSR_CH4_Pos)) +#define AFEC_CHSR_CH5_Pos _U_(5) /**< (AFEC_CHSR) Channel 5 Status Position */ +#define AFEC_CHSR_CH5_Msk (_U_(0x1) << AFEC_CHSR_CH5_Pos) /**< (AFEC_CHSR) Channel 5 Status Mask */ +#define AFEC_CHSR_CH5(value) (AFEC_CHSR_CH5_Msk & ((value) << AFEC_CHSR_CH5_Pos)) +#define AFEC_CHSR_CH6_Pos _U_(6) /**< (AFEC_CHSR) Channel 6 Status Position */ +#define AFEC_CHSR_CH6_Msk (_U_(0x1) << AFEC_CHSR_CH6_Pos) /**< (AFEC_CHSR) Channel 6 Status Mask */ +#define AFEC_CHSR_CH6(value) (AFEC_CHSR_CH6_Msk & ((value) << AFEC_CHSR_CH6_Pos)) +#define AFEC_CHSR_CH7_Pos _U_(7) /**< (AFEC_CHSR) Channel 7 Status Position */ +#define AFEC_CHSR_CH7_Msk (_U_(0x1) << AFEC_CHSR_CH7_Pos) /**< (AFEC_CHSR) Channel 7 Status Mask */ +#define AFEC_CHSR_CH7(value) (AFEC_CHSR_CH7_Msk & ((value) << AFEC_CHSR_CH7_Pos)) +#define AFEC_CHSR_CH8_Pos _U_(8) /**< (AFEC_CHSR) Channel 8 Status Position */ +#define AFEC_CHSR_CH8_Msk (_U_(0x1) << AFEC_CHSR_CH8_Pos) /**< (AFEC_CHSR) Channel 8 Status Mask */ +#define AFEC_CHSR_CH8(value) (AFEC_CHSR_CH8_Msk & ((value) << AFEC_CHSR_CH8_Pos)) +#define AFEC_CHSR_CH9_Pos _U_(9) /**< (AFEC_CHSR) Channel 9 Status Position */ +#define AFEC_CHSR_CH9_Msk (_U_(0x1) << AFEC_CHSR_CH9_Pos) /**< (AFEC_CHSR) Channel 9 Status Mask */ +#define AFEC_CHSR_CH9(value) (AFEC_CHSR_CH9_Msk & ((value) << AFEC_CHSR_CH9_Pos)) +#define AFEC_CHSR_CH10_Pos _U_(10) /**< (AFEC_CHSR) Channel 10 Status Position */ +#define AFEC_CHSR_CH10_Msk (_U_(0x1) << AFEC_CHSR_CH10_Pos) /**< (AFEC_CHSR) Channel 10 Status Mask */ +#define AFEC_CHSR_CH10(value) (AFEC_CHSR_CH10_Msk & ((value) << AFEC_CHSR_CH10_Pos)) +#define AFEC_CHSR_CH11_Pos _U_(11) /**< (AFEC_CHSR) Channel 11 Status Position */ +#define AFEC_CHSR_CH11_Msk (_U_(0x1) << AFEC_CHSR_CH11_Pos) /**< (AFEC_CHSR) Channel 11 Status Mask */ +#define AFEC_CHSR_CH11(value) (AFEC_CHSR_CH11_Msk & ((value) << AFEC_CHSR_CH11_Pos)) +#define AFEC_CHSR_Msk _U_(0x00000FFF) /**< (AFEC_CHSR) Register Mask */ + +#define AFEC_CHSR_CH_Pos _U_(0) /**< (AFEC_CHSR Position) Channel xx Status */ +#define AFEC_CHSR_CH_Msk (_U_(0xFFF) << AFEC_CHSR_CH_Pos) /**< (AFEC_CHSR Mask) CH */ +#define AFEC_CHSR_CH(value) (AFEC_CHSR_CH_Msk & ((value) << AFEC_CHSR_CH_Pos)) + +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) ( R/ 32) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos _U_(0) /**< (AFEC_LCDR) Last Data Converted Position */ +#define AFEC_LCDR_LDATA_Msk (_U_(0xFFFF) << AFEC_LCDR_LDATA_Pos) /**< (AFEC_LCDR) Last Data Converted Mask */ +#define AFEC_LCDR_LDATA(value) (AFEC_LCDR_LDATA_Msk & ((value) << AFEC_LCDR_LDATA_Pos)) +#define AFEC_LCDR_CHNB_Pos _U_(24) /**< (AFEC_LCDR) Channel Number Position */ +#define AFEC_LCDR_CHNB_Msk (_U_(0xF) << AFEC_LCDR_CHNB_Pos) /**< (AFEC_LCDR) Channel Number Mask */ +#define AFEC_LCDR_CHNB(value) (AFEC_LCDR_CHNB_Msk & ((value) << AFEC_LCDR_CHNB_Pos)) +#define AFEC_LCDR_Msk _U_(0x0F00FFFF) /**< (AFEC_LCDR) Register Mask */ + + +/* -------- AFEC_IER : (AFEC Offset: 0x24) ( /W 32) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0_Pos _U_(0) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Position */ +#define AFEC_IER_EOC0_Msk (_U_(0x1) << AFEC_IER_EOC0_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Mask */ +#define AFEC_IER_EOC0(value) (AFEC_IER_EOC0_Msk & ((value) << AFEC_IER_EOC0_Pos)) +#define AFEC_IER_EOC1_Pos _U_(1) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Position */ +#define AFEC_IER_EOC1_Msk (_U_(0x1) << AFEC_IER_EOC1_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Mask */ +#define AFEC_IER_EOC1(value) (AFEC_IER_EOC1_Msk & ((value) << AFEC_IER_EOC1_Pos)) +#define AFEC_IER_EOC2_Pos _U_(2) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Position */ +#define AFEC_IER_EOC2_Msk (_U_(0x1) << AFEC_IER_EOC2_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Mask */ +#define AFEC_IER_EOC2(value) (AFEC_IER_EOC2_Msk & ((value) << AFEC_IER_EOC2_Pos)) +#define AFEC_IER_EOC3_Pos _U_(3) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Position */ +#define AFEC_IER_EOC3_Msk (_U_(0x1) << AFEC_IER_EOC3_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Mask */ +#define AFEC_IER_EOC3(value) (AFEC_IER_EOC3_Msk & ((value) << AFEC_IER_EOC3_Pos)) +#define AFEC_IER_EOC4_Pos _U_(4) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Position */ +#define AFEC_IER_EOC4_Msk (_U_(0x1) << AFEC_IER_EOC4_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Mask */ +#define AFEC_IER_EOC4(value) (AFEC_IER_EOC4_Msk & ((value) << AFEC_IER_EOC4_Pos)) +#define AFEC_IER_EOC5_Pos _U_(5) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Position */ +#define AFEC_IER_EOC5_Msk (_U_(0x1) << AFEC_IER_EOC5_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Mask */ +#define AFEC_IER_EOC5(value) (AFEC_IER_EOC5_Msk & ((value) << AFEC_IER_EOC5_Pos)) +#define AFEC_IER_EOC6_Pos _U_(6) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Position */ +#define AFEC_IER_EOC6_Msk (_U_(0x1) << AFEC_IER_EOC6_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Mask */ +#define AFEC_IER_EOC6(value) (AFEC_IER_EOC6_Msk & ((value) << AFEC_IER_EOC6_Pos)) +#define AFEC_IER_EOC7_Pos _U_(7) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Position */ +#define AFEC_IER_EOC7_Msk (_U_(0x1) << AFEC_IER_EOC7_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Mask */ +#define AFEC_IER_EOC7(value) (AFEC_IER_EOC7_Msk & ((value) << AFEC_IER_EOC7_Pos)) +#define AFEC_IER_EOC8_Pos _U_(8) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Position */ +#define AFEC_IER_EOC8_Msk (_U_(0x1) << AFEC_IER_EOC8_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Mask */ +#define AFEC_IER_EOC8(value) (AFEC_IER_EOC8_Msk & ((value) << AFEC_IER_EOC8_Pos)) +#define AFEC_IER_EOC9_Pos _U_(9) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Position */ +#define AFEC_IER_EOC9_Msk (_U_(0x1) << AFEC_IER_EOC9_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Mask */ +#define AFEC_IER_EOC9(value) (AFEC_IER_EOC9_Msk & ((value) << AFEC_IER_EOC9_Pos)) +#define AFEC_IER_EOC10_Pos _U_(10) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Position */ +#define AFEC_IER_EOC10_Msk (_U_(0x1) << AFEC_IER_EOC10_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Mask */ +#define AFEC_IER_EOC10(value) (AFEC_IER_EOC10_Msk & ((value) << AFEC_IER_EOC10_Pos)) +#define AFEC_IER_EOC11_Pos _U_(11) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Position */ +#define AFEC_IER_EOC11_Msk (_U_(0x1) << AFEC_IER_EOC11_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Mask */ +#define AFEC_IER_EOC11(value) (AFEC_IER_EOC11_Msk & ((value) << AFEC_IER_EOC11_Pos)) +#define AFEC_IER_DRDY_Pos _U_(24) /**< (AFEC_IER) Data Ready Interrupt Enable Position */ +#define AFEC_IER_DRDY_Msk (_U_(0x1) << AFEC_IER_DRDY_Pos) /**< (AFEC_IER) Data Ready Interrupt Enable Mask */ +#define AFEC_IER_DRDY(value) (AFEC_IER_DRDY_Msk & ((value) << AFEC_IER_DRDY_Pos)) +#define AFEC_IER_GOVRE_Pos _U_(25) /**< (AFEC_IER) General Overrun Error Interrupt Enable Position */ +#define AFEC_IER_GOVRE_Msk (_U_(0x1) << AFEC_IER_GOVRE_Pos) /**< (AFEC_IER) General Overrun Error Interrupt Enable Mask */ +#define AFEC_IER_GOVRE(value) (AFEC_IER_GOVRE_Msk & ((value) << AFEC_IER_GOVRE_Pos)) +#define AFEC_IER_COMPE_Pos _U_(26) /**< (AFEC_IER) Comparison Event Interrupt Enable Position */ +#define AFEC_IER_COMPE_Msk (_U_(0x1) << AFEC_IER_COMPE_Pos) /**< (AFEC_IER) Comparison Event Interrupt Enable Mask */ +#define AFEC_IER_COMPE(value) (AFEC_IER_COMPE_Msk & ((value) << AFEC_IER_COMPE_Pos)) +#define AFEC_IER_TEMPCHG_Pos _U_(30) /**< (AFEC_IER) Temperature Change Interrupt Enable Position */ +#define AFEC_IER_TEMPCHG_Msk (_U_(0x1) << AFEC_IER_TEMPCHG_Pos) /**< (AFEC_IER) Temperature Change Interrupt Enable Mask */ +#define AFEC_IER_TEMPCHG(value) (AFEC_IER_TEMPCHG_Msk & ((value) << AFEC_IER_TEMPCHG_Pos)) +#define AFEC_IER_Msk _U_(0x47000FFF) /**< (AFEC_IER) Register Mask */ + +#define AFEC_IER_EOC_Pos _U_(0) /**< (AFEC_IER Position) End of Conversion Interrupt Enable x */ +#define AFEC_IER_EOC_Msk (_U_(0xFFF) << AFEC_IER_EOC_Pos) /**< (AFEC_IER Mask) EOC */ +#define AFEC_IER_EOC(value) (AFEC_IER_EOC_Msk & ((value) << AFEC_IER_EOC_Pos)) + +/* -------- AFEC_IDR : (AFEC Offset: 0x28) ( /W 32) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0_Pos _U_(0) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Position */ +#define AFEC_IDR_EOC0_Msk (_U_(0x1) << AFEC_IDR_EOC0_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Mask */ +#define AFEC_IDR_EOC0(value) (AFEC_IDR_EOC0_Msk & ((value) << AFEC_IDR_EOC0_Pos)) +#define AFEC_IDR_EOC1_Pos _U_(1) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Position */ +#define AFEC_IDR_EOC1_Msk (_U_(0x1) << AFEC_IDR_EOC1_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Mask */ +#define AFEC_IDR_EOC1(value) (AFEC_IDR_EOC1_Msk & ((value) << AFEC_IDR_EOC1_Pos)) +#define AFEC_IDR_EOC2_Pos _U_(2) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Position */ +#define AFEC_IDR_EOC2_Msk (_U_(0x1) << AFEC_IDR_EOC2_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Mask */ +#define AFEC_IDR_EOC2(value) (AFEC_IDR_EOC2_Msk & ((value) << AFEC_IDR_EOC2_Pos)) +#define AFEC_IDR_EOC3_Pos _U_(3) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Position */ +#define AFEC_IDR_EOC3_Msk (_U_(0x1) << AFEC_IDR_EOC3_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Mask */ +#define AFEC_IDR_EOC3(value) (AFEC_IDR_EOC3_Msk & ((value) << AFEC_IDR_EOC3_Pos)) +#define AFEC_IDR_EOC4_Pos _U_(4) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Position */ +#define AFEC_IDR_EOC4_Msk (_U_(0x1) << AFEC_IDR_EOC4_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Mask */ +#define AFEC_IDR_EOC4(value) (AFEC_IDR_EOC4_Msk & ((value) << AFEC_IDR_EOC4_Pos)) +#define AFEC_IDR_EOC5_Pos _U_(5) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Position */ +#define AFEC_IDR_EOC5_Msk (_U_(0x1) << AFEC_IDR_EOC5_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Mask */ +#define AFEC_IDR_EOC5(value) (AFEC_IDR_EOC5_Msk & ((value) << AFEC_IDR_EOC5_Pos)) +#define AFEC_IDR_EOC6_Pos _U_(6) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Position */ +#define AFEC_IDR_EOC6_Msk (_U_(0x1) << AFEC_IDR_EOC6_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Mask */ +#define AFEC_IDR_EOC6(value) (AFEC_IDR_EOC6_Msk & ((value) << AFEC_IDR_EOC6_Pos)) +#define AFEC_IDR_EOC7_Pos _U_(7) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Position */ +#define AFEC_IDR_EOC7_Msk (_U_(0x1) << AFEC_IDR_EOC7_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Mask */ +#define AFEC_IDR_EOC7(value) (AFEC_IDR_EOC7_Msk & ((value) << AFEC_IDR_EOC7_Pos)) +#define AFEC_IDR_EOC8_Pos _U_(8) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Position */ +#define AFEC_IDR_EOC8_Msk (_U_(0x1) << AFEC_IDR_EOC8_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Mask */ +#define AFEC_IDR_EOC8(value) (AFEC_IDR_EOC8_Msk & ((value) << AFEC_IDR_EOC8_Pos)) +#define AFEC_IDR_EOC9_Pos _U_(9) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Position */ +#define AFEC_IDR_EOC9_Msk (_U_(0x1) << AFEC_IDR_EOC9_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Mask */ +#define AFEC_IDR_EOC9(value) (AFEC_IDR_EOC9_Msk & ((value) << AFEC_IDR_EOC9_Pos)) +#define AFEC_IDR_EOC10_Pos _U_(10) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Position */ +#define AFEC_IDR_EOC10_Msk (_U_(0x1) << AFEC_IDR_EOC10_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Mask */ +#define AFEC_IDR_EOC10(value) (AFEC_IDR_EOC10_Msk & ((value) << AFEC_IDR_EOC10_Pos)) +#define AFEC_IDR_EOC11_Pos _U_(11) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Position */ +#define AFEC_IDR_EOC11_Msk (_U_(0x1) << AFEC_IDR_EOC11_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Mask */ +#define AFEC_IDR_EOC11(value) (AFEC_IDR_EOC11_Msk & ((value) << AFEC_IDR_EOC11_Pos)) +#define AFEC_IDR_DRDY_Pos _U_(24) /**< (AFEC_IDR) Data Ready Interrupt Disable Position */ +#define AFEC_IDR_DRDY_Msk (_U_(0x1) << AFEC_IDR_DRDY_Pos) /**< (AFEC_IDR) Data Ready Interrupt Disable Mask */ +#define AFEC_IDR_DRDY(value) (AFEC_IDR_DRDY_Msk & ((value) << AFEC_IDR_DRDY_Pos)) +#define AFEC_IDR_GOVRE_Pos _U_(25) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Position */ +#define AFEC_IDR_GOVRE_Msk (_U_(0x1) << AFEC_IDR_GOVRE_Pos) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Mask */ +#define AFEC_IDR_GOVRE(value) (AFEC_IDR_GOVRE_Msk & ((value) << AFEC_IDR_GOVRE_Pos)) +#define AFEC_IDR_COMPE_Pos _U_(26) /**< (AFEC_IDR) Comparison Event Interrupt Disable Position */ +#define AFEC_IDR_COMPE_Msk (_U_(0x1) << AFEC_IDR_COMPE_Pos) /**< (AFEC_IDR) Comparison Event Interrupt Disable Mask */ +#define AFEC_IDR_COMPE(value) (AFEC_IDR_COMPE_Msk & ((value) << AFEC_IDR_COMPE_Pos)) +#define AFEC_IDR_TEMPCHG_Pos _U_(30) /**< (AFEC_IDR) Temperature Change Interrupt Disable Position */ +#define AFEC_IDR_TEMPCHG_Msk (_U_(0x1) << AFEC_IDR_TEMPCHG_Pos) /**< (AFEC_IDR) Temperature Change Interrupt Disable Mask */ +#define AFEC_IDR_TEMPCHG(value) (AFEC_IDR_TEMPCHG_Msk & ((value) << AFEC_IDR_TEMPCHG_Pos)) +#define AFEC_IDR_Msk _U_(0x47000FFF) /**< (AFEC_IDR) Register Mask */ + +#define AFEC_IDR_EOC_Pos _U_(0) /**< (AFEC_IDR Position) End of Conversion Interrupt Disable x */ +#define AFEC_IDR_EOC_Msk (_U_(0xFFF) << AFEC_IDR_EOC_Pos) /**< (AFEC_IDR Mask) EOC */ +#define AFEC_IDR_EOC(value) (AFEC_IDR_EOC_Msk & ((value) << AFEC_IDR_EOC_Pos)) + +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) ( R/ 32) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0_Pos _U_(0) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Position */ +#define AFEC_IMR_EOC0_Msk (_U_(0x1) << AFEC_IMR_EOC0_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Mask */ +#define AFEC_IMR_EOC0(value) (AFEC_IMR_EOC0_Msk & ((value) << AFEC_IMR_EOC0_Pos)) +#define AFEC_IMR_EOC1_Pos _U_(1) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Position */ +#define AFEC_IMR_EOC1_Msk (_U_(0x1) << AFEC_IMR_EOC1_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Mask */ +#define AFEC_IMR_EOC1(value) (AFEC_IMR_EOC1_Msk & ((value) << AFEC_IMR_EOC1_Pos)) +#define AFEC_IMR_EOC2_Pos _U_(2) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Position */ +#define AFEC_IMR_EOC2_Msk (_U_(0x1) << AFEC_IMR_EOC2_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Mask */ +#define AFEC_IMR_EOC2(value) (AFEC_IMR_EOC2_Msk & ((value) << AFEC_IMR_EOC2_Pos)) +#define AFEC_IMR_EOC3_Pos _U_(3) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Position */ +#define AFEC_IMR_EOC3_Msk (_U_(0x1) << AFEC_IMR_EOC3_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Mask */ +#define AFEC_IMR_EOC3(value) (AFEC_IMR_EOC3_Msk & ((value) << AFEC_IMR_EOC3_Pos)) +#define AFEC_IMR_EOC4_Pos _U_(4) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Position */ +#define AFEC_IMR_EOC4_Msk (_U_(0x1) << AFEC_IMR_EOC4_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Mask */ +#define AFEC_IMR_EOC4(value) (AFEC_IMR_EOC4_Msk & ((value) << AFEC_IMR_EOC4_Pos)) +#define AFEC_IMR_EOC5_Pos _U_(5) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Position */ +#define AFEC_IMR_EOC5_Msk (_U_(0x1) << AFEC_IMR_EOC5_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Mask */ +#define AFEC_IMR_EOC5(value) (AFEC_IMR_EOC5_Msk & ((value) << AFEC_IMR_EOC5_Pos)) +#define AFEC_IMR_EOC6_Pos _U_(6) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Position */ +#define AFEC_IMR_EOC6_Msk (_U_(0x1) << AFEC_IMR_EOC6_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Mask */ +#define AFEC_IMR_EOC6(value) (AFEC_IMR_EOC6_Msk & ((value) << AFEC_IMR_EOC6_Pos)) +#define AFEC_IMR_EOC7_Pos _U_(7) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Position */ +#define AFEC_IMR_EOC7_Msk (_U_(0x1) << AFEC_IMR_EOC7_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Mask */ +#define AFEC_IMR_EOC7(value) (AFEC_IMR_EOC7_Msk & ((value) << AFEC_IMR_EOC7_Pos)) +#define AFEC_IMR_EOC8_Pos _U_(8) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Position */ +#define AFEC_IMR_EOC8_Msk (_U_(0x1) << AFEC_IMR_EOC8_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Mask */ +#define AFEC_IMR_EOC8(value) (AFEC_IMR_EOC8_Msk & ((value) << AFEC_IMR_EOC8_Pos)) +#define AFEC_IMR_EOC9_Pos _U_(9) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Position */ +#define AFEC_IMR_EOC9_Msk (_U_(0x1) << AFEC_IMR_EOC9_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Mask */ +#define AFEC_IMR_EOC9(value) (AFEC_IMR_EOC9_Msk & ((value) << AFEC_IMR_EOC9_Pos)) +#define AFEC_IMR_EOC10_Pos _U_(10) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Position */ +#define AFEC_IMR_EOC10_Msk (_U_(0x1) << AFEC_IMR_EOC10_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Mask */ +#define AFEC_IMR_EOC10(value) (AFEC_IMR_EOC10_Msk & ((value) << AFEC_IMR_EOC10_Pos)) +#define AFEC_IMR_EOC11_Pos _U_(11) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Position */ +#define AFEC_IMR_EOC11_Msk (_U_(0x1) << AFEC_IMR_EOC11_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Mask */ +#define AFEC_IMR_EOC11(value) (AFEC_IMR_EOC11_Msk & ((value) << AFEC_IMR_EOC11_Pos)) +#define AFEC_IMR_DRDY_Pos _U_(24) /**< (AFEC_IMR) Data Ready Interrupt Mask Position */ +#define AFEC_IMR_DRDY_Msk (_U_(0x1) << AFEC_IMR_DRDY_Pos) /**< (AFEC_IMR) Data Ready Interrupt Mask Mask */ +#define AFEC_IMR_DRDY(value) (AFEC_IMR_DRDY_Msk & ((value) << AFEC_IMR_DRDY_Pos)) +#define AFEC_IMR_GOVRE_Pos _U_(25) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Position */ +#define AFEC_IMR_GOVRE_Msk (_U_(0x1) << AFEC_IMR_GOVRE_Pos) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Mask */ +#define AFEC_IMR_GOVRE(value) (AFEC_IMR_GOVRE_Msk & ((value) << AFEC_IMR_GOVRE_Pos)) +#define AFEC_IMR_COMPE_Pos _U_(26) /**< (AFEC_IMR) Comparison Event Interrupt Mask Position */ +#define AFEC_IMR_COMPE_Msk (_U_(0x1) << AFEC_IMR_COMPE_Pos) /**< (AFEC_IMR) Comparison Event Interrupt Mask Mask */ +#define AFEC_IMR_COMPE(value) (AFEC_IMR_COMPE_Msk & ((value) << AFEC_IMR_COMPE_Pos)) +#define AFEC_IMR_TEMPCHG_Pos _U_(30) /**< (AFEC_IMR) Temperature Change Interrupt Mask Position */ +#define AFEC_IMR_TEMPCHG_Msk (_U_(0x1) << AFEC_IMR_TEMPCHG_Pos) /**< (AFEC_IMR) Temperature Change Interrupt Mask Mask */ +#define AFEC_IMR_TEMPCHG(value) (AFEC_IMR_TEMPCHG_Msk & ((value) << AFEC_IMR_TEMPCHG_Pos)) +#define AFEC_IMR_Msk _U_(0x47000FFF) /**< (AFEC_IMR) Register Mask */ + +#define AFEC_IMR_EOC_Pos _U_(0) /**< (AFEC_IMR Position) End of Conversion Interrupt Mask x */ +#define AFEC_IMR_EOC_Msk (_U_(0xFFF) << AFEC_IMR_EOC_Pos) /**< (AFEC_IMR Mask) EOC */ +#define AFEC_IMR_EOC(value) (AFEC_IMR_EOC_Msk & ((value) << AFEC_IMR_EOC_Pos)) + +/* -------- AFEC_ISR : (AFEC Offset: 0x30) ( R/ 32) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0_Pos _U_(0) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC0_Msk (_U_(0x1) << AFEC_ISR_EOC0_Pos) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC0(value) (AFEC_ISR_EOC0_Msk & ((value) << AFEC_ISR_EOC0_Pos)) +#define AFEC_ISR_EOC1_Pos _U_(1) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC1_Msk (_U_(0x1) << AFEC_ISR_EOC1_Pos) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC1(value) (AFEC_ISR_EOC1_Msk & ((value) << AFEC_ISR_EOC1_Pos)) +#define AFEC_ISR_EOC2_Pos _U_(2) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC2_Msk (_U_(0x1) << AFEC_ISR_EOC2_Pos) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC2(value) (AFEC_ISR_EOC2_Msk & ((value) << AFEC_ISR_EOC2_Pos)) +#define AFEC_ISR_EOC3_Pos _U_(3) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC3_Msk (_U_(0x1) << AFEC_ISR_EOC3_Pos) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC3(value) (AFEC_ISR_EOC3_Msk & ((value) << AFEC_ISR_EOC3_Pos)) +#define AFEC_ISR_EOC4_Pos _U_(4) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC4_Msk (_U_(0x1) << AFEC_ISR_EOC4_Pos) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC4(value) (AFEC_ISR_EOC4_Msk & ((value) << AFEC_ISR_EOC4_Pos)) +#define AFEC_ISR_EOC5_Pos _U_(5) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC5_Msk (_U_(0x1) << AFEC_ISR_EOC5_Pos) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC5(value) (AFEC_ISR_EOC5_Msk & ((value) << AFEC_ISR_EOC5_Pos)) +#define AFEC_ISR_EOC6_Pos _U_(6) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC6_Msk (_U_(0x1) << AFEC_ISR_EOC6_Pos) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC6(value) (AFEC_ISR_EOC6_Msk & ((value) << AFEC_ISR_EOC6_Pos)) +#define AFEC_ISR_EOC7_Pos _U_(7) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC7_Msk (_U_(0x1) << AFEC_ISR_EOC7_Pos) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC7(value) (AFEC_ISR_EOC7_Msk & ((value) << AFEC_ISR_EOC7_Pos)) +#define AFEC_ISR_EOC8_Pos _U_(8) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC8_Msk (_U_(0x1) << AFEC_ISR_EOC8_Pos) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC8(value) (AFEC_ISR_EOC8_Msk & ((value) << AFEC_ISR_EOC8_Pos)) +#define AFEC_ISR_EOC9_Pos _U_(9) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC9_Msk (_U_(0x1) << AFEC_ISR_EOC9_Pos) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC9(value) (AFEC_ISR_EOC9_Msk & ((value) << AFEC_ISR_EOC9_Pos)) +#define AFEC_ISR_EOC10_Pos _U_(10) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC10_Msk (_U_(0x1) << AFEC_ISR_EOC10_Pos) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC10(value) (AFEC_ISR_EOC10_Msk & ((value) << AFEC_ISR_EOC10_Pos)) +#define AFEC_ISR_EOC11_Pos _U_(11) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC11_Msk (_U_(0x1) << AFEC_ISR_EOC11_Pos) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC11(value) (AFEC_ISR_EOC11_Msk & ((value) << AFEC_ISR_EOC11_Pos)) +#define AFEC_ISR_DRDY_Pos _U_(24) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Position */ +#define AFEC_ISR_DRDY_Msk (_U_(0x1) << AFEC_ISR_DRDY_Pos) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Mask */ +#define AFEC_ISR_DRDY(value) (AFEC_ISR_DRDY_Msk & ((value) << AFEC_ISR_DRDY_Pos)) +#define AFEC_ISR_GOVRE_Pos _U_(25) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_GOVRE_Msk (_U_(0x1) << AFEC_ISR_GOVRE_Pos) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_GOVRE(value) (AFEC_ISR_GOVRE_Msk & ((value) << AFEC_ISR_GOVRE_Pos)) +#define AFEC_ISR_COMPE_Pos _U_(26) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_COMPE_Msk (_U_(0x1) << AFEC_ISR_COMPE_Pos) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_COMPE(value) (AFEC_ISR_COMPE_Msk & ((value) << AFEC_ISR_COMPE_Pos)) +#define AFEC_ISR_TEMPCHG_Pos _U_(30) /**< (AFEC_ISR) Temperature Change (cleared on read) Position */ +#define AFEC_ISR_TEMPCHG_Msk (_U_(0x1) << AFEC_ISR_TEMPCHG_Pos) /**< (AFEC_ISR) Temperature Change (cleared on read) Mask */ +#define AFEC_ISR_TEMPCHG(value) (AFEC_ISR_TEMPCHG_Msk & ((value) << AFEC_ISR_TEMPCHG_Pos)) +#define AFEC_ISR_Msk _U_(0x47000FFF) /**< (AFEC_ISR) Register Mask */ + +#define AFEC_ISR_EOC_Pos _U_(0) /**< (AFEC_ISR Position) End of Conversion x (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC_Msk (_U_(0xFFF) << AFEC_ISR_EOC_Pos) /**< (AFEC_ISR Mask) EOC */ +#define AFEC_ISR_EOC(value) (AFEC_ISR_EOC_Msk & ((value) << AFEC_ISR_EOC_Pos)) + +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) ( R/ 32) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0_Pos _U_(0) /**< (AFEC_OVER) Overrun Error 0 Position */ +#define AFEC_OVER_OVRE0_Msk (_U_(0x1) << AFEC_OVER_OVRE0_Pos) /**< (AFEC_OVER) Overrun Error 0 Mask */ +#define AFEC_OVER_OVRE0(value) (AFEC_OVER_OVRE0_Msk & ((value) << AFEC_OVER_OVRE0_Pos)) +#define AFEC_OVER_OVRE1_Pos _U_(1) /**< (AFEC_OVER) Overrun Error 1 Position */ +#define AFEC_OVER_OVRE1_Msk (_U_(0x1) << AFEC_OVER_OVRE1_Pos) /**< (AFEC_OVER) Overrun Error 1 Mask */ +#define AFEC_OVER_OVRE1(value) (AFEC_OVER_OVRE1_Msk & ((value) << AFEC_OVER_OVRE1_Pos)) +#define AFEC_OVER_OVRE2_Pos _U_(2) /**< (AFEC_OVER) Overrun Error 2 Position */ +#define AFEC_OVER_OVRE2_Msk (_U_(0x1) << AFEC_OVER_OVRE2_Pos) /**< (AFEC_OVER) Overrun Error 2 Mask */ +#define AFEC_OVER_OVRE2(value) (AFEC_OVER_OVRE2_Msk & ((value) << AFEC_OVER_OVRE2_Pos)) +#define AFEC_OVER_OVRE3_Pos _U_(3) /**< (AFEC_OVER) Overrun Error 3 Position */ +#define AFEC_OVER_OVRE3_Msk (_U_(0x1) << AFEC_OVER_OVRE3_Pos) /**< (AFEC_OVER) Overrun Error 3 Mask */ +#define AFEC_OVER_OVRE3(value) (AFEC_OVER_OVRE3_Msk & ((value) << AFEC_OVER_OVRE3_Pos)) +#define AFEC_OVER_OVRE4_Pos _U_(4) /**< (AFEC_OVER) Overrun Error 4 Position */ +#define AFEC_OVER_OVRE4_Msk (_U_(0x1) << AFEC_OVER_OVRE4_Pos) /**< (AFEC_OVER) Overrun Error 4 Mask */ +#define AFEC_OVER_OVRE4(value) (AFEC_OVER_OVRE4_Msk & ((value) << AFEC_OVER_OVRE4_Pos)) +#define AFEC_OVER_OVRE5_Pos _U_(5) /**< (AFEC_OVER) Overrun Error 5 Position */ +#define AFEC_OVER_OVRE5_Msk (_U_(0x1) << AFEC_OVER_OVRE5_Pos) /**< (AFEC_OVER) Overrun Error 5 Mask */ +#define AFEC_OVER_OVRE5(value) (AFEC_OVER_OVRE5_Msk & ((value) << AFEC_OVER_OVRE5_Pos)) +#define AFEC_OVER_OVRE6_Pos _U_(6) /**< (AFEC_OVER) Overrun Error 6 Position */ +#define AFEC_OVER_OVRE6_Msk (_U_(0x1) << AFEC_OVER_OVRE6_Pos) /**< (AFEC_OVER) Overrun Error 6 Mask */ +#define AFEC_OVER_OVRE6(value) (AFEC_OVER_OVRE6_Msk & ((value) << AFEC_OVER_OVRE6_Pos)) +#define AFEC_OVER_OVRE7_Pos _U_(7) /**< (AFEC_OVER) Overrun Error 7 Position */ +#define AFEC_OVER_OVRE7_Msk (_U_(0x1) << AFEC_OVER_OVRE7_Pos) /**< (AFEC_OVER) Overrun Error 7 Mask */ +#define AFEC_OVER_OVRE7(value) (AFEC_OVER_OVRE7_Msk & ((value) << AFEC_OVER_OVRE7_Pos)) +#define AFEC_OVER_OVRE8_Pos _U_(8) /**< (AFEC_OVER) Overrun Error 8 Position */ +#define AFEC_OVER_OVRE8_Msk (_U_(0x1) << AFEC_OVER_OVRE8_Pos) /**< (AFEC_OVER) Overrun Error 8 Mask */ +#define AFEC_OVER_OVRE8(value) (AFEC_OVER_OVRE8_Msk & ((value) << AFEC_OVER_OVRE8_Pos)) +#define AFEC_OVER_OVRE9_Pos _U_(9) /**< (AFEC_OVER) Overrun Error 9 Position */ +#define AFEC_OVER_OVRE9_Msk (_U_(0x1) << AFEC_OVER_OVRE9_Pos) /**< (AFEC_OVER) Overrun Error 9 Mask */ +#define AFEC_OVER_OVRE9(value) (AFEC_OVER_OVRE9_Msk & ((value) << AFEC_OVER_OVRE9_Pos)) +#define AFEC_OVER_OVRE10_Pos _U_(10) /**< (AFEC_OVER) Overrun Error 10 Position */ +#define AFEC_OVER_OVRE10_Msk (_U_(0x1) << AFEC_OVER_OVRE10_Pos) /**< (AFEC_OVER) Overrun Error 10 Mask */ +#define AFEC_OVER_OVRE10(value) (AFEC_OVER_OVRE10_Msk & ((value) << AFEC_OVER_OVRE10_Pos)) +#define AFEC_OVER_OVRE11_Pos _U_(11) /**< (AFEC_OVER) Overrun Error 11 Position */ +#define AFEC_OVER_OVRE11_Msk (_U_(0x1) << AFEC_OVER_OVRE11_Pos) /**< (AFEC_OVER) Overrun Error 11 Mask */ +#define AFEC_OVER_OVRE11(value) (AFEC_OVER_OVRE11_Msk & ((value) << AFEC_OVER_OVRE11_Pos)) +#define AFEC_OVER_Msk _U_(0x00000FFF) /**< (AFEC_OVER) Register Mask */ + +#define AFEC_OVER_OVRE_Pos _U_(0) /**< (AFEC_OVER Position) Overrun Error xx */ +#define AFEC_OVER_OVRE_Msk (_U_(0xFFF) << AFEC_OVER_OVRE_Pos) /**< (AFEC_OVER Mask) OVRE */ +#define AFEC_OVER_OVRE(value) (AFEC_OVER_OVRE_Msk & ((value) << AFEC_OVER_OVRE_Pos)) + +/* -------- AFEC_CWR : (AFEC Offset: 0x50) (R/W 32) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos _U_(0) /**< (AFEC_CWR) Low Threshold Position */ +#define AFEC_CWR_LOWTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_LOWTHRES_Pos) /**< (AFEC_CWR) Low Threshold Mask */ +#define AFEC_CWR_LOWTHRES(value) (AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)) +#define AFEC_CWR_HIGHTHRES_Pos _U_(16) /**< (AFEC_CWR) High Threshold Position */ +#define AFEC_CWR_HIGHTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_HIGHTHRES_Pos) /**< (AFEC_CWR) High Threshold Mask */ +#define AFEC_CWR_HIGHTHRES(value) (AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)) +#define AFEC_CWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CWR) Register Mask */ + + +/* -------- AFEC_CGR : (AFEC Offset: 0x54) (R/W 32) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos _U_(0) /**< (AFEC_CGR) Gain for Channel 0 Position */ +#define AFEC_CGR_GAIN0_Msk (_U_(0x3) << AFEC_CGR_GAIN0_Pos) /**< (AFEC_CGR) Gain for Channel 0 Mask */ +#define AFEC_CGR_GAIN0(value) (AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)) +#define AFEC_CGR_GAIN1_Pos _U_(2) /**< (AFEC_CGR) Gain for Channel 1 Position */ +#define AFEC_CGR_GAIN1_Msk (_U_(0x3) << AFEC_CGR_GAIN1_Pos) /**< (AFEC_CGR) Gain for Channel 1 Mask */ +#define AFEC_CGR_GAIN1(value) (AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)) +#define AFEC_CGR_GAIN2_Pos _U_(4) /**< (AFEC_CGR) Gain for Channel 2 Position */ +#define AFEC_CGR_GAIN2_Msk (_U_(0x3) << AFEC_CGR_GAIN2_Pos) /**< (AFEC_CGR) Gain for Channel 2 Mask */ +#define AFEC_CGR_GAIN2(value) (AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)) +#define AFEC_CGR_GAIN3_Pos _U_(6) /**< (AFEC_CGR) Gain for Channel 3 Position */ +#define AFEC_CGR_GAIN3_Msk (_U_(0x3) << AFEC_CGR_GAIN3_Pos) /**< (AFEC_CGR) Gain for Channel 3 Mask */ +#define AFEC_CGR_GAIN3(value) (AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)) +#define AFEC_CGR_GAIN4_Pos _U_(8) /**< (AFEC_CGR) Gain for Channel 4 Position */ +#define AFEC_CGR_GAIN4_Msk (_U_(0x3) << AFEC_CGR_GAIN4_Pos) /**< (AFEC_CGR) Gain for Channel 4 Mask */ +#define AFEC_CGR_GAIN4(value) (AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)) +#define AFEC_CGR_GAIN5_Pos _U_(10) /**< (AFEC_CGR) Gain for Channel 5 Position */ +#define AFEC_CGR_GAIN5_Msk (_U_(0x3) << AFEC_CGR_GAIN5_Pos) /**< (AFEC_CGR) Gain for Channel 5 Mask */ +#define AFEC_CGR_GAIN5(value) (AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)) +#define AFEC_CGR_GAIN6_Pos _U_(12) /**< (AFEC_CGR) Gain for Channel 6 Position */ +#define AFEC_CGR_GAIN6_Msk (_U_(0x3) << AFEC_CGR_GAIN6_Pos) /**< (AFEC_CGR) Gain for Channel 6 Mask */ +#define AFEC_CGR_GAIN6(value) (AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)) +#define AFEC_CGR_GAIN7_Pos _U_(14) /**< (AFEC_CGR) Gain for Channel 7 Position */ +#define AFEC_CGR_GAIN7_Msk (_U_(0x3) << AFEC_CGR_GAIN7_Pos) /**< (AFEC_CGR) Gain for Channel 7 Mask */ +#define AFEC_CGR_GAIN7(value) (AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)) +#define AFEC_CGR_GAIN8_Pos _U_(16) /**< (AFEC_CGR) Gain for Channel 8 Position */ +#define AFEC_CGR_GAIN8_Msk (_U_(0x3) << AFEC_CGR_GAIN8_Pos) /**< (AFEC_CGR) Gain for Channel 8 Mask */ +#define AFEC_CGR_GAIN8(value) (AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)) +#define AFEC_CGR_GAIN9_Pos _U_(18) /**< (AFEC_CGR) Gain for Channel 9 Position */ +#define AFEC_CGR_GAIN9_Msk (_U_(0x3) << AFEC_CGR_GAIN9_Pos) /**< (AFEC_CGR) Gain for Channel 9 Mask */ +#define AFEC_CGR_GAIN9(value) (AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)) +#define AFEC_CGR_GAIN10_Pos _U_(20) /**< (AFEC_CGR) Gain for Channel 10 Position */ +#define AFEC_CGR_GAIN10_Msk (_U_(0x3) << AFEC_CGR_GAIN10_Pos) /**< (AFEC_CGR) Gain for Channel 10 Mask */ +#define AFEC_CGR_GAIN10(value) (AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)) +#define AFEC_CGR_GAIN11_Pos _U_(22) /**< (AFEC_CGR) Gain for Channel 11 Position */ +#define AFEC_CGR_GAIN11_Msk (_U_(0x3) << AFEC_CGR_GAIN11_Pos) /**< (AFEC_CGR) Gain for Channel 11 Mask */ +#define AFEC_CGR_GAIN11(value) (AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)) +#define AFEC_CGR_Msk _U_(0x00FFFFFF) /**< (AFEC_CGR) Register Mask */ + + +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) (R/W 32) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0_Pos _U_(0) /**< (AFEC_DIFFR) Differential inputs for channel 0 Position */ +#define AFEC_DIFFR_DIFF0_Msk (_U_(0x1) << AFEC_DIFFR_DIFF0_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 0 Mask */ +#define AFEC_DIFFR_DIFF0(value) (AFEC_DIFFR_DIFF0_Msk & ((value) << AFEC_DIFFR_DIFF0_Pos)) +#define AFEC_DIFFR_DIFF1_Pos _U_(1) /**< (AFEC_DIFFR) Differential inputs for channel 1 Position */ +#define AFEC_DIFFR_DIFF1_Msk (_U_(0x1) << AFEC_DIFFR_DIFF1_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 1 Mask */ +#define AFEC_DIFFR_DIFF1(value) (AFEC_DIFFR_DIFF1_Msk & ((value) << AFEC_DIFFR_DIFF1_Pos)) +#define AFEC_DIFFR_DIFF2_Pos _U_(2) /**< (AFEC_DIFFR) Differential inputs for channel 2 Position */ +#define AFEC_DIFFR_DIFF2_Msk (_U_(0x1) << AFEC_DIFFR_DIFF2_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 2 Mask */ +#define AFEC_DIFFR_DIFF2(value) (AFEC_DIFFR_DIFF2_Msk & ((value) << AFEC_DIFFR_DIFF2_Pos)) +#define AFEC_DIFFR_DIFF3_Pos _U_(3) /**< (AFEC_DIFFR) Differential inputs for channel 3 Position */ +#define AFEC_DIFFR_DIFF3_Msk (_U_(0x1) << AFEC_DIFFR_DIFF3_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 3 Mask */ +#define AFEC_DIFFR_DIFF3(value) (AFEC_DIFFR_DIFF3_Msk & ((value) << AFEC_DIFFR_DIFF3_Pos)) +#define AFEC_DIFFR_DIFF4_Pos _U_(4) /**< (AFEC_DIFFR) Differential inputs for channel 4 Position */ +#define AFEC_DIFFR_DIFF4_Msk (_U_(0x1) << AFEC_DIFFR_DIFF4_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 4 Mask */ +#define AFEC_DIFFR_DIFF4(value) (AFEC_DIFFR_DIFF4_Msk & ((value) << AFEC_DIFFR_DIFF4_Pos)) +#define AFEC_DIFFR_DIFF5_Pos _U_(5) /**< (AFEC_DIFFR) Differential inputs for channel 5 Position */ +#define AFEC_DIFFR_DIFF5_Msk (_U_(0x1) << AFEC_DIFFR_DIFF5_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 5 Mask */ +#define AFEC_DIFFR_DIFF5(value) (AFEC_DIFFR_DIFF5_Msk & ((value) << AFEC_DIFFR_DIFF5_Pos)) +#define AFEC_DIFFR_DIFF6_Pos _U_(6) /**< (AFEC_DIFFR) Differential inputs for channel 6 Position */ +#define AFEC_DIFFR_DIFF6_Msk (_U_(0x1) << AFEC_DIFFR_DIFF6_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 6 Mask */ +#define AFEC_DIFFR_DIFF6(value) (AFEC_DIFFR_DIFF6_Msk & ((value) << AFEC_DIFFR_DIFF6_Pos)) +#define AFEC_DIFFR_DIFF7_Pos _U_(7) /**< (AFEC_DIFFR) Differential inputs for channel 7 Position */ +#define AFEC_DIFFR_DIFF7_Msk (_U_(0x1) << AFEC_DIFFR_DIFF7_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 7 Mask */ +#define AFEC_DIFFR_DIFF7(value) (AFEC_DIFFR_DIFF7_Msk & ((value) << AFEC_DIFFR_DIFF7_Pos)) +#define AFEC_DIFFR_DIFF8_Pos _U_(8) /**< (AFEC_DIFFR) Differential inputs for channel 8 Position */ +#define AFEC_DIFFR_DIFF8_Msk (_U_(0x1) << AFEC_DIFFR_DIFF8_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 8 Mask */ +#define AFEC_DIFFR_DIFF8(value) (AFEC_DIFFR_DIFF8_Msk & ((value) << AFEC_DIFFR_DIFF8_Pos)) +#define AFEC_DIFFR_DIFF9_Pos _U_(9) /**< (AFEC_DIFFR) Differential inputs for channel 9 Position */ +#define AFEC_DIFFR_DIFF9_Msk (_U_(0x1) << AFEC_DIFFR_DIFF9_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 9 Mask */ +#define AFEC_DIFFR_DIFF9(value) (AFEC_DIFFR_DIFF9_Msk & ((value) << AFEC_DIFFR_DIFF9_Pos)) +#define AFEC_DIFFR_DIFF10_Pos _U_(10) /**< (AFEC_DIFFR) Differential inputs for channel 10 Position */ +#define AFEC_DIFFR_DIFF10_Msk (_U_(0x1) << AFEC_DIFFR_DIFF10_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 10 Mask */ +#define AFEC_DIFFR_DIFF10(value) (AFEC_DIFFR_DIFF10_Msk & ((value) << AFEC_DIFFR_DIFF10_Pos)) +#define AFEC_DIFFR_DIFF11_Pos _U_(11) /**< (AFEC_DIFFR) Differential inputs for channel 11 Position */ +#define AFEC_DIFFR_DIFF11_Msk (_U_(0x1) << AFEC_DIFFR_DIFF11_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 11 Mask */ +#define AFEC_DIFFR_DIFF11(value) (AFEC_DIFFR_DIFF11_Msk & ((value) << AFEC_DIFFR_DIFF11_Pos)) +#define AFEC_DIFFR_Msk _U_(0x00000FFF) /**< (AFEC_DIFFR) Register Mask */ + +#define AFEC_DIFFR_DIFF_Pos _U_(0) /**< (AFEC_DIFFR Position) Differential inputs for channel xx */ +#define AFEC_DIFFR_DIFF_Msk (_U_(0xFFF) << AFEC_DIFFR_DIFF_Pos) /**< (AFEC_DIFFR Mask) DIFF */ +#define AFEC_DIFFR_DIFF(value) (AFEC_DIFFR_DIFF_Msk & ((value) << AFEC_DIFFR_DIFF_Pos)) + +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) (R/W 32) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos _U_(0) /**< (AFEC_CSELR) Channel Selection Position */ +#define AFEC_CSELR_CSEL_Msk (_U_(0xF) << AFEC_CSELR_CSEL_Pos) /**< (AFEC_CSELR) Channel Selection Mask */ +#define AFEC_CSELR_CSEL(value) (AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)) +#define AFEC_CSELR_Msk _U_(0x0000000F) /**< (AFEC_CSELR) Register Mask */ + + +/* -------- AFEC_CDR : (AFEC Offset: 0x68) ( R/ 32) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos _U_(0) /**< (AFEC_CDR) Converted Data Position */ +#define AFEC_CDR_DATA_Msk (_U_(0xFFFF) << AFEC_CDR_DATA_Pos) /**< (AFEC_CDR) Converted Data Mask */ +#define AFEC_CDR_DATA(value) (AFEC_CDR_DATA_Msk & ((value) << AFEC_CDR_DATA_Pos)) +#define AFEC_CDR_Msk _U_(0x0000FFFF) /**< (AFEC_CDR) Register Mask */ + + +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) (R/W 32) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos _U_(0) /**< (AFEC_COCR) Analog Offset Position */ +#define AFEC_COCR_AOFF_Msk (_U_(0x3FF) << AFEC_COCR_AOFF_Pos) /**< (AFEC_COCR) Analog Offset Mask */ +#define AFEC_COCR_AOFF(value) (AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)) +#define AFEC_COCR_Msk _U_(0x000003FF) /**< (AFEC_COCR) Register Mask */ + + +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) (R/W 32) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT_Pos _U_(0) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Position */ +#define AFEC_TEMPMR_RTCT_Msk (_U_(0x1) << AFEC_TEMPMR_RTCT_Pos) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Mask */ +#define AFEC_TEMPMR_RTCT(value) (AFEC_TEMPMR_RTCT_Msk & ((value) << AFEC_TEMPMR_RTCT_Pos)) +#define AFEC_TEMPMR_TEMPCMPMOD_Pos _U_(4) /**< (AFEC_TEMPMR) Temperature Comparison Mode Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (_U_(0x3) << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Temperature Comparison Mode Mask */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) (AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW_Val _U_(0x0) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val _U_(0x1) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN_Val _U_(0x2) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT_Val _U_(0x3) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (AFEC_TEMPMR_TEMPCMPMOD_LOW_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (AFEC_TEMPMR_TEMPCMPMOD_IN_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (AFEC_TEMPMR_TEMPCMPMOD_OUT_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_TEMPMR_Msk _U_(0x00000031) /**< (AFEC_TEMPMR) Register Mask */ + + +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) (R/W 32) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos _U_(0) /**< (AFEC_TEMPCWR) Temperature Low Threshold Position */ +#define AFEC_TEMPCWR_TLOWTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature Low Threshold Mask */ +#define AFEC_TEMPCWR_TLOWTHRES(value) (AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)) +#define AFEC_TEMPCWR_THIGHTHRES_Pos _U_(16) /**< (AFEC_TEMPCWR) Temperature High Threshold Position */ +#define AFEC_TEMPCWR_THIGHTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature High Threshold Mask */ +#define AFEC_TEMPCWR_THIGHTHRES(value) (AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)) +#define AFEC_TEMPCWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_TEMPCWR) Register Mask */ + + +/* -------- AFEC_ACR : (AFEC Offset: 0x94) (R/W 32) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN_Pos _U_(2) /**< (AFEC_ACR) PGA0 Enable Position */ +#define AFEC_ACR_PGA0EN_Msk (_U_(0x1) << AFEC_ACR_PGA0EN_Pos) /**< (AFEC_ACR) PGA0 Enable Mask */ +#define AFEC_ACR_PGA0EN(value) (AFEC_ACR_PGA0EN_Msk & ((value) << AFEC_ACR_PGA0EN_Pos)) +#define AFEC_ACR_PGA1EN_Pos _U_(3) /**< (AFEC_ACR) PGA1 Enable Position */ +#define AFEC_ACR_PGA1EN_Msk (_U_(0x1) << AFEC_ACR_PGA1EN_Pos) /**< (AFEC_ACR) PGA1 Enable Mask */ +#define AFEC_ACR_PGA1EN(value) (AFEC_ACR_PGA1EN_Msk & ((value) << AFEC_ACR_PGA1EN_Pos)) +#define AFEC_ACR_IBCTL_Pos _U_(8) /**< (AFEC_ACR) AFE Bias Current Control Position */ +#define AFEC_ACR_IBCTL_Msk (_U_(0x3) << AFEC_ACR_IBCTL_Pos) /**< (AFEC_ACR) AFE Bias Current Control Mask */ +#define AFEC_ACR_IBCTL(value) (AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)) +#define AFEC_ACR_Msk _U_(0x0000030C) /**< (AFEC_ACR) Register Mask */ + + +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) (R/W 32) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0_Pos _U_(0) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Position */ +#define AFEC_SHMR_DUAL0_Msk (_U_(0x1) << AFEC_SHMR_DUAL0_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Mask */ +#define AFEC_SHMR_DUAL0(value) (AFEC_SHMR_DUAL0_Msk & ((value) << AFEC_SHMR_DUAL0_Pos)) +#define AFEC_SHMR_DUAL1_Pos _U_(1) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Position */ +#define AFEC_SHMR_DUAL1_Msk (_U_(0x1) << AFEC_SHMR_DUAL1_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Mask */ +#define AFEC_SHMR_DUAL1(value) (AFEC_SHMR_DUAL1_Msk & ((value) << AFEC_SHMR_DUAL1_Pos)) +#define AFEC_SHMR_DUAL2_Pos _U_(2) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Position */ +#define AFEC_SHMR_DUAL2_Msk (_U_(0x1) << AFEC_SHMR_DUAL2_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Mask */ +#define AFEC_SHMR_DUAL2(value) (AFEC_SHMR_DUAL2_Msk & ((value) << AFEC_SHMR_DUAL2_Pos)) +#define AFEC_SHMR_DUAL3_Pos _U_(3) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Position */ +#define AFEC_SHMR_DUAL3_Msk (_U_(0x1) << AFEC_SHMR_DUAL3_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Mask */ +#define AFEC_SHMR_DUAL3(value) (AFEC_SHMR_DUAL3_Msk & ((value) << AFEC_SHMR_DUAL3_Pos)) +#define AFEC_SHMR_DUAL4_Pos _U_(4) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Position */ +#define AFEC_SHMR_DUAL4_Msk (_U_(0x1) << AFEC_SHMR_DUAL4_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Mask */ +#define AFEC_SHMR_DUAL4(value) (AFEC_SHMR_DUAL4_Msk & ((value) << AFEC_SHMR_DUAL4_Pos)) +#define AFEC_SHMR_DUAL5_Pos _U_(5) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Position */ +#define AFEC_SHMR_DUAL5_Msk (_U_(0x1) << AFEC_SHMR_DUAL5_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Mask */ +#define AFEC_SHMR_DUAL5(value) (AFEC_SHMR_DUAL5_Msk & ((value) << AFEC_SHMR_DUAL5_Pos)) +#define AFEC_SHMR_DUAL6_Pos _U_(6) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Position */ +#define AFEC_SHMR_DUAL6_Msk (_U_(0x1) << AFEC_SHMR_DUAL6_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Mask */ +#define AFEC_SHMR_DUAL6(value) (AFEC_SHMR_DUAL6_Msk & ((value) << AFEC_SHMR_DUAL6_Pos)) +#define AFEC_SHMR_DUAL7_Pos _U_(7) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Position */ +#define AFEC_SHMR_DUAL7_Msk (_U_(0x1) << AFEC_SHMR_DUAL7_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Mask */ +#define AFEC_SHMR_DUAL7(value) (AFEC_SHMR_DUAL7_Msk & ((value) << AFEC_SHMR_DUAL7_Pos)) +#define AFEC_SHMR_DUAL8_Pos _U_(8) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Position */ +#define AFEC_SHMR_DUAL8_Msk (_U_(0x1) << AFEC_SHMR_DUAL8_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Mask */ +#define AFEC_SHMR_DUAL8(value) (AFEC_SHMR_DUAL8_Msk & ((value) << AFEC_SHMR_DUAL8_Pos)) +#define AFEC_SHMR_DUAL9_Pos _U_(9) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Position */ +#define AFEC_SHMR_DUAL9_Msk (_U_(0x1) << AFEC_SHMR_DUAL9_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Mask */ +#define AFEC_SHMR_DUAL9(value) (AFEC_SHMR_DUAL9_Msk & ((value) << AFEC_SHMR_DUAL9_Pos)) +#define AFEC_SHMR_DUAL10_Pos _U_(10) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Position */ +#define AFEC_SHMR_DUAL10_Msk (_U_(0x1) << AFEC_SHMR_DUAL10_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Mask */ +#define AFEC_SHMR_DUAL10(value) (AFEC_SHMR_DUAL10_Msk & ((value) << AFEC_SHMR_DUAL10_Pos)) +#define AFEC_SHMR_DUAL11_Pos _U_(11) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Position */ +#define AFEC_SHMR_DUAL11_Msk (_U_(0x1) << AFEC_SHMR_DUAL11_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Mask */ +#define AFEC_SHMR_DUAL11(value) (AFEC_SHMR_DUAL11_Msk & ((value) << AFEC_SHMR_DUAL11_Pos)) +#define AFEC_SHMR_Msk _U_(0x00000FFF) /**< (AFEC_SHMR) Register Mask */ + +#define AFEC_SHMR_DUAL_Pos _U_(0) /**< (AFEC_SHMR Position) Dual Sample & Hold for channel xx */ +#define AFEC_SHMR_DUAL_Msk (_U_(0xFFF) << AFEC_SHMR_DUAL_Pos) /**< (AFEC_SHMR Mask) DUAL */ +#define AFEC_SHMR_DUAL(value) (AFEC_SHMR_DUAL_Msk & ((value) << AFEC_SHMR_DUAL_Pos)) + +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) (R/W 32) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL_Pos _U_(0) /**< (AFEC_COSR) Sample & Hold unit Correction Select Position */ +#define AFEC_COSR_CSEL_Msk (_U_(0x1) << AFEC_COSR_CSEL_Pos) /**< (AFEC_COSR) Sample & Hold unit Correction Select Mask */ +#define AFEC_COSR_CSEL(value) (AFEC_COSR_CSEL_Msk & ((value) << AFEC_COSR_CSEL_Pos)) +#define AFEC_COSR_Msk _U_(0x00000001) /**< (AFEC_COSR) Register Mask */ + + +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) (R/W 32) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos _U_(0) /**< (AFEC_CVR) Offset Correction Position */ +#define AFEC_CVR_OFFSETCORR_Msk (_U_(0xFFFF) << AFEC_CVR_OFFSETCORR_Pos) /**< (AFEC_CVR) Offset Correction Mask */ +#define AFEC_CVR_OFFSETCORR(value) (AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)) +#define AFEC_CVR_GAINCORR_Pos _U_(16) /**< (AFEC_CVR) Gain Correction Position */ +#define AFEC_CVR_GAINCORR_Msk (_U_(0xFFFF) << AFEC_CVR_GAINCORR_Pos) /**< (AFEC_CVR) Gain Correction Mask */ +#define AFEC_CVR_GAINCORR(value) (AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)) +#define AFEC_CVR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CVR) Register Mask */ + + +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) (R/W 32) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0_Pos _U_(0) /**< (AFEC_CECR) Error Correction Enable for channel 0 Position */ +#define AFEC_CECR_ECORR0_Msk (_U_(0x1) << AFEC_CECR_ECORR0_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 0 Mask */ +#define AFEC_CECR_ECORR0(value) (AFEC_CECR_ECORR0_Msk & ((value) << AFEC_CECR_ECORR0_Pos)) +#define AFEC_CECR_ECORR1_Pos _U_(1) /**< (AFEC_CECR) Error Correction Enable for channel 1 Position */ +#define AFEC_CECR_ECORR1_Msk (_U_(0x1) << AFEC_CECR_ECORR1_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 1 Mask */ +#define AFEC_CECR_ECORR1(value) (AFEC_CECR_ECORR1_Msk & ((value) << AFEC_CECR_ECORR1_Pos)) +#define AFEC_CECR_ECORR2_Pos _U_(2) /**< (AFEC_CECR) Error Correction Enable for channel 2 Position */ +#define AFEC_CECR_ECORR2_Msk (_U_(0x1) << AFEC_CECR_ECORR2_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 2 Mask */ +#define AFEC_CECR_ECORR2(value) (AFEC_CECR_ECORR2_Msk & ((value) << AFEC_CECR_ECORR2_Pos)) +#define AFEC_CECR_ECORR3_Pos _U_(3) /**< (AFEC_CECR) Error Correction Enable for channel 3 Position */ +#define AFEC_CECR_ECORR3_Msk (_U_(0x1) << AFEC_CECR_ECORR3_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 3 Mask */ +#define AFEC_CECR_ECORR3(value) (AFEC_CECR_ECORR3_Msk & ((value) << AFEC_CECR_ECORR3_Pos)) +#define AFEC_CECR_ECORR4_Pos _U_(4) /**< (AFEC_CECR) Error Correction Enable for channel 4 Position */ +#define AFEC_CECR_ECORR4_Msk (_U_(0x1) << AFEC_CECR_ECORR4_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 4 Mask */ +#define AFEC_CECR_ECORR4(value) (AFEC_CECR_ECORR4_Msk & ((value) << AFEC_CECR_ECORR4_Pos)) +#define AFEC_CECR_ECORR5_Pos _U_(5) /**< (AFEC_CECR) Error Correction Enable for channel 5 Position */ +#define AFEC_CECR_ECORR5_Msk (_U_(0x1) << AFEC_CECR_ECORR5_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 5 Mask */ +#define AFEC_CECR_ECORR5(value) (AFEC_CECR_ECORR5_Msk & ((value) << AFEC_CECR_ECORR5_Pos)) +#define AFEC_CECR_ECORR6_Pos _U_(6) /**< (AFEC_CECR) Error Correction Enable for channel 6 Position */ +#define AFEC_CECR_ECORR6_Msk (_U_(0x1) << AFEC_CECR_ECORR6_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 6 Mask */ +#define AFEC_CECR_ECORR6(value) (AFEC_CECR_ECORR6_Msk & ((value) << AFEC_CECR_ECORR6_Pos)) +#define AFEC_CECR_ECORR7_Pos _U_(7) /**< (AFEC_CECR) Error Correction Enable for channel 7 Position */ +#define AFEC_CECR_ECORR7_Msk (_U_(0x1) << AFEC_CECR_ECORR7_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 7 Mask */ +#define AFEC_CECR_ECORR7(value) (AFEC_CECR_ECORR7_Msk & ((value) << AFEC_CECR_ECORR7_Pos)) +#define AFEC_CECR_ECORR8_Pos _U_(8) /**< (AFEC_CECR) Error Correction Enable for channel 8 Position */ +#define AFEC_CECR_ECORR8_Msk (_U_(0x1) << AFEC_CECR_ECORR8_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 8 Mask */ +#define AFEC_CECR_ECORR8(value) (AFEC_CECR_ECORR8_Msk & ((value) << AFEC_CECR_ECORR8_Pos)) +#define AFEC_CECR_ECORR9_Pos _U_(9) /**< (AFEC_CECR) Error Correction Enable for channel 9 Position */ +#define AFEC_CECR_ECORR9_Msk (_U_(0x1) << AFEC_CECR_ECORR9_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 9 Mask */ +#define AFEC_CECR_ECORR9(value) (AFEC_CECR_ECORR9_Msk & ((value) << AFEC_CECR_ECORR9_Pos)) +#define AFEC_CECR_ECORR10_Pos _U_(10) /**< (AFEC_CECR) Error Correction Enable for channel 10 Position */ +#define AFEC_CECR_ECORR10_Msk (_U_(0x1) << AFEC_CECR_ECORR10_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 10 Mask */ +#define AFEC_CECR_ECORR10(value) (AFEC_CECR_ECORR10_Msk & ((value) << AFEC_CECR_ECORR10_Pos)) +#define AFEC_CECR_ECORR11_Pos _U_(11) /**< (AFEC_CECR) Error Correction Enable for channel 11 Position */ +#define AFEC_CECR_ECORR11_Msk (_U_(0x1) << AFEC_CECR_ECORR11_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 11 Mask */ +#define AFEC_CECR_ECORR11(value) (AFEC_CECR_ECORR11_Msk & ((value) << AFEC_CECR_ECORR11_Pos)) +#define AFEC_CECR_Msk _U_(0x00000FFF) /**< (AFEC_CECR) Register Mask */ + +#define AFEC_CECR_ECORR_Pos _U_(0) /**< (AFEC_CECR Position) Error Correction Enable for channel xx */ +#define AFEC_CECR_ECORR_Msk (_U_(0xFFF) << AFEC_CECR_ECORR_Pos) /**< (AFEC_CECR Mask) ECORR */ +#define AFEC_CECR_ECORR(value) (AFEC_CECR_ECORR_Msk & ((value) << AFEC_CECR_ECORR_Pos)) + +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) (R/W 32) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN_Pos _U_(0) /**< (AFEC_WPMR) Write Protection Enable Position */ +#define AFEC_WPMR_WPEN_Msk (_U_(0x1) << AFEC_WPMR_WPEN_Pos) /**< (AFEC_WPMR) Write Protection Enable Mask */ +#define AFEC_WPMR_WPEN(value) (AFEC_WPMR_WPEN_Msk & ((value) << AFEC_WPMR_WPEN_Pos)) +#define AFEC_WPMR_WPKEY_Pos _U_(8) /**< (AFEC_WPMR) Write Protect KEY Position */ +#define AFEC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Write Protect KEY Mask */ +#define AFEC_WPMR_WPKEY(value) (AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)) +#define AFEC_WPMR_WPKEY_PASSWD_Val _U_(0x414443) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define AFEC_WPMR_WPKEY_PASSWD (AFEC_WPMR_WPKEY_PASSWD_Val << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define AFEC_WPMR_Msk _U_(0xFFFFFF01) /**< (AFEC_WPMR) Register Mask */ + + +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) ( R/ 32) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS_Pos _U_(0) /**< (AFEC_WPSR) Write Protect Violation Status Position */ +#define AFEC_WPSR_WPVS_Msk (_U_(0x1) << AFEC_WPSR_WPVS_Pos) /**< (AFEC_WPSR) Write Protect Violation Status Mask */ +#define AFEC_WPSR_WPVS(value) (AFEC_WPSR_WPVS_Msk & ((value) << AFEC_WPSR_WPVS_Pos)) +#define AFEC_WPSR_WPVSRC_Pos _U_(8) /**< (AFEC_WPSR) Write Protect Violation Source Position */ +#define AFEC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << AFEC_WPSR_WPVSRC_Pos) /**< (AFEC_WPSR) Write Protect Violation Source Mask */ +#define AFEC_WPSR_WPVSRC(value) (AFEC_WPSR_WPVSRC_Msk & ((value) << AFEC_WPSR_WPVSRC_Pos)) +#define AFEC_WPSR_Msk _U_(0x00FFFF01) /**< (AFEC_WPSR) Register Mask */ + + +/** \brief AFEC register offsets definitions */ +#define AFEC_CR_REG_OFST (0x00) /**< (AFEC_CR) AFEC Control Register Offset */ +#define AFEC_MR_REG_OFST (0x04) /**< (AFEC_MR) AFEC Mode Register Offset */ +#define AFEC_EMR_REG_OFST (0x08) /**< (AFEC_EMR) AFEC Extended Mode Register Offset */ +#define AFEC_SEQ1R_REG_OFST (0x0C) /**< (AFEC_SEQ1R) AFEC Channel Sequence 1 Register Offset */ +#define AFEC_SEQ2R_REG_OFST (0x10) /**< (AFEC_SEQ2R) AFEC Channel Sequence 2 Register Offset */ +#define AFEC_CHER_REG_OFST (0x14) /**< (AFEC_CHER) AFEC Channel Enable Register Offset */ +#define AFEC_CHDR_REG_OFST (0x18) /**< (AFEC_CHDR) AFEC Channel Disable Register Offset */ +#define AFEC_CHSR_REG_OFST (0x1C) /**< (AFEC_CHSR) AFEC Channel Status Register Offset */ +#define AFEC_LCDR_REG_OFST (0x20) /**< (AFEC_LCDR) AFEC Last Converted Data Register Offset */ +#define AFEC_IER_REG_OFST (0x24) /**< (AFEC_IER) AFEC Interrupt Enable Register Offset */ +#define AFEC_IDR_REG_OFST (0x28) /**< (AFEC_IDR) AFEC Interrupt Disable Register Offset */ +#define AFEC_IMR_REG_OFST (0x2C) /**< (AFEC_IMR) AFEC Interrupt Mask Register Offset */ +#define AFEC_ISR_REG_OFST (0x30) /**< (AFEC_ISR) AFEC Interrupt Status Register Offset */ +#define AFEC_OVER_REG_OFST (0x4C) /**< (AFEC_OVER) AFEC Overrun Status Register Offset */ +#define AFEC_CWR_REG_OFST (0x50) /**< (AFEC_CWR) AFEC Compare Window Register Offset */ +#define AFEC_CGR_REG_OFST (0x54) /**< (AFEC_CGR) AFEC Channel Gain Register Offset */ +#define AFEC_DIFFR_REG_OFST (0x60) /**< (AFEC_DIFFR) AFEC Channel Differential Register Offset */ +#define AFEC_CSELR_REG_OFST (0x64) /**< (AFEC_CSELR) AFEC Channel Selection Register Offset */ +#define AFEC_CDR_REG_OFST (0x68) /**< (AFEC_CDR) AFEC Channel Data Register Offset */ +#define AFEC_COCR_REG_OFST (0x6C) /**< (AFEC_COCR) AFEC Channel Offset Compensation Register Offset */ +#define AFEC_TEMPMR_REG_OFST (0x70) /**< (AFEC_TEMPMR) AFEC Temperature Sensor Mode Register Offset */ +#define AFEC_TEMPCWR_REG_OFST (0x74) /**< (AFEC_TEMPCWR) AFEC Temperature Compare Window Register Offset */ +#define AFEC_ACR_REG_OFST (0x94) /**< (AFEC_ACR) AFEC Analog Control Register Offset */ +#define AFEC_SHMR_REG_OFST (0xA0) /**< (AFEC_SHMR) AFEC Sample & Hold Mode Register Offset */ +#define AFEC_COSR_REG_OFST (0xD0) /**< (AFEC_COSR) AFEC Correction Select Register Offset */ +#define AFEC_CVR_REG_OFST (0xD4) /**< (AFEC_CVR) AFEC Correction Values Register Offset */ +#define AFEC_CECR_REG_OFST (0xD8) /**< (AFEC_CECR) AFEC Channel Error Correction Register Offset */ +#define AFEC_WPMR_REG_OFST (0xE4) /**< (AFEC_WPMR) AFEC Write Protection Mode Register Offset */ +#define AFEC_WPSR_REG_OFST (0xE8) /**< (AFEC_WPSR) AFEC Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AFEC register API structure */ +typedef struct +{ + __O uint32_t AFEC_CR; /**< Offset: 0x00 ( /W 32) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< Offset: 0x04 (R/W 32) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< Offset: 0x08 (R/W 32) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< Offset: 0x0C (R/W 32) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< Offset: 0x10 (R/W 32) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< Offset: 0x14 ( /W 32) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< Offset: 0x18 ( /W 32) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< Offset: 0x1C (R/ 32) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< Offset: 0x20 (R/ 32) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< Offset: 0x24 ( /W 32) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< Offset: 0x28 ( /W 32) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< Offset: 0x2C (R/ 32) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< Offset: 0x30 (R/ 32) AFEC Interrupt Status Register */ + __I uint8_t Reserved1[0x18]; + __I uint32_t AFEC_OVER; /**< Offset: 0x4C (R/ 32) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< Offset: 0x50 (R/W 32) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< Offset: 0x54 (R/W 32) AFEC Channel Gain Register */ + __I uint8_t Reserved2[0x08]; + __IO uint32_t AFEC_DIFFR; /**< Offset: 0x60 (R/W 32) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< Offset: 0x64 (R/W 32) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< Offset: 0x68 (R/ 32) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< Offset: 0x6C (R/W 32) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< Offset: 0x70 (R/W 32) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< Offset: 0x74 (R/W 32) AFEC Temperature Compare Window Register */ + __I uint8_t Reserved3[0x1C]; + __IO uint32_t AFEC_ACR; /**< Offset: 0x94 (R/W 32) AFEC Analog Control Register */ + __I uint8_t Reserved4[0x08]; + __IO uint32_t AFEC_SHMR; /**< Offset: 0xA0 (R/W 32) AFEC Sample & Hold Mode Register */ + __I uint8_t Reserved5[0x2C]; + __IO uint32_t AFEC_COSR; /**< Offset: 0xD0 (R/W 32) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< Offset: 0xD4 (R/W 32) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< Offset: 0xD8 (R/W 32) AFEC Channel Error Correction Register */ + __I uint8_t Reserved6[0x08]; + __IO uint32_t AFEC_WPMR; /**< Offset: 0xE4 (R/W 32) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< Offset: 0xE8 (R/ 32) AFEC Write Protection Status Register */ +} afec_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_AFEC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/chipid.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/chipid.h new file mode 100644 index 00000000..0cc7f643 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/chipid.h @@ -0,0 +1,188 @@ +/** + * \brief Component description for CHIPID + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_CHIPID_COMPONENT_H_ +#define _SAME70_CHIPID_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CHIPID */ +/* ************************************************************************** */ + +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) ( R/ 32) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos _U_(0) /**< (CHIPID_CIDR) Version of the Device Position */ +#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */ +#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos)) +#define CHIPID_CIDR_EPROC_Pos _U_(5) /**< (CHIPID_CIDR) Embedded Processor Position */ +#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */ +#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos)) +#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */ +#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */ +#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */ +#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */ +#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */ +#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */ +#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */ +#define CHIPID_CIDR_NVPSIZ_Pos _U_(8) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos)) +#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_Pos _U_(12) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos)) +#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_Pos _U_(16) /**< (CHIPID_CIDR) Internal SRAM Size Position */ +#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */ +#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos)) +#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_ARCH_Pos _U_(20) /**< (CHIPID_CIDR) Architecture Identifier Position */ +#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */ +#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos)) +#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */ +#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */ +#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */ +#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */ +#define CHIPID_CIDR_NVPTYP_Pos _U_(28) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */ +#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */ +#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos)) +#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */ +#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */ +#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */ +#define CHIPID_CIDR_EXT_Pos _U_(31) /**< (CHIPID_CIDR) Extension Flag Position */ +#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */ +#define CHIPID_CIDR_EXT(value) (CHIPID_CIDR_EXT_Msk & ((value) << CHIPID_CIDR_EXT_Pos)) +#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */ + + +/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) ( R/ 32) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos _U_(0) /**< (CHIPID_EXID) Chip ID Extension Position */ +#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */ +#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos)) +#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */ + + +/** \brief CHIPID register offsets definitions */ +#define CHIPID_CIDR_REG_OFST (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */ +#define CHIPID_EXID_REG_OFST (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CHIPID register API structure */ +typedef struct +{ + __I uint32_t CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */ +} chipid_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_CHIPID_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/dacc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/dacc.h new file mode 100644 index 00000000..7482af74 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/dacc.h @@ -0,0 +1,387 @@ +/** + * \brief Component description for DACC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_DACC_COMPONENT_H_ +#define _SAME70_DACC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DACC */ +/* ************************************************************************** */ + +/* -------- DACC_CR : (DACC Offset: 0x00) ( /W 32) Control Register -------- */ +#define DACC_CR_SWRST_Pos _U_(0) /**< (DACC_CR) Software Reset Position */ +#define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */ +#define DACC_CR_SWRST(value) (DACC_CR_SWRST_Msk & ((value) << DACC_CR_SWRST_Pos)) +#define DACC_CR_Msk _U_(0x00000001) /**< (DACC_CR) Register Mask */ + + +/* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define DACC_MR_MAXS0_Pos _U_(0) /**< (DACC_MR) Max Speed Mode for Channel 0 Position */ +#define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */ +#define DACC_MR_MAXS0(value) (DACC_MR_MAXS0_Msk & ((value) << DACC_MR_MAXS0_Pos)) +#define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_MAXS1_Pos _U_(1) /**< (DACC_MR) Max Speed Mode for Channel 1 Position */ +#define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */ +#define DACC_MR_MAXS1(value) (DACC_MR_MAXS1_Msk & ((value) << DACC_MR_MAXS1_Pos)) +#define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_WORD_Pos _U_(4) /**< (DACC_MR) Word Transfer Mode Position */ +#define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */ +#define DACC_MR_WORD(value) (DACC_MR_WORD_Msk & ((value) << DACC_MR_WORD_Pos)) +#define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */ +#define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */ +#define DACC_MR_ZERO_Pos _U_(5) /**< (DACC_MR) Must always be written to 0. Position */ +#define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */ +#define DACC_MR_ZERO(value) (DACC_MR_ZERO_Msk & ((value) << DACC_MR_ZERO_Pos)) +#define DACC_MR_DIFF_Pos _U_(23) /**< (DACC_MR) Differential Mode Position */ +#define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */ +#define DACC_MR_DIFF(value) (DACC_MR_DIFF_Msk & ((value) << DACC_MR_DIFF_Pos)) +#define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */ +#define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */ +#define DACC_MR_PRESCALER_Pos _U_(24) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */ +#define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */ +#define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)) +#define DACC_MR_Msk _U_(0x0F800033) /**< (DACC_MR) Register Mask */ + +#define DACC_MR_MAXS_Pos _U_(0) /**< (DACC_MR Position) Max Speed Mode for Channel x */ +#define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */ +#define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos)) + +/* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0_Pos _U_(0) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */ +#define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */ +#define DACC_TRIGR_TRGEN0(value) (DACC_TRIGR_TRGEN0_Msk & ((value) << DACC_TRIGR_TRGEN0_Pos)) +#define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGEN1_Pos _U_(1) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */ +#define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */ +#define DACC_TRIGR_TRGEN1(value) (DACC_TRIGR_TRGEN1_Msk & ((value) << DACC_TRIGR_TRGEN1_Pos)) +#define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGSEL0_Pos _U_(4) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */ +#define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */ +#define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)) +#define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DATRG Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 output Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC1 output Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC2 output Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */ +#define DACC_TRIGR_TRGSEL1_Pos _U_(8) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */ +#define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */ +#define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)) +#define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DATRG Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 output Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC1 output Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC2 output Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */ +#define DACC_TRIGR_OSR0_Pos _U_(16) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */ +#define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */ +#define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)) +#define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_OSR1_Pos _U_(20) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */ +#define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */ +#define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)) +#define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_Msk _U_(0x00770773) /**< (DACC_TRIGR) Register Mask */ + +#define DACC_TRIGR_TRGEN_Pos _U_(0) /**< (DACC_TRIGR Position) Trigger Enable of Channel x */ +#define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */ +#define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos)) + +/* -------- DACC_CHER : (DACC Offset: 0x10) ( /W 32) Channel Enable Register -------- */ +#define DACC_CHER_CH0_Pos _U_(0) /**< (DACC_CHER) Channel 0 Enable Position */ +#define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */ +#define DACC_CHER_CH0(value) (DACC_CHER_CH0_Msk & ((value) << DACC_CHER_CH0_Pos)) +#define DACC_CHER_CH1_Pos _U_(1) /**< (DACC_CHER) Channel 1 Enable Position */ +#define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */ +#define DACC_CHER_CH1(value) (DACC_CHER_CH1_Msk & ((value) << DACC_CHER_CH1_Pos)) +#define DACC_CHER_Msk _U_(0x00000003) /**< (DACC_CHER) Register Mask */ + +#define DACC_CHER_CH_Pos _U_(0) /**< (DACC_CHER Position) Channel x Enable */ +#define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */ +#define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos)) + +/* -------- DACC_CHDR : (DACC Offset: 0x14) ( /W 32) Channel Disable Register -------- */ +#define DACC_CHDR_CH0_Pos _U_(0) /**< (DACC_CHDR) Channel 0 Disable Position */ +#define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */ +#define DACC_CHDR_CH0(value) (DACC_CHDR_CH0_Msk & ((value) << DACC_CHDR_CH0_Pos)) +#define DACC_CHDR_CH1_Pos _U_(1) /**< (DACC_CHDR) Channel 1 Disable Position */ +#define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */ +#define DACC_CHDR_CH1(value) (DACC_CHDR_CH1_Msk & ((value) << DACC_CHDR_CH1_Pos)) +#define DACC_CHDR_Msk _U_(0x00000003) /**< (DACC_CHDR) Register Mask */ + +#define DACC_CHDR_CH_Pos _U_(0) /**< (DACC_CHDR Position) Channel x Disable */ +#define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */ +#define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos)) + +/* -------- DACC_CHSR : (DACC Offset: 0x18) ( R/ 32) Channel Status Register -------- */ +#define DACC_CHSR_CH0_Pos _U_(0) /**< (DACC_CHSR) Channel 0 Status Position */ +#define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */ +#define DACC_CHSR_CH0(value) (DACC_CHSR_CH0_Msk & ((value) << DACC_CHSR_CH0_Pos)) +#define DACC_CHSR_CH1_Pos _U_(1) /**< (DACC_CHSR) Channel 1 Status Position */ +#define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */ +#define DACC_CHSR_CH1(value) (DACC_CHSR_CH1_Msk & ((value) << DACC_CHSR_CH1_Pos)) +#define DACC_CHSR_DACRDY0_Pos _U_(8) /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY0(value) (DACC_CHSR_DACRDY0_Msk & ((value) << DACC_CHSR_DACRDY0_Pos)) +#define DACC_CHSR_DACRDY1_Pos _U_(9) /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY1(value) (DACC_CHSR_DACRDY1_Msk & ((value) << DACC_CHSR_DACRDY1_Pos)) +#define DACC_CHSR_Msk _U_(0x00000303) /**< (DACC_CHSR) Register Mask */ + +#define DACC_CHSR_CH_Pos _U_(0) /**< (DACC_CHSR Position) Channel x Status */ +#define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */ +#define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos)) +#define DACC_CHSR_DACRDY_Pos _U_(8) /**< (DACC_CHSR Position) DAC Ready Flag */ +#define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */ +#define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos)) + +/* -------- DACC_CDR : (DACC Offset: 0x1C) ( /W 32) Conversion Data Register 0 -------- */ +#define DACC_CDR_DATA0_Pos _U_(0) /**< (DACC_CDR) Data to Convert for channel 0 Position */ +#define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */ +#define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)) +#define DACC_CDR_DATA1_Pos _U_(16) /**< (DACC_CDR) Data to Convert for channel 1 Position */ +#define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */ +#define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)) +#define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */ + + +/* -------- DACC_IER : (DACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0_Pos _U_(0) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */ +#define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */ +#define DACC_IER_TXRDY0(value) (DACC_IER_TXRDY0_Msk & ((value) << DACC_IER_TXRDY0_Pos)) +#define DACC_IER_TXRDY1_Pos _U_(1) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */ +#define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */ +#define DACC_IER_TXRDY1(value) (DACC_IER_TXRDY1_Msk & ((value) << DACC_IER_TXRDY1_Pos)) +#define DACC_IER_EOC0_Pos _U_(4) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */ +#define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */ +#define DACC_IER_EOC0(value) (DACC_IER_EOC0_Msk & ((value) << DACC_IER_EOC0_Pos)) +#define DACC_IER_EOC1_Pos _U_(5) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */ +#define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */ +#define DACC_IER_EOC1(value) (DACC_IER_EOC1_Msk & ((value) << DACC_IER_EOC1_Pos)) +#define DACC_IER_Msk _U_(0x00000033) /**< (DACC_IER) Register Mask */ + +#define DACC_IER_TXRDY_Pos _U_(0) /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */ +#define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */ +#define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos)) +#define DACC_IER_EOC_Pos _U_(4) /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */ +#define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */ +#define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos)) + +/* -------- DACC_IDR : (DACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0_Pos _U_(0) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */ +#define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_TXRDY0(value) (DACC_IDR_TXRDY0_Msk & ((value) << DACC_IDR_TXRDY0_Pos)) +#define DACC_IDR_TXRDY1_Pos _U_(1) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */ +#define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_TXRDY1(value) (DACC_IDR_TXRDY1_Msk & ((value) << DACC_IDR_TXRDY1_Pos)) +#define DACC_IDR_EOC0_Pos _U_(4) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */ +#define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_EOC0(value) (DACC_IDR_EOC0_Msk & ((value) << DACC_IDR_EOC0_Pos)) +#define DACC_IDR_EOC1_Pos _U_(5) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */ +#define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_EOC1(value) (DACC_IDR_EOC1_Msk & ((value) << DACC_IDR_EOC1_Pos)) +#define DACC_IDR_Msk _U_(0x00000033) /**< (DACC_IDR) Register Mask */ + +#define DACC_IDR_TXRDY_Pos _U_(0) /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */ +#define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */ +#define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos)) +#define DACC_IDR_EOC_Pos _U_(4) /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */ +#define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */ +#define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos)) + +/* -------- DACC_IMR : (DACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0_Pos _U_(0) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */ +#define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_TXRDY0(value) (DACC_IMR_TXRDY0_Msk & ((value) << DACC_IMR_TXRDY0_Pos)) +#define DACC_IMR_TXRDY1_Pos _U_(1) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */ +#define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_TXRDY1(value) (DACC_IMR_TXRDY1_Msk & ((value) << DACC_IMR_TXRDY1_Pos)) +#define DACC_IMR_EOC0_Pos _U_(4) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */ +#define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_EOC0(value) (DACC_IMR_EOC0_Msk & ((value) << DACC_IMR_EOC0_Pos)) +#define DACC_IMR_EOC1_Pos _U_(5) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */ +#define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_EOC1(value) (DACC_IMR_EOC1_Msk & ((value) << DACC_IMR_EOC1_Pos)) +#define DACC_IMR_Msk _U_(0x00000033) /**< (DACC_IMR) Register Mask */ + +#define DACC_IMR_TXRDY_Pos _U_(0) /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */ +#define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */ +#define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos)) +#define DACC_IMR_EOC_Pos _U_(4) /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */ +#define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */ +#define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos)) + +/* -------- DACC_ISR : (DACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0_Pos _U_(0) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */ +#define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_TXRDY0(value) (DACC_ISR_TXRDY0_Msk & ((value) << DACC_ISR_TXRDY0_Pos)) +#define DACC_ISR_TXRDY1_Pos _U_(1) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */ +#define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_TXRDY1(value) (DACC_ISR_TXRDY1_Msk & ((value) << DACC_ISR_TXRDY1_Pos)) +#define DACC_ISR_EOC0_Pos _U_(4) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */ +#define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_EOC0(value) (DACC_ISR_EOC0_Msk & ((value) << DACC_ISR_EOC0_Pos)) +#define DACC_ISR_EOC1_Pos _U_(5) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */ +#define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_EOC1(value) (DACC_ISR_EOC1_Msk & ((value) << DACC_ISR_EOC1_Pos)) +#define DACC_ISR_Msk _U_(0x00000033) /**< (DACC_ISR) Register Mask */ + +#define DACC_ISR_TXRDY_Pos _U_(0) /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */ +#define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */ +#define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos)) +#define DACC_ISR_EOC_Pos _U_(4) /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */ +#define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */ +#define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos)) + +/* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos _U_(0) /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)) +#define DACC_ACR_IBCTLCH1_Pos _U_(2) /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)) +#define DACC_ACR_Msk _U_(0x0000000F) /**< (DACC_ACR) Register Mask */ + + +/* -------- DACC_WPMR : (DACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN_Pos _U_(0) /**< (DACC_WPMR) Write Protection Enable Position */ +#define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */ +#define DACC_WPMR_WPEN(value) (DACC_WPMR_WPEN_Msk & ((value) << DACC_WPMR_WPEN_Pos)) +#define DACC_WPMR_WPKEY_Pos _U_(8) /**< (DACC_WPMR) Write Protect Key Position */ +#define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */ +#define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)) +#define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +#define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */ +#define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */ + + +/* -------- DACC_WPSR : (DACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS_Pos _U_(0) /**< (DACC_WPSR) Write Protection Violation Status Position */ +#define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */ +#define DACC_WPSR_WPVS(value) (DACC_WPSR_WPVS_Msk & ((value) << DACC_WPSR_WPVS_Pos)) +#define DACC_WPSR_WPVSRC_Pos _U_(8) /**< (DACC_WPSR) Write Protection Violation Source Position */ +#define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */ +#define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos)) +#define DACC_WPSR_Msk _U_(0x0000FF01) /**< (DACC_WPSR) Register Mask */ + + +/** \brief DACC register offsets definitions */ +#define DACC_CR_REG_OFST (0x00) /**< (DACC_CR) Control Register Offset */ +#define DACC_MR_REG_OFST (0x04) /**< (DACC_MR) Mode Register Offset */ +#define DACC_TRIGR_REG_OFST (0x08) /**< (DACC_TRIGR) Trigger Register Offset */ +#define DACC_CHER_REG_OFST (0x10) /**< (DACC_CHER) Channel Enable Register Offset */ +#define DACC_CHDR_REG_OFST (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */ +#define DACC_CHSR_REG_OFST (0x18) /**< (DACC_CHSR) Channel Status Register Offset */ +#define DACC_CDR_REG_OFST (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */ +#define DACC_IER_REG_OFST (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */ +#define DACC_IDR_REG_OFST (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */ +#define DACC_IMR_REG_OFST (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */ +#define DACC_ISR_REG_OFST (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */ +#define DACC_ACR_REG_OFST (0x94) /**< (DACC_ACR) Analog Current Register Offset */ +#define DACC_WPMR_REG_OFST (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */ +#define DACC_WPSR_REG_OFST (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DACC register API structure */ +typedef struct +{ + __O uint32_t DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */ + __O uint32_t DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x60]; + __IO uint32_t DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */ + __I uint8_t Reserved3[0x4C]; + __IO uint32_t DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} dacc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_DACC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/efc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/efc.h new file mode 100644 index 00000000..c379760b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/efc.h @@ -0,0 +1,172 @@ +/** + * \brief Component description for EFC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_EFC_COMPONENT_H_ +#define _SAME70_EFC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR EFC */ +/* ************************************************************************** */ + +/* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY_Pos _U_(0) /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */ +#define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */ +#define EEFC_FMR_FRDY(value) (EEFC_FMR_FRDY_Msk & ((value) << EEFC_FMR_FRDY_Pos)) +#define EEFC_FMR_FWS_Pos _U_(8) /**< (EEFC_FMR) Flash Wait State Position */ +#define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */ +#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)) +#define EEFC_FMR_SCOD_Pos _U_(16) /**< (EEFC_FMR) Sequential Code Optimization Disable Position */ +#define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */ +#define EEFC_FMR_SCOD(value) (EEFC_FMR_SCOD_Msk & ((value) << EEFC_FMR_SCOD_Pos)) +#define EEFC_FMR_CLOE_Pos _U_(26) /**< (EEFC_FMR) Code Loop Optimization Enable Position */ +#define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */ +#define EEFC_FMR_CLOE(value) (EEFC_FMR_CLOE_Msk & ((value) << EEFC_FMR_CLOE_Pos)) +#define EEFC_FMR_Msk _U_(0x04010F01) /**< (EEFC_FMR) Register Mask */ + + +/* -------- EEFC_FCR : (EFC Offset: 0x04) ( /W 32) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos _U_(0) /**< (EEFC_FCR) Flash Command Position */ +#define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */ +#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)) +#define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */ +#define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */ +#define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */ +#define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */ +#define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */ +#define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */ +#define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */ +#define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */ +#define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */ +#define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */ +#define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */ +#define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */ +#define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */ +#define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */ +#define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */ +#define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */ +#define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */ +#define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */ +#define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */ +#define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */ +#define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */ +#define EEFC_FCR_FARG_Pos _U_(8) /**< (EEFC_FCR) Flash Command Argument Position */ +#define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */ +#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)) +#define EEFC_FCR_FKEY_Pos _U_(24) /**< (EEFC_FCR) Flash Writing Protection Key Position */ +#define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */ +#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)) +#define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +#define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */ +#define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */ + + +/* -------- EEFC_FSR : (EFC Offset: 0x08) ( R/ 32) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY_Pos _U_(0) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */ +#define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */ +#define EEFC_FSR_FRDY(value) (EEFC_FSR_FRDY_Msk & ((value) << EEFC_FSR_FRDY_Pos)) +#define EEFC_FSR_FCMDE_Pos _U_(1) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */ +#define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */ +#define EEFC_FSR_FCMDE(value) (EEFC_FSR_FCMDE_Msk & ((value) << EEFC_FSR_FCMDE_Pos)) +#define EEFC_FSR_FLOCKE_Pos _U_(2) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */ +#define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */ +#define EEFC_FSR_FLOCKE(value) (EEFC_FSR_FLOCKE_Msk & ((value) << EEFC_FSR_FLOCKE_Pos)) +#define EEFC_FSR_FLERR_Pos _U_(3) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */ +#define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */ +#define EEFC_FSR_FLERR(value) (EEFC_FSR_FLERR_Msk & ((value) << EEFC_FSR_FLERR_Pos)) +#define EEFC_FSR_UECCELSB_Pos _U_(16) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCELSB(value) (EEFC_FSR_UECCELSB_Msk & ((value) << EEFC_FSR_UECCELSB_Pos)) +#define EEFC_FSR_MECCELSB_Pos _U_(17) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCELSB(value) (EEFC_FSR_MECCELSB_Msk & ((value) << EEFC_FSR_MECCELSB_Pos)) +#define EEFC_FSR_UECCEMSB_Pos _U_(18) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCEMSB(value) (EEFC_FSR_UECCEMSB_Msk & ((value) << EEFC_FSR_UECCEMSB_Pos)) +#define EEFC_FSR_MECCEMSB_Pos _U_(19) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCEMSB(value) (EEFC_FSR_MECCEMSB_Msk & ((value) << EEFC_FSR_MECCEMSB_Pos)) +#define EEFC_FSR_Msk _U_(0x000F000F) /**< (EEFC_FSR) Register Mask */ + + +/* -------- EEFC_FRR : (EFC Offset: 0x0C) ( R/ 32) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos _U_(0) /**< (EEFC_FRR) Flash Result Value Position */ +#define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */ +#define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos)) +#define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */ + + +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN_Pos _U_(0) /**< (EEFC_WPMR) Write Protection Enable Position */ +#define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */ +#define EEFC_WPMR_WPEN(value) (EEFC_WPMR_WPEN_Msk & ((value) << EEFC_WPMR_WPEN_Pos)) +#define EEFC_WPMR_WPKEY_Pos _U_(8) /**< (EEFC_WPMR) Write Protection Key Position */ +#define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */ +#define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)) +#define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */ + + +/** \brief EFC register offsets definitions */ +#define EEFC_FMR_REG_OFST (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */ +#define EEFC_FCR_REG_OFST (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */ +#define EEFC_FSR_REG_OFST (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */ +#define EEFC_FRR_REG_OFST (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */ +#define EEFC_WPMR_REG_OFST (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief EFC register API structure */ +typedef struct +{ + __IO uint32_t EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */ + __I uint8_t Reserved1[0xD4]; + __IO uint32_t EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} efc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_EFC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/gmac.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/gmac.h new file mode 100644 index 00000000..88eeafb8 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/gmac.h @@ -0,0 +1,2500 @@ +/** + * \brief Component description for GMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_GMAC_COMPONENT_H_ +#define _SAME70_GMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR GMAC */ +/* ************************************************************************** */ + +/* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos _U_(0) /**< (GMAC_SAB) Specific Address 1 Position */ +#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /**< (GMAC_SAB) Specific Address 1 Mask */ +#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)) +#define GMAC_SAB_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAB) Register Mask */ + + +/* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos _U_(0) /**< (GMAC_SAT) Specific Address 1 Position */ +#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos) /**< (GMAC_SAT) Specific Address 1 Mask */ +#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)) +#define GMAC_SAT_Msk _U_(0x0000FFFF) /**< (GMAC_SAT) Register Mask */ + + +/* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ +#define GMAC_NCR_LBL_Pos _U_(1) /**< (GMAC_NCR) Loop Back Local Position */ +#define GMAC_NCR_LBL_Msk (_U_(0x1) << GMAC_NCR_LBL_Pos) /**< (GMAC_NCR) Loop Back Local Mask */ +#define GMAC_NCR_LBL(value) (GMAC_NCR_LBL_Msk & ((value) << GMAC_NCR_LBL_Pos)) +#define GMAC_NCR_RXEN_Pos _U_(2) /**< (GMAC_NCR) Receive Enable Position */ +#define GMAC_NCR_RXEN_Msk (_U_(0x1) << GMAC_NCR_RXEN_Pos) /**< (GMAC_NCR) Receive Enable Mask */ +#define GMAC_NCR_RXEN(value) (GMAC_NCR_RXEN_Msk & ((value) << GMAC_NCR_RXEN_Pos)) +#define GMAC_NCR_TXEN_Pos _U_(3) /**< (GMAC_NCR) Transmit Enable Position */ +#define GMAC_NCR_TXEN_Msk (_U_(0x1) << GMAC_NCR_TXEN_Pos) /**< (GMAC_NCR) Transmit Enable Mask */ +#define GMAC_NCR_TXEN(value) (GMAC_NCR_TXEN_Msk & ((value) << GMAC_NCR_TXEN_Pos)) +#define GMAC_NCR_MPE_Pos _U_(4) /**< (GMAC_NCR) Management Port Enable Position */ +#define GMAC_NCR_MPE_Msk (_U_(0x1) << GMAC_NCR_MPE_Pos) /**< (GMAC_NCR) Management Port Enable Mask */ +#define GMAC_NCR_MPE(value) (GMAC_NCR_MPE_Msk & ((value) << GMAC_NCR_MPE_Pos)) +#define GMAC_NCR_CLRSTAT_Pos _U_(5) /**< (GMAC_NCR) Clear Statistics Registers Position */ +#define GMAC_NCR_CLRSTAT_Msk (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos) /**< (GMAC_NCR) Clear Statistics Registers Mask */ +#define GMAC_NCR_CLRSTAT(value) (GMAC_NCR_CLRSTAT_Msk & ((value) << GMAC_NCR_CLRSTAT_Pos)) +#define GMAC_NCR_INCSTAT_Pos _U_(6) /**< (GMAC_NCR) Increment Statistics Registers Position */ +#define GMAC_NCR_INCSTAT_Msk (_U_(0x1) << GMAC_NCR_INCSTAT_Pos) /**< (GMAC_NCR) Increment Statistics Registers Mask */ +#define GMAC_NCR_INCSTAT(value) (GMAC_NCR_INCSTAT_Msk & ((value) << GMAC_NCR_INCSTAT_Pos)) +#define GMAC_NCR_WESTAT_Pos _U_(7) /**< (GMAC_NCR) Write Enable for Statistics Registers Position */ +#define GMAC_NCR_WESTAT_Msk (_U_(0x1) << GMAC_NCR_WESTAT_Pos) /**< (GMAC_NCR) Write Enable for Statistics Registers Mask */ +#define GMAC_NCR_WESTAT(value) (GMAC_NCR_WESTAT_Msk & ((value) << GMAC_NCR_WESTAT_Pos)) +#define GMAC_NCR_BP_Pos _U_(8) /**< (GMAC_NCR) Back pressure Position */ +#define GMAC_NCR_BP_Msk (_U_(0x1) << GMAC_NCR_BP_Pos) /**< (GMAC_NCR) Back pressure Mask */ +#define GMAC_NCR_BP(value) (GMAC_NCR_BP_Msk & ((value) << GMAC_NCR_BP_Pos)) +#define GMAC_NCR_TSTART_Pos _U_(9) /**< (GMAC_NCR) Start Transmission Position */ +#define GMAC_NCR_TSTART_Msk (_U_(0x1) << GMAC_NCR_TSTART_Pos) /**< (GMAC_NCR) Start Transmission Mask */ +#define GMAC_NCR_TSTART(value) (GMAC_NCR_TSTART_Msk & ((value) << GMAC_NCR_TSTART_Pos)) +#define GMAC_NCR_THALT_Pos _U_(10) /**< (GMAC_NCR) Transmit Halt Position */ +#define GMAC_NCR_THALT_Msk (_U_(0x1) << GMAC_NCR_THALT_Pos) /**< (GMAC_NCR) Transmit Halt Mask */ +#define GMAC_NCR_THALT(value) (GMAC_NCR_THALT_Msk & ((value) << GMAC_NCR_THALT_Pos)) +#define GMAC_NCR_TXPF_Pos _U_(11) /**< (GMAC_NCR) Transmit Pause Frame Position */ +#define GMAC_NCR_TXPF_Msk (_U_(0x1) << GMAC_NCR_TXPF_Pos) /**< (GMAC_NCR) Transmit Pause Frame Mask */ +#define GMAC_NCR_TXPF(value) (GMAC_NCR_TXPF_Msk & ((value) << GMAC_NCR_TXPF_Pos)) +#define GMAC_NCR_TXZQPF_Pos _U_(12) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ +#define GMAC_NCR_TXZQPF_Msk (_U_(0x1) << GMAC_NCR_TXZQPF_Pos) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ +#define GMAC_NCR_TXZQPF(value) (GMAC_NCR_TXZQPF_Msk & ((value) << GMAC_NCR_TXZQPF_Pos)) +#define GMAC_NCR_SRTSM_Pos _U_(15) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Position */ +#define GMAC_NCR_SRTSM_Msk (_U_(0x1) << GMAC_NCR_SRTSM_Pos) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ +#define GMAC_NCR_SRTSM(value) (GMAC_NCR_SRTSM_Msk & ((value) << GMAC_NCR_SRTSM_Pos)) +#define GMAC_NCR_ENPBPR_Pos _U_(16) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ +#define GMAC_NCR_ENPBPR_Msk (_U_(0x1) << GMAC_NCR_ENPBPR_Pos) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ +#define GMAC_NCR_ENPBPR(value) (GMAC_NCR_ENPBPR_Msk & ((value) << GMAC_NCR_ENPBPR_Pos)) +#define GMAC_NCR_TXPBPF_Pos _U_(17) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ +#define GMAC_NCR_TXPBPF_Msk (_U_(0x1) << GMAC_NCR_TXPBPF_Pos) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ +#define GMAC_NCR_TXPBPF(value) (GMAC_NCR_TXPBPF_Msk & ((value) << GMAC_NCR_TXPBPF_Pos)) +#define GMAC_NCR_FNP_Pos _U_(18) /**< (GMAC_NCR) Flush Next Packet Position */ +#define GMAC_NCR_FNP_Msk (_U_(0x1) << GMAC_NCR_FNP_Pos) /**< (GMAC_NCR) Flush Next Packet Mask */ +#define GMAC_NCR_FNP(value) (GMAC_NCR_FNP_Msk & ((value) << GMAC_NCR_FNP_Pos)) +#define GMAC_NCR_Msk _U_(0x00079FFE) /**< (GMAC_NCR) Register Mask */ + + +/* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD_Pos _U_(0) /**< (GMAC_NCFGR) Speed Position */ +#define GMAC_NCFGR_SPD_Msk (_U_(0x1) << GMAC_NCFGR_SPD_Pos) /**< (GMAC_NCFGR) Speed Mask */ +#define GMAC_NCFGR_SPD(value) (GMAC_NCFGR_SPD_Msk & ((value) << GMAC_NCFGR_SPD_Pos)) +#define GMAC_NCFGR_FD_Pos _U_(1) /**< (GMAC_NCFGR) Full Duplex Position */ +#define GMAC_NCFGR_FD_Msk (_U_(0x1) << GMAC_NCFGR_FD_Pos) /**< (GMAC_NCFGR) Full Duplex Mask */ +#define GMAC_NCFGR_FD(value) (GMAC_NCFGR_FD_Msk & ((value) << GMAC_NCFGR_FD_Pos)) +#define GMAC_NCFGR_DNVLAN_Pos _U_(2) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ +#define GMAC_NCFGR_DNVLAN_Msk (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ +#define GMAC_NCFGR_DNVLAN(value) (GMAC_NCFGR_DNVLAN_Msk & ((value) << GMAC_NCFGR_DNVLAN_Pos)) +#define GMAC_NCFGR_JFRAME_Pos _U_(3) /**< (GMAC_NCFGR) Jumbo Frame Size Position */ +#define GMAC_NCFGR_JFRAME_Msk (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos) /**< (GMAC_NCFGR) Jumbo Frame Size Mask */ +#define GMAC_NCFGR_JFRAME(value) (GMAC_NCFGR_JFRAME_Msk & ((value) << GMAC_NCFGR_JFRAME_Pos)) +#define GMAC_NCFGR_CAF_Pos _U_(4) /**< (GMAC_NCFGR) Copy All Frames Position */ +#define GMAC_NCFGR_CAF_Msk (_U_(0x1) << GMAC_NCFGR_CAF_Pos) /**< (GMAC_NCFGR) Copy All Frames Mask */ +#define GMAC_NCFGR_CAF(value) (GMAC_NCFGR_CAF_Msk & ((value) << GMAC_NCFGR_CAF_Pos)) +#define GMAC_NCFGR_NBC_Pos _U_(5) /**< (GMAC_NCFGR) No Broadcast Position */ +#define GMAC_NCFGR_NBC_Msk (_U_(0x1) << GMAC_NCFGR_NBC_Pos) /**< (GMAC_NCFGR) No Broadcast Mask */ +#define GMAC_NCFGR_NBC(value) (GMAC_NCFGR_NBC_Msk & ((value) << GMAC_NCFGR_NBC_Pos)) +#define GMAC_NCFGR_MTIHEN_Pos _U_(6) /**< (GMAC_NCFGR) Multicast Hash Enable Position */ +#define GMAC_NCFGR_MTIHEN_Msk (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /**< (GMAC_NCFGR) Multicast Hash Enable Mask */ +#define GMAC_NCFGR_MTIHEN(value) (GMAC_NCFGR_MTIHEN_Msk & ((value) << GMAC_NCFGR_MTIHEN_Pos)) +#define GMAC_NCFGR_UNIHEN_Pos _U_(7) /**< (GMAC_NCFGR) Unicast Hash Enable Position */ +#define GMAC_NCFGR_UNIHEN_Msk (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /**< (GMAC_NCFGR) Unicast Hash Enable Mask */ +#define GMAC_NCFGR_UNIHEN(value) (GMAC_NCFGR_UNIHEN_Msk & ((value) << GMAC_NCFGR_UNIHEN_Pos)) +#define GMAC_NCFGR_MAXFS_Pos _U_(8) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Position */ +#define GMAC_NCFGR_MAXFS_Msk (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ +#define GMAC_NCFGR_MAXFS(value) (GMAC_NCFGR_MAXFS_Msk & ((value) << GMAC_NCFGR_MAXFS_Pos)) +#define GMAC_NCFGR_RTY_Pos _U_(12) /**< (GMAC_NCFGR) Retry Test Position */ +#define GMAC_NCFGR_RTY_Msk (_U_(0x1) << GMAC_NCFGR_RTY_Pos) /**< (GMAC_NCFGR) Retry Test Mask */ +#define GMAC_NCFGR_RTY(value) (GMAC_NCFGR_RTY_Msk & ((value) << GMAC_NCFGR_RTY_Pos)) +#define GMAC_NCFGR_PEN_Pos _U_(13) /**< (GMAC_NCFGR) Pause Enable Position */ +#define GMAC_NCFGR_PEN_Msk (_U_(0x1) << GMAC_NCFGR_PEN_Pos) /**< (GMAC_NCFGR) Pause Enable Mask */ +#define GMAC_NCFGR_PEN(value) (GMAC_NCFGR_PEN_Msk & ((value) << GMAC_NCFGR_PEN_Pos)) +#define GMAC_NCFGR_RXBUFO_Pos _U_(14) /**< (GMAC_NCFGR) Receive Buffer Offset Position */ +#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /**< (GMAC_NCFGR) Receive Buffer Offset Mask */ +#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)) +#define GMAC_NCFGR_LFERD_Pos _U_(16) /**< (GMAC_NCFGR) Length Field Error Frame Discard Position */ +#define GMAC_NCFGR_LFERD_Msk (_U_(0x1) << GMAC_NCFGR_LFERD_Pos) /**< (GMAC_NCFGR) Length Field Error Frame Discard Mask */ +#define GMAC_NCFGR_LFERD(value) (GMAC_NCFGR_LFERD_Msk & ((value) << GMAC_NCFGR_LFERD_Pos)) +#define GMAC_NCFGR_RFCS_Pos _U_(17) /**< (GMAC_NCFGR) Remove FCS Position */ +#define GMAC_NCFGR_RFCS_Msk (_U_(0x1) << GMAC_NCFGR_RFCS_Pos) /**< (GMAC_NCFGR) Remove FCS Mask */ +#define GMAC_NCFGR_RFCS(value) (GMAC_NCFGR_RFCS_Msk & ((value) << GMAC_NCFGR_RFCS_Pos)) +#define GMAC_NCFGR_CLK_Pos _U_(18) /**< (GMAC_NCFGR) MDC CLock Division Position */ +#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MDC CLock Division Mask */ +#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)) +#define GMAC_NCFGR_CLK_MCK_8_Val _U_(0x0) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16_Val _U_(0x1) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32_Val _U_(0x2) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48_Val _U_(0x3) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64_Val _U_(0x4) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96_Val _U_(0x5) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_CLK_MCK_8 (GMAC_NCFGR_CLK_MCK_8_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_16 (GMAC_NCFGR_CLK_MCK_16_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_32 (GMAC_NCFGR_CLK_MCK_32_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_48 (GMAC_NCFGR_CLK_MCK_48_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_64 (GMAC_NCFGR_CLK_MCK_64_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_96 (GMAC_NCFGR_CLK_MCK_96_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) Position */ +#define GMAC_NCFGR_DBW_Pos _U_(21) /**< (GMAC_NCFGR) Data Bus Width Position */ +#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos) /**< (GMAC_NCFGR) Data Bus Width Mask */ +#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)) +#define GMAC_NCFGR_DCPF_Pos _U_(23) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Position */ +#define GMAC_NCFGR_DCPF_Msk (_U_(0x1) << GMAC_NCFGR_DCPF_Pos) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ +#define GMAC_NCFGR_DCPF(value) (GMAC_NCFGR_DCPF_Msk & ((value) << GMAC_NCFGR_DCPF_Pos)) +#define GMAC_NCFGR_RXCOEN_Pos _U_(24) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Position */ +#define GMAC_NCFGR_RXCOEN_Msk (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ +#define GMAC_NCFGR_RXCOEN(value) (GMAC_NCFGR_RXCOEN_Msk & ((value) << GMAC_NCFGR_RXCOEN_Pos)) +#define GMAC_NCFGR_EFRHD_Pos _U_(25) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ +#define GMAC_NCFGR_EFRHD_Msk (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ +#define GMAC_NCFGR_EFRHD(value) (GMAC_NCFGR_EFRHD_Msk & ((value) << GMAC_NCFGR_EFRHD_Pos)) +#define GMAC_NCFGR_IRXFCS_Pos _U_(26) /**< (GMAC_NCFGR) Ignore RX FCS Position */ +#define GMAC_NCFGR_IRXFCS_Msk (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /**< (GMAC_NCFGR) Ignore RX FCS Mask */ +#define GMAC_NCFGR_IRXFCS(value) (GMAC_NCFGR_IRXFCS_Msk & ((value) << GMAC_NCFGR_IRXFCS_Pos)) +#define GMAC_NCFGR_IPGSEN_Pos _U_(28) /**< (GMAC_NCFGR) IP Stretch Enable Position */ +#define GMAC_NCFGR_IPGSEN_Msk (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /**< (GMAC_NCFGR) IP Stretch Enable Mask */ +#define GMAC_NCFGR_IPGSEN(value) (GMAC_NCFGR_IPGSEN_Msk & ((value) << GMAC_NCFGR_IPGSEN_Pos)) +#define GMAC_NCFGR_RXBP_Pos _U_(29) /**< (GMAC_NCFGR) Receive Bad Preamble Position */ +#define GMAC_NCFGR_RXBP_Msk (_U_(0x1) << GMAC_NCFGR_RXBP_Pos) /**< (GMAC_NCFGR) Receive Bad Preamble Mask */ +#define GMAC_NCFGR_RXBP(value) (GMAC_NCFGR_RXBP_Msk & ((value) << GMAC_NCFGR_RXBP_Pos)) +#define GMAC_NCFGR_IRXER_Pos _U_(30) /**< (GMAC_NCFGR) Ignore IPG GRXER Position */ +#define GMAC_NCFGR_IRXER_Msk (_U_(0x1) << GMAC_NCFGR_IRXER_Pos) /**< (GMAC_NCFGR) Ignore IPG GRXER Mask */ +#define GMAC_NCFGR_IRXER(value) (GMAC_NCFGR_IRXER_Msk & ((value) << GMAC_NCFGR_IRXER_Pos)) +#define GMAC_NCFGR_Msk _U_(0x77FFF1FF) /**< (GMAC_NCFGR) Register Mask */ + + +/* -------- GMAC_NSR : (GMAC Offset: 0x08) ( R/ 32) Network Status Register -------- */ +#define GMAC_NSR_MDIO_Pos _U_(1) /**< (GMAC_NSR) MDIO Input Status Position */ +#define GMAC_NSR_MDIO_Msk (_U_(0x1) << GMAC_NSR_MDIO_Pos) /**< (GMAC_NSR) MDIO Input Status Mask */ +#define GMAC_NSR_MDIO(value) (GMAC_NSR_MDIO_Msk & ((value) << GMAC_NSR_MDIO_Pos)) +#define GMAC_NSR_IDLE_Pos _U_(2) /**< (GMAC_NSR) PHY Management Logic Idle Position */ +#define GMAC_NSR_IDLE_Msk (_U_(0x1) << GMAC_NSR_IDLE_Pos) /**< (GMAC_NSR) PHY Management Logic Idle Mask */ +#define GMAC_NSR_IDLE(value) (GMAC_NSR_IDLE_Msk & ((value) << GMAC_NSR_IDLE_Pos)) +#define GMAC_NSR_Msk _U_(0x00000006) /**< (GMAC_NSR) Register Mask */ + + +/* -------- GMAC_UR : (GMAC Offset: 0x0C) (R/W 32) User Register -------- */ +#define GMAC_UR_RMII_Pos _U_(0) /**< (GMAC_UR) Reduced MII Mode Position */ +#define GMAC_UR_RMII_Msk (_U_(0x1) << GMAC_UR_RMII_Pos) /**< (GMAC_UR) Reduced MII Mode Mask */ +#define GMAC_UR_RMII(value) (GMAC_UR_RMII_Msk & ((value) << GMAC_UR_RMII_Pos)) +#define GMAC_UR_Msk _U_(0x00000001) /**< (GMAC_UR) Register Mask */ + + +/* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos _U_(0) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ +#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ +#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)) +#define GMAC_DCFGR_FBLDO_SINGLE_Val _U_(0x1) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4_Val _U_(0x4) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8_Val _U_(0x8) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16_Val _U_(0x10) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ +#define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ +#define GMAC_DCFGR_ESMA_Pos _U_(6) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ +#define GMAC_DCFGR_ESMA_Msk (_U_(0x1) << GMAC_DCFGR_ESMA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ +#define GMAC_DCFGR_ESMA(value) (GMAC_DCFGR_ESMA_Msk & ((value) << GMAC_DCFGR_ESMA_Pos)) +#define GMAC_DCFGR_ESPA_Pos _U_(7) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ +#define GMAC_DCFGR_ESPA_Msk (_U_(0x1) << GMAC_DCFGR_ESPA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ +#define GMAC_DCFGR_ESPA(value) (GMAC_DCFGR_ESPA_Msk & ((value) << GMAC_DCFGR_ESPA_Pos)) +#define GMAC_DCFGR_RXBMS_Pos _U_(8) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)) +#define GMAC_DCFGR_RXBMS_EIGHTH_Val _U_(0x0) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER_Val _U_(0x1) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF_Val _U_(0x2) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL_Val _U_(0x3) /**< (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size Position */ +#define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_TXPBMS_Pos _U_(10) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_TXPBMS_Msk (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_TXPBMS(value) (GMAC_DCFGR_TXPBMS_Msk & ((value) << GMAC_DCFGR_TXPBMS_Pos)) +#define GMAC_DCFGR_TXCOEN_Pos _U_(11) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ +#define GMAC_DCFGR_TXCOEN_Msk (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ +#define GMAC_DCFGR_TXCOEN(value) (GMAC_DCFGR_TXCOEN_Msk & ((value) << GMAC_DCFGR_TXCOEN_Pos)) +#define GMAC_DCFGR_DRBS_Pos _U_(16) /**< (GMAC_DCFGR) DMA Receive Buffer Size Position */ +#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos) /**< (GMAC_DCFGR) DMA Receive Buffer Size Mask */ +#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)) +#define GMAC_DCFGR_DDRP_Pos _U_(24) /**< (GMAC_DCFGR) DMA Discard Receive Packets Position */ +#define GMAC_DCFGR_DDRP_Msk (_U_(0x1) << GMAC_DCFGR_DDRP_Pos) /**< (GMAC_DCFGR) DMA Discard Receive Packets Mask */ +#define GMAC_DCFGR_DDRP(value) (GMAC_DCFGR_DDRP_Msk & ((value) << GMAC_DCFGR_DDRP_Pos)) +#define GMAC_DCFGR_Msk _U_(0x01FF0FDF) /**< (GMAC_DCFGR) Register Mask */ + + +/* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ +#define GMAC_TSR_UBR_Pos _U_(0) /**< (GMAC_TSR) Used Bit Read Position */ +#define GMAC_TSR_UBR_Msk (_U_(0x1) << GMAC_TSR_UBR_Pos) /**< (GMAC_TSR) Used Bit Read Mask */ +#define GMAC_TSR_UBR(value) (GMAC_TSR_UBR_Msk & ((value) << GMAC_TSR_UBR_Pos)) +#define GMAC_TSR_COL_Pos _U_(1) /**< (GMAC_TSR) Collision Occurred Position */ +#define GMAC_TSR_COL_Msk (_U_(0x1) << GMAC_TSR_COL_Pos) /**< (GMAC_TSR) Collision Occurred Mask */ +#define GMAC_TSR_COL(value) (GMAC_TSR_COL_Msk & ((value) << GMAC_TSR_COL_Pos)) +#define GMAC_TSR_RLE_Pos _U_(2) /**< (GMAC_TSR) Retry Limit Exceeded Position */ +#define GMAC_TSR_RLE_Msk (_U_(0x1) << GMAC_TSR_RLE_Pos) /**< (GMAC_TSR) Retry Limit Exceeded Mask */ +#define GMAC_TSR_RLE(value) (GMAC_TSR_RLE_Msk & ((value) << GMAC_TSR_RLE_Pos)) +#define GMAC_TSR_TXGO_Pos _U_(3) /**< (GMAC_TSR) Transmit Go Position */ +#define GMAC_TSR_TXGO_Msk (_U_(0x1) << GMAC_TSR_TXGO_Pos) /**< (GMAC_TSR) Transmit Go Mask */ +#define GMAC_TSR_TXGO(value) (GMAC_TSR_TXGO_Msk & ((value) << GMAC_TSR_TXGO_Pos)) +#define GMAC_TSR_TFC_Pos _U_(4) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_TSR_TFC_Msk (_U_(0x1) << GMAC_TSR_TFC_Pos) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_TSR_TFC(value) (GMAC_TSR_TFC_Msk & ((value) << GMAC_TSR_TFC_Pos)) +#define GMAC_TSR_TXCOMP_Pos _U_(5) /**< (GMAC_TSR) Transmit Complete Position */ +#define GMAC_TSR_TXCOMP_Msk (_U_(0x1) << GMAC_TSR_TXCOMP_Pos) /**< (GMAC_TSR) Transmit Complete Mask */ +#define GMAC_TSR_TXCOMP(value) (GMAC_TSR_TXCOMP_Msk & ((value) << GMAC_TSR_TXCOMP_Pos)) +#define GMAC_TSR_HRESP_Pos _U_(8) /**< (GMAC_TSR) HRESP Not OK Position */ +#define GMAC_TSR_HRESP_Msk (_U_(0x1) << GMAC_TSR_HRESP_Pos) /**< (GMAC_TSR) HRESP Not OK Mask */ +#define GMAC_TSR_HRESP(value) (GMAC_TSR_HRESP_Msk & ((value) << GMAC_TSR_HRESP_Pos)) +#define GMAC_TSR_Msk _U_(0x0000013F) /**< (GMAC_TSR) Register Mask */ + + +/* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos _U_(2) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)) +#define GMAC_RBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQB) Register Mask */ + + +/* -------- GMAC_TBQB : (GMAC Offset: 0x1C) (R/W 32) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos _U_(2) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)) +#define GMAC_TBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQB) Register Mask */ + + +/* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ +#define GMAC_RSR_BNA_Pos _U_(0) /**< (GMAC_RSR) Buffer Not Available Position */ +#define GMAC_RSR_BNA_Msk (_U_(0x1) << GMAC_RSR_BNA_Pos) /**< (GMAC_RSR) Buffer Not Available Mask */ +#define GMAC_RSR_BNA(value) (GMAC_RSR_BNA_Msk & ((value) << GMAC_RSR_BNA_Pos)) +#define GMAC_RSR_REC_Pos _U_(1) /**< (GMAC_RSR) Frame Received Position */ +#define GMAC_RSR_REC_Msk (_U_(0x1) << GMAC_RSR_REC_Pos) /**< (GMAC_RSR) Frame Received Mask */ +#define GMAC_RSR_REC(value) (GMAC_RSR_REC_Msk & ((value) << GMAC_RSR_REC_Pos)) +#define GMAC_RSR_RXOVR_Pos _U_(2) /**< (GMAC_RSR) Receive Overrun Position */ +#define GMAC_RSR_RXOVR_Msk (_U_(0x1) << GMAC_RSR_RXOVR_Pos) /**< (GMAC_RSR) Receive Overrun Mask */ +#define GMAC_RSR_RXOVR(value) (GMAC_RSR_RXOVR_Msk & ((value) << GMAC_RSR_RXOVR_Pos)) +#define GMAC_RSR_HNO_Pos _U_(3) /**< (GMAC_RSR) HRESP Not OK Position */ +#define GMAC_RSR_HNO_Msk (_U_(0x1) << GMAC_RSR_HNO_Pos) /**< (GMAC_RSR) HRESP Not OK Mask */ +#define GMAC_RSR_HNO(value) (GMAC_RSR_HNO_Msk & ((value) << GMAC_RSR_HNO_Pos)) +#define GMAC_RSR_Msk _U_(0x0000000F) /**< (GMAC_RSR) Register Mask */ + + +/* -------- GMAC_ISR : (GMAC Offset: 0x24) ( R/ 32) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS_Pos _U_(0) /**< (GMAC_ISR) Management Frame Sent Position */ +#define GMAC_ISR_MFS_Msk (_U_(0x1) << GMAC_ISR_MFS_Pos) /**< (GMAC_ISR) Management Frame Sent Mask */ +#define GMAC_ISR_MFS(value) (GMAC_ISR_MFS_Msk & ((value) << GMAC_ISR_MFS_Pos)) +#define GMAC_ISR_RCOMP_Pos _U_(1) /**< (GMAC_ISR) Receive Complete Position */ +#define GMAC_ISR_RCOMP_Msk (_U_(0x1) << GMAC_ISR_RCOMP_Pos) /**< (GMAC_ISR) Receive Complete Mask */ +#define GMAC_ISR_RCOMP(value) (GMAC_ISR_RCOMP_Msk & ((value) << GMAC_ISR_RCOMP_Pos)) +#define GMAC_ISR_RXUBR_Pos _U_(2) /**< (GMAC_ISR) RX Used Bit Read Position */ +#define GMAC_ISR_RXUBR_Msk (_U_(0x1) << GMAC_ISR_RXUBR_Pos) /**< (GMAC_ISR) RX Used Bit Read Mask */ +#define GMAC_ISR_RXUBR(value) (GMAC_ISR_RXUBR_Msk & ((value) << GMAC_ISR_RXUBR_Pos)) +#define GMAC_ISR_TXUBR_Pos _U_(3) /**< (GMAC_ISR) TX Used Bit Read Position */ +#define GMAC_ISR_TXUBR_Msk (_U_(0x1) << GMAC_ISR_TXUBR_Pos) /**< (GMAC_ISR) TX Used Bit Read Mask */ +#define GMAC_ISR_TXUBR(value) (GMAC_ISR_TXUBR_Msk & ((value) << GMAC_ISR_TXUBR_Pos)) +#define GMAC_ISR_TUR_Pos _U_(4) /**< (GMAC_ISR) Transmit Underrun Position */ +#define GMAC_ISR_TUR_Msk (_U_(0x1) << GMAC_ISR_TUR_Pos) /**< (GMAC_ISR) Transmit Underrun Mask */ +#define GMAC_ISR_TUR(value) (GMAC_ISR_TUR_Msk & ((value) << GMAC_ISR_TUR_Pos)) +#define GMAC_ISR_RLEX_Pos _U_(5) /**< (GMAC_ISR) Retry Limit Exceeded Position */ +#define GMAC_ISR_RLEX_Msk (_U_(0x1) << GMAC_ISR_RLEX_Pos) /**< (GMAC_ISR) Retry Limit Exceeded Mask */ +#define GMAC_ISR_RLEX(value) (GMAC_ISR_RLEX_Msk & ((value) << GMAC_ISR_RLEX_Pos)) +#define GMAC_ISR_TFC_Pos _U_(6) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISR_TFC_Msk (_U_(0x1) << GMAC_ISR_TFC_Pos) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISR_TFC(value) (GMAC_ISR_TFC_Msk & ((value) << GMAC_ISR_TFC_Pos)) +#define GMAC_ISR_TCOMP_Pos _U_(7) /**< (GMAC_ISR) Transmit Complete Position */ +#define GMAC_ISR_TCOMP_Msk (_U_(0x1) << GMAC_ISR_TCOMP_Pos) /**< (GMAC_ISR) Transmit Complete Mask */ +#define GMAC_ISR_TCOMP(value) (GMAC_ISR_TCOMP_Msk & ((value) << GMAC_ISR_TCOMP_Pos)) +#define GMAC_ISR_ROVR_Pos _U_(10) /**< (GMAC_ISR) Receive Overrun Position */ +#define GMAC_ISR_ROVR_Msk (_U_(0x1) << GMAC_ISR_ROVR_Pos) /**< (GMAC_ISR) Receive Overrun Mask */ +#define GMAC_ISR_ROVR(value) (GMAC_ISR_ROVR_Msk & ((value) << GMAC_ISR_ROVR_Pos)) +#define GMAC_ISR_HRESP_Pos _U_(11) /**< (GMAC_ISR) HRESP Not OK Position */ +#define GMAC_ISR_HRESP_Msk (_U_(0x1) << GMAC_ISR_HRESP_Pos) /**< (GMAC_ISR) HRESP Not OK Mask */ +#define GMAC_ISR_HRESP(value) (GMAC_ISR_HRESP_Msk & ((value) << GMAC_ISR_HRESP_Pos)) +#define GMAC_ISR_PFNZ_Pos _U_(12) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_ISR_PFNZ_Msk (_U_(0x1) << GMAC_ISR_PFNZ_Pos) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_ISR_PFNZ(value) (GMAC_ISR_PFNZ_Msk & ((value) << GMAC_ISR_PFNZ_Pos)) +#define GMAC_ISR_PTZ_Pos _U_(13) /**< (GMAC_ISR) Pause Time Zero Position */ +#define GMAC_ISR_PTZ_Msk (_U_(0x1) << GMAC_ISR_PTZ_Pos) /**< (GMAC_ISR) Pause Time Zero Mask */ +#define GMAC_ISR_PTZ(value) (GMAC_ISR_PTZ_Msk & ((value) << GMAC_ISR_PTZ_Pos)) +#define GMAC_ISR_PFTR_Pos _U_(14) /**< (GMAC_ISR) Pause Frame Transmitted Position */ +#define GMAC_ISR_PFTR_Msk (_U_(0x1) << GMAC_ISR_PFTR_Pos) /**< (GMAC_ISR) Pause Frame Transmitted Mask */ +#define GMAC_ISR_PFTR(value) (GMAC_ISR_PFTR_Msk & ((value) << GMAC_ISR_PFTR_Pos)) +#define GMAC_ISR_DRQFR_Pos _U_(18) /**< (GMAC_ISR) PTP Delay Request Frame Received Position */ +#define GMAC_ISR_DRQFR_Msk (_U_(0x1) << GMAC_ISR_DRQFR_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Received Mask */ +#define GMAC_ISR_DRQFR(value) (GMAC_ISR_DRQFR_Msk & ((value) << GMAC_ISR_DRQFR_Pos)) +#define GMAC_ISR_SFR_Pos _U_(19) /**< (GMAC_ISR) PTP Sync Frame Received Position */ +#define GMAC_ISR_SFR_Msk (_U_(0x1) << GMAC_ISR_SFR_Pos) /**< (GMAC_ISR) PTP Sync Frame Received Mask */ +#define GMAC_ISR_SFR(value) (GMAC_ISR_SFR_Msk & ((value) << GMAC_ISR_SFR_Pos)) +#define GMAC_ISR_DRQFT_Pos _U_(20) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_ISR_DRQFT_Msk (_U_(0x1) << GMAC_ISR_DRQFT_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_ISR_DRQFT(value) (GMAC_ISR_DRQFT_Msk & ((value) << GMAC_ISR_DRQFT_Pos)) +#define GMAC_ISR_SFT_Pos _U_(21) /**< (GMAC_ISR) PTP Sync Frame Transmitted Position */ +#define GMAC_ISR_SFT_Msk (_U_(0x1) << GMAC_ISR_SFT_Pos) /**< (GMAC_ISR) PTP Sync Frame Transmitted Mask */ +#define GMAC_ISR_SFT(value) (GMAC_ISR_SFT_Msk & ((value) << GMAC_ISR_SFT_Pos)) +#define GMAC_ISR_PDRQFR_Pos _U_(22) /**< (GMAC_ISR) PDelay Request Frame Received Position */ +#define GMAC_ISR_PDRQFR_Msk (_U_(0x1) << GMAC_ISR_PDRQFR_Pos) /**< (GMAC_ISR) PDelay Request Frame Received Mask */ +#define GMAC_ISR_PDRQFR(value) (GMAC_ISR_PDRQFR_Msk & ((value) << GMAC_ISR_PDRQFR_Pos)) +#define GMAC_ISR_PDRSFR_Pos _U_(23) /**< (GMAC_ISR) PDelay Response Frame Received Position */ +#define GMAC_ISR_PDRSFR_Msk (_U_(0x1) << GMAC_ISR_PDRSFR_Pos) /**< (GMAC_ISR) PDelay Response Frame Received Mask */ +#define GMAC_ISR_PDRSFR(value) (GMAC_ISR_PDRSFR_Msk & ((value) << GMAC_ISR_PDRSFR_Pos)) +#define GMAC_ISR_PDRQFT_Pos _U_(24) /**< (GMAC_ISR) PDelay Request Frame Transmitted Position */ +#define GMAC_ISR_PDRQFT_Msk (_U_(0x1) << GMAC_ISR_PDRQFT_Pos) /**< (GMAC_ISR) PDelay Request Frame Transmitted Mask */ +#define GMAC_ISR_PDRQFT(value) (GMAC_ISR_PDRQFT_Msk & ((value) << GMAC_ISR_PDRQFT_Pos)) +#define GMAC_ISR_PDRSFT_Pos _U_(25) /**< (GMAC_ISR) PDelay Response Frame Transmitted Position */ +#define GMAC_ISR_PDRSFT_Msk (_U_(0x1) << GMAC_ISR_PDRSFT_Pos) /**< (GMAC_ISR) PDelay Response Frame Transmitted Mask */ +#define GMAC_ISR_PDRSFT(value) (GMAC_ISR_PDRSFT_Msk & ((value) << GMAC_ISR_PDRSFT_Pos)) +#define GMAC_ISR_SRI_Pos _U_(26) /**< (GMAC_ISR) TSU Seconds Register Increment Position */ +#define GMAC_ISR_SRI_Msk (_U_(0x1) << GMAC_ISR_SRI_Pos) /**< (GMAC_ISR) TSU Seconds Register Increment Mask */ +#define GMAC_ISR_SRI(value) (GMAC_ISR_SRI_Msk & ((value) << GMAC_ISR_SRI_Pos)) +#define GMAC_ISR_WOL_Pos _U_(28) /**< (GMAC_ISR) Wake On LAN Position */ +#define GMAC_ISR_WOL_Msk (_U_(0x1) << GMAC_ISR_WOL_Pos) /**< (GMAC_ISR) Wake On LAN Mask */ +#define GMAC_ISR_WOL(value) (GMAC_ISR_WOL_Msk & ((value) << GMAC_ISR_WOL_Pos)) +#define GMAC_ISR_Msk _U_(0x17FC7CFF) /**< (GMAC_ISR) Register Mask */ + + +/* -------- GMAC_IER : (GMAC Offset: 0x28) ( /W 32) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS_Pos _U_(0) /**< (GMAC_IER) Management Frame Sent Position */ +#define GMAC_IER_MFS_Msk (_U_(0x1) << GMAC_IER_MFS_Pos) /**< (GMAC_IER) Management Frame Sent Mask */ +#define GMAC_IER_MFS(value) (GMAC_IER_MFS_Msk & ((value) << GMAC_IER_MFS_Pos)) +#define GMAC_IER_RCOMP_Pos _U_(1) /**< (GMAC_IER) Receive Complete Position */ +#define GMAC_IER_RCOMP_Msk (_U_(0x1) << GMAC_IER_RCOMP_Pos) /**< (GMAC_IER) Receive Complete Mask */ +#define GMAC_IER_RCOMP(value) (GMAC_IER_RCOMP_Msk & ((value) << GMAC_IER_RCOMP_Pos)) +#define GMAC_IER_RXUBR_Pos _U_(2) /**< (GMAC_IER) RX Used Bit Read Position */ +#define GMAC_IER_RXUBR_Msk (_U_(0x1) << GMAC_IER_RXUBR_Pos) /**< (GMAC_IER) RX Used Bit Read Mask */ +#define GMAC_IER_RXUBR(value) (GMAC_IER_RXUBR_Msk & ((value) << GMAC_IER_RXUBR_Pos)) +#define GMAC_IER_TXUBR_Pos _U_(3) /**< (GMAC_IER) TX Used Bit Read Position */ +#define GMAC_IER_TXUBR_Msk (_U_(0x1) << GMAC_IER_TXUBR_Pos) /**< (GMAC_IER) TX Used Bit Read Mask */ +#define GMAC_IER_TXUBR(value) (GMAC_IER_TXUBR_Msk & ((value) << GMAC_IER_TXUBR_Pos)) +#define GMAC_IER_TUR_Pos _U_(4) /**< (GMAC_IER) Transmit Underrun Position */ +#define GMAC_IER_TUR_Msk (_U_(0x1) << GMAC_IER_TUR_Pos) /**< (GMAC_IER) Transmit Underrun Mask */ +#define GMAC_IER_TUR(value) (GMAC_IER_TUR_Msk & ((value) << GMAC_IER_TUR_Pos)) +#define GMAC_IER_RLEX_Pos _U_(5) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IER_RLEX_Msk (_U_(0x1) << GMAC_IER_RLEX_Pos) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IER_RLEX(value) (GMAC_IER_RLEX_Msk & ((value) << GMAC_IER_RLEX_Pos)) +#define GMAC_IER_TFC_Pos _U_(6) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IER_TFC_Msk (_U_(0x1) << GMAC_IER_TFC_Pos) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IER_TFC(value) (GMAC_IER_TFC_Msk & ((value) << GMAC_IER_TFC_Pos)) +#define GMAC_IER_TCOMP_Pos _U_(7) /**< (GMAC_IER) Transmit Complete Position */ +#define GMAC_IER_TCOMP_Msk (_U_(0x1) << GMAC_IER_TCOMP_Pos) /**< (GMAC_IER) Transmit Complete Mask */ +#define GMAC_IER_TCOMP(value) (GMAC_IER_TCOMP_Msk & ((value) << GMAC_IER_TCOMP_Pos)) +#define GMAC_IER_ROVR_Pos _U_(10) /**< (GMAC_IER) Receive Overrun Position */ +#define GMAC_IER_ROVR_Msk (_U_(0x1) << GMAC_IER_ROVR_Pos) /**< (GMAC_IER) Receive Overrun Mask */ +#define GMAC_IER_ROVR(value) (GMAC_IER_ROVR_Msk & ((value) << GMAC_IER_ROVR_Pos)) +#define GMAC_IER_HRESP_Pos _U_(11) /**< (GMAC_IER) HRESP Not OK Position */ +#define GMAC_IER_HRESP_Msk (_U_(0x1) << GMAC_IER_HRESP_Pos) /**< (GMAC_IER) HRESP Not OK Mask */ +#define GMAC_IER_HRESP(value) (GMAC_IER_HRESP_Msk & ((value) << GMAC_IER_HRESP_Pos)) +#define GMAC_IER_PFNZ_Pos _U_(12) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IER_PFNZ_Msk (_U_(0x1) << GMAC_IER_PFNZ_Pos) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IER_PFNZ(value) (GMAC_IER_PFNZ_Msk & ((value) << GMAC_IER_PFNZ_Pos)) +#define GMAC_IER_PTZ_Pos _U_(13) /**< (GMAC_IER) Pause Time Zero Position */ +#define GMAC_IER_PTZ_Msk (_U_(0x1) << GMAC_IER_PTZ_Pos) /**< (GMAC_IER) Pause Time Zero Mask */ +#define GMAC_IER_PTZ(value) (GMAC_IER_PTZ_Msk & ((value) << GMAC_IER_PTZ_Pos)) +#define GMAC_IER_PFTR_Pos _U_(14) /**< (GMAC_IER) Pause Frame Transmitted Position */ +#define GMAC_IER_PFTR_Msk (_U_(0x1) << GMAC_IER_PFTR_Pos) /**< (GMAC_IER) Pause Frame Transmitted Mask */ +#define GMAC_IER_PFTR(value) (GMAC_IER_PFTR_Msk & ((value) << GMAC_IER_PFTR_Pos)) +#define GMAC_IER_EXINT_Pos _U_(15) /**< (GMAC_IER) External Interrupt Position */ +#define GMAC_IER_EXINT_Msk (_U_(0x1) << GMAC_IER_EXINT_Pos) /**< (GMAC_IER) External Interrupt Mask */ +#define GMAC_IER_EXINT(value) (GMAC_IER_EXINT_Msk & ((value) << GMAC_IER_EXINT_Pos)) +#define GMAC_IER_DRQFR_Pos _U_(18) /**< (GMAC_IER) PTP Delay Request Frame Received Position */ +#define GMAC_IER_DRQFR_Msk (_U_(0x1) << GMAC_IER_DRQFR_Pos) /**< (GMAC_IER) PTP Delay Request Frame Received Mask */ +#define GMAC_IER_DRQFR(value) (GMAC_IER_DRQFR_Msk & ((value) << GMAC_IER_DRQFR_Pos)) +#define GMAC_IER_SFR_Pos _U_(19) /**< (GMAC_IER) PTP Sync Frame Received Position */ +#define GMAC_IER_SFR_Msk (_U_(0x1) << GMAC_IER_SFR_Pos) /**< (GMAC_IER) PTP Sync Frame Received Mask */ +#define GMAC_IER_SFR(value) (GMAC_IER_SFR_Msk & ((value) << GMAC_IER_SFR_Pos)) +#define GMAC_IER_DRQFT_Pos _U_(20) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IER_DRQFT_Msk (_U_(0x1) << GMAC_IER_DRQFT_Pos) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IER_DRQFT(value) (GMAC_IER_DRQFT_Msk & ((value) << GMAC_IER_DRQFT_Pos)) +#define GMAC_IER_SFT_Pos _U_(21) /**< (GMAC_IER) PTP Sync Frame Transmitted Position */ +#define GMAC_IER_SFT_Msk (_U_(0x1) << GMAC_IER_SFT_Pos) /**< (GMAC_IER) PTP Sync Frame Transmitted Mask */ +#define GMAC_IER_SFT(value) (GMAC_IER_SFT_Msk & ((value) << GMAC_IER_SFT_Pos)) +#define GMAC_IER_PDRQFR_Pos _U_(22) /**< (GMAC_IER) PDelay Request Frame Received Position */ +#define GMAC_IER_PDRQFR_Msk (_U_(0x1) << GMAC_IER_PDRQFR_Pos) /**< (GMAC_IER) PDelay Request Frame Received Mask */ +#define GMAC_IER_PDRQFR(value) (GMAC_IER_PDRQFR_Msk & ((value) << GMAC_IER_PDRQFR_Pos)) +#define GMAC_IER_PDRSFR_Pos _U_(23) /**< (GMAC_IER) PDelay Response Frame Received Position */ +#define GMAC_IER_PDRSFR_Msk (_U_(0x1) << GMAC_IER_PDRSFR_Pos) /**< (GMAC_IER) PDelay Response Frame Received Mask */ +#define GMAC_IER_PDRSFR(value) (GMAC_IER_PDRSFR_Msk & ((value) << GMAC_IER_PDRSFR_Pos)) +#define GMAC_IER_PDRQFT_Pos _U_(24) /**< (GMAC_IER) PDelay Request Frame Transmitted Position */ +#define GMAC_IER_PDRQFT_Msk (_U_(0x1) << GMAC_IER_PDRQFT_Pos) /**< (GMAC_IER) PDelay Request Frame Transmitted Mask */ +#define GMAC_IER_PDRQFT(value) (GMAC_IER_PDRQFT_Msk & ((value) << GMAC_IER_PDRQFT_Pos)) +#define GMAC_IER_PDRSFT_Pos _U_(25) /**< (GMAC_IER) PDelay Response Frame Transmitted Position */ +#define GMAC_IER_PDRSFT_Msk (_U_(0x1) << GMAC_IER_PDRSFT_Pos) /**< (GMAC_IER) PDelay Response Frame Transmitted Mask */ +#define GMAC_IER_PDRSFT(value) (GMAC_IER_PDRSFT_Msk & ((value) << GMAC_IER_PDRSFT_Pos)) +#define GMAC_IER_SRI_Pos _U_(26) /**< (GMAC_IER) TSU Seconds Register Increment Position */ +#define GMAC_IER_SRI_Msk (_U_(0x1) << GMAC_IER_SRI_Pos) /**< (GMAC_IER) TSU Seconds Register Increment Mask */ +#define GMAC_IER_SRI(value) (GMAC_IER_SRI_Msk & ((value) << GMAC_IER_SRI_Pos)) +#define GMAC_IER_WOL_Pos _U_(28) /**< (GMAC_IER) Wake On LAN Position */ +#define GMAC_IER_WOL_Msk (_U_(0x1) << GMAC_IER_WOL_Pos) /**< (GMAC_IER) Wake On LAN Mask */ +#define GMAC_IER_WOL(value) (GMAC_IER_WOL_Msk & ((value) << GMAC_IER_WOL_Pos)) +#define GMAC_IER_Msk _U_(0x17FCFCFF) /**< (GMAC_IER) Register Mask */ + + +/* -------- GMAC_IDR : (GMAC Offset: 0x2C) ( /W 32) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS_Pos _U_(0) /**< (GMAC_IDR) Management Frame Sent Position */ +#define GMAC_IDR_MFS_Msk (_U_(0x1) << GMAC_IDR_MFS_Pos) /**< (GMAC_IDR) Management Frame Sent Mask */ +#define GMAC_IDR_MFS(value) (GMAC_IDR_MFS_Msk & ((value) << GMAC_IDR_MFS_Pos)) +#define GMAC_IDR_RCOMP_Pos _U_(1) /**< (GMAC_IDR) Receive Complete Position */ +#define GMAC_IDR_RCOMP_Msk (_U_(0x1) << GMAC_IDR_RCOMP_Pos) /**< (GMAC_IDR) Receive Complete Mask */ +#define GMAC_IDR_RCOMP(value) (GMAC_IDR_RCOMP_Msk & ((value) << GMAC_IDR_RCOMP_Pos)) +#define GMAC_IDR_RXUBR_Pos _U_(2) /**< (GMAC_IDR) RX Used Bit Read Position */ +#define GMAC_IDR_RXUBR_Msk (_U_(0x1) << GMAC_IDR_RXUBR_Pos) /**< (GMAC_IDR) RX Used Bit Read Mask */ +#define GMAC_IDR_RXUBR(value) (GMAC_IDR_RXUBR_Msk & ((value) << GMAC_IDR_RXUBR_Pos)) +#define GMAC_IDR_TXUBR_Pos _U_(3) /**< (GMAC_IDR) TX Used Bit Read Position */ +#define GMAC_IDR_TXUBR_Msk (_U_(0x1) << GMAC_IDR_TXUBR_Pos) /**< (GMAC_IDR) TX Used Bit Read Mask */ +#define GMAC_IDR_TXUBR(value) (GMAC_IDR_TXUBR_Msk & ((value) << GMAC_IDR_TXUBR_Pos)) +#define GMAC_IDR_TUR_Pos _U_(4) /**< (GMAC_IDR) Transmit Underrun Position */ +#define GMAC_IDR_TUR_Msk (_U_(0x1) << GMAC_IDR_TUR_Pos) /**< (GMAC_IDR) Transmit Underrun Mask */ +#define GMAC_IDR_TUR(value) (GMAC_IDR_TUR_Msk & ((value) << GMAC_IDR_TUR_Pos)) +#define GMAC_IDR_RLEX_Pos _U_(5) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDR_RLEX_Msk (_U_(0x1) << GMAC_IDR_RLEX_Pos) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDR_RLEX(value) (GMAC_IDR_RLEX_Msk & ((value) << GMAC_IDR_RLEX_Pos)) +#define GMAC_IDR_TFC_Pos _U_(6) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDR_TFC_Msk (_U_(0x1) << GMAC_IDR_TFC_Pos) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDR_TFC(value) (GMAC_IDR_TFC_Msk & ((value) << GMAC_IDR_TFC_Pos)) +#define GMAC_IDR_TCOMP_Pos _U_(7) /**< (GMAC_IDR) Transmit Complete Position */ +#define GMAC_IDR_TCOMP_Msk (_U_(0x1) << GMAC_IDR_TCOMP_Pos) /**< (GMAC_IDR) Transmit Complete Mask */ +#define GMAC_IDR_TCOMP(value) (GMAC_IDR_TCOMP_Msk & ((value) << GMAC_IDR_TCOMP_Pos)) +#define GMAC_IDR_ROVR_Pos _U_(10) /**< (GMAC_IDR) Receive Overrun Position */ +#define GMAC_IDR_ROVR_Msk (_U_(0x1) << GMAC_IDR_ROVR_Pos) /**< (GMAC_IDR) Receive Overrun Mask */ +#define GMAC_IDR_ROVR(value) (GMAC_IDR_ROVR_Msk & ((value) << GMAC_IDR_ROVR_Pos)) +#define GMAC_IDR_HRESP_Pos _U_(11) /**< (GMAC_IDR) HRESP Not OK Position */ +#define GMAC_IDR_HRESP_Msk (_U_(0x1) << GMAC_IDR_HRESP_Pos) /**< (GMAC_IDR) HRESP Not OK Mask */ +#define GMAC_IDR_HRESP(value) (GMAC_IDR_HRESP_Msk & ((value) << GMAC_IDR_HRESP_Pos)) +#define GMAC_IDR_PFNZ_Pos _U_(12) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IDR_PFNZ_Msk (_U_(0x1) << GMAC_IDR_PFNZ_Pos) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IDR_PFNZ(value) (GMAC_IDR_PFNZ_Msk & ((value) << GMAC_IDR_PFNZ_Pos)) +#define GMAC_IDR_PTZ_Pos _U_(13) /**< (GMAC_IDR) Pause Time Zero Position */ +#define GMAC_IDR_PTZ_Msk (_U_(0x1) << GMAC_IDR_PTZ_Pos) /**< (GMAC_IDR) Pause Time Zero Mask */ +#define GMAC_IDR_PTZ(value) (GMAC_IDR_PTZ_Msk & ((value) << GMAC_IDR_PTZ_Pos)) +#define GMAC_IDR_PFTR_Pos _U_(14) /**< (GMAC_IDR) Pause Frame Transmitted Position */ +#define GMAC_IDR_PFTR_Msk (_U_(0x1) << GMAC_IDR_PFTR_Pos) /**< (GMAC_IDR) Pause Frame Transmitted Mask */ +#define GMAC_IDR_PFTR(value) (GMAC_IDR_PFTR_Msk & ((value) << GMAC_IDR_PFTR_Pos)) +#define GMAC_IDR_EXINT_Pos _U_(15) /**< (GMAC_IDR) External Interrupt Position */ +#define GMAC_IDR_EXINT_Msk (_U_(0x1) << GMAC_IDR_EXINT_Pos) /**< (GMAC_IDR) External Interrupt Mask */ +#define GMAC_IDR_EXINT(value) (GMAC_IDR_EXINT_Msk & ((value) << GMAC_IDR_EXINT_Pos)) +#define GMAC_IDR_DRQFR_Pos _U_(18) /**< (GMAC_IDR) PTP Delay Request Frame Received Position */ +#define GMAC_IDR_DRQFR_Msk (_U_(0x1) << GMAC_IDR_DRQFR_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Received Mask */ +#define GMAC_IDR_DRQFR(value) (GMAC_IDR_DRQFR_Msk & ((value) << GMAC_IDR_DRQFR_Pos)) +#define GMAC_IDR_SFR_Pos _U_(19) /**< (GMAC_IDR) PTP Sync Frame Received Position */ +#define GMAC_IDR_SFR_Msk (_U_(0x1) << GMAC_IDR_SFR_Pos) /**< (GMAC_IDR) PTP Sync Frame Received Mask */ +#define GMAC_IDR_SFR(value) (GMAC_IDR_SFR_Msk & ((value) << GMAC_IDR_SFR_Pos)) +#define GMAC_IDR_DRQFT_Pos _U_(20) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IDR_DRQFT_Msk (_U_(0x1) << GMAC_IDR_DRQFT_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IDR_DRQFT(value) (GMAC_IDR_DRQFT_Msk & ((value) << GMAC_IDR_DRQFT_Pos)) +#define GMAC_IDR_SFT_Pos _U_(21) /**< (GMAC_IDR) PTP Sync Frame Transmitted Position */ +#define GMAC_IDR_SFT_Msk (_U_(0x1) << GMAC_IDR_SFT_Pos) /**< (GMAC_IDR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IDR_SFT(value) (GMAC_IDR_SFT_Msk & ((value) << GMAC_IDR_SFT_Pos)) +#define GMAC_IDR_PDRQFR_Pos _U_(22) /**< (GMAC_IDR) PDelay Request Frame Received Position */ +#define GMAC_IDR_PDRQFR_Msk (_U_(0x1) << GMAC_IDR_PDRQFR_Pos) /**< (GMAC_IDR) PDelay Request Frame Received Mask */ +#define GMAC_IDR_PDRQFR(value) (GMAC_IDR_PDRQFR_Msk & ((value) << GMAC_IDR_PDRQFR_Pos)) +#define GMAC_IDR_PDRSFR_Pos _U_(23) /**< (GMAC_IDR) PDelay Response Frame Received Position */ +#define GMAC_IDR_PDRSFR_Msk (_U_(0x1) << GMAC_IDR_PDRSFR_Pos) /**< (GMAC_IDR) PDelay Response Frame Received Mask */ +#define GMAC_IDR_PDRSFR(value) (GMAC_IDR_PDRSFR_Msk & ((value) << GMAC_IDR_PDRSFR_Pos)) +#define GMAC_IDR_PDRQFT_Pos _U_(24) /**< (GMAC_IDR) PDelay Request Frame Transmitted Position */ +#define GMAC_IDR_PDRQFT_Msk (_U_(0x1) << GMAC_IDR_PDRQFT_Pos) /**< (GMAC_IDR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IDR_PDRQFT(value) (GMAC_IDR_PDRQFT_Msk & ((value) << GMAC_IDR_PDRQFT_Pos)) +#define GMAC_IDR_PDRSFT_Pos _U_(25) /**< (GMAC_IDR) PDelay Response Frame Transmitted Position */ +#define GMAC_IDR_PDRSFT_Msk (_U_(0x1) << GMAC_IDR_PDRSFT_Pos) /**< (GMAC_IDR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IDR_PDRSFT(value) (GMAC_IDR_PDRSFT_Msk & ((value) << GMAC_IDR_PDRSFT_Pos)) +#define GMAC_IDR_SRI_Pos _U_(26) /**< (GMAC_IDR) TSU Seconds Register Increment Position */ +#define GMAC_IDR_SRI_Msk (_U_(0x1) << GMAC_IDR_SRI_Pos) /**< (GMAC_IDR) TSU Seconds Register Increment Mask */ +#define GMAC_IDR_SRI(value) (GMAC_IDR_SRI_Msk & ((value) << GMAC_IDR_SRI_Pos)) +#define GMAC_IDR_WOL_Pos _U_(28) /**< (GMAC_IDR) Wake On LAN Position */ +#define GMAC_IDR_WOL_Msk (_U_(0x1) << GMAC_IDR_WOL_Pos) /**< (GMAC_IDR) Wake On LAN Mask */ +#define GMAC_IDR_WOL(value) (GMAC_IDR_WOL_Msk & ((value) << GMAC_IDR_WOL_Pos)) +#define GMAC_IDR_Msk _U_(0x17FCFCFF) /**< (GMAC_IDR) Register Mask */ + + +/* -------- GMAC_IMR : (GMAC Offset: 0x30) (R/W 32) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS_Pos _U_(0) /**< (GMAC_IMR) Management Frame Sent Position */ +#define GMAC_IMR_MFS_Msk (_U_(0x1) << GMAC_IMR_MFS_Pos) /**< (GMAC_IMR) Management Frame Sent Mask */ +#define GMAC_IMR_MFS(value) (GMAC_IMR_MFS_Msk & ((value) << GMAC_IMR_MFS_Pos)) +#define GMAC_IMR_RCOMP_Pos _U_(1) /**< (GMAC_IMR) Receive Complete Position */ +#define GMAC_IMR_RCOMP_Msk (_U_(0x1) << GMAC_IMR_RCOMP_Pos) /**< (GMAC_IMR) Receive Complete Mask */ +#define GMAC_IMR_RCOMP(value) (GMAC_IMR_RCOMP_Msk & ((value) << GMAC_IMR_RCOMP_Pos)) +#define GMAC_IMR_RXUBR_Pos _U_(2) /**< (GMAC_IMR) RX Used Bit Read Position */ +#define GMAC_IMR_RXUBR_Msk (_U_(0x1) << GMAC_IMR_RXUBR_Pos) /**< (GMAC_IMR) RX Used Bit Read Mask */ +#define GMAC_IMR_RXUBR(value) (GMAC_IMR_RXUBR_Msk & ((value) << GMAC_IMR_RXUBR_Pos)) +#define GMAC_IMR_TXUBR_Pos _U_(3) /**< (GMAC_IMR) TX Used Bit Read Position */ +#define GMAC_IMR_TXUBR_Msk (_U_(0x1) << GMAC_IMR_TXUBR_Pos) /**< (GMAC_IMR) TX Used Bit Read Mask */ +#define GMAC_IMR_TXUBR(value) (GMAC_IMR_TXUBR_Msk & ((value) << GMAC_IMR_TXUBR_Pos)) +#define GMAC_IMR_TUR_Pos _U_(4) /**< (GMAC_IMR) Transmit Underrun Position */ +#define GMAC_IMR_TUR_Msk (_U_(0x1) << GMAC_IMR_TUR_Pos) /**< (GMAC_IMR) Transmit Underrun Mask */ +#define GMAC_IMR_TUR(value) (GMAC_IMR_TUR_Msk & ((value) << GMAC_IMR_TUR_Pos)) +#define GMAC_IMR_RLEX_Pos _U_(5) /**< (GMAC_IMR) Retry Limit Exceeded Position */ +#define GMAC_IMR_RLEX_Msk (_U_(0x1) << GMAC_IMR_RLEX_Pos) /**< (GMAC_IMR) Retry Limit Exceeded Mask */ +#define GMAC_IMR_RLEX(value) (GMAC_IMR_RLEX_Msk & ((value) << GMAC_IMR_RLEX_Pos)) +#define GMAC_IMR_TFC_Pos _U_(6) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IMR_TFC_Msk (_U_(0x1) << GMAC_IMR_TFC_Pos) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IMR_TFC(value) (GMAC_IMR_TFC_Msk & ((value) << GMAC_IMR_TFC_Pos)) +#define GMAC_IMR_TCOMP_Pos _U_(7) /**< (GMAC_IMR) Transmit Complete Position */ +#define GMAC_IMR_TCOMP_Msk (_U_(0x1) << GMAC_IMR_TCOMP_Pos) /**< (GMAC_IMR) Transmit Complete Mask */ +#define GMAC_IMR_TCOMP(value) (GMAC_IMR_TCOMP_Msk & ((value) << GMAC_IMR_TCOMP_Pos)) +#define GMAC_IMR_ROVR_Pos _U_(10) /**< (GMAC_IMR) Receive Overrun Position */ +#define GMAC_IMR_ROVR_Msk (_U_(0x1) << GMAC_IMR_ROVR_Pos) /**< (GMAC_IMR) Receive Overrun Mask */ +#define GMAC_IMR_ROVR(value) (GMAC_IMR_ROVR_Msk & ((value) << GMAC_IMR_ROVR_Pos)) +#define GMAC_IMR_HRESP_Pos _U_(11) /**< (GMAC_IMR) HRESP Not OK Position */ +#define GMAC_IMR_HRESP_Msk (_U_(0x1) << GMAC_IMR_HRESP_Pos) /**< (GMAC_IMR) HRESP Not OK Mask */ +#define GMAC_IMR_HRESP(value) (GMAC_IMR_HRESP_Msk & ((value) << GMAC_IMR_HRESP_Pos)) +#define GMAC_IMR_PFNZ_Pos _U_(12) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IMR_PFNZ_Msk (_U_(0x1) << GMAC_IMR_PFNZ_Pos) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IMR_PFNZ(value) (GMAC_IMR_PFNZ_Msk & ((value) << GMAC_IMR_PFNZ_Pos)) +#define GMAC_IMR_PTZ_Pos _U_(13) /**< (GMAC_IMR) Pause Time Zero Position */ +#define GMAC_IMR_PTZ_Msk (_U_(0x1) << GMAC_IMR_PTZ_Pos) /**< (GMAC_IMR) Pause Time Zero Mask */ +#define GMAC_IMR_PTZ(value) (GMAC_IMR_PTZ_Msk & ((value) << GMAC_IMR_PTZ_Pos)) +#define GMAC_IMR_PFTR_Pos _U_(14) /**< (GMAC_IMR) Pause Frame Transmitted Position */ +#define GMAC_IMR_PFTR_Msk (_U_(0x1) << GMAC_IMR_PFTR_Pos) /**< (GMAC_IMR) Pause Frame Transmitted Mask */ +#define GMAC_IMR_PFTR(value) (GMAC_IMR_PFTR_Msk & ((value) << GMAC_IMR_PFTR_Pos)) +#define GMAC_IMR_EXINT_Pos _U_(15) /**< (GMAC_IMR) External Interrupt Position */ +#define GMAC_IMR_EXINT_Msk (_U_(0x1) << GMAC_IMR_EXINT_Pos) /**< (GMAC_IMR) External Interrupt Mask */ +#define GMAC_IMR_EXINT(value) (GMAC_IMR_EXINT_Msk & ((value) << GMAC_IMR_EXINT_Pos)) +#define GMAC_IMR_DRQFR_Pos _U_(18) /**< (GMAC_IMR) PTP Delay Request Frame Received Position */ +#define GMAC_IMR_DRQFR_Msk (_U_(0x1) << GMAC_IMR_DRQFR_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Received Mask */ +#define GMAC_IMR_DRQFR(value) (GMAC_IMR_DRQFR_Msk & ((value) << GMAC_IMR_DRQFR_Pos)) +#define GMAC_IMR_SFR_Pos _U_(19) /**< (GMAC_IMR) PTP Sync Frame Received Position */ +#define GMAC_IMR_SFR_Msk (_U_(0x1) << GMAC_IMR_SFR_Pos) /**< (GMAC_IMR) PTP Sync Frame Received Mask */ +#define GMAC_IMR_SFR(value) (GMAC_IMR_SFR_Msk & ((value) << GMAC_IMR_SFR_Pos)) +#define GMAC_IMR_DRQFT_Pos _U_(20) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IMR_DRQFT_Msk (_U_(0x1) << GMAC_IMR_DRQFT_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IMR_DRQFT(value) (GMAC_IMR_DRQFT_Msk & ((value) << GMAC_IMR_DRQFT_Pos)) +#define GMAC_IMR_SFT_Pos _U_(21) /**< (GMAC_IMR) PTP Sync Frame Transmitted Position */ +#define GMAC_IMR_SFT_Msk (_U_(0x1) << GMAC_IMR_SFT_Pos) /**< (GMAC_IMR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IMR_SFT(value) (GMAC_IMR_SFT_Msk & ((value) << GMAC_IMR_SFT_Pos)) +#define GMAC_IMR_PDRQFR_Pos _U_(22) /**< (GMAC_IMR) PDelay Request Frame Received Position */ +#define GMAC_IMR_PDRQFR_Msk (_U_(0x1) << GMAC_IMR_PDRQFR_Pos) /**< (GMAC_IMR) PDelay Request Frame Received Mask */ +#define GMAC_IMR_PDRQFR(value) (GMAC_IMR_PDRQFR_Msk & ((value) << GMAC_IMR_PDRQFR_Pos)) +#define GMAC_IMR_PDRSFR_Pos _U_(23) /**< (GMAC_IMR) PDelay Response Frame Received Position */ +#define GMAC_IMR_PDRSFR_Msk (_U_(0x1) << GMAC_IMR_PDRSFR_Pos) /**< (GMAC_IMR) PDelay Response Frame Received Mask */ +#define GMAC_IMR_PDRSFR(value) (GMAC_IMR_PDRSFR_Msk & ((value) << GMAC_IMR_PDRSFR_Pos)) +#define GMAC_IMR_PDRQFT_Pos _U_(24) /**< (GMAC_IMR) PDelay Request Frame Transmitted Position */ +#define GMAC_IMR_PDRQFT_Msk (_U_(0x1) << GMAC_IMR_PDRQFT_Pos) /**< (GMAC_IMR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IMR_PDRQFT(value) (GMAC_IMR_PDRQFT_Msk & ((value) << GMAC_IMR_PDRQFT_Pos)) +#define GMAC_IMR_PDRSFT_Pos _U_(25) /**< (GMAC_IMR) PDelay Response Frame Transmitted Position */ +#define GMAC_IMR_PDRSFT_Msk (_U_(0x1) << GMAC_IMR_PDRSFT_Pos) /**< (GMAC_IMR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IMR_PDRSFT(value) (GMAC_IMR_PDRSFT_Msk & ((value) << GMAC_IMR_PDRSFT_Pos)) +#define GMAC_IMR_SRI_Pos _U_(26) /**< (GMAC_IMR) TSU Seconds Register Increment Position */ +#define GMAC_IMR_SRI_Msk (_U_(0x1) << GMAC_IMR_SRI_Pos) /**< (GMAC_IMR) TSU Seconds Register Increment Mask */ +#define GMAC_IMR_SRI(value) (GMAC_IMR_SRI_Msk & ((value) << GMAC_IMR_SRI_Pos)) +#define GMAC_IMR_WOL_Pos _U_(28) /**< (GMAC_IMR) Wake On LAN Position */ +#define GMAC_IMR_WOL_Msk (_U_(0x1) << GMAC_IMR_WOL_Pos) /**< (GMAC_IMR) Wake On LAN Mask */ +#define GMAC_IMR_WOL(value) (GMAC_IMR_WOL_Msk & ((value) << GMAC_IMR_WOL_Pos)) +#define GMAC_IMR_Msk _U_(0x17FCFCFF) /**< (GMAC_IMR) Register Mask */ + + +/* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos _U_(0) /**< (GMAC_MAN) PHY Data Position */ +#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos) /**< (GMAC_MAN) PHY Data Mask */ +#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)) +#define GMAC_MAN_WTN_Pos _U_(16) /**< (GMAC_MAN) Write Ten Position */ +#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos) /**< (GMAC_MAN) Write Ten Mask */ +#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)) +#define GMAC_MAN_REGA_Pos _U_(18) /**< (GMAC_MAN) Register Address Position */ +#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos) /**< (GMAC_MAN) Register Address Mask */ +#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)) +#define GMAC_MAN_PHYA_Pos _U_(23) /**< (GMAC_MAN) PHY Address Position */ +#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos) /**< (GMAC_MAN) PHY Address Mask */ +#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)) +#define GMAC_MAN_OP_Pos _U_(28) /**< (GMAC_MAN) Operation Position */ +#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos) /**< (GMAC_MAN) Operation Mask */ +#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)) +#define GMAC_MAN_CLTTO_Pos _U_(30) /**< (GMAC_MAN) Clause 22 Operation Position */ +#define GMAC_MAN_CLTTO_Msk (_U_(0x1) << GMAC_MAN_CLTTO_Pos) /**< (GMAC_MAN) Clause 22 Operation Mask */ +#define GMAC_MAN_CLTTO(value) (GMAC_MAN_CLTTO_Msk & ((value) << GMAC_MAN_CLTTO_Pos)) +#define GMAC_MAN_WZO_Pos _U_(31) /**< (GMAC_MAN) Write ZERO Position */ +#define GMAC_MAN_WZO_Msk (_U_(0x1) << GMAC_MAN_WZO_Pos) /**< (GMAC_MAN) Write ZERO Mask */ +#define GMAC_MAN_WZO(value) (GMAC_MAN_WZO_Msk & ((value) << GMAC_MAN_WZO_Pos)) +#define GMAC_MAN_Msk _U_(0xFFFFFFFF) /**< (GMAC_MAN) Register Mask */ + + +/* -------- GMAC_RPQ : (GMAC Offset: 0x38) ( R/ 32) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos _U_(0) /**< (GMAC_RPQ) Received Pause Quantum Position */ +#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /**< (GMAC_RPQ) Received Pause Quantum Mask */ +#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos)) +#define GMAC_RPQ_Msk _U_(0x0000FFFF) /**< (GMAC_RPQ) Register Mask */ + + +/* -------- GMAC_TPQ : (GMAC Offset: 0x3C) (R/W 32) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos _U_(0) /**< (GMAC_TPQ) Transmit Pause Quantum Position */ +#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /**< (GMAC_TPQ) Transmit Pause Quantum Mask */ +#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)) +#define GMAC_TPQ_Msk _U_(0x0000FFFF) /**< (GMAC_TPQ) Register Mask */ + + +/* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos _U_(0) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Position */ +#define GMAC_TPSF_TPB1ADR_Msk (_U_(0xFFF) << GMAC_TPSF_TPB1ADR_Pos) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Mask */ +#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)) +#define GMAC_TPSF_ENTXP_Pos _U_(31) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Position */ +#define GMAC_TPSF_ENTXP_Msk (_U_(0x1) << GMAC_TPSF_ENTXP_Pos) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Mask */ +#define GMAC_TPSF_ENTXP(value) (GMAC_TPSF_ENTXP_Msk & ((value) << GMAC_TPSF_ENTXP_Pos)) +#define GMAC_TPSF_Msk _U_(0x80000FFF) /**< (GMAC_TPSF) Register Mask */ + + +/* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos _U_(0) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Position */ +#define GMAC_RPSF_RPB1ADR_Msk (_U_(0xFFF) << GMAC_RPSF_RPB1ADR_Pos) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Mask */ +#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)) +#define GMAC_RPSF_ENRXP_Pos _U_(31) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Position */ +#define GMAC_RPSF_ENRXP_Msk (_U_(0x1) << GMAC_RPSF_ENRXP_Pos) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Mask */ +#define GMAC_RPSF_ENRXP(value) (GMAC_RPSF_ENRXP_Msk & ((value) << GMAC_RPSF_ENRXP_Pos)) +#define GMAC_RPSF_Msk _U_(0x80000FFF) /**< (GMAC_RPSF) Register Mask */ + + +/* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos _U_(0) /**< (GMAC_RJFML) Frame Max Length Position */ +#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos) /**< (GMAC_RJFML) Frame Max Length Mask */ +#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)) +#define GMAC_RJFML_Msk _U_(0x00003FFF) /**< (GMAC_RJFML) Register Mask */ + + +/* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos _U_(0) /**< (GMAC_HRB) Hash Address Position */ +#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /**< (GMAC_HRB) Hash Address Mask */ +#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)) +#define GMAC_HRB_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRB) Register Mask */ + + +/* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos _U_(0) /**< (GMAC_HRT) Hash Address Position */ +#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /**< (GMAC_HRT) Hash Address Mask */ +#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)) +#define GMAC_HRT_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRT) Register Mask */ + + +/* -------- GMAC_TIDM1 : (GMAC Offset: 0xA8) (R/W 32) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos _U_(0) /**< (GMAC_TIDM1) Type ID Match 1 Position */ +#define GMAC_TIDM1_TID_Msk (_U_(0xFFFF) << GMAC_TIDM1_TID_Pos) /**< (GMAC_TIDM1) Type ID Match 1 Mask */ +#define GMAC_TIDM1_TID(value) (GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)) +#define GMAC_TIDM1_ENID1_Pos _U_(31) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM1_ENID1_Msk (_U_(0x1) << GMAC_TIDM1_ENID1_Pos) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM1_ENID1(value) (GMAC_TIDM1_ENID1_Msk & ((value) << GMAC_TIDM1_ENID1_Pos)) +#define GMAC_TIDM1_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM1) Register Mask */ + +#define GMAC_TIDM1_ENID_Pos _U_(31) /**< (GMAC_TIDM1 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM1_ENID_Msk (_U_(0x1) << GMAC_TIDM1_ENID_Pos) /**< (GMAC_TIDM1 Mask) ENID */ +#define GMAC_TIDM1_ENID(value) (GMAC_TIDM1_ENID_Msk & ((value) << GMAC_TIDM1_ENID_Pos)) + +/* -------- GMAC_TIDM2 : (GMAC Offset: 0xAC) (R/W 32) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos _U_(0) /**< (GMAC_TIDM2) Type ID Match 2 Position */ +#define GMAC_TIDM2_TID_Msk (_U_(0xFFFF) << GMAC_TIDM2_TID_Pos) /**< (GMAC_TIDM2) Type ID Match 2 Mask */ +#define GMAC_TIDM2_TID(value) (GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)) +#define GMAC_TIDM2_ENID2_Pos _U_(31) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM2_ENID2_Msk (_U_(0x1) << GMAC_TIDM2_ENID2_Pos) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM2_ENID2(value) (GMAC_TIDM2_ENID2_Msk & ((value) << GMAC_TIDM2_ENID2_Pos)) +#define GMAC_TIDM2_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM2) Register Mask */ + +#define GMAC_TIDM2_ENID_Pos _U_(31) /**< (GMAC_TIDM2 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM2_ENID_Msk (_U_(0x1) << GMAC_TIDM2_ENID_Pos) /**< (GMAC_TIDM2 Mask) ENID */ +#define GMAC_TIDM2_ENID(value) (GMAC_TIDM2_ENID_Msk & ((value) << GMAC_TIDM2_ENID_Pos)) + +/* -------- GMAC_TIDM3 : (GMAC Offset: 0xB0) (R/W 32) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos _U_(0) /**< (GMAC_TIDM3) Type ID Match 3 Position */ +#define GMAC_TIDM3_TID_Msk (_U_(0xFFFF) << GMAC_TIDM3_TID_Pos) /**< (GMAC_TIDM3) Type ID Match 3 Mask */ +#define GMAC_TIDM3_TID(value) (GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)) +#define GMAC_TIDM3_ENID3_Pos _U_(31) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM3_ENID3_Msk (_U_(0x1) << GMAC_TIDM3_ENID3_Pos) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM3_ENID3(value) (GMAC_TIDM3_ENID3_Msk & ((value) << GMAC_TIDM3_ENID3_Pos)) +#define GMAC_TIDM3_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM3) Register Mask */ + +#define GMAC_TIDM3_ENID_Pos _U_(31) /**< (GMAC_TIDM3 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM3_ENID_Msk (_U_(0x1) << GMAC_TIDM3_ENID_Pos) /**< (GMAC_TIDM3 Mask) ENID */ +#define GMAC_TIDM3_ENID(value) (GMAC_TIDM3_ENID_Msk & ((value) << GMAC_TIDM3_ENID_Pos)) + +/* -------- GMAC_TIDM4 : (GMAC Offset: 0xB4) (R/W 32) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos _U_(0) /**< (GMAC_TIDM4) Type ID Match 4 Position */ +#define GMAC_TIDM4_TID_Msk (_U_(0xFFFF) << GMAC_TIDM4_TID_Pos) /**< (GMAC_TIDM4) Type ID Match 4 Mask */ +#define GMAC_TIDM4_TID(value) (GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)) +#define GMAC_TIDM4_ENID4_Pos _U_(31) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM4_ENID4_Msk (_U_(0x1) << GMAC_TIDM4_ENID4_Pos) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM4_ENID4(value) (GMAC_TIDM4_ENID4_Msk & ((value) << GMAC_TIDM4_ENID4_Pos)) +#define GMAC_TIDM4_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM4) Register Mask */ + +#define GMAC_TIDM4_ENID_Pos _U_(31) /**< (GMAC_TIDM4 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM4_ENID_Msk (_U_(0x1) << GMAC_TIDM4_ENID_Pos) /**< (GMAC_TIDM4 Mask) ENID */ +#define GMAC_TIDM4_ENID(value) (GMAC_TIDM4_ENID_Msk & ((value) << GMAC_TIDM4_ENID_Pos)) + +/* -------- GMAC_WOL : (GMAC Offset: 0xB8) (R/W 32) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos _U_(0) /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)) +#define GMAC_WOL_MAG_Pos _U_(16) /**< (GMAC_WOL) Magic Packet Event Enable Position */ +#define GMAC_WOL_MAG_Msk (_U_(0x1) << GMAC_WOL_MAG_Pos) /**< (GMAC_WOL) Magic Packet Event Enable Mask */ +#define GMAC_WOL_MAG(value) (GMAC_WOL_MAG_Msk & ((value) << GMAC_WOL_MAG_Pos)) +#define GMAC_WOL_ARP_Pos _U_(17) /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_ARP_Msk (_U_(0x1) << GMAC_WOL_ARP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_ARP(value) (GMAC_WOL_ARP_Msk & ((value) << GMAC_WOL_ARP_Pos)) +#define GMAC_WOL_SA1_Pos _U_(18) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Position */ +#define GMAC_WOL_SA1_Msk (_U_(0x1) << GMAC_WOL_SA1_Pos) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Mask */ +#define GMAC_WOL_SA1(value) (GMAC_WOL_SA1_Msk & ((value) << GMAC_WOL_SA1_Pos)) +#define GMAC_WOL_MTI_Pos _U_(19) /**< (GMAC_WOL) Multicast Hash Event Enable Position */ +#define GMAC_WOL_MTI_Msk (_U_(0x1) << GMAC_WOL_MTI_Pos) /**< (GMAC_WOL) Multicast Hash Event Enable Mask */ +#define GMAC_WOL_MTI(value) (GMAC_WOL_MTI_Msk & ((value) << GMAC_WOL_MTI_Pos)) +#define GMAC_WOL_Msk _U_(0x000FFFFF) /**< (GMAC_WOL) Register Mask */ + +#define GMAC_WOL_SA_Pos _U_(18) /**< (GMAC_WOL Position) Specific Address Register x Event Enable */ +#define GMAC_WOL_SA_Msk (_U_(0x1) << GMAC_WOL_SA_Pos) /**< (GMAC_WOL Mask) SA */ +#define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & ((value) << GMAC_WOL_SA_Pos)) + +/* -------- GMAC_IPGS : (GMAC Offset: 0xBC) (R/W 32) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos _U_(0) /**< (GMAC_IPGS) Frame Length Position */ +#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos) /**< (GMAC_IPGS) Frame Length Mask */ +#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)) +#define GMAC_IPGS_Msk _U_(0x0000FFFF) /**< (GMAC_IPGS) Register Mask */ + + +/* -------- GMAC_SVLAN : (GMAC Offset: 0xC0) (R/W 32) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos _U_(0) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ +#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ +#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)) +#define GMAC_SVLAN_ESVLAN_Pos _U_(31) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ +#define GMAC_SVLAN_ESVLAN_Msk (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ +#define GMAC_SVLAN_ESVLAN(value) (GMAC_SVLAN_ESVLAN_Msk & ((value) << GMAC_SVLAN_ESVLAN_Pos)) +#define GMAC_SVLAN_Msk _U_(0x8000FFFF) /**< (GMAC_SVLAN) Register Mask */ + + +/* -------- GMAC_TPFCP : (GMAC Offset: 0xC4) (R/W 32) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos _U_(0) /**< (GMAC_TPFCP) Priority Enable Vector Position */ +#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos) /**< (GMAC_TPFCP) Priority Enable Vector Mask */ +#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)) +#define GMAC_TPFCP_PQ_Pos _U_(8) /**< (GMAC_TPFCP) Pause Quantum Position */ +#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos) /**< (GMAC_TPFCP) Pause Quantum Mask */ +#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)) +#define GMAC_TPFCP_Msk _U_(0x0000FFFF) /**< (GMAC_TPFCP) Register Mask */ + + +/* -------- GMAC_SAMB1 : (GMAC Offset: 0xC8) (R/W 32) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos _U_(0) /**< (GMAC_SAMB1) Specific Address 1 Mask Position */ +#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /**< (GMAC_SAMB1) Specific Address 1 Mask Mask */ +#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)) +#define GMAC_SAMB1_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAMB1) Register Mask */ + + +/* -------- GMAC_SAMT1 : (GMAC Offset: 0xCC) (R/W 32) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos _U_(0) /**< (GMAC_SAMT1) Specific Address 1 Mask Position */ +#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /**< (GMAC_SAMT1) Specific Address 1 Mask Mask */ +#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)) +#define GMAC_SAMT1_Msk _U_(0x0000FFFF) /**< (GMAC_SAMT1) Register Mask */ + + +/* -------- GMAC_NSC : (GMAC Offset: 0xDC) (R/W 32) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos _U_(0) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Position */ +#define GMAC_NSC_NANOSEC_Msk (_U_(0x3FFFFF) << GMAC_NSC_NANOSEC_Pos) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Mask */ +#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)) +#define GMAC_NSC_Msk _U_(0x003FFFFF) /**< (GMAC_NSC) Register Mask */ + + +/* -------- GMAC_SCL : (GMAC Offset: 0xE0) (R/W 32) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos _U_(0) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)) +#define GMAC_SCL_Msk _U_(0xFFFFFFFF) /**< (GMAC_SCL) Register Mask */ + + +/* -------- GMAC_SCH : (GMAC Offset: 0xE4) (R/W 32) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos _U_(0) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)) +#define GMAC_SCH_Msk _U_(0x0000FFFF) /**< (GMAC_SCH) Register Mask */ + + +/* -------- GMAC_EFTSH : (GMAC Offset: 0xE8) ( R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos _U_(0) /**< (GMAC_EFTSH) Register Update Position */ +#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /**< (GMAC_EFTSH) Register Update Mask */ +#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos)) +#define GMAC_EFTSH_Msk _U_(0x0000FFFF) /**< (GMAC_EFTSH) Register Mask */ + + +/* -------- GMAC_EFRSH : (GMAC Offset: 0xEC) ( R/ 32) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos _U_(0) /**< (GMAC_EFRSH) Register Update Position */ +#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /**< (GMAC_EFRSH) Register Update Mask */ +#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos)) +#define GMAC_EFRSH_Msk _U_(0x0000FFFF) /**< (GMAC_EFRSH) Register Mask */ + + +/* -------- GMAC_PEFTSH : (GMAC Offset: 0xF0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos _U_(0) /**< (GMAC_PEFTSH) Register Update Position */ +#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /**< (GMAC_PEFTSH) Register Update Mask */ +#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos)) +#define GMAC_PEFTSH_Msk _U_(0x0000FFFF) /**< (GMAC_PEFTSH) Register Mask */ + + +/* -------- GMAC_PEFRSH : (GMAC Offset: 0xF4) ( R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos _U_(0) /**< (GMAC_PEFRSH) Register Update Position */ +#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /**< (GMAC_PEFRSH) Register Update Mask */ +#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos)) +#define GMAC_PEFRSH_Msk _U_(0x0000FFFF) /**< (GMAC_PEFRSH) Register Mask */ + + +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) ( R/ 32) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos _U_(0) /**< (GMAC_OTLO) Transmitted Octets Position */ +#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /**< (GMAC_OTLO) Transmitted Octets Mask */ +#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos)) +#define GMAC_OTLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_OTLO) Register Mask */ + + +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) ( R/ 32) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos _U_(0) /**< (GMAC_OTHI) Transmitted Octets Position */ +#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos) /**< (GMAC_OTHI) Transmitted Octets Mask */ +#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos)) +#define GMAC_OTHI_Msk _U_(0x0000FFFF) /**< (GMAC_OTHI) Register Mask */ + + +/* -------- GMAC_FT : (GMAC Offset: 0x108) ( R/ 32) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos _U_(0) /**< (GMAC_FT) Frames Transmitted without Error Position */ +#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /**< (GMAC_FT) Frames Transmitted without Error Mask */ +#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos)) +#define GMAC_FT_Msk _U_(0xFFFFFFFF) /**< (GMAC_FT) Register Mask */ + + +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) ( R/ 32) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos _U_(0) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ +#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ +#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos)) +#define GMAC_BCFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFT) Register Mask */ + + +/* -------- GMAC_MFT : (GMAC Offset: 0x110) ( R/ 32) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos _U_(0) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Position */ +#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ +#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos)) +#define GMAC_MFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFT) Register Mask */ + + +/* -------- GMAC_PFT : (GMAC Offset: 0x114) ( R/ 32) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos _U_(0) /**< (GMAC_PFT) Pause Frames Transmitted Register Position */ +#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos) /**< (GMAC_PFT) Pause Frames Transmitted Register Mask */ +#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos)) +#define GMAC_PFT_Msk _U_(0x0000FFFF) /**< (GMAC_PFT) Register Mask */ + + +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) ( R/ 32) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos _U_(0) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ +#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ +#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos)) +#define GMAC_BFT64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFT64) Register Mask */ + + +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) ( R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos _U_(0) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos)) +#define GMAC_TBFT127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT127) Register Mask */ + + +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) ( R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos _U_(0) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos)) +#define GMAC_TBFT255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT255) Register Mask */ + + +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) ( R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos _U_(0) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos)) +#define GMAC_TBFT511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT511) Register Mask */ + + +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) ( R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos _U_(0) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos)) +#define GMAC_TBFT1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1023) Register Mask */ + + +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) ( R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos _U_(0) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos)) +#define GMAC_TBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1518) Register Mask */ + + +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) ( R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos _U_(0) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos)) +#define GMAC_GTBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_GTBFT1518) Register Mask */ + + +/* -------- GMAC_TUR : (GMAC Offset: 0x134) ( R/ 32) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos _U_(0) /**< (GMAC_TUR) Transmit Underruns Position */ +#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos) /**< (GMAC_TUR) Transmit Underruns Mask */ +#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos)) +#define GMAC_TUR_Msk _U_(0x000003FF) /**< (GMAC_TUR) Register Mask */ + + +/* -------- GMAC_SCF : (GMAC Offset: 0x138) ( R/ 32) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos _U_(0) /**< (GMAC_SCF) Single Collision Position */ +#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /**< (GMAC_SCF) Single Collision Mask */ +#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos)) +#define GMAC_SCF_Msk _U_(0x0003FFFF) /**< (GMAC_SCF) Register Mask */ + + +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) ( R/ 32) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos _U_(0) /**< (GMAC_MCF) Multiple Collision Position */ +#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /**< (GMAC_MCF) Multiple Collision Mask */ +#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos)) +#define GMAC_MCF_Msk _U_(0x0003FFFF) /**< (GMAC_MCF) Register Mask */ + + +/* -------- GMAC_EC : (GMAC Offset: 0x140) ( R/ 32) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos _U_(0) /**< (GMAC_EC) Excessive Collisions Position */ +#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos) /**< (GMAC_EC) Excessive Collisions Mask */ +#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos)) +#define GMAC_EC_Msk _U_(0x000003FF) /**< (GMAC_EC) Register Mask */ + + +/* -------- GMAC_LC : (GMAC Offset: 0x144) ( R/ 32) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos _U_(0) /**< (GMAC_LC) Late Collisions Position */ +#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos) /**< (GMAC_LC) Late Collisions Mask */ +#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos)) +#define GMAC_LC_Msk _U_(0x000003FF) /**< (GMAC_LC) Register Mask */ + + +/* -------- GMAC_DTF : (GMAC Offset: 0x148) ( R/ 32) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos _U_(0) /**< (GMAC_DTF) Deferred Transmission Position */ +#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /**< (GMAC_DTF) Deferred Transmission Mask */ +#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos)) +#define GMAC_DTF_Msk _U_(0x0003FFFF) /**< (GMAC_DTF) Register Mask */ + + +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) ( R/ 32) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos _U_(0) /**< (GMAC_CSE) Carrier Sense Error Position */ +#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos) /**< (GMAC_CSE) Carrier Sense Error Mask */ +#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos)) +#define GMAC_CSE_Msk _U_(0x000003FF) /**< (GMAC_CSE) Register Mask */ + + +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) ( R/ 32) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos _U_(0) /**< (GMAC_ORLO) Received Octets Position */ +#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /**< (GMAC_ORLO) Received Octets Mask */ +#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos)) +#define GMAC_ORLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_ORLO) Register Mask */ + + +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) ( R/ 32) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos _U_(0) /**< (GMAC_ORHI) Received Octets Position */ +#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos) /**< (GMAC_ORHI) Received Octets Mask */ +#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos)) +#define GMAC_ORHI_Msk _U_(0x0000FFFF) /**< (GMAC_ORHI) Register Mask */ + + +/* -------- GMAC_FR : (GMAC Offset: 0x158) ( R/ 32) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos _U_(0) /**< (GMAC_FR) Frames Received without Error Position */ +#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /**< (GMAC_FR) Frames Received without Error Mask */ +#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos)) +#define GMAC_FR_Msk _U_(0xFFFFFFFF) /**< (GMAC_FR) Register Mask */ + + +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) ( R/ 32) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos _U_(0) /**< (GMAC_BCFR) Broadcast Frames Received without Error Position */ +#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /**< (GMAC_BCFR) Broadcast Frames Received without Error Mask */ +#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos)) +#define GMAC_BCFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFR) Register Mask */ + + +/* -------- GMAC_MFR : (GMAC Offset: 0x160) ( R/ 32) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos _U_(0) /**< (GMAC_MFR) Multicast Frames Received without Error Position */ +#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /**< (GMAC_MFR) Multicast Frames Received without Error Mask */ +#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos)) +#define GMAC_MFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFR) Register Mask */ + + +/* -------- GMAC_PFR : (GMAC Offset: 0x164) ( R/ 32) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos _U_(0) /**< (GMAC_PFR) Pause Frames Received Register Position */ +#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos) /**< (GMAC_PFR) Pause Frames Received Register Mask */ +#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos)) +#define GMAC_PFR_Msk _U_(0x0000FFFF) /**< (GMAC_PFR) Register Mask */ + + +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) ( R/ 32) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos _U_(0) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Position */ +#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ +#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos)) +#define GMAC_BFR64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFR64) Register Mask */ + + +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) ( R/ 32) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos _U_(0) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ +#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ +#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos)) +#define GMAC_TBFR127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR127) Register Mask */ + + +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) ( R/ 32) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos _U_(0) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ +#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ +#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos)) +#define GMAC_TBFR255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR255) Register Mask */ + + +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) ( R/ 32) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos _U_(0) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ +#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ +#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos)) +#define GMAC_TBFR511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR511) Register Mask */ + + +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) ( R/ 32) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos _U_(0) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ +#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos)) +#define GMAC_TBFR1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1023) Register Mask */ + + +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) ( R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos _U_(0) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ +#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos)) +#define GMAC_TBFR1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1518) Register Mask */ + + +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) ( R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos _U_(0) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ +#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ +#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos)) +#define GMAC_TMXBFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_TMXBFR) Register Mask */ + + +/* -------- GMAC_UFR : (GMAC Offset: 0x184) ( R/ 32) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos _U_(0) /**< (GMAC_UFR) Undersize Frames Received Position */ +#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos) /**< (GMAC_UFR) Undersize Frames Received Mask */ +#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos)) +#define GMAC_UFR_Msk _U_(0x000003FF) /**< (GMAC_UFR) Register Mask */ + + +/* -------- GMAC_OFR : (GMAC Offset: 0x188) ( R/ 32) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos _U_(0) /**< (GMAC_OFR) Oversized Frames Received Position */ +#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos) /**< (GMAC_OFR) Oversized Frames Received Mask */ +#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos)) +#define GMAC_OFR_Msk _U_(0x000003FF) /**< (GMAC_OFR) Register Mask */ + + +/* -------- GMAC_JR : (GMAC Offset: 0x18C) ( R/ 32) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos _U_(0) /**< (GMAC_JR) Jabbers Received Position */ +#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos) /**< (GMAC_JR) Jabbers Received Mask */ +#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos)) +#define GMAC_JR_Msk _U_(0x000003FF) /**< (GMAC_JR) Register Mask */ + + +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) ( R/ 32) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos _U_(0) /**< (GMAC_FCSE) Frame Check Sequence Errors Position */ +#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos) /**< (GMAC_FCSE) Frame Check Sequence Errors Mask */ +#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos)) +#define GMAC_FCSE_Msk _U_(0x000003FF) /**< (GMAC_FCSE) Register Mask */ + + +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) ( R/ 32) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos _U_(0) /**< (GMAC_LFFE) Length Field Frame Errors Position */ +#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos) /**< (GMAC_LFFE) Length Field Frame Errors Mask */ +#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos)) +#define GMAC_LFFE_Msk _U_(0x000003FF) /**< (GMAC_LFFE) Register Mask */ + + +/* -------- GMAC_RSE : (GMAC Offset: 0x198) ( R/ 32) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos _U_(0) /**< (GMAC_RSE) Receive Symbol Errors Position */ +#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos) /**< (GMAC_RSE) Receive Symbol Errors Mask */ +#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos)) +#define GMAC_RSE_Msk _U_(0x000003FF) /**< (GMAC_RSE) Register Mask */ + + +/* -------- GMAC_AE : (GMAC Offset: 0x19C) ( R/ 32) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos _U_(0) /**< (GMAC_AE) Alignment Errors Position */ +#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos) /**< (GMAC_AE) Alignment Errors Mask */ +#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos)) +#define GMAC_AE_Msk _U_(0x000003FF) /**< (GMAC_AE) Register Mask */ + + +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) ( R/ 32) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos _U_(0) /**< (GMAC_RRE) Receive Resource Errors Position */ +#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /**< (GMAC_RRE) Receive Resource Errors Mask */ +#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos)) +#define GMAC_RRE_Msk _U_(0x0003FFFF) /**< (GMAC_RRE) Register Mask */ + + +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) ( R/ 32) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos _U_(0) /**< (GMAC_ROE) Receive Overruns Position */ +#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos) /**< (GMAC_ROE) Receive Overruns Mask */ +#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos)) +#define GMAC_ROE_Msk _U_(0x000003FF) /**< (GMAC_ROE) Register Mask */ + + +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) ( R/ 32) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos _U_(0) /**< (GMAC_IHCE) IP Header Checksum Errors Position */ +#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos) /**< (GMAC_IHCE) IP Header Checksum Errors Mask */ +#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos)) +#define GMAC_IHCE_Msk _U_(0x000000FF) /**< (GMAC_IHCE) Register Mask */ + + +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) ( R/ 32) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos _U_(0) /**< (GMAC_TCE) TCP Checksum Errors Position */ +#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos) /**< (GMAC_TCE) TCP Checksum Errors Mask */ +#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos)) +#define GMAC_TCE_Msk _U_(0x000000FF) /**< (GMAC_TCE) Register Mask */ + + +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) ( R/ 32) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos _U_(0) /**< (GMAC_UCE) UDP Checksum Errors Position */ +#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos) /**< (GMAC_UCE) UDP Checksum Errors Mask */ +#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos)) +#define GMAC_UCE_Msk _U_(0x000000FF) /**< (GMAC_UCE) Register Mask */ + + +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos _U_(0) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Position */ +#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Mask */ +#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)) +#define GMAC_TISUBN_Msk _U_(0x0000FFFF) /**< (GMAC_TISUBN) Register Mask */ + + +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos _U_(0) /**< (GMAC_TSH) Timer Count in Seconds Position */ +#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos) /**< (GMAC_TSH) Timer Count in Seconds Mask */ +#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)) +#define GMAC_TSH_Msk _U_(0x0000FFFF) /**< (GMAC_TSH) Register Mask */ + + +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos _U_(0) /**< (GMAC_TSL) Timer Count in Seconds Position */ +#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /**< (GMAC_TSL) Timer Count in Seconds Mask */ +#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)) +#define GMAC_TSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_TSL) Register Mask */ + + +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos _U_(0) /**< (GMAC_TN) Timer Count in Nanoseconds Position */ +#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /**< (GMAC_TN) Timer Count in Nanoseconds Mask */ +#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)) +#define GMAC_TN_Msk _U_(0x3FFFFFFF) /**< (GMAC_TN) Register Mask */ + + +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos _U_(0) /**< (GMAC_TA) Increment/Decrement Position */ +#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /**< (GMAC_TA) Increment/Decrement Mask */ +#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)) +#define GMAC_TA_ADJ_Pos _U_(31) /**< (GMAC_TA) Adjust 1588 Timer Position */ +#define GMAC_TA_ADJ_Msk (_U_(0x1) << GMAC_TA_ADJ_Pos) /**< (GMAC_TA) Adjust 1588 Timer Mask */ +#define GMAC_TA_ADJ(value) (GMAC_TA_ADJ_Msk & ((value) << GMAC_TA_ADJ_Pos)) +#define GMAC_TA_Msk _U_(0xBFFFFFFF) /**< (GMAC_TA) Register Mask */ + + +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos _U_(0) /**< (GMAC_TI) Count Nanoseconds Position */ +#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos) /**< (GMAC_TI) Count Nanoseconds Mask */ +#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)) +#define GMAC_TI_ACNS_Pos _U_(8) /**< (GMAC_TI) Alternative Count Nanoseconds Position */ +#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos) /**< (GMAC_TI) Alternative Count Nanoseconds Mask */ +#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)) +#define GMAC_TI_NIT_Pos _U_(16) /**< (GMAC_TI) Number of Increments Position */ +#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos) /**< (GMAC_TI) Number of Increments Mask */ +#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)) +#define GMAC_TI_Msk _U_(0x00FFFFFF) /**< (GMAC_TI) Register Mask */ + + +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) ( R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos _U_(0) /**< (GMAC_EFTSL) Register Update Position */ +#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /**< (GMAC_EFTSL) Register Update Mask */ +#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos)) +#define GMAC_EFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFTSL) Register Mask */ + + +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) ( R/ 32) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos _U_(0) /**< (GMAC_EFTN) Register Update Position */ +#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /**< (GMAC_EFTN) Register Update Mask */ +#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos)) +#define GMAC_EFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFTN) Register Mask */ + + +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) ( R/ 32) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos _U_(0) /**< (GMAC_EFRSL) Register Update Position */ +#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /**< (GMAC_EFRSL) Register Update Mask */ +#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos)) +#define GMAC_EFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFRSL) Register Mask */ + + +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) ( R/ 32) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos _U_(0) /**< (GMAC_EFRN) Register Update Position */ +#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /**< (GMAC_EFRN) Register Update Mask */ +#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos)) +#define GMAC_EFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFRN) Register Mask */ + + +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos _U_(0) /**< (GMAC_PEFTSL) Register Update Position */ +#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /**< (GMAC_PEFTSL) Register Update Mask */ +#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos)) +#define GMAC_PEFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFTSL) Register Mask */ + + +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) ( R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos _U_(0) /**< (GMAC_PEFTN) Register Update Position */ +#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /**< (GMAC_PEFTN) Register Update Mask */ +#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos)) +#define GMAC_PEFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFTN) Register Mask */ + + +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) ( R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos _U_(0) /**< (GMAC_PEFRSL) Register Update Position */ +#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /**< (GMAC_PEFRSL) Register Update Mask */ +#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos)) +#define GMAC_PEFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFRSL) Register Mask */ + + +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) ( R/ 32) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos _U_(0) /**< (GMAC_PEFRN) Register Update Position */ +#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /**< (GMAC_PEFRN) Register Update Mask */ +#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos)) +#define GMAC_PEFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFRN) Register Mask */ + + +/* -------- GMAC_ISRPQ : (GMAC Offset: 0x3FC) ( R/ 32) Interrupt Status Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_ISRPQ_RCOMP_Pos _U_(1) /**< (GMAC_ISRPQ) Receive Complete Position */ +#define GMAC_ISRPQ_RCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_RCOMP_Pos) /**< (GMAC_ISRPQ) Receive Complete Mask */ +#define GMAC_ISRPQ_RCOMP(value) (GMAC_ISRPQ_RCOMP_Msk & ((value) << GMAC_ISRPQ_RCOMP_Pos)) +#define GMAC_ISRPQ_RXUBR_Pos _U_(2) /**< (GMAC_ISRPQ) RX Used Bit Read Position */ +#define GMAC_ISRPQ_RXUBR_Msk (_U_(0x1) << GMAC_ISRPQ_RXUBR_Pos) /**< (GMAC_ISRPQ) RX Used Bit Read Mask */ +#define GMAC_ISRPQ_RXUBR(value) (GMAC_ISRPQ_RXUBR_Msk & ((value) << GMAC_ISRPQ_RXUBR_Pos)) +#define GMAC_ISRPQ_RLEX_Pos _U_(5) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_ISRPQ_RLEX_Msk (_U_(0x1) << GMAC_ISRPQ_RLEX_Pos) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_ISRPQ_RLEX(value) (GMAC_ISRPQ_RLEX_Msk & ((value) << GMAC_ISRPQ_RLEX_Pos)) +#define GMAC_ISRPQ_TFC_Pos _U_(6) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISRPQ_TFC_Msk (_U_(0x1) << GMAC_ISRPQ_TFC_Pos) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISRPQ_TFC(value) (GMAC_ISRPQ_TFC_Msk & ((value) << GMAC_ISRPQ_TFC_Pos)) +#define GMAC_ISRPQ_TCOMP_Pos _U_(7) /**< (GMAC_ISRPQ) Transmit Complete Position */ +#define GMAC_ISRPQ_TCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_TCOMP_Pos) /**< (GMAC_ISRPQ) Transmit Complete Mask */ +#define GMAC_ISRPQ_TCOMP(value) (GMAC_ISRPQ_TCOMP_Msk & ((value) << GMAC_ISRPQ_TCOMP_Pos)) +#define GMAC_ISRPQ_ROVR_Pos _U_(10) /**< (GMAC_ISRPQ) Receive Overrun Position */ +#define GMAC_ISRPQ_ROVR_Msk (_U_(0x1) << GMAC_ISRPQ_ROVR_Pos) /**< (GMAC_ISRPQ) Receive Overrun Mask */ +#define GMAC_ISRPQ_ROVR(value) (GMAC_ISRPQ_ROVR_Msk & ((value) << GMAC_ISRPQ_ROVR_Pos)) +#define GMAC_ISRPQ_HRESP_Pos _U_(11) /**< (GMAC_ISRPQ) HRESP Not OK Position */ +#define GMAC_ISRPQ_HRESP_Msk (_U_(0x1) << GMAC_ISRPQ_HRESP_Pos) /**< (GMAC_ISRPQ) HRESP Not OK Mask */ +#define GMAC_ISRPQ_HRESP(value) (GMAC_ISRPQ_HRESP_Msk & ((value) << GMAC_ISRPQ_HRESP_Pos)) +#define GMAC_ISRPQ_Msk _U_(0x00000CE6) /**< (GMAC_ISRPQ) Register Mask */ + + +/* -------- GMAC_TBQBAPQ : (GMAC Offset: 0x43C) (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos _U_(2) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQBAPQ_TXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_TBQBAPQ_TXBQBA_Pos) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQBAPQ_TXBQBA(value) (GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)) +#define GMAC_TBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBQBAPQ : (GMAC Offset: 0x47C) (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos _U_(2) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQBAPQ_RXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_RBQBAPQ_RXBQBA_Pos) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQBAPQ_RXBQBA(value) (GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)) +#define GMAC_RBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBSRPQ : (GMAC Offset: 0x49C) (R/W 32) Receive Buffer Size Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_RBSRPQ_RBS_Pos _U_(0) /**< (GMAC_RBSRPQ) Receive Buffer Size Position */ +#define GMAC_RBSRPQ_RBS_Msk (_U_(0xFFFF) << GMAC_RBSRPQ_RBS_Pos) /**< (GMAC_RBSRPQ) Receive Buffer Size Mask */ +#define GMAC_RBSRPQ_RBS(value) (GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)) +#define GMAC_RBSRPQ_Msk _U_(0x0000FFFF) /**< (GMAC_RBSRPQ) Register Mask */ + + +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) (R/W 32) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE_Pos _U_(0) /**< (GMAC_CBSCR) Queue B CBS Enable Position */ +#define GMAC_CBSCR_QBE_Msk (_U_(0x1) << GMAC_CBSCR_QBE_Pos) /**< (GMAC_CBSCR) Queue B CBS Enable Mask */ +#define GMAC_CBSCR_QBE(value) (GMAC_CBSCR_QBE_Msk & ((value) << GMAC_CBSCR_QBE_Pos)) +#define GMAC_CBSCR_QAE_Pos _U_(1) /**< (GMAC_CBSCR) Queue A CBS Enable Position */ +#define GMAC_CBSCR_QAE_Msk (_U_(0x1) << GMAC_CBSCR_QAE_Pos) /**< (GMAC_CBSCR) Queue A CBS Enable Mask */ +#define GMAC_CBSCR_QAE(value) (GMAC_CBSCR_QAE_Msk & ((value) << GMAC_CBSCR_QAE_Pos)) +#define GMAC_CBSCR_Msk _U_(0x00000003) /**< (GMAC_CBSCR) Register Mask */ + + +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos _U_(0) /**< (GMAC_CBSISQA) IdleSlope Position */ +#define GMAC_CBSISQA_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQA_IS_Pos) /**< (GMAC_CBSISQA) IdleSlope Mask */ +#define GMAC_CBSISQA_IS(value) (GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)) +#define GMAC_CBSISQA_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQA) Register Mask */ + + +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos _U_(0) /**< (GMAC_CBSISQB) IdleSlope Position */ +#define GMAC_CBSISQB_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQB_IS_Pos) /**< (GMAC_CBSISQB) IdleSlope Mask */ +#define GMAC_CBSISQB_IS(value) (GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)) +#define GMAC_CBSISQB_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQB) Register Mask */ + + +/* -------- GMAC_ST1RPQ : (GMAC Offset: 0x500) (R/W 32) Screening Type 1 Register Priority Queue (index = 0) 0 -------- */ +#define GMAC_ST1RPQ_QNB_Pos _U_(0) /**< (GMAC_ST1RPQ) Queue Number (0-2) Position */ +#define GMAC_ST1RPQ_QNB_Msk (_U_(0x7) << GMAC_ST1RPQ_QNB_Pos) /**< (GMAC_ST1RPQ) Queue Number (0-2) Mask */ +#define GMAC_ST1RPQ_QNB(value) (GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)) +#define GMAC_ST1RPQ_DSTCM_Pos _U_(4) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Position */ +#define GMAC_ST1RPQ_DSTCM_Msk (_U_(0xFF) << GMAC_ST1RPQ_DSTCM_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Mask */ +#define GMAC_ST1RPQ_DSTCM(value) (GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)) +#define GMAC_ST1RPQ_UDPM_Pos _U_(12) /**< (GMAC_ST1RPQ) UDP Port Match Position */ +#define GMAC_ST1RPQ_UDPM_Msk (_U_(0xFFFF) << GMAC_ST1RPQ_UDPM_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Mask */ +#define GMAC_ST1RPQ_UDPM(value) (GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)) +#define GMAC_ST1RPQ_DSTCE_Pos _U_(28) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Position */ +#define GMAC_ST1RPQ_DSTCE_Msk (_U_(0x1) << GMAC_ST1RPQ_DSTCE_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Mask */ +#define GMAC_ST1RPQ_DSTCE(value) (GMAC_ST1RPQ_DSTCE_Msk & ((value) << GMAC_ST1RPQ_DSTCE_Pos)) +#define GMAC_ST1RPQ_UDPE_Pos _U_(29) /**< (GMAC_ST1RPQ) UDP Port Match Enable Position */ +#define GMAC_ST1RPQ_UDPE_Msk (_U_(0x1) << GMAC_ST1RPQ_UDPE_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Enable Mask */ +#define GMAC_ST1RPQ_UDPE(value) (GMAC_ST1RPQ_UDPE_Msk & ((value) << GMAC_ST1RPQ_UDPE_Pos)) +#define GMAC_ST1RPQ_Msk _U_(0x3FFFFFF7) /**< (GMAC_ST1RPQ) Register Mask */ + + +/* -------- GMAC_ST2RPQ : (GMAC Offset: 0x540) (R/W 32) Screening Type 2 Register Priority Queue (index = 0) 0 -------- */ +#define GMAC_ST2RPQ_QNB_Pos _U_(0) /**< (GMAC_ST2RPQ) Queue Number (0-2) Position */ +#define GMAC_ST2RPQ_QNB_Msk (_U_(0x7) << GMAC_ST2RPQ_QNB_Pos) /**< (GMAC_ST2RPQ) Queue Number (0-2) Mask */ +#define GMAC_ST2RPQ_QNB(value) (GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)) +#define GMAC_ST2RPQ_VLANP_Pos _U_(4) /**< (GMAC_ST2RPQ) VLAN Priority Position */ +#define GMAC_ST2RPQ_VLANP_Msk (_U_(0x7) << GMAC_ST2RPQ_VLANP_Pos) /**< (GMAC_ST2RPQ) VLAN Priority Mask */ +#define GMAC_ST2RPQ_VLANP(value) (GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)) +#define GMAC_ST2RPQ_VLANE_Pos _U_(8) /**< (GMAC_ST2RPQ) VLAN Enable Position */ +#define GMAC_ST2RPQ_VLANE_Msk (_U_(0x1) << GMAC_ST2RPQ_VLANE_Pos) /**< (GMAC_ST2RPQ) VLAN Enable Mask */ +#define GMAC_ST2RPQ_VLANE(value) (GMAC_ST2RPQ_VLANE_Msk & ((value) << GMAC_ST2RPQ_VLANE_Pos)) +#define GMAC_ST2RPQ_I2ETH_Pos _U_(9) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Position */ +#define GMAC_ST2RPQ_I2ETH_Msk (_U_(0x7) << GMAC_ST2RPQ_I2ETH_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Mask */ +#define GMAC_ST2RPQ_I2ETH(value) (GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)) +#define GMAC_ST2RPQ_ETHE_Pos _U_(12) /**< (GMAC_ST2RPQ) EtherType Enable Position */ +#define GMAC_ST2RPQ_ETHE_Msk (_U_(0x1) << GMAC_ST2RPQ_ETHE_Pos) /**< (GMAC_ST2RPQ) EtherType Enable Mask */ +#define GMAC_ST2RPQ_ETHE(value) (GMAC_ST2RPQ_ETHE_Msk & ((value) << GMAC_ST2RPQ_ETHE_Pos)) +#define GMAC_ST2RPQ_COMPA_Pos _U_(13) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPA_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPA_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPA(value) (GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)) +#define GMAC_ST2RPQ_COMPAE_Pos _U_(18) /**< (GMAC_ST2RPQ) Compare A Enable Position */ +#define GMAC_ST2RPQ_COMPAE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPAE_Pos) /**< (GMAC_ST2RPQ) Compare A Enable Mask */ +#define GMAC_ST2RPQ_COMPAE(value) (GMAC_ST2RPQ_COMPAE_Msk & ((value) << GMAC_ST2RPQ_COMPAE_Pos)) +#define GMAC_ST2RPQ_COMPB_Pos _U_(19) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPB_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPB_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPB(value) (GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)) +#define GMAC_ST2RPQ_COMPBE_Pos _U_(24) /**< (GMAC_ST2RPQ) Compare B Enable Position */ +#define GMAC_ST2RPQ_COMPBE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPBE_Pos) /**< (GMAC_ST2RPQ) Compare B Enable Mask */ +#define GMAC_ST2RPQ_COMPBE(value) (GMAC_ST2RPQ_COMPBE_Msk & ((value) << GMAC_ST2RPQ_COMPBE_Pos)) +#define GMAC_ST2RPQ_COMPC_Pos _U_(25) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPC_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPC_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPC(value) (GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)) +#define GMAC_ST2RPQ_COMPCE_Pos _U_(30) /**< (GMAC_ST2RPQ) Compare C Enable Position */ +#define GMAC_ST2RPQ_COMPCE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPCE_Pos) /**< (GMAC_ST2RPQ) Compare C Enable Mask */ +#define GMAC_ST2RPQ_COMPCE(value) (GMAC_ST2RPQ_COMPCE_Msk & ((value) << GMAC_ST2RPQ_COMPCE_Pos)) +#define GMAC_ST2RPQ_Msk _U_(0x7FFFFF77) /**< (GMAC_ST2RPQ) Register Mask */ + + +/* -------- GMAC_IERPQ : (GMAC Offset: 0x5FC) ( /W 32) Interrupt Enable Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_IERPQ_RCOMP_Pos _U_(1) /**< (GMAC_IERPQ) Receive Complete Position */ +#define GMAC_IERPQ_RCOMP_Msk (_U_(0x1) << GMAC_IERPQ_RCOMP_Pos) /**< (GMAC_IERPQ) Receive Complete Mask */ +#define GMAC_IERPQ_RCOMP(value) (GMAC_IERPQ_RCOMP_Msk & ((value) << GMAC_IERPQ_RCOMP_Pos)) +#define GMAC_IERPQ_RXUBR_Pos _U_(2) /**< (GMAC_IERPQ) RX Used Bit Read Position */ +#define GMAC_IERPQ_RXUBR_Msk (_U_(0x1) << GMAC_IERPQ_RXUBR_Pos) /**< (GMAC_IERPQ) RX Used Bit Read Mask */ +#define GMAC_IERPQ_RXUBR(value) (GMAC_IERPQ_RXUBR_Msk & ((value) << GMAC_IERPQ_RXUBR_Pos)) +#define GMAC_IERPQ_RLEX_Pos _U_(5) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IERPQ_RLEX_Msk (_U_(0x1) << GMAC_IERPQ_RLEX_Pos) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IERPQ_RLEX(value) (GMAC_IERPQ_RLEX_Msk & ((value) << GMAC_IERPQ_RLEX_Pos)) +#define GMAC_IERPQ_TFC_Pos _U_(6) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IERPQ_TFC_Msk (_U_(0x1) << GMAC_IERPQ_TFC_Pos) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IERPQ_TFC(value) (GMAC_IERPQ_TFC_Msk & ((value) << GMAC_IERPQ_TFC_Pos)) +#define GMAC_IERPQ_TCOMP_Pos _U_(7) /**< (GMAC_IERPQ) Transmit Complete Position */ +#define GMAC_IERPQ_TCOMP_Msk (_U_(0x1) << GMAC_IERPQ_TCOMP_Pos) /**< (GMAC_IERPQ) Transmit Complete Mask */ +#define GMAC_IERPQ_TCOMP(value) (GMAC_IERPQ_TCOMP_Msk & ((value) << GMAC_IERPQ_TCOMP_Pos)) +#define GMAC_IERPQ_ROVR_Pos _U_(10) /**< (GMAC_IERPQ) Receive Overrun Position */ +#define GMAC_IERPQ_ROVR_Msk (_U_(0x1) << GMAC_IERPQ_ROVR_Pos) /**< (GMAC_IERPQ) Receive Overrun Mask */ +#define GMAC_IERPQ_ROVR(value) (GMAC_IERPQ_ROVR_Msk & ((value) << GMAC_IERPQ_ROVR_Pos)) +#define GMAC_IERPQ_HRESP_Pos _U_(11) /**< (GMAC_IERPQ) HRESP Not OK Position */ +#define GMAC_IERPQ_HRESP_Msk (_U_(0x1) << GMAC_IERPQ_HRESP_Pos) /**< (GMAC_IERPQ) HRESP Not OK Mask */ +#define GMAC_IERPQ_HRESP(value) (GMAC_IERPQ_HRESP_Msk & ((value) << GMAC_IERPQ_HRESP_Pos)) +#define GMAC_IERPQ_Msk _U_(0x00000CE6) /**< (GMAC_IERPQ) Register Mask */ + + +/* -------- GMAC_IDRPQ : (GMAC Offset: 0x61C) ( /W 32) Interrupt Disable Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_IDRPQ_RCOMP_Pos _U_(1) /**< (GMAC_IDRPQ) Receive Complete Position */ +#define GMAC_IDRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_RCOMP_Pos) /**< (GMAC_IDRPQ) Receive Complete Mask */ +#define GMAC_IDRPQ_RCOMP(value) (GMAC_IDRPQ_RCOMP_Msk & ((value) << GMAC_IDRPQ_RCOMP_Pos)) +#define GMAC_IDRPQ_RXUBR_Pos _U_(2) /**< (GMAC_IDRPQ) RX Used Bit Read Position */ +#define GMAC_IDRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IDRPQ_RXUBR_Pos) /**< (GMAC_IDRPQ) RX Used Bit Read Mask */ +#define GMAC_IDRPQ_RXUBR(value) (GMAC_IDRPQ_RXUBR_Msk & ((value) << GMAC_IDRPQ_RXUBR_Pos)) +#define GMAC_IDRPQ_RLEX_Pos _U_(5) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDRPQ_RLEX_Msk (_U_(0x1) << GMAC_IDRPQ_RLEX_Pos) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDRPQ_RLEX(value) (GMAC_IDRPQ_RLEX_Msk & ((value) << GMAC_IDRPQ_RLEX_Pos)) +#define GMAC_IDRPQ_TFC_Pos _U_(6) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDRPQ_TFC_Msk (_U_(0x1) << GMAC_IDRPQ_TFC_Pos) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDRPQ_TFC(value) (GMAC_IDRPQ_TFC_Msk & ((value) << GMAC_IDRPQ_TFC_Pos)) +#define GMAC_IDRPQ_TCOMP_Pos _U_(7) /**< (GMAC_IDRPQ) Transmit Complete Position */ +#define GMAC_IDRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_TCOMP_Pos) /**< (GMAC_IDRPQ) Transmit Complete Mask */ +#define GMAC_IDRPQ_TCOMP(value) (GMAC_IDRPQ_TCOMP_Msk & ((value) << GMAC_IDRPQ_TCOMP_Pos)) +#define GMAC_IDRPQ_ROVR_Pos _U_(10) /**< (GMAC_IDRPQ) Receive Overrun Position */ +#define GMAC_IDRPQ_ROVR_Msk (_U_(0x1) << GMAC_IDRPQ_ROVR_Pos) /**< (GMAC_IDRPQ) Receive Overrun Mask */ +#define GMAC_IDRPQ_ROVR(value) (GMAC_IDRPQ_ROVR_Msk & ((value) << GMAC_IDRPQ_ROVR_Pos)) +#define GMAC_IDRPQ_HRESP_Pos _U_(11) /**< (GMAC_IDRPQ) HRESP Not OK Position */ +#define GMAC_IDRPQ_HRESP_Msk (_U_(0x1) << GMAC_IDRPQ_HRESP_Pos) /**< (GMAC_IDRPQ) HRESP Not OK Mask */ +#define GMAC_IDRPQ_HRESP(value) (GMAC_IDRPQ_HRESP_Msk & ((value) << GMAC_IDRPQ_HRESP_Pos)) +#define GMAC_IDRPQ_Msk _U_(0x00000CE6) /**< (GMAC_IDRPQ) Register Mask */ + + +/* -------- GMAC_IMRPQ : (GMAC Offset: 0x63C) (R/W 32) Interrupt Mask Register Priority Queue (index = 1) 0 -------- */ +#define GMAC_IMRPQ_RCOMP_Pos _U_(1) /**< (GMAC_IMRPQ) Receive Complete Position */ +#define GMAC_IMRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_RCOMP_Pos) /**< (GMAC_IMRPQ) Receive Complete Mask */ +#define GMAC_IMRPQ_RCOMP(value) (GMAC_IMRPQ_RCOMP_Msk & ((value) << GMAC_IMRPQ_RCOMP_Pos)) +#define GMAC_IMRPQ_RXUBR_Pos _U_(2) /**< (GMAC_IMRPQ) RX Used Bit Read Position */ +#define GMAC_IMRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IMRPQ_RXUBR_Pos) /**< (GMAC_IMRPQ) RX Used Bit Read Mask */ +#define GMAC_IMRPQ_RXUBR(value) (GMAC_IMRPQ_RXUBR_Msk & ((value) << GMAC_IMRPQ_RXUBR_Pos)) +#define GMAC_IMRPQ_RLEX_Pos _U_(5) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IMRPQ_RLEX_Msk (_U_(0x1) << GMAC_IMRPQ_RLEX_Pos) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IMRPQ_RLEX(value) (GMAC_IMRPQ_RLEX_Msk & ((value) << GMAC_IMRPQ_RLEX_Pos)) +#define GMAC_IMRPQ_AHB_Pos _U_(6) /**< (GMAC_IMRPQ) AHB Error Position */ +#define GMAC_IMRPQ_AHB_Msk (_U_(0x1) << GMAC_IMRPQ_AHB_Pos) /**< (GMAC_IMRPQ) AHB Error Mask */ +#define GMAC_IMRPQ_AHB(value) (GMAC_IMRPQ_AHB_Msk & ((value) << GMAC_IMRPQ_AHB_Pos)) +#define GMAC_IMRPQ_TCOMP_Pos _U_(7) /**< (GMAC_IMRPQ) Transmit Complete Position */ +#define GMAC_IMRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_TCOMP_Pos) /**< (GMAC_IMRPQ) Transmit Complete Mask */ +#define GMAC_IMRPQ_TCOMP(value) (GMAC_IMRPQ_TCOMP_Msk & ((value) << GMAC_IMRPQ_TCOMP_Pos)) +#define GMAC_IMRPQ_ROVR_Pos _U_(10) /**< (GMAC_IMRPQ) Receive Overrun Position */ +#define GMAC_IMRPQ_ROVR_Msk (_U_(0x1) << GMAC_IMRPQ_ROVR_Pos) /**< (GMAC_IMRPQ) Receive Overrun Mask */ +#define GMAC_IMRPQ_ROVR(value) (GMAC_IMRPQ_ROVR_Msk & ((value) << GMAC_IMRPQ_ROVR_Pos)) +#define GMAC_IMRPQ_HRESP_Pos _U_(11) /**< (GMAC_IMRPQ) HRESP Not OK Position */ +#define GMAC_IMRPQ_HRESP_Msk (_U_(0x1) << GMAC_IMRPQ_HRESP_Pos) /**< (GMAC_IMRPQ) HRESP Not OK Mask */ +#define GMAC_IMRPQ_HRESP(value) (GMAC_IMRPQ_HRESP_Msk & ((value) << GMAC_IMRPQ_HRESP_Pos)) +#define GMAC_IMRPQ_Msk _U_(0x00000CE6) /**< (GMAC_IMRPQ) Register Mask */ + + +/* -------- GMAC_ST2ER : (GMAC Offset: 0x6E0) (R/W 32) Screening Type 2 Ethertype Register (index = 0) 0 -------- */ +#define GMAC_ST2ER_COMPVAL_Pos _U_(0) /**< (GMAC_ST2ER) Ethertype Compare Value Position */ +#define GMAC_ST2ER_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2ER_COMPVAL_Pos) /**< (GMAC_ST2ER) Ethertype Compare Value Mask */ +#define GMAC_ST2ER_COMPVAL(value) (GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)) +#define GMAC_ST2ER_Msk _U_(0x0000FFFF) /**< (GMAC_ST2ER) Register Mask */ + + +/* -------- GMAC_ST2CW00 : (GMAC Offset: 0x700) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 0) -------- */ +#define GMAC_ST2CW00_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW00) Mask Value Position */ +#define GMAC_ST2CW00_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW00_MASKVAL_Pos) /**< (GMAC_ST2CW00) Mask Value Mask */ +#define GMAC_ST2CW00_MASKVAL(value) (GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)) +#define GMAC_ST2CW00_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW00) Compare Value Position */ +#define GMAC_ST2CW00_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW00_COMPVAL_Pos) /**< (GMAC_ST2CW00) Compare Value Mask */ +#define GMAC_ST2CW00_COMPVAL(value) (GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)) +#define GMAC_ST2CW00_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW00) Register Mask */ + + +/* -------- GMAC_ST2CW10 : (GMAC Offset: 0x704) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 0) -------- */ +#define GMAC_ST2CW10_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW10) Offset Value in Bytes Position */ +#define GMAC_ST2CW10_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW10_OFFSVAL_Pos) /**< (GMAC_ST2CW10) Offset Value in Bytes Mask */ +#define GMAC_ST2CW10_OFFSVAL(value) (GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)) +#define GMAC_ST2CW10_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW10) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW10_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW10_OFFSSTRT(value) (GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)) +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW10) Offset from the start of the frame */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW10) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW10_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW10) Offset from the byte after the IP header field */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (GMAC_ST2CW10_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the start of the frame Position */ +#define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (GMAC_ST2CW10_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW10_OFFSSTRT_IP (GMAC_ST2CW10_OFFSSTRT_IP_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (GMAC_ST2CW10_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW10_OFFSSTRT_Pos) /**< (GMAC_ST2CW10) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW10_Msk _U_(0x000001FF) /**< (GMAC_ST2CW10) Register Mask */ + + +/* -------- GMAC_ST2CW01 : (GMAC Offset: 0x708) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 1) -------- */ +#define GMAC_ST2CW01_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW01) Mask Value Position */ +#define GMAC_ST2CW01_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW01_MASKVAL_Pos) /**< (GMAC_ST2CW01) Mask Value Mask */ +#define GMAC_ST2CW01_MASKVAL(value) (GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)) +#define GMAC_ST2CW01_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW01) Compare Value Position */ +#define GMAC_ST2CW01_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW01_COMPVAL_Pos) /**< (GMAC_ST2CW01) Compare Value Mask */ +#define GMAC_ST2CW01_COMPVAL(value) (GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)) +#define GMAC_ST2CW01_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW01) Register Mask */ + + +/* -------- GMAC_ST2CW11 : (GMAC Offset: 0x70C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 1) -------- */ +#define GMAC_ST2CW11_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW11) Offset Value in Bytes Position */ +#define GMAC_ST2CW11_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW11_OFFSVAL_Pos) /**< (GMAC_ST2CW11) Offset Value in Bytes Mask */ +#define GMAC_ST2CW11_OFFSVAL(value) (GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)) +#define GMAC_ST2CW11_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW11) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW11_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW11_OFFSSTRT(value) (GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)) +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW11) Offset from the start of the frame */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW11) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW11_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW11) Offset from the byte after the IP header field */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (GMAC_ST2CW11_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the start of the frame Position */ +#define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (GMAC_ST2CW11_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW11_OFFSSTRT_IP (GMAC_ST2CW11_OFFSSTRT_IP_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (GMAC_ST2CW11_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW11_OFFSSTRT_Pos) /**< (GMAC_ST2CW11) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW11_Msk _U_(0x000001FF) /**< (GMAC_ST2CW11) Register Mask */ + + +/* -------- GMAC_ST2CW02 : (GMAC Offset: 0x710) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 2) -------- */ +#define GMAC_ST2CW02_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW02) Mask Value Position */ +#define GMAC_ST2CW02_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW02_MASKVAL_Pos) /**< (GMAC_ST2CW02) Mask Value Mask */ +#define GMAC_ST2CW02_MASKVAL(value) (GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)) +#define GMAC_ST2CW02_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW02) Compare Value Position */ +#define GMAC_ST2CW02_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW02_COMPVAL_Pos) /**< (GMAC_ST2CW02) Compare Value Mask */ +#define GMAC_ST2CW02_COMPVAL(value) (GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)) +#define GMAC_ST2CW02_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW02) Register Mask */ + + +/* -------- GMAC_ST2CW12 : (GMAC Offset: 0x714) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 2) -------- */ +#define GMAC_ST2CW12_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW12) Offset Value in Bytes Position */ +#define GMAC_ST2CW12_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW12_OFFSVAL_Pos) /**< (GMAC_ST2CW12) Offset Value in Bytes Mask */ +#define GMAC_ST2CW12_OFFSVAL(value) (GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)) +#define GMAC_ST2CW12_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW12) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW12_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW12_OFFSSTRT(value) (GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)) +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW12) Offset from the start of the frame */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW12) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW12_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW12) Offset from the byte after the IP header field */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (GMAC_ST2CW12_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the start of the frame Position */ +#define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (GMAC_ST2CW12_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW12_OFFSSTRT_IP (GMAC_ST2CW12_OFFSSTRT_IP_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (GMAC_ST2CW12_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW12_OFFSSTRT_Pos) /**< (GMAC_ST2CW12) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW12_Msk _U_(0x000001FF) /**< (GMAC_ST2CW12) Register Mask */ + + +/* -------- GMAC_ST2CW03 : (GMAC Offset: 0x718) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 3) -------- */ +#define GMAC_ST2CW03_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW03) Mask Value Position */ +#define GMAC_ST2CW03_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW03_MASKVAL_Pos) /**< (GMAC_ST2CW03) Mask Value Mask */ +#define GMAC_ST2CW03_MASKVAL(value) (GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)) +#define GMAC_ST2CW03_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW03) Compare Value Position */ +#define GMAC_ST2CW03_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW03_COMPVAL_Pos) /**< (GMAC_ST2CW03) Compare Value Mask */ +#define GMAC_ST2CW03_COMPVAL(value) (GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)) +#define GMAC_ST2CW03_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW03) Register Mask */ + + +/* -------- GMAC_ST2CW13 : (GMAC Offset: 0x71C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 3) -------- */ +#define GMAC_ST2CW13_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW13) Offset Value in Bytes Position */ +#define GMAC_ST2CW13_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW13_OFFSVAL_Pos) /**< (GMAC_ST2CW13) Offset Value in Bytes Mask */ +#define GMAC_ST2CW13_OFFSVAL(value) (GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)) +#define GMAC_ST2CW13_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW13) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW13_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW13_OFFSSTRT(value) (GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)) +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW13) Offset from the start of the frame */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW13) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW13_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW13) Offset from the byte after the IP header field */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (GMAC_ST2CW13_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the start of the frame Position */ +#define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (GMAC_ST2CW13_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW13_OFFSSTRT_IP (GMAC_ST2CW13_OFFSSTRT_IP_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (GMAC_ST2CW13_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW13_OFFSSTRT_Pos) /**< (GMAC_ST2CW13) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW13_Msk _U_(0x000001FF) /**< (GMAC_ST2CW13) Register Mask */ + + +/* -------- GMAC_ST2CW04 : (GMAC Offset: 0x720) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 4) -------- */ +#define GMAC_ST2CW04_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW04) Mask Value Position */ +#define GMAC_ST2CW04_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW04_MASKVAL_Pos) /**< (GMAC_ST2CW04) Mask Value Mask */ +#define GMAC_ST2CW04_MASKVAL(value) (GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)) +#define GMAC_ST2CW04_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW04) Compare Value Position */ +#define GMAC_ST2CW04_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW04_COMPVAL_Pos) /**< (GMAC_ST2CW04) Compare Value Mask */ +#define GMAC_ST2CW04_COMPVAL(value) (GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)) +#define GMAC_ST2CW04_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW04) Register Mask */ + + +/* -------- GMAC_ST2CW14 : (GMAC Offset: 0x724) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 4) -------- */ +#define GMAC_ST2CW14_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW14) Offset Value in Bytes Position */ +#define GMAC_ST2CW14_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW14_OFFSVAL_Pos) /**< (GMAC_ST2CW14) Offset Value in Bytes Mask */ +#define GMAC_ST2CW14_OFFSVAL(value) (GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)) +#define GMAC_ST2CW14_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW14) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW14_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW14_OFFSSTRT(value) (GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)) +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW14) Offset from the start of the frame */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW14) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW14_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW14) Offset from the byte after the IP header field */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (GMAC_ST2CW14_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the start of the frame Position */ +#define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (GMAC_ST2CW14_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW14_OFFSSTRT_IP (GMAC_ST2CW14_OFFSSTRT_IP_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (GMAC_ST2CW14_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW14_OFFSSTRT_Pos) /**< (GMAC_ST2CW14) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW14_Msk _U_(0x000001FF) /**< (GMAC_ST2CW14) Register Mask */ + + +/* -------- GMAC_ST2CW05 : (GMAC Offset: 0x728) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 5) -------- */ +#define GMAC_ST2CW05_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW05) Mask Value Position */ +#define GMAC_ST2CW05_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW05_MASKVAL_Pos) /**< (GMAC_ST2CW05) Mask Value Mask */ +#define GMAC_ST2CW05_MASKVAL(value) (GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)) +#define GMAC_ST2CW05_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW05) Compare Value Position */ +#define GMAC_ST2CW05_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW05_COMPVAL_Pos) /**< (GMAC_ST2CW05) Compare Value Mask */ +#define GMAC_ST2CW05_COMPVAL(value) (GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)) +#define GMAC_ST2CW05_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW05) Register Mask */ + + +/* -------- GMAC_ST2CW15 : (GMAC Offset: 0x72C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 5) -------- */ +#define GMAC_ST2CW15_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW15) Offset Value in Bytes Position */ +#define GMAC_ST2CW15_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW15_OFFSVAL_Pos) /**< (GMAC_ST2CW15) Offset Value in Bytes Mask */ +#define GMAC_ST2CW15_OFFSVAL(value) (GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)) +#define GMAC_ST2CW15_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW15) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW15_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW15_OFFSSTRT(value) (GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)) +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW15) Offset from the start of the frame */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW15) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW15_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW15) Offset from the byte after the IP header field */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (GMAC_ST2CW15_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the start of the frame Position */ +#define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (GMAC_ST2CW15_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW15_OFFSSTRT_IP (GMAC_ST2CW15_OFFSSTRT_IP_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (GMAC_ST2CW15_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW15_OFFSSTRT_Pos) /**< (GMAC_ST2CW15) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW15_Msk _U_(0x000001FF) /**< (GMAC_ST2CW15) Register Mask */ + + +/* -------- GMAC_ST2CW06 : (GMAC Offset: 0x730) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 6) -------- */ +#define GMAC_ST2CW06_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW06) Mask Value Position */ +#define GMAC_ST2CW06_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW06_MASKVAL_Pos) /**< (GMAC_ST2CW06) Mask Value Mask */ +#define GMAC_ST2CW06_MASKVAL(value) (GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)) +#define GMAC_ST2CW06_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW06) Compare Value Position */ +#define GMAC_ST2CW06_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW06_COMPVAL_Pos) /**< (GMAC_ST2CW06) Compare Value Mask */ +#define GMAC_ST2CW06_COMPVAL(value) (GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)) +#define GMAC_ST2CW06_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW06) Register Mask */ + + +/* -------- GMAC_ST2CW16 : (GMAC Offset: 0x734) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 6) -------- */ +#define GMAC_ST2CW16_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW16) Offset Value in Bytes Position */ +#define GMAC_ST2CW16_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW16_OFFSVAL_Pos) /**< (GMAC_ST2CW16) Offset Value in Bytes Mask */ +#define GMAC_ST2CW16_OFFSVAL(value) (GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)) +#define GMAC_ST2CW16_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW16) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW16_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW16_OFFSSTRT(value) (GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)) +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW16) Offset from the start of the frame */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW16) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW16_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW16) Offset from the byte after the IP header field */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (GMAC_ST2CW16_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the start of the frame Position */ +#define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (GMAC_ST2CW16_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW16_OFFSSTRT_IP (GMAC_ST2CW16_OFFSSTRT_IP_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (GMAC_ST2CW16_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW16_OFFSSTRT_Pos) /**< (GMAC_ST2CW16) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW16_Msk _U_(0x000001FF) /**< (GMAC_ST2CW16) Register Mask */ + + +/* -------- GMAC_ST2CW07 : (GMAC Offset: 0x738) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 7) -------- */ +#define GMAC_ST2CW07_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW07) Mask Value Position */ +#define GMAC_ST2CW07_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW07_MASKVAL_Pos) /**< (GMAC_ST2CW07) Mask Value Mask */ +#define GMAC_ST2CW07_MASKVAL(value) (GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)) +#define GMAC_ST2CW07_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW07) Compare Value Position */ +#define GMAC_ST2CW07_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW07_COMPVAL_Pos) /**< (GMAC_ST2CW07) Compare Value Mask */ +#define GMAC_ST2CW07_COMPVAL(value) (GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)) +#define GMAC_ST2CW07_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW07) Register Mask */ + + +/* -------- GMAC_ST2CW17 : (GMAC Offset: 0x73C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 7) -------- */ +#define GMAC_ST2CW17_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW17) Offset Value in Bytes Position */ +#define GMAC_ST2CW17_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW17_OFFSVAL_Pos) /**< (GMAC_ST2CW17) Offset Value in Bytes Mask */ +#define GMAC_ST2CW17_OFFSVAL(value) (GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)) +#define GMAC_ST2CW17_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW17) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW17_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW17_OFFSSTRT(value) (GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)) +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW17) Offset from the start of the frame */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW17) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW17_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW17) Offset from the byte after the IP header field */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (GMAC_ST2CW17_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the start of the frame Position */ +#define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (GMAC_ST2CW17_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW17_OFFSSTRT_IP (GMAC_ST2CW17_OFFSSTRT_IP_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (GMAC_ST2CW17_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW17_OFFSSTRT_Pos) /**< (GMAC_ST2CW17) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW17_Msk _U_(0x000001FF) /**< (GMAC_ST2CW17) Register Mask */ + + +/* -------- GMAC_ST2CW08 : (GMAC Offset: 0x740) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 8) -------- */ +#define GMAC_ST2CW08_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW08) Mask Value Position */ +#define GMAC_ST2CW08_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW08_MASKVAL_Pos) /**< (GMAC_ST2CW08) Mask Value Mask */ +#define GMAC_ST2CW08_MASKVAL(value) (GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)) +#define GMAC_ST2CW08_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW08) Compare Value Position */ +#define GMAC_ST2CW08_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW08_COMPVAL_Pos) /**< (GMAC_ST2CW08) Compare Value Mask */ +#define GMAC_ST2CW08_COMPVAL(value) (GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)) +#define GMAC_ST2CW08_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW08) Register Mask */ + + +/* -------- GMAC_ST2CW18 : (GMAC Offset: 0x744) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 8) -------- */ +#define GMAC_ST2CW18_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW18) Offset Value in Bytes Position */ +#define GMAC_ST2CW18_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW18_OFFSVAL_Pos) /**< (GMAC_ST2CW18) Offset Value in Bytes Mask */ +#define GMAC_ST2CW18_OFFSVAL(value) (GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)) +#define GMAC_ST2CW18_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW18) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW18_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW18_OFFSSTRT(value) (GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)) +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW18) Offset from the start of the frame */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW18) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW18_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW18) Offset from the byte after the IP header field */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (GMAC_ST2CW18_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the start of the frame Position */ +#define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (GMAC_ST2CW18_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW18_OFFSSTRT_IP (GMAC_ST2CW18_OFFSSTRT_IP_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (GMAC_ST2CW18_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW18_OFFSSTRT_Pos) /**< (GMAC_ST2CW18) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW18_Msk _U_(0x000001FF) /**< (GMAC_ST2CW18) Register Mask */ + + +/* -------- GMAC_ST2CW09 : (GMAC Offset: 0x748) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 9) -------- */ +#define GMAC_ST2CW09_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW09) Mask Value Position */ +#define GMAC_ST2CW09_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW09_MASKVAL_Pos) /**< (GMAC_ST2CW09) Mask Value Mask */ +#define GMAC_ST2CW09_MASKVAL(value) (GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)) +#define GMAC_ST2CW09_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW09) Compare Value Position */ +#define GMAC_ST2CW09_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW09_COMPVAL_Pos) /**< (GMAC_ST2CW09) Compare Value Mask */ +#define GMAC_ST2CW09_COMPVAL(value) (GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)) +#define GMAC_ST2CW09_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW09) Register Mask */ + + +/* -------- GMAC_ST2CW19 : (GMAC Offset: 0x74C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 9) -------- */ +#define GMAC_ST2CW19_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW19) Offset Value in Bytes Position */ +#define GMAC_ST2CW19_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW19_OFFSVAL_Pos) /**< (GMAC_ST2CW19) Offset Value in Bytes Mask */ +#define GMAC_ST2CW19_OFFSVAL(value) (GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)) +#define GMAC_ST2CW19_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW19) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW19_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW19_OFFSSTRT(value) (GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)) +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW19) Offset from the start of the frame */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW19) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW19_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW19) Offset from the byte after the IP header field */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (GMAC_ST2CW19_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the start of the frame Position */ +#define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (GMAC_ST2CW19_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW19_OFFSSTRT_IP (GMAC_ST2CW19_OFFSSTRT_IP_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (GMAC_ST2CW19_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW19_OFFSSTRT_Pos) /**< (GMAC_ST2CW19) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW19_Msk _U_(0x000001FF) /**< (GMAC_ST2CW19) Register Mask */ + + +/* -------- GMAC_ST2CW010 : (GMAC Offset: 0x750) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 10) -------- */ +#define GMAC_ST2CW010_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW010) Mask Value Position */ +#define GMAC_ST2CW010_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW010_MASKVAL_Pos) /**< (GMAC_ST2CW010) Mask Value Mask */ +#define GMAC_ST2CW010_MASKVAL(value) (GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)) +#define GMAC_ST2CW010_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW010) Compare Value Position */ +#define GMAC_ST2CW010_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW010_COMPVAL_Pos) /**< (GMAC_ST2CW010) Compare Value Mask */ +#define GMAC_ST2CW010_COMPVAL(value) (GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)) +#define GMAC_ST2CW010_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW010) Register Mask */ + + +/* -------- GMAC_ST2CW110 : (GMAC Offset: 0x754) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 10) -------- */ +#define GMAC_ST2CW110_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW110) Offset Value in Bytes Position */ +#define GMAC_ST2CW110_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW110_OFFSVAL_Pos) /**< (GMAC_ST2CW110) Offset Value in Bytes Mask */ +#define GMAC_ST2CW110_OFFSVAL(value) (GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)) +#define GMAC_ST2CW110_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW110) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW110_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW110_OFFSSTRT(value) (GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)) +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW110) Offset from the start of the frame */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW110) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW110_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW110) Offset from the byte after the IP header field */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (GMAC_ST2CW110_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the start of the frame Position */ +#define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (GMAC_ST2CW110_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW110_OFFSSTRT_IP (GMAC_ST2CW110_OFFSSTRT_IP_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (GMAC_ST2CW110_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW110_OFFSSTRT_Pos) /**< (GMAC_ST2CW110) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW110_Msk _U_(0x000001FF) /**< (GMAC_ST2CW110) Register Mask */ + + +/* -------- GMAC_ST2CW011 : (GMAC Offset: 0x758) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 11) -------- */ +#define GMAC_ST2CW011_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW011) Mask Value Position */ +#define GMAC_ST2CW011_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW011_MASKVAL_Pos) /**< (GMAC_ST2CW011) Mask Value Mask */ +#define GMAC_ST2CW011_MASKVAL(value) (GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)) +#define GMAC_ST2CW011_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW011) Compare Value Position */ +#define GMAC_ST2CW011_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW011_COMPVAL_Pos) /**< (GMAC_ST2CW011) Compare Value Mask */ +#define GMAC_ST2CW011_COMPVAL(value) (GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)) +#define GMAC_ST2CW011_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW011) Register Mask */ + + +/* -------- GMAC_ST2CW111 : (GMAC Offset: 0x75C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 11) -------- */ +#define GMAC_ST2CW111_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW111) Offset Value in Bytes Position */ +#define GMAC_ST2CW111_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW111_OFFSVAL_Pos) /**< (GMAC_ST2CW111) Offset Value in Bytes Mask */ +#define GMAC_ST2CW111_OFFSVAL(value) (GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)) +#define GMAC_ST2CW111_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW111) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW111_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW111_OFFSSTRT(value) (GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)) +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW111) Offset from the start of the frame */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW111) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW111_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW111) Offset from the byte after the IP header field */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (GMAC_ST2CW111_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the start of the frame Position */ +#define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (GMAC_ST2CW111_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW111_OFFSSTRT_IP (GMAC_ST2CW111_OFFSSTRT_IP_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (GMAC_ST2CW111_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW111_OFFSSTRT_Pos) /**< (GMAC_ST2CW111) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW111_Msk _U_(0x000001FF) /**< (GMAC_ST2CW111) Register Mask */ + + +/* -------- GMAC_ST2CW012 : (GMAC Offset: 0x760) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 12) -------- */ +#define GMAC_ST2CW012_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW012) Mask Value Position */ +#define GMAC_ST2CW012_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW012_MASKVAL_Pos) /**< (GMAC_ST2CW012) Mask Value Mask */ +#define GMAC_ST2CW012_MASKVAL(value) (GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)) +#define GMAC_ST2CW012_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW012) Compare Value Position */ +#define GMAC_ST2CW012_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW012_COMPVAL_Pos) /**< (GMAC_ST2CW012) Compare Value Mask */ +#define GMAC_ST2CW012_COMPVAL(value) (GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)) +#define GMAC_ST2CW012_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW012) Register Mask */ + + +/* -------- GMAC_ST2CW112 : (GMAC Offset: 0x764) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 12) -------- */ +#define GMAC_ST2CW112_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW112) Offset Value in Bytes Position */ +#define GMAC_ST2CW112_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW112_OFFSVAL_Pos) /**< (GMAC_ST2CW112) Offset Value in Bytes Mask */ +#define GMAC_ST2CW112_OFFSVAL(value) (GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)) +#define GMAC_ST2CW112_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW112) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW112_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW112_OFFSSTRT(value) (GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)) +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW112) Offset from the start of the frame */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW112) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW112_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW112) Offset from the byte after the IP header field */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (GMAC_ST2CW112_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the start of the frame Position */ +#define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (GMAC_ST2CW112_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW112_OFFSSTRT_IP (GMAC_ST2CW112_OFFSSTRT_IP_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (GMAC_ST2CW112_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW112_OFFSSTRT_Pos) /**< (GMAC_ST2CW112) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW112_Msk _U_(0x000001FF) /**< (GMAC_ST2CW112) Register Mask */ + + +/* -------- GMAC_ST2CW013 : (GMAC Offset: 0x768) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 13) -------- */ +#define GMAC_ST2CW013_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW013) Mask Value Position */ +#define GMAC_ST2CW013_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW013_MASKVAL_Pos) /**< (GMAC_ST2CW013) Mask Value Mask */ +#define GMAC_ST2CW013_MASKVAL(value) (GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)) +#define GMAC_ST2CW013_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW013) Compare Value Position */ +#define GMAC_ST2CW013_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW013_COMPVAL_Pos) /**< (GMAC_ST2CW013) Compare Value Mask */ +#define GMAC_ST2CW013_COMPVAL(value) (GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)) +#define GMAC_ST2CW013_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW013) Register Mask */ + + +/* -------- GMAC_ST2CW113 : (GMAC Offset: 0x76C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 13) -------- */ +#define GMAC_ST2CW113_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW113) Offset Value in Bytes Position */ +#define GMAC_ST2CW113_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW113_OFFSVAL_Pos) /**< (GMAC_ST2CW113) Offset Value in Bytes Mask */ +#define GMAC_ST2CW113_OFFSVAL(value) (GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)) +#define GMAC_ST2CW113_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW113) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW113_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW113_OFFSSTRT(value) (GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)) +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW113) Offset from the start of the frame */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW113) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW113_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW113) Offset from the byte after the IP header field */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (GMAC_ST2CW113_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the start of the frame Position */ +#define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (GMAC_ST2CW113_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW113_OFFSSTRT_IP (GMAC_ST2CW113_OFFSSTRT_IP_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (GMAC_ST2CW113_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW113_OFFSSTRT_Pos) /**< (GMAC_ST2CW113) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW113_Msk _U_(0x000001FF) /**< (GMAC_ST2CW113) Register Mask */ + + +/* -------- GMAC_ST2CW014 : (GMAC Offset: 0x770) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 14) -------- */ +#define GMAC_ST2CW014_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW014) Mask Value Position */ +#define GMAC_ST2CW014_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW014_MASKVAL_Pos) /**< (GMAC_ST2CW014) Mask Value Mask */ +#define GMAC_ST2CW014_MASKVAL(value) (GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)) +#define GMAC_ST2CW014_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW014) Compare Value Position */ +#define GMAC_ST2CW014_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW014_COMPVAL_Pos) /**< (GMAC_ST2CW014) Compare Value Mask */ +#define GMAC_ST2CW014_COMPVAL(value) (GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)) +#define GMAC_ST2CW014_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW014) Register Mask */ + + +/* -------- GMAC_ST2CW114 : (GMAC Offset: 0x774) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 14) -------- */ +#define GMAC_ST2CW114_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW114) Offset Value in Bytes Position */ +#define GMAC_ST2CW114_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW114_OFFSVAL_Pos) /**< (GMAC_ST2CW114) Offset Value in Bytes Mask */ +#define GMAC_ST2CW114_OFFSVAL(value) (GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)) +#define GMAC_ST2CW114_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW114) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW114_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW114_OFFSSTRT(value) (GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)) +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW114) Offset from the start of the frame */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW114) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW114_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW114) Offset from the byte after the IP header field */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (GMAC_ST2CW114_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the start of the frame Position */ +#define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (GMAC_ST2CW114_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW114_OFFSSTRT_IP (GMAC_ST2CW114_OFFSSTRT_IP_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (GMAC_ST2CW114_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW114_OFFSSTRT_Pos) /**< (GMAC_ST2CW114) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW114_Msk _U_(0x000001FF) /**< (GMAC_ST2CW114) Register Mask */ + + +/* -------- GMAC_ST2CW015 : (GMAC Offset: 0x778) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 15) -------- */ +#define GMAC_ST2CW015_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW015) Mask Value Position */ +#define GMAC_ST2CW015_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW015_MASKVAL_Pos) /**< (GMAC_ST2CW015) Mask Value Mask */ +#define GMAC_ST2CW015_MASKVAL(value) (GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)) +#define GMAC_ST2CW015_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW015) Compare Value Position */ +#define GMAC_ST2CW015_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW015_COMPVAL_Pos) /**< (GMAC_ST2CW015) Compare Value Mask */ +#define GMAC_ST2CW015_COMPVAL(value) (GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)) +#define GMAC_ST2CW015_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW015) Register Mask */ + + +/* -------- GMAC_ST2CW115 : (GMAC Offset: 0x77C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 15) -------- */ +#define GMAC_ST2CW115_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW115) Offset Value in Bytes Position */ +#define GMAC_ST2CW115_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW115_OFFSVAL_Pos) /**< (GMAC_ST2CW115) Offset Value in Bytes Mask */ +#define GMAC_ST2CW115_OFFSVAL(value) (GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)) +#define GMAC_ST2CW115_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW115) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW115_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW115_OFFSSTRT(value) (GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)) +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW115) Offset from the start of the frame */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW115) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW115_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW115) Offset from the byte after the IP header field */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (GMAC_ST2CW115_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the start of the frame Position */ +#define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (GMAC_ST2CW115_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW115_OFFSSTRT_IP (GMAC_ST2CW115_OFFSSTRT_IP_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (GMAC_ST2CW115_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW115_OFFSSTRT_Pos) /**< (GMAC_ST2CW115) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW115_Msk _U_(0x000001FF) /**< (GMAC_ST2CW115) Register Mask */ + + +/* -------- GMAC_ST2CW016 : (GMAC Offset: 0x780) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 16) -------- */ +#define GMAC_ST2CW016_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW016) Mask Value Position */ +#define GMAC_ST2CW016_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW016_MASKVAL_Pos) /**< (GMAC_ST2CW016) Mask Value Mask */ +#define GMAC_ST2CW016_MASKVAL(value) (GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)) +#define GMAC_ST2CW016_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW016) Compare Value Position */ +#define GMAC_ST2CW016_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW016_COMPVAL_Pos) /**< (GMAC_ST2CW016) Compare Value Mask */ +#define GMAC_ST2CW016_COMPVAL(value) (GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)) +#define GMAC_ST2CW016_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW016) Register Mask */ + + +/* -------- GMAC_ST2CW116 : (GMAC Offset: 0x784) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 16) -------- */ +#define GMAC_ST2CW116_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW116) Offset Value in Bytes Position */ +#define GMAC_ST2CW116_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW116_OFFSVAL_Pos) /**< (GMAC_ST2CW116) Offset Value in Bytes Mask */ +#define GMAC_ST2CW116_OFFSVAL(value) (GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)) +#define GMAC_ST2CW116_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW116) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW116_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW116_OFFSSTRT(value) (GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)) +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW116) Offset from the start of the frame */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW116) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW116_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW116) Offset from the byte after the IP header field */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (GMAC_ST2CW116_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the start of the frame Position */ +#define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (GMAC_ST2CW116_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW116_OFFSSTRT_IP (GMAC_ST2CW116_OFFSSTRT_IP_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (GMAC_ST2CW116_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW116_OFFSSTRT_Pos) /**< (GMAC_ST2CW116) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW116_Msk _U_(0x000001FF) /**< (GMAC_ST2CW116) Register Mask */ + + +/* -------- GMAC_ST2CW017 : (GMAC Offset: 0x788) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 17) -------- */ +#define GMAC_ST2CW017_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW017) Mask Value Position */ +#define GMAC_ST2CW017_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW017_MASKVAL_Pos) /**< (GMAC_ST2CW017) Mask Value Mask */ +#define GMAC_ST2CW017_MASKVAL(value) (GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)) +#define GMAC_ST2CW017_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW017) Compare Value Position */ +#define GMAC_ST2CW017_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW017_COMPVAL_Pos) /**< (GMAC_ST2CW017) Compare Value Mask */ +#define GMAC_ST2CW017_COMPVAL(value) (GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)) +#define GMAC_ST2CW017_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW017) Register Mask */ + + +/* -------- GMAC_ST2CW117 : (GMAC Offset: 0x78C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 17) -------- */ +#define GMAC_ST2CW117_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW117) Offset Value in Bytes Position */ +#define GMAC_ST2CW117_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW117_OFFSVAL_Pos) /**< (GMAC_ST2CW117) Offset Value in Bytes Mask */ +#define GMAC_ST2CW117_OFFSVAL(value) (GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)) +#define GMAC_ST2CW117_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW117) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW117_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW117_OFFSSTRT(value) (GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)) +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW117) Offset from the start of the frame */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW117) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW117_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW117) Offset from the byte after the IP header field */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (GMAC_ST2CW117_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the start of the frame Position */ +#define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (GMAC_ST2CW117_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW117_OFFSSTRT_IP (GMAC_ST2CW117_OFFSSTRT_IP_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (GMAC_ST2CW117_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW117_OFFSSTRT_Pos) /**< (GMAC_ST2CW117) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW117_Msk _U_(0x000001FF) /**< (GMAC_ST2CW117) Register Mask */ + + +/* -------- GMAC_ST2CW018 : (GMAC Offset: 0x790) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 18) -------- */ +#define GMAC_ST2CW018_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW018) Mask Value Position */ +#define GMAC_ST2CW018_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW018_MASKVAL_Pos) /**< (GMAC_ST2CW018) Mask Value Mask */ +#define GMAC_ST2CW018_MASKVAL(value) (GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)) +#define GMAC_ST2CW018_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW018) Compare Value Position */ +#define GMAC_ST2CW018_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW018_COMPVAL_Pos) /**< (GMAC_ST2CW018) Compare Value Mask */ +#define GMAC_ST2CW018_COMPVAL(value) (GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)) +#define GMAC_ST2CW018_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW018) Register Mask */ + + +/* -------- GMAC_ST2CW118 : (GMAC Offset: 0x794) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 18) -------- */ +#define GMAC_ST2CW118_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW118) Offset Value in Bytes Position */ +#define GMAC_ST2CW118_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW118_OFFSVAL_Pos) /**< (GMAC_ST2CW118) Offset Value in Bytes Mask */ +#define GMAC_ST2CW118_OFFSVAL(value) (GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)) +#define GMAC_ST2CW118_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW118) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW118_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW118_OFFSSTRT(value) (GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)) +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW118) Offset from the start of the frame */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW118) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW118_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW118) Offset from the byte after the IP header field */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (GMAC_ST2CW118_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the start of the frame Position */ +#define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (GMAC_ST2CW118_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW118_OFFSSTRT_IP (GMAC_ST2CW118_OFFSSTRT_IP_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (GMAC_ST2CW118_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW118_OFFSSTRT_Pos) /**< (GMAC_ST2CW118) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW118_Msk _U_(0x000001FF) /**< (GMAC_ST2CW118) Register Mask */ + + +/* -------- GMAC_ST2CW019 : (GMAC Offset: 0x798) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 19) -------- */ +#define GMAC_ST2CW019_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW019) Mask Value Position */ +#define GMAC_ST2CW019_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW019_MASKVAL_Pos) /**< (GMAC_ST2CW019) Mask Value Mask */ +#define GMAC_ST2CW019_MASKVAL(value) (GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)) +#define GMAC_ST2CW019_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW019) Compare Value Position */ +#define GMAC_ST2CW019_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW019_COMPVAL_Pos) /**< (GMAC_ST2CW019) Compare Value Mask */ +#define GMAC_ST2CW019_COMPVAL(value) (GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)) +#define GMAC_ST2CW019_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW019) Register Mask */ + + +/* -------- GMAC_ST2CW119 : (GMAC Offset: 0x79C) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 19) -------- */ +#define GMAC_ST2CW119_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW119) Offset Value in Bytes Position */ +#define GMAC_ST2CW119_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW119_OFFSVAL_Pos) /**< (GMAC_ST2CW119) Offset Value in Bytes Mask */ +#define GMAC_ST2CW119_OFFSVAL(value) (GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)) +#define GMAC_ST2CW119_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW119) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW119_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW119_OFFSSTRT(value) (GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)) +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW119) Offset from the start of the frame */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW119) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW119_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW119) Offset from the byte after the IP header field */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (GMAC_ST2CW119_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the start of the frame Position */ +#define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (GMAC_ST2CW119_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW119_OFFSSTRT_IP (GMAC_ST2CW119_OFFSSTRT_IP_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (GMAC_ST2CW119_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW119_OFFSSTRT_Pos) /**< (GMAC_ST2CW119) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW119_Msk _U_(0x000001FF) /**< (GMAC_ST2CW119) Register Mask */ + + +/* -------- GMAC_ST2CW020 : (GMAC Offset: 0x7A0) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 20) -------- */ +#define GMAC_ST2CW020_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW020) Mask Value Position */ +#define GMAC_ST2CW020_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW020_MASKVAL_Pos) /**< (GMAC_ST2CW020) Mask Value Mask */ +#define GMAC_ST2CW020_MASKVAL(value) (GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)) +#define GMAC_ST2CW020_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW020) Compare Value Position */ +#define GMAC_ST2CW020_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW020_COMPVAL_Pos) /**< (GMAC_ST2CW020) Compare Value Mask */ +#define GMAC_ST2CW020_COMPVAL(value) (GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)) +#define GMAC_ST2CW020_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW020) Register Mask */ + + +/* -------- GMAC_ST2CW120 : (GMAC Offset: 0x7A4) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 20) -------- */ +#define GMAC_ST2CW120_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW120) Offset Value in Bytes Position */ +#define GMAC_ST2CW120_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW120_OFFSVAL_Pos) /**< (GMAC_ST2CW120) Offset Value in Bytes Mask */ +#define GMAC_ST2CW120_OFFSVAL(value) (GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)) +#define GMAC_ST2CW120_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW120) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW120_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW120_OFFSSTRT(value) (GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)) +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW120) Offset from the start of the frame */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW120) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW120_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW120) Offset from the byte after the IP header field */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (GMAC_ST2CW120_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the start of the frame Position */ +#define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (GMAC_ST2CW120_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW120_OFFSSTRT_IP (GMAC_ST2CW120_OFFSSTRT_IP_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (GMAC_ST2CW120_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW120_OFFSSTRT_Pos) /**< (GMAC_ST2CW120) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW120_Msk _U_(0x000001FF) /**< (GMAC_ST2CW120) Register Mask */ + + +/* -------- GMAC_ST2CW021 : (GMAC Offset: 0x7A8) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 21) -------- */ +#define GMAC_ST2CW021_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW021) Mask Value Position */ +#define GMAC_ST2CW021_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW021_MASKVAL_Pos) /**< (GMAC_ST2CW021) Mask Value Mask */ +#define GMAC_ST2CW021_MASKVAL(value) (GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)) +#define GMAC_ST2CW021_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW021) Compare Value Position */ +#define GMAC_ST2CW021_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW021_COMPVAL_Pos) /**< (GMAC_ST2CW021) Compare Value Mask */ +#define GMAC_ST2CW021_COMPVAL(value) (GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)) +#define GMAC_ST2CW021_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW021) Register Mask */ + + +/* -------- GMAC_ST2CW121 : (GMAC Offset: 0x7AC) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 21) -------- */ +#define GMAC_ST2CW121_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW121) Offset Value in Bytes Position */ +#define GMAC_ST2CW121_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW121_OFFSVAL_Pos) /**< (GMAC_ST2CW121) Offset Value in Bytes Mask */ +#define GMAC_ST2CW121_OFFSVAL(value) (GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)) +#define GMAC_ST2CW121_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW121) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW121_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW121_OFFSSTRT(value) (GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)) +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW121) Offset from the start of the frame */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW121) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW121_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW121) Offset from the byte after the IP header field */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (GMAC_ST2CW121_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the start of the frame Position */ +#define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (GMAC_ST2CW121_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW121_OFFSSTRT_IP (GMAC_ST2CW121_OFFSSTRT_IP_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (GMAC_ST2CW121_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW121_OFFSSTRT_Pos) /**< (GMAC_ST2CW121) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW121_Msk _U_(0x000001FF) /**< (GMAC_ST2CW121) Register Mask */ + + +/* -------- GMAC_ST2CW022 : (GMAC Offset: 0x7B0) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 22) -------- */ +#define GMAC_ST2CW022_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW022) Mask Value Position */ +#define GMAC_ST2CW022_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW022_MASKVAL_Pos) /**< (GMAC_ST2CW022) Mask Value Mask */ +#define GMAC_ST2CW022_MASKVAL(value) (GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)) +#define GMAC_ST2CW022_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW022) Compare Value Position */ +#define GMAC_ST2CW022_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW022_COMPVAL_Pos) /**< (GMAC_ST2CW022) Compare Value Mask */ +#define GMAC_ST2CW022_COMPVAL(value) (GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)) +#define GMAC_ST2CW022_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW022) Register Mask */ + + +/* -------- GMAC_ST2CW122 : (GMAC Offset: 0x7B4) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 22) -------- */ +#define GMAC_ST2CW122_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW122) Offset Value in Bytes Position */ +#define GMAC_ST2CW122_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW122_OFFSVAL_Pos) /**< (GMAC_ST2CW122) Offset Value in Bytes Mask */ +#define GMAC_ST2CW122_OFFSVAL(value) (GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)) +#define GMAC_ST2CW122_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW122) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW122_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW122_OFFSSTRT(value) (GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)) +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW122) Offset from the start of the frame */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW122) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW122_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW122) Offset from the byte after the IP header field */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (GMAC_ST2CW122_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the start of the frame Position */ +#define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (GMAC_ST2CW122_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW122_OFFSSTRT_IP (GMAC_ST2CW122_OFFSSTRT_IP_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (GMAC_ST2CW122_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW122_OFFSSTRT_Pos) /**< (GMAC_ST2CW122) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW122_Msk _U_(0x000001FF) /**< (GMAC_ST2CW122) Register Mask */ + + +/* -------- GMAC_ST2CW023 : (GMAC Offset: 0x7B8) (R/W 32) Screening Type 2 Compare Word 0 Register (index = 23) -------- */ +#define GMAC_ST2CW023_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW023) Mask Value Position */ +#define GMAC_ST2CW023_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW023_MASKVAL_Pos) /**< (GMAC_ST2CW023) Mask Value Mask */ +#define GMAC_ST2CW023_MASKVAL(value) (GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)) +#define GMAC_ST2CW023_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW023) Compare Value Position */ +#define GMAC_ST2CW023_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW023_COMPVAL_Pos) /**< (GMAC_ST2CW023) Compare Value Mask */ +#define GMAC_ST2CW023_COMPVAL(value) (GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)) +#define GMAC_ST2CW023_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW023) Register Mask */ + + +/* -------- GMAC_ST2CW123 : (GMAC Offset: 0x7BC) (R/W 32) Screening Type 2 Compare Word 1 Register (index = 23) -------- */ +#define GMAC_ST2CW123_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW123) Offset Value in Bytes Position */ +#define GMAC_ST2CW123_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW123_OFFSVAL_Pos) /**< (GMAC_ST2CW123) Offset Value in Bytes Mask */ +#define GMAC_ST2CW123_OFFSVAL(value) (GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)) +#define GMAC_ST2CW123_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW123) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW123_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW123_OFFSSTRT(value) (GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)) +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW123) Offset from the start of the frame */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW123) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW123_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW123) Offset from the byte after the IP header field */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (GMAC_ST2CW123_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the start of the frame Position */ +#define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (GMAC_ST2CW123_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW123_OFFSSTRT_IP (GMAC_ST2CW123_OFFSSTRT_IP_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (GMAC_ST2CW123_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW123_OFFSSTRT_Pos) /**< (GMAC_ST2CW123) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW123_Msk _U_(0x000001FF) /**< (GMAC_ST2CW123) Register Mask */ + + +/** \brief GMAC register offsets definitions */ +#define GMAC_SAB_REG_OFST (0x00) /**< (GMAC_SAB) Specific Address 1 Bottom Register Offset */ +#define GMAC_SAT_REG_OFST (0x04) /**< (GMAC_SAT) Specific Address 1 Top Register Offset */ +#define GMAC_NCR_REG_OFST (0x00) /**< (GMAC_NCR) Network Control Register Offset */ +#define GMAC_NCFGR_REG_OFST (0x04) /**< (GMAC_NCFGR) Network Configuration Register Offset */ +#define GMAC_NSR_REG_OFST (0x08) /**< (GMAC_NSR) Network Status Register Offset */ +#define GMAC_UR_REG_OFST (0x0C) /**< (GMAC_UR) User Register Offset */ +#define GMAC_DCFGR_REG_OFST (0x10) /**< (GMAC_DCFGR) DMA Configuration Register Offset */ +#define GMAC_TSR_REG_OFST (0x14) /**< (GMAC_TSR) Transmit Status Register Offset */ +#define GMAC_RBQB_REG_OFST (0x18) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Register Offset */ +#define GMAC_TBQB_REG_OFST (0x1C) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Register Offset */ +#define GMAC_RSR_REG_OFST (0x20) /**< (GMAC_RSR) Receive Status Register Offset */ +#define GMAC_ISR_REG_OFST (0x24) /**< (GMAC_ISR) Interrupt Status Register Offset */ +#define GMAC_IER_REG_OFST (0x28) /**< (GMAC_IER) Interrupt Enable Register Offset */ +#define GMAC_IDR_REG_OFST (0x2C) /**< (GMAC_IDR) Interrupt Disable Register Offset */ +#define GMAC_IMR_REG_OFST (0x30) /**< (GMAC_IMR) Interrupt Mask Register Offset */ +#define GMAC_MAN_REG_OFST (0x34) /**< (GMAC_MAN) PHY Maintenance Register Offset */ +#define GMAC_RPQ_REG_OFST (0x38) /**< (GMAC_RPQ) Received Pause Quantum Register Offset */ +#define GMAC_TPQ_REG_OFST (0x3C) /**< (GMAC_TPQ) Transmit Pause Quantum Register Offset */ +#define GMAC_TPSF_REG_OFST (0x40) /**< (GMAC_TPSF) TX Partial Store and Forward Register Offset */ +#define GMAC_RPSF_REG_OFST (0x44) /**< (GMAC_RPSF) RX Partial Store and Forward Register Offset */ +#define GMAC_RJFML_REG_OFST (0x48) /**< (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ +#define GMAC_HRB_REG_OFST (0x80) /**< (GMAC_HRB) Hash Register Bottom Offset */ +#define GMAC_HRT_REG_OFST (0x84) /**< (GMAC_HRT) Hash Register Top Offset */ +#define GMAC_TIDM1_REG_OFST (0xA8) /**< (GMAC_TIDM1) Type ID Match 1 Register Offset */ +#define GMAC_TIDM2_REG_OFST (0xAC) /**< (GMAC_TIDM2) Type ID Match 2 Register Offset */ +#define GMAC_TIDM3_REG_OFST (0xB0) /**< (GMAC_TIDM3) Type ID Match 3 Register Offset */ +#define GMAC_TIDM4_REG_OFST (0xB4) /**< (GMAC_TIDM4) Type ID Match 4 Register Offset */ +#define GMAC_WOL_REG_OFST (0xB8) /**< (GMAC_WOL) Wake on LAN Register Offset */ +#define GMAC_IPGS_REG_OFST (0xBC) /**< (GMAC_IPGS) IPG Stretch Register Offset */ +#define GMAC_SVLAN_REG_OFST (0xC0) /**< (GMAC_SVLAN) Stacked VLAN Register Offset */ +#define GMAC_TPFCP_REG_OFST (0xC4) /**< (GMAC_TPFCP) Transmit PFC Pause Register Offset */ +#define GMAC_SAMB1_REG_OFST (0xC8) /**< (GMAC_SAMB1) Specific Address 1 Mask Bottom Register Offset */ +#define GMAC_SAMT1_REG_OFST (0xCC) /**< (GMAC_SAMT1) Specific Address 1 Mask Top Register Offset */ +#define GMAC_NSC_REG_OFST (0xDC) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Register Offset */ +#define GMAC_SCL_REG_OFST (0xE0) /**< (GMAC_SCL) 1588 Timer Second Comparison Low Register Offset */ +#define GMAC_SCH_REG_OFST (0xE4) /**< (GMAC_SCH) 1588 Timer Second Comparison High Register Offset */ +#define GMAC_EFTSH_REG_OFST (0xE8) /**< (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ +#define GMAC_EFRSH_REG_OFST (0xEC) /**< (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ +#define GMAC_PEFTSH_REG_OFST (0xF0) /**< (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ +#define GMAC_PEFRSH_REG_OFST (0xF4) /**< (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ +#define GMAC_OTLO_REG_OFST (0x100) /**< (GMAC_OTLO) Octets Transmitted Low Register Offset */ +#define GMAC_OTHI_REG_OFST (0x104) /**< (GMAC_OTHI) Octets Transmitted High Register Offset */ +#define GMAC_FT_REG_OFST (0x108) /**< (GMAC_FT) Frames Transmitted Register Offset */ +#define GMAC_BCFT_REG_OFST (0x10C) /**< (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ +#define GMAC_MFT_REG_OFST (0x110) /**< (GMAC_MFT) Multicast Frames Transmitted Register Offset */ +#define GMAC_PFT_REG_OFST (0x114) /**< (GMAC_PFT) Pause Frames Transmitted Register Offset */ +#define GMAC_BFT64_REG_OFST (0x118) /**< (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT127_REG_OFST (0x11C) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT255_REG_OFST (0x120) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT511_REG_OFST (0x124) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT1023_REG_OFST (0x128) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT1518_REG_OFST (0x12C) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ +#define GMAC_GTBFT1518_REG_OFST (0x130) /**< (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ +#define GMAC_TUR_REG_OFST (0x134) /**< (GMAC_TUR) Transmit Underruns Register Offset */ +#define GMAC_SCF_REG_OFST (0x138) /**< (GMAC_SCF) Single Collision Frames Register Offset */ +#define GMAC_MCF_REG_OFST (0x13C) /**< (GMAC_MCF) Multiple Collision Frames Register Offset */ +#define GMAC_EC_REG_OFST (0x140) /**< (GMAC_EC) Excessive Collisions Register Offset */ +#define GMAC_LC_REG_OFST (0x144) /**< (GMAC_LC) Late Collisions Register Offset */ +#define GMAC_DTF_REG_OFST (0x148) /**< (GMAC_DTF) Deferred Transmission Frames Register Offset */ +#define GMAC_CSE_REG_OFST (0x14C) /**< (GMAC_CSE) Carrier Sense Errors Register Offset */ +#define GMAC_ORLO_REG_OFST (0x150) /**< (GMAC_ORLO) Octets Received Low Received Register Offset */ +#define GMAC_ORHI_REG_OFST (0x154) /**< (GMAC_ORHI) Octets Received High Received Register Offset */ +#define GMAC_FR_REG_OFST (0x158) /**< (GMAC_FR) Frames Received Register Offset */ +#define GMAC_BCFR_REG_OFST (0x15C) /**< (GMAC_BCFR) Broadcast Frames Received Register Offset */ +#define GMAC_MFR_REG_OFST (0x160) /**< (GMAC_MFR) Multicast Frames Received Register Offset */ +#define GMAC_PFR_REG_OFST (0x164) /**< (GMAC_PFR) Pause Frames Received Register Offset */ +#define GMAC_BFR64_REG_OFST (0x168) /**< (GMAC_BFR64) 64 Byte Frames Received Register Offset */ +#define GMAC_TBFR127_REG_OFST (0x16C) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ +#define GMAC_TBFR255_REG_OFST (0x170) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ +#define GMAC_TBFR511_REG_OFST (0x174) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received Register Offset */ +#define GMAC_TBFR1023_REG_OFST (0x178) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ +#define GMAC_TBFR1518_REG_OFST (0x17C) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ +#define GMAC_TMXBFR_REG_OFST (0x180) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ +#define GMAC_UFR_REG_OFST (0x184) /**< (GMAC_UFR) Undersize Frames Received Register Offset */ +#define GMAC_OFR_REG_OFST (0x188) /**< (GMAC_OFR) Oversize Frames Received Register Offset */ +#define GMAC_JR_REG_OFST (0x18C) /**< (GMAC_JR) Jabbers Received Register Offset */ +#define GMAC_FCSE_REG_OFST (0x190) /**< (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ +#define GMAC_LFFE_REG_OFST (0x194) /**< (GMAC_LFFE) Length Field Frame Errors Register Offset */ +#define GMAC_RSE_REG_OFST (0x198) /**< (GMAC_RSE) Receive Symbol Errors Register Offset */ +#define GMAC_AE_REG_OFST (0x19C) /**< (GMAC_AE) Alignment Errors Register Offset */ +#define GMAC_RRE_REG_OFST (0x1A0) /**< (GMAC_RRE) Receive Resource Errors Register Offset */ +#define GMAC_ROE_REG_OFST (0x1A4) /**< (GMAC_ROE) Receive Overrun Register Offset */ +#define GMAC_IHCE_REG_OFST (0x1A8) /**< (GMAC_IHCE) IP Header Checksum Errors Register Offset */ +#define GMAC_TCE_REG_OFST (0x1AC) /**< (GMAC_TCE) TCP Checksum Errors Register Offset */ +#define GMAC_UCE_REG_OFST (0x1B0) /**< (GMAC_UCE) UDP Checksum Errors Register Offset */ +#define GMAC_TISUBN_REG_OFST (0x1BC) /**< (GMAC_TISUBN) 1588 Timer Increment Sub-nanoseconds Register Offset */ +#define GMAC_TSH_REG_OFST (0x1C0) /**< (GMAC_TSH) 1588 Timer Seconds High Register Offset */ +#define GMAC_TSL_REG_OFST (0x1D0) /**< (GMAC_TSL) 1588 Timer Seconds Low Register Offset */ +#define GMAC_TN_REG_OFST (0x1D4) /**< (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ +#define GMAC_TA_REG_OFST (0x1D8) /**< (GMAC_TA) 1588 Timer Adjust Register Offset */ +#define GMAC_TI_REG_OFST (0x1DC) /**< (GMAC_TI) 1588 Timer Increment Register Offset */ +#define GMAC_EFTSL_REG_OFST (0x1E0) /**< (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ +#define GMAC_EFTN_REG_OFST (0x1E4) /**< (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Register Offset */ +#define GMAC_EFRSL_REG_OFST (0x1E8) /**< (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ +#define GMAC_EFRN_REG_OFST (0x1EC) /**< (GMAC_EFRN) PTP Event Frame Received Nanoseconds Register Offset */ +#define GMAC_PEFTSL_REG_OFST (0x1F0) /**< (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ +#define GMAC_PEFTN_REG_OFST (0x1F4) /**< (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Register Offset */ +#define GMAC_PEFRSL_REG_OFST (0x1F8) /**< (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ +#define GMAC_PEFRN_REG_OFST (0x1FC) /**< (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Register Offset */ +#define GMAC_ISRPQ_REG_OFST (0x3FC) /**< (GMAC_ISRPQ) Interrupt Status Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_TBQBAPQ_REG_OFST (0x43C) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_RBQBAPQ_REG_OFST (0x47C) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_RBSRPQ_REG_OFST (0x49C) /**< (GMAC_RBSRPQ) Receive Buffer Size Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_CBSCR_REG_OFST (0x4BC) /**< (GMAC_CBSCR) Credit-Based Shaping Control Register Offset */ +#define GMAC_CBSISQA_REG_OFST (0x4C0) /**< (GMAC_CBSISQA) Credit-Based Shaping IdleSlope Register for Queue A Offset */ +#define GMAC_CBSISQB_REG_OFST (0x4C4) /**< (GMAC_CBSISQB) Credit-Based Shaping IdleSlope Register for Queue B Offset */ +#define GMAC_ST1RPQ_REG_OFST (0x500) /**< (GMAC_ST1RPQ) Screening Type 1 Register Priority Queue (index = 0) 0 Offset */ +#define GMAC_ST2RPQ_REG_OFST (0x540) /**< (GMAC_ST2RPQ) Screening Type 2 Register Priority Queue (index = 0) 0 Offset */ +#define GMAC_IERPQ_REG_OFST (0x5FC) /**< (GMAC_IERPQ) Interrupt Enable Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_IDRPQ_REG_OFST (0x61C) /**< (GMAC_IDRPQ) Interrupt Disable Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_IMRPQ_REG_OFST (0x63C) /**< (GMAC_IMRPQ) Interrupt Mask Register Priority Queue (index = 1) 0 Offset */ +#define GMAC_ST2ER_REG_OFST (0x6E0) /**< (GMAC_ST2ER) Screening Type 2 Ethertype Register (index = 0) 0 Offset */ +#define GMAC_ST2CW00_REG_OFST (0x700) /**< (GMAC_ST2CW00) Screening Type 2 Compare Word 0 Register (index = 0) Offset */ +#define GMAC_ST2CW10_REG_OFST (0x704) /**< (GMAC_ST2CW10) Screening Type 2 Compare Word 1 Register (index = 0) Offset */ +#define GMAC_ST2CW01_REG_OFST (0x708) /**< (GMAC_ST2CW01) Screening Type 2 Compare Word 0 Register (index = 1) Offset */ +#define GMAC_ST2CW11_REG_OFST (0x70C) /**< (GMAC_ST2CW11) Screening Type 2 Compare Word 1 Register (index = 1) Offset */ +#define GMAC_ST2CW02_REG_OFST (0x710) /**< (GMAC_ST2CW02) Screening Type 2 Compare Word 0 Register (index = 2) Offset */ +#define GMAC_ST2CW12_REG_OFST (0x714) /**< (GMAC_ST2CW12) Screening Type 2 Compare Word 1 Register (index = 2) Offset */ +#define GMAC_ST2CW03_REG_OFST (0x718) /**< (GMAC_ST2CW03) Screening Type 2 Compare Word 0 Register (index = 3) Offset */ +#define GMAC_ST2CW13_REG_OFST (0x71C) /**< (GMAC_ST2CW13) Screening Type 2 Compare Word 1 Register (index = 3) Offset */ +#define GMAC_ST2CW04_REG_OFST (0x720) /**< (GMAC_ST2CW04) Screening Type 2 Compare Word 0 Register (index = 4) Offset */ +#define GMAC_ST2CW14_REG_OFST (0x724) /**< (GMAC_ST2CW14) Screening Type 2 Compare Word 1 Register (index = 4) Offset */ +#define GMAC_ST2CW05_REG_OFST (0x728) /**< (GMAC_ST2CW05) Screening Type 2 Compare Word 0 Register (index = 5) Offset */ +#define GMAC_ST2CW15_REG_OFST (0x72C) /**< (GMAC_ST2CW15) Screening Type 2 Compare Word 1 Register (index = 5) Offset */ +#define GMAC_ST2CW06_REG_OFST (0x730) /**< (GMAC_ST2CW06) Screening Type 2 Compare Word 0 Register (index = 6) Offset */ +#define GMAC_ST2CW16_REG_OFST (0x734) /**< (GMAC_ST2CW16) Screening Type 2 Compare Word 1 Register (index = 6) Offset */ +#define GMAC_ST2CW07_REG_OFST (0x738) /**< (GMAC_ST2CW07) Screening Type 2 Compare Word 0 Register (index = 7) Offset */ +#define GMAC_ST2CW17_REG_OFST (0x73C) /**< (GMAC_ST2CW17) Screening Type 2 Compare Word 1 Register (index = 7) Offset */ +#define GMAC_ST2CW08_REG_OFST (0x740) /**< (GMAC_ST2CW08) Screening Type 2 Compare Word 0 Register (index = 8) Offset */ +#define GMAC_ST2CW18_REG_OFST (0x744) /**< (GMAC_ST2CW18) Screening Type 2 Compare Word 1 Register (index = 8) Offset */ +#define GMAC_ST2CW09_REG_OFST (0x748) /**< (GMAC_ST2CW09) Screening Type 2 Compare Word 0 Register (index = 9) Offset */ +#define GMAC_ST2CW19_REG_OFST (0x74C) /**< (GMAC_ST2CW19) Screening Type 2 Compare Word 1 Register (index = 9) Offset */ +#define GMAC_ST2CW010_REG_OFST (0x750) /**< (GMAC_ST2CW010) Screening Type 2 Compare Word 0 Register (index = 10) Offset */ +#define GMAC_ST2CW110_REG_OFST (0x754) /**< (GMAC_ST2CW110) Screening Type 2 Compare Word 1 Register (index = 10) Offset */ +#define GMAC_ST2CW011_REG_OFST (0x758) /**< (GMAC_ST2CW011) Screening Type 2 Compare Word 0 Register (index = 11) Offset */ +#define GMAC_ST2CW111_REG_OFST (0x75C) /**< (GMAC_ST2CW111) Screening Type 2 Compare Word 1 Register (index = 11) Offset */ +#define GMAC_ST2CW012_REG_OFST (0x760) /**< (GMAC_ST2CW012) Screening Type 2 Compare Word 0 Register (index = 12) Offset */ +#define GMAC_ST2CW112_REG_OFST (0x764) /**< (GMAC_ST2CW112) Screening Type 2 Compare Word 1 Register (index = 12) Offset */ +#define GMAC_ST2CW013_REG_OFST (0x768) /**< (GMAC_ST2CW013) Screening Type 2 Compare Word 0 Register (index = 13) Offset */ +#define GMAC_ST2CW113_REG_OFST (0x76C) /**< (GMAC_ST2CW113) Screening Type 2 Compare Word 1 Register (index = 13) Offset */ +#define GMAC_ST2CW014_REG_OFST (0x770) /**< (GMAC_ST2CW014) Screening Type 2 Compare Word 0 Register (index = 14) Offset */ +#define GMAC_ST2CW114_REG_OFST (0x774) /**< (GMAC_ST2CW114) Screening Type 2 Compare Word 1 Register (index = 14) Offset */ +#define GMAC_ST2CW015_REG_OFST (0x778) /**< (GMAC_ST2CW015) Screening Type 2 Compare Word 0 Register (index = 15) Offset */ +#define GMAC_ST2CW115_REG_OFST (0x77C) /**< (GMAC_ST2CW115) Screening Type 2 Compare Word 1 Register (index = 15) Offset */ +#define GMAC_ST2CW016_REG_OFST (0x780) /**< (GMAC_ST2CW016) Screening Type 2 Compare Word 0 Register (index = 16) Offset */ +#define GMAC_ST2CW116_REG_OFST (0x784) /**< (GMAC_ST2CW116) Screening Type 2 Compare Word 1 Register (index = 16) Offset */ +#define GMAC_ST2CW017_REG_OFST (0x788) /**< (GMAC_ST2CW017) Screening Type 2 Compare Word 0 Register (index = 17) Offset */ +#define GMAC_ST2CW117_REG_OFST (0x78C) /**< (GMAC_ST2CW117) Screening Type 2 Compare Word 1 Register (index = 17) Offset */ +#define GMAC_ST2CW018_REG_OFST (0x790) /**< (GMAC_ST2CW018) Screening Type 2 Compare Word 0 Register (index = 18) Offset */ +#define GMAC_ST2CW118_REG_OFST (0x794) /**< (GMAC_ST2CW118) Screening Type 2 Compare Word 1 Register (index = 18) Offset */ +#define GMAC_ST2CW019_REG_OFST (0x798) /**< (GMAC_ST2CW019) Screening Type 2 Compare Word 0 Register (index = 19) Offset */ +#define GMAC_ST2CW119_REG_OFST (0x79C) /**< (GMAC_ST2CW119) Screening Type 2 Compare Word 1 Register (index = 19) Offset */ +#define GMAC_ST2CW020_REG_OFST (0x7A0) /**< (GMAC_ST2CW020) Screening Type 2 Compare Word 0 Register (index = 20) Offset */ +#define GMAC_ST2CW120_REG_OFST (0x7A4) /**< (GMAC_ST2CW120) Screening Type 2 Compare Word 1 Register (index = 20) Offset */ +#define GMAC_ST2CW021_REG_OFST (0x7A8) /**< (GMAC_ST2CW021) Screening Type 2 Compare Word 0 Register (index = 21) Offset */ +#define GMAC_ST2CW121_REG_OFST (0x7AC) /**< (GMAC_ST2CW121) Screening Type 2 Compare Word 1 Register (index = 21) Offset */ +#define GMAC_ST2CW022_REG_OFST (0x7B0) /**< (GMAC_ST2CW022) Screening Type 2 Compare Word 0 Register (index = 22) Offset */ +#define GMAC_ST2CW122_REG_OFST (0x7B4) /**< (GMAC_ST2CW122) Screening Type 2 Compare Word 1 Register (index = 22) Offset */ +#define GMAC_ST2CW023_REG_OFST (0x7B8) /**< (GMAC_ST2CW023) Screening Type 2 Compare Word 0 Register (index = 23) Offset */ +#define GMAC_ST2CW123_REG_OFST (0x7BC) /**< (GMAC_ST2CW123) Screening Type 2 Compare Word 1 Register (index = 23) Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GMAC_SA register API structure */ +typedef struct +{ + __IO uint32_t GMAC_SAB; /**< Offset: 0x00 (R/W 32) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< Offset: 0x04 (R/W 32) Specific Address 1 Top Register */ +} gmac_sa_registers_t; + +#define GMAC_SA_NUMBER _U_(4) + +/** \brief GMAC register API structure */ +typedef struct +{ + __IO uint32_t GMAC_NCR; /**< Offset: 0x00 (R/W 32) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< Offset: 0x04 (R/W 32) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< Offset: 0x08 (R/ 32) Network Status Register */ + __IO uint32_t GMAC_UR; /**< Offset: 0x0C (R/W 32) User Register */ + __IO uint32_t GMAC_DCFGR; /**< Offset: 0x10 (R/W 32) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< Offset: 0x14 (R/W 32) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< Offset: 0x20 (R/W 32) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< Offset: 0x24 (R/ 32) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< Offset: 0x28 ( /W 32) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< Offset: 0x2C ( /W 32) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< Offset: 0x30 (R/W 32) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< Offset: 0x34 (R/W 32) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< Offset: 0x38 (R/ 32) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< Offset: 0x40 (R/W 32) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< Offset: 0x44 (R/W 32) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ + __I uint8_t Reserved1[0x34]; + __IO uint32_t GMAC_HRB; /**< Offset: 0x80 (R/W 32) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< Offset: 0x84 (R/W 32) Hash Register Top */ + gmac_sa_registers_t GMAC_SA[GMAC_SA_NUMBER]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_TIDM1; /**< Offset: 0xA8 (R/W 32) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< Offset: 0xAC (R/W 32) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< Offset: 0xB0 (R/W 32) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< Offset: 0xB4 (R/W 32) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< Offset: 0xB8 (R/W 32) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< Offset: 0xBC (R/W 32) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< Offset: 0xC0 (R/W 32) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< Offset: 0xCC (R/W 32) Specific Address 1 Mask Top Register */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t GMAC_NSC; /**< Offset: 0xDC (R/W 32) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< Offset: 0xE0 (R/W 32) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< Offset: 0xE4 (R/W 32) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ + __I uint8_t Reserved3[0x08]; + __I uint32_t GMAC_OTLO; /**< Offset: 0x100 (R/ 32) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< Offset: 0x104 (R/ 32) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< Offset: 0x108 (R/ 32) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< Offset: 0x134 (R/ 32) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< Offset: 0x138 (R/ 32) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< Offset: 0x140 (R/ 32) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< Offset: 0x144 (R/ 32) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< Offset: 0x150 (R/ 32) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< Offset: 0x154 (R/ 32) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< Offset: 0x158 (R/ 32) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< Offset: 0x160 (R/ 32) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< Offset: 0x164 (R/ 32) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< Offset: 0x174 (R/ 32) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< Offset: 0x184 (R/ 32) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< Offset: 0x188 (R/ 32) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< Offset: 0x18C (R/ 32) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< Offset: 0x19C (R/ 32) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< Offset: 0x1A4 (R/ 32) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ + __I uint8_t Reserved4[0x08]; + __IO uint32_t GMAC_TISUBN; /**< Offset: 0x1BC (R/W 32) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High Register */ + __I uint8_t Reserved5[0x0C]; + __IO uint32_t GMAC_TSL; /**< Offset: 0x1D0 (R/W 32) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint8_t Reserved6[0x1FC]; + __I uint32_t GMAC_ISRPQ[2]; /**< Offset: 0x3FC (R/ 32) Interrupt Status Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved7[0x38]; + __IO uint32_t GMAC_TBQBAPQ[2]; /**< Offset: 0x43C (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved8[0x38]; + __IO uint32_t GMAC_RBQBAPQ[2]; /**< Offset: 0x47C (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved9[0x18]; + __IO uint32_t GMAC_RBSRPQ[2]; /**< Offset: 0x49C (R/W 32) Receive Buffer Size Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved10[0x18]; + __IO uint32_t GMAC_CBSCR; /**< Offset: 0x4BC (R/W 32) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< Offset: 0x4C0 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< Offset: 0x4C4 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint8_t Reserved11[0x38]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< Offset: 0x500 (R/W 32) Screening Type 1 Register Priority Queue (index = 0) 0 */ + __I uint8_t Reserved12[0x30]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< Offset: 0x540 (R/W 32) Screening Type 2 Register Priority Queue (index = 0) 0 */ + __I uint8_t Reserved13[0x9C]; + __O uint32_t GMAC_IERPQ[2]; /**< Offset: 0x5FC ( /W 32) Interrupt Enable Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved14[0x18]; + __O uint32_t GMAC_IDRPQ[2]; /**< Offset: 0x61C ( /W 32) Interrupt Disable Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved15[0x18]; + __IO uint32_t GMAC_IMRPQ[2]; /**< Offset: 0x63C (R/W 32) Interrupt Mask Register Priority Queue (index = 1) 0 */ + __I uint8_t Reserved16[0x9C]; + __IO uint32_t GMAC_ST2ER[4]; /**< Offset: 0x6E0 (R/W 32) Screening Type 2 Ethertype Register (index = 0) 0 */ + __I uint8_t Reserved17[0x10]; + __IO uint32_t GMAC_ST2CW00; /**< Offset: 0x700 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW10; /**< Offset: 0x704 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 0) */ + __IO uint32_t GMAC_ST2CW01; /**< Offset: 0x708 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW11; /**< Offset: 0x70C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 1) */ + __IO uint32_t GMAC_ST2CW02; /**< Offset: 0x710 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW12; /**< Offset: 0x714 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 2) */ + __IO uint32_t GMAC_ST2CW03; /**< Offset: 0x718 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW13; /**< Offset: 0x71C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 3) */ + __IO uint32_t GMAC_ST2CW04; /**< Offset: 0x720 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW14; /**< Offset: 0x724 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 4) */ + __IO uint32_t GMAC_ST2CW05; /**< Offset: 0x728 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW15; /**< Offset: 0x72C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 5) */ + __IO uint32_t GMAC_ST2CW06; /**< Offset: 0x730 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW16; /**< Offset: 0x734 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 6) */ + __IO uint32_t GMAC_ST2CW07; /**< Offset: 0x738 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW17; /**< Offset: 0x73C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 7) */ + __IO uint32_t GMAC_ST2CW08; /**< Offset: 0x740 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW18; /**< Offset: 0x744 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 8) */ + __IO uint32_t GMAC_ST2CW09; /**< Offset: 0x748 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW19; /**< Offset: 0x74C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 9) */ + __IO uint32_t GMAC_ST2CW010; /**< Offset: 0x750 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW110; /**< Offset: 0x754 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 10) */ + __IO uint32_t GMAC_ST2CW011; /**< Offset: 0x758 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW111; /**< Offset: 0x75C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 11) */ + __IO uint32_t GMAC_ST2CW012; /**< Offset: 0x760 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW112; /**< Offset: 0x764 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 12) */ + __IO uint32_t GMAC_ST2CW013; /**< Offset: 0x768 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW113; /**< Offset: 0x76C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 13) */ + __IO uint32_t GMAC_ST2CW014; /**< Offset: 0x770 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW114; /**< Offset: 0x774 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 14) */ + __IO uint32_t GMAC_ST2CW015; /**< Offset: 0x778 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW115; /**< Offset: 0x77C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 15) */ + __IO uint32_t GMAC_ST2CW016; /**< Offset: 0x780 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW116; /**< Offset: 0x784 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 16) */ + __IO uint32_t GMAC_ST2CW017; /**< Offset: 0x788 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW117; /**< Offset: 0x78C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 17) */ + __IO uint32_t GMAC_ST2CW018; /**< Offset: 0x790 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW118; /**< Offset: 0x794 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 18) */ + __IO uint32_t GMAC_ST2CW019; /**< Offset: 0x798 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW119; /**< Offset: 0x79C (R/W 32) Screening Type 2 Compare Word 1 Register (index = 19) */ + __IO uint32_t GMAC_ST2CW020; /**< Offset: 0x7A0 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW120; /**< Offset: 0x7A4 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 20) */ + __IO uint32_t GMAC_ST2CW021; /**< Offset: 0x7A8 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW121; /**< Offset: 0x7AC (R/W 32) Screening Type 2 Compare Word 1 Register (index = 21) */ + __IO uint32_t GMAC_ST2CW022; /**< Offset: 0x7B0 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW122; /**< Offset: 0x7B4 (R/W 32) Screening Type 2 Compare Word 1 Register (index = 22) */ + __IO uint32_t GMAC_ST2CW023; /**< Offset: 0x7B8 (R/W 32) Screening Type 2 Compare Word 0 Register (index = 23) */ + __IO uint32_t GMAC_ST2CW123; /**< Offset: 0x7BC (R/W 32) Screening Type 2 Compare Word 1 Register (index = 23) */ +} gmac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_GMAC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/gpbr.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/gpbr.h new file mode 100644 index 00000000..10f4ec36 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/gpbr.h @@ -0,0 +1,50 @@ +/** + * \brief Component description for GPBR + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_GPBR_COMPONENT_H_ +#define _SAME70_GPBR_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR GPBR */ +/* ************************************************************************** */ + +/* -------- SYS_GPBR : (GPBR Offset: 0x00) (R/W 32) General Purpose Backup Register 0 -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos _U_(0) /**< (SYS_GPBR) Value of GPBR x Position */ +#define SYS_GPBR_GPBR_VALUE_Msk (_U_(0xFFFFFFFF) << SYS_GPBR_GPBR_VALUE_Pos) /**< (SYS_GPBR) Value of GPBR x Mask */ +#define SYS_GPBR_GPBR_VALUE(value) (SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)) +#define SYS_GPBR_Msk _U_(0xFFFFFFFF) /**< (SYS_GPBR) Register Mask */ + + +/** \brief GPBR register offsets definitions */ +#define SYS_GPBR_REG_OFST (0x00) /**< (SYS_GPBR) General Purpose Backup Register 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GPBR register API structure */ +typedef struct +{ + __IO uint32_t SYS_GPBR[8]; /**< Offset: 0x00 (R/W 32) General Purpose Backup Register 0 */ +} gpbr_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_GPBR_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/hsmci.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/hsmci.h new file mode 100644 index 00000000..16fcc42d --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/hsmci.h @@ -0,0 +1,704 @@ +/** + * \brief Component description for HSMCI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_HSMCI_COMPONENT_H_ +#define _SAME70_HSMCI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR HSMCI */ +/* ************************************************************************** */ + +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) ( /W 32) Control Register -------- */ +#define HSMCI_CR_MCIEN_Pos _U_(0) /**< (HSMCI_CR) Multi-Media Interface Enable Position */ +#define HSMCI_CR_MCIEN_Msk (_U_(0x1) << HSMCI_CR_MCIEN_Pos) /**< (HSMCI_CR) Multi-Media Interface Enable Mask */ +#define HSMCI_CR_MCIEN(value) (HSMCI_CR_MCIEN_Msk & ((value) << HSMCI_CR_MCIEN_Pos)) +#define HSMCI_CR_MCIDIS_Pos _U_(1) /**< (HSMCI_CR) Multi-Media Interface Disable Position */ +#define HSMCI_CR_MCIDIS_Msk (_U_(0x1) << HSMCI_CR_MCIDIS_Pos) /**< (HSMCI_CR) Multi-Media Interface Disable Mask */ +#define HSMCI_CR_MCIDIS(value) (HSMCI_CR_MCIDIS_Msk & ((value) << HSMCI_CR_MCIDIS_Pos)) +#define HSMCI_CR_PWSEN_Pos _U_(2) /**< (HSMCI_CR) Power Save Mode Enable Position */ +#define HSMCI_CR_PWSEN_Msk (_U_(0x1) << HSMCI_CR_PWSEN_Pos) /**< (HSMCI_CR) Power Save Mode Enable Mask */ +#define HSMCI_CR_PWSEN(value) (HSMCI_CR_PWSEN_Msk & ((value) << HSMCI_CR_PWSEN_Pos)) +#define HSMCI_CR_PWSDIS_Pos _U_(3) /**< (HSMCI_CR) Power Save Mode Disable Position */ +#define HSMCI_CR_PWSDIS_Msk (_U_(0x1) << HSMCI_CR_PWSDIS_Pos) /**< (HSMCI_CR) Power Save Mode Disable Mask */ +#define HSMCI_CR_PWSDIS(value) (HSMCI_CR_PWSDIS_Msk & ((value) << HSMCI_CR_PWSDIS_Pos)) +#define HSMCI_CR_SWRST_Pos _U_(7) /**< (HSMCI_CR) Software Reset Position */ +#define HSMCI_CR_SWRST_Msk (_U_(0x1) << HSMCI_CR_SWRST_Pos) /**< (HSMCI_CR) Software Reset Mask */ +#define HSMCI_CR_SWRST(value) (HSMCI_CR_SWRST_Msk & ((value) << HSMCI_CR_SWRST_Pos)) +#define HSMCI_CR_Msk _U_(0x0000008F) /**< (HSMCI_CR) Register Mask */ + + +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos _U_(0) /**< (HSMCI_MR) Clock Divider Position */ +#define HSMCI_MR_CLKDIV_Msk (_U_(0xFF) << HSMCI_MR_CLKDIV_Pos) /**< (HSMCI_MR) Clock Divider Mask */ +#define HSMCI_MR_CLKDIV(value) (HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)) +#define HSMCI_MR_PWSDIV_Pos _U_(8) /**< (HSMCI_MR) Power Saving Divider Position */ +#define HSMCI_MR_PWSDIV_Msk (_U_(0x7) << HSMCI_MR_PWSDIV_Pos) /**< (HSMCI_MR) Power Saving Divider Mask */ +#define HSMCI_MR_PWSDIV(value) (HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)) +#define HSMCI_MR_RDPROOF_Pos _U_(11) /**< (HSMCI_MR) Read Proof Enable Position */ +#define HSMCI_MR_RDPROOF_Msk (_U_(0x1) << HSMCI_MR_RDPROOF_Pos) /**< (HSMCI_MR) Read Proof Enable Mask */ +#define HSMCI_MR_RDPROOF(value) (HSMCI_MR_RDPROOF_Msk & ((value) << HSMCI_MR_RDPROOF_Pos)) +#define HSMCI_MR_WRPROOF_Pos _U_(12) /**< (HSMCI_MR) Write Proof Enable Position */ +#define HSMCI_MR_WRPROOF_Msk (_U_(0x1) << HSMCI_MR_WRPROOF_Pos) /**< (HSMCI_MR) Write Proof Enable Mask */ +#define HSMCI_MR_WRPROOF(value) (HSMCI_MR_WRPROOF_Msk & ((value) << HSMCI_MR_WRPROOF_Pos)) +#define HSMCI_MR_FBYTE_Pos _U_(13) /**< (HSMCI_MR) Force Byte Transfer Position */ +#define HSMCI_MR_FBYTE_Msk (_U_(0x1) << HSMCI_MR_FBYTE_Pos) /**< (HSMCI_MR) Force Byte Transfer Mask */ +#define HSMCI_MR_FBYTE(value) (HSMCI_MR_FBYTE_Msk & ((value) << HSMCI_MR_FBYTE_Pos)) +#define HSMCI_MR_PADV_Pos _U_(14) /**< (HSMCI_MR) Padding Value Position */ +#define HSMCI_MR_PADV_Msk (_U_(0x1) << HSMCI_MR_PADV_Pos) /**< (HSMCI_MR) Padding Value Mask */ +#define HSMCI_MR_PADV(value) (HSMCI_MR_PADV_Msk & ((value) << HSMCI_MR_PADV_Pos)) +#define HSMCI_MR_CLKODD_Pos _U_(16) /**< (HSMCI_MR) Clock divider is odd Position */ +#define HSMCI_MR_CLKODD_Msk (_U_(0x1) << HSMCI_MR_CLKODD_Pos) /**< (HSMCI_MR) Clock divider is odd Mask */ +#define HSMCI_MR_CLKODD(value) (HSMCI_MR_CLKODD_Msk & ((value) << HSMCI_MR_CLKODD_Pos)) +#define HSMCI_MR_Msk _U_(0x00017FFF) /**< (HSMCI_MR) Register Mask */ + + +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) (R/W 32) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos _U_(0) /**< (HSMCI_DTOR) Data Timeout Cycle Number Position */ +#define HSMCI_DTOR_DTOCYC_Msk (_U_(0xF) << HSMCI_DTOR_DTOCYC_Pos) /**< (HSMCI_DTOR) Data Timeout Cycle Number Mask */ +#define HSMCI_DTOR_DTOCYC(value) (HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)) +#define HSMCI_DTOR_DTOMUL_Pos _U_(4) /**< (HSMCI_DTOR) Data Timeout Multiplier Position */ +#define HSMCI_DTOR_DTOMUL_Msk (_U_(0x7) << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) Data Timeout Multiplier Mask */ +#define HSMCI_DTOR_DTOMUL(value) (HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)) +#define HSMCI_DTOR_DTOMUL_1_Val _U_(0x0) /**< (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16_Val _U_(0x1) /**< (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128_Val _U_(0x2) /**< (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256_Val _U_(0x3) /**< (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024_Val _U_(0x4) /**< (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096_Val _U_(0x5) /**< (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536_Val _U_(0x6) /**< (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_DTOR) DTOCYC x 1048576 */ +#define HSMCI_DTOR_DTOMUL_1 (HSMCI_DTOR_DTOMUL_1_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC Position */ +#define HSMCI_DTOR_DTOMUL_16 (HSMCI_DTOR_DTOMUL_16_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 16 Position */ +#define HSMCI_DTOR_DTOMUL_128 (HSMCI_DTOR_DTOMUL_128_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 128 Position */ +#define HSMCI_DTOR_DTOMUL_256 (HSMCI_DTOR_DTOMUL_256_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 256 Position */ +#define HSMCI_DTOR_DTOMUL_1024 (HSMCI_DTOR_DTOMUL_1024_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1024 Position */ +#define HSMCI_DTOR_DTOMUL_4096 (HSMCI_DTOR_DTOMUL_4096_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 4096 Position */ +#define HSMCI_DTOR_DTOMUL_65536 (HSMCI_DTOR_DTOMUL_65536_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 65536 Position */ +#define HSMCI_DTOR_DTOMUL_1048576 (HSMCI_DTOR_DTOMUL_1048576_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1048576 Position */ +#define HSMCI_DTOR_Msk _U_(0x0000007F) /**< (HSMCI_DTOR) Register Mask */ + + +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) (R/W 32) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos _U_(0) /**< (HSMCI_SDCR) SDCard/SDIO Slot Position */ +#define HSMCI_SDCR_SDCSEL_Msk (_U_(0x3) << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Slot Mask */ +#define HSMCI_SDCR_SDCSEL(value) (HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)) +#define HSMCI_SDCR_SDCSEL_SLOTA_Val _U_(0x0) /**< (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTA (HSMCI_SDCR_SDCSEL_SLOTA_Val << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) Slot A is selected. Position */ +#define HSMCI_SDCR_SDCBUS_Pos _U_(6) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Position */ +#define HSMCI_SDCR_SDCBUS_Msk (_U_(0x3) << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Mask */ +#define HSMCI_SDCR_SDCBUS(value) (HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)) +#define HSMCI_SDCR_SDCBUS_1_Val _U_(0x0) /**< (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4_Val _U_(0x2) /**< (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8_Val _U_(0x3) /**< (HSMCI_SDCR) 8 bits */ +#define HSMCI_SDCR_SDCBUS_1 (HSMCI_SDCR_SDCBUS_1_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 1 bit Position */ +#define HSMCI_SDCR_SDCBUS_4 (HSMCI_SDCR_SDCBUS_4_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 4 bits Position */ +#define HSMCI_SDCR_SDCBUS_8 (HSMCI_SDCR_SDCBUS_8_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 8 bits Position */ +#define HSMCI_SDCR_Msk _U_(0x000000C3) /**< (HSMCI_SDCR) Register Mask */ + + +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) (R/W 32) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos _U_(0) /**< (HSMCI_ARGR) Command Argument Position */ +#define HSMCI_ARGR_ARG_Msk (_U_(0xFFFFFFFF) << HSMCI_ARGR_ARG_Pos) /**< (HSMCI_ARGR) Command Argument Mask */ +#define HSMCI_ARGR_ARG(value) (HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)) +#define HSMCI_ARGR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_ARGR) Register Mask */ + + +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) ( /W 32) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos _U_(0) /**< (HSMCI_CMDR) Command Number Position */ +#define HSMCI_CMDR_CMDNB_Msk (_U_(0x3F) << HSMCI_CMDR_CMDNB_Pos) /**< (HSMCI_CMDR) Command Number Mask */ +#define HSMCI_CMDR_CMDNB(value) (HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)) +#define HSMCI_CMDR_RSPTYP_Pos _U_(6) /**< (HSMCI_CMDR) Response Type Position */ +#define HSMCI_CMDR_RSPTYP_Msk (_U_(0x3) << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) Response Type Mask */ +#define HSMCI_CMDR_RSPTYP(value) (HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)) +#define HSMCI_CMDR_RSPTYP_NORESP_Val _U_(0x0) /**< (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT_Val _U_(0x1) /**< (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT_Val _U_(0x2) /**< (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B_Val _U_(0x3) /**< (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_RSPTYP_NORESP (HSMCI_CMDR_RSPTYP_NORESP_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) No response Position */ +#define HSMCI_CMDR_RSPTYP_48_BIT (HSMCI_CMDR_RSPTYP_48_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 48-bit response Position */ +#define HSMCI_CMDR_RSPTYP_136_BIT (HSMCI_CMDR_RSPTYP_136_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 136-bit response Position */ +#define HSMCI_CMDR_RSPTYP_R1B (HSMCI_CMDR_RSPTYP_R1B_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) R1b response type Position */ +#define HSMCI_CMDR_SPCMD_Pos _U_(8) /**< (HSMCI_CMDR) Special Command Position */ +#define HSMCI_CMDR_SPCMD_Msk (_U_(0x7) << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Special Command Mask */ +#define HSMCI_CMDR_SPCMD(value) (HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)) +#define HSMCI_CMDR_SPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT_Val _U_(0x1) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC_Val _U_(0x2) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA_Val _U_(0x3) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD_Val _U_(0x4) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP_Val _U_(0x5) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR_Val _U_(0x6) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO_Val _U_(0x7) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_SPCMD_STD (HSMCI_CMDR_SPCMD_STD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Not a special CMD. Position */ +#define HSMCI_CMDR_SPCMD_INIT (HSMCI_CMDR_SPCMD_INIT_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. Position */ +#define HSMCI_CMDR_SPCMD_SYNC (HSMCI_CMDR_SPCMD_SYNC_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Position */ +#define HSMCI_CMDR_SPCMD_CE_ATA (HSMCI_CMDR_SPCMD_CE_ATA_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Position */ +#define HSMCI_CMDR_SPCMD_IT_CMD (HSMCI_CMDR_SPCMD_IT_CMD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_IT_RESP (HSMCI_CMDR_SPCMD_IT_RESP_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_BOR (HSMCI_CMDR_SPCMD_BOR_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. Position */ +#define HSMCI_CMDR_SPCMD_EBO (HSMCI_CMDR_SPCMD_EBO_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. Position */ +#define HSMCI_CMDR_OPDCMD_Pos _U_(11) /**< (HSMCI_CMDR) Open Drain Command Position */ +#define HSMCI_CMDR_OPDCMD_Msk (_U_(0x1) << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open Drain Command Mask */ +#define HSMCI_CMDR_OPDCMD(value) (HSMCI_CMDR_OPDCMD_Msk & ((value) << HSMCI_CMDR_OPDCMD_Pos)) +#define HSMCI_CMDR_OPDCMD_PUSHPULL_Val _U_(0x0) /**< (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN_Val _U_(0x1) /**< (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (HSMCI_CMDR_OPDCMD_PUSHPULL_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Push pull command. Position */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (HSMCI_CMDR_OPDCMD_OPENDRAIN_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open drain command. Position */ +#define HSMCI_CMDR_MAXLAT_Pos _U_(12) /**< (HSMCI_CMDR) Max Latency for Command to Response Position */ +#define HSMCI_CMDR_MAXLAT_Msk (_U_(0x1) << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) Max Latency for Command to Response Mask */ +#define HSMCI_CMDR_MAXLAT(value) (HSMCI_CMDR_MAXLAT_Msk & ((value) << HSMCI_CMDR_MAXLAT_Pos)) +#define HSMCI_CMDR_MAXLAT_5_Val _U_(0x0) /**< (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64_Val _U_(0x1) /**< (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_5 (HSMCI_CMDR_MAXLAT_5_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 5-cycle max latency. Position */ +#define HSMCI_CMDR_MAXLAT_64 (HSMCI_CMDR_MAXLAT_64_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 64-cycle max latency. Position */ +#define HSMCI_CMDR_TRCMD_Pos _U_(16) /**< (HSMCI_CMDR) Transfer Command Position */ +#define HSMCI_CMDR_TRCMD_Msk (_U_(0x3) << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Transfer Command Mask */ +#define HSMCI_CMDR_TRCMD(value) (HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)) +#define HSMCI_CMDR_TRCMD_NO_DATA_Val _U_(0x0) /**< (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA_Val _U_(0x1) /**< (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA_Val _U_(0x2) /**< (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRCMD_NO_DATA (HSMCI_CMDR_TRCMD_NO_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) No data transfer Position */ +#define HSMCI_CMDR_TRCMD_START_DATA (HSMCI_CMDR_TRCMD_START_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Start data transfer Position */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (HSMCI_CMDR_TRCMD_STOP_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Stop data transfer Position */ +#define HSMCI_CMDR_TRDIR_Pos _U_(18) /**< (HSMCI_CMDR) Transfer Direction Position */ +#define HSMCI_CMDR_TRDIR_Msk (_U_(0x1) << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Transfer Direction Mask */ +#define HSMCI_CMDR_TRDIR(value) (HSMCI_CMDR_TRDIR_Msk & ((value) << HSMCI_CMDR_TRDIR_Pos)) +#define HSMCI_CMDR_TRDIR_WRITE_Val _U_(0x0) /**< (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ_Val _U_(0x1) /**< (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRDIR_WRITE (HSMCI_CMDR_TRDIR_WRITE_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Write. Position */ +#define HSMCI_CMDR_TRDIR_READ (HSMCI_CMDR_TRDIR_READ_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Read. Position */ +#define HSMCI_CMDR_TRTYP_Pos _U_(19) /**< (HSMCI_CMDR) Transfer Type Position */ +#define HSMCI_CMDR_TRTYP_Msk (_U_(0x7) << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) Transfer Type Mask */ +#define HSMCI_CMDR_TRTYP(value) (HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)) +#define HSMCI_CMDR_TRTYP_SINGLE_Val _U_(0x0) /**< (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE_Val _U_(0x1) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM_Val _U_(0x2) /**< (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE_Val _U_(0x4) /**< (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK_Val _U_(0x5) /**< (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_TRTYP_SINGLE (HSMCI_CMDR_TRTYP_SINGLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Single Block Position */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (HSMCI_CMDR_TRTYP_MULTIPLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block Position */ +#define HSMCI_CMDR_TRTYP_STREAM (HSMCI_CMDR_TRTYP_STREAM_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC Stream Position */ +#define HSMCI_CMDR_TRTYP_BYTE (HSMCI_CMDR_TRTYP_BYTE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Byte Position */ +#define HSMCI_CMDR_TRTYP_BLOCK (HSMCI_CMDR_TRTYP_BLOCK_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Block Position */ +#define HSMCI_CMDR_IOSPCMD_Pos _U_(24) /**< (HSMCI_CMDR) SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_Msk (_U_(0x3) << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Special Command Mask */ +#define HSMCI_CMDR_IOSPCMD(value) (HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)) +#define HSMCI_CMDR_IOSPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND_Val _U_(0x1) /**< (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME_Val _U_(0x2) /**< (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_IOSPCMD_STD (HSMCI_CMDR_IOSPCMD_STD_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) Not an SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (HSMCI_CMDR_IOSPCMD_SUSPEND_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Suspend Command Position */ +#define HSMCI_CMDR_IOSPCMD_RESUME (HSMCI_CMDR_IOSPCMD_RESUME_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Resume Command Position */ +#define HSMCI_CMDR_ATACS_Pos _U_(26) /**< (HSMCI_CMDR) ATA with Command Completion Signal Position */ +#define HSMCI_CMDR_ATACS_Msk (_U_(0x1) << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) ATA with Command Completion Signal Mask */ +#define HSMCI_CMDR_ATACS(value) (HSMCI_CMDR_ATACS_Msk & ((value) << HSMCI_CMDR_ATACS_Pos)) +#define HSMCI_CMDR_ATACS_NORMAL_Val _U_(0x0) /**< (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION_Val _U_(0x1) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_ATACS_NORMAL (HSMCI_CMDR_ATACS_NORMAL_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) Normal operation mode. Position */ +#define HSMCI_CMDR_ATACS_COMPLETION (HSMCI_CMDR_ATACS_COMPLETION_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). Position */ +#define HSMCI_CMDR_BOOT_ACK_Pos _U_(27) /**< (HSMCI_CMDR) Boot Operation Acknowledge Position */ +#define HSMCI_CMDR_BOOT_ACK_Msk (_U_(0x1) << HSMCI_CMDR_BOOT_ACK_Pos) /**< (HSMCI_CMDR) Boot Operation Acknowledge Mask */ +#define HSMCI_CMDR_BOOT_ACK(value) (HSMCI_CMDR_BOOT_ACK_Msk & ((value) << HSMCI_CMDR_BOOT_ACK_Pos)) +#define HSMCI_CMDR_Msk _U_(0x0F3F1FFF) /**< (HSMCI_CMDR) Register Mask */ + + +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) (R/W 32) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos _U_(0) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Position */ +#define HSMCI_BLKR_BCNT_Msk (_U_(0xFFFF) << HSMCI_BLKR_BCNT_Pos) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Mask */ +#define HSMCI_BLKR_BCNT(value) (HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)) +#define HSMCI_BLKR_BLKLEN_Pos _U_(16) /**< (HSMCI_BLKR) Data Block Length Position */ +#define HSMCI_BLKR_BLKLEN_Msk (_U_(0xFFFF) << HSMCI_BLKR_BLKLEN_Pos) /**< (HSMCI_BLKR) Data Block Length Mask */ +#define HSMCI_BLKR_BLKLEN(value) (HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)) +#define HSMCI_BLKR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_BLKR) Register Mask */ + + +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) (R/W 32) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos _U_(0) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Position */ +#define HSMCI_CSTOR_CSTOCYC_Msk (_U_(0xF) << HSMCI_CSTOR_CSTOCYC_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Mask */ +#define HSMCI_CSTOR_CSTOCYC(value) (HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)) +#define HSMCI_CSTOR_CSTOMUL_Pos _U_(4) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Position */ +#define HSMCI_CSTOR_CSTOMUL_Msk (_U_(0x7) << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Mask */ +#define HSMCI_CSTOR_CSTOMUL(value) (HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)) +#define HSMCI_CSTOR_CSTOMUL_1_Val _U_(0x0) /**< (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16_Val _U_(0x1) /**< (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128_Val _U_(0x2) /**< (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256_Val _U_(0x3) /**< (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024_Val _U_(0x4) /**< (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096_Val _U_(0x5) /**< (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536_Val _U_(0x6) /**< (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 */ +#define HSMCI_CSTOR_CSTOMUL_1 (HSMCI_CSTOR_CSTOMUL_1_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1 Position */ +#define HSMCI_CSTOR_CSTOMUL_16 (HSMCI_CSTOR_CSTOMUL_16_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 16 Position */ +#define HSMCI_CSTOR_CSTOMUL_128 (HSMCI_CSTOR_CSTOMUL_128_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 128 Position */ +#define HSMCI_CSTOR_CSTOMUL_256 (HSMCI_CSTOR_CSTOMUL_256_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 256 Position */ +#define HSMCI_CSTOR_CSTOMUL_1024 (HSMCI_CSTOR_CSTOMUL_1024_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1024 Position */ +#define HSMCI_CSTOR_CSTOMUL_4096 (HSMCI_CSTOR_CSTOMUL_4096_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 4096 Position */ +#define HSMCI_CSTOR_CSTOMUL_65536 (HSMCI_CSTOR_CSTOMUL_65536_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 65536 Position */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (HSMCI_CSTOR_CSTOMUL_1048576_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 Position */ +#define HSMCI_CSTOR_Msk _U_(0x0000007F) /**< (HSMCI_CSTOR) Register Mask */ + + +/* -------- HSMCI_RSPR : (HSMCI Offset: 0x20) ( R/ 32) Response Register 0 -------- */ +#define HSMCI_RSPR_RSP_Pos _U_(0) /**< (HSMCI_RSPR) Response Position */ +#define HSMCI_RSPR_RSP_Msk (_U_(0xFFFFFFFF) << HSMCI_RSPR_RSP_Pos) /**< (HSMCI_RSPR) Response Mask */ +#define HSMCI_RSPR_RSP(value) (HSMCI_RSPR_RSP_Msk & ((value) << HSMCI_RSPR_RSP_Pos)) +#define HSMCI_RSPR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RSPR) Register Mask */ + + +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) ( R/ 32) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos _U_(0) /**< (HSMCI_RDR) Data to Read Position */ +#define HSMCI_RDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_RDR_DATA_Pos) /**< (HSMCI_RDR) Data to Read Mask */ +#define HSMCI_RDR_DATA(value) (HSMCI_RDR_DATA_Msk & ((value) << HSMCI_RDR_DATA_Pos)) +#define HSMCI_RDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RDR) Register Mask */ + + +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) ( /W 32) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos _U_(0) /**< (HSMCI_TDR) Data to Write Position */ +#define HSMCI_TDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_TDR_DATA_Pos) /**< (HSMCI_TDR) Data to Write Mask */ +#define HSMCI_TDR_DATA(value) (HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)) +#define HSMCI_TDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_TDR) Register Mask */ + + +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) ( R/ 32) Status Register -------- */ +#define HSMCI_SR_CMDRDY_Pos _U_(0) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_CMDRDY_Msk (_U_(0x1) << HSMCI_SR_CMDRDY_Pos) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_CMDRDY(value) (HSMCI_SR_CMDRDY_Msk & ((value) << HSMCI_SR_CMDRDY_Pos)) +#define HSMCI_SR_RXRDY_Pos _U_(1) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Position */ +#define HSMCI_SR_RXRDY_Msk (_U_(0x1) << HSMCI_SR_RXRDY_Pos) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Mask */ +#define HSMCI_SR_RXRDY(value) (HSMCI_SR_RXRDY_Msk & ((value) << HSMCI_SR_RXRDY_Pos)) +#define HSMCI_SR_TXRDY_Pos _U_(2) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Position */ +#define HSMCI_SR_TXRDY_Msk (_U_(0x1) << HSMCI_SR_TXRDY_Pos) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Mask */ +#define HSMCI_SR_TXRDY(value) (HSMCI_SR_TXRDY_Msk & ((value) << HSMCI_SR_TXRDY_Pos)) +#define HSMCI_SR_BLKE_Pos _U_(3) /**< (HSMCI_SR) Data Block Ended (cleared on read) Position */ +#define HSMCI_SR_BLKE_Msk (_U_(0x1) << HSMCI_SR_BLKE_Pos) /**< (HSMCI_SR) Data Block Ended (cleared on read) Mask */ +#define HSMCI_SR_BLKE(value) (HSMCI_SR_BLKE_Msk & ((value) << HSMCI_SR_BLKE_Pos)) +#define HSMCI_SR_DTIP_Pos _U_(4) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Position */ +#define HSMCI_SR_DTIP_Msk (_U_(0x1) << HSMCI_SR_DTIP_Pos) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Mask */ +#define HSMCI_SR_DTIP(value) (HSMCI_SR_DTIP_Msk & ((value) << HSMCI_SR_DTIP_Pos)) +#define HSMCI_SR_NOTBUSY_Pos _U_(5) /**< (HSMCI_SR) HSMCI Not Busy Position */ +#define HSMCI_SR_NOTBUSY_Msk (_U_(0x1) << HSMCI_SR_NOTBUSY_Pos) /**< (HSMCI_SR) HSMCI Not Busy Mask */ +#define HSMCI_SR_NOTBUSY(value) (HSMCI_SR_NOTBUSY_Msk & ((value) << HSMCI_SR_NOTBUSY_Pos)) +#define HSMCI_SR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Position */ +#define HSMCI_SR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_SR_SDIOIRQA_Pos) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Mask */ +#define HSMCI_SR_SDIOIRQA(value) (HSMCI_SR_SDIOIRQA_Msk & ((value) << HSMCI_SR_SDIOIRQA_Pos)) +#define HSMCI_SR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_SR) SDIO Read Wait Operation Status Position */ +#define HSMCI_SR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_SR_SDIOWAIT_Pos) /**< (HSMCI_SR) SDIO Read Wait Operation Status Mask */ +#define HSMCI_SR_SDIOWAIT(value) (HSMCI_SR_SDIOWAIT_Msk & ((value) << HSMCI_SR_SDIOWAIT_Pos)) +#define HSMCI_SR_CSRCV_Pos _U_(13) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Position */ +#define HSMCI_SR_CSRCV_Msk (_U_(0x1) << HSMCI_SR_CSRCV_Pos) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Mask */ +#define HSMCI_SR_CSRCV(value) (HSMCI_SR_CSRCV_Msk & ((value) << HSMCI_SR_CSRCV_Pos)) +#define HSMCI_SR_RINDE_Pos _U_(16) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RINDE_Msk (_U_(0x1) << HSMCI_SR_RINDE_Pos) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RINDE(value) (HSMCI_SR_RINDE_Msk & ((value) << HSMCI_SR_RINDE_Pos)) +#define HSMCI_SR_RDIRE_Pos _U_(17) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RDIRE_Msk (_U_(0x1) << HSMCI_SR_RDIRE_Pos) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RDIRE(value) (HSMCI_SR_RDIRE_Msk & ((value) << HSMCI_SR_RDIRE_Pos)) +#define HSMCI_SR_RCRCE_Pos _U_(18) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RCRCE_Msk (_U_(0x1) << HSMCI_SR_RCRCE_Pos) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RCRCE(value) (HSMCI_SR_RCRCE_Msk & ((value) << HSMCI_SR_RCRCE_Pos)) +#define HSMCI_SR_RENDE_Pos _U_(19) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RENDE_Msk (_U_(0x1) << HSMCI_SR_RENDE_Pos) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RENDE(value) (HSMCI_SR_RENDE_Msk & ((value) << HSMCI_SR_RENDE_Pos)) +#define HSMCI_SR_RTOE_Pos _U_(20) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RTOE_Msk (_U_(0x1) << HSMCI_SR_RTOE_Pos) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RTOE(value) (HSMCI_SR_RTOE_Msk & ((value) << HSMCI_SR_RTOE_Pos)) +#define HSMCI_SR_DCRCE_Pos _U_(21) /**< (HSMCI_SR) Data CRC Error (cleared on read) Position */ +#define HSMCI_SR_DCRCE_Msk (_U_(0x1) << HSMCI_SR_DCRCE_Pos) /**< (HSMCI_SR) Data CRC Error (cleared on read) Mask */ +#define HSMCI_SR_DCRCE(value) (HSMCI_SR_DCRCE_Msk & ((value) << HSMCI_SR_DCRCE_Pos)) +#define HSMCI_SR_DTOE_Pos _U_(22) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Position */ +#define HSMCI_SR_DTOE_Msk (_U_(0x1) << HSMCI_SR_DTOE_Pos) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_DTOE(value) (HSMCI_SR_DTOE_Msk & ((value) << HSMCI_SR_DTOE_Pos)) +#define HSMCI_SR_CSTOE_Pos _U_(23) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Position */ +#define HSMCI_SR_CSTOE_Msk (_U_(0x1) << HSMCI_SR_CSTOE_Pos) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_CSTOE(value) (HSMCI_SR_CSTOE_Msk & ((value) << HSMCI_SR_CSTOE_Pos)) +#define HSMCI_SR_BLKOVRE_Pos _U_(24) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Position */ +#define HSMCI_SR_BLKOVRE_Msk (_U_(0x1) << HSMCI_SR_BLKOVRE_Pos) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Mask */ +#define HSMCI_SR_BLKOVRE(value) (HSMCI_SR_BLKOVRE_Msk & ((value) << HSMCI_SR_BLKOVRE_Pos)) +#define HSMCI_SR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_SR) FIFO empty flag Position */ +#define HSMCI_SR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_SR_FIFOEMPTY_Pos) /**< (HSMCI_SR) FIFO empty flag Mask */ +#define HSMCI_SR_FIFOEMPTY(value) (HSMCI_SR_FIFOEMPTY_Msk & ((value) << HSMCI_SR_FIFOEMPTY_Pos)) +#define HSMCI_SR_XFRDONE_Pos _U_(27) /**< (HSMCI_SR) Transfer Done flag Position */ +#define HSMCI_SR_XFRDONE_Msk (_U_(0x1) << HSMCI_SR_XFRDONE_Pos) /**< (HSMCI_SR) Transfer Done flag Mask */ +#define HSMCI_SR_XFRDONE(value) (HSMCI_SR_XFRDONE_Msk & ((value) << HSMCI_SR_XFRDONE_Pos)) +#define HSMCI_SR_ACKRCV_Pos _U_(28) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Position */ +#define HSMCI_SR_ACKRCV_Msk (_U_(0x1) << HSMCI_SR_ACKRCV_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Mask */ +#define HSMCI_SR_ACKRCV(value) (HSMCI_SR_ACKRCV_Msk & ((value) << HSMCI_SR_ACKRCV_Pos)) +#define HSMCI_SR_ACKRCVE_Pos _U_(29) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Position */ +#define HSMCI_SR_ACKRCVE_Msk (_U_(0x1) << HSMCI_SR_ACKRCVE_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Mask */ +#define HSMCI_SR_ACKRCVE(value) (HSMCI_SR_ACKRCVE_Msk & ((value) << HSMCI_SR_ACKRCVE_Pos)) +#define HSMCI_SR_OVRE_Pos _U_(30) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_OVRE_Msk (_U_(0x1) << HSMCI_SR_OVRE_Pos) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_OVRE(value) (HSMCI_SR_OVRE_Msk & ((value) << HSMCI_SR_OVRE_Pos)) +#define HSMCI_SR_UNRE_Pos _U_(31) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_UNRE_Msk (_U_(0x1) << HSMCI_SR_UNRE_Pos) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_UNRE(value) (HSMCI_SR_UNRE_Msk & ((value) << HSMCI_SR_UNRE_Pos)) +#define HSMCI_SR_Msk _U_(0xFDFF313F) /**< (HSMCI_SR) Register Mask */ + + +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) ( /W 32) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY_Pos _U_(0) /**< (HSMCI_IER) Command Ready Interrupt Enable Position */ +#define HSMCI_IER_CMDRDY_Msk (_U_(0x1) << HSMCI_IER_CMDRDY_Pos) /**< (HSMCI_IER) Command Ready Interrupt Enable Mask */ +#define HSMCI_IER_CMDRDY(value) (HSMCI_IER_CMDRDY_Msk & ((value) << HSMCI_IER_CMDRDY_Pos)) +#define HSMCI_IER_RXRDY_Pos _U_(1) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Position */ +#define HSMCI_IER_RXRDY_Msk (_U_(0x1) << HSMCI_IER_RXRDY_Pos) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Mask */ +#define HSMCI_IER_RXRDY(value) (HSMCI_IER_RXRDY_Msk & ((value) << HSMCI_IER_RXRDY_Pos)) +#define HSMCI_IER_TXRDY_Pos _U_(2) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Position */ +#define HSMCI_IER_TXRDY_Msk (_U_(0x1) << HSMCI_IER_TXRDY_Pos) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Mask */ +#define HSMCI_IER_TXRDY(value) (HSMCI_IER_TXRDY_Msk & ((value) << HSMCI_IER_TXRDY_Pos)) +#define HSMCI_IER_BLKE_Pos _U_(3) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Position */ +#define HSMCI_IER_BLKE_Msk (_U_(0x1) << HSMCI_IER_BLKE_Pos) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Mask */ +#define HSMCI_IER_BLKE(value) (HSMCI_IER_BLKE_Msk & ((value) << HSMCI_IER_BLKE_Pos)) +#define HSMCI_IER_DTIP_Pos _U_(4) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Position */ +#define HSMCI_IER_DTIP_Msk (_U_(0x1) << HSMCI_IER_DTIP_Pos) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Mask */ +#define HSMCI_IER_DTIP(value) (HSMCI_IER_DTIP_Msk & ((value) << HSMCI_IER_DTIP_Pos)) +#define HSMCI_IER_NOTBUSY_Pos _U_(5) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Position */ +#define HSMCI_IER_NOTBUSY_Msk (_U_(0x1) << HSMCI_IER_NOTBUSY_Pos) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Mask */ +#define HSMCI_IER_NOTBUSY(value) (HSMCI_IER_NOTBUSY_Msk & ((value) << HSMCI_IER_NOTBUSY_Pos)) +#define HSMCI_IER_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Position */ +#define HSMCI_IER_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IER_SDIOIRQA_Pos) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Mask */ +#define HSMCI_IER_SDIOIRQA(value) (HSMCI_IER_SDIOIRQA_Msk & ((value) << HSMCI_IER_SDIOIRQA_Pos)) +#define HSMCI_IER_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Position */ +#define HSMCI_IER_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IER_SDIOWAIT_Pos) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Mask */ +#define HSMCI_IER_SDIOWAIT(value) (HSMCI_IER_SDIOWAIT_Msk & ((value) << HSMCI_IER_SDIOWAIT_Pos)) +#define HSMCI_IER_CSRCV_Pos _U_(13) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Position */ +#define HSMCI_IER_CSRCV_Msk (_U_(0x1) << HSMCI_IER_CSRCV_Pos) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Mask */ +#define HSMCI_IER_CSRCV(value) (HSMCI_IER_CSRCV_Msk & ((value) << HSMCI_IER_CSRCV_Pos)) +#define HSMCI_IER_RINDE_Pos _U_(16) /**< (HSMCI_IER) Response Index Error Interrupt Enable Position */ +#define HSMCI_IER_RINDE_Msk (_U_(0x1) << HSMCI_IER_RINDE_Pos) /**< (HSMCI_IER) Response Index Error Interrupt Enable Mask */ +#define HSMCI_IER_RINDE(value) (HSMCI_IER_RINDE_Msk & ((value) << HSMCI_IER_RINDE_Pos)) +#define HSMCI_IER_RDIRE_Pos _U_(17) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Position */ +#define HSMCI_IER_RDIRE_Msk (_U_(0x1) << HSMCI_IER_RDIRE_Pos) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Mask */ +#define HSMCI_IER_RDIRE(value) (HSMCI_IER_RDIRE_Msk & ((value) << HSMCI_IER_RDIRE_Pos)) +#define HSMCI_IER_RCRCE_Pos _U_(18) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Position */ +#define HSMCI_IER_RCRCE_Msk (_U_(0x1) << HSMCI_IER_RCRCE_Pos) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_RCRCE(value) (HSMCI_IER_RCRCE_Msk & ((value) << HSMCI_IER_RCRCE_Pos)) +#define HSMCI_IER_RENDE_Pos _U_(19) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Position */ +#define HSMCI_IER_RENDE_Msk (_U_(0x1) << HSMCI_IER_RENDE_Pos) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Mask */ +#define HSMCI_IER_RENDE(value) (HSMCI_IER_RENDE_Msk & ((value) << HSMCI_IER_RENDE_Pos)) +#define HSMCI_IER_RTOE_Pos _U_(20) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_RTOE_Msk (_U_(0x1) << HSMCI_IER_RTOE_Pos) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_RTOE(value) (HSMCI_IER_RTOE_Msk & ((value) << HSMCI_IER_RTOE_Pos)) +#define HSMCI_IER_DCRCE_Pos _U_(21) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Position */ +#define HSMCI_IER_DCRCE_Msk (_U_(0x1) << HSMCI_IER_DCRCE_Pos) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_DCRCE(value) (HSMCI_IER_DCRCE_Msk & ((value) << HSMCI_IER_DCRCE_Pos)) +#define HSMCI_IER_DTOE_Pos _U_(22) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_DTOE_Msk (_U_(0x1) << HSMCI_IER_DTOE_Pos) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_DTOE(value) (HSMCI_IER_DTOE_Msk & ((value) << HSMCI_IER_DTOE_Pos)) +#define HSMCI_IER_CSTOE_Pos _U_(23) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Position */ +#define HSMCI_IER_CSTOE_Msk (_U_(0x1) << HSMCI_IER_CSTOE_Pos) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Mask */ +#define HSMCI_IER_CSTOE(value) (HSMCI_IER_CSTOE_Msk & ((value) << HSMCI_IER_CSTOE_Pos)) +#define HSMCI_IER_BLKOVRE_Pos _U_(24) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Position */ +#define HSMCI_IER_BLKOVRE_Msk (_U_(0x1) << HSMCI_IER_BLKOVRE_Pos) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Mask */ +#define HSMCI_IER_BLKOVRE(value) (HSMCI_IER_BLKOVRE_Msk & ((value) << HSMCI_IER_BLKOVRE_Pos)) +#define HSMCI_IER_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IER) FIFO empty Interrupt enable Position */ +#define HSMCI_IER_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IER_FIFOEMPTY_Pos) /**< (HSMCI_IER) FIFO empty Interrupt enable Mask */ +#define HSMCI_IER_FIFOEMPTY(value) (HSMCI_IER_FIFOEMPTY_Msk & ((value) << HSMCI_IER_FIFOEMPTY_Pos)) +#define HSMCI_IER_XFRDONE_Pos _U_(27) /**< (HSMCI_IER) Transfer Done Interrupt enable Position */ +#define HSMCI_IER_XFRDONE_Msk (_U_(0x1) << HSMCI_IER_XFRDONE_Pos) /**< (HSMCI_IER) Transfer Done Interrupt enable Mask */ +#define HSMCI_IER_XFRDONE(value) (HSMCI_IER_XFRDONE_Msk & ((value) << HSMCI_IER_XFRDONE_Pos)) +#define HSMCI_IER_ACKRCV_Pos _U_(28) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Position */ +#define HSMCI_IER_ACKRCV_Msk (_U_(0x1) << HSMCI_IER_ACKRCV_Pos) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCV(value) (HSMCI_IER_ACKRCV_Msk & ((value) << HSMCI_IER_ACKRCV_Pos)) +#define HSMCI_IER_ACKRCVE_Pos _U_(29) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Position */ +#define HSMCI_IER_ACKRCVE_Msk (_U_(0x1) << HSMCI_IER_ACKRCVE_Pos) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCVE(value) (HSMCI_IER_ACKRCVE_Msk & ((value) << HSMCI_IER_ACKRCVE_Pos)) +#define HSMCI_IER_OVRE_Pos _U_(30) /**< (HSMCI_IER) Overrun Interrupt Enable Position */ +#define HSMCI_IER_OVRE_Msk (_U_(0x1) << HSMCI_IER_OVRE_Pos) /**< (HSMCI_IER) Overrun Interrupt Enable Mask */ +#define HSMCI_IER_OVRE(value) (HSMCI_IER_OVRE_Msk & ((value) << HSMCI_IER_OVRE_Pos)) +#define HSMCI_IER_UNRE_Pos _U_(31) /**< (HSMCI_IER) Underrun Interrupt Enable Position */ +#define HSMCI_IER_UNRE_Msk (_U_(0x1) << HSMCI_IER_UNRE_Pos) /**< (HSMCI_IER) Underrun Interrupt Enable Mask */ +#define HSMCI_IER_UNRE(value) (HSMCI_IER_UNRE_Msk & ((value) << HSMCI_IER_UNRE_Pos)) +#define HSMCI_IER_Msk _U_(0xFDFF313F) /**< (HSMCI_IER) Register Mask */ + + +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) ( /W 32) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY_Pos _U_(0) /**< (HSMCI_IDR) Command Ready Interrupt Disable Position */ +#define HSMCI_IDR_CMDRDY_Msk (_U_(0x1) << HSMCI_IDR_CMDRDY_Pos) /**< (HSMCI_IDR) Command Ready Interrupt Disable Mask */ +#define HSMCI_IDR_CMDRDY(value) (HSMCI_IDR_CMDRDY_Msk & ((value) << HSMCI_IDR_CMDRDY_Pos)) +#define HSMCI_IDR_RXRDY_Pos _U_(1) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Position */ +#define HSMCI_IDR_RXRDY_Msk (_U_(0x1) << HSMCI_IDR_RXRDY_Pos) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Mask */ +#define HSMCI_IDR_RXRDY(value) (HSMCI_IDR_RXRDY_Msk & ((value) << HSMCI_IDR_RXRDY_Pos)) +#define HSMCI_IDR_TXRDY_Pos _U_(2) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Position */ +#define HSMCI_IDR_TXRDY_Msk (_U_(0x1) << HSMCI_IDR_TXRDY_Pos) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Mask */ +#define HSMCI_IDR_TXRDY(value) (HSMCI_IDR_TXRDY_Msk & ((value) << HSMCI_IDR_TXRDY_Pos)) +#define HSMCI_IDR_BLKE_Pos _U_(3) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Position */ +#define HSMCI_IDR_BLKE_Msk (_U_(0x1) << HSMCI_IDR_BLKE_Pos) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Mask */ +#define HSMCI_IDR_BLKE(value) (HSMCI_IDR_BLKE_Msk & ((value) << HSMCI_IDR_BLKE_Pos)) +#define HSMCI_IDR_DTIP_Pos _U_(4) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Position */ +#define HSMCI_IDR_DTIP_Msk (_U_(0x1) << HSMCI_IDR_DTIP_Pos) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Mask */ +#define HSMCI_IDR_DTIP(value) (HSMCI_IDR_DTIP_Msk & ((value) << HSMCI_IDR_DTIP_Pos)) +#define HSMCI_IDR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Position */ +#define HSMCI_IDR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IDR_NOTBUSY_Pos) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Mask */ +#define HSMCI_IDR_NOTBUSY(value) (HSMCI_IDR_NOTBUSY_Msk & ((value) << HSMCI_IDR_NOTBUSY_Pos)) +#define HSMCI_IDR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Position */ +#define HSMCI_IDR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IDR_SDIOIRQA_Pos) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOIRQA(value) (HSMCI_IDR_SDIOIRQA_Msk & ((value) << HSMCI_IDR_SDIOIRQA_Pos)) +#define HSMCI_IDR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Position */ +#define HSMCI_IDR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IDR_SDIOWAIT_Pos) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOWAIT(value) (HSMCI_IDR_SDIOWAIT_Msk & ((value) << HSMCI_IDR_SDIOWAIT_Pos)) +#define HSMCI_IDR_CSRCV_Pos _U_(13) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Position */ +#define HSMCI_IDR_CSRCV_Msk (_U_(0x1) << HSMCI_IDR_CSRCV_Pos) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Mask */ +#define HSMCI_IDR_CSRCV(value) (HSMCI_IDR_CSRCV_Msk & ((value) << HSMCI_IDR_CSRCV_Pos)) +#define HSMCI_IDR_RINDE_Pos _U_(16) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Position */ +#define HSMCI_IDR_RINDE_Msk (_U_(0x1) << HSMCI_IDR_RINDE_Pos) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Mask */ +#define HSMCI_IDR_RINDE(value) (HSMCI_IDR_RINDE_Msk & ((value) << HSMCI_IDR_RINDE_Pos)) +#define HSMCI_IDR_RDIRE_Pos _U_(17) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Position */ +#define HSMCI_IDR_RDIRE_Msk (_U_(0x1) << HSMCI_IDR_RDIRE_Pos) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Mask */ +#define HSMCI_IDR_RDIRE(value) (HSMCI_IDR_RDIRE_Msk & ((value) << HSMCI_IDR_RDIRE_Pos)) +#define HSMCI_IDR_RCRCE_Pos _U_(18) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_RCRCE_Msk (_U_(0x1) << HSMCI_IDR_RCRCE_Pos) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_RCRCE(value) (HSMCI_IDR_RCRCE_Msk & ((value) << HSMCI_IDR_RCRCE_Pos)) +#define HSMCI_IDR_RENDE_Pos _U_(19) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Position */ +#define HSMCI_IDR_RENDE_Msk (_U_(0x1) << HSMCI_IDR_RENDE_Pos) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Mask */ +#define HSMCI_IDR_RENDE(value) (HSMCI_IDR_RENDE_Msk & ((value) << HSMCI_IDR_RENDE_Pos)) +#define HSMCI_IDR_RTOE_Pos _U_(20) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_RTOE_Msk (_U_(0x1) << HSMCI_IDR_RTOE_Pos) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_RTOE(value) (HSMCI_IDR_RTOE_Msk & ((value) << HSMCI_IDR_RTOE_Pos)) +#define HSMCI_IDR_DCRCE_Pos _U_(21) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_DCRCE_Msk (_U_(0x1) << HSMCI_IDR_DCRCE_Pos) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_DCRCE(value) (HSMCI_IDR_DCRCE_Msk & ((value) << HSMCI_IDR_DCRCE_Pos)) +#define HSMCI_IDR_DTOE_Pos _U_(22) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_DTOE_Msk (_U_(0x1) << HSMCI_IDR_DTOE_Pos) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_DTOE(value) (HSMCI_IDR_DTOE_Msk & ((value) << HSMCI_IDR_DTOE_Pos)) +#define HSMCI_IDR_CSTOE_Pos _U_(23) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Position */ +#define HSMCI_IDR_CSTOE_Msk (_U_(0x1) << HSMCI_IDR_CSTOE_Pos) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Mask */ +#define HSMCI_IDR_CSTOE(value) (HSMCI_IDR_CSTOE_Msk & ((value) << HSMCI_IDR_CSTOE_Pos)) +#define HSMCI_IDR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Position */ +#define HSMCI_IDR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IDR_BLKOVRE_Pos) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Mask */ +#define HSMCI_IDR_BLKOVRE(value) (HSMCI_IDR_BLKOVRE_Msk & ((value) << HSMCI_IDR_BLKOVRE_Pos)) +#define HSMCI_IDR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Position */ +#define HSMCI_IDR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IDR_FIFOEMPTY_Pos) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Mask */ +#define HSMCI_IDR_FIFOEMPTY(value) (HSMCI_IDR_FIFOEMPTY_Msk & ((value) << HSMCI_IDR_FIFOEMPTY_Pos)) +#define HSMCI_IDR_XFRDONE_Pos _U_(27) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Position */ +#define HSMCI_IDR_XFRDONE_Msk (_U_(0x1) << HSMCI_IDR_XFRDONE_Pos) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Mask */ +#define HSMCI_IDR_XFRDONE(value) (HSMCI_IDR_XFRDONE_Msk & ((value) << HSMCI_IDR_XFRDONE_Pos)) +#define HSMCI_IDR_ACKRCV_Pos _U_(28) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCV_Msk (_U_(0x1) << HSMCI_IDR_ACKRCV_Pos) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCV(value) (HSMCI_IDR_ACKRCV_Msk & ((value) << HSMCI_IDR_ACKRCV_Pos)) +#define HSMCI_IDR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IDR_ACKRCVE_Pos) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCVE(value) (HSMCI_IDR_ACKRCVE_Msk & ((value) << HSMCI_IDR_ACKRCVE_Pos)) +#define HSMCI_IDR_OVRE_Pos _U_(30) /**< (HSMCI_IDR) Overrun Interrupt Disable Position */ +#define HSMCI_IDR_OVRE_Msk (_U_(0x1) << HSMCI_IDR_OVRE_Pos) /**< (HSMCI_IDR) Overrun Interrupt Disable Mask */ +#define HSMCI_IDR_OVRE(value) (HSMCI_IDR_OVRE_Msk & ((value) << HSMCI_IDR_OVRE_Pos)) +#define HSMCI_IDR_UNRE_Pos _U_(31) /**< (HSMCI_IDR) Underrun Interrupt Disable Position */ +#define HSMCI_IDR_UNRE_Msk (_U_(0x1) << HSMCI_IDR_UNRE_Pos) /**< (HSMCI_IDR) Underrun Interrupt Disable Mask */ +#define HSMCI_IDR_UNRE(value) (HSMCI_IDR_UNRE_Msk & ((value) << HSMCI_IDR_UNRE_Pos)) +#define HSMCI_IDR_Msk _U_(0xFDFF313F) /**< (HSMCI_IDR) Register Mask */ + + +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) ( R/ 32) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY_Pos _U_(0) /**< (HSMCI_IMR) Command Ready Interrupt Mask Position */ +#define HSMCI_IMR_CMDRDY_Msk (_U_(0x1) << HSMCI_IMR_CMDRDY_Pos) /**< (HSMCI_IMR) Command Ready Interrupt Mask Mask */ +#define HSMCI_IMR_CMDRDY(value) (HSMCI_IMR_CMDRDY_Msk & ((value) << HSMCI_IMR_CMDRDY_Pos)) +#define HSMCI_IMR_RXRDY_Pos _U_(1) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Position */ +#define HSMCI_IMR_RXRDY_Msk (_U_(0x1) << HSMCI_IMR_RXRDY_Pos) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Mask */ +#define HSMCI_IMR_RXRDY(value) (HSMCI_IMR_RXRDY_Msk & ((value) << HSMCI_IMR_RXRDY_Pos)) +#define HSMCI_IMR_TXRDY_Pos _U_(2) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Position */ +#define HSMCI_IMR_TXRDY_Msk (_U_(0x1) << HSMCI_IMR_TXRDY_Pos) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Mask */ +#define HSMCI_IMR_TXRDY(value) (HSMCI_IMR_TXRDY_Msk & ((value) << HSMCI_IMR_TXRDY_Pos)) +#define HSMCI_IMR_BLKE_Pos _U_(3) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Position */ +#define HSMCI_IMR_BLKE_Msk (_U_(0x1) << HSMCI_IMR_BLKE_Pos) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Mask */ +#define HSMCI_IMR_BLKE(value) (HSMCI_IMR_BLKE_Msk & ((value) << HSMCI_IMR_BLKE_Pos)) +#define HSMCI_IMR_DTIP_Pos _U_(4) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Position */ +#define HSMCI_IMR_DTIP_Msk (_U_(0x1) << HSMCI_IMR_DTIP_Pos) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Mask */ +#define HSMCI_IMR_DTIP(value) (HSMCI_IMR_DTIP_Msk & ((value) << HSMCI_IMR_DTIP_Pos)) +#define HSMCI_IMR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Position */ +#define HSMCI_IMR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IMR_NOTBUSY_Pos) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Mask */ +#define HSMCI_IMR_NOTBUSY(value) (HSMCI_IMR_NOTBUSY_Msk & ((value) << HSMCI_IMR_NOTBUSY_Pos)) +#define HSMCI_IMR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Position */ +#define HSMCI_IMR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IMR_SDIOIRQA_Pos) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOIRQA(value) (HSMCI_IMR_SDIOIRQA_Msk & ((value) << HSMCI_IMR_SDIOIRQA_Pos)) +#define HSMCI_IMR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Position */ +#define HSMCI_IMR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IMR_SDIOWAIT_Pos) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOWAIT(value) (HSMCI_IMR_SDIOWAIT_Msk & ((value) << HSMCI_IMR_SDIOWAIT_Pos)) +#define HSMCI_IMR_CSRCV_Pos _U_(13) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Position */ +#define HSMCI_IMR_CSRCV_Msk (_U_(0x1) << HSMCI_IMR_CSRCV_Pos) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Mask */ +#define HSMCI_IMR_CSRCV(value) (HSMCI_IMR_CSRCV_Msk & ((value) << HSMCI_IMR_CSRCV_Pos)) +#define HSMCI_IMR_RINDE_Pos _U_(16) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Position */ +#define HSMCI_IMR_RINDE_Msk (_U_(0x1) << HSMCI_IMR_RINDE_Pos) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Mask */ +#define HSMCI_IMR_RINDE(value) (HSMCI_IMR_RINDE_Msk & ((value) << HSMCI_IMR_RINDE_Pos)) +#define HSMCI_IMR_RDIRE_Pos _U_(17) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Position */ +#define HSMCI_IMR_RDIRE_Msk (_U_(0x1) << HSMCI_IMR_RDIRE_Pos) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Mask */ +#define HSMCI_IMR_RDIRE(value) (HSMCI_IMR_RDIRE_Msk & ((value) << HSMCI_IMR_RDIRE_Pos)) +#define HSMCI_IMR_RCRCE_Pos _U_(18) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_RCRCE_Msk (_U_(0x1) << HSMCI_IMR_RCRCE_Pos) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_RCRCE(value) (HSMCI_IMR_RCRCE_Msk & ((value) << HSMCI_IMR_RCRCE_Pos)) +#define HSMCI_IMR_RENDE_Pos _U_(19) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Position */ +#define HSMCI_IMR_RENDE_Msk (_U_(0x1) << HSMCI_IMR_RENDE_Pos) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Mask */ +#define HSMCI_IMR_RENDE(value) (HSMCI_IMR_RENDE_Msk & ((value) << HSMCI_IMR_RENDE_Pos)) +#define HSMCI_IMR_RTOE_Pos _U_(20) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_RTOE_Msk (_U_(0x1) << HSMCI_IMR_RTOE_Pos) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_RTOE(value) (HSMCI_IMR_RTOE_Msk & ((value) << HSMCI_IMR_RTOE_Pos)) +#define HSMCI_IMR_DCRCE_Pos _U_(21) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_DCRCE_Msk (_U_(0x1) << HSMCI_IMR_DCRCE_Pos) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_DCRCE(value) (HSMCI_IMR_DCRCE_Msk & ((value) << HSMCI_IMR_DCRCE_Pos)) +#define HSMCI_IMR_DTOE_Pos _U_(22) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_DTOE_Msk (_U_(0x1) << HSMCI_IMR_DTOE_Pos) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_DTOE(value) (HSMCI_IMR_DTOE_Msk & ((value) << HSMCI_IMR_DTOE_Pos)) +#define HSMCI_IMR_CSTOE_Pos _U_(23) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_CSTOE_Msk (_U_(0x1) << HSMCI_IMR_CSTOE_Pos) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_CSTOE(value) (HSMCI_IMR_CSTOE_Msk & ((value) << HSMCI_IMR_CSTOE_Pos)) +#define HSMCI_IMR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Position */ +#define HSMCI_IMR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IMR_BLKOVRE_Pos) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Mask */ +#define HSMCI_IMR_BLKOVRE(value) (HSMCI_IMR_BLKOVRE_Msk & ((value) << HSMCI_IMR_BLKOVRE_Pos)) +#define HSMCI_IMR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Position */ +#define HSMCI_IMR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IMR_FIFOEMPTY_Pos) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Mask */ +#define HSMCI_IMR_FIFOEMPTY(value) (HSMCI_IMR_FIFOEMPTY_Msk & ((value) << HSMCI_IMR_FIFOEMPTY_Pos)) +#define HSMCI_IMR_XFRDONE_Pos _U_(27) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Position */ +#define HSMCI_IMR_XFRDONE_Msk (_U_(0x1) << HSMCI_IMR_XFRDONE_Pos) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Mask */ +#define HSMCI_IMR_XFRDONE(value) (HSMCI_IMR_XFRDONE_Msk & ((value) << HSMCI_IMR_XFRDONE_Pos)) +#define HSMCI_IMR_ACKRCV_Pos _U_(28) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCV_Msk (_U_(0x1) << HSMCI_IMR_ACKRCV_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCV(value) (HSMCI_IMR_ACKRCV_Msk & ((value) << HSMCI_IMR_ACKRCV_Pos)) +#define HSMCI_IMR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IMR_ACKRCVE_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCVE(value) (HSMCI_IMR_ACKRCVE_Msk & ((value) << HSMCI_IMR_ACKRCVE_Pos)) +#define HSMCI_IMR_OVRE_Pos _U_(30) /**< (HSMCI_IMR) Overrun Interrupt Mask Position */ +#define HSMCI_IMR_OVRE_Msk (_U_(0x1) << HSMCI_IMR_OVRE_Pos) /**< (HSMCI_IMR) Overrun Interrupt Mask Mask */ +#define HSMCI_IMR_OVRE(value) (HSMCI_IMR_OVRE_Msk & ((value) << HSMCI_IMR_OVRE_Pos)) +#define HSMCI_IMR_UNRE_Pos _U_(31) /**< (HSMCI_IMR) Underrun Interrupt Mask Position */ +#define HSMCI_IMR_UNRE_Msk (_U_(0x1) << HSMCI_IMR_UNRE_Pos) /**< (HSMCI_IMR) Underrun Interrupt Mask Mask */ +#define HSMCI_IMR_UNRE(value) (HSMCI_IMR_UNRE_Msk & ((value) << HSMCI_IMR_UNRE_Pos)) +#define HSMCI_IMR_Msk _U_(0xFDFF313F) /**< (HSMCI_IMR) Register Mask */ + + +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) (R/W 32) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos _U_(4) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Position */ +#define HSMCI_DMA_CHKSIZE_Msk (_U_(0x7) << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Mask */ +#define HSMCI_DMA_CHKSIZE(value) (HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)) +#define HSMCI_DMA_CHKSIZE_1_Val _U_(0x0) /**< (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2_Val _U_(0x1) /**< (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4_Val _U_(0x2) /**< (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8_Val _U_(0x3) /**< (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16_Val _U_(0x4) /**< (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_CHKSIZE_1 (HSMCI_DMA_CHKSIZE_1_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 1 data available Position */ +#define HSMCI_DMA_CHKSIZE_2 (HSMCI_DMA_CHKSIZE_2_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 2 data available Position */ +#define HSMCI_DMA_CHKSIZE_4 (HSMCI_DMA_CHKSIZE_4_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 4 data available Position */ +#define HSMCI_DMA_CHKSIZE_8 (HSMCI_DMA_CHKSIZE_8_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 8 data available Position */ +#define HSMCI_DMA_CHKSIZE_16 (HSMCI_DMA_CHKSIZE_16_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 16 data available Position */ +#define HSMCI_DMA_DMAEN_Pos _U_(8) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Position */ +#define HSMCI_DMA_DMAEN_Msk (_U_(0x1) << HSMCI_DMA_DMAEN_Pos) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Mask */ +#define HSMCI_DMA_DMAEN(value) (HSMCI_DMA_DMAEN_Msk & ((value) << HSMCI_DMA_DMAEN_Pos)) +#define HSMCI_DMA_Msk _U_(0x00000170) /**< (HSMCI_DMA) Register Mask */ + + +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) (R/W 32) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE_Pos _U_(0) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Position */ +#define HSMCI_CFG_FIFOMODE_Msk (_U_(0x1) << HSMCI_CFG_FIFOMODE_Pos) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Mask */ +#define HSMCI_CFG_FIFOMODE(value) (HSMCI_CFG_FIFOMODE_Msk & ((value) << HSMCI_CFG_FIFOMODE_Pos)) +#define HSMCI_CFG_FERRCTRL_Pos _U_(4) /**< (HSMCI_CFG) Flow Error flag reset control mode Position */ +#define HSMCI_CFG_FERRCTRL_Msk (_U_(0x1) << HSMCI_CFG_FERRCTRL_Pos) /**< (HSMCI_CFG) Flow Error flag reset control mode Mask */ +#define HSMCI_CFG_FERRCTRL(value) (HSMCI_CFG_FERRCTRL_Msk & ((value) << HSMCI_CFG_FERRCTRL_Pos)) +#define HSMCI_CFG_HSMODE_Pos _U_(8) /**< (HSMCI_CFG) High Speed Mode Position */ +#define HSMCI_CFG_HSMODE_Msk (_U_(0x1) << HSMCI_CFG_HSMODE_Pos) /**< (HSMCI_CFG) High Speed Mode Mask */ +#define HSMCI_CFG_HSMODE(value) (HSMCI_CFG_HSMODE_Msk & ((value) << HSMCI_CFG_HSMODE_Pos)) +#define HSMCI_CFG_LSYNC_Pos _U_(12) /**< (HSMCI_CFG) Synchronize on the last block Position */ +#define HSMCI_CFG_LSYNC_Msk (_U_(0x1) << HSMCI_CFG_LSYNC_Pos) /**< (HSMCI_CFG) Synchronize on the last block Mask */ +#define HSMCI_CFG_LSYNC(value) (HSMCI_CFG_LSYNC_Msk & ((value) << HSMCI_CFG_LSYNC_Pos)) +#define HSMCI_CFG_Msk _U_(0x00001111) /**< (HSMCI_CFG) Register Mask */ + + +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN_Pos _U_(0) /**< (HSMCI_WPMR) Write Protect Enable Position */ +#define HSMCI_WPMR_WPEN_Msk (_U_(0x1) << HSMCI_WPMR_WPEN_Pos) /**< (HSMCI_WPMR) Write Protect Enable Mask */ +#define HSMCI_WPMR_WPEN(value) (HSMCI_WPMR_WPEN_Msk & ((value) << HSMCI_WPMR_WPEN_Pos)) +#define HSMCI_WPMR_WPKEY_Pos _U_(8) /**< (HSMCI_WPMR) Write Protect Key Position */ +#define HSMCI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Write Protect Key Mask */ +#define HSMCI_WPMR_WPKEY(value) (HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)) +#define HSMCI_WPMR_WPKEY_PASSWD_Val _U_(0x4D4349) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define HSMCI_WPMR_WPKEY_PASSWD (HSMCI_WPMR_WPKEY_PASSWD_Val << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define HSMCI_WPMR_Msk _U_(0xFFFFFF01) /**< (HSMCI_WPMR) Register Mask */ + + +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS_Pos _U_(0) /**< (HSMCI_WPSR) Write Protection Violation Status Position */ +#define HSMCI_WPSR_WPVS_Msk (_U_(0x1) << HSMCI_WPSR_WPVS_Pos) /**< (HSMCI_WPSR) Write Protection Violation Status Mask */ +#define HSMCI_WPSR_WPVS(value) (HSMCI_WPSR_WPVS_Msk & ((value) << HSMCI_WPSR_WPVS_Pos)) +#define HSMCI_WPSR_WPVSRC_Pos _U_(8) /**< (HSMCI_WPSR) Write Protection Violation Source Position */ +#define HSMCI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << HSMCI_WPSR_WPVSRC_Pos) /**< (HSMCI_WPSR) Write Protection Violation Source Mask */ +#define HSMCI_WPSR_WPVSRC(value) (HSMCI_WPSR_WPVSRC_Msk & ((value) << HSMCI_WPSR_WPVSRC_Pos)) +#define HSMCI_WPSR_Msk _U_(0x00FFFF01) /**< (HSMCI_WPSR) Register Mask */ + + +/* -------- HSMCI_FIFO : (HSMCI Offset: 0x200) (R/W 32) FIFO Memory Aperture0 0 -------- */ +#define HSMCI_FIFO_DATA_Pos _U_(0) /**< (HSMCI_FIFO) Data to Read or Data to Write Position */ +#define HSMCI_FIFO_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_FIFO_DATA_Pos) /**< (HSMCI_FIFO) Data to Read or Data to Write Mask */ +#define HSMCI_FIFO_DATA(value) (HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)) +#define HSMCI_FIFO_Msk _U_(0xFFFFFFFF) /**< (HSMCI_FIFO) Register Mask */ + + +/** \brief HSMCI register offsets definitions */ +#define HSMCI_CR_REG_OFST (0x00) /**< (HSMCI_CR) Control Register Offset */ +#define HSMCI_MR_REG_OFST (0x04) /**< (HSMCI_MR) Mode Register Offset */ +#define HSMCI_DTOR_REG_OFST (0x08) /**< (HSMCI_DTOR) Data Timeout Register Offset */ +#define HSMCI_SDCR_REG_OFST (0x0C) /**< (HSMCI_SDCR) SD/SDIO Card Register Offset */ +#define HSMCI_ARGR_REG_OFST (0x10) /**< (HSMCI_ARGR) Argument Register Offset */ +#define HSMCI_CMDR_REG_OFST (0x14) /**< (HSMCI_CMDR) Command Register Offset */ +#define HSMCI_BLKR_REG_OFST (0x18) /**< (HSMCI_BLKR) Block Register Offset */ +#define HSMCI_CSTOR_REG_OFST (0x1C) /**< (HSMCI_CSTOR) Completion Signal Timeout Register Offset */ +#define HSMCI_RSPR_REG_OFST (0x20) /**< (HSMCI_RSPR) Response Register 0 Offset */ +#define HSMCI_RDR_REG_OFST (0x30) /**< (HSMCI_RDR) Receive Data Register Offset */ +#define HSMCI_TDR_REG_OFST (0x34) /**< (HSMCI_TDR) Transmit Data Register Offset */ +#define HSMCI_SR_REG_OFST (0x40) /**< (HSMCI_SR) Status Register Offset */ +#define HSMCI_IER_REG_OFST (0x44) /**< (HSMCI_IER) Interrupt Enable Register Offset */ +#define HSMCI_IDR_REG_OFST (0x48) /**< (HSMCI_IDR) Interrupt Disable Register Offset */ +#define HSMCI_IMR_REG_OFST (0x4C) /**< (HSMCI_IMR) Interrupt Mask Register Offset */ +#define HSMCI_DMA_REG_OFST (0x50) /**< (HSMCI_DMA) DMA Configuration Register Offset */ +#define HSMCI_CFG_REG_OFST (0x54) /**< (HSMCI_CFG) Configuration Register Offset */ +#define HSMCI_WPMR_REG_OFST (0xE4) /**< (HSMCI_WPMR) Write Protection Mode Register Offset */ +#define HSMCI_WPSR_REG_OFST (0xE8) /**< (HSMCI_WPSR) Write Protection Status Register Offset */ +#define HSMCI_FIFO_REG_OFST (0x200) /**< (HSMCI_FIFO) FIFO Memory Aperture0 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief HSMCI register API structure */ +typedef struct +{ + __O uint32_t HSMCI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t HSMCI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< Offset: 0x08 (R/W 32) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< Offset: 0x0C (R/W 32) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< Offset: 0x10 (R/W 32) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< Offset: 0x14 ( /W 32) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< Offset: 0x18 (R/W 32) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< Offset: 0x1C (R/W 32) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< Offset: 0x20 (R/ 32) Response Register 0 */ + __I uint32_t HSMCI_RDR; /**< Offset: 0x30 (R/ 32) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< Offset: 0x34 ( /W 32) Transmit Data Register */ + __I uint8_t Reserved1[0x08]; + __I uint32_t HSMCI_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O uint32_t HSMCI_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< Offset: 0x50 (R/W 32) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< Offset: 0x54 (R/W 32) Configuration Register */ + __I uint8_t Reserved2[0x8C]; + __IO uint32_t HSMCI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved3[0x114]; + __IO uint32_t HSMCI_FIFO[256]; /**< Offset: 0x200 (R/W 32) FIFO Memory Aperture0 0 */ +} hsmci_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_HSMCI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/icm.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/icm.h new file mode 100644 index 00000000..28ab77d8 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/icm.h @@ -0,0 +1,272 @@ +/** + * \brief Component description for ICM + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_ICM_COMPONENT_H_ +#define _SAME70_ICM_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ICM */ +/* ************************************************************************** */ + +/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */ +#define ICM_CFG_WBDIS_Pos _U_(0) /**< (ICM_CFG) Write Back Disable Position */ +#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */ +#define ICM_CFG_WBDIS(value) (ICM_CFG_WBDIS_Msk & ((value) << ICM_CFG_WBDIS_Pos)) +#define ICM_CFG_EOMDIS_Pos _U_(1) /**< (ICM_CFG) End of Monitoring Disable Position */ +#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */ +#define ICM_CFG_EOMDIS(value) (ICM_CFG_EOMDIS_Msk & ((value) << ICM_CFG_EOMDIS_Pos)) +#define ICM_CFG_SLBDIS_Pos _U_(2) /**< (ICM_CFG) Secondary List Branching Disable Position */ +#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */ +#define ICM_CFG_SLBDIS(value) (ICM_CFG_SLBDIS_Msk & ((value) << ICM_CFG_SLBDIS_Pos)) +#define ICM_CFG_BBC_Pos _U_(4) /**< (ICM_CFG) Bus Burden Control Position */ +#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */ +#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) +#define ICM_CFG_ASCD_Pos _U_(8) /**< (ICM_CFG) Automatic Switch To Compare Digest Position */ +#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */ +#define ICM_CFG_ASCD(value) (ICM_CFG_ASCD_Msk & ((value) << ICM_CFG_ASCD_Pos)) +#define ICM_CFG_DUALBUFF_Pos _U_(9) /**< (ICM_CFG) Dual Input Buffer Position */ +#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */ +#define ICM_CFG_DUALBUFF(value) (ICM_CFG_DUALBUFF_Msk & ((value) << ICM_CFG_DUALBUFF_Pos)) +#define ICM_CFG_UIHASH_Pos _U_(12) /**< (ICM_CFG) User Initial Hash Value Position */ +#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */ +#define ICM_CFG_UIHASH(value) (ICM_CFG_UIHASH_Msk & ((value) << ICM_CFG_UIHASH_Pos)) +#define ICM_CFG_UALGO_Pos _U_(13) /**< (ICM_CFG) User SHA Algorithm Position */ +#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */ +#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) +#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */ +#define ICM_CFG_Msk _U_(0x0000F3F7) /**< (ICM_CFG) Register Mask */ + + +/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control Register -------- */ +#define ICM_CTRL_ENABLE_Pos _U_(0) /**< (ICM_CTRL) ICM Enable Position */ +#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */ +#define ICM_CTRL_ENABLE(value) (ICM_CTRL_ENABLE_Msk & ((value) << ICM_CTRL_ENABLE_Pos)) +#define ICM_CTRL_DISABLE_Pos _U_(1) /**< (ICM_CTRL) ICM Disable Register Position */ +#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */ +#define ICM_CTRL_DISABLE(value) (ICM_CTRL_DISABLE_Msk & ((value) << ICM_CTRL_DISABLE_Pos)) +#define ICM_CTRL_SWRST_Pos _U_(2) /**< (ICM_CTRL) Software Reset Position */ +#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */ +#define ICM_CTRL_SWRST(value) (ICM_CTRL_SWRST_Msk & ((value) << ICM_CTRL_SWRST_Pos)) +#define ICM_CTRL_REHASH_Pos _U_(4) /**< (ICM_CTRL) Recompute Internal Hash Position */ +#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */ +#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)) +#define ICM_CTRL_RMDIS_Pos _U_(8) /**< (ICM_CTRL) Region Monitoring Disable Position */ +#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */ +#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)) +#define ICM_CTRL_RMEN_Pos _U_(12) /**< (ICM_CTRL) Region Monitoring Enable Position */ +#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */ +#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)) +#define ICM_CTRL_Msk _U_(0x0000FFF7) /**< (ICM_CTRL) Register Mask */ + + +/* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status Register -------- */ +#define ICM_SR_ENABLE_Pos _U_(0) /**< (ICM_SR) ICM Controller Enable Register Position */ +#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */ +#define ICM_SR_ENABLE(value) (ICM_SR_ENABLE_Msk & ((value) << ICM_SR_ENABLE_Pos)) +#define ICM_SR_RAWRMDIS_Pos _U_(8) /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */ +#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */ +#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)) +#define ICM_SR_RMDIS_Pos _U_(12) /**< (ICM_SR) Region Monitoring Disabled Status Position */ +#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */ +#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)) +#define ICM_SR_Msk _U_(0x0000FF01) /**< (ICM_SR) Register Mask */ + + +/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos _U_(0) /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */ +#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */ +#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) +#define ICM_IER_RDM_Pos _U_(4) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */ +#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */ +#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) +#define ICM_IER_RBE_Pos _U_(8) /**< (ICM_IER) Region Bus Error Interrupt Enable Position */ +#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */ +#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) +#define ICM_IER_RWC_Pos _U_(12) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */ +#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */ +#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) +#define ICM_IER_REC_Pos _U_(16) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */ +#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */ +#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) +#define ICM_IER_RSU_Pos _U_(20) /**< (ICM_IER) Region Status Updated Interrupt Disable Position */ +#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */ +#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) +#define ICM_IER_URAD_Pos _U_(24) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */ +#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */ +#define ICM_IER_URAD(value) (ICM_IER_URAD_Msk & ((value) << ICM_IER_URAD_Pos)) +#define ICM_IER_Msk _U_(0x01FFFFFF) /**< (ICM_IER) Register Mask */ + + +/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos _U_(0) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */ +#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */ +#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) +#define ICM_IDR_RDM_Pos _U_(4) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */ +#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */ +#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) +#define ICM_IDR_RBE_Pos _U_(8) /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */ +#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */ +#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) +#define ICM_IDR_RWC_Pos _U_(12) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */ +#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */ +#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)) +#define ICM_IDR_REC_Pos _U_(16) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */ +#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */ +#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)) +#define ICM_IDR_RSU_Pos _U_(20) /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */ +#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */ +#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)) +#define ICM_IDR_URAD_Pos _U_(24) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */ +#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */ +#define ICM_IDR_URAD(value) (ICM_IDR_URAD_Msk & ((value) << ICM_IDR_URAD_Pos)) +#define ICM_IDR_Msk _U_(0x01FFFFFF) /**< (ICM_IDR) Register Mask */ + + +/* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos _U_(0) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */ +#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */ +#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos)) +#define ICM_IMR_RDM_Pos _U_(4) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */ +#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */ +#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos)) +#define ICM_IMR_RBE_Pos _U_(8) /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */ +#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */ +#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos)) +#define ICM_IMR_RWC_Pos _U_(12) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */ +#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos)) +#define ICM_IMR_REC_Pos _U_(16) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */ +#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos)) +#define ICM_IMR_RSU_Pos _U_(20) /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */ +#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */ +#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos)) +#define ICM_IMR_URAD_Pos _U_(24) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */ +#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */ +#define ICM_IMR_URAD(value) (ICM_IMR_URAD_Msk & ((value) << ICM_IMR_URAD_Pos)) +#define ICM_IMR_Msk _U_(0x01FFFFFF) /**< (ICM_IMR) Register Mask */ + + +/* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos _U_(0) /**< (ICM_ISR) Region Hash Completed Position */ +#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */ +#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos)) +#define ICM_ISR_RDM_Pos _U_(4) /**< (ICM_ISR) Region Digest Mismatch Position */ +#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */ +#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos)) +#define ICM_ISR_RBE_Pos _U_(8) /**< (ICM_ISR) Region Bus Error Position */ +#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */ +#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos)) +#define ICM_ISR_RWC_Pos _U_(12) /**< (ICM_ISR) Region Wrap Condition Detected Position */ +#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */ +#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos)) +#define ICM_ISR_REC_Pos _U_(16) /**< (ICM_ISR) Region End bit Condition Detected Position */ +#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */ +#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos)) +#define ICM_ISR_RSU_Pos _U_(20) /**< (ICM_ISR) Region Status Updated Detected Position */ +#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */ +#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos)) +#define ICM_ISR_URAD_Pos _U_(24) /**< (ICM_ISR) Undefined Register Access Detection Status Position */ +#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */ +#define ICM_ISR_URAD(value) (ICM_ISR_URAD_Msk & ((value) << ICM_ISR_URAD_Pos)) +#define ICM_ISR_Msk _U_(0x01FFFFFF) /**< (ICM_ISR) Register Mask */ + + +/* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos _U_(0) /**< (ICM_UASR) Undefined Register Access Trace Position */ +#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */ +#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos)) +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */ +#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */ +#define ICM_UASR_Msk _U_(0x00000007) /**< (ICM_UASR) Register Mask */ + + +/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos _U_(6) /**< (ICM_DSCR) Descriptor Area Start Address Position */ +#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */ +#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)) +#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */ + + +/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos _U_(7) /**< (ICM_HASH) Hash Area Start Address Position */ +#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */ +#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)) +#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */ + + +/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value 0 Register 0 -------- */ +#define ICM_UIHVAL_VAL_Pos _U_(0) /**< (ICM_UIHVAL) Initial Hash Value Position */ +#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */ +#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)) +#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */ + + +/** \brief ICM register offsets definitions */ +#define ICM_CFG_REG_OFST (0x00) /**< (ICM_CFG) Configuration Register Offset */ +#define ICM_CTRL_REG_OFST (0x04) /**< (ICM_CTRL) Control Register Offset */ +#define ICM_SR_REG_OFST (0x08) /**< (ICM_SR) Status Register Offset */ +#define ICM_IER_REG_OFST (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */ +#define ICM_IDR_REG_OFST (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */ +#define ICM_IMR_REG_OFST (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */ +#define ICM_ISR_REG_OFST (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */ +#define ICM_UASR_REG_OFST (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */ +#define ICM_DSCR_REG_OFST (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */ +#define ICM_HASH_REG_OFST (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */ +#define ICM_UIHVAL_REG_OFST (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ICM register API structure */ +typedef struct +{ + __IO uint32_t ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */ + __O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */ + __I uint32_t ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */ +} icm_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ICM_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/isi.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/isi.h new file mode 100644 index 00000000..c3e741c2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/isi.h @@ -0,0 +1,543 @@ +/** + * \brief Component description for ISI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_ISI_COMPONENT_H_ +#define _SAME70_ISI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ISI */ +/* ************************************************************************** */ + +/* -------- ISI_CFG1 : (ISI Offset: 0x00) (R/W 32) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL_Pos _U_(2) /**< (ISI_CFG1) Horizontal Synchronization Polarity Position */ +#define ISI_CFG1_HSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_HSYNC_POL_Pos) /**< (ISI_CFG1) Horizontal Synchronization Polarity Mask */ +#define ISI_CFG1_HSYNC_POL(value) (ISI_CFG1_HSYNC_POL_Msk & ((value) << ISI_CFG1_HSYNC_POL_Pos)) +#define ISI_CFG1_VSYNC_POL_Pos _U_(3) /**< (ISI_CFG1) Vertical Synchronization Polarity Position */ +#define ISI_CFG1_VSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_VSYNC_POL_Pos) /**< (ISI_CFG1) Vertical Synchronization Polarity Mask */ +#define ISI_CFG1_VSYNC_POL(value) (ISI_CFG1_VSYNC_POL_Msk & ((value) << ISI_CFG1_VSYNC_POL_Pos)) +#define ISI_CFG1_PIXCLK_POL_Pos _U_(4) /**< (ISI_CFG1) Pixel Clock Polarity Position */ +#define ISI_CFG1_PIXCLK_POL_Msk (_U_(0x1) << ISI_CFG1_PIXCLK_POL_Pos) /**< (ISI_CFG1) Pixel Clock Polarity Mask */ +#define ISI_CFG1_PIXCLK_POL(value) (ISI_CFG1_PIXCLK_POL_Msk & ((value) << ISI_CFG1_PIXCLK_POL_Pos)) +#define ISI_CFG1_GRAYLE_Pos _U_(5) /**< (ISI_CFG1) Grayscale Little Endian Position */ +#define ISI_CFG1_GRAYLE_Msk (_U_(0x1) << ISI_CFG1_GRAYLE_Pos) /**< (ISI_CFG1) Grayscale Little Endian Mask */ +#define ISI_CFG1_GRAYLE(value) (ISI_CFG1_GRAYLE_Msk & ((value) << ISI_CFG1_GRAYLE_Pos)) +#define ISI_CFG1_EMB_SYNC_Pos _U_(6) /**< (ISI_CFG1) Embedded Synchronization Position */ +#define ISI_CFG1_EMB_SYNC_Msk (_U_(0x1) << ISI_CFG1_EMB_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Mask */ +#define ISI_CFG1_EMB_SYNC(value) (ISI_CFG1_EMB_SYNC_Msk & ((value) << ISI_CFG1_EMB_SYNC_Pos)) +#define ISI_CFG1_CRC_SYNC_Pos _U_(7) /**< (ISI_CFG1) Embedded Synchronization Correction Position */ +#define ISI_CFG1_CRC_SYNC_Msk (_U_(0x1) << ISI_CFG1_CRC_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Correction Mask */ +#define ISI_CFG1_CRC_SYNC(value) (ISI_CFG1_CRC_SYNC_Msk & ((value) << ISI_CFG1_CRC_SYNC_Pos)) +#define ISI_CFG1_FRATE_Pos _U_(8) /**< (ISI_CFG1) Frame Rate [0..7] Position */ +#define ISI_CFG1_FRATE_Msk (_U_(0x7) << ISI_CFG1_FRATE_Pos) /**< (ISI_CFG1) Frame Rate [0..7] Mask */ +#define ISI_CFG1_FRATE(value) (ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)) +#define ISI_CFG1_DISCR_Pos _U_(11) /**< (ISI_CFG1) Disable Codec Request Position */ +#define ISI_CFG1_DISCR_Msk (_U_(0x1) << ISI_CFG1_DISCR_Pos) /**< (ISI_CFG1) Disable Codec Request Mask */ +#define ISI_CFG1_DISCR(value) (ISI_CFG1_DISCR_Msk & ((value) << ISI_CFG1_DISCR_Pos)) +#define ISI_CFG1_FULL_Pos _U_(12) /**< (ISI_CFG1) Full Mode is Allowed Position */ +#define ISI_CFG1_FULL_Msk (_U_(0x1) << ISI_CFG1_FULL_Pos) /**< (ISI_CFG1) Full Mode is Allowed Mask */ +#define ISI_CFG1_FULL(value) (ISI_CFG1_FULL_Msk & ((value) << ISI_CFG1_FULL_Pos)) +#define ISI_CFG1_THMASK_Pos _U_(13) /**< (ISI_CFG1) Threshold Mask Position */ +#define ISI_CFG1_THMASK_Msk (_U_(0x3) << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Threshold Mask Mask */ +#define ISI_CFG1_THMASK(value) (ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)) +#define ISI_CFG1_THMASK_BEATS_4_Val _U_(0x0) /**< (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8_Val _U_(0x1) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16_Val _U_(0x2) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_4 (ISI_CFG1_THMASK_BEATS_4_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_8 (ISI_CFG1_THMASK_BEATS_8_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_16 (ISI_CFG1_THMASK_BEATS_16_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed Position */ +#define ISI_CFG1_SLD_Pos _U_(16) /**< (ISI_CFG1) Start of Line Delay Position */ +#define ISI_CFG1_SLD_Msk (_U_(0xFF) << ISI_CFG1_SLD_Pos) /**< (ISI_CFG1) Start of Line Delay Mask */ +#define ISI_CFG1_SLD(value) (ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)) +#define ISI_CFG1_SFD_Pos _U_(24) /**< (ISI_CFG1) Start of Frame Delay Position */ +#define ISI_CFG1_SFD_Msk (_U_(0xFF) << ISI_CFG1_SFD_Pos) /**< (ISI_CFG1) Start of Frame Delay Mask */ +#define ISI_CFG1_SFD(value) (ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)) +#define ISI_CFG1_Msk _U_(0xFFFF7FFC) /**< (ISI_CFG1) Register Mask */ + + +/* -------- ISI_CFG2 : (ISI Offset: 0x04) (R/W 32) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos _U_(0) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_VSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_VSIZE_Pos) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_VSIZE(value) (ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)) +#define ISI_CFG2_GS_MODE_Pos _U_(11) /**< (ISI_CFG2) Grayscale Pixel Format Mode Position */ +#define ISI_CFG2_GS_MODE_Msk (_U_(0x1) << ISI_CFG2_GS_MODE_Pos) /**< (ISI_CFG2) Grayscale Pixel Format Mode Mask */ +#define ISI_CFG2_GS_MODE(value) (ISI_CFG2_GS_MODE_Msk & ((value) << ISI_CFG2_GS_MODE_Pos)) +#define ISI_CFG2_RGB_MODE_Pos _U_(12) /**< (ISI_CFG2) RGB Input Mode Position */ +#define ISI_CFG2_RGB_MODE_Msk (_U_(0x1) << ISI_CFG2_RGB_MODE_Pos) /**< (ISI_CFG2) RGB Input Mode Mask */ +#define ISI_CFG2_RGB_MODE(value) (ISI_CFG2_RGB_MODE_Msk & ((value) << ISI_CFG2_RGB_MODE_Pos)) +#define ISI_CFG2_GRAYSCALE_Pos _U_(13) /**< (ISI_CFG2) Grayscale Mode Format Enable Position */ +#define ISI_CFG2_GRAYSCALE_Msk (_U_(0x1) << ISI_CFG2_GRAYSCALE_Pos) /**< (ISI_CFG2) Grayscale Mode Format Enable Mask */ +#define ISI_CFG2_GRAYSCALE(value) (ISI_CFG2_GRAYSCALE_Msk & ((value) << ISI_CFG2_GRAYSCALE_Pos)) +#define ISI_CFG2_RGB_SWAP_Pos _U_(14) /**< (ISI_CFG2) RGB Format Swap Mode Position */ +#define ISI_CFG2_RGB_SWAP_Msk (_U_(0x1) << ISI_CFG2_RGB_SWAP_Pos) /**< (ISI_CFG2) RGB Format Swap Mode Mask */ +#define ISI_CFG2_RGB_SWAP(value) (ISI_CFG2_RGB_SWAP_Msk & ((value) << ISI_CFG2_RGB_SWAP_Pos)) +#define ISI_CFG2_COL_SPACE_Pos _U_(15) /**< (ISI_CFG2) Color Space for the Image Data Position */ +#define ISI_CFG2_COL_SPACE_Msk (_U_(0x1) << ISI_CFG2_COL_SPACE_Pos) /**< (ISI_CFG2) Color Space for the Image Data Mask */ +#define ISI_CFG2_COL_SPACE(value) (ISI_CFG2_COL_SPACE_Msk & ((value) << ISI_CFG2_COL_SPACE_Pos)) +#define ISI_CFG2_IM_HSIZE_Pos _U_(16) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_HSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_HSIZE_Pos) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_HSIZE(value) (ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)) +#define ISI_CFG2_YCC_SWAP_Pos _U_(28) /**< (ISI_CFG2) YCrCb Format Swap Mode Position */ +#define ISI_CFG2_YCC_SWAP_Msk (_U_(0x3) << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) YCrCb Format Swap Mode Mask */ +#define ISI_CFG2_YCC_SWAP(value) (ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)) +#define ISI_CFG2_YCC_SWAP_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_YCC_SWAP_DEFAULT (ISI_CFG2_YCC_SWAP_DEFAULT_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE1 (ISI_CFG2_YCC_SWAP_MODE1_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE2 (ISI_CFG2_YCC_SWAP_MODE2_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) Position */ +#define ISI_CFG2_YCC_SWAP_MODE3 (ISI_CFG2_YCC_SWAP_MODE3_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) Position */ +#define ISI_CFG2_RGB_CFG_Pos _U_(30) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Position */ +#define ISI_CFG2_RGB_CFG_Msk (_U_(0x3) << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Mask */ +#define ISI_CFG2_RGB_CFG(value) (ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)) +#define ISI_CFG2_RGB_CFG_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +#define ISI_CFG2_RGB_CFG_DEFAULT (ISI_CFG2_RGB_CFG_DEFAULT_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B Position */ +#define ISI_CFG2_RGB_CFG_MODE1 (ISI_CFG2_RGB_CFG_MODE1_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R Position */ +#define ISI_CFG2_RGB_CFG_MODE2 (ISI_CFG2_RGB_CFG_MODE2_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) Position */ +#define ISI_CFG2_RGB_CFG_MODE3 (ISI_CFG2_RGB_CFG_MODE3_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) Position */ +#define ISI_CFG2_Msk _U_(0xF7FFFFFF) /**< (ISI_CFG2) Register Mask */ + + +/* -------- ISI_PSIZE : (ISI Offset: 0x08) (R/W 32) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos _U_(0) /**< (ISI_PSIZE) Vertical Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_VSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_VSIZE_Pos) /**< (ISI_PSIZE) Vertical Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_VSIZE(value) (ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)) +#define ISI_PSIZE_PREV_HSIZE_Pos _U_(16) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_HSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_HSIZE_Pos) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_HSIZE(value) (ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)) +#define ISI_PSIZE_Msk _U_(0x03FF03FF) /**< (ISI_PSIZE) Register Mask */ + + +/* -------- ISI_PDECF : (ISI Offset: 0x0C) (R/W 32) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos _U_(0) /**< (ISI_PDECF) Decimation Factor Position */ +#define ISI_PDECF_DEC_FACTOR_Msk (_U_(0xFF) << ISI_PDECF_DEC_FACTOR_Pos) /**< (ISI_PDECF) Decimation Factor Mask */ +#define ISI_PDECF_DEC_FACTOR(value) (ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)) +#define ISI_PDECF_Msk _U_(0x000000FF) /**< (ISI_PDECF) Register Mask */ + + +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos _U_(0) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_Y2R_SET0_C0_Msk (_U_(0xFF) << ISI_Y2R_SET0_C0_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_Y2R_SET0_C0(value) (ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)) +#define ISI_Y2R_SET0_C1_Pos _U_(8) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_Y2R_SET0_C1_Msk (_U_(0xFF) << ISI_Y2R_SET0_C1_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_Y2R_SET0_C1(value) (ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)) +#define ISI_Y2R_SET0_C2_Pos _U_(16) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_Y2R_SET0_C2_Msk (_U_(0xFF) << ISI_Y2R_SET0_C2_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_Y2R_SET0_C2(value) (ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)) +#define ISI_Y2R_SET0_C3_Pos _U_(24) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_Y2R_SET0_C3_Msk (_U_(0xFF) << ISI_Y2R_SET0_C3_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_Y2R_SET0_C3(value) (ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)) +#define ISI_Y2R_SET0_Msk _U_(0xFFFFFFFF) /**< (ISI_Y2R_SET0) Register Mask */ + + +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos _U_(0) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_Y2R_SET1_C4_Msk (_U_(0x1FF) << ISI_Y2R_SET1_C4_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_Y2R_SET1_C4(value) (ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)) +#define ISI_Y2R_SET1_Yoff_Pos _U_(12) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Position */ +#define ISI_Y2R_SET1_Yoff_Msk (_U_(0x1) << ISI_Y2R_SET1_Yoff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Mask */ +#define ISI_Y2R_SET1_Yoff(value) (ISI_Y2R_SET1_Yoff_Msk & ((value) << ISI_Y2R_SET1_Yoff_Pos)) +#define ISI_Y2R_SET1_Croff_Pos _U_(13) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Croff_Msk (_U_(0x1) << ISI_Y2R_SET1_Croff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Croff(value) (ISI_Y2R_SET1_Croff_Msk & ((value) << ISI_Y2R_SET1_Croff_Pos)) +#define ISI_Y2R_SET1_Cboff_Pos _U_(14) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Cboff_Msk (_U_(0x1) << ISI_Y2R_SET1_Cboff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Cboff(value) (ISI_Y2R_SET1_Cboff_Msk & ((value) << ISI_Y2R_SET1_Cboff_Pos)) +#define ISI_Y2R_SET1_Msk _U_(0x000071FF) /**< (ISI_Y2R_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos _U_(0) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_R2Y_SET0_C0_Msk (_U_(0x7F) << ISI_R2Y_SET0_C0_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_R2Y_SET0_C0(value) (ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)) +#define ISI_R2Y_SET0_C1_Pos _U_(8) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_R2Y_SET0_C1_Msk (_U_(0x7F) << ISI_R2Y_SET0_C1_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_R2Y_SET0_C1(value) (ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)) +#define ISI_R2Y_SET0_C2_Pos _U_(16) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_R2Y_SET0_C2_Msk (_U_(0x7F) << ISI_R2Y_SET0_C2_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_R2Y_SET0_C2(value) (ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)) +#define ISI_R2Y_SET0_Roff_Pos _U_(24) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Position */ +#define ISI_R2Y_SET0_Roff_Msk (_U_(0x1) << ISI_R2Y_SET0_Roff_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Mask */ +#define ISI_R2Y_SET0_Roff(value) (ISI_R2Y_SET0_Roff_Msk & ((value) << ISI_R2Y_SET0_Roff_Pos)) +#define ISI_R2Y_SET0_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET0) Register Mask */ + + +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos _U_(0) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_R2Y_SET1_C3_Msk (_U_(0x7F) << ISI_R2Y_SET1_C3_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_R2Y_SET1_C3(value) (ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)) +#define ISI_R2Y_SET1_C4_Pos _U_(8) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_R2Y_SET1_C4_Msk (_U_(0x7F) << ISI_R2Y_SET1_C4_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_R2Y_SET1_C4(value) (ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)) +#define ISI_R2Y_SET1_C5_Pos _U_(16) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Position */ +#define ISI_R2Y_SET1_C5_Msk (_U_(0x7F) << ISI_R2Y_SET1_C5_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Mask */ +#define ISI_R2Y_SET1_C5(value) (ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)) +#define ISI_R2Y_SET1_Goff_Pos _U_(24) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Position */ +#define ISI_R2Y_SET1_Goff_Msk (_U_(0x1) << ISI_R2Y_SET1_Goff_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Mask */ +#define ISI_R2Y_SET1_Goff(value) (ISI_R2Y_SET1_Goff_Msk & ((value) << ISI_R2Y_SET1_Goff_Pos)) +#define ISI_R2Y_SET1_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos _U_(0) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Position */ +#define ISI_R2Y_SET2_C6_Msk (_U_(0x7F) << ISI_R2Y_SET2_C6_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Mask */ +#define ISI_R2Y_SET2_C6(value) (ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)) +#define ISI_R2Y_SET2_C7_Pos _U_(8) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Position */ +#define ISI_R2Y_SET2_C7_Msk (_U_(0x7F) << ISI_R2Y_SET2_C7_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Mask */ +#define ISI_R2Y_SET2_C7(value) (ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)) +#define ISI_R2Y_SET2_C8_Pos _U_(16) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Position */ +#define ISI_R2Y_SET2_C8_Msk (_U_(0x7F) << ISI_R2Y_SET2_C8_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Mask */ +#define ISI_R2Y_SET2_C8(value) (ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)) +#define ISI_R2Y_SET2_Boff_Pos _U_(24) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Position */ +#define ISI_R2Y_SET2_Boff_Msk (_U_(0x1) << ISI_R2Y_SET2_Boff_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Mask */ +#define ISI_R2Y_SET2_Boff(value) (ISI_R2Y_SET2_Boff_Msk & ((value) << ISI_R2Y_SET2_Boff_Pos)) +#define ISI_R2Y_SET2_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET2) Register Mask */ + + +/* -------- ISI_CR : (ISI Offset: 0x24) ( /W 32) ISI Control Register -------- */ +#define ISI_CR_ISI_EN_Pos _U_(0) /**< (ISI_CR) ISI Module Enable Request Position */ +#define ISI_CR_ISI_EN_Msk (_U_(0x1) << ISI_CR_ISI_EN_Pos) /**< (ISI_CR) ISI Module Enable Request Mask */ +#define ISI_CR_ISI_EN(value) (ISI_CR_ISI_EN_Msk & ((value) << ISI_CR_ISI_EN_Pos)) +#define ISI_CR_ISI_DIS_Pos _U_(1) /**< (ISI_CR) ISI Module Disable Request Position */ +#define ISI_CR_ISI_DIS_Msk (_U_(0x1) << ISI_CR_ISI_DIS_Pos) /**< (ISI_CR) ISI Module Disable Request Mask */ +#define ISI_CR_ISI_DIS(value) (ISI_CR_ISI_DIS_Msk & ((value) << ISI_CR_ISI_DIS_Pos)) +#define ISI_CR_ISI_SRST_Pos _U_(2) /**< (ISI_CR) ISI Software Reset Request Position */ +#define ISI_CR_ISI_SRST_Msk (_U_(0x1) << ISI_CR_ISI_SRST_Pos) /**< (ISI_CR) ISI Software Reset Request Mask */ +#define ISI_CR_ISI_SRST(value) (ISI_CR_ISI_SRST_Msk & ((value) << ISI_CR_ISI_SRST_Pos)) +#define ISI_CR_ISI_CDC_Pos _U_(8) /**< (ISI_CR) ISI Codec Request Position */ +#define ISI_CR_ISI_CDC_Msk (_U_(0x1) << ISI_CR_ISI_CDC_Pos) /**< (ISI_CR) ISI Codec Request Mask */ +#define ISI_CR_ISI_CDC(value) (ISI_CR_ISI_CDC_Msk & ((value) << ISI_CR_ISI_CDC_Pos)) +#define ISI_CR_Msk _U_(0x00000107) /**< (ISI_CR) Register Mask */ + + +/* -------- ISI_SR : (ISI Offset: 0x28) ( R/ 32) ISI Status Register -------- */ +#define ISI_SR_ENABLE_Pos _U_(0) /**< (ISI_SR) Module Enable Position */ +#define ISI_SR_ENABLE_Msk (_U_(0x1) << ISI_SR_ENABLE_Pos) /**< (ISI_SR) Module Enable Mask */ +#define ISI_SR_ENABLE(value) (ISI_SR_ENABLE_Msk & ((value) << ISI_SR_ENABLE_Pos)) +#define ISI_SR_DIS_DONE_Pos _U_(1) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Position */ +#define ISI_SR_DIS_DONE_Msk (_U_(0x1) << ISI_SR_DIS_DONE_Pos) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Mask */ +#define ISI_SR_DIS_DONE(value) (ISI_SR_DIS_DONE_Msk & ((value) << ISI_SR_DIS_DONE_Pos)) +#define ISI_SR_SRST_Pos _U_(2) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Position */ +#define ISI_SR_SRST_Msk (_U_(0x1) << ISI_SR_SRST_Pos) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Mask */ +#define ISI_SR_SRST(value) (ISI_SR_SRST_Msk & ((value) << ISI_SR_SRST_Pos)) +#define ISI_SR_CDC_PND_Pos _U_(8) /**< (ISI_SR) Pending Codec Request Position */ +#define ISI_SR_CDC_PND_Msk (_U_(0x1) << ISI_SR_CDC_PND_Pos) /**< (ISI_SR) Pending Codec Request Mask */ +#define ISI_SR_CDC_PND(value) (ISI_SR_CDC_PND_Msk & ((value) << ISI_SR_CDC_PND_Pos)) +#define ISI_SR_VSYNC_Pos _U_(10) /**< (ISI_SR) Vertical Synchronization (cleared on read) Position */ +#define ISI_SR_VSYNC_Msk (_U_(0x1) << ISI_SR_VSYNC_Pos) /**< (ISI_SR) Vertical Synchronization (cleared on read) Mask */ +#define ISI_SR_VSYNC(value) (ISI_SR_VSYNC_Msk & ((value) << ISI_SR_VSYNC_Pos)) +#define ISI_SR_PXFR_DONE_Pos _U_(16) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_PXFR_DONE_Msk (_U_(0x1) << ISI_SR_PXFR_DONE_Pos) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_PXFR_DONE(value) (ISI_SR_PXFR_DONE_Msk & ((value) << ISI_SR_PXFR_DONE_Pos)) +#define ISI_SR_CXFR_DONE_Pos _U_(17) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_CXFR_DONE_Msk (_U_(0x1) << ISI_SR_CXFR_DONE_Pos) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_CXFR_DONE(value) (ISI_SR_CXFR_DONE_Msk & ((value) << ISI_SR_CXFR_DONE_Pos)) +#define ISI_SR_SIP_Pos _U_(19) /**< (ISI_SR) Synchronization in Progress Position */ +#define ISI_SR_SIP_Msk (_U_(0x1) << ISI_SR_SIP_Pos) /**< (ISI_SR) Synchronization in Progress Mask */ +#define ISI_SR_SIP(value) (ISI_SR_SIP_Msk & ((value) << ISI_SR_SIP_Pos)) +#define ISI_SR_P_OVR_Pos _U_(24) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Position */ +#define ISI_SR_P_OVR_Msk (_U_(0x1) << ISI_SR_P_OVR_Pos) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_P_OVR(value) (ISI_SR_P_OVR_Msk & ((value) << ISI_SR_P_OVR_Pos)) +#define ISI_SR_C_OVR_Pos _U_(25) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Position */ +#define ISI_SR_C_OVR_Msk (_U_(0x1) << ISI_SR_C_OVR_Pos) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_C_OVR(value) (ISI_SR_C_OVR_Msk & ((value) << ISI_SR_C_OVR_Pos)) +#define ISI_SR_CRC_ERR_Pos _U_(26) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Position */ +#define ISI_SR_CRC_ERR_Msk (_U_(0x1) << ISI_SR_CRC_ERR_Pos) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Mask */ +#define ISI_SR_CRC_ERR(value) (ISI_SR_CRC_ERR_Msk & ((value) << ISI_SR_CRC_ERR_Pos)) +#define ISI_SR_FR_OVR_Pos _U_(27) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Position */ +#define ISI_SR_FR_OVR_Msk (_U_(0x1) << ISI_SR_FR_OVR_Pos) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Mask */ +#define ISI_SR_FR_OVR(value) (ISI_SR_FR_OVR_Msk & ((value) << ISI_SR_FR_OVR_Pos)) +#define ISI_SR_Msk _U_(0x0F0B0507) /**< (ISI_SR) Register Mask */ + + +/* -------- ISI_IER : (ISI Offset: 0x2C) ( /W 32) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE_Pos _U_(1) /**< (ISI_IER) Disable Done Interrupt Enable Position */ +#define ISI_IER_DIS_DONE_Msk (_U_(0x1) << ISI_IER_DIS_DONE_Pos) /**< (ISI_IER) Disable Done Interrupt Enable Mask */ +#define ISI_IER_DIS_DONE(value) (ISI_IER_DIS_DONE_Msk & ((value) << ISI_IER_DIS_DONE_Pos)) +#define ISI_IER_SRST_Pos _U_(2) /**< (ISI_IER) Software Reset Interrupt Enable Position */ +#define ISI_IER_SRST_Msk (_U_(0x1) << ISI_IER_SRST_Pos) /**< (ISI_IER) Software Reset Interrupt Enable Mask */ +#define ISI_IER_SRST(value) (ISI_IER_SRST_Msk & ((value) << ISI_IER_SRST_Pos)) +#define ISI_IER_VSYNC_Pos _U_(10) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Position */ +#define ISI_IER_VSYNC_Msk (_U_(0x1) << ISI_IER_VSYNC_Pos) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Mask */ +#define ISI_IER_VSYNC(value) (ISI_IER_VSYNC_Msk & ((value) << ISI_IER_VSYNC_Pos)) +#define ISI_IER_PXFR_DONE_Pos _U_(16) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_PXFR_DONE_Msk (_U_(0x1) << ISI_IER_PXFR_DONE_Pos) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_PXFR_DONE(value) (ISI_IER_PXFR_DONE_Msk & ((value) << ISI_IER_PXFR_DONE_Pos)) +#define ISI_IER_CXFR_DONE_Pos _U_(17) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_CXFR_DONE_Msk (_U_(0x1) << ISI_IER_CXFR_DONE_Pos) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_CXFR_DONE(value) (ISI_IER_CXFR_DONE_Msk & ((value) << ISI_IER_CXFR_DONE_Pos)) +#define ISI_IER_P_OVR_Pos _U_(24) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_P_OVR_Msk (_U_(0x1) << ISI_IER_P_OVR_Pos) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_P_OVR(value) (ISI_IER_P_OVR_Msk & ((value) << ISI_IER_P_OVR_Pos)) +#define ISI_IER_C_OVR_Pos _U_(25) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_C_OVR_Msk (_U_(0x1) << ISI_IER_C_OVR_Pos) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_C_OVR(value) (ISI_IER_C_OVR_Msk & ((value) << ISI_IER_C_OVR_Pos)) +#define ISI_IER_CRC_ERR_Pos _U_(26) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Position */ +#define ISI_IER_CRC_ERR_Msk (_U_(0x1) << ISI_IER_CRC_ERR_Pos) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Mask */ +#define ISI_IER_CRC_ERR(value) (ISI_IER_CRC_ERR_Msk & ((value) << ISI_IER_CRC_ERR_Pos)) +#define ISI_IER_FR_OVR_Pos _U_(27) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Position */ +#define ISI_IER_FR_OVR_Msk (_U_(0x1) << ISI_IER_FR_OVR_Pos) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Mask */ +#define ISI_IER_FR_OVR(value) (ISI_IER_FR_OVR_Msk & ((value) << ISI_IER_FR_OVR_Pos)) +#define ISI_IER_Msk _U_(0x0F030406) /**< (ISI_IER) Register Mask */ + + +/* -------- ISI_IDR : (ISI Offset: 0x30) ( /W 32) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE_Pos _U_(1) /**< (ISI_IDR) Disable Done Interrupt Disable Position */ +#define ISI_IDR_DIS_DONE_Msk (_U_(0x1) << ISI_IDR_DIS_DONE_Pos) /**< (ISI_IDR) Disable Done Interrupt Disable Mask */ +#define ISI_IDR_DIS_DONE(value) (ISI_IDR_DIS_DONE_Msk & ((value) << ISI_IDR_DIS_DONE_Pos)) +#define ISI_IDR_SRST_Pos _U_(2) /**< (ISI_IDR) Software Reset Interrupt Disable Position */ +#define ISI_IDR_SRST_Msk (_U_(0x1) << ISI_IDR_SRST_Pos) /**< (ISI_IDR) Software Reset Interrupt Disable Mask */ +#define ISI_IDR_SRST(value) (ISI_IDR_SRST_Msk & ((value) << ISI_IDR_SRST_Pos)) +#define ISI_IDR_VSYNC_Pos _U_(10) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Position */ +#define ISI_IDR_VSYNC_Msk (_U_(0x1) << ISI_IDR_VSYNC_Pos) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Mask */ +#define ISI_IDR_VSYNC(value) (ISI_IDR_VSYNC_Msk & ((value) << ISI_IDR_VSYNC_Pos)) +#define ISI_IDR_PXFR_DONE_Pos _U_(16) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_PXFR_DONE_Msk (_U_(0x1) << ISI_IDR_PXFR_DONE_Pos) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_PXFR_DONE(value) (ISI_IDR_PXFR_DONE_Msk & ((value) << ISI_IDR_PXFR_DONE_Pos)) +#define ISI_IDR_CXFR_DONE_Pos _U_(17) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_CXFR_DONE_Msk (_U_(0x1) << ISI_IDR_CXFR_DONE_Pos) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_CXFR_DONE(value) (ISI_IDR_CXFR_DONE_Msk & ((value) << ISI_IDR_CXFR_DONE_Pos)) +#define ISI_IDR_P_OVR_Pos _U_(24) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_P_OVR_Msk (_U_(0x1) << ISI_IDR_P_OVR_Pos) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_P_OVR(value) (ISI_IDR_P_OVR_Msk & ((value) << ISI_IDR_P_OVR_Pos)) +#define ISI_IDR_C_OVR_Pos _U_(25) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_C_OVR_Msk (_U_(0x1) << ISI_IDR_C_OVR_Pos) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_C_OVR(value) (ISI_IDR_C_OVR_Msk & ((value) << ISI_IDR_C_OVR_Pos)) +#define ISI_IDR_CRC_ERR_Pos _U_(26) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Position */ +#define ISI_IDR_CRC_ERR_Msk (_U_(0x1) << ISI_IDR_CRC_ERR_Pos) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Mask */ +#define ISI_IDR_CRC_ERR(value) (ISI_IDR_CRC_ERR_Msk & ((value) << ISI_IDR_CRC_ERR_Pos)) +#define ISI_IDR_FR_OVR_Pos _U_(27) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Position */ +#define ISI_IDR_FR_OVR_Msk (_U_(0x1) << ISI_IDR_FR_OVR_Pos) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Mask */ +#define ISI_IDR_FR_OVR(value) (ISI_IDR_FR_OVR_Msk & ((value) << ISI_IDR_FR_OVR_Pos)) +#define ISI_IDR_Msk _U_(0x0F030406) /**< (ISI_IDR) Register Mask */ + + +/* -------- ISI_IMR : (ISI Offset: 0x34) ( R/ 32) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE_Pos _U_(1) /**< (ISI_IMR) Module Disable Operation Completed Position */ +#define ISI_IMR_DIS_DONE_Msk (_U_(0x1) << ISI_IMR_DIS_DONE_Pos) /**< (ISI_IMR) Module Disable Operation Completed Mask */ +#define ISI_IMR_DIS_DONE(value) (ISI_IMR_DIS_DONE_Msk & ((value) << ISI_IMR_DIS_DONE_Pos)) +#define ISI_IMR_SRST_Pos _U_(2) /**< (ISI_IMR) Software Reset Completed Position */ +#define ISI_IMR_SRST_Msk (_U_(0x1) << ISI_IMR_SRST_Pos) /**< (ISI_IMR) Software Reset Completed Mask */ +#define ISI_IMR_SRST(value) (ISI_IMR_SRST_Msk & ((value) << ISI_IMR_SRST_Pos)) +#define ISI_IMR_VSYNC_Pos _U_(10) /**< (ISI_IMR) Vertical Synchronization Position */ +#define ISI_IMR_VSYNC_Msk (_U_(0x1) << ISI_IMR_VSYNC_Pos) /**< (ISI_IMR) Vertical Synchronization Mask */ +#define ISI_IMR_VSYNC(value) (ISI_IMR_VSYNC_Msk & ((value) << ISI_IMR_VSYNC_Pos)) +#define ISI_IMR_PXFR_DONE_Pos _U_(16) /**< (ISI_IMR) Preview DMA Transfer Completed Position */ +#define ISI_IMR_PXFR_DONE_Msk (_U_(0x1) << ISI_IMR_PXFR_DONE_Pos) /**< (ISI_IMR) Preview DMA Transfer Completed Mask */ +#define ISI_IMR_PXFR_DONE(value) (ISI_IMR_PXFR_DONE_Msk & ((value) << ISI_IMR_PXFR_DONE_Pos)) +#define ISI_IMR_CXFR_DONE_Pos _U_(17) /**< (ISI_IMR) Codec DMA Transfer Completed Position */ +#define ISI_IMR_CXFR_DONE_Msk (_U_(0x1) << ISI_IMR_CXFR_DONE_Pos) /**< (ISI_IMR) Codec DMA Transfer Completed Mask */ +#define ISI_IMR_CXFR_DONE(value) (ISI_IMR_CXFR_DONE_Msk & ((value) << ISI_IMR_CXFR_DONE_Pos)) +#define ISI_IMR_P_OVR_Pos _U_(24) /**< (ISI_IMR) Preview FIFO Overflow Position */ +#define ISI_IMR_P_OVR_Msk (_U_(0x1) << ISI_IMR_P_OVR_Pos) /**< (ISI_IMR) Preview FIFO Overflow Mask */ +#define ISI_IMR_P_OVR(value) (ISI_IMR_P_OVR_Msk & ((value) << ISI_IMR_P_OVR_Pos)) +#define ISI_IMR_C_OVR_Pos _U_(25) /**< (ISI_IMR) Codec FIFO Overflow Position */ +#define ISI_IMR_C_OVR_Msk (_U_(0x1) << ISI_IMR_C_OVR_Pos) /**< (ISI_IMR) Codec FIFO Overflow Mask */ +#define ISI_IMR_C_OVR(value) (ISI_IMR_C_OVR_Msk & ((value) << ISI_IMR_C_OVR_Pos)) +#define ISI_IMR_CRC_ERR_Pos _U_(26) /**< (ISI_IMR) CRC Synchronization Error Position */ +#define ISI_IMR_CRC_ERR_Msk (_U_(0x1) << ISI_IMR_CRC_ERR_Pos) /**< (ISI_IMR) CRC Synchronization Error Mask */ +#define ISI_IMR_CRC_ERR(value) (ISI_IMR_CRC_ERR_Msk & ((value) << ISI_IMR_CRC_ERR_Pos)) +#define ISI_IMR_FR_OVR_Pos _U_(27) /**< (ISI_IMR) Frame Rate Overrun Position */ +#define ISI_IMR_FR_OVR_Msk (_U_(0x1) << ISI_IMR_FR_OVR_Pos) /**< (ISI_IMR) Frame Rate Overrun Mask */ +#define ISI_IMR_FR_OVR(value) (ISI_IMR_FR_OVR_Msk & ((value) << ISI_IMR_FR_OVR_Pos)) +#define ISI_IMR_Msk _U_(0x0F030406) /**< (ISI_IMR) Register Mask */ + + +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) ( /W 32) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN_Pos _U_(0) /**< (ISI_DMA_CHER) Preview Channel Enable Position */ +#define ISI_DMA_CHER_P_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_P_CH_EN_Pos) /**< (ISI_DMA_CHER) Preview Channel Enable Mask */ +#define ISI_DMA_CHER_P_CH_EN(value) (ISI_DMA_CHER_P_CH_EN_Msk & ((value) << ISI_DMA_CHER_P_CH_EN_Pos)) +#define ISI_DMA_CHER_C_CH_EN_Pos _U_(1) /**< (ISI_DMA_CHER) Codec Channel Enable Position */ +#define ISI_DMA_CHER_C_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_C_CH_EN_Pos) /**< (ISI_DMA_CHER) Codec Channel Enable Mask */ +#define ISI_DMA_CHER_C_CH_EN(value) (ISI_DMA_CHER_C_CH_EN_Msk & ((value) << ISI_DMA_CHER_C_CH_EN_Pos)) +#define ISI_DMA_CHER_Msk _U_(0x00000003) /**< (ISI_DMA_CHER) Register Mask */ + + +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) ( /W 32) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS_Pos _U_(0) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Position */ +#define ISI_DMA_CHDR_P_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_P_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Mask */ +#define ISI_DMA_CHDR_P_CH_DIS(value) (ISI_DMA_CHDR_P_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_P_CH_DIS_Pos)) +#define ISI_DMA_CHDR_C_CH_DIS_Pos _U_(1) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Position */ +#define ISI_DMA_CHDR_C_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_C_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Mask */ +#define ISI_DMA_CHDR_C_CH_DIS(value) (ISI_DMA_CHDR_C_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_C_CH_DIS_Pos)) +#define ISI_DMA_CHDR_Msk _U_(0x00000003) /**< (ISI_DMA_CHDR) Register Mask */ + + +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) ( R/ 32) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S_Pos _U_(0) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Position */ +#define ISI_DMA_CHSR_P_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_P_CH_S_Pos) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Mask */ +#define ISI_DMA_CHSR_P_CH_S(value) (ISI_DMA_CHSR_P_CH_S_Msk & ((value) << ISI_DMA_CHSR_P_CH_S_Pos)) +#define ISI_DMA_CHSR_C_CH_S_Pos _U_(1) /**< (ISI_DMA_CHSR) Code DMA Channel Status Position */ +#define ISI_DMA_CHSR_C_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_C_CH_S_Pos) /**< (ISI_DMA_CHSR) Code DMA Channel Status Mask */ +#define ISI_DMA_CHSR_C_CH_S(value) (ISI_DMA_CHSR_C_CH_S_Msk & ((value) << ISI_DMA_CHSR_C_CH_S_Pos)) +#define ISI_DMA_CHSR_Msk _U_(0x00000003) /**< (ISI_DMA_CHSR) Register Mask */ + + +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) (R/W 32) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos _U_(2) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Position */ +#define ISI_DMA_P_ADDR_P_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Mask */ +#define ISI_DMA_P_ADDR_P_ADDR(value) (ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)) +#define ISI_DMA_P_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_ADDR) Register Mask */ + + +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) (R/W 32) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH_Pos _U_(0) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_P_CTRL_P_FETCH_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_FETCH_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_FETCH(value) (ISI_DMA_P_CTRL_P_FETCH_Msk & ((value) << ISI_DMA_P_CTRL_P_FETCH_Pos)) +#define ISI_DMA_P_CTRL_P_WB_Pos _U_(1) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_P_CTRL_P_WB_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_WB_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_WB(value) (ISI_DMA_P_CTRL_P_WB_Msk & ((value) << ISI_DMA_P_CTRL_P_WB_Pos)) +#define ISI_DMA_P_CTRL_P_IEN_Pos _U_(2) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_P_CTRL_P_IEN_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_IEN_Pos) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_P_CTRL_P_IEN(value) (ISI_DMA_P_CTRL_P_IEN_Msk & ((value) << ISI_DMA_P_CTRL_P_IEN_Pos)) +#define ISI_DMA_P_CTRL_P_DONE_Pos _U_(3) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Position */ +#define ISI_DMA_P_CTRL_P_DONE_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_DONE_Pos) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Mask */ +#define ISI_DMA_P_CTRL_P_DONE(value) (ISI_DMA_P_CTRL_P_DONE_Msk & ((value) << ISI_DMA_P_CTRL_P_DONE_Pos)) +#define ISI_DMA_P_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_P_CTRL) Register Mask */ + + +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) (R/W 32) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos _U_(2) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Position */ +#define ISI_DMA_P_DSCR_P_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Mask */ +#define ISI_DMA_P_DSCR_P_DSCR(value) (ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)) +#define ISI_DMA_P_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_DSCR) Register Mask */ + + +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) (R/W 32) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos _U_(2) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Position */ +#define ISI_DMA_C_ADDR_C_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Mask */ +#define ISI_DMA_C_ADDR_C_ADDR(value) (ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)) +#define ISI_DMA_C_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_ADDR) Register Mask */ + + +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) (R/W 32) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH_Pos _U_(0) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_C_CTRL_C_FETCH_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_FETCH_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_FETCH(value) (ISI_DMA_C_CTRL_C_FETCH_Msk & ((value) << ISI_DMA_C_CTRL_C_FETCH_Pos)) +#define ISI_DMA_C_CTRL_C_WB_Pos _U_(1) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_C_CTRL_C_WB_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_WB_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_WB(value) (ISI_DMA_C_CTRL_C_WB_Msk & ((value) << ISI_DMA_C_CTRL_C_WB_Pos)) +#define ISI_DMA_C_CTRL_C_IEN_Pos _U_(2) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_C_CTRL_C_IEN_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_IEN_Pos) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_C_CTRL_C_IEN(value) (ISI_DMA_C_CTRL_C_IEN_Msk & ((value) << ISI_DMA_C_CTRL_C_IEN_Pos)) +#define ISI_DMA_C_CTRL_C_DONE_Pos _U_(3) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Position */ +#define ISI_DMA_C_CTRL_C_DONE_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_DONE_Pos) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Mask */ +#define ISI_DMA_C_CTRL_C_DONE(value) (ISI_DMA_C_CTRL_C_DONE_Msk & ((value) << ISI_DMA_C_CTRL_C_DONE_Pos)) +#define ISI_DMA_C_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_C_CTRL) Register Mask */ + + +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) (R/W 32) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos _U_(2) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Position */ +#define ISI_DMA_C_DSCR_C_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Mask */ +#define ISI_DMA_C_DSCR_C_DSCR(value) (ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)) +#define ISI_DMA_C_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_DSCR) Register Mask */ + + +/* -------- ISI_WPMR : (ISI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN_Pos _U_(0) /**< (ISI_WPMR) Write Protection Enable Position */ +#define ISI_WPMR_WPEN_Msk (_U_(0x1) << ISI_WPMR_WPEN_Pos) /**< (ISI_WPMR) Write Protection Enable Mask */ +#define ISI_WPMR_WPEN(value) (ISI_WPMR_WPEN_Msk & ((value) << ISI_WPMR_WPEN_Pos)) +#define ISI_WPMR_WPKEY_Pos _U_(8) /**< (ISI_WPMR) Write Protection Key Password Position */ +#define ISI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Write Protection Key Password Mask */ +#define ISI_WPMR_WPKEY(value) (ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)) +#define ISI_WPMR_WPKEY_PASSWD_Val _U_(0x495349) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ISI_WPMR_WPKEY_PASSWD (ISI_WPMR_WPKEY_PASSWD_Val << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ISI_WPMR_Msk _U_(0xFFFFFF01) /**< (ISI_WPMR) Register Mask */ + + +/* -------- ISI_WPSR : (ISI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS_Pos _U_(0) /**< (ISI_WPSR) Write Protection Violation Status Position */ +#define ISI_WPSR_WPVS_Msk (_U_(0x1) << ISI_WPSR_WPVS_Pos) /**< (ISI_WPSR) Write Protection Violation Status Mask */ +#define ISI_WPSR_WPVS(value) (ISI_WPSR_WPVS_Msk & ((value) << ISI_WPSR_WPVS_Pos)) +#define ISI_WPSR_WPVSRC_Pos _U_(8) /**< (ISI_WPSR) Write Protection Violation Source Position */ +#define ISI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << ISI_WPSR_WPVSRC_Pos) /**< (ISI_WPSR) Write Protection Violation Source Mask */ +#define ISI_WPSR_WPVSRC(value) (ISI_WPSR_WPVSRC_Msk & ((value) << ISI_WPSR_WPVSRC_Pos)) +#define ISI_WPSR_Msk _U_(0x00FFFF01) /**< (ISI_WPSR) Register Mask */ + + +/** \brief ISI register offsets definitions */ +#define ISI_CFG1_REG_OFST (0x00) /**< (ISI_CFG1) ISI Configuration 1 Register Offset */ +#define ISI_CFG2_REG_OFST (0x04) /**< (ISI_CFG2) ISI Configuration 2 Register Offset */ +#define ISI_PSIZE_REG_OFST (0x08) /**< (ISI_PSIZE) ISI Preview Size Register Offset */ +#define ISI_PDECF_REG_OFST (0x0C) /**< (ISI_PDECF) ISI Preview Decimation Factor Register Offset */ +#define ISI_Y2R_SET0_REG_OFST (0x10) /**< (ISI_Y2R_SET0) ISI Color Space Conversion YCrCb To RGB Set 0 Register Offset */ +#define ISI_Y2R_SET1_REG_OFST (0x14) /**< (ISI_Y2R_SET1) ISI Color Space Conversion YCrCb To RGB Set 1 Register Offset */ +#define ISI_R2Y_SET0_REG_OFST (0x18) /**< (ISI_R2Y_SET0) ISI Color Space Conversion RGB To YCrCb Set 0 Register Offset */ +#define ISI_R2Y_SET1_REG_OFST (0x1C) /**< (ISI_R2Y_SET1) ISI Color Space Conversion RGB To YCrCb Set 1 Register Offset */ +#define ISI_R2Y_SET2_REG_OFST (0x20) /**< (ISI_R2Y_SET2) ISI Color Space Conversion RGB To YCrCb Set 2 Register Offset */ +#define ISI_CR_REG_OFST (0x24) /**< (ISI_CR) ISI Control Register Offset */ +#define ISI_SR_REG_OFST (0x28) /**< (ISI_SR) ISI Status Register Offset */ +#define ISI_IER_REG_OFST (0x2C) /**< (ISI_IER) ISI Interrupt Enable Register Offset */ +#define ISI_IDR_REG_OFST (0x30) /**< (ISI_IDR) ISI Interrupt Disable Register Offset */ +#define ISI_IMR_REG_OFST (0x34) /**< (ISI_IMR) ISI Interrupt Mask Register Offset */ +#define ISI_DMA_CHER_REG_OFST (0x38) /**< (ISI_DMA_CHER) DMA Channel Enable Register Offset */ +#define ISI_DMA_CHDR_REG_OFST (0x3C) /**< (ISI_DMA_CHDR) DMA Channel Disable Register Offset */ +#define ISI_DMA_CHSR_REG_OFST (0x40) /**< (ISI_DMA_CHSR) DMA Channel Status Register Offset */ +#define ISI_DMA_P_ADDR_REG_OFST (0x44) /**< (ISI_DMA_P_ADDR) DMA Preview Base Address Register Offset */ +#define ISI_DMA_P_CTRL_REG_OFST (0x48) /**< (ISI_DMA_P_CTRL) DMA Preview Control Register Offset */ +#define ISI_DMA_P_DSCR_REG_OFST (0x4C) /**< (ISI_DMA_P_DSCR) DMA Preview Descriptor Address Register Offset */ +#define ISI_DMA_C_ADDR_REG_OFST (0x50) /**< (ISI_DMA_C_ADDR) DMA Codec Base Address Register Offset */ +#define ISI_DMA_C_CTRL_REG_OFST (0x54) /**< (ISI_DMA_C_CTRL) DMA Codec Control Register Offset */ +#define ISI_DMA_C_DSCR_REG_OFST (0x58) /**< (ISI_DMA_C_DSCR) DMA Codec Descriptor Address Register Offset */ +#define ISI_WPMR_REG_OFST (0xE4) /**< (ISI_WPMR) Write Protection Mode Register Offset */ +#define ISI_WPSR_REG_OFST (0xE8) /**< (ISI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ISI register API structure */ +typedef struct +{ + __IO uint32_t ISI_CFG1; /**< Offset: 0x00 (R/W 32) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< Offset: 0x04 (R/W 32) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< Offset: 0x08 (R/W 32) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< Offset: 0x0C (R/W 32) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< Offset: 0x10 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< Offset: 0x14 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< Offset: 0x18 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< Offset: 0x1C (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< Offset: 0x20 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< Offset: 0x24 ( /W 32) ISI Control Register */ + __I uint32_t ISI_SR; /**< Offset: 0x28 (R/ 32) ISI Status Register */ + __O uint32_t ISI_IER; /**< Offset: 0x2C ( /W 32) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< Offset: 0x30 ( /W 32) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< Offset: 0x34 (R/ 32) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< Offset: 0x38 ( /W 32) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< Offset: 0x3C ( /W 32) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< Offset: 0x40 (R/ 32) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< Offset: 0x44 (R/W 32) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< Offset: 0x48 (R/W 32) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< Offset: 0x4C (R/W 32) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< Offset: 0x50 (R/W 32) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< Offset: 0x54 (R/W 32) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< Offset: 0x58 (R/W 32) DMA Codec Descriptor Address Register */ + __I uint8_t Reserved1[0x88]; + __IO uint32_t ISI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} isi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ISI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/matrix.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/matrix.h new file mode 100644 index 00000000..f9415cdf --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/matrix.h @@ -0,0 +1,274 @@ +/** + * \brief Component description for MATRIX + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_MATRIX_COMPONENT_H_ +#define _SAME70_MATRIX_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR MATRIX */ +/* ************************************************************************** */ + +/* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos _U_(0) /**< (MATRIX_PRAS) Master 0 Priority Position */ +#define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */ +#define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)) +#define MATRIX_PRAS_M1PR_Pos _U_(4) /**< (MATRIX_PRAS) Master 1 Priority Position */ +#define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */ +#define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)) +#define MATRIX_PRAS_M2PR_Pos _U_(8) /**< (MATRIX_PRAS) Master 2 Priority Position */ +#define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */ +#define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)) +#define MATRIX_PRAS_M3PR_Pos _U_(12) /**< (MATRIX_PRAS) Master 3 Priority Position */ +#define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */ +#define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)) +#define MATRIX_PRAS_M4PR_Pos _U_(16) /**< (MATRIX_PRAS) Master 4 Priority Position */ +#define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */ +#define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)) +#define MATRIX_PRAS_M5PR_Pos _U_(20) /**< (MATRIX_PRAS) Master 5 Priority Position */ +#define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */ +#define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)) +#define MATRIX_PRAS_M6PR_Pos _U_(24) /**< (MATRIX_PRAS) Master 6 Priority Position */ +#define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */ +#define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)) +#define MATRIX_PRAS_Msk _U_(0x03333333) /**< (MATRIX_PRAS) Register Mask */ + + +/* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos _U_(0) /**< (MATRIX_PRBS) Master 8 Priority Position */ +#define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */ +#define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)) +#define MATRIX_PRBS_M9PR_Pos _U_(4) /**< (MATRIX_PRBS) Master 9 Priority Position */ +#define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */ +#define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)) +#define MATRIX_PRBS_M10PR_Pos _U_(8) /**< (MATRIX_PRBS) Master 10 Priority Position */ +#define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */ +#define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)) +#define MATRIX_PRBS_M11PR_Pos _U_(12) /**< (MATRIX_PRBS) Master 11 Priority Position */ +#define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */ +#define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)) +#define MATRIX_PRBS_Msk _U_(0x00003333) /**< (MATRIX_PRBS) Register Mask */ + + +/* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG_ULBT_Pos _U_(0) /**< (MATRIX_MCFG) Undefined Length Burst Type Position */ +#define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */ +#define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */ +#define MATRIX_MCFG_Msk _U_(0x00000007) /**< (MATRIX_MCFG) Register Mask */ + + +/* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos _U_(0) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */ +#define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */ +#define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos _U_(16) /**< (MATRIX_SCFG) Default Master Type Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos _U_(18) /**< (MATRIX_SCFG) Fixed Default Master Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)) +#define MATRIX_SCFG_Msk _U_(0x003F01FF) /**< (MATRIX_SCFG) Register Mask */ + + +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0_Pos _U_(0) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */ +#define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */ +#define MATRIX_MRCR_RCB0(value) (MATRIX_MRCR_RCB0_Msk & ((value) << MATRIX_MRCR_RCB0_Pos)) +#define MATRIX_MRCR_RCB1_Pos _U_(1) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */ +#define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */ +#define MATRIX_MRCR_RCB1(value) (MATRIX_MRCR_RCB1_Msk & ((value) << MATRIX_MRCR_RCB1_Pos)) +#define MATRIX_MRCR_RCB2_Pos _U_(2) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */ +#define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */ +#define MATRIX_MRCR_RCB2(value) (MATRIX_MRCR_RCB2_Msk & ((value) << MATRIX_MRCR_RCB2_Pos)) +#define MATRIX_MRCR_RCB3_Pos _U_(3) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */ +#define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */ +#define MATRIX_MRCR_RCB3(value) (MATRIX_MRCR_RCB3_Msk & ((value) << MATRIX_MRCR_RCB3_Pos)) +#define MATRIX_MRCR_RCB4_Pos _U_(4) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */ +#define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */ +#define MATRIX_MRCR_RCB4(value) (MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)) +#define MATRIX_MRCR_RCB5_Pos _U_(5) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */ +#define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */ +#define MATRIX_MRCR_RCB5(value) (MATRIX_MRCR_RCB5_Msk & ((value) << MATRIX_MRCR_RCB5_Pos)) +#define MATRIX_MRCR_RCB6_Pos _U_(6) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */ +#define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */ +#define MATRIX_MRCR_RCB6(value) (MATRIX_MRCR_RCB6_Msk & ((value) << MATRIX_MRCR_RCB6_Pos)) +#define MATRIX_MRCR_RCB8_Pos _U_(8) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */ +#define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */ +#define MATRIX_MRCR_RCB8(value) (MATRIX_MRCR_RCB8_Msk & ((value) << MATRIX_MRCR_RCB8_Pos)) +#define MATRIX_MRCR_RCB9_Pos _U_(9) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */ +#define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */ +#define MATRIX_MRCR_RCB9(value) (MATRIX_MRCR_RCB9_Msk & ((value) << MATRIX_MRCR_RCB9_Pos)) +#define MATRIX_MRCR_RCB10_Pos _U_(10) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */ +#define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */ +#define MATRIX_MRCR_RCB10(value) (MATRIX_MRCR_RCB10_Msk & ((value) << MATRIX_MRCR_RCB10_Pos)) +#define MATRIX_MRCR_RCB11_Pos _U_(11) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */ +#define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */ +#define MATRIX_MRCR_RCB11(value) (MATRIX_MRCR_RCB11_Msk & ((value) << MATRIX_MRCR_RCB11_Pos)) +#define MATRIX_MRCR_Msk _U_(0x00000F7F) /**< (MATRIX_MRCR) Register Mask */ + +#define MATRIX_MRCR_RCB_Pos _U_(0) /**< (MATRIX_MRCR Position) Remap Command Bit for Master xx */ +#define MATRIX_MRCR_RCB_Msk (_U_(0x7FF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */ +#define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos)) + +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos _U_(16) /**< (CCFG_CAN0) CAN0 DMA Base Address Position */ +#define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */ +#define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)) +#define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */ + + +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4_Pos _U_(4) /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */ +#define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */ +#define CCFG_SYSIO_SYSIO4(value) (CCFG_SYSIO_SYSIO4_Msk & ((value) << CCFG_SYSIO_SYSIO4_Pos)) +#define CCFG_SYSIO_SYSIO5_Pos _U_(5) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */ +#define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */ +#define CCFG_SYSIO_SYSIO5(value) (CCFG_SYSIO_SYSIO5_Msk & ((value) << CCFG_SYSIO_SYSIO5_Pos)) +#define CCFG_SYSIO_SYSIO6_Pos _U_(6) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */ +#define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */ +#define CCFG_SYSIO_SYSIO6(value) (CCFG_SYSIO_SYSIO6_Msk & ((value) << CCFG_SYSIO_SYSIO6_Pos)) +#define CCFG_SYSIO_SYSIO7_Pos _U_(7) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */ +#define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */ +#define CCFG_SYSIO_SYSIO7(value) (CCFG_SYSIO_SYSIO7_Msk & ((value) << CCFG_SYSIO_SYSIO7_Pos)) +#define CCFG_SYSIO_SYSIO12_Pos _U_(12) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */ +#define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */ +#define CCFG_SYSIO_SYSIO12(value) (CCFG_SYSIO_SYSIO12_Msk & ((value) << CCFG_SYSIO_SYSIO12_Pos)) +#define CCFG_SYSIO_CAN1DMABA_Pos _U_(16) /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */ +#define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */ +#define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)) +#define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */ + +#define CCFG_SYSIO_SYSIO_Pos _U_(4) /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */ +#define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos)) + +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0_Pos _U_(0) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS0(value) (CCFG_SMCNFCS_SMC_NFCS0_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS0_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS1_Pos _U_(1) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS1(value) (CCFG_SMCNFCS_SMC_NFCS1_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS1_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS2_Pos _U_(2) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS2(value) (CCFG_SMCNFCS_SMC_NFCS2_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS2_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS3_Pos _U_(3) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS3(value) (CCFG_SMCNFCS_SMC_NFCS3_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS3_Pos)) +#define CCFG_SMCNFCS_SDRAMEN_Pos _U_(4) /**< (CCFG_SMCNFCS) SDRAM Enable Position */ +#define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */ +#define CCFG_SMCNFCS_SDRAMEN(value) (CCFG_SMCNFCS_SDRAMEN_Msk & ((value) << CCFG_SMCNFCS_SDRAMEN_Pos)) +#define CCFG_SMCNFCS_Msk _U_(0x0000001F) /**< (CCFG_SMCNFCS) Register Mask */ + +#define CCFG_SMCNFCS_SMC_NFCS_Pos _U_(0) /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */ +#define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos)) + +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) (R/W 32) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN_Pos _U_(0) /**< (MATRIX_WPMR) Write Protection Enable Position */ +#define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */ +#define MATRIX_WPMR_WPEN(value) (MATRIX_WPMR_WPEN_Msk & ((value) << MATRIX_WPMR_WPEN_Pos)) +#define MATRIX_WPMR_WPKEY_Pos _U_(8) /**< (MATRIX_WPMR) Write Protection Key Position */ +#define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */ +#define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)) +#define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */ + + +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) ( R/ 32) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS_Pos _U_(0) /**< (MATRIX_WPSR) Write Protection Violation Status Position */ +#define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */ +#define MATRIX_WPSR_WPVS(value) (MATRIX_WPSR_WPVS_Msk & ((value) << MATRIX_WPSR_WPVS_Pos)) +#define MATRIX_WPSR_WPVSRC_Pos _U_(8) /**< (MATRIX_WPSR) Write Protection Violation Source Position */ +#define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */ +#define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos)) +#define MATRIX_WPSR_Msk _U_(0x00FFFF01) /**< (MATRIX_WPSR) Register Mask */ + + +/** \brief MATRIX register offsets definitions */ +#define MATRIX_PRAS_REG_OFST (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */ +#define MATRIX_PRBS_REG_OFST (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */ +#define MATRIX_MCFG_REG_OFST (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */ +#define MATRIX_SCFG_REG_OFST (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */ +#define MATRIX_MRCR_REG_OFST (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */ +#define CCFG_CAN0_REG_OFST (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */ +#define CCFG_SYSIO_REG_OFST (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */ +#define CCFG_SMCNFCS_REG_OFST (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */ +#define MATRIX_WPMR_REG_OFST (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */ +#define MATRIX_WPSR_REG_OFST (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MATRIX_PR register API structure */ +typedef struct +{ + __IO uint32_t MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */ +} matrix_pr_registers_t; + +#define MATRIX_PR_NUMBER _U_(9) + +/** \brief MATRIX register API structure */ +typedef struct +{ + __IO uint32_t MATRIX_MCFG[12]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */ + __I uint8_t Reserved1[0x10]; + __IO uint32_t MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */ + __I uint8_t Reserved2[0x1C]; + matrix_pr_registers_t MATRIX_PR[MATRIX_PR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */ + __I uint8_t Reserved3[0x38]; + __IO uint32_t MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */ + __I uint8_t Reserved4[0x0C]; + __IO uint32_t CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */ + __I uint8_t Reserved5[0x0C]; + __IO uint32_t CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */ + __I uint8_t Reserved6[0xBC]; + __IO uint32_t MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */ +} matrix_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_MATRIX_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/mcan.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/mcan.h new file mode 100644 index 00000000..6017898c --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/mcan.h @@ -0,0 +1,1993 @@ +/** + * \brief Component description for MCAN + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_MCAN_COMPONENT_H_ +#define _SAME70_MCAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR MCAN */ +/* ************************************************************************** */ + +/* -------- MCAN_CUST : (MCAN Offset: 0x08) (R/W 32) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos _U_(0) /**< (MCAN_CUST) Customer-specific Value Position */ +#define MCAN_CUST_CSV_Msk (_U_(0xFFFFFFFF) << MCAN_CUST_CSV_Pos) /**< (MCAN_CUST) Customer-specific Value Mask */ +#define MCAN_CUST_CSV(value) (MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)) +#define MCAN_CUST_Msk _U_(0xFFFFFFFF) /**< (MCAN_CUST) Register Mask */ + + +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos _U_(0) /**< (MCAN_FBTP) Fast (Re) Synchronization Jump Width Position */ +#define MCAN_FBTP_FSJW_Msk (_U_(0x3) << MCAN_FBTP_FSJW_Pos) /**< (MCAN_FBTP) Fast (Re) Synchronization Jump Width Mask */ +#define MCAN_FBTP_FSJW(value) (MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos)) +#define MCAN_FBTP_FTSEG2_Pos _U_(4) /**< (MCAN_FBTP) Fast Time Segment After Sample Point Position */ +#define MCAN_FBTP_FTSEG2_Msk (_U_(0x7) << MCAN_FBTP_FTSEG2_Pos) /**< (MCAN_FBTP) Fast Time Segment After Sample Point Mask */ +#define MCAN_FBTP_FTSEG2(value) (MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos)) +#define MCAN_FBTP_FTSEG1_Pos _U_(8) /**< (MCAN_FBTP) Fast Time Segment Before Sample Point Position */ +#define MCAN_FBTP_FTSEG1_Msk (_U_(0xF) << MCAN_FBTP_FTSEG1_Pos) /**< (MCAN_FBTP) Fast Time Segment Before Sample Point Mask */ +#define MCAN_FBTP_FTSEG1(value) (MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos)) +#define MCAN_FBTP_FBRP_Pos _U_(16) /**< (MCAN_FBTP) Fast Baud Rate Prescaler Position */ +#define MCAN_FBTP_FBRP_Msk (_U_(0x1F) << MCAN_FBTP_FBRP_Pos) /**< (MCAN_FBTP) Fast Baud Rate Prescaler Mask */ +#define MCAN_FBTP_FBRP(value) (MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos)) +#define MCAN_FBTP_TDC_Pos _U_(23) /**< (MCAN_FBTP) Transceiver Delay Compensation Position */ +#define MCAN_FBTP_TDC_Msk (_U_(0x1) << MCAN_FBTP_TDC_Pos) /**< (MCAN_FBTP) Transceiver Delay Compensation Mask */ +#define MCAN_FBTP_TDC(value) (MCAN_FBTP_TDC_Msk & ((value) << MCAN_FBTP_TDC_Pos)) +#define MCAN_FBTP_TDC_DISABLED_Val _U_(0x0) /**< (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED_Val _U_(0x1) /**< (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDC_DISABLED (MCAN_FBTP_TDC_DISABLED_Val << MCAN_FBTP_TDC_Pos) /**< (MCAN_FBTP) Transceiver Delay Compensation disabled. Position */ +#define MCAN_FBTP_TDC_ENABLED (MCAN_FBTP_TDC_ENABLED_Val << MCAN_FBTP_TDC_Pos) /**< (MCAN_FBTP) Transceiver Delay Compensation enabled. Position */ +#define MCAN_FBTP_TDCO_Pos _U_(24) /**< (MCAN_FBTP) Transceiver Delay Compensation Offset Position */ +#define MCAN_FBTP_TDCO_Msk (_U_(0x1F) << MCAN_FBTP_TDCO_Pos) /**< (MCAN_FBTP) Transceiver Delay Compensation Offset Mask */ +#define MCAN_FBTP_TDCO(value) (MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos)) +#define MCAN_FBTP_Msk _U_(0x1F9F0F73) /**< (MCAN_FBTP) Register Mask */ + + +/* -------- MCAN_TEST : (MCAN Offset: 0x10) (R/W 32) Test Register -------- */ +#define MCAN_TEST_LBCK_Pos _U_(4) /**< (MCAN_TEST) Loop Back Mode (read/write) Position */ +#define MCAN_TEST_LBCK_Msk (_U_(0x1) << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back Mode (read/write) Mask */ +#define MCAN_TEST_LBCK(value) (MCAN_TEST_LBCK_Msk & ((value) << MCAN_TEST_LBCK_Pos)) +#define MCAN_TEST_LBCK_DISABLED_Val _U_(0x0) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED_Val _U_(0x1) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). */ +#define MCAN_TEST_LBCK_DISABLED (MCAN_TEST_LBCK_DISABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. Position */ +#define MCAN_TEST_LBCK_ENABLED (MCAN_TEST_LBCK_ENABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 1.5.1.9). Position */ +#define MCAN_TEST_TX_Pos _U_(5) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Position */ +#define MCAN_TEST_TX_Msk (_U_(0x3) << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Mask */ +#define MCAN_TEST_TX(value) (MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)) +#define MCAN_TEST_TX_RESET_Val _U_(0x0) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val _U_(0x1) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_TX_RESET (MCAN_TEST_TX_RESET_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. Position */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. Position */ +#define MCAN_TEST_TX_DOMINANT (MCAN_TEST_TX_DOMINANT_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. Position */ +#define MCAN_TEST_TX_RECESSIVE (MCAN_TEST_TX_RECESSIVE_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. Position */ +#define MCAN_TEST_RX_Pos _U_(7) /**< (MCAN_TEST) Receive Pin (read-only) Position */ +#define MCAN_TEST_RX_Msk (_U_(0x1) << MCAN_TEST_RX_Pos) /**< (MCAN_TEST) Receive Pin (read-only) Mask */ +#define MCAN_TEST_RX(value) (MCAN_TEST_RX_Msk & ((value) << MCAN_TEST_RX_Pos)) +#define MCAN_TEST_TDCV_Pos _U_(8) /**< (MCAN_TEST) Transceiver Delay Compensation Value (read-only) Position */ +#define MCAN_TEST_TDCV_Msk (_U_(0x3F) << MCAN_TEST_TDCV_Pos) /**< (MCAN_TEST) Transceiver Delay Compensation Value (read-only) Mask */ +#define MCAN_TEST_TDCV(value) (MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos)) +#define MCAN_TEST_Msk _U_(0x00003FF0) /**< (MCAN_TEST) Register Mask */ + + +/* -------- MCAN_RWD : (MCAN Offset: 0x14) (R/W 32) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos _U_(0) /**< (MCAN_RWD) Watchdog Configuration (read/write) Position */ +#define MCAN_RWD_WDC_Msk (_U_(0xFF) << MCAN_RWD_WDC_Pos) /**< (MCAN_RWD) Watchdog Configuration (read/write) Mask */ +#define MCAN_RWD_WDC(value) (MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)) +#define MCAN_RWD_WDV_Pos _U_(8) /**< (MCAN_RWD) Watchdog Value (read-only) Position */ +#define MCAN_RWD_WDV_Msk (_U_(0xFF) << MCAN_RWD_WDV_Pos) /**< (MCAN_RWD) Watchdog Value (read-only) Mask */ +#define MCAN_RWD_WDV(value) (MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)) +#define MCAN_RWD_Msk _U_(0x0000FFFF) /**< (MCAN_RWD) Register Mask */ + + +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) (R/W 32) CC Control Register -------- */ +#define MCAN_CCCR_INIT_Pos _U_(0) /**< (MCAN_CCCR) Initialization (read/write) Position */ +#define MCAN_CCCR_INIT_Msk (_U_(0x1) << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization (read/write) Mask */ +#define MCAN_CCCR_INIT(value) (MCAN_CCCR_INIT_Msk & ((value) << MCAN_CCCR_INIT_Pos)) +#define MCAN_CCCR_INIT_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_INIT_DISABLED (MCAN_CCCR_INIT_DISABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Normal operation. Position */ +#define MCAN_CCCR_INIT_ENABLED (MCAN_CCCR_INIT_ENABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization is started. Position */ +#define MCAN_CCCR_CCE_Pos _U_(1) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Position */ +#define MCAN_CCCR_CCE_Msk (_U_(0x1) << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_CCE(value) (MCAN_CCCR_CCE_Msk & ((value) << MCAN_CCCR_CCE_Pos)) +#define MCAN_CCCR_CCE_PROTECTED_Val _U_(0x0) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE_Val _U_(0x1) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_CCE_PROTECTED (MCAN_CCCR_CCE_PROTECTED_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. Position */ +#define MCAN_CCCR_CCE_CONFIGURABLE (MCAN_CCCR_CCE_CONFIGURABLE_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). Position */ +#define MCAN_CCCR_ASM_Pos _U_(2) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_ASM_Msk (_U_(0x1) << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_ASM(value) (MCAN_CCCR_ASM_Msk & ((value) << MCAN_CCCR_ASM_Pos)) +#define MCAN_CCCR_ASM_NORMAL_Val _U_(0x0) /**< (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED_Val _U_(0x1) /**< (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_ASM_NORMAL (MCAN_CCCR_ASM_NORMAL_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Normal CAN operation. Position */ +#define MCAN_CCCR_ASM_RESTRICTED (MCAN_CCCR_ASM_RESTRICTED_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted operation mode active. Position */ +#define MCAN_CCCR_CSA_Pos _U_(3) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Position */ +#define MCAN_CCCR_CSA_Msk (_U_(0x1) << MCAN_CCCR_CSA_Pos) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Mask */ +#define MCAN_CCCR_CSA(value) (MCAN_CCCR_CSA_Msk & ((value) << MCAN_CCCR_CSA_Pos)) +#define MCAN_CCCR_CSR_Pos _U_(4) /**< (MCAN_CCCR) Clock Stop Request (read/write) Position */ +#define MCAN_CCCR_CSR_Msk (_U_(0x1) << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock Stop Request (read/write) Mask */ +#define MCAN_CCCR_CSR(value) (MCAN_CCCR_CSR_Msk & ((value) << MCAN_CCCR_CSR_Pos)) +#define MCAN_CCCR_CSR_NO_CLOCK_STOP_Val _U_(0x0) /**< (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP_Val _U_(0x1) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (MCAN_CCCR_CSR_NO_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) No clock stop is requested. Position */ +#define MCAN_CCCR_CSR_CLOCK_STOP (MCAN_CCCR_CSR_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. Position */ +#define MCAN_CCCR_MON_Pos _U_(5) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_MON_Msk (_U_(0x1) << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_MON(value) (MCAN_CCCR_MON_Msk & ((value) << MCAN_CCCR_MON_Pos)) +#define MCAN_CCCR_MON_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_MON_DISABLED (MCAN_CCCR_MON_DISABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. Position */ +#define MCAN_CCCR_MON_ENABLED (MCAN_CCCR_MON_ENABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. Position */ +#define MCAN_CCCR_DAR_Pos _U_(6) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Position */ +#define MCAN_CCCR_DAR_Msk (_U_(0x1) << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Mask */ +#define MCAN_CCCR_DAR(value) (MCAN_CCCR_DAR_Msk & ((value) << MCAN_CCCR_DAR_Pos)) +#define MCAN_CCCR_DAR_AUTO_RETX_Val _U_(0x0) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX_Val _U_(0x1) /**< (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_DAR_AUTO_RETX (MCAN_CCCR_DAR_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. Position */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (MCAN_CCCR_DAR_NO_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission disabled. Position */ +#define MCAN_CCCR_TEST_Pos _U_(7) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Position */ +#define MCAN_CCCR_TEST_Msk (_U_(0x1) << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_TEST(value) (MCAN_CCCR_TEST_Msk & ((value) << MCAN_CCCR_TEST_Pos)) +#define MCAN_CCCR_TEST_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_TEST_DISABLED (MCAN_CCCR_TEST_DISABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. Position */ +#define MCAN_CCCR_TEST_ENABLED (MCAN_CCCR_TEST_ENABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. Position */ +#define MCAN_CCCR_CME_Pos _U_(8) /**< (MCAN_CCCR) CAN Mode Enable (read/write, write protection) Position */ +#define MCAN_CCCR_CME_Msk (_U_(0x3) << MCAN_CCCR_CME_Pos) /**< (MCAN_CCCR) CAN Mode Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_CME(value) (MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos)) +#define MCAN_CCCR_CME_ISO11898_1_Val _U_(0x0) /**< (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD_Val _U_(0x1) /**< (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CME_ISO11898_1 (MCAN_CCCR_CME_ISO11898_1_Val << MCAN_CCCR_CME_Pos) /**< (MCAN_CCCR) CAN operation according to ISO11898-1 enabled Position */ +#define MCAN_CCCR_CME_FD (MCAN_CCCR_CME_FD_Val << MCAN_CCCR_CME_Pos) /**< (MCAN_CCCR) CAN FD operation enabled Position */ +#define MCAN_CCCR_CMR_Pos _U_(10) /**< (MCAN_CCCR) CAN Mode Request (read/write) Position */ +#define MCAN_CCCR_CMR_Msk (_U_(0x3) << MCAN_CCCR_CMR_Pos) /**< (MCAN_CCCR) CAN Mode Request (read/write) Mask */ +#define MCAN_CCCR_CMR(value) (MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos)) +#define MCAN_CCCR_CMR_NO_CHANGE_Val _U_(0x0) /**< (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD_Val _U_(0x1) /**< (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH_Val _U_(0x2) /**< (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1_Val _U_(0x3) /**< (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_CMR_NO_CHANGE (MCAN_CCCR_CMR_NO_CHANGE_Val << MCAN_CCCR_CMR_Pos) /**< (MCAN_CCCR) No mode change Position */ +#define MCAN_CCCR_CMR_FD (MCAN_CCCR_CMR_FD_Val << MCAN_CCCR_CMR_Pos) /**< (MCAN_CCCR) Request CAN FD operation Position */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (MCAN_CCCR_CMR_FD_BITRATE_SWITCH_Val << MCAN_CCCR_CMR_Pos) /**< (MCAN_CCCR) Request CAN FD operation with bit rate switching Position */ +#define MCAN_CCCR_CMR_ISO11898_1 (MCAN_CCCR_CMR_ISO11898_1_Val << MCAN_CCCR_CMR_Pos) /**< (MCAN_CCCR) Request CAN operation according ISO11898-1 Position */ +#define MCAN_CCCR_FDO_Pos _U_(12) /**< (MCAN_CCCR) CAN FD Operation (read-only) Position */ +#define MCAN_CCCR_FDO_Msk (_U_(0x1) << MCAN_CCCR_FDO_Pos) /**< (MCAN_CCCR) CAN FD Operation (read-only) Mask */ +#define MCAN_CCCR_FDO(value) (MCAN_CCCR_FDO_Msk & ((value) << MCAN_CCCR_FDO_Pos)) +#define MCAN_CCCR_FDBS_Pos _U_(13) /**< (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) Position */ +#define MCAN_CCCR_FDBS_Msk (_U_(0x1) << MCAN_CCCR_FDBS_Pos) /**< (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) Mask */ +#define MCAN_CCCR_FDBS(value) (MCAN_CCCR_FDBS_Msk & ((value) << MCAN_CCCR_FDBS_Pos)) +#define MCAN_CCCR_TXP_Pos _U_(14) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Position */ +#define MCAN_CCCR_TXP_Msk (_U_(0x1) << MCAN_CCCR_TXP_Pos) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Mask */ +#define MCAN_CCCR_TXP(value) (MCAN_CCCR_TXP_Msk & ((value) << MCAN_CCCR_TXP_Pos)) +#define MCAN_CCCR_Msk _U_(0x00007FFF) /**< (MCAN_CCCR) Register Mask */ + + +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) (R/W 32) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos _U_(0) /**< (MCAN_BTP) (Re) Synchronization Jump Width Position */ +#define MCAN_BTP_SJW_Msk (_U_(0xF) << MCAN_BTP_SJW_Pos) /**< (MCAN_BTP) (Re) Synchronization Jump Width Mask */ +#define MCAN_BTP_SJW(value) (MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos)) +#define MCAN_BTP_TSEG2_Pos _U_(4) /**< (MCAN_BTP) Time Segment After Sample Point Position */ +#define MCAN_BTP_TSEG2_Msk (_U_(0xF) << MCAN_BTP_TSEG2_Pos) /**< (MCAN_BTP) Time Segment After Sample Point Mask */ +#define MCAN_BTP_TSEG2(value) (MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos)) +#define MCAN_BTP_TSEG1_Pos _U_(8) /**< (MCAN_BTP) Time Segment Before Sample Point Position */ +#define MCAN_BTP_TSEG1_Msk (_U_(0x3F) << MCAN_BTP_TSEG1_Pos) /**< (MCAN_BTP) Time Segment Before Sample Point Mask */ +#define MCAN_BTP_TSEG1(value) (MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos)) +#define MCAN_BTP_BRP_Pos _U_(16) /**< (MCAN_BTP) Baud Rate Prescaler Position */ +#define MCAN_BTP_BRP_Msk (_U_(0x3FF) << MCAN_BTP_BRP_Pos) /**< (MCAN_BTP) Baud Rate Prescaler Mask */ +#define MCAN_BTP_BRP(value) (MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos)) +#define MCAN_BTP_Msk _U_(0x03FF3FFF) /**< (MCAN_BTP) Register Mask */ + + +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos _U_(0) /**< (MCAN_TSCC) Timestamp Select Position */ +#define MCAN_TSCC_TSS_Msk (_U_(0x3) << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp Select Mask */ +#define MCAN_TSCC_TSS(value) (MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)) +#define MCAN_TSCC_TSS_ALWAYS_0_Val _U_(0x0) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC_Val _U_(0x1) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP_Val _U_(0x2) /**< (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TSS_ALWAYS_0 (MCAN_TSCC_TSS_ALWAYS_0_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define MCAN_TSCC_TSS_TCP_INC (MCAN_TSCC_TSS_TCP_INC_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP Position */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (MCAN_TSCC_TSS_EXT_TIMESTAMP_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) External timestamp counter value used Position */ +#define MCAN_TSCC_TCP_Pos _U_(16) /**< (MCAN_TSCC) Timestamp Counter Prescaler Position */ +#define MCAN_TSCC_TCP_Msk (_U_(0xF) << MCAN_TSCC_TCP_Pos) /**< (MCAN_TSCC) Timestamp Counter Prescaler Mask */ +#define MCAN_TSCC_TCP(value) (MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)) +#define MCAN_TSCC_Msk _U_(0x000F0003) /**< (MCAN_TSCC) Register Mask */ + + +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) (R/W 32) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos _U_(0) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Position */ +#define MCAN_TSCV_TSC_Msk (_U_(0xFFFF) << MCAN_TSCV_TSC_Pos) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Mask */ +#define MCAN_TSCV_TSC(value) (MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)) +#define MCAN_TSCV_Msk _U_(0x0000FFFF) /**< (MCAN_TSCV) Register Mask */ + + +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) (R/W 32) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC_Pos _U_(0) /**< (MCAN_TOCC) Enable Timeout Counter Position */ +#define MCAN_TOCC_ETOC_Msk (_U_(0x1) << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Enable Timeout Counter Mask */ +#define MCAN_TOCC_ETOC(value) (MCAN_TOCC_ETOC_Msk & ((value) << MCAN_TOCC_ETOC_Pos)) +#define MCAN_TOCC_ETOC_NO_TIMEOUT_Val _U_(0x0) /**< (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED_Val _U_(0x1) /**< (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (MCAN_TOCC_ETOC_NO_TIMEOUT_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter disabled. Position */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (MCAN_TOCC_ETOC_TOS_CONTROLLED_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter enabled. Position */ +#define MCAN_TOCC_TOS_Pos _U_(1) /**< (MCAN_TOCC) Timeout Select Position */ +#define MCAN_TOCC_TOS_Msk (_U_(0x3) << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout Select Mask */ +#define MCAN_TOCC_TOS(value) (MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)) +#define MCAN_TOCC_TOS_CONTINUOUS_Val _U_(0x0) /**< (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val _U_(0x1) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val _U_(0x2) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val _U_(0x3) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOS_CONTINUOUS (MCAN_TOCC_TOS_CONTINUOUS_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Continuous operation Position */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO Position */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 Position */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 Position */ +#define MCAN_TOCC_TOP_Pos _U_(16) /**< (MCAN_TOCC) Timeout Period Position */ +#define MCAN_TOCC_TOP_Msk (_U_(0xFFFF) << MCAN_TOCC_TOP_Pos) /**< (MCAN_TOCC) Timeout Period Mask */ +#define MCAN_TOCC_TOP(value) (MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)) +#define MCAN_TOCC_Msk _U_(0xFFFF0007) /**< (MCAN_TOCC) Register Mask */ + + +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) (R/W 32) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos _U_(0) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Position */ +#define MCAN_TOCV_TOC_Msk (_U_(0xFFFF) << MCAN_TOCV_TOC_Pos) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Mask */ +#define MCAN_TOCV_TOC(value) (MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)) +#define MCAN_TOCV_Msk _U_(0x0000FFFF) /**< (MCAN_TOCV) Register Mask */ + + +/* -------- MCAN_ECR : (MCAN Offset: 0x40) ( R/ 32) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos _U_(0) /**< (MCAN_ECR) Transmit Error Counter Position */ +#define MCAN_ECR_TEC_Msk (_U_(0xFF) << MCAN_ECR_TEC_Pos) /**< (MCAN_ECR) Transmit Error Counter Mask */ +#define MCAN_ECR_TEC(value) (MCAN_ECR_TEC_Msk & ((value) << MCAN_ECR_TEC_Pos)) +#define MCAN_ECR_REC_Pos _U_(8) /**< (MCAN_ECR) Receive Error Counter Position */ +#define MCAN_ECR_REC_Msk (_U_(0x7F) << MCAN_ECR_REC_Pos) /**< (MCAN_ECR) Receive Error Counter Mask */ +#define MCAN_ECR_REC(value) (MCAN_ECR_REC_Msk & ((value) << MCAN_ECR_REC_Pos)) +#define MCAN_ECR_RP_Pos _U_(15) /**< (MCAN_ECR) Receive Error Passive Position */ +#define MCAN_ECR_RP_Msk (_U_(0x1) << MCAN_ECR_RP_Pos) /**< (MCAN_ECR) Receive Error Passive Mask */ +#define MCAN_ECR_RP(value) (MCAN_ECR_RP_Msk & ((value) << MCAN_ECR_RP_Pos)) +#define MCAN_ECR_CEL_Pos _U_(16) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Position */ +#define MCAN_ECR_CEL_Msk (_U_(0xFF) << MCAN_ECR_CEL_Pos) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Mask */ +#define MCAN_ECR_CEL(value) (MCAN_ECR_CEL_Msk & ((value) << MCAN_ECR_CEL_Pos)) +#define MCAN_ECR_Msk _U_(0x00FFFFFF) /**< (MCAN_ECR) Register Mask */ + + +/* -------- MCAN_PSR : (MCAN Offset: 0x44) ( R/ 32) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos _U_(0) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_LEC_Msk (_U_(0x7) << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_LEC(value) (MCAN_PSR_LEC_Msk & ((value) << MCAN_PSR_LEC_Pos)) +#define MCAN_PSR_LEC_NO_ERROR_Val _U_(0x0) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR_Val _U_(0x1) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR_Val _U_(0x2) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR_Val _U_(0x3) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR_Val _U_(0x4) /**< (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR_Val _U_(0x5) /**< (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR_Val _U_(0x6) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE_Val _U_(0x7) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_LEC_NO_ERROR (MCAN_PSR_LEC_NO_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. Position */ +#define MCAN_PSR_LEC_STUFF_ERROR (MCAN_PSR_LEC_STUFF_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Position */ +#define MCAN_PSR_LEC_FORM_ERROR (MCAN_PSR_LEC_FORM_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. Position */ +#define MCAN_PSR_LEC_ACK_ERROR (MCAN_PSR_LEC_ACK_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. Position */ +#define MCAN_PSR_LEC_BIT1_ERROR (MCAN_PSR_LEC_BIT1_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. Position */ +#define MCAN_PSR_LEC_BIT0_ERROR (MCAN_PSR_LEC_BIT0_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). Position */ +#define MCAN_PSR_LEC_CRC_ERROR (MCAN_PSR_LEC_CRC_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. Position */ +#define MCAN_PSR_LEC_NO_CHANGE (MCAN_PSR_LEC_NO_CHANGE_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. Position */ +#define MCAN_PSR_ACT_Pos _U_(3) /**< (MCAN_PSR) Activity Position */ +#define MCAN_PSR_ACT_Msk (_U_(0x3) << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Activity Mask */ +#define MCAN_PSR_ACT(value) (MCAN_PSR_ACT_Msk & ((value) << MCAN_PSR_ACT_Pos)) +#define MCAN_PSR_ACT_SYNCHRONIZING_Val _U_(0x0) /**< (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER_Val _U_(0x2) /**< (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER_Val _U_(0x3) /**< (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_ACT_SYNCHRONIZING (MCAN_PSR_ACT_SYNCHRONIZING_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is synchronizing on CAN communication Position */ +#define MCAN_PSR_ACT_IDLE (MCAN_PSR_ACT_IDLE_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is neither receiver nor transmitter Position */ +#define MCAN_PSR_ACT_RECEIVER (MCAN_PSR_ACT_RECEIVER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as receiver Position */ +#define MCAN_PSR_ACT_TRANSMITTER (MCAN_PSR_ACT_TRANSMITTER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as transmitter Position */ +#define MCAN_PSR_EP_Pos _U_(5) /**< (MCAN_PSR) Error Passive Position */ +#define MCAN_PSR_EP_Msk (_U_(0x1) << MCAN_PSR_EP_Pos) /**< (MCAN_PSR) Error Passive Mask */ +#define MCAN_PSR_EP(value) (MCAN_PSR_EP_Msk & ((value) << MCAN_PSR_EP_Pos)) +#define MCAN_PSR_EW_Pos _U_(6) /**< (MCAN_PSR) Warning Status Position */ +#define MCAN_PSR_EW_Msk (_U_(0x1) << MCAN_PSR_EW_Pos) /**< (MCAN_PSR) Warning Status Mask */ +#define MCAN_PSR_EW(value) (MCAN_PSR_EW_Msk & ((value) << MCAN_PSR_EW_Pos)) +#define MCAN_PSR_BO_Pos _U_(7) /**< (MCAN_PSR) Bus_Off Status Position */ +#define MCAN_PSR_BO_Msk (_U_(0x1) << MCAN_PSR_BO_Pos) /**< (MCAN_PSR) Bus_Off Status Mask */ +#define MCAN_PSR_BO(value) (MCAN_PSR_BO_Msk & ((value) << MCAN_PSR_BO_Pos)) +#define MCAN_PSR_FLEC_Pos _U_(8) /**< (MCAN_PSR) Fast Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_FLEC_Msk (_U_(0x7) << MCAN_PSR_FLEC_Pos) /**< (MCAN_PSR) Fast Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_FLEC(value) (MCAN_PSR_FLEC_Msk & ((value) << MCAN_PSR_FLEC_Pos)) +#define MCAN_PSR_RESI_Pos _U_(11) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RESI_Msk (_U_(0x1) << MCAN_PSR_RESI_Pos) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RESI(value) (MCAN_PSR_RESI_Msk & ((value) << MCAN_PSR_RESI_Pos)) +#define MCAN_PSR_RBRS_Pos _U_(12) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RBRS_Msk (_U_(0x1) << MCAN_PSR_RBRS_Pos) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RBRS(value) (MCAN_PSR_RBRS_Msk & ((value) << MCAN_PSR_RBRS_Pos)) +#define MCAN_PSR_REDL_Pos _U_(13) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_REDL_Msk (_U_(0x1) << MCAN_PSR_REDL_Pos) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_REDL(value) (MCAN_PSR_REDL_Msk & ((value) << MCAN_PSR_REDL_Pos)) +#define MCAN_PSR_Msk _U_(0x00003FFF) /**< (MCAN_PSR) Register Mask */ + + +/* -------- MCAN_IR : (MCAN Offset: 0x50) (R/W 32) Interrupt Register -------- */ +#define MCAN_IR_RF0N_Pos _U_(0) /**< (MCAN_IR) Receive FIFO 0 New Message Position */ +#define MCAN_IR_RF0N_Msk (_U_(0x1) << MCAN_IR_RF0N_Pos) /**< (MCAN_IR) Receive FIFO 0 New Message Mask */ +#define MCAN_IR_RF0N(value) (MCAN_IR_RF0N_Msk & ((value) << MCAN_IR_RF0N_Pos)) +#define MCAN_IR_RF0W_Pos _U_(1) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Position */ +#define MCAN_IR_RF0W_Msk (_U_(0x1) << MCAN_IR_RF0W_Pos) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Mask */ +#define MCAN_IR_RF0W(value) (MCAN_IR_RF0W_Msk & ((value) << MCAN_IR_RF0W_Pos)) +#define MCAN_IR_RF0F_Pos _U_(2) /**< (MCAN_IR) Receive FIFO 0 Full Position */ +#define MCAN_IR_RF0F_Msk (_U_(0x1) << MCAN_IR_RF0F_Pos) /**< (MCAN_IR) Receive FIFO 0 Full Mask */ +#define MCAN_IR_RF0F(value) (MCAN_IR_RF0F_Msk & ((value) << MCAN_IR_RF0F_Pos)) +#define MCAN_IR_RF0L_Pos _U_(3) /**< (MCAN_IR) Receive FIFO 0 Message Lost Position */ +#define MCAN_IR_RF0L_Msk (_U_(0x1) << MCAN_IR_RF0L_Pos) /**< (MCAN_IR) Receive FIFO 0 Message Lost Mask */ +#define MCAN_IR_RF0L(value) (MCAN_IR_RF0L_Msk & ((value) << MCAN_IR_RF0L_Pos)) +#define MCAN_IR_RF1N_Pos _U_(4) /**< (MCAN_IR) Receive FIFO 1 New Message Position */ +#define MCAN_IR_RF1N_Msk (_U_(0x1) << MCAN_IR_RF1N_Pos) /**< (MCAN_IR) Receive FIFO 1 New Message Mask */ +#define MCAN_IR_RF1N(value) (MCAN_IR_RF1N_Msk & ((value) << MCAN_IR_RF1N_Pos)) +#define MCAN_IR_RF1W_Pos _U_(5) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Position */ +#define MCAN_IR_RF1W_Msk (_U_(0x1) << MCAN_IR_RF1W_Pos) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Mask */ +#define MCAN_IR_RF1W(value) (MCAN_IR_RF1W_Msk & ((value) << MCAN_IR_RF1W_Pos)) +#define MCAN_IR_RF1F_Pos _U_(6) /**< (MCAN_IR) Receive FIFO 1 Full Position */ +#define MCAN_IR_RF1F_Msk (_U_(0x1) << MCAN_IR_RF1F_Pos) /**< (MCAN_IR) Receive FIFO 1 Full Mask */ +#define MCAN_IR_RF1F(value) (MCAN_IR_RF1F_Msk & ((value) << MCAN_IR_RF1F_Pos)) +#define MCAN_IR_RF1L_Pos _U_(7) /**< (MCAN_IR) Receive FIFO 1 Message Lost Position */ +#define MCAN_IR_RF1L_Msk (_U_(0x1) << MCAN_IR_RF1L_Pos) /**< (MCAN_IR) Receive FIFO 1 Message Lost Mask */ +#define MCAN_IR_RF1L(value) (MCAN_IR_RF1L_Msk & ((value) << MCAN_IR_RF1L_Pos)) +#define MCAN_IR_HPM_Pos _U_(8) /**< (MCAN_IR) High Priority Message Position */ +#define MCAN_IR_HPM_Msk (_U_(0x1) << MCAN_IR_HPM_Pos) /**< (MCAN_IR) High Priority Message Mask */ +#define MCAN_IR_HPM(value) (MCAN_IR_HPM_Msk & ((value) << MCAN_IR_HPM_Pos)) +#define MCAN_IR_TC_Pos _U_(9) /**< (MCAN_IR) Transmission Completed Position */ +#define MCAN_IR_TC_Msk (_U_(0x1) << MCAN_IR_TC_Pos) /**< (MCAN_IR) Transmission Completed Mask */ +#define MCAN_IR_TC(value) (MCAN_IR_TC_Msk & ((value) << MCAN_IR_TC_Pos)) +#define MCAN_IR_TCF_Pos _U_(10) /**< (MCAN_IR) Transmission Cancellation Finished Position */ +#define MCAN_IR_TCF_Msk (_U_(0x1) << MCAN_IR_TCF_Pos) /**< (MCAN_IR) Transmission Cancellation Finished Mask */ +#define MCAN_IR_TCF(value) (MCAN_IR_TCF_Msk & ((value) << MCAN_IR_TCF_Pos)) +#define MCAN_IR_TFE_Pos _U_(11) /**< (MCAN_IR) Tx FIFO Empty Position */ +#define MCAN_IR_TFE_Msk (_U_(0x1) << MCAN_IR_TFE_Pos) /**< (MCAN_IR) Tx FIFO Empty Mask */ +#define MCAN_IR_TFE(value) (MCAN_IR_TFE_Msk & ((value) << MCAN_IR_TFE_Pos)) +#define MCAN_IR_TEFN_Pos _U_(12) /**< (MCAN_IR) Tx Event FIFO New Entry Position */ +#define MCAN_IR_TEFN_Msk (_U_(0x1) << MCAN_IR_TEFN_Pos) /**< (MCAN_IR) Tx Event FIFO New Entry Mask */ +#define MCAN_IR_TEFN(value) (MCAN_IR_TEFN_Msk & ((value) << MCAN_IR_TEFN_Pos)) +#define MCAN_IR_TEFW_Pos _U_(13) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Position */ +#define MCAN_IR_TEFW_Msk (_U_(0x1) << MCAN_IR_TEFW_Pos) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define MCAN_IR_TEFW(value) (MCAN_IR_TEFW_Msk & ((value) << MCAN_IR_TEFW_Pos)) +#define MCAN_IR_TEFF_Pos _U_(14) /**< (MCAN_IR) Tx Event FIFO Full Position */ +#define MCAN_IR_TEFF_Msk (_U_(0x1) << MCAN_IR_TEFF_Pos) /**< (MCAN_IR) Tx Event FIFO Full Mask */ +#define MCAN_IR_TEFF(value) (MCAN_IR_TEFF_Msk & ((value) << MCAN_IR_TEFF_Pos)) +#define MCAN_IR_TEFL_Pos _U_(15) /**< (MCAN_IR) Tx Event FIFO Element Lost Position */ +#define MCAN_IR_TEFL_Msk (_U_(0x1) << MCAN_IR_TEFL_Pos) /**< (MCAN_IR) Tx Event FIFO Element Lost Mask */ +#define MCAN_IR_TEFL(value) (MCAN_IR_TEFL_Msk & ((value) << MCAN_IR_TEFL_Pos)) +#define MCAN_IR_TSW_Pos _U_(16) /**< (MCAN_IR) Timestamp Wraparound Position */ +#define MCAN_IR_TSW_Msk (_U_(0x1) << MCAN_IR_TSW_Pos) /**< (MCAN_IR) Timestamp Wraparound Mask */ +#define MCAN_IR_TSW(value) (MCAN_IR_TSW_Msk & ((value) << MCAN_IR_TSW_Pos)) +#define MCAN_IR_MRAF_Pos _U_(17) /**< (MCAN_IR) Message RAM Access Failure Position */ +#define MCAN_IR_MRAF_Msk (_U_(0x1) << MCAN_IR_MRAF_Pos) /**< (MCAN_IR) Message RAM Access Failure Mask */ +#define MCAN_IR_MRAF(value) (MCAN_IR_MRAF_Msk & ((value) << MCAN_IR_MRAF_Pos)) +#define MCAN_IR_TOO_Pos _U_(18) /**< (MCAN_IR) Timeout Occurred Position */ +#define MCAN_IR_TOO_Msk (_U_(0x1) << MCAN_IR_TOO_Pos) /**< (MCAN_IR) Timeout Occurred Mask */ +#define MCAN_IR_TOO(value) (MCAN_IR_TOO_Msk & ((value) << MCAN_IR_TOO_Pos)) +#define MCAN_IR_DRX_Pos _U_(19) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Position */ +#define MCAN_IR_DRX_Msk (_U_(0x1) << MCAN_IR_DRX_Pos) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Mask */ +#define MCAN_IR_DRX(value) (MCAN_IR_DRX_Msk & ((value) << MCAN_IR_DRX_Pos)) +#define MCAN_IR_ELO_Pos _U_(22) /**< (MCAN_IR) Error Logging Overflow Position */ +#define MCAN_IR_ELO_Msk (_U_(0x1) << MCAN_IR_ELO_Pos) /**< (MCAN_IR) Error Logging Overflow Mask */ +#define MCAN_IR_ELO(value) (MCAN_IR_ELO_Msk & ((value) << MCAN_IR_ELO_Pos)) +#define MCAN_IR_EP_Pos _U_(23) /**< (MCAN_IR) Error Passive Position */ +#define MCAN_IR_EP_Msk (_U_(0x1) << MCAN_IR_EP_Pos) /**< (MCAN_IR) Error Passive Mask */ +#define MCAN_IR_EP(value) (MCAN_IR_EP_Msk & ((value) << MCAN_IR_EP_Pos)) +#define MCAN_IR_EW_Pos _U_(24) /**< (MCAN_IR) Warning Status Position */ +#define MCAN_IR_EW_Msk (_U_(0x1) << MCAN_IR_EW_Pos) /**< (MCAN_IR) Warning Status Mask */ +#define MCAN_IR_EW(value) (MCAN_IR_EW_Msk & ((value) << MCAN_IR_EW_Pos)) +#define MCAN_IR_BO_Pos _U_(25) /**< (MCAN_IR) Bus_Off Status Position */ +#define MCAN_IR_BO_Msk (_U_(0x1) << MCAN_IR_BO_Pos) /**< (MCAN_IR) Bus_Off Status Mask */ +#define MCAN_IR_BO(value) (MCAN_IR_BO_Msk & ((value) << MCAN_IR_BO_Pos)) +#define MCAN_IR_WDI_Pos _U_(26) /**< (MCAN_IR) Watchdog Interrupt Position */ +#define MCAN_IR_WDI_Msk (_U_(0x1) << MCAN_IR_WDI_Pos) /**< (MCAN_IR) Watchdog Interrupt Mask */ +#define MCAN_IR_WDI(value) (MCAN_IR_WDI_Msk & ((value) << MCAN_IR_WDI_Pos)) +#define MCAN_IR_CRCE_Pos _U_(27) /**< (MCAN_IR) CRC Error Position */ +#define MCAN_IR_CRCE_Msk (_U_(0x1) << MCAN_IR_CRCE_Pos) /**< (MCAN_IR) CRC Error Mask */ +#define MCAN_IR_CRCE(value) (MCAN_IR_CRCE_Msk & ((value) << MCAN_IR_CRCE_Pos)) +#define MCAN_IR_BE_Pos _U_(28) /**< (MCAN_IR) Bit Error Position */ +#define MCAN_IR_BE_Msk (_U_(0x1) << MCAN_IR_BE_Pos) /**< (MCAN_IR) Bit Error Mask */ +#define MCAN_IR_BE(value) (MCAN_IR_BE_Msk & ((value) << MCAN_IR_BE_Pos)) +#define MCAN_IR_ACKE_Pos _U_(29) /**< (MCAN_IR) Acknowledge Error Position */ +#define MCAN_IR_ACKE_Msk (_U_(0x1) << MCAN_IR_ACKE_Pos) /**< (MCAN_IR) Acknowledge Error Mask */ +#define MCAN_IR_ACKE(value) (MCAN_IR_ACKE_Msk & ((value) << MCAN_IR_ACKE_Pos)) +#define MCAN_IR_FOE_Pos _U_(30) /**< (MCAN_IR) Format Error Position */ +#define MCAN_IR_FOE_Msk (_U_(0x1) << MCAN_IR_FOE_Pos) /**< (MCAN_IR) Format Error Mask */ +#define MCAN_IR_FOE(value) (MCAN_IR_FOE_Msk & ((value) << MCAN_IR_FOE_Pos)) +#define MCAN_IR_STE_Pos _U_(31) /**< (MCAN_IR) Stuff Error Position */ +#define MCAN_IR_STE_Msk (_U_(0x1) << MCAN_IR_STE_Pos) /**< (MCAN_IR) Stuff Error Mask */ +#define MCAN_IR_STE(value) (MCAN_IR_STE_Msk & ((value) << MCAN_IR_STE_Pos)) +#define MCAN_IR_Msk _U_(0xFFCFFFFF) /**< (MCAN_IR) Register Mask */ + + +/* -------- MCAN_IE : (MCAN Offset: 0x54) (R/W 32) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE_Pos _U_(0) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Position */ +#define MCAN_IE_RF0NE_Msk (_U_(0x1) << MCAN_IE_RF0NE_Pos) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF0NE(value) (MCAN_IE_RF0NE_Msk & ((value) << MCAN_IE_RF0NE_Pos)) +#define MCAN_IE_RF0WE_Pos _U_(1) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF0WE_Msk (_U_(0x1) << MCAN_IE_RF0WE_Pos) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF0WE(value) (MCAN_IE_RF0WE_Msk & ((value) << MCAN_IE_RF0WE_Pos)) +#define MCAN_IE_RF0FE_Pos _U_(2) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Position */ +#define MCAN_IE_RF0FE_Msk (_U_(0x1) << MCAN_IE_RF0FE_Pos) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Mask */ +#define MCAN_IE_RF0FE(value) (MCAN_IE_RF0FE_Msk & ((value) << MCAN_IE_RF0FE_Pos)) +#define MCAN_IE_RF0LE_Pos _U_(3) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF0LE_Msk (_U_(0x1) << MCAN_IE_RF0LE_Pos) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF0LE(value) (MCAN_IE_RF0LE_Msk & ((value) << MCAN_IE_RF0LE_Pos)) +#define MCAN_IE_RF1NE_Pos _U_(4) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Position */ +#define MCAN_IE_RF1NE_Msk (_U_(0x1) << MCAN_IE_RF1NE_Pos) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF1NE(value) (MCAN_IE_RF1NE_Msk & ((value) << MCAN_IE_RF1NE_Pos)) +#define MCAN_IE_RF1WE_Pos _U_(5) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF1WE_Msk (_U_(0x1) << MCAN_IE_RF1WE_Pos) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF1WE(value) (MCAN_IE_RF1WE_Msk & ((value) << MCAN_IE_RF1WE_Pos)) +#define MCAN_IE_RF1FE_Pos _U_(6) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Position */ +#define MCAN_IE_RF1FE_Msk (_U_(0x1) << MCAN_IE_RF1FE_Pos) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Mask */ +#define MCAN_IE_RF1FE(value) (MCAN_IE_RF1FE_Msk & ((value) << MCAN_IE_RF1FE_Pos)) +#define MCAN_IE_RF1LE_Pos _U_(7) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF1LE_Msk (_U_(0x1) << MCAN_IE_RF1LE_Pos) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF1LE(value) (MCAN_IE_RF1LE_Msk & ((value) << MCAN_IE_RF1LE_Pos)) +#define MCAN_IE_HPME_Pos _U_(8) /**< (MCAN_IE) High Priority Message Interrupt Enable Position */ +#define MCAN_IE_HPME_Msk (_U_(0x1) << MCAN_IE_HPME_Pos) /**< (MCAN_IE) High Priority Message Interrupt Enable Mask */ +#define MCAN_IE_HPME(value) (MCAN_IE_HPME_Msk & ((value) << MCAN_IE_HPME_Pos)) +#define MCAN_IE_TCE_Pos _U_(9) /**< (MCAN_IE) Transmission Completed Interrupt Enable Position */ +#define MCAN_IE_TCE_Msk (_U_(0x1) << MCAN_IE_TCE_Pos) /**< (MCAN_IE) Transmission Completed Interrupt Enable Mask */ +#define MCAN_IE_TCE(value) (MCAN_IE_TCE_Msk & ((value) << MCAN_IE_TCE_Pos)) +#define MCAN_IE_TCFE_Pos _U_(10) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define MCAN_IE_TCFE_Msk (_U_(0x1) << MCAN_IE_TCFE_Pos) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define MCAN_IE_TCFE(value) (MCAN_IE_TCFE_Msk & ((value) << MCAN_IE_TCFE_Pos)) +#define MCAN_IE_TFEE_Pos _U_(11) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define MCAN_IE_TFEE_Msk (_U_(0x1) << MCAN_IE_TFEE_Pos) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define MCAN_IE_TFEE(value) (MCAN_IE_TFEE_Msk & ((value) << MCAN_IE_TFEE_Pos)) +#define MCAN_IE_TEFNE_Pos _U_(12) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define MCAN_IE_TEFNE_Msk (_U_(0x1) << MCAN_IE_TEFNE_Pos) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define MCAN_IE_TEFNE(value) (MCAN_IE_TEFNE_Msk & ((value) << MCAN_IE_TEFNE_Pos)) +#define MCAN_IE_TEFWE_Pos _U_(13) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_TEFWE_Msk (_U_(0x1) << MCAN_IE_TEFWE_Pos) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_TEFWE(value) (MCAN_IE_TEFWE_Msk & ((value) << MCAN_IE_TEFWE_Pos)) +#define MCAN_IE_TEFFE_Pos _U_(14) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define MCAN_IE_TEFFE_Msk (_U_(0x1) << MCAN_IE_TEFFE_Pos) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define MCAN_IE_TEFFE(value) (MCAN_IE_TEFFE_Msk & ((value) << MCAN_IE_TEFFE_Pos)) +#define MCAN_IE_TEFLE_Pos _U_(15) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Position */ +#define MCAN_IE_TEFLE_Msk (_U_(0x1) << MCAN_IE_TEFLE_Pos) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Mask */ +#define MCAN_IE_TEFLE(value) (MCAN_IE_TEFLE_Msk & ((value) << MCAN_IE_TEFLE_Pos)) +#define MCAN_IE_TSWE_Pos _U_(16) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define MCAN_IE_TSWE_Msk (_U_(0x1) << MCAN_IE_TSWE_Pos) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define MCAN_IE_TSWE(value) (MCAN_IE_TSWE_Msk & ((value) << MCAN_IE_TSWE_Pos)) +#define MCAN_IE_MRAFE_Pos _U_(17) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define MCAN_IE_MRAFE_Msk (_U_(0x1) << MCAN_IE_MRAFE_Pos) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define MCAN_IE_MRAFE(value) (MCAN_IE_MRAFE_Msk & ((value) << MCAN_IE_MRAFE_Pos)) +#define MCAN_IE_TOOE_Pos _U_(18) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Position */ +#define MCAN_IE_TOOE_Msk (_U_(0x1) << MCAN_IE_TOOE_Pos) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define MCAN_IE_TOOE(value) (MCAN_IE_TOOE_Msk & ((value) << MCAN_IE_TOOE_Pos)) +#define MCAN_IE_DRXE_Pos _U_(19) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Position */ +#define MCAN_IE_DRXE_Msk (_U_(0x1) << MCAN_IE_DRXE_Pos) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Mask */ +#define MCAN_IE_DRXE(value) (MCAN_IE_DRXE_Msk & ((value) << MCAN_IE_DRXE_Pos)) +#define MCAN_IE_ELOE_Pos _U_(22) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define MCAN_IE_ELOE_Msk (_U_(0x1) << MCAN_IE_ELOE_Pos) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define MCAN_IE_ELOE(value) (MCAN_IE_ELOE_Msk & ((value) << MCAN_IE_ELOE_Pos)) +#define MCAN_IE_EPE_Pos _U_(23) /**< (MCAN_IE) Error Passive Interrupt Enable Position */ +#define MCAN_IE_EPE_Msk (_U_(0x1) << MCAN_IE_EPE_Pos) /**< (MCAN_IE) Error Passive Interrupt Enable Mask */ +#define MCAN_IE_EPE(value) (MCAN_IE_EPE_Msk & ((value) << MCAN_IE_EPE_Pos)) +#define MCAN_IE_EWE_Pos _U_(24) /**< (MCAN_IE) Warning Status Interrupt Enable Position */ +#define MCAN_IE_EWE_Msk (_U_(0x1) << MCAN_IE_EWE_Pos) /**< (MCAN_IE) Warning Status Interrupt Enable Mask */ +#define MCAN_IE_EWE(value) (MCAN_IE_EWE_Msk & ((value) << MCAN_IE_EWE_Pos)) +#define MCAN_IE_BOE_Pos _U_(25) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Position */ +#define MCAN_IE_BOE_Msk (_U_(0x1) << MCAN_IE_BOE_Pos) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define MCAN_IE_BOE(value) (MCAN_IE_BOE_Msk & ((value) << MCAN_IE_BOE_Pos)) +#define MCAN_IE_WDIE_Pos _U_(26) /**< (MCAN_IE) Watchdog Interrupt Enable Position */ +#define MCAN_IE_WDIE_Msk (_U_(0x1) << MCAN_IE_WDIE_Pos) /**< (MCAN_IE) Watchdog Interrupt Enable Mask */ +#define MCAN_IE_WDIE(value) (MCAN_IE_WDIE_Msk & ((value) << MCAN_IE_WDIE_Pos)) +#define MCAN_IE_CRCEE_Pos _U_(27) /**< (MCAN_IE) CRC Error Interrupt Enable Position */ +#define MCAN_IE_CRCEE_Msk (_U_(0x1) << MCAN_IE_CRCEE_Pos) /**< (MCAN_IE) CRC Error Interrupt Enable Mask */ +#define MCAN_IE_CRCEE(value) (MCAN_IE_CRCEE_Msk & ((value) << MCAN_IE_CRCEE_Pos)) +#define MCAN_IE_BEE_Pos _U_(28) /**< (MCAN_IE) Bit Error Interrupt Enable Position */ +#define MCAN_IE_BEE_Msk (_U_(0x1) << MCAN_IE_BEE_Pos) /**< (MCAN_IE) Bit Error Interrupt Enable Mask */ +#define MCAN_IE_BEE(value) (MCAN_IE_BEE_Msk & ((value) << MCAN_IE_BEE_Pos)) +#define MCAN_IE_ACKEE_Pos _U_(29) /**< (MCAN_IE) Acknowledge Error Interrupt Enable Position */ +#define MCAN_IE_ACKEE_Msk (_U_(0x1) << MCAN_IE_ACKEE_Pos) /**< (MCAN_IE) Acknowledge Error Interrupt Enable Mask */ +#define MCAN_IE_ACKEE(value) (MCAN_IE_ACKEE_Msk & ((value) << MCAN_IE_ACKEE_Pos)) +#define MCAN_IE_FOEE_Pos _U_(30) /**< (MCAN_IE) Format Error Interrupt Enable Position */ +#define MCAN_IE_FOEE_Msk (_U_(0x1) << MCAN_IE_FOEE_Pos) /**< (MCAN_IE) Format Error Interrupt Enable Mask */ +#define MCAN_IE_FOEE(value) (MCAN_IE_FOEE_Msk & ((value) << MCAN_IE_FOEE_Pos)) +#define MCAN_IE_STEE_Pos _U_(31) /**< (MCAN_IE) Stuff Error Interrupt Enable Position */ +#define MCAN_IE_STEE_Msk (_U_(0x1) << MCAN_IE_STEE_Pos) /**< (MCAN_IE) Stuff Error Interrupt Enable Mask */ +#define MCAN_IE_STEE(value) (MCAN_IE_STEE_Msk & ((value) << MCAN_IE_STEE_Pos)) +#define MCAN_IE_Msk _U_(0xFFCFFFFF) /**< (MCAN_IE) Register Mask */ + + +/* -------- MCAN_ILS : (MCAN Offset: 0x58) (R/W 32) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL_Pos _U_(0) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Position */ +#define MCAN_ILS_RF0NL_Msk (_U_(0x1) << MCAN_ILS_RF0NL_Pos) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF0NL(value) (MCAN_ILS_RF0NL_Msk & ((value) << MCAN_ILS_RF0NL_Pos)) +#define MCAN_ILS_RF0WL_Pos _U_(1) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF0WL_Msk (_U_(0x1) << MCAN_ILS_RF0WL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF0WL(value) (MCAN_ILS_RF0WL_Msk & ((value) << MCAN_ILS_RF0WL_Pos)) +#define MCAN_ILS_RF0FL_Pos _U_(2) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Position */ +#define MCAN_ILS_RF0FL_Msk (_U_(0x1) << MCAN_ILS_RF0FL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Mask */ +#define MCAN_ILS_RF0FL(value) (MCAN_ILS_RF0FL_Msk & ((value) << MCAN_ILS_RF0FL_Pos)) +#define MCAN_ILS_RF0LL_Pos _U_(3) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF0LL_Msk (_U_(0x1) << MCAN_ILS_RF0LL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF0LL(value) (MCAN_ILS_RF0LL_Msk & ((value) << MCAN_ILS_RF0LL_Pos)) +#define MCAN_ILS_RF1NL_Pos _U_(4) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Position */ +#define MCAN_ILS_RF1NL_Msk (_U_(0x1) << MCAN_ILS_RF1NL_Pos) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF1NL(value) (MCAN_ILS_RF1NL_Msk & ((value) << MCAN_ILS_RF1NL_Pos)) +#define MCAN_ILS_RF1WL_Pos _U_(5) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF1WL_Msk (_U_(0x1) << MCAN_ILS_RF1WL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF1WL(value) (MCAN_ILS_RF1WL_Msk & ((value) << MCAN_ILS_RF1WL_Pos)) +#define MCAN_ILS_RF1FL_Pos _U_(6) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Position */ +#define MCAN_ILS_RF1FL_Msk (_U_(0x1) << MCAN_ILS_RF1FL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Mask */ +#define MCAN_ILS_RF1FL(value) (MCAN_ILS_RF1FL_Msk & ((value) << MCAN_ILS_RF1FL_Pos)) +#define MCAN_ILS_RF1LL_Pos _U_(7) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF1LL_Msk (_U_(0x1) << MCAN_ILS_RF1LL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF1LL(value) (MCAN_ILS_RF1LL_Msk & ((value) << MCAN_ILS_RF1LL_Pos)) +#define MCAN_ILS_HPML_Pos _U_(8) /**< (MCAN_ILS) High Priority Message Interrupt Line Position */ +#define MCAN_ILS_HPML_Msk (_U_(0x1) << MCAN_ILS_HPML_Pos) /**< (MCAN_ILS) High Priority Message Interrupt Line Mask */ +#define MCAN_ILS_HPML(value) (MCAN_ILS_HPML_Msk & ((value) << MCAN_ILS_HPML_Pos)) +#define MCAN_ILS_TCL_Pos _U_(9) /**< (MCAN_ILS) Transmission Completed Interrupt Line Position */ +#define MCAN_ILS_TCL_Msk (_U_(0x1) << MCAN_ILS_TCL_Pos) /**< (MCAN_ILS) Transmission Completed Interrupt Line Mask */ +#define MCAN_ILS_TCL(value) (MCAN_ILS_TCL_Msk & ((value) << MCAN_ILS_TCL_Pos)) +#define MCAN_ILS_TCFL_Pos _U_(10) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define MCAN_ILS_TCFL_Msk (_U_(0x1) << MCAN_ILS_TCFL_Pos) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define MCAN_ILS_TCFL(value) (MCAN_ILS_TCFL_Msk & ((value) << MCAN_ILS_TCFL_Pos)) +#define MCAN_ILS_TFEL_Pos _U_(11) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define MCAN_ILS_TFEL_Msk (_U_(0x1) << MCAN_ILS_TFEL_Pos) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define MCAN_ILS_TFEL(value) (MCAN_ILS_TFEL_Msk & ((value) << MCAN_ILS_TFEL_Pos)) +#define MCAN_ILS_TEFNL_Pos _U_(12) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define MCAN_ILS_TEFNL_Msk (_U_(0x1) << MCAN_ILS_TEFNL_Pos) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define MCAN_ILS_TEFNL(value) (MCAN_ILS_TEFNL_Msk & ((value) << MCAN_ILS_TEFNL_Pos)) +#define MCAN_ILS_TEFWL_Pos _U_(13) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_TEFWL_Msk (_U_(0x1) << MCAN_ILS_TEFWL_Pos) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_TEFWL(value) (MCAN_ILS_TEFWL_Msk & ((value) << MCAN_ILS_TEFWL_Pos)) +#define MCAN_ILS_TEFFL_Pos _U_(14) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define MCAN_ILS_TEFFL_Msk (_U_(0x1) << MCAN_ILS_TEFFL_Pos) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define MCAN_ILS_TEFFL(value) (MCAN_ILS_TEFFL_Msk & ((value) << MCAN_ILS_TEFFL_Pos)) +#define MCAN_ILS_TEFLL_Pos _U_(15) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Position */ +#define MCAN_ILS_TEFLL_Msk (_U_(0x1) << MCAN_ILS_TEFLL_Pos) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Mask */ +#define MCAN_ILS_TEFLL(value) (MCAN_ILS_TEFLL_Msk & ((value) << MCAN_ILS_TEFLL_Pos)) +#define MCAN_ILS_TSWL_Pos _U_(16) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define MCAN_ILS_TSWL_Msk (_U_(0x1) << MCAN_ILS_TSWL_Pos) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define MCAN_ILS_TSWL(value) (MCAN_ILS_TSWL_Msk & ((value) << MCAN_ILS_TSWL_Pos)) +#define MCAN_ILS_MRAFL_Pos _U_(17) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define MCAN_ILS_MRAFL_Msk (_U_(0x1) << MCAN_ILS_MRAFL_Pos) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define MCAN_ILS_MRAFL(value) (MCAN_ILS_MRAFL_Msk & ((value) << MCAN_ILS_MRAFL_Pos)) +#define MCAN_ILS_TOOL_Pos _U_(18) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Position */ +#define MCAN_ILS_TOOL_Msk (_U_(0x1) << MCAN_ILS_TOOL_Pos) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define MCAN_ILS_TOOL(value) (MCAN_ILS_TOOL_Msk & ((value) << MCAN_ILS_TOOL_Pos)) +#define MCAN_ILS_DRXL_Pos _U_(19) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Position */ +#define MCAN_ILS_DRXL_Msk (_U_(0x1) << MCAN_ILS_DRXL_Pos) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Mask */ +#define MCAN_ILS_DRXL(value) (MCAN_ILS_DRXL_Msk & ((value) << MCAN_ILS_DRXL_Pos)) +#define MCAN_ILS_ELOL_Pos _U_(22) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define MCAN_ILS_ELOL_Msk (_U_(0x1) << MCAN_ILS_ELOL_Pos) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define MCAN_ILS_ELOL(value) (MCAN_ILS_ELOL_Msk & ((value) << MCAN_ILS_ELOL_Pos)) +#define MCAN_ILS_EPL_Pos _U_(23) /**< (MCAN_ILS) Error Passive Interrupt Line Position */ +#define MCAN_ILS_EPL_Msk (_U_(0x1) << MCAN_ILS_EPL_Pos) /**< (MCAN_ILS) Error Passive Interrupt Line Mask */ +#define MCAN_ILS_EPL(value) (MCAN_ILS_EPL_Msk & ((value) << MCAN_ILS_EPL_Pos)) +#define MCAN_ILS_EWL_Pos _U_(24) /**< (MCAN_ILS) Warning Status Interrupt Line Position */ +#define MCAN_ILS_EWL_Msk (_U_(0x1) << MCAN_ILS_EWL_Pos) /**< (MCAN_ILS) Warning Status Interrupt Line Mask */ +#define MCAN_ILS_EWL(value) (MCAN_ILS_EWL_Msk & ((value) << MCAN_ILS_EWL_Pos)) +#define MCAN_ILS_BOL_Pos _U_(25) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Position */ +#define MCAN_ILS_BOL_Msk (_U_(0x1) << MCAN_ILS_BOL_Pos) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define MCAN_ILS_BOL(value) (MCAN_ILS_BOL_Msk & ((value) << MCAN_ILS_BOL_Pos)) +#define MCAN_ILS_WDIL_Pos _U_(26) /**< (MCAN_ILS) Watchdog Interrupt Line Position */ +#define MCAN_ILS_WDIL_Msk (_U_(0x1) << MCAN_ILS_WDIL_Pos) /**< (MCAN_ILS) Watchdog Interrupt Line Mask */ +#define MCAN_ILS_WDIL(value) (MCAN_ILS_WDIL_Msk & ((value) << MCAN_ILS_WDIL_Pos)) +#define MCAN_ILS_CRCEL_Pos _U_(27) /**< (MCAN_ILS) CRC Error Interrupt Line Position */ +#define MCAN_ILS_CRCEL_Msk (_U_(0x1) << MCAN_ILS_CRCEL_Pos) /**< (MCAN_ILS) CRC Error Interrupt Line Mask */ +#define MCAN_ILS_CRCEL(value) (MCAN_ILS_CRCEL_Msk & ((value) << MCAN_ILS_CRCEL_Pos)) +#define MCAN_ILS_BEL_Pos _U_(28) /**< (MCAN_ILS) Bit Error Interrupt Line Position */ +#define MCAN_ILS_BEL_Msk (_U_(0x1) << MCAN_ILS_BEL_Pos) /**< (MCAN_ILS) Bit Error Interrupt Line Mask */ +#define MCAN_ILS_BEL(value) (MCAN_ILS_BEL_Msk & ((value) << MCAN_ILS_BEL_Pos)) +#define MCAN_ILS_ACKEL_Pos _U_(29) /**< (MCAN_ILS) Acknowledge Error Interrupt Line Position */ +#define MCAN_ILS_ACKEL_Msk (_U_(0x1) << MCAN_ILS_ACKEL_Pos) /**< (MCAN_ILS) Acknowledge Error Interrupt Line Mask */ +#define MCAN_ILS_ACKEL(value) (MCAN_ILS_ACKEL_Msk & ((value) << MCAN_ILS_ACKEL_Pos)) +#define MCAN_ILS_FOEL_Pos _U_(30) /**< (MCAN_ILS) Format Error Interrupt Line Position */ +#define MCAN_ILS_FOEL_Msk (_U_(0x1) << MCAN_ILS_FOEL_Pos) /**< (MCAN_ILS) Format Error Interrupt Line Mask */ +#define MCAN_ILS_FOEL(value) (MCAN_ILS_FOEL_Msk & ((value) << MCAN_ILS_FOEL_Pos)) +#define MCAN_ILS_STEL_Pos _U_(31) /**< (MCAN_ILS) Stuff Error Interrupt Line Position */ +#define MCAN_ILS_STEL_Msk (_U_(0x1) << MCAN_ILS_STEL_Pos) /**< (MCAN_ILS) Stuff Error Interrupt Line Mask */ +#define MCAN_ILS_STEL(value) (MCAN_ILS_STEL_Msk & ((value) << MCAN_ILS_STEL_Pos)) +#define MCAN_ILS_Msk _U_(0xFFCFFFFF) /**< (MCAN_ILS) Register Mask */ + + +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) (R/W 32) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0_Pos _U_(0) /**< (MCAN_ILE) Enable Interrupt Line 0 Position */ +#define MCAN_ILE_EINT0_Msk (_U_(0x1) << MCAN_ILE_EINT0_Pos) /**< (MCAN_ILE) Enable Interrupt Line 0 Mask */ +#define MCAN_ILE_EINT0(value) (MCAN_ILE_EINT0_Msk & ((value) << MCAN_ILE_EINT0_Pos)) +#define MCAN_ILE_EINT1_Pos _U_(1) /**< (MCAN_ILE) Enable Interrupt Line 1 Position */ +#define MCAN_ILE_EINT1_Msk (_U_(0x1) << MCAN_ILE_EINT1_Pos) /**< (MCAN_ILE) Enable Interrupt Line 1 Mask */ +#define MCAN_ILE_EINT1(value) (MCAN_ILE_EINT1_Msk & ((value) << MCAN_ILE_EINT1_Pos)) +#define MCAN_ILE_Msk _U_(0x00000003) /**< (MCAN_ILE) Register Mask */ + +#define MCAN_ILE_EINT_Pos _U_(0) /**< (MCAN_ILE Position) Enable Interrupt Line x */ +#define MCAN_ILE_EINT_Msk (_U_(0x3) << MCAN_ILE_EINT_Pos) /**< (MCAN_ILE Mask) EINT */ +#define MCAN_ILE_EINT(value) (MCAN_ILE_EINT_Msk & ((value) << MCAN_ILE_EINT_Pos)) + +/* -------- MCAN_GFC : (MCAN Offset: 0x80) (R/W 32) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE_Pos _U_(0) /**< (MCAN_GFC) Reject Remote Frames Extended Position */ +#define MCAN_GFC_RRFE_Msk (_U_(0x1) << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject Remote Frames Extended Mask */ +#define MCAN_GFC_RRFE(value) (MCAN_GFC_RRFE_Msk & ((value) << MCAN_GFC_RRFE_Pos)) +#define MCAN_GFC_RRFE_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_FILTER (MCAN_GFC_RRFE_FILTER_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFE_REJECT (MCAN_GFC_RRFE_REJECT_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFS_Pos _U_(1) /**< (MCAN_GFC) Reject Remote Frames Standard Position */ +#define MCAN_GFC_RRFS_Msk (_U_(0x1) << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject Remote Frames Standard Mask */ +#define MCAN_GFC_RRFS(value) (MCAN_GFC_RRFS_Msk & ((value) << MCAN_GFC_RRFS_Pos)) +#define MCAN_GFC_RRFS_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_FILTER (MCAN_GFC_RRFS_FILTER_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_RRFS_REJECT (MCAN_GFC_RRFS_REJECT_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_ANFE_Pos _U_(2) /**< (MCAN_GFC) Accept Non-matching Frames Extended Position */ +#define MCAN_GFC_ANFE_Msk (_U_(0x3) << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Extended Mask */ +#define MCAN_GFC_ANFE(value) (MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)) +#define MCAN_GFC_ANFE_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFE_RX_FIFO_0 (MCAN_GFC_ANFE_RX_FIFO_0_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Message stored in Receive FIFO 0 Position */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (MCAN_GFC_ANFE_RX_FIFO_1_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Message stored in Receive FIFO 1 Position */ +#define MCAN_GFC_ANFS_Pos _U_(4) /**< (MCAN_GFC) Accept Non-matching Frames Standard Position */ +#define MCAN_GFC_ANFS_Msk (_U_(0x3) << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Standard Mask */ +#define MCAN_GFC_ANFS(value) (MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)) +#define MCAN_GFC_ANFS_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_RX_FIFO_0 (MCAN_GFC_ANFS_RX_FIFO_0_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Message stored in Receive FIFO 0 Position */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (MCAN_GFC_ANFS_RX_FIFO_1_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Message stored in Receive FIFO 1 Position */ +#define MCAN_GFC_Msk _U_(0x0000003F) /**< (MCAN_GFC) Register Mask */ + + +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos _U_(2) /**< (MCAN_SIDFC) Filter List Standard Start Address Position */ +#define MCAN_SIDFC_FLSSA_Msk (_U_(0x3FFF) << MCAN_SIDFC_FLSSA_Pos) /**< (MCAN_SIDFC) Filter List Standard Start Address Mask */ +#define MCAN_SIDFC_FLSSA(value) (MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)) +#define MCAN_SIDFC_LSS_Pos _U_(16) /**< (MCAN_SIDFC) List Size Standard Position */ +#define MCAN_SIDFC_LSS_Msk (_U_(0xFF) << MCAN_SIDFC_LSS_Pos) /**< (MCAN_SIDFC) List Size Standard Mask */ +#define MCAN_SIDFC_LSS(value) (MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)) +#define MCAN_SIDFC_Msk _U_(0x00FFFFFC) /**< (MCAN_SIDFC) Register Mask */ + + +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos _U_(2) /**< (MCAN_XIDFC) Filter List Extended Start Address Position */ +#define MCAN_XIDFC_FLESA_Msk (_U_(0x3FFF) << MCAN_XIDFC_FLESA_Pos) /**< (MCAN_XIDFC) Filter List Extended Start Address Mask */ +#define MCAN_XIDFC_FLESA(value) (MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)) +#define MCAN_XIDFC_LSE_Pos _U_(16) /**< (MCAN_XIDFC) List Size Extended Position */ +#define MCAN_XIDFC_LSE_Msk (_U_(0x7F) << MCAN_XIDFC_LSE_Pos) /**< (MCAN_XIDFC) List Size Extended Mask */ +#define MCAN_XIDFC_LSE(value) (MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)) +#define MCAN_XIDFC_Msk _U_(0x007FFFFC) /**< (MCAN_XIDFC) Register Mask */ + + +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) (R/W 32) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos _U_(0) /**< (MCAN_XIDAM) Extended ID Mask Position */ +#define MCAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << MCAN_XIDAM_EIDM_Pos) /**< (MCAN_XIDAM) Extended ID Mask Mask */ +#define MCAN_XIDAM_EIDM(value) (MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)) +#define MCAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (MCAN_XIDAM) Register Mask */ + + +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) ( R/ 32) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos _U_(0) /**< (MCAN_HPMS) Buffer Index Position */ +#define MCAN_HPMS_BIDX_Msk (_U_(0x3F) << MCAN_HPMS_BIDX_Pos) /**< (MCAN_HPMS) Buffer Index Mask */ +#define MCAN_HPMS_BIDX(value) (MCAN_HPMS_BIDX_Msk & ((value) << MCAN_HPMS_BIDX_Pos)) +#define MCAN_HPMS_MSI_Pos _U_(6) /**< (MCAN_HPMS) Message Storage Indicator Position */ +#define MCAN_HPMS_MSI_Msk (_U_(0x3) << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message Storage Indicator Mask */ +#define MCAN_HPMS_MSI(value) (MCAN_HPMS_MSI_Msk & ((value) << MCAN_HPMS_MSI_Pos)) +#define MCAN_HPMS_MSI_NO_FIFO_SEL_Val _U_(0x0) /**< (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0_Val _U_(0x2) /**< (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1_Val _U_(0x3) /**< (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (MCAN_HPMS_MSI_NO_FIFO_SEL_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) No FIFO selected. Position */ +#define MCAN_HPMS_MSI_LOST (MCAN_HPMS_MSI_LOST_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) FIFO message. Position */ +#define MCAN_HPMS_MSI_FIFO_0 (MCAN_HPMS_MSI_FIFO_0_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 0. Position */ +#define MCAN_HPMS_MSI_FIFO_1 (MCAN_HPMS_MSI_FIFO_1_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 1. Position */ +#define MCAN_HPMS_FIDX_Pos _U_(8) /**< (MCAN_HPMS) Filter Index Position */ +#define MCAN_HPMS_FIDX_Msk (_U_(0x7F) << MCAN_HPMS_FIDX_Pos) /**< (MCAN_HPMS) Filter Index Mask */ +#define MCAN_HPMS_FIDX(value) (MCAN_HPMS_FIDX_Msk & ((value) << MCAN_HPMS_FIDX_Pos)) +#define MCAN_HPMS_FLST_Pos _U_(15) /**< (MCAN_HPMS) Filter List Position */ +#define MCAN_HPMS_FLST_Msk (_U_(0x1) << MCAN_HPMS_FLST_Pos) /**< (MCAN_HPMS) Filter List Mask */ +#define MCAN_HPMS_FLST(value) (MCAN_HPMS_FLST_Msk & ((value) << MCAN_HPMS_FLST_Pos)) +#define MCAN_HPMS_Msk _U_(0x0000FFFF) /**< (MCAN_HPMS) Register Mask */ + + +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) (R/W 32) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0_Pos _U_(0) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND0_Msk (_U_(0x1) << MCAN_NDAT1_ND0_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND0(value) (MCAN_NDAT1_ND0_Msk & ((value) << MCAN_NDAT1_ND0_Pos)) +#define MCAN_NDAT1_ND1_Pos _U_(1) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND1_Msk (_U_(0x1) << MCAN_NDAT1_ND1_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND1(value) (MCAN_NDAT1_ND1_Msk & ((value) << MCAN_NDAT1_ND1_Pos)) +#define MCAN_NDAT1_ND2_Pos _U_(2) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND2_Msk (_U_(0x1) << MCAN_NDAT1_ND2_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND2(value) (MCAN_NDAT1_ND2_Msk & ((value) << MCAN_NDAT1_ND2_Pos)) +#define MCAN_NDAT1_ND3_Pos _U_(3) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND3_Msk (_U_(0x1) << MCAN_NDAT1_ND3_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND3(value) (MCAN_NDAT1_ND3_Msk & ((value) << MCAN_NDAT1_ND3_Pos)) +#define MCAN_NDAT1_ND4_Pos _U_(4) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND4_Msk (_U_(0x1) << MCAN_NDAT1_ND4_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND4(value) (MCAN_NDAT1_ND4_Msk & ((value) << MCAN_NDAT1_ND4_Pos)) +#define MCAN_NDAT1_ND5_Pos _U_(5) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND5_Msk (_U_(0x1) << MCAN_NDAT1_ND5_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND5(value) (MCAN_NDAT1_ND5_Msk & ((value) << MCAN_NDAT1_ND5_Pos)) +#define MCAN_NDAT1_ND6_Pos _U_(6) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND6_Msk (_U_(0x1) << MCAN_NDAT1_ND6_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND6(value) (MCAN_NDAT1_ND6_Msk & ((value) << MCAN_NDAT1_ND6_Pos)) +#define MCAN_NDAT1_ND7_Pos _U_(7) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND7_Msk (_U_(0x1) << MCAN_NDAT1_ND7_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND7(value) (MCAN_NDAT1_ND7_Msk & ((value) << MCAN_NDAT1_ND7_Pos)) +#define MCAN_NDAT1_ND8_Pos _U_(8) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND8_Msk (_U_(0x1) << MCAN_NDAT1_ND8_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND8(value) (MCAN_NDAT1_ND8_Msk & ((value) << MCAN_NDAT1_ND8_Pos)) +#define MCAN_NDAT1_ND9_Pos _U_(9) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND9_Msk (_U_(0x1) << MCAN_NDAT1_ND9_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND9(value) (MCAN_NDAT1_ND9_Msk & ((value) << MCAN_NDAT1_ND9_Pos)) +#define MCAN_NDAT1_ND10_Pos _U_(10) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND10_Msk (_U_(0x1) << MCAN_NDAT1_ND10_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND10(value) (MCAN_NDAT1_ND10_Msk & ((value) << MCAN_NDAT1_ND10_Pos)) +#define MCAN_NDAT1_ND11_Pos _U_(11) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND11_Msk (_U_(0x1) << MCAN_NDAT1_ND11_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND11(value) (MCAN_NDAT1_ND11_Msk & ((value) << MCAN_NDAT1_ND11_Pos)) +#define MCAN_NDAT1_ND12_Pos _U_(12) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND12_Msk (_U_(0x1) << MCAN_NDAT1_ND12_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND12(value) (MCAN_NDAT1_ND12_Msk & ((value) << MCAN_NDAT1_ND12_Pos)) +#define MCAN_NDAT1_ND13_Pos _U_(13) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND13_Msk (_U_(0x1) << MCAN_NDAT1_ND13_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND13(value) (MCAN_NDAT1_ND13_Msk & ((value) << MCAN_NDAT1_ND13_Pos)) +#define MCAN_NDAT1_ND14_Pos _U_(14) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND14_Msk (_U_(0x1) << MCAN_NDAT1_ND14_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND14(value) (MCAN_NDAT1_ND14_Msk & ((value) << MCAN_NDAT1_ND14_Pos)) +#define MCAN_NDAT1_ND15_Pos _U_(15) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND15_Msk (_U_(0x1) << MCAN_NDAT1_ND15_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND15(value) (MCAN_NDAT1_ND15_Msk & ((value) << MCAN_NDAT1_ND15_Pos)) +#define MCAN_NDAT1_ND16_Pos _U_(16) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND16_Msk (_U_(0x1) << MCAN_NDAT1_ND16_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND16(value) (MCAN_NDAT1_ND16_Msk & ((value) << MCAN_NDAT1_ND16_Pos)) +#define MCAN_NDAT1_ND17_Pos _U_(17) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND17_Msk (_U_(0x1) << MCAN_NDAT1_ND17_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND17(value) (MCAN_NDAT1_ND17_Msk & ((value) << MCAN_NDAT1_ND17_Pos)) +#define MCAN_NDAT1_ND18_Pos _U_(18) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND18_Msk (_U_(0x1) << MCAN_NDAT1_ND18_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND18(value) (MCAN_NDAT1_ND18_Msk & ((value) << MCAN_NDAT1_ND18_Pos)) +#define MCAN_NDAT1_ND19_Pos _U_(19) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND19_Msk (_U_(0x1) << MCAN_NDAT1_ND19_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND19(value) (MCAN_NDAT1_ND19_Msk & ((value) << MCAN_NDAT1_ND19_Pos)) +#define MCAN_NDAT1_ND20_Pos _U_(20) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND20_Msk (_U_(0x1) << MCAN_NDAT1_ND20_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND20(value) (MCAN_NDAT1_ND20_Msk & ((value) << MCAN_NDAT1_ND20_Pos)) +#define MCAN_NDAT1_ND21_Pos _U_(21) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND21_Msk (_U_(0x1) << MCAN_NDAT1_ND21_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND21(value) (MCAN_NDAT1_ND21_Msk & ((value) << MCAN_NDAT1_ND21_Pos)) +#define MCAN_NDAT1_ND22_Pos _U_(22) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND22_Msk (_U_(0x1) << MCAN_NDAT1_ND22_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND22(value) (MCAN_NDAT1_ND22_Msk & ((value) << MCAN_NDAT1_ND22_Pos)) +#define MCAN_NDAT1_ND23_Pos _U_(23) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND23_Msk (_U_(0x1) << MCAN_NDAT1_ND23_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND23(value) (MCAN_NDAT1_ND23_Msk & ((value) << MCAN_NDAT1_ND23_Pos)) +#define MCAN_NDAT1_ND24_Pos _U_(24) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND24_Msk (_U_(0x1) << MCAN_NDAT1_ND24_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND24(value) (MCAN_NDAT1_ND24_Msk & ((value) << MCAN_NDAT1_ND24_Pos)) +#define MCAN_NDAT1_ND25_Pos _U_(25) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND25_Msk (_U_(0x1) << MCAN_NDAT1_ND25_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND25(value) (MCAN_NDAT1_ND25_Msk & ((value) << MCAN_NDAT1_ND25_Pos)) +#define MCAN_NDAT1_ND26_Pos _U_(26) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND26_Msk (_U_(0x1) << MCAN_NDAT1_ND26_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND26(value) (MCAN_NDAT1_ND26_Msk & ((value) << MCAN_NDAT1_ND26_Pos)) +#define MCAN_NDAT1_ND27_Pos _U_(27) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND27_Msk (_U_(0x1) << MCAN_NDAT1_ND27_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND27(value) (MCAN_NDAT1_ND27_Msk & ((value) << MCAN_NDAT1_ND27_Pos)) +#define MCAN_NDAT1_ND28_Pos _U_(28) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND28_Msk (_U_(0x1) << MCAN_NDAT1_ND28_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND28(value) (MCAN_NDAT1_ND28_Msk & ((value) << MCAN_NDAT1_ND28_Pos)) +#define MCAN_NDAT1_ND29_Pos _U_(29) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND29_Msk (_U_(0x1) << MCAN_NDAT1_ND29_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND29(value) (MCAN_NDAT1_ND29_Msk & ((value) << MCAN_NDAT1_ND29_Pos)) +#define MCAN_NDAT1_ND30_Pos _U_(30) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND30_Msk (_U_(0x1) << MCAN_NDAT1_ND30_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND30(value) (MCAN_NDAT1_ND30_Msk & ((value) << MCAN_NDAT1_ND30_Pos)) +#define MCAN_NDAT1_ND31_Pos _U_(31) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND31_Msk (_U_(0x1) << MCAN_NDAT1_ND31_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND31(value) (MCAN_NDAT1_ND31_Msk & ((value) << MCAN_NDAT1_ND31_Pos)) +#define MCAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT1) Register Mask */ + +#define MCAN_NDAT1_ND_Pos _U_(0) /**< (MCAN_NDAT1 Position) New Data */ +#define MCAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT1_ND_Pos) /**< (MCAN_NDAT1 Mask) ND */ +#define MCAN_NDAT1_ND(value) (MCAN_NDAT1_ND_Msk & ((value) << MCAN_NDAT1_ND_Pos)) + +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) (R/W 32) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32_Pos _U_(0) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND32_Msk (_U_(0x1) << MCAN_NDAT2_ND32_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND32(value) (MCAN_NDAT2_ND32_Msk & ((value) << MCAN_NDAT2_ND32_Pos)) +#define MCAN_NDAT2_ND33_Pos _U_(1) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND33_Msk (_U_(0x1) << MCAN_NDAT2_ND33_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND33(value) (MCAN_NDAT2_ND33_Msk & ((value) << MCAN_NDAT2_ND33_Pos)) +#define MCAN_NDAT2_ND34_Pos _U_(2) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND34_Msk (_U_(0x1) << MCAN_NDAT2_ND34_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND34(value) (MCAN_NDAT2_ND34_Msk & ((value) << MCAN_NDAT2_ND34_Pos)) +#define MCAN_NDAT2_ND35_Pos _U_(3) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND35_Msk (_U_(0x1) << MCAN_NDAT2_ND35_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND35(value) (MCAN_NDAT2_ND35_Msk & ((value) << MCAN_NDAT2_ND35_Pos)) +#define MCAN_NDAT2_ND36_Pos _U_(4) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND36_Msk (_U_(0x1) << MCAN_NDAT2_ND36_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND36(value) (MCAN_NDAT2_ND36_Msk & ((value) << MCAN_NDAT2_ND36_Pos)) +#define MCAN_NDAT2_ND37_Pos _U_(5) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND37_Msk (_U_(0x1) << MCAN_NDAT2_ND37_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND37(value) (MCAN_NDAT2_ND37_Msk & ((value) << MCAN_NDAT2_ND37_Pos)) +#define MCAN_NDAT2_ND38_Pos _U_(6) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND38_Msk (_U_(0x1) << MCAN_NDAT2_ND38_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND38(value) (MCAN_NDAT2_ND38_Msk & ((value) << MCAN_NDAT2_ND38_Pos)) +#define MCAN_NDAT2_ND39_Pos _U_(7) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND39_Msk (_U_(0x1) << MCAN_NDAT2_ND39_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND39(value) (MCAN_NDAT2_ND39_Msk & ((value) << MCAN_NDAT2_ND39_Pos)) +#define MCAN_NDAT2_ND40_Pos _U_(8) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND40_Msk (_U_(0x1) << MCAN_NDAT2_ND40_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND40(value) (MCAN_NDAT2_ND40_Msk & ((value) << MCAN_NDAT2_ND40_Pos)) +#define MCAN_NDAT2_ND41_Pos _U_(9) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND41_Msk (_U_(0x1) << MCAN_NDAT2_ND41_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND41(value) (MCAN_NDAT2_ND41_Msk & ((value) << MCAN_NDAT2_ND41_Pos)) +#define MCAN_NDAT2_ND42_Pos _U_(10) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND42_Msk (_U_(0x1) << MCAN_NDAT2_ND42_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND42(value) (MCAN_NDAT2_ND42_Msk & ((value) << MCAN_NDAT2_ND42_Pos)) +#define MCAN_NDAT2_ND43_Pos _U_(11) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND43_Msk (_U_(0x1) << MCAN_NDAT2_ND43_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND43(value) (MCAN_NDAT2_ND43_Msk & ((value) << MCAN_NDAT2_ND43_Pos)) +#define MCAN_NDAT2_ND44_Pos _U_(12) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND44_Msk (_U_(0x1) << MCAN_NDAT2_ND44_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND44(value) (MCAN_NDAT2_ND44_Msk & ((value) << MCAN_NDAT2_ND44_Pos)) +#define MCAN_NDAT2_ND45_Pos _U_(13) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND45_Msk (_U_(0x1) << MCAN_NDAT2_ND45_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND45(value) (MCAN_NDAT2_ND45_Msk & ((value) << MCAN_NDAT2_ND45_Pos)) +#define MCAN_NDAT2_ND46_Pos _U_(14) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND46_Msk (_U_(0x1) << MCAN_NDAT2_ND46_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND46(value) (MCAN_NDAT2_ND46_Msk & ((value) << MCAN_NDAT2_ND46_Pos)) +#define MCAN_NDAT2_ND47_Pos _U_(15) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND47_Msk (_U_(0x1) << MCAN_NDAT2_ND47_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND47(value) (MCAN_NDAT2_ND47_Msk & ((value) << MCAN_NDAT2_ND47_Pos)) +#define MCAN_NDAT2_ND48_Pos _U_(16) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND48_Msk (_U_(0x1) << MCAN_NDAT2_ND48_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND48(value) (MCAN_NDAT2_ND48_Msk & ((value) << MCAN_NDAT2_ND48_Pos)) +#define MCAN_NDAT2_ND49_Pos _U_(17) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND49_Msk (_U_(0x1) << MCAN_NDAT2_ND49_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND49(value) (MCAN_NDAT2_ND49_Msk & ((value) << MCAN_NDAT2_ND49_Pos)) +#define MCAN_NDAT2_ND50_Pos _U_(18) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND50_Msk (_U_(0x1) << MCAN_NDAT2_ND50_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND50(value) (MCAN_NDAT2_ND50_Msk & ((value) << MCAN_NDAT2_ND50_Pos)) +#define MCAN_NDAT2_ND51_Pos _U_(19) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND51_Msk (_U_(0x1) << MCAN_NDAT2_ND51_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND51(value) (MCAN_NDAT2_ND51_Msk & ((value) << MCAN_NDAT2_ND51_Pos)) +#define MCAN_NDAT2_ND52_Pos _U_(20) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND52_Msk (_U_(0x1) << MCAN_NDAT2_ND52_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND52(value) (MCAN_NDAT2_ND52_Msk & ((value) << MCAN_NDAT2_ND52_Pos)) +#define MCAN_NDAT2_ND53_Pos _U_(21) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND53_Msk (_U_(0x1) << MCAN_NDAT2_ND53_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND53(value) (MCAN_NDAT2_ND53_Msk & ((value) << MCAN_NDAT2_ND53_Pos)) +#define MCAN_NDAT2_ND54_Pos _U_(22) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND54_Msk (_U_(0x1) << MCAN_NDAT2_ND54_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND54(value) (MCAN_NDAT2_ND54_Msk & ((value) << MCAN_NDAT2_ND54_Pos)) +#define MCAN_NDAT2_ND55_Pos _U_(23) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND55_Msk (_U_(0x1) << MCAN_NDAT2_ND55_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND55(value) (MCAN_NDAT2_ND55_Msk & ((value) << MCAN_NDAT2_ND55_Pos)) +#define MCAN_NDAT2_ND56_Pos _U_(24) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND56_Msk (_U_(0x1) << MCAN_NDAT2_ND56_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND56(value) (MCAN_NDAT2_ND56_Msk & ((value) << MCAN_NDAT2_ND56_Pos)) +#define MCAN_NDAT2_ND57_Pos _U_(25) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND57_Msk (_U_(0x1) << MCAN_NDAT2_ND57_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND57(value) (MCAN_NDAT2_ND57_Msk & ((value) << MCAN_NDAT2_ND57_Pos)) +#define MCAN_NDAT2_ND58_Pos _U_(26) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND58_Msk (_U_(0x1) << MCAN_NDAT2_ND58_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND58(value) (MCAN_NDAT2_ND58_Msk & ((value) << MCAN_NDAT2_ND58_Pos)) +#define MCAN_NDAT2_ND59_Pos _U_(27) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND59_Msk (_U_(0x1) << MCAN_NDAT2_ND59_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND59(value) (MCAN_NDAT2_ND59_Msk & ((value) << MCAN_NDAT2_ND59_Pos)) +#define MCAN_NDAT2_ND60_Pos _U_(28) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND60_Msk (_U_(0x1) << MCAN_NDAT2_ND60_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND60(value) (MCAN_NDAT2_ND60_Msk & ((value) << MCAN_NDAT2_ND60_Pos)) +#define MCAN_NDAT2_ND61_Pos _U_(29) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND61_Msk (_U_(0x1) << MCAN_NDAT2_ND61_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND61(value) (MCAN_NDAT2_ND61_Msk & ((value) << MCAN_NDAT2_ND61_Pos)) +#define MCAN_NDAT2_ND62_Pos _U_(30) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND62_Msk (_U_(0x1) << MCAN_NDAT2_ND62_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND62(value) (MCAN_NDAT2_ND62_Msk & ((value) << MCAN_NDAT2_ND62_Pos)) +#define MCAN_NDAT2_ND63_Pos _U_(31) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND63_Msk (_U_(0x1) << MCAN_NDAT2_ND63_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND63(value) (MCAN_NDAT2_ND63_Msk & ((value) << MCAN_NDAT2_ND63_Pos)) +#define MCAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT2) Register Mask */ + +#define MCAN_NDAT2_ND_Pos _U_(0) /**< (MCAN_NDAT2 Position) New Data */ +#define MCAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT2_ND_Pos) /**< (MCAN_NDAT2 Mask) ND */ +#define MCAN_NDAT2_ND(value) (MCAN_NDAT2_ND_Msk & ((value) << MCAN_NDAT2_ND_Pos)) + +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) (R/W 32) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos _U_(2) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0SA_Msk (_U_(0x3FFF) << MCAN_RXF0C_F0SA_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0SA(value) (MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)) +#define MCAN_RXF0C_F0S_Pos _U_(16) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0S_Msk (_U_(0x7F) << MCAN_RXF0C_F0S_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0S(value) (MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)) +#define MCAN_RXF0C_F0WM_Pos _U_(24) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Position */ +#define MCAN_RXF0C_F0WM_Msk (_U_(0x7F) << MCAN_RXF0C_F0WM_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Mask */ +#define MCAN_RXF0C_F0WM(value) (MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)) +#define MCAN_RXF0C_F0OM_Pos _U_(31) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Position */ +#define MCAN_RXF0C_F0OM_Msk (_U_(0x1) << MCAN_RXF0C_F0OM_Pos) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define MCAN_RXF0C_F0OM(value) (MCAN_RXF0C_F0OM_Msk & ((value) << MCAN_RXF0C_F0OM_Pos)) +#define MCAN_RXF0C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF0C) Register Mask */ + + +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) ( R/ 32) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos _U_(0) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0FL_Msk (_U_(0x7F) << MCAN_RXF0S_F0FL_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0FL(value) (MCAN_RXF0S_F0FL_Msk & ((value) << MCAN_RXF0S_F0FL_Pos)) +#define MCAN_RXF0S_F0GI_Pos _U_(8) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Position */ +#define MCAN_RXF0S_F0GI_Msk (_U_(0x3F) << MCAN_RXF0S_F0GI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Mask */ +#define MCAN_RXF0S_F0GI(value) (MCAN_RXF0S_F0GI_Msk & ((value) << MCAN_RXF0S_F0GI_Pos)) +#define MCAN_RXF0S_F0PI_Pos _U_(16) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Position */ +#define MCAN_RXF0S_F0PI_Msk (_U_(0x3F) << MCAN_RXF0S_F0PI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Mask */ +#define MCAN_RXF0S_F0PI(value) (MCAN_RXF0S_F0PI_Msk & ((value) << MCAN_RXF0S_F0PI_Pos)) +#define MCAN_RXF0S_F0F_Pos _U_(24) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0F_Msk (_U_(0x1) << MCAN_RXF0S_F0F_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0F(value) (MCAN_RXF0S_F0F_Msk & ((value) << MCAN_RXF0S_F0F_Pos)) +#define MCAN_RXF0S_RF0L_Pos _U_(25) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Position */ +#define MCAN_RXF0S_RF0L_Msk (_U_(0x1) << MCAN_RXF0S_RF0L_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Mask */ +#define MCAN_RXF0S_RF0L(value) (MCAN_RXF0S_RF0L_Msk & ((value) << MCAN_RXF0S_RF0L_Pos)) +#define MCAN_RXF0S_Msk _U_(0x033F3F7F) /**< (MCAN_RXF0S) Register Mask */ + + +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) (R/W 32) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos _U_(0) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Position */ +#define MCAN_RXF0A_F0AI_Msk (_U_(0x3F) << MCAN_RXF0A_F0AI_Pos) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Mask */ +#define MCAN_RXF0A_F0AI(value) (MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)) +#define MCAN_RXF0A_Msk _U_(0x0000003F) /**< (MCAN_RXF0A) Register Mask */ + + +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) (R/W 32) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos _U_(2) /**< (MCAN_RXBC) Receive Buffer Start Address Position */ +#define MCAN_RXBC_RBSA_Msk (_U_(0x3FFF) << MCAN_RXBC_RBSA_Pos) /**< (MCAN_RXBC) Receive Buffer Start Address Mask */ +#define MCAN_RXBC_RBSA(value) (MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)) +#define MCAN_RXBC_Msk _U_(0x0000FFFC) /**< (MCAN_RXBC) Register Mask */ + + +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) (R/W 32) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos _U_(2) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1SA_Msk (_U_(0x3FFF) << MCAN_RXF1C_F1SA_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1SA(value) (MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)) +#define MCAN_RXF1C_F1S_Pos _U_(16) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1S_Msk (_U_(0x7F) << MCAN_RXF1C_F1S_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1S(value) (MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)) +#define MCAN_RXF1C_F1WM_Pos _U_(24) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Position */ +#define MCAN_RXF1C_F1WM_Msk (_U_(0x7F) << MCAN_RXF1C_F1WM_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Mask */ +#define MCAN_RXF1C_F1WM(value) (MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)) +#define MCAN_RXF1C_F1OM_Pos _U_(31) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Position */ +#define MCAN_RXF1C_F1OM_Msk (_U_(0x1) << MCAN_RXF1C_F1OM_Pos) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define MCAN_RXF1C_F1OM(value) (MCAN_RXF1C_F1OM_Msk & ((value) << MCAN_RXF1C_F1OM_Pos)) +#define MCAN_RXF1C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF1C) Register Mask */ + + +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) ( R/ 32) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos _U_(0) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1FL_Msk (_U_(0x7F) << MCAN_RXF1S_F1FL_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1FL(value) (MCAN_RXF1S_F1FL_Msk & ((value) << MCAN_RXF1S_F1FL_Pos)) +#define MCAN_RXF1S_F1GI_Pos _U_(8) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Position */ +#define MCAN_RXF1S_F1GI_Msk (_U_(0x3F) << MCAN_RXF1S_F1GI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Mask */ +#define MCAN_RXF1S_F1GI(value) (MCAN_RXF1S_F1GI_Msk & ((value) << MCAN_RXF1S_F1GI_Pos)) +#define MCAN_RXF1S_F1PI_Pos _U_(16) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Position */ +#define MCAN_RXF1S_F1PI_Msk (_U_(0x3F) << MCAN_RXF1S_F1PI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Mask */ +#define MCAN_RXF1S_F1PI(value) (MCAN_RXF1S_F1PI_Msk & ((value) << MCAN_RXF1S_F1PI_Pos)) +#define MCAN_RXF1S_F1F_Pos _U_(24) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1F_Msk (_U_(0x1) << MCAN_RXF1S_F1F_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1F(value) (MCAN_RXF1S_F1F_Msk & ((value) << MCAN_RXF1S_F1F_Pos)) +#define MCAN_RXF1S_RF1L_Pos _U_(25) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Position */ +#define MCAN_RXF1S_RF1L_Msk (_U_(0x1) << MCAN_RXF1S_RF1L_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Mask */ +#define MCAN_RXF1S_RF1L(value) (MCAN_RXF1S_RF1L_Msk & ((value) << MCAN_RXF1S_RF1L_Pos)) +#define MCAN_RXF1S_DMS_Pos _U_(30) /**< (MCAN_RXF1S) Debug Message Status Position */ +#define MCAN_RXF1S_DMS_Msk (_U_(0x3) << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug Message Status Mask */ +#define MCAN_RXF1S_DMS(value) (MCAN_RXF1S_DMS_Msk & ((value) << MCAN_RXF1S_DMS_Pos)) +#define MCAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A_Val _U_(0x1) /**< (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB_Val _U_(0x2) /**< (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC_Val _U_(0x3) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +#define MCAN_RXF1S_DMS_IDLE (MCAN_RXF1S_DMS_IDLE_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. Position */ +#define MCAN_RXF1S_DMS_MSG_A (MCAN_RXF1S_DMS_MSG_A_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug message A received. Position */ +#define MCAN_RXF1S_DMS_MSG_AB (MCAN_RXF1S_DMS_MSG_AB_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B received. Position */ +#define MCAN_RXF1S_DMS_MSG_ABC (MCAN_RXF1S_DMS_MSG_ABC_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. Position */ +#define MCAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (MCAN_RXF1S) Register Mask */ + + +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) (R/W 32) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos _U_(0) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Position */ +#define MCAN_RXF1A_F1AI_Msk (_U_(0x3F) << MCAN_RXF1A_F1AI_Pos) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Mask */ +#define MCAN_RXF1A_F1AI(value) (MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)) +#define MCAN_RXF1A_Msk _U_(0x0000003F) /**< (MCAN_RXF1A) Register Mask */ + + +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) (R/W 32) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos _U_(0) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Position */ +#define MCAN_RXESC_F0DS_Msk (_U_(0x7) << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Mask */ +#define MCAN_RXESC_F0DS(value) (MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)) +#define MCAN_RXESC_F0DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F0DS_8_BYTE (MCAN_RXESC_F0DS_8_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F0DS_12_BYTE (MCAN_RXESC_F0DS_12_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F0DS_16_BYTE (MCAN_RXESC_F0DS_16_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F0DS_20_BYTE (MCAN_RXESC_F0DS_20_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F0DS_24_BYTE (MCAN_RXESC_F0DS_24_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F0DS_32_BYTE (MCAN_RXESC_F0DS_32_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F0DS_48_BYTE (MCAN_RXESC_F0DS_48_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F0DS_64_BYTE (MCAN_RXESC_F0DS_64_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_F1DS_Pos _U_(4) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Position */ +#define MCAN_RXESC_F1DS_Msk (_U_(0x7) << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Mask */ +#define MCAN_RXESC_F1DS(value) (MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)) +#define MCAN_RXESC_F1DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_8_BYTE (MCAN_RXESC_F1DS_8_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F1DS_12_BYTE (MCAN_RXESC_F1DS_12_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F1DS_16_BYTE (MCAN_RXESC_F1DS_16_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F1DS_20_BYTE (MCAN_RXESC_F1DS_20_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F1DS_24_BYTE (MCAN_RXESC_F1DS_24_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F1DS_32_BYTE (MCAN_RXESC_F1DS_32_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F1DS_48_BYTE (MCAN_RXESC_F1DS_48_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F1DS_64_BYTE (MCAN_RXESC_F1DS_64_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_RBDS_Pos _U_(8) /**< (MCAN_RXESC) Receive Buffer Data Field Size Position */ +#define MCAN_RXESC_RBDS_Msk (_U_(0x7) << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) Receive Buffer Data Field Size Mask */ +#define MCAN_RXESC_RBDS(value) (MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)) +#define MCAN_RXESC_RBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_8_BYTE (MCAN_RXESC_RBDS_8_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_RBDS_12_BYTE (MCAN_RXESC_RBDS_12_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_RBDS_16_BYTE (MCAN_RXESC_RBDS_16_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_RBDS_20_BYTE (MCAN_RXESC_RBDS_20_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_RBDS_24_BYTE (MCAN_RXESC_RBDS_24_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_RBDS_32_BYTE (MCAN_RXESC_RBDS_32_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_RBDS_48_BYTE (MCAN_RXESC_RBDS_48_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_RBDS_64_BYTE (MCAN_RXESC_RBDS_64_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_Msk _U_(0x00000777) /**< (MCAN_RXESC) Register Mask */ + + +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) (R/W 32) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos _U_(2) /**< (MCAN_TXBC) Tx Buffers Start Address Position */ +#define MCAN_TXBC_TBSA_Msk (_U_(0x3FFF) << MCAN_TXBC_TBSA_Pos) /**< (MCAN_TXBC) Tx Buffers Start Address Mask */ +#define MCAN_TXBC_TBSA(value) (MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)) +#define MCAN_TXBC_NDTB_Pos _U_(16) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define MCAN_TXBC_NDTB_Msk (_U_(0x3F) << MCAN_TXBC_NDTB_Pos) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define MCAN_TXBC_NDTB(value) (MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)) +#define MCAN_TXBC_TFQS_Pos _U_(24) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Position */ +#define MCAN_TXBC_TFQS_Msk (_U_(0x3F) << MCAN_TXBC_TFQS_Pos) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define MCAN_TXBC_TFQS(value) (MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)) +#define MCAN_TXBC_TFQM_Pos _U_(30) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Position */ +#define MCAN_TXBC_TFQM_Msk (_U_(0x1) << MCAN_TXBC_TFQM_Pos) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define MCAN_TXBC_TFQM(value) (MCAN_TXBC_TFQM_Msk & ((value) << MCAN_TXBC_TFQM_Pos)) +#define MCAN_TXBC_Msk _U_(0x7F3FFFFC) /**< (MCAN_TXBC) Register Mask */ + + +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) ( R/ 32) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos _U_(0) /**< (MCAN_TXFQS) Tx FIFO Free Level Position */ +#define MCAN_TXFQS_TFFL_Msk (_U_(0x3F) << MCAN_TXFQS_TFFL_Pos) /**< (MCAN_TXFQS) Tx FIFO Free Level Mask */ +#define MCAN_TXFQS_TFFL(value) (MCAN_TXFQS_TFFL_Msk & ((value) << MCAN_TXFQS_TFFL_Pos)) +#define MCAN_TXFQS_TFGI_Pos _U_(8) /**< (MCAN_TXFQS) Tx FIFO Get Index Position */ +#define MCAN_TXFQS_TFGI_Msk (_U_(0x1F) << MCAN_TXFQS_TFGI_Pos) /**< (MCAN_TXFQS) Tx FIFO Get Index Mask */ +#define MCAN_TXFQS_TFGI(value) (MCAN_TXFQS_TFGI_Msk & ((value) << MCAN_TXFQS_TFGI_Pos)) +#define MCAN_TXFQS_TFQPI_Pos _U_(16) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define MCAN_TXFQS_TFQPI_Msk (_U_(0x1F) << MCAN_TXFQS_TFQPI_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define MCAN_TXFQS_TFQPI(value) (MCAN_TXFQS_TFQPI_Msk & ((value) << MCAN_TXFQS_TFQPI_Pos)) +#define MCAN_TXFQS_TFQF_Pos _U_(21) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Position */ +#define MCAN_TXFQS_TFQF_Msk (_U_(0x1) << MCAN_TXFQS_TFQF_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define MCAN_TXFQS_TFQF(value) (MCAN_TXFQS_TFQF_Msk & ((value) << MCAN_TXFQS_TFQF_Pos)) +#define MCAN_TXFQS_Msk _U_(0x003F1F3F) /**< (MCAN_TXFQS) Register Mask */ + + +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) (R/W 32) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos _U_(0) /**< (MCAN_TXESC) Tx Buffer Data Field Size Position */ +#define MCAN_TXESC_TBDS_Msk (_U_(0x7) << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) Tx Buffer Data Field Size Mask */ +#define MCAN_TXESC_TBDS(value) (MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)) +#define MCAN_TXESC_TBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_TXESC) 4- byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_TXESC) 64-byte data field */ +#define MCAN_TXESC_TBDS_8_BYTE (MCAN_TXESC_TBDS_8_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 8-byte data field Position */ +#define MCAN_TXESC_TBDS_12_BYTE (MCAN_TXESC_TBDS_12_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 12-byte data field Position */ +#define MCAN_TXESC_TBDS_16_BYTE (MCAN_TXESC_TBDS_16_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 16-byte data field Position */ +#define MCAN_TXESC_TBDS_20_BYTE (MCAN_TXESC_TBDS_20_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 20-byte data field Position */ +#define MCAN_TXESC_TBDS_24_BYTE (MCAN_TXESC_TBDS_24_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 24-byte data field Position */ +#define MCAN_TXESC_TBDS_32_BYTE (MCAN_TXESC_TBDS_32_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 32-byte data field Position */ +#define MCAN_TXESC_TBDS_48_BYTE (MCAN_TXESC_TBDS_48_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 4- byte data field Position */ +#define MCAN_TXESC_TBDS_64_BYTE (MCAN_TXESC_TBDS_64_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 64-byte data field Position */ +#define MCAN_TXESC_Msk _U_(0x00000007) /**< (MCAN_TXESC) Register Mask */ + + +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) ( R/ 32) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0_Pos _U_(0) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Position */ +#define MCAN_TXBRP_TRP0_Msk (_U_(0x1) << MCAN_TXBRP_TRP0_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Mask */ +#define MCAN_TXBRP_TRP0(value) (MCAN_TXBRP_TRP0_Msk & ((value) << MCAN_TXBRP_TRP0_Pos)) +#define MCAN_TXBRP_TRP1_Pos _U_(1) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Position */ +#define MCAN_TXBRP_TRP1_Msk (_U_(0x1) << MCAN_TXBRP_TRP1_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Mask */ +#define MCAN_TXBRP_TRP1(value) (MCAN_TXBRP_TRP1_Msk & ((value) << MCAN_TXBRP_TRP1_Pos)) +#define MCAN_TXBRP_TRP2_Pos _U_(2) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Position */ +#define MCAN_TXBRP_TRP2_Msk (_U_(0x1) << MCAN_TXBRP_TRP2_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Mask */ +#define MCAN_TXBRP_TRP2(value) (MCAN_TXBRP_TRP2_Msk & ((value) << MCAN_TXBRP_TRP2_Pos)) +#define MCAN_TXBRP_TRP3_Pos _U_(3) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Position */ +#define MCAN_TXBRP_TRP3_Msk (_U_(0x1) << MCAN_TXBRP_TRP3_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Mask */ +#define MCAN_TXBRP_TRP3(value) (MCAN_TXBRP_TRP3_Msk & ((value) << MCAN_TXBRP_TRP3_Pos)) +#define MCAN_TXBRP_TRP4_Pos _U_(4) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Position */ +#define MCAN_TXBRP_TRP4_Msk (_U_(0x1) << MCAN_TXBRP_TRP4_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Mask */ +#define MCAN_TXBRP_TRP4(value) (MCAN_TXBRP_TRP4_Msk & ((value) << MCAN_TXBRP_TRP4_Pos)) +#define MCAN_TXBRP_TRP5_Pos _U_(5) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Position */ +#define MCAN_TXBRP_TRP5_Msk (_U_(0x1) << MCAN_TXBRP_TRP5_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Mask */ +#define MCAN_TXBRP_TRP5(value) (MCAN_TXBRP_TRP5_Msk & ((value) << MCAN_TXBRP_TRP5_Pos)) +#define MCAN_TXBRP_TRP6_Pos _U_(6) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Position */ +#define MCAN_TXBRP_TRP6_Msk (_U_(0x1) << MCAN_TXBRP_TRP6_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Mask */ +#define MCAN_TXBRP_TRP6(value) (MCAN_TXBRP_TRP6_Msk & ((value) << MCAN_TXBRP_TRP6_Pos)) +#define MCAN_TXBRP_TRP7_Pos _U_(7) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Position */ +#define MCAN_TXBRP_TRP7_Msk (_U_(0x1) << MCAN_TXBRP_TRP7_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Mask */ +#define MCAN_TXBRP_TRP7(value) (MCAN_TXBRP_TRP7_Msk & ((value) << MCAN_TXBRP_TRP7_Pos)) +#define MCAN_TXBRP_TRP8_Pos _U_(8) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Position */ +#define MCAN_TXBRP_TRP8_Msk (_U_(0x1) << MCAN_TXBRP_TRP8_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Mask */ +#define MCAN_TXBRP_TRP8(value) (MCAN_TXBRP_TRP8_Msk & ((value) << MCAN_TXBRP_TRP8_Pos)) +#define MCAN_TXBRP_TRP9_Pos _U_(9) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Position */ +#define MCAN_TXBRP_TRP9_Msk (_U_(0x1) << MCAN_TXBRP_TRP9_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Mask */ +#define MCAN_TXBRP_TRP9(value) (MCAN_TXBRP_TRP9_Msk & ((value) << MCAN_TXBRP_TRP9_Pos)) +#define MCAN_TXBRP_TRP10_Pos _U_(10) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Position */ +#define MCAN_TXBRP_TRP10_Msk (_U_(0x1) << MCAN_TXBRP_TRP10_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Mask */ +#define MCAN_TXBRP_TRP10(value) (MCAN_TXBRP_TRP10_Msk & ((value) << MCAN_TXBRP_TRP10_Pos)) +#define MCAN_TXBRP_TRP11_Pos _U_(11) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Position */ +#define MCAN_TXBRP_TRP11_Msk (_U_(0x1) << MCAN_TXBRP_TRP11_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Mask */ +#define MCAN_TXBRP_TRP11(value) (MCAN_TXBRP_TRP11_Msk & ((value) << MCAN_TXBRP_TRP11_Pos)) +#define MCAN_TXBRP_TRP12_Pos _U_(12) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Position */ +#define MCAN_TXBRP_TRP12_Msk (_U_(0x1) << MCAN_TXBRP_TRP12_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Mask */ +#define MCAN_TXBRP_TRP12(value) (MCAN_TXBRP_TRP12_Msk & ((value) << MCAN_TXBRP_TRP12_Pos)) +#define MCAN_TXBRP_TRP13_Pos _U_(13) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Position */ +#define MCAN_TXBRP_TRP13_Msk (_U_(0x1) << MCAN_TXBRP_TRP13_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Mask */ +#define MCAN_TXBRP_TRP13(value) (MCAN_TXBRP_TRP13_Msk & ((value) << MCAN_TXBRP_TRP13_Pos)) +#define MCAN_TXBRP_TRP14_Pos _U_(14) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Position */ +#define MCAN_TXBRP_TRP14_Msk (_U_(0x1) << MCAN_TXBRP_TRP14_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Mask */ +#define MCAN_TXBRP_TRP14(value) (MCAN_TXBRP_TRP14_Msk & ((value) << MCAN_TXBRP_TRP14_Pos)) +#define MCAN_TXBRP_TRP15_Pos _U_(15) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Position */ +#define MCAN_TXBRP_TRP15_Msk (_U_(0x1) << MCAN_TXBRP_TRP15_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Mask */ +#define MCAN_TXBRP_TRP15(value) (MCAN_TXBRP_TRP15_Msk & ((value) << MCAN_TXBRP_TRP15_Pos)) +#define MCAN_TXBRP_TRP16_Pos _U_(16) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Position */ +#define MCAN_TXBRP_TRP16_Msk (_U_(0x1) << MCAN_TXBRP_TRP16_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Mask */ +#define MCAN_TXBRP_TRP16(value) (MCAN_TXBRP_TRP16_Msk & ((value) << MCAN_TXBRP_TRP16_Pos)) +#define MCAN_TXBRP_TRP17_Pos _U_(17) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Position */ +#define MCAN_TXBRP_TRP17_Msk (_U_(0x1) << MCAN_TXBRP_TRP17_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Mask */ +#define MCAN_TXBRP_TRP17(value) (MCAN_TXBRP_TRP17_Msk & ((value) << MCAN_TXBRP_TRP17_Pos)) +#define MCAN_TXBRP_TRP18_Pos _U_(18) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Position */ +#define MCAN_TXBRP_TRP18_Msk (_U_(0x1) << MCAN_TXBRP_TRP18_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Mask */ +#define MCAN_TXBRP_TRP18(value) (MCAN_TXBRP_TRP18_Msk & ((value) << MCAN_TXBRP_TRP18_Pos)) +#define MCAN_TXBRP_TRP19_Pos _U_(19) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Position */ +#define MCAN_TXBRP_TRP19_Msk (_U_(0x1) << MCAN_TXBRP_TRP19_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Mask */ +#define MCAN_TXBRP_TRP19(value) (MCAN_TXBRP_TRP19_Msk & ((value) << MCAN_TXBRP_TRP19_Pos)) +#define MCAN_TXBRP_TRP20_Pos _U_(20) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Position */ +#define MCAN_TXBRP_TRP20_Msk (_U_(0x1) << MCAN_TXBRP_TRP20_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Mask */ +#define MCAN_TXBRP_TRP20(value) (MCAN_TXBRP_TRP20_Msk & ((value) << MCAN_TXBRP_TRP20_Pos)) +#define MCAN_TXBRP_TRP21_Pos _U_(21) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Position */ +#define MCAN_TXBRP_TRP21_Msk (_U_(0x1) << MCAN_TXBRP_TRP21_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Mask */ +#define MCAN_TXBRP_TRP21(value) (MCAN_TXBRP_TRP21_Msk & ((value) << MCAN_TXBRP_TRP21_Pos)) +#define MCAN_TXBRP_TRP22_Pos _U_(22) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Position */ +#define MCAN_TXBRP_TRP22_Msk (_U_(0x1) << MCAN_TXBRP_TRP22_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Mask */ +#define MCAN_TXBRP_TRP22(value) (MCAN_TXBRP_TRP22_Msk & ((value) << MCAN_TXBRP_TRP22_Pos)) +#define MCAN_TXBRP_TRP23_Pos _U_(23) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Position */ +#define MCAN_TXBRP_TRP23_Msk (_U_(0x1) << MCAN_TXBRP_TRP23_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Mask */ +#define MCAN_TXBRP_TRP23(value) (MCAN_TXBRP_TRP23_Msk & ((value) << MCAN_TXBRP_TRP23_Pos)) +#define MCAN_TXBRP_TRP24_Pos _U_(24) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Position */ +#define MCAN_TXBRP_TRP24_Msk (_U_(0x1) << MCAN_TXBRP_TRP24_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Mask */ +#define MCAN_TXBRP_TRP24(value) (MCAN_TXBRP_TRP24_Msk & ((value) << MCAN_TXBRP_TRP24_Pos)) +#define MCAN_TXBRP_TRP25_Pos _U_(25) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Position */ +#define MCAN_TXBRP_TRP25_Msk (_U_(0x1) << MCAN_TXBRP_TRP25_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Mask */ +#define MCAN_TXBRP_TRP25(value) (MCAN_TXBRP_TRP25_Msk & ((value) << MCAN_TXBRP_TRP25_Pos)) +#define MCAN_TXBRP_TRP26_Pos _U_(26) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Position */ +#define MCAN_TXBRP_TRP26_Msk (_U_(0x1) << MCAN_TXBRP_TRP26_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Mask */ +#define MCAN_TXBRP_TRP26(value) (MCAN_TXBRP_TRP26_Msk & ((value) << MCAN_TXBRP_TRP26_Pos)) +#define MCAN_TXBRP_TRP27_Pos _U_(27) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Position */ +#define MCAN_TXBRP_TRP27_Msk (_U_(0x1) << MCAN_TXBRP_TRP27_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Mask */ +#define MCAN_TXBRP_TRP27(value) (MCAN_TXBRP_TRP27_Msk & ((value) << MCAN_TXBRP_TRP27_Pos)) +#define MCAN_TXBRP_TRP28_Pos _U_(28) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Position */ +#define MCAN_TXBRP_TRP28_Msk (_U_(0x1) << MCAN_TXBRP_TRP28_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Mask */ +#define MCAN_TXBRP_TRP28(value) (MCAN_TXBRP_TRP28_Msk & ((value) << MCAN_TXBRP_TRP28_Pos)) +#define MCAN_TXBRP_TRP29_Pos _U_(29) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Position */ +#define MCAN_TXBRP_TRP29_Msk (_U_(0x1) << MCAN_TXBRP_TRP29_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Mask */ +#define MCAN_TXBRP_TRP29(value) (MCAN_TXBRP_TRP29_Msk & ((value) << MCAN_TXBRP_TRP29_Pos)) +#define MCAN_TXBRP_TRP30_Pos _U_(30) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Position */ +#define MCAN_TXBRP_TRP30_Msk (_U_(0x1) << MCAN_TXBRP_TRP30_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Mask */ +#define MCAN_TXBRP_TRP30(value) (MCAN_TXBRP_TRP30_Msk & ((value) << MCAN_TXBRP_TRP30_Pos)) +#define MCAN_TXBRP_TRP31_Pos _U_(31) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Position */ +#define MCAN_TXBRP_TRP31_Msk (_U_(0x1) << MCAN_TXBRP_TRP31_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Mask */ +#define MCAN_TXBRP_TRP31(value) (MCAN_TXBRP_TRP31_Msk & ((value) << MCAN_TXBRP_TRP31_Pos)) +#define MCAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBRP) Register Mask */ + +#define MCAN_TXBRP_TRP_Pos _U_(0) /**< (MCAN_TXBRP Position) Transmission Request Pending for Buffer 3x */ +#define MCAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << MCAN_TXBRP_TRP_Pos) /**< (MCAN_TXBRP Mask) TRP */ +#define MCAN_TXBRP_TRP(value) (MCAN_TXBRP_TRP_Msk & ((value) << MCAN_TXBRP_TRP_Pos)) + +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) (R/W 32) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0_Pos _U_(0) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Position */ +#define MCAN_TXBAR_AR0_Msk (_U_(0x1) << MCAN_TXBAR_AR0_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBAR_AR0(value) (MCAN_TXBAR_AR0_Msk & ((value) << MCAN_TXBAR_AR0_Pos)) +#define MCAN_TXBAR_AR1_Pos _U_(1) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Position */ +#define MCAN_TXBAR_AR1_Msk (_U_(0x1) << MCAN_TXBAR_AR1_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBAR_AR1(value) (MCAN_TXBAR_AR1_Msk & ((value) << MCAN_TXBAR_AR1_Pos)) +#define MCAN_TXBAR_AR2_Pos _U_(2) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Position */ +#define MCAN_TXBAR_AR2_Msk (_U_(0x1) << MCAN_TXBAR_AR2_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBAR_AR2(value) (MCAN_TXBAR_AR2_Msk & ((value) << MCAN_TXBAR_AR2_Pos)) +#define MCAN_TXBAR_AR3_Pos _U_(3) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Position */ +#define MCAN_TXBAR_AR3_Msk (_U_(0x1) << MCAN_TXBAR_AR3_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBAR_AR3(value) (MCAN_TXBAR_AR3_Msk & ((value) << MCAN_TXBAR_AR3_Pos)) +#define MCAN_TXBAR_AR4_Pos _U_(4) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Position */ +#define MCAN_TXBAR_AR4_Msk (_U_(0x1) << MCAN_TXBAR_AR4_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBAR_AR4(value) (MCAN_TXBAR_AR4_Msk & ((value) << MCAN_TXBAR_AR4_Pos)) +#define MCAN_TXBAR_AR5_Pos _U_(5) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Position */ +#define MCAN_TXBAR_AR5_Msk (_U_(0x1) << MCAN_TXBAR_AR5_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBAR_AR5(value) (MCAN_TXBAR_AR5_Msk & ((value) << MCAN_TXBAR_AR5_Pos)) +#define MCAN_TXBAR_AR6_Pos _U_(6) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Position */ +#define MCAN_TXBAR_AR6_Msk (_U_(0x1) << MCAN_TXBAR_AR6_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBAR_AR6(value) (MCAN_TXBAR_AR6_Msk & ((value) << MCAN_TXBAR_AR6_Pos)) +#define MCAN_TXBAR_AR7_Pos _U_(7) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Position */ +#define MCAN_TXBAR_AR7_Msk (_U_(0x1) << MCAN_TXBAR_AR7_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBAR_AR7(value) (MCAN_TXBAR_AR7_Msk & ((value) << MCAN_TXBAR_AR7_Pos)) +#define MCAN_TXBAR_AR8_Pos _U_(8) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Position */ +#define MCAN_TXBAR_AR8_Msk (_U_(0x1) << MCAN_TXBAR_AR8_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBAR_AR8(value) (MCAN_TXBAR_AR8_Msk & ((value) << MCAN_TXBAR_AR8_Pos)) +#define MCAN_TXBAR_AR9_Pos _U_(9) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Position */ +#define MCAN_TXBAR_AR9_Msk (_U_(0x1) << MCAN_TXBAR_AR9_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBAR_AR9(value) (MCAN_TXBAR_AR9_Msk & ((value) << MCAN_TXBAR_AR9_Pos)) +#define MCAN_TXBAR_AR10_Pos _U_(10) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Position */ +#define MCAN_TXBAR_AR10_Msk (_U_(0x1) << MCAN_TXBAR_AR10_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBAR_AR10(value) (MCAN_TXBAR_AR10_Msk & ((value) << MCAN_TXBAR_AR10_Pos)) +#define MCAN_TXBAR_AR11_Pos _U_(11) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Position */ +#define MCAN_TXBAR_AR11_Msk (_U_(0x1) << MCAN_TXBAR_AR11_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBAR_AR11(value) (MCAN_TXBAR_AR11_Msk & ((value) << MCAN_TXBAR_AR11_Pos)) +#define MCAN_TXBAR_AR12_Pos _U_(12) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Position */ +#define MCAN_TXBAR_AR12_Msk (_U_(0x1) << MCAN_TXBAR_AR12_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBAR_AR12(value) (MCAN_TXBAR_AR12_Msk & ((value) << MCAN_TXBAR_AR12_Pos)) +#define MCAN_TXBAR_AR13_Pos _U_(13) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Position */ +#define MCAN_TXBAR_AR13_Msk (_U_(0x1) << MCAN_TXBAR_AR13_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBAR_AR13(value) (MCAN_TXBAR_AR13_Msk & ((value) << MCAN_TXBAR_AR13_Pos)) +#define MCAN_TXBAR_AR14_Pos _U_(14) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Position */ +#define MCAN_TXBAR_AR14_Msk (_U_(0x1) << MCAN_TXBAR_AR14_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBAR_AR14(value) (MCAN_TXBAR_AR14_Msk & ((value) << MCAN_TXBAR_AR14_Pos)) +#define MCAN_TXBAR_AR15_Pos _U_(15) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Position */ +#define MCAN_TXBAR_AR15_Msk (_U_(0x1) << MCAN_TXBAR_AR15_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBAR_AR15(value) (MCAN_TXBAR_AR15_Msk & ((value) << MCAN_TXBAR_AR15_Pos)) +#define MCAN_TXBAR_AR16_Pos _U_(16) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Position */ +#define MCAN_TXBAR_AR16_Msk (_U_(0x1) << MCAN_TXBAR_AR16_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBAR_AR16(value) (MCAN_TXBAR_AR16_Msk & ((value) << MCAN_TXBAR_AR16_Pos)) +#define MCAN_TXBAR_AR17_Pos _U_(17) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Position */ +#define MCAN_TXBAR_AR17_Msk (_U_(0x1) << MCAN_TXBAR_AR17_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBAR_AR17(value) (MCAN_TXBAR_AR17_Msk & ((value) << MCAN_TXBAR_AR17_Pos)) +#define MCAN_TXBAR_AR18_Pos _U_(18) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Position */ +#define MCAN_TXBAR_AR18_Msk (_U_(0x1) << MCAN_TXBAR_AR18_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBAR_AR18(value) (MCAN_TXBAR_AR18_Msk & ((value) << MCAN_TXBAR_AR18_Pos)) +#define MCAN_TXBAR_AR19_Pos _U_(19) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Position */ +#define MCAN_TXBAR_AR19_Msk (_U_(0x1) << MCAN_TXBAR_AR19_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBAR_AR19(value) (MCAN_TXBAR_AR19_Msk & ((value) << MCAN_TXBAR_AR19_Pos)) +#define MCAN_TXBAR_AR20_Pos _U_(20) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Position */ +#define MCAN_TXBAR_AR20_Msk (_U_(0x1) << MCAN_TXBAR_AR20_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBAR_AR20(value) (MCAN_TXBAR_AR20_Msk & ((value) << MCAN_TXBAR_AR20_Pos)) +#define MCAN_TXBAR_AR21_Pos _U_(21) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Position */ +#define MCAN_TXBAR_AR21_Msk (_U_(0x1) << MCAN_TXBAR_AR21_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBAR_AR21(value) (MCAN_TXBAR_AR21_Msk & ((value) << MCAN_TXBAR_AR21_Pos)) +#define MCAN_TXBAR_AR22_Pos _U_(22) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Position */ +#define MCAN_TXBAR_AR22_Msk (_U_(0x1) << MCAN_TXBAR_AR22_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBAR_AR22(value) (MCAN_TXBAR_AR22_Msk & ((value) << MCAN_TXBAR_AR22_Pos)) +#define MCAN_TXBAR_AR23_Pos _U_(23) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Position */ +#define MCAN_TXBAR_AR23_Msk (_U_(0x1) << MCAN_TXBAR_AR23_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBAR_AR23(value) (MCAN_TXBAR_AR23_Msk & ((value) << MCAN_TXBAR_AR23_Pos)) +#define MCAN_TXBAR_AR24_Pos _U_(24) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Position */ +#define MCAN_TXBAR_AR24_Msk (_U_(0x1) << MCAN_TXBAR_AR24_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBAR_AR24(value) (MCAN_TXBAR_AR24_Msk & ((value) << MCAN_TXBAR_AR24_Pos)) +#define MCAN_TXBAR_AR25_Pos _U_(25) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Position */ +#define MCAN_TXBAR_AR25_Msk (_U_(0x1) << MCAN_TXBAR_AR25_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBAR_AR25(value) (MCAN_TXBAR_AR25_Msk & ((value) << MCAN_TXBAR_AR25_Pos)) +#define MCAN_TXBAR_AR26_Pos _U_(26) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Position */ +#define MCAN_TXBAR_AR26_Msk (_U_(0x1) << MCAN_TXBAR_AR26_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBAR_AR26(value) (MCAN_TXBAR_AR26_Msk & ((value) << MCAN_TXBAR_AR26_Pos)) +#define MCAN_TXBAR_AR27_Pos _U_(27) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Position */ +#define MCAN_TXBAR_AR27_Msk (_U_(0x1) << MCAN_TXBAR_AR27_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBAR_AR27(value) (MCAN_TXBAR_AR27_Msk & ((value) << MCAN_TXBAR_AR27_Pos)) +#define MCAN_TXBAR_AR28_Pos _U_(28) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Position */ +#define MCAN_TXBAR_AR28_Msk (_U_(0x1) << MCAN_TXBAR_AR28_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBAR_AR28(value) (MCAN_TXBAR_AR28_Msk & ((value) << MCAN_TXBAR_AR28_Pos)) +#define MCAN_TXBAR_AR29_Pos _U_(29) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Position */ +#define MCAN_TXBAR_AR29_Msk (_U_(0x1) << MCAN_TXBAR_AR29_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBAR_AR29(value) (MCAN_TXBAR_AR29_Msk & ((value) << MCAN_TXBAR_AR29_Pos)) +#define MCAN_TXBAR_AR30_Pos _U_(30) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Position */ +#define MCAN_TXBAR_AR30_Msk (_U_(0x1) << MCAN_TXBAR_AR30_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBAR_AR30(value) (MCAN_TXBAR_AR30_Msk & ((value) << MCAN_TXBAR_AR30_Pos)) +#define MCAN_TXBAR_AR31_Pos _U_(31) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Position */ +#define MCAN_TXBAR_AR31_Msk (_U_(0x1) << MCAN_TXBAR_AR31_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBAR_AR31(value) (MCAN_TXBAR_AR31_Msk & ((value) << MCAN_TXBAR_AR31_Pos)) +#define MCAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBAR) Register Mask */ + +#define MCAN_TXBAR_AR_Pos _U_(0) /**< (MCAN_TXBAR Position) Add Request for Transmit Buffer 3x */ +#define MCAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBAR_AR_Pos) /**< (MCAN_TXBAR Mask) AR */ +#define MCAN_TXBAR_AR(value) (MCAN_TXBAR_AR_Msk & ((value) << MCAN_TXBAR_AR_Pos)) + +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) (R/W 32) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0_Pos _U_(0) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Position */ +#define MCAN_TXBCR_CR0_Msk (_U_(0x1) << MCAN_TXBCR_CR0_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBCR_CR0(value) (MCAN_TXBCR_CR0_Msk & ((value) << MCAN_TXBCR_CR0_Pos)) +#define MCAN_TXBCR_CR1_Pos _U_(1) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Position */ +#define MCAN_TXBCR_CR1_Msk (_U_(0x1) << MCAN_TXBCR_CR1_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBCR_CR1(value) (MCAN_TXBCR_CR1_Msk & ((value) << MCAN_TXBCR_CR1_Pos)) +#define MCAN_TXBCR_CR2_Pos _U_(2) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Position */ +#define MCAN_TXBCR_CR2_Msk (_U_(0x1) << MCAN_TXBCR_CR2_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBCR_CR2(value) (MCAN_TXBCR_CR2_Msk & ((value) << MCAN_TXBCR_CR2_Pos)) +#define MCAN_TXBCR_CR3_Pos _U_(3) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Position */ +#define MCAN_TXBCR_CR3_Msk (_U_(0x1) << MCAN_TXBCR_CR3_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBCR_CR3(value) (MCAN_TXBCR_CR3_Msk & ((value) << MCAN_TXBCR_CR3_Pos)) +#define MCAN_TXBCR_CR4_Pos _U_(4) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Position */ +#define MCAN_TXBCR_CR4_Msk (_U_(0x1) << MCAN_TXBCR_CR4_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBCR_CR4(value) (MCAN_TXBCR_CR4_Msk & ((value) << MCAN_TXBCR_CR4_Pos)) +#define MCAN_TXBCR_CR5_Pos _U_(5) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Position */ +#define MCAN_TXBCR_CR5_Msk (_U_(0x1) << MCAN_TXBCR_CR5_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBCR_CR5(value) (MCAN_TXBCR_CR5_Msk & ((value) << MCAN_TXBCR_CR5_Pos)) +#define MCAN_TXBCR_CR6_Pos _U_(6) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Position */ +#define MCAN_TXBCR_CR6_Msk (_U_(0x1) << MCAN_TXBCR_CR6_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBCR_CR6(value) (MCAN_TXBCR_CR6_Msk & ((value) << MCAN_TXBCR_CR6_Pos)) +#define MCAN_TXBCR_CR7_Pos _U_(7) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Position */ +#define MCAN_TXBCR_CR7_Msk (_U_(0x1) << MCAN_TXBCR_CR7_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBCR_CR7(value) (MCAN_TXBCR_CR7_Msk & ((value) << MCAN_TXBCR_CR7_Pos)) +#define MCAN_TXBCR_CR8_Pos _U_(8) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Position */ +#define MCAN_TXBCR_CR8_Msk (_U_(0x1) << MCAN_TXBCR_CR8_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBCR_CR8(value) (MCAN_TXBCR_CR8_Msk & ((value) << MCAN_TXBCR_CR8_Pos)) +#define MCAN_TXBCR_CR9_Pos _U_(9) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Position */ +#define MCAN_TXBCR_CR9_Msk (_U_(0x1) << MCAN_TXBCR_CR9_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBCR_CR9(value) (MCAN_TXBCR_CR9_Msk & ((value) << MCAN_TXBCR_CR9_Pos)) +#define MCAN_TXBCR_CR10_Pos _U_(10) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Position */ +#define MCAN_TXBCR_CR10_Msk (_U_(0x1) << MCAN_TXBCR_CR10_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBCR_CR10(value) (MCAN_TXBCR_CR10_Msk & ((value) << MCAN_TXBCR_CR10_Pos)) +#define MCAN_TXBCR_CR11_Pos _U_(11) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Position */ +#define MCAN_TXBCR_CR11_Msk (_U_(0x1) << MCAN_TXBCR_CR11_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBCR_CR11(value) (MCAN_TXBCR_CR11_Msk & ((value) << MCAN_TXBCR_CR11_Pos)) +#define MCAN_TXBCR_CR12_Pos _U_(12) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Position */ +#define MCAN_TXBCR_CR12_Msk (_U_(0x1) << MCAN_TXBCR_CR12_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBCR_CR12(value) (MCAN_TXBCR_CR12_Msk & ((value) << MCAN_TXBCR_CR12_Pos)) +#define MCAN_TXBCR_CR13_Pos _U_(13) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Position */ +#define MCAN_TXBCR_CR13_Msk (_U_(0x1) << MCAN_TXBCR_CR13_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBCR_CR13(value) (MCAN_TXBCR_CR13_Msk & ((value) << MCAN_TXBCR_CR13_Pos)) +#define MCAN_TXBCR_CR14_Pos _U_(14) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Position */ +#define MCAN_TXBCR_CR14_Msk (_U_(0x1) << MCAN_TXBCR_CR14_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBCR_CR14(value) (MCAN_TXBCR_CR14_Msk & ((value) << MCAN_TXBCR_CR14_Pos)) +#define MCAN_TXBCR_CR15_Pos _U_(15) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Position */ +#define MCAN_TXBCR_CR15_Msk (_U_(0x1) << MCAN_TXBCR_CR15_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBCR_CR15(value) (MCAN_TXBCR_CR15_Msk & ((value) << MCAN_TXBCR_CR15_Pos)) +#define MCAN_TXBCR_CR16_Pos _U_(16) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Position */ +#define MCAN_TXBCR_CR16_Msk (_U_(0x1) << MCAN_TXBCR_CR16_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBCR_CR16(value) (MCAN_TXBCR_CR16_Msk & ((value) << MCAN_TXBCR_CR16_Pos)) +#define MCAN_TXBCR_CR17_Pos _U_(17) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Position */ +#define MCAN_TXBCR_CR17_Msk (_U_(0x1) << MCAN_TXBCR_CR17_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBCR_CR17(value) (MCAN_TXBCR_CR17_Msk & ((value) << MCAN_TXBCR_CR17_Pos)) +#define MCAN_TXBCR_CR18_Pos _U_(18) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Position */ +#define MCAN_TXBCR_CR18_Msk (_U_(0x1) << MCAN_TXBCR_CR18_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBCR_CR18(value) (MCAN_TXBCR_CR18_Msk & ((value) << MCAN_TXBCR_CR18_Pos)) +#define MCAN_TXBCR_CR19_Pos _U_(19) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Position */ +#define MCAN_TXBCR_CR19_Msk (_U_(0x1) << MCAN_TXBCR_CR19_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBCR_CR19(value) (MCAN_TXBCR_CR19_Msk & ((value) << MCAN_TXBCR_CR19_Pos)) +#define MCAN_TXBCR_CR20_Pos _U_(20) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Position */ +#define MCAN_TXBCR_CR20_Msk (_U_(0x1) << MCAN_TXBCR_CR20_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBCR_CR20(value) (MCAN_TXBCR_CR20_Msk & ((value) << MCAN_TXBCR_CR20_Pos)) +#define MCAN_TXBCR_CR21_Pos _U_(21) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Position */ +#define MCAN_TXBCR_CR21_Msk (_U_(0x1) << MCAN_TXBCR_CR21_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBCR_CR21(value) (MCAN_TXBCR_CR21_Msk & ((value) << MCAN_TXBCR_CR21_Pos)) +#define MCAN_TXBCR_CR22_Pos _U_(22) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Position */ +#define MCAN_TXBCR_CR22_Msk (_U_(0x1) << MCAN_TXBCR_CR22_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBCR_CR22(value) (MCAN_TXBCR_CR22_Msk & ((value) << MCAN_TXBCR_CR22_Pos)) +#define MCAN_TXBCR_CR23_Pos _U_(23) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Position */ +#define MCAN_TXBCR_CR23_Msk (_U_(0x1) << MCAN_TXBCR_CR23_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBCR_CR23(value) (MCAN_TXBCR_CR23_Msk & ((value) << MCAN_TXBCR_CR23_Pos)) +#define MCAN_TXBCR_CR24_Pos _U_(24) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Position */ +#define MCAN_TXBCR_CR24_Msk (_U_(0x1) << MCAN_TXBCR_CR24_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBCR_CR24(value) (MCAN_TXBCR_CR24_Msk & ((value) << MCAN_TXBCR_CR24_Pos)) +#define MCAN_TXBCR_CR25_Pos _U_(25) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Position */ +#define MCAN_TXBCR_CR25_Msk (_U_(0x1) << MCAN_TXBCR_CR25_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBCR_CR25(value) (MCAN_TXBCR_CR25_Msk & ((value) << MCAN_TXBCR_CR25_Pos)) +#define MCAN_TXBCR_CR26_Pos _U_(26) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Position */ +#define MCAN_TXBCR_CR26_Msk (_U_(0x1) << MCAN_TXBCR_CR26_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBCR_CR26(value) (MCAN_TXBCR_CR26_Msk & ((value) << MCAN_TXBCR_CR26_Pos)) +#define MCAN_TXBCR_CR27_Pos _U_(27) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Position */ +#define MCAN_TXBCR_CR27_Msk (_U_(0x1) << MCAN_TXBCR_CR27_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBCR_CR27(value) (MCAN_TXBCR_CR27_Msk & ((value) << MCAN_TXBCR_CR27_Pos)) +#define MCAN_TXBCR_CR28_Pos _U_(28) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Position */ +#define MCAN_TXBCR_CR28_Msk (_U_(0x1) << MCAN_TXBCR_CR28_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBCR_CR28(value) (MCAN_TXBCR_CR28_Msk & ((value) << MCAN_TXBCR_CR28_Pos)) +#define MCAN_TXBCR_CR29_Pos _U_(29) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Position */ +#define MCAN_TXBCR_CR29_Msk (_U_(0x1) << MCAN_TXBCR_CR29_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBCR_CR29(value) (MCAN_TXBCR_CR29_Msk & ((value) << MCAN_TXBCR_CR29_Pos)) +#define MCAN_TXBCR_CR30_Pos _U_(30) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Position */ +#define MCAN_TXBCR_CR30_Msk (_U_(0x1) << MCAN_TXBCR_CR30_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBCR_CR30(value) (MCAN_TXBCR_CR30_Msk & ((value) << MCAN_TXBCR_CR30_Pos)) +#define MCAN_TXBCR_CR31_Pos _U_(31) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Position */ +#define MCAN_TXBCR_CR31_Msk (_U_(0x1) << MCAN_TXBCR_CR31_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBCR_CR31(value) (MCAN_TXBCR_CR31_Msk & ((value) << MCAN_TXBCR_CR31_Pos)) +#define MCAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCR) Register Mask */ + +#define MCAN_TXBCR_CR_Pos _U_(0) /**< (MCAN_TXBCR Position) Cancellation Request for Transmit Buffer 3x */ +#define MCAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCR_CR_Pos) /**< (MCAN_TXBCR Mask) CR */ +#define MCAN_TXBCR_CR(value) (MCAN_TXBCR_CR_Msk & ((value) << MCAN_TXBCR_CR_Pos)) + +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) ( R/ 32) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0_Pos _U_(0) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Position */ +#define MCAN_TXBTO_TO0_Msk (_U_(0x1) << MCAN_TXBTO_TO0_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Mask */ +#define MCAN_TXBTO_TO0(value) (MCAN_TXBTO_TO0_Msk & ((value) << MCAN_TXBTO_TO0_Pos)) +#define MCAN_TXBTO_TO1_Pos _U_(1) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Position */ +#define MCAN_TXBTO_TO1_Msk (_U_(0x1) << MCAN_TXBTO_TO1_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Mask */ +#define MCAN_TXBTO_TO1(value) (MCAN_TXBTO_TO1_Msk & ((value) << MCAN_TXBTO_TO1_Pos)) +#define MCAN_TXBTO_TO2_Pos _U_(2) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Position */ +#define MCAN_TXBTO_TO2_Msk (_U_(0x1) << MCAN_TXBTO_TO2_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Mask */ +#define MCAN_TXBTO_TO2(value) (MCAN_TXBTO_TO2_Msk & ((value) << MCAN_TXBTO_TO2_Pos)) +#define MCAN_TXBTO_TO3_Pos _U_(3) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Position */ +#define MCAN_TXBTO_TO3_Msk (_U_(0x1) << MCAN_TXBTO_TO3_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Mask */ +#define MCAN_TXBTO_TO3(value) (MCAN_TXBTO_TO3_Msk & ((value) << MCAN_TXBTO_TO3_Pos)) +#define MCAN_TXBTO_TO4_Pos _U_(4) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Position */ +#define MCAN_TXBTO_TO4_Msk (_U_(0x1) << MCAN_TXBTO_TO4_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Mask */ +#define MCAN_TXBTO_TO4(value) (MCAN_TXBTO_TO4_Msk & ((value) << MCAN_TXBTO_TO4_Pos)) +#define MCAN_TXBTO_TO5_Pos _U_(5) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Position */ +#define MCAN_TXBTO_TO5_Msk (_U_(0x1) << MCAN_TXBTO_TO5_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Mask */ +#define MCAN_TXBTO_TO5(value) (MCAN_TXBTO_TO5_Msk & ((value) << MCAN_TXBTO_TO5_Pos)) +#define MCAN_TXBTO_TO6_Pos _U_(6) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Position */ +#define MCAN_TXBTO_TO6_Msk (_U_(0x1) << MCAN_TXBTO_TO6_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Mask */ +#define MCAN_TXBTO_TO6(value) (MCAN_TXBTO_TO6_Msk & ((value) << MCAN_TXBTO_TO6_Pos)) +#define MCAN_TXBTO_TO7_Pos _U_(7) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Position */ +#define MCAN_TXBTO_TO7_Msk (_U_(0x1) << MCAN_TXBTO_TO7_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Mask */ +#define MCAN_TXBTO_TO7(value) (MCAN_TXBTO_TO7_Msk & ((value) << MCAN_TXBTO_TO7_Pos)) +#define MCAN_TXBTO_TO8_Pos _U_(8) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Position */ +#define MCAN_TXBTO_TO8_Msk (_U_(0x1) << MCAN_TXBTO_TO8_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Mask */ +#define MCAN_TXBTO_TO8(value) (MCAN_TXBTO_TO8_Msk & ((value) << MCAN_TXBTO_TO8_Pos)) +#define MCAN_TXBTO_TO9_Pos _U_(9) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Position */ +#define MCAN_TXBTO_TO9_Msk (_U_(0x1) << MCAN_TXBTO_TO9_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Mask */ +#define MCAN_TXBTO_TO9(value) (MCAN_TXBTO_TO9_Msk & ((value) << MCAN_TXBTO_TO9_Pos)) +#define MCAN_TXBTO_TO10_Pos _U_(10) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Position */ +#define MCAN_TXBTO_TO10_Msk (_U_(0x1) << MCAN_TXBTO_TO10_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Mask */ +#define MCAN_TXBTO_TO10(value) (MCAN_TXBTO_TO10_Msk & ((value) << MCAN_TXBTO_TO10_Pos)) +#define MCAN_TXBTO_TO11_Pos _U_(11) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Position */ +#define MCAN_TXBTO_TO11_Msk (_U_(0x1) << MCAN_TXBTO_TO11_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Mask */ +#define MCAN_TXBTO_TO11(value) (MCAN_TXBTO_TO11_Msk & ((value) << MCAN_TXBTO_TO11_Pos)) +#define MCAN_TXBTO_TO12_Pos _U_(12) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Position */ +#define MCAN_TXBTO_TO12_Msk (_U_(0x1) << MCAN_TXBTO_TO12_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Mask */ +#define MCAN_TXBTO_TO12(value) (MCAN_TXBTO_TO12_Msk & ((value) << MCAN_TXBTO_TO12_Pos)) +#define MCAN_TXBTO_TO13_Pos _U_(13) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Position */ +#define MCAN_TXBTO_TO13_Msk (_U_(0x1) << MCAN_TXBTO_TO13_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Mask */ +#define MCAN_TXBTO_TO13(value) (MCAN_TXBTO_TO13_Msk & ((value) << MCAN_TXBTO_TO13_Pos)) +#define MCAN_TXBTO_TO14_Pos _U_(14) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Position */ +#define MCAN_TXBTO_TO14_Msk (_U_(0x1) << MCAN_TXBTO_TO14_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Mask */ +#define MCAN_TXBTO_TO14(value) (MCAN_TXBTO_TO14_Msk & ((value) << MCAN_TXBTO_TO14_Pos)) +#define MCAN_TXBTO_TO15_Pos _U_(15) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Position */ +#define MCAN_TXBTO_TO15_Msk (_U_(0x1) << MCAN_TXBTO_TO15_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Mask */ +#define MCAN_TXBTO_TO15(value) (MCAN_TXBTO_TO15_Msk & ((value) << MCAN_TXBTO_TO15_Pos)) +#define MCAN_TXBTO_TO16_Pos _U_(16) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Position */ +#define MCAN_TXBTO_TO16_Msk (_U_(0x1) << MCAN_TXBTO_TO16_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Mask */ +#define MCAN_TXBTO_TO16(value) (MCAN_TXBTO_TO16_Msk & ((value) << MCAN_TXBTO_TO16_Pos)) +#define MCAN_TXBTO_TO17_Pos _U_(17) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Position */ +#define MCAN_TXBTO_TO17_Msk (_U_(0x1) << MCAN_TXBTO_TO17_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Mask */ +#define MCAN_TXBTO_TO17(value) (MCAN_TXBTO_TO17_Msk & ((value) << MCAN_TXBTO_TO17_Pos)) +#define MCAN_TXBTO_TO18_Pos _U_(18) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Position */ +#define MCAN_TXBTO_TO18_Msk (_U_(0x1) << MCAN_TXBTO_TO18_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Mask */ +#define MCAN_TXBTO_TO18(value) (MCAN_TXBTO_TO18_Msk & ((value) << MCAN_TXBTO_TO18_Pos)) +#define MCAN_TXBTO_TO19_Pos _U_(19) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Position */ +#define MCAN_TXBTO_TO19_Msk (_U_(0x1) << MCAN_TXBTO_TO19_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Mask */ +#define MCAN_TXBTO_TO19(value) (MCAN_TXBTO_TO19_Msk & ((value) << MCAN_TXBTO_TO19_Pos)) +#define MCAN_TXBTO_TO20_Pos _U_(20) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Position */ +#define MCAN_TXBTO_TO20_Msk (_U_(0x1) << MCAN_TXBTO_TO20_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Mask */ +#define MCAN_TXBTO_TO20(value) (MCAN_TXBTO_TO20_Msk & ((value) << MCAN_TXBTO_TO20_Pos)) +#define MCAN_TXBTO_TO21_Pos _U_(21) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Position */ +#define MCAN_TXBTO_TO21_Msk (_U_(0x1) << MCAN_TXBTO_TO21_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Mask */ +#define MCAN_TXBTO_TO21(value) (MCAN_TXBTO_TO21_Msk & ((value) << MCAN_TXBTO_TO21_Pos)) +#define MCAN_TXBTO_TO22_Pos _U_(22) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Position */ +#define MCAN_TXBTO_TO22_Msk (_U_(0x1) << MCAN_TXBTO_TO22_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Mask */ +#define MCAN_TXBTO_TO22(value) (MCAN_TXBTO_TO22_Msk & ((value) << MCAN_TXBTO_TO22_Pos)) +#define MCAN_TXBTO_TO23_Pos _U_(23) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Position */ +#define MCAN_TXBTO_TO23_Msk (_U_(0x1) << MCAN_TXBTO_TO23_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Mask */ +#define MCAN_TXBTO_TO23(value) (MCAN_TXBTO_TO23_Msk & ((value) << MCAN_TXBTO_TO23_Pos)) +#define MCAN_TXBTO_TO24_Pos _U_(24) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Position */ +#define MCAN_TXBTO_TO24_Msk (_U_(0x1) << MCAN_TXBTO_TO24_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Mask */ +#define MCAN_TXBTO_TO24(value) (MCAN_TXBTO_TO24_Msk & ((value) << MCAN_TXBTO_TO24_Pos)) +#define MCAN_TXBTO_TO25_Pos _U_(25) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Position */ +#define MCAN_TXBTO_TO25_Msk (_U_(0x1) << MCAN_TXBTO_TO25_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Mask */ +#define MCAN_TXBTO_TO25(value) (MCAN_TXBTO_TO25_Msk & ((value) << MCAN_TXBTO_TO25_Pos)) +#define MCAN_TXBTO_TO26_Pos _U_(26) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Position */ +#define MCAN_TXBTO_TO26_Msk (_U_(0x1) << MCAN_TXBTO_TO26_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Mask */ +#define MCAN_TXBTO_TO26(value) (MCAN_TXBTO_TO26_Msk & ((value) << MCAN_TXBTO_TO26_Pos)) +#define MCAN_TXBTO_TO27_Pos _U_(27) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Position */ +#define MCAN_TXBTO_TO27_Msk (_U_(0x1) << MCAN_TXBTO_TO27_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Mask */ +#define MCAN_TXBTO_TO27(value) (MCAN_TXBTO_TO27_Msk & ((value) << MCAN_TXBTO_TO27_Pos)) +#define MCAN_TXBTO_TO28_Pos _U_(28) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Position */ +#define MCAN_TXBTO_TO28_Msk (_U_(0x1) << MCAN_TXBTO_TO28_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Mask */ +#define MCAN_TXBTO_TO28(value) (MCAN_TXBTO_TO28_Msk & ((value) << MCAN_TXBTO_TO28_Pos)) +#define MCAN_TXBTO_TO29_Pos _U_(29) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Position */ +#define MCAN_TXBTO_TO29_Msk (_U_(0x1) << MCAN_TXBTO_TO29_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Mask */ +#define MCAN_TXBTO_TO29(value) (MCAN_TXBTO_TO29_Msk & ((value) << MCAN_TXBTO_TO29_Pos)) +#define MCAN_TXBTO_TO30_Pos _U_(30) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Position */ +#define MCAN_TXBTO_TO30_Msk (_U_(0x1) << MCAN_TXBTO_TO30_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Mask */ +#define MCAN_TXBTO_TO30(value) (MCAN_TXBTO_TO30_Msk & ((value) << MCAN_TXBTO_TO30_Pos)) +#define MCAN_TXBTO_TO31_Pos _U_(31) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Position */ +#define MCAN_TXBTO_TO31_Msk (_U_(0x1) << MCAN_TXBTO_TO31_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Mask */ +#define MCAN_TXBTO_TO31(value) (MCAN_TXBTO_TO31_Msk & ((value) << MCAN_TXBTO_TO31_Pos)) +#define MCAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTO) Register Mask */ + +#define MCAN_TXBTO_TO_Pos _U_(0) /**< (MCAN_TXBTO Position) Transmission Occurred for Buffer 3x */ +#define MCAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTO_TO_Pos) /**< (MCAN_TXBTO Mask) TO */ +#define MCAN_TXBTO_TO(value) (MCAN_TXBTO_TO_Msk & ((value) << MCAN_TXBTO_TO_Pos)) + +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) ( R/ 32) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0_Pos _U_(0) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Position */ +#define MCAN_TXBCF_CF0_Msk (_U_(0x1) << MCAN_TXBCF_CF0_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Mask */ +#define MCAN_TXBCF_CF0(value) (MCAN_TXBCF_CF0_Msk & ((value) << MCAN_TXBCF_CF0_Pos)) +#define MCAN_TXBCF_CF1_Pos _U_(1) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Position */ +#define MCAN_TXBCF_CF1_Msk (_U_(0x1) << MCAN_TXBCF_CF1_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Mask */ +#define MCAN_TXBCF_CF1(value) (MCAN_TXBCF_CF1_Msk & ((value) << MCAN_TXBCF_CF1_Pos)) +#define MCAN_TXBCF_CF2_Pos _U_(2) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Position */ +#define MCAN_TXBCF_CF2_Msk (_U_(0x1) << MCAN_TXBCF_CF2_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Mask */ +#define MCAN_TXBCF_CF2(value) (MCAN_TXBCF_CF2_Msk & ((value) << MCAN_TXBCF_CF2_Pos)) +#define MCAN_TXBCF_CF3_Pos _U_(3) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Position */ +#define MCAN_TXBCF_CF3_Msk (_U_(0x1) << MCAN_TXBCF_CF3_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Mask */ +#define MCAN_TXBCF_CF3(value) (MCAN_TXBCF_CF3_Msk & ((value) << MCAN_TXBCF_CF3_Pos)) +#define MCAN_TXBCF_CF4_Pos _U_(4) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Position */ +#define MCAN_TXBCF_CF4_Msk (_U_(0x1) << MCAN_TXBCF_CF4_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Mask */ +#define MCAN_TXBCF_CF4(value) (MCAN_TXBCF_CF4_Msk & ((value) << MCAN_TXBCF_CF4_Pos)) +#define MCAN_TXBCF_CF5_Pos _U_(5) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Position */ +#define MCAN_TXBCF_CF5_Msk (_U_(0x1) << MCAN_TXBCF_CF5_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Mask */ +#define MCAN_TXBCF_CF5(value) (MCAN_TXBCF_CF5_Msk & ((value) << MCAN_TXBCF_CF5_Pos)) +#define MCAN_TXBCF_CF6_Pos _U_(6) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Position */ +#define MCAN_TXBCF_CF6_Msk (_U_(0x1) << MCAN_TXBCF_CF6_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Mask */ +#define MCAN_TXBCF_CF6(value) (MCAN_TXBCF_CF6_Msk & ((value) << MCAN_TXBCF_CF6_Pos)) +#define MCAN_TXBCF_CF7_Pos _U_(7) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Position */ +#define MCAN_TXBCF_CF7_Msk (_U_(0x1) << MCAN_TXBCF_CF7_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Mask */ +#define MCAN_TXBCF_CF7(value) (MCAN_TXBCF_CF7_Msk & ((value) << MCAN_TXBCF_CF7_Pos)) +#define MCAN_TXBCF_CF8_Pos _U_(8) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Position */ +#define MCAN_TXBCF_CF8_Msk (_U_(0x1) << MCAN_TXBCF_CF8_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Mask */ +#define MCAN_TXBCF_CF8(value) (MCAN_TXBCF_CF8_Msk & ((value) << MCAN_TXBCF_CF8_Pos)) +#define MCAN_TXBCF_CF9_Pos _U_(9) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Position */ +#define MCAN_TXBCF_CF9_Msk (_U_(0x1) << MCAN_TXBCF_CF9_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Mask */ +#define MCAN_TXBCF_CF9(value) (MCAN_TXBCF_CF9_Msk & ((value) << MCAN_TXBCF_CF9_Pos)) +#define MCAN_TXBCF_CF10_Pos _U_(10) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Position */ +#define MCAN_TXBCF_CF10_Msk (_U_(0x1) << MCAN_TXBCF_CF10_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Mask */ +#define MCAN_TXBCF_CF10(value) (MCAN_TXBCF_CF10_Msk & ((value) << MCAN_TXBCF_CF10_Pos)) +#define MCAN_TXBCF_CF11_Pos _U_(11) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Position */ +#define MCAN_TXBCF_CF11_Msk (_U_(0x1) << MCAN_TXBCF_CF11_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Mask */ +#define MCAN_TXBCF_CF11(value) (MCAN_TXBCF_CF11_Msk & ((value) << MCAN_TXBCF_CF11_Pos)) +#define MCAN_TXBCF_CF12_Pos _U_(12) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Position */ +#define MCAN_TXBCF_CF12_Msk (_U_(0x1) << MCAN_TXBCF_CF12_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Mask */ +#define MCAN_TXBCF_CF12(value) (MCAN_TXBCF_CF12_Msk & ((value) << MCAN_TXBCF_CF12_Pos)) +#define MCAN_TXBCF_CF13_Pos _U_(13) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Position */ +#define MCAN_TXBCF_CF13_Msk (_U_(0x1) << MCAN_TXBCF_CF13_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Mask */ +#define MCAN_TXBCF_CF13(value) (MCAN_TXBCF_CF13_Msk & ((value) << MCAN_TXBCF_CF13_Pos)) +#define MCAN_TXBCF_CF14_Pos _U_(14) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Position */ +#define MCAN_TXBCF_CF14_Msk (_U_(0x1) << MCAN_TXBCF_CF14_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Mask */ +#define MCAN_TXBCF_CF14(value) (MCAN_TXBCF_CF14_Msk & ((value) << MCAN_TXBCF_CF14_Pos)) +#define MCAN_TXBCF_CF15_Pos _U_(15) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Position */ +#define MCAN_TXBCF_CF15_Msk (_U_(0x1) << MCAN_TXBCF_CF15_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Mask */ +#define MCAN_TXBCF_CF15(value) (MCAN_TXBCF_CF15_Msk & ((value) << MCAN_TXBCF_CF15_Pos)) +#define MCAN_TXBCF_CF16_Pos _U_(16) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Position */ +#define MCAN_TXBCF_CF16_Msk (_U_(0x1) << MCAN_TXBCF_CF16_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Mask */ +#define MCAN_TXBCF_CF16(value) (MCAN_TXBCF_CF16_Msk & ((value) << MCAN_TXBCF_CF16_Pos)) +#define MCAN_TXBCF_CF17_Pos _U_(17) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Position */ +#define MCAN_TXBCF_CF17_Msk (_U_(0x1) << MCAN_TXBCF_CF17_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Mask */ +#define MCAN_TXBCF_CF17(value) (MCAN_TXBCF_CF17_Msk & ((value) << MCAN_TXBCF_CF17_Pos)) +#define MCAN_TXBCF_CF18_Pos _U_(18) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Position */ +#define MCAN_TXBCF_CF18_Msk (_U_(0x1) << MCAN_TXBCF_CF18_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Mask */ +#define MCAN_TXBCF_CF18(value) (MCAN_TXBCF_CF18_Msk & ((value) << MCAN_TXBCF_CF18_Pos)) +#define MCAN_TXBCF_CF19_Pos _U_(19) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Position */ +#define MCAN_TXBCF_CF19_Msk (_U_(0x1) << MCAN_TXBCF_CF19_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Mask */ +#define MCAN_TXBCF_CF19(value) (MCAN_TXBCF_CF19_Msk & ((value) << MCAN_TXBCF_CF19_Pos)) +#define MCAN_TXBCF_CF20_Pos _U_(20) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Position */ +#define MCAN_TXBCF_CF20_Msk (_U_(0x1) << MCAN_TXBCF_CF20_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Mask */ +#define MCAN_TXBCF_CF20(value) (MCAN_TXBCF_CF20_Msk & ((value) << MCAN_TXBCF_CF20_Pos)) +#define MCAN_TXBCF_CF21_Pos _U_(21) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Position */ +#define MCAN_TXBCF_CF21_Msk (_U_(0x1) << MCAN_TXBCF_CF21_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Mask */ +#define MCAN_TXBCF_CF21(value) (MCAN_TXBCF_CF21_Msk & ((value) << MCAN_TXBCF_CF21_Pos)) +#define MCAN_TXBCF_CF22_Pos _U_(22) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Position */ +#define MCAN_TXBCF_CF22_Msk (_U_(0x1) << MCAN_TXBCF_CF22_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Mask */ +#define MCAN_TXBCF_CF22(value) (MCAN_TXBCF_CF22_Msk & ((value) << MCAN_TXBCF_CF22_Pos)) +#define MCAN_TXBCF_CF23_Pos _U_(23) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Position */ +#define MCAN_TXBCF_CF23_Msk (_U_(0x1) << MCAN_TXBCF_CF23_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Mask */ +#define MCAN_TXBCF_CF23(value) (MCAN_TXBCF_CF23_Msk & ((value) << MCAN_TXBCF_CF23_Pos)) +#define MCAN_TXBCF_CF24_Pos _U_(24) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Position */ +#define MCAN_TXBCF_CF24_Msk (_U_(0x1) << MCAN_TXBCF_CF24_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Mask */ +#define MCAN_TXBCF_CF24(value) (MCAN_TXBCF_CF24_Msk & ((value) << MCAN_TXBCF_CF24_Pos)) +#define MCAN_TXBCF_CF25_Pos _U_(25) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Position */ +#define MCAN_TXBCF_CF25_Msk (_U_(0x1) << MCAN_TXBCF_CF25_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Mask */ +#define MCAN_TXBCF_CF25(value) (MCAN_TXBCF_CF25_Msk & ((value) << MCAN_TXBCF_CF25_Pos)) +#define MCAN_TXBCF_CF26_Pos _U_(26) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Position */ +#define MCAN_TXBCF_CF26_Msk (_U_(0x1) << MCAN_TXBCF_CF26_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Mask */ +#define MCAN_TXBCF_CF26(value) (MCAN_TXBCF_CF26_Msk & ((value) << MCAN_TXBCF_CF26_Pos)) +#define MCAN_TXBCF_CF27_Pos _U_(27) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Position */ +#define MCAN_TXBCF_CF27_Msk (_U_(0x1) << MCAN_TXBCF_CF27_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Mask */ +#define MCAN_TXBCF_CF27(value) (MCAN_TXBCF_CF27_Msk & ((value) << MCAN_TXBCF_CF27_Pos)) +#define MCAN_TXBCF_CF28_Pos _U_(28) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Position */ +#define MCAN_TXBCF_CF28_Msk (_U_(0x1) << MCAN_TXBCF_CF28_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Mask */ +#define MCAN_TXBCF_CF28(value) (MCAN_TXBCF_CF28_Msk & ((value) << MCAN_TXBCF_CF28_Pos)) +#define MCAN_TXBCF_CF29_Pos _U_(29) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Position */ +#define MCAN_TXBCF_CF29_Msk (_U_(0x1) << MCAN_TXBCF_CF29_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Mask */ +#define MCAN_TXBCF_CF29(value) (MCAN_TXBCF_CF29_Msk & ((value) << MCAN_TXBCF_CF29_Pos)) +#define MCAN_TXBCF_CF30_Pos _U_(30) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Position */ +#define MCAN_TXBCF_CF30_Msk (_U_(0x1) << MCAN_TXBCF_CF30_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Mask */ +#define MCAN_TXBCF_CF30(value) (MCAN_TXBCF_CF30_Msk & ((value) << MCAN_TXBCF_CF30_Pos)) +#define MCAN_TXBCF_CF31_Pos _U_(31) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Position */ +#define MCAN_TXBCF_CF31_Msk (_U_(0x1) << MCAN_TXBCF_CF31_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Mask */ +#define MCAN_TXBCF_CF31(value) (MCAN_TXBCF_CF31_Msk & ((value) << MCAN_TXBCF_CF31_Pos)) +#define MCAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCF) Register Mask */ + +#define MCAN_TXBCF_CF_Pos _U_(0) /**< (MCAN_TXBCF Position) Cancellation Finished for Transmit Buffer 3x */ +#define MCAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCF_CF_Pos) /**< (MCAN_TXBCF Mask) CF */ +#define MCAN_TXBCF_CF(value) (MCAN_TXBCF_CF_Msk & ((value) << MCAN_TXBCF_CF_Pos)) + +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) (R/W 32) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0_Pos _U_(0) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Position */ +#define MCAN_TXBTIE_TIE0_Msk (_U_(0x1) << MCAN_TXBTIE_TIE0_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Mask */ +#define MCAN_TXBTIE_TIE0(value) (MCAN_TXBTIE_TIE0_Msk & ((value) << MCAN_TXBTIE_TIE0_Pos)) +#define MCAN_TXBTIE_TIE1_Pos _U_(1) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Position */ +#define MCAN_TXBTIE_TIE1_Msk (_U_(0x1) << MCAN_TXBTIE_TIE1_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Mask */ +#define MCAN_TXBTIE_TIE1(value) (MCAN_TXBTIE_TIE1_Msk & ((value) << MCAN_TXBTIE_TIE1_Pos)) +#define MCAN_TXBTIE_TIE2_Pos _U_(2) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Position */ +#define MCAN_TXBTIE_TIE2_Msk (_U_(0x1) << MCAN_TXBTIE_TIE2_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Mask */ +#define MCAN_TXBTIE_TIE2(value) (MCAN_TXBTIE_TIE2_Msk & ((value) << MCAN_TXBTIE_TIE2_Pos)) +#define MCAN_TXBTIE_TIE3_Pos _U_(3) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Position */ +#define MCAN_TXBTIE_TIE3_Msk (_U_(0x1) << MCAN_TXBTIE_TIE3_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Mask */ +#define MCAN_TXBTIE_TIE3(value) (MCAN_TXBTIE_TIE3_Msk & ((value) << MCAN_TXBTIE_TIE3_Pos)) +#define MCAN_TXBTIE_TIE4_Pos _U_(4) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Position */ +#define MCAN_TXBTIE_TIE4_Msk (_U_(0x1) << MCAN_TXBTIE_TIE4_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Mask */ +#define MCAN_TXBTIE_TIE4(value) (MCAN_TXBTIE_TIE4_Msk & ((value) << MCAN_TXBTIE_TIE4_Pos)) +#define MCAN_TXBTIE_TIE5_Pos _U_(5) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Position */ +#define MCAN_TXBTIE_TIE5_Msk (_U_(0x1) << MCAN_TXBTIE_TIE5_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Mask */ +#define MCAN_TXBTIE_TIE5(value) (MCAN_TXBTIE_TIE5_Msk & ((value) << MCAN_TXBTIE_TIE5_Pos)) +#define MCAN_TXBTIE_TIE6_Pos _U_(6) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Position */ +#define MCAN_TXBTIE_TIE6_Msk (_U_(0x1) << MCAN_TXBTIE_TIE6_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Mask */ +#define MCAN_TXBTIE_TIE6(value) (MCAN_TXBTIE_TIE6_Msk & ((value) << MCAN_TXBTIE_TIE6_Pos)) +#define MCAN_TXBTIE_TIE7_Pos _U_(7) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Position */ +#define MCAN_TXBTIE_TIE7_Msk (_U_(0x1) << MCAN_TXBTIE_TIE7_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Mask */ +#define MCAN_TXBTIE_TIE7(value) (MCAN_TXBTIE_TIE7_Msk & ((value) << MCAN_TXBTIE_TIE7_Pos)) +#define MCAN_TXBTIE_TIE8_Pos _U_(8) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Position */ +#define MCAN_TXBTIE_TIE8_Msk (_U_(0x1) << MCAN_TXBTIE_TIE8_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Mask */ +#define MCAN_TXBTIE_TIE8(value) (MCAN_TXBTIE_TIE8_Msk & ((value) << MCAN_TXBTIE_TIE8_Pos)) +#define MCAN_TXBTIE_TIE9_Pos _U_(9) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Position */ +#define MCAN_TXBTIE_TIE9_Msk (_U_(0x1) << MCAN_TXBTIE_TIE9_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Mask */ +#define MCAN_TXBTIE_TIE9(value) (MCAN_TXBTIE_TIE9_Msk & ((value) << MCAN_TXBTIE_TIE9_Pos)) +#define MCAN_TXBTIE_TIE10_Pos _U_(10) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Position */ +#define MCAN_TXBTIE_TIE10_Msk (_U_(0x1) << MCAN_TXBTIE_TIE10_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Mask */ +#define MCAN_TXBTIE_TIE10(value) (MCAN_TXBTIE_TIE10_Msk & ((value) << MCAN_TXBTIE_TIE10_Pos)) +#define MCAN_TXBTIE_TIE11_Pos _U_(11) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Position */ +#define MCAN_TXBTIE_TIE11_Msk (_U_(0x1) << MCAN_TXBTIE_TIE11_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Mask */ +#define MCAN_TXBTIE_TIE11(value) (MCAN_TXBTIE_TIE11_Msk & ((value) << MCAN_TXBTIE_TIE11_Pos)) +#define MCAN_TXBTIE_TIE12_Pos _U_(12) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Position */ +#define MCAN_TXBTIE_TIE12_Msk (_U_(0x1) << MCAN_TXBTIE_TIE12_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Mask */ +#define MCAN_TXBTIE_TIE12(value) (MCAN_TXBTIE_TIE12_Msk & ((value) << MCAN_TXBTIE_TIE12_Pos)) +#define MCAN_TXBTIE_TIE13_Pos _U_(13) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Position */ +#define MCAN_TXBTIE_TIE13_Msk (_U_(0x1) << MCAN_TXBTIE_TIE13_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Mask */ +#define MCAN_TXBTIE_TIE13(value) (MCAN_TXBTIE_TIE13_Msk & ((value) << MCAN_TXBTIE_TIE13_Pos)) +#define MCAN_TXBTIE_TIE14_Pos _U_(14) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Position */ +#define MCAN_TXBTIE_TIE14_Msk (_U_(0x1) << MCAN_TXBTIE_TIE14_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Mask */ +#define MCAN_TXBTIE_TIE14(value) (MCAN_TXBTIE_TIE14_Msk & ((value) << MCAN_TXBTIE_TIE14_Pos)) +#define MCAN_TXBTIE_TIE15_Pos _U_(15) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Position */ +#define MCAN_TXBTIE_TIE15_Msk (_U_(0x1) << MCAN_TXBTIE_TIE15_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Mask */ +#define MCAN_TXBTIE_TIE15(value) (MCAN_TXBTIE_TIE15_Msk & ((value) << MCAN_TXBTIE_TIE15_Pos)) +#define MCAN_TXBTIE_TIE16_Pos _U_(16) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Position */ +#define MCAN_TXBTIE_TIE16_Msk (_U_(0x1) << MCAN_TXBTIE_TIE16_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Mask */ +#define MCAN_TXBTIE_TIE16(value) (MCAN_TXBTIE_TIE16_Msk & ((value) << MCAN_TXBTIE_TIE16_Pos)) +#define MCAN_TXBTIE_TIE17_Pos _U_(17) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Position */ +#define MCAN_TXBTIE_TIE17_Msk (_U_(0x1) << MCAN_TXBTIE_TIE17_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Mask */ +#define MCAN_TXBTIE_TIE17(value) (MCAN_TXBTIE_TIE17_Msk & ((value) << MCAN_TXBTIE_TIE17_Pos)) +#define MCAN_TXBTIE_TIE18_Pos _U_(18) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Position */ +#define MCAN_TXBTIE_TIE18_Msk (_U_(0x1) << MCAN_TXBTIE_TIE18_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Mask */ +#define MCAN_TXBTIE_TIE18(value) (MCAN_TXBTIE_TIE18_Msk & ((value) << MCAN_TXBTIE_TIE18_Pos)) +#define MCAN_TXBTIE_TIE19_Pos _U_(19) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Position */ +#define MCAN_TXBTIE_TIE19_Msk (_U_(0x1) << MCAN_TXBTIE_TIE19_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Mask */ +#define MCAN_TXBTIE_TIE19(value) (MCAN_TXBTIE_TIE19_Msk & ((value) << MCAN_TXBTIE_TIE19_Pos)) +#define MCAN_TXBTIE_TIE20_Pos _U_(20) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Position */ +#define MCAN_TXBTIE_TIE20_Msk (_U_(0x1) << MCAN_TXBTIE_TIE20_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Mask */ +#define MCAN_TXBTIE_TIE20(value) (MCAN_TXBTIE_TIE20_Msk & ((value) << MCAN_TXBTIE_TIE20_Pos)) +#define MCAN_TXBTIE_TIE21_Pos _U_(21) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Position */ +#define MCAN_TXBTIE_TIE21_Msk (_U_(0x1) << MCAN_TXBTIE_TIE21_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Mask */ +#define MCAN_TXBTIE_TIE21(value) (MCAN_TXBTIE_TIE21_Msk & ((value) << MCAN_TXBTIE_TIE21_Pos)) +#define MCAN_TXBTIE_TIE22_Pos _U_(22) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Position */ +#define MCAN_TXBTIE_TIE22_Msk (_U_(0x1) << MCAN_TXBTIE_TIE22_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Mask */ +#define MCAN_TXBTIE_TIE22(value) (MCAN_TXBTIE_TIE22_Msk & ((value) << MCAN_TXBTIE_TIE22_Pos)) +#define MCAN_TXBTIE_TIE23_Pos _U_(23) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Position */ +#define MCAN_TXBTIE_TIE23_Msk (_U_(0x1) << MCAN_TXBTIE_TIE23_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Mask */ +#define MCAN_TXBTIE_TIE23(value) (MCAN_TXBTIE_TIE23_Msk & ((value) << MCAN_TXBTIE_TIE23_Pos)) +#define MCAN_TXBTIE_TIE24_Pos _U_(24) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Position */ +#define MCAN_TXBTIE_TIE24_Msk (_U_(0x1) << MCAN_TXBTIE_TIE24_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Mask */ +#define MCAN_TXBTIE_TIE24(value) (MCAN_TXBTIE_TIE24_Msk & ((value) << MCAN_TXBTIE_TIE24_Pos)) +#define MCAN_TXBTIE_TIE25_Pos _U_(25) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Position */ +#define MCAN_TXBTIE_TIE25_Msk (_U_(0x1) << MCAN_TXBTIE_TIE25_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Mask */ +#define MCAN_TXBTIE_TIE25(value) (MCAN_TXBTIE_TIE25_Msk & ((value) << MCAN_TXBTIE_TIE25_Pos)) +#define MCAN_TXBTIE_TIE26_Pos _U_(26) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Position */ +#define MCAN_TXBTIE_TIE26_Msk (_U_(0x1) << MCAN_TXBTIE_TIE26_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Mask */ +#define MCAN_TXBTIE_TIE26(value) (MCAN_TXBTIE_TIE26_Msk & ((value) << MCAN_TXBTIE_TIE26_Pos)) +#define MCAN_TXBTIE_TIE27_Pos _U_(27) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Position */ +#define MCAN_TXBTIE_TIE27_Msk (_U_(0x1) << MCAN_TXBTIE_TIE27_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Mask */ +#define MCAN_TXBTIE_TIE27(value) (MCAN_TXBTIE_TIE27_Msk & ((value) << MCAN_TXBTIE_TIE27_Pos)) +#define MCAN_TXBTIE_TIE28_Pos _U_(28) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Position */ +#define MCAN_TXBTIE_TIE28_Msk (_U_(0x1) << MCAN_TXBTIE_TIE28_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Mask */ +#define MCAN_TXBTIE_TIE28(value) (MCAN_TXBTIE_TIE28_Msk & ((value) << MCAN_TXBTIE_TIE28_Pos)) +#define MCAN_TXBTIE_TIE29_Pos _U_(29) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Position */ +#define MCAN_TXBTIE_TIE29_Msk (_U_(0x1) << MCAN_TXBTIE_TIE29_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Mask */ +#define MCAN_TXBTIE_TIE29(value) (MCAN_TXBTIE_TIE29_Msk & ((value) << MCAN_TXBTIE_TIE29_Pos)) +#define MCAN_TXBTIE_TIE30_Pos _U_(30) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Position */ +#define MCAN_TXBTIE_TIE30_Msk (_U_(0x1) << MCAN_TXBTIE_TIE30_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Mask */ +#define MCAN_TXBTIE_TIE30(value) (MCAN_TXBTIE_TIE30_Msk & ((value) << MCAN_TXBTIE_TIE30_Pos)) +#define MCAN_TXBTIE_TIE31_Pos _U_(31) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Position */ +#define MCAN_TXBTIE_TIE31_Msk (_U_(0x1) << MCAN_TXBTIE_TIE31_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Mask */ +#define MCAN_TXBTIE_TIE31(value) (MCAN_TXBTIE_TIE31_Msk & ((value) << MCAN_TXBTIE_TIE31_Pos)) +#define MCAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTIE) Register Mask */ + +#define MCAN_TXBTIE_TIE_Pos _U_(0) /**< (MCAN_TXBTIE Position) Transmission Interrupt Enable for Buffer 3x */ +#define MCAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTIE_TIE_Pos) /**< (MCAN_TXBTIE Mask) TIE */ +#define MCAN_TXBTIE_TIE(value) (MCAN_TXBTIE_TIE_Msk & ((value) << MCAN_TXBTIE_TIE_Pos)) + +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0_Pos _U_(0) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Position */ +#define MCAN_TXBCIE_CFIE0_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE0_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Mask */ +#define MCAN_TXBCIE_CFIE0(value) (MCAN_TXBCIE_CFIE0_Msk & ((value) << MCAN_TXBCIE_CFIE0_Pos)) +#define MCAN_TXBCIE_CFIE1_Pos _U_(1) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Position */ +#define MCAN_TXBCIE_CFIE1_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE1_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Mask */ +#define MCAN_TXBCIE_CFIE1(value) (MCAN_TXBCIE_CFIE1_Msk & ((value) << MCAN_TXBCIE_CFIE1_Pos)) +#define MCAN_TXBCIE_CFIE2_Pos _U_(2) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Position */ +#define MCAN_TXBCIE_CFIE2_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE2_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Mask */ +#define MCAN_TXBCIE_CFIE2(value) (MCAN_TXBCIE_CFIE2_Msk & ((value) << MCAN_TXBCIE_CFIE2_Pos)) +#define MCAN_TXBCIE_CFIE3_Pos _U_(3) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Position */ +#define MCAN_TXBCIE_CFIE3_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE3_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Mask */ +#define MCAN_TXBCIE_CFIE3(value) (MCAN_TXBCIE_CFIE3_Msk & ((value) << MCAN_TXBCIE_CFIE3_Pos)) +#define MCAN_TXBCIE_CFIE4_Pos _U_(4) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Position */ +#define MCAN_TXBCIE_CFIE4_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE4_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Mask */ +#define MCAN_TXBCIE_CFIE4(value) (MCAN_TXBCIE_CFIE4_Msk & ((value) << MCAN_TXBCIE_CFIE4_Pos)) +#define MCAN_TXBCIE_CFIE5_Pos _U_(5) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Position */ +#define MCAN_TXBCIE_CFIE5_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE5_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Mask */ +#define MCAN_TXBCIE_CFIE5(value) (MCAN_TXBCIE_CFIE5_Msk & ((value) << MCAN_TXBCIE_CFIE5_Pos)) +#define MCAN_TXBCIE_CFIE6_Pos _U_(6) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Position */ +#define MCAN_TXBCIE_CFIE6_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE6_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Mask */ +#define MCAN_TXBCIE_CFIE6(value) (MCAN_TXBCIE_CFIE6_Msk & ((value) << MCAN_TXBCIE_CFIE6_Pos)) +#define MCAN_TXBCIE_CFIE7_Pos _U_(7) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Position */ +#define MCAN_TXBCIE_CFIE7_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE7_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Mask */ +#define MCAN_TXBCIE_CFIE7(value) (MCAN_TXBCIE_CFIE7_Msk & ((value) << MCAN_TXBCIE_CFIE7_Pos)) +#define MCAN_TXBCIE_CFIE8_Pos _U_(8) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Position */ +#define MCAN_TXBCIE_CFIE8_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE8_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Mask */ +#define MCAN_TXBCIE_CFIE8(value) (MCAN_TXBCIE_CFIE8_Msk & ((value) << MCAN_TXBCIE_CFIE8_Pos)) +#define MCAN_TXBCIE_CFIE9_Pos _U_(9) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Position */ +#define MCAN_TXBCIE_CFIE9_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE9_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Mask */ +#define MCAN_TXBCIE_CFIE9(value) (MCAN_TXBCIE_CFIE9_Msk & ((value) << MCAN_TXBCIE_CFIE9_Pos)) +#define MCAN_TXBCIE_CFIE10_Pos _U_(10) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Position */ +#define MCAN_TXBCIE_CFIE10_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE10_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Mask */ +#define MCAN_TXBCIE_CFIE10(value) (MCAN_TXBCIE_CFIE10_Msk & ((value) << MCAN_TXBCIE_CFIE10_Pos)) +#define MCAN_TXBCIE_CFIE11_Pos _U_(11) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Position */ +#define MCAN_TXBCIE_CFIE11_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE11_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Mask */ +#define MCAN_TXBCIE_CFIE11(value) (MCAN_TXBCIE_CFIE11_Msk & ((value) << MCAN_TXBCIE_CFIE11_Pos)) +#define MCAN_TXBCIE_CFIE12_Pos _U_(12) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Position */ +#define MCAN_TXBCIE_CFIE12_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE12_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Mask */ +#define MCAN_TXBCIE_CFIE12(value) (MCAN_TXBCIE_CFIE12_Msk & ((value) << MCAN_TXBCIE_CFIE12_Pos)) +#define MCAN_TXBCIE_CFIE13_Pos _U_(13) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Position */ +#define MCAN_TXBCIE_CFIE13_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE13_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Mask */ +#define MCAN_TXBCIE_CFIE13(value) (MCAN_TXBCIE_CFIE13_Msk & ((value) << MCAN_TXBCIE_CFIE13_Pos)) +#define MCAN_TXBCIE_CFIE14_Pos _U_(14) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Position */ +#define MCAN_TXBCIE_CFIE14_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE14_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Mask */ +#define MCAN_TXBCIE_CFIE14(value) (MCAN_TXBCIE_CFIE14_Msk & ((value) << MCAN_TXBCIE_CFIE14_Pos)) +#define MCAN_TXBCIE_CFIE15_Pos _U_(15) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Position */ +#define MCAN_TXBCIE_CFIE15_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE15_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Mask */ +#define MCAN_TXBCIE_CFIE15(value) (MCAN_TXBCIE_CFIE15_Msk & ((value) << MCAN_TXBCIE_CFIE15_Pos)) +#define MCAN_TXBCIE_CFIE16_Pos _U_(16) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Position */ +#define MCAN_TXBCIE_CFIE16_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE16_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Mask */ +#define MCAN_TXBCIE_CFIE16(value) (MCAN_TXBCIE_CFIE16_Msk & ((value) << MCAN_TXBCIE_CFIE16_Pos)) +#define MCAN_TXBCIE_CFIE17_Pos _U_(17) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Position */ +#define MCAN_TXBCIE_CFIE17_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE17_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Mask */ +#define MCAN_TXBCIE_CFIE17(value) (MCAN_TXBCIE_CFIE17_Msk & ((value) << MCAN_TXBCIE_CFIE17_Pos)) +#define MCAN_TXBCIE_CFIE18_Pos _U_(18) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Position */ +#define MCAN_TXBCIE_CFIE18_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE18_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Mask */ +#define MCAN_TXBCIE_CFIE18(value) (MCAN_TXBCIE_CFIE18_Msk & ((value) << MCAN_TXBCIE_CFIE18_Pos)) +#define MCAN_TXBCIE_CFIE19_Pos _U_(19) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Position */ +#define MCAN_TXBCIE_CFIE19_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE19_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Mask */ +#define MCAN_TXBCIE_CFIE19(value) (MCAN_TXBCIE_CFIE19_Msk & ((value) << MCAN_TXBCIE_CFIE19_Pos)) +#define MCAN_TXBCIE_CFIE20_Pos _U_(20) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Position */ +#define MCAN_TXBCIE_CFIE20_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE20_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Mask */ +#define MCAN_TXBCIE_CFIE20(value) (MCAN_TXBCIE_CFIE20_Msk & ((value) << MCAN_TXBCIE_CFIE20_Pos)) +#define MCAN_TXBCIE_CFIE21_Pos _U_(21) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Position */ +#define MCAN_TXBCIE_CFIE21_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE21_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Mask */ +#define MCAN_TXBCIE_CFIE21(value) (MCAN_TXBCIE_CFIE21_Msk & ((value) << MCAN_TXBCIE_CFIE21_Pos)) +#define MCAN_TXBCIE_CFIE22_Pos _U_(22) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Position */ +#define MCAN_TXBCIE_CFIE22_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE22_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Mask */ +#define MCAN_TXBCIE_CFIE22(value) (MCAN_TXBCIE_CFIE22_Msk & ((value) << MCAN_TXBCIE_CFIE22_Pos)) +#define MCAN_TXBCIE_CFIE23_Pos _U_(23) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Position */ +#define MCAN_TXBCIE_CFIE23_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE23_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Mask */ +#define MCAN_TXBCIE_CFIE23(value) (MCAN_TXBCIE_CFIE23_Msk & ((value) << MCAN_TXBCIE_CFIE23_Pos)) +#define MCAN_TXBCIE_CFIE24_Pos _U_(24) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Position */ +#define MCAN_TXBCIE_CFIE24_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE24_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Mask */ +#define MCAN_TXBCIE_CFIE24(value) (MCAN_TXBCIE_CFIE24_Msk & ((value) << MCAN_TXBCIE_CFIE24_Pos)) +#define MCAN_TXBCIE_CFIE25_Pos _U_(25) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Position */ +#define MCAN_TXBCIE_CFIE25_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE25_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Mask */ +#define MCAN_TXBCIE_CFIE25(value) (MCAN_TXBCIE_CFIE25_Msk & ((value) << MCAN_TXBCIE_CFIE25_Pos)) +#define MCAN_TXBCIE_CFIE26_Pos _U_(26) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Position */ +#define MCAN_TXBCIE_CFIE26_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE26_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Mask */ +#define MCAN_TXBCIE_CFIE26(value) (MCAN_TXBCIE_CFIE26_Msk & ((value) << MCAN_TXBCIE_CFIE26_Pos)) +#define MCAN_TXBCIE_CFIE27_Pos _U_(27) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Position */ +#define MCAN_TXBCIE_CFIE27_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE27_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Mask */ +#define MCAN_TXBCIE_CFIE27(value) (MCAN_TXBCIE_CFIE27_Msk & ((value) << MCAN_TXBCIE_CFIE27_Pos)) +#define MCAN_TXBCIE_CFIE28_Pos _U_(28) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Position */ +#define MCAN_TXBCIE_CFIE28_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE28_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Mask */ +#define MCAN_TXBCIE_CFIE28(value) (MCAN_TXBCIE_CFIE28_Msk & ((value) << MCAN_TXBCIE_CFIE28_Pos)) +#define MCAN_TXBCIE_CFIE29_Pos _U_(29) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Position */ +#define MCAN_TXBCIE_CFIE29_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE29_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Mask */ +#define MCAN_TXBCIE_CFIE29(value) (MCAN_TXBCIE_CFIE29_Msk & ((value) << MCAN_TXBCIE_CFIE29_Pos)) +#define MCAN_TXBCIE_CFIE30_Pos _U_(30) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Position */ +#define MCAN_TXBCIE_CFIE30_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE30_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Mask */ +#define MCAN_TXBCIE_CFIE30(value) (MCAN_TXBCIE_CFIE30_Msk & ((value) << MCAN_TXBCIE_CFIE30_Pos)) +#define MCAN_TXBCIE_CFIE31_Pos _U_(31) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Position */ +#define MCAN_TXBCIE_CFIE31_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE31_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Mask */ +#define MCAN_TXBCIE_CFIE31(value) (MCAN_TXBCIE_CFIE31_Msk & ((value) << MCAN_TXBCIE_CFIE31_Pos)) +#define MCAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCIE) Register Mask */ + +#define MCAN_TXBCIE_CFIE_Pos _U_(0) /**< (MCAN_TXBCIE Position) Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ +#define MCAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCIE_CFIE_Pos) /**< (MCAN_TXBCIE Mask) CFIE */ +#define MCAN_TXBCIE_CFIE(value) (MCAN_TXBCIE_CFIE_Msk & ((value) << MCAN_TXBCIE_CFIE_Pos)) + +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) (R/W 32) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos _U_(2) /**< (MCAN_TXEFC) Event FIFO Start Address Position */ +#define MCAN_TXEFC_EFSA_Msk (_U_(0x3FFF) << MCAN_TXEFC_EFSA_Pos) /**< (MCAN_TXEFC) Event FIFO Start Address Mask */ +#define MCAN_TXEFC_EFSA(value) (MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)) +#define MCAN_TXEFC_EFS_Pos _U_(16) /**< (MCAN_TXEFC) Event FIFO Size Position */ +#define MCAN_TXEFC_EFS_Msk (_U_(0x3F) << MCAN_TXEFC_EFS_Pos) /**< (MCAN_TXEFC) Event FIFO Size Mask */ +#define MCAN_TXEFC_EFS(value) (MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)) +#define MCAN_TXEFC_EFWM_Pos _U_(24) /**< (MCAN_TXEFC) Event FIFO Watermark Position */ +#define MCAN_TXEFC_EFWM_Msk (_U_(0x3F) << MCAN_TXEFC_EFWM_Pos) /**< (MCAN_TXEFC) Event FIFO Watermark Mask */ +#define MCAN_TXEFC_EFWM(value) (MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)) +#define MCAN_TXEFC_Msk _U_(0x3F3FFFFC) /**< (MCAN_TXEFC) Register Mask */ + + +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) ( R/ 32) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos _U_(0) /**< (MCAN_TXEFS) Event FIFO Fill Level Position */ +#define MCAN_TXEFS_EFFL_Msk (_U_(0x3F) << MCAN_TXEFS_EFFL_Pos) /**< (MCAN_TXEFS) Event FIFO Fill Level Mask */ +#define MCAN_TXEFS_EFFL(value) (MCAN_TXEFS_EFFL_Msk & ((value) << MCAN_TXEFS_EFFL_Pos)) +#define MCAN_TXEFS_EFGI_Pos _U_(8) /**< (MCAN_TXEFS) Event FIFO Get Index Position */ +#define MCAN_TXEFS_EFGI_Msk (_U_(0x1F) << MCAN_TXEFS_EFGI_Pos) /**< (MCAN_TXEFS) Event FIFO Get Index Mask */ +#define MCAN_TXEFS_EFGI(value) (MCAN_TXEFS_EFGI_Msk & ((value) << MCAN_TXEFS_EFGI_Pos)) +#define MCAN_TXEFS_EFPI_Pos _U_(16) /**< (MCAN_TXEFS) Event FIFO Put Index Position */ +#define MCAN_TXEFS_EFPI_Msk (_U_(0x1F) << MCAN_TXEFS_EFPI_Pos) /**< (MCAN_TXEFS) Event FIFO Put Index Mask */ +#define MCAN_TXEFS_EFPI(value) (MCAN_TXEFS_EFPI_Msk & ((value) << MCAN_TXEFS_EFPI_Pos)) +#define MCAN_TXEFS_EFF_Pos _U_(24) /**< (MCAN_TXEFS) Event FIFO Full Position */ +#define MCAN_TXEFS_EFF_Msk (_U_(0x1) << MCAN_TXEFS_EFF_Pos) /**< (MCAN_TXEFS) Event FIFO Full Mask */ +#define MCAN_TXEFS_EFF(value) (MCAN_TXEFS_EFF_Msk & ((value) << MCAN_TXEFS_EFF_Pos)) +#define MCAN_TXEFS_TEFL_Pos _U_(25) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define MCAN_TXEFS_TEFL_Msk (_U_(0x1) << MCAN_TXEFS_TEFL_Pos) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define MCAN_TXEFS_TEFL(value) (MCAN_TXEFS_TEFL_Msk & ((value) << MCAN_TXEFS_TEFL_Pos)) +#define MCAN_TXEFS_Msk _U_(0x031F1F3F) /**< (MCAN_TXEFS) Register Mask */ + + +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) (R/W 32) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos _U_(0) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define MCAN_TXEFA_EFAI_Msk (_U_(0x1F) << MCAN_TXEFA_EFAI_Pos) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define MCAN_TXEFA_EFAI(value) (MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)) +#define MCAN_TXEFA_Msk _U_(0x0000001F) /**< (MCAN_TXEFA) Register Mask */ + + +/** \brief MCAN register offsets definitions */ +#define MCAN_CUST_REG_OFST (0x08) /**< (MCAN_CUST) Customer Register Offset */ +#define MCAN_FBTP_REG_OFST (0x0C) /**< (MCAN_FBTP) Fast Bit Timing and Prescaler Register Offset */ +#define MCAN_TEST_REG_OFST (0x10) /**< (MCAN_TEST) Test Register Offset */ +#define MCAN_RWD_REG_OFST (0x14) /**< (MCAN_RWD) RAM Watchdog Register Offset */ +#define MCAN_CCCR_REG_OFST (0x18) /**< (MCAN_CCCR) CC Control Register Offset */ +#define MCAN_BTP_REG_OFST (0x1C) /**< (MCAN_BTP) Bit Timing and Prescaler Register Offset */ +#define MCAN_TSCC_REG_OFST (0x20) /**< (MCAN_TSCC) Timestamp Counter Configuration Register Offset */ +#define MCAN_TSCV_REG_OFST (0x24) /**< (MCAN_TSCV) Timestamp Counter Value Register Offset */ +#define MCAN_TOCC_REG_OFST (0x28) /**< (MCAN_TOCC) Timeout Counter Configuration Register Offset */ +#define MCAN_TOCV_REG_OFST (0x2C) /**< (MCAN_TOCV) Timeout Counter Value Register Offset */ +#define MCAN_ECR_REG_OFST (0x40) /**< (MCAN_ECR) Error Counter Register Offset */ +#define MCAN_PSR_REG_OFST (0x44) /**< (MCAN_PSR) Protocol Status Register Offset */ +#define MCAN_IR_REG_OFST (0x50) /**< (MCAN_IR) Interrupt Register Offset */ +#define MCAN_IE_REG_OFST (0x54) /**< (MCAN_IE) Interrupt Enable Register Offset */ +#define MCAN_ILS_REG_OFST (0x58) /**< (MCAN_ILS) Interrupt Line Select Register Offset */ +#define MCAN_ILE_REG_OFST (0x5C) /**< (MCAN_ILE) Interrupt Line Enable Register Offset */ +#define MCAN_GFC_REG_OFST (0x80) /**< (MCAN_GFC) Global Filter Configuration Register Offset */ +#define MCAN_SIDFC_REG_OFST (0x84) /**< (MCAN_SIDFC) Standard ID Filter Configuration Register Offset */ +#define MCAN_XIDFC_REG_OFST (0x88) /**< (MCAN_XIDFC) Extended ID Filter Configuration Register Offset */ +#define MCAN_XIDAM_REG_OFST (0x90) /**< (MCAN_XIDAM) Extended ID AND Mask Register Offset */ +#define MCAN_HPMS_REG_OFST (0x94) /**< (MCAN_HPMS) High Priority Message Status Register Offset */ +#define MCAN_NDAT1_REG_OFST (0x98) /**< (MCAN_NDAT1) New Data 1 Register Offset */ +#define MCAN_NDAT2_REG_OFST (0x9C) /**< (MCAN_NDAT2) New Data 2 Register Offset */ +#define MCAN_RXF0C_REG_OFST (0xA0) /**< (MCAN_RXF0C) Receive FIFO 0 Configuration Register Offset */ +#define MCAN_RXF0S_REG_OFST (0xA4) /**< (MCAN_RXF0S) Receive FIFO 0 Status Register Offset */ +#define MCAN_RXF0A_REG_OFST (0xA8) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Register Offset */ +#define MCAN_RXBC_REG_OFST (0xAC) /**< (MCAN_RXBC) Receive Rx Buffer Configuration Register Offset */ +#define MCAN_RXF1C_REG_OFST (0xB0) /**< (MCAN_RXF1C) Receive FIFO 1 Configuration Register Offset */ +#define MCAN_RXF1S_REG_OFST (0xB4) /**< (MCAN_RXF1S) Receive FIFO 1 Status Register Offset */ +#define MCAN_RXF1A_REG_OFST (0xB8) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Register Offset */ +#define MCAN_RXESC_REG_OFST (0xBC) /**< (MCAN_RXESC) Receive Buffer / FIFO Element Size Configuration Register Offset */ +#define MCAN_TXBC_REG_OFST (0xC0) /**< (MCAN_TXBC) Transmit Buffer Configuration Register Offset */ +#define MCAN_TXFQS_REG_OFST (0xC4) /**< (MCAN_TXFQS) Transmit FIFO/Queue Status Register Offset */ +#define MCAN_TXESC_REG_OFST (0xC8) /**< (MCAN_TXESC) Transmit Buffer Element Size Configuration Register Offset */ +#define MCAN_TXBRP_REG_OFST (0xCC) /**< (MCAN_TXBRP) Transmit Buffer Request Pending Register Offset */ +#define MCAN_TXBAR_REG_OFST (0xD0) /**< (MCAN_TXBAR) Transmit Buffer Add Request Register Offset */ +#define MCAN_TXBCR_REG_OFST (0xD4) /**< (MCAN_TXBCR) Transmit Buffer Cancellation Request Register Offset */ +#define MCAN_TXBTO_REG_OFST (0xD8) /**< (MCAN_TXBTO) Transmit Buffer Transmission Occurred Register Offset */ +#define MCAN_TXBCF_REG_OFST (0xDC) /**< (MCAN_TXBCF) Transmit Buffer Cancellation Finished Register Offset */ +#define MCAN_TXBTIE_REG_OFST (0xE0) /**< (MCAN_TXBTIE) Transmit Buffer Transmission Interrupt Enable Register Offset */ +#define MCAN_TXBCIE_REG_OFST (0xE4) /**< (MCAN_TXBCIE) Transmit Buffer Cancellation Finished Interrupt Enable Register Offset */ +#define MCAN_TXEFC_REG_OFST (0xF0) /**< (MCAN_TXEFC) Transmit Event FIFO Configuration Register Offset */ +#define MCAN_TXEFS_REG_OFST (0xF4) /**< (MCAN_TXEFS) Transmit Event FIFO Status Register Offset */ +#define MCAN_TXEFA_REG_OFST (0xF8) /**< (MCAN_TXEFA) Transmit Event FIFO Acknowledge Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MCAN register API structure */ +typedef struct +{ + __I uint8_t Reserved1[0x08]; + __IO uint32_t MCAN_CUST; /**< Offset: 0x08 (R/W 32) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< Offset: 0x10 (R/W 32) Test Register */ + __IO uint32_t MCAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< Offset: 0x1C (R/W 32) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< Offset: 0x24 (R/W 32) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value Register */ + __I uint8_t Reserved2[0x10]; + __I uint32_t MCAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status Register */ + __I uint8_t Reserved3[0x08]; + __IO uint32_t MCAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable Register */ + __I uint8_t Reserved4[0x20]; + __IO uint32_t MCAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration Register */ + __I uint8_t Reserved5[0x04]; + __IO uint32_t MCAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< Offset: 0xAC (R/W 32) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< Offset: 0xBC (R/W 32) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< Offset: 0xC0 (R/W 32) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< Offset: 0xC8 (R/W 32) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< Offset: 0xCC (R/ 32) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< Offset: 0xDC (R/ 32) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint8_t Reserved6[0x08]; + __IO uint32_t MCAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Transmit Event FIFO Acknowledge Register */ +} mcan_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_MCAN_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/pio.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/pio.h new file mode 100644 index 00000000..a69d07a6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/pio.h @@ -0,0 +1,5045 @@ +/** + * \brief Component description for PIO + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_PIO_COMPONENT_H_ +#define _SAME70_PIO_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PIO */ +/* ************************************************************************** */ + +/* -------- PIO_PER : (PIO Offset: 0x00) ( /W 32) PIO Enable Register -------- */ +#define PIO_PER_P0_Pos _U_(0) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P0_Msk (_U_(0x1) << PIO_PER_P0_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P0(value) (PIO_PER_P0_Msk & ((value) << PIO_PER_P0_Pos)) +#define PIO_PER_P1_Pos _U_(1) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P1_Msk (_U_(0x1) << PIO_PER_P1_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P1(value) (PIO_PER_P1_Msk & ((value) << PIO_PER_P1_Pos)) +#define PIO_PER_P2_Pos _U_(2) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P2_Msk (_U_(0x1) << PIO_PER_P2_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P2(value) (PIO_PER_P2_Msk & ((value) << PIO_PER_P2_Pos)) +#define PIO_PER_P3_Pos _U_(3) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P3_Msk (_U_(0x1) << PIO_PER_P3_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P3(value) (PIO_PER_P3_Msk & ((value) << PIO_PER_P3_Pos)) +#define PIO_PER_P4_Pos _U_(4) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P4_Msk (_U_(0x1) << PIO_PER_P4_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P4(value) (PIO_PER_P4_Msk & ((value) << PIO_PER_P4_Pos)) +#define PIO_PER_P5_Pos _U_(5) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P5_Msk (_U_(0x1) << PIO_PER_P5_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P5(value) (PIO_PER_P5_Msk & ((value) << PIO_PER_P5_Pos)) +#define PIO_PER_P6_Pos _U_(6) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P6_Msk (_U_(0x1) << PIO_PER_P6_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P6(value) (PIO_PER_P6_Msk & ((value) << PIO_PER_P6_Pos)) +#define PIO_PER_P7_Pos _U_(7) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P7_Msk (_U_(0x1) << PIO_PER_P7_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P7(value) (PIO_PER_P7_Msk & ((value) << PIO_PER_P7_Pos)) +#define PIO_PER_P8_Pos _U_(8) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P8_Msk (_U_(0x1) << PIO_PER_P8_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P8(value) (PIO_PER_P8_Msk & ((value) << PIO_PER_P8_Pos)) +#define PIO_PER_P9_Pos _U_(9) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P9_Msk (_U_(0x1) << PIO_PER_P9_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P9(value) (PIO_PER_P9_Msk & ((value) << PIO_PER_P9_Pos)) +#define PIO_PER_P10_Pos _U_(10) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P10_Msk (_U_(0x1) << PIO_PER_P10_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P10(value) (PIO_PER_P10_Msk & ((value) << PIO_PER_P10_Pos)) +#define PIO_PER_P11_Pos _U_(11) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P11_Msk (_U_(0x1) << PIO_PER_P11_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P11(value) (PIO_PER_P11_Msk & ((value) << PIO_PER_P11_Pos)) +#define PIO_PER_P12_Pos _U_(12) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P12_Msk (_U_(0x1) << PIO_PER_P12_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P12(value) (PIO_PER_P12_Msk & ((value) << PIO_PER_P12_Pos)) +#define PIO_PER_P13_Pos _U_(13) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P13_Msk (_U_(0x1) << PIO_PER_P13_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P13(value) (PIO_PER_P13_Msk & ((value) << PIO_PER_P13_Pos)) +#define PIO_PER_P14_Pos _U_(14) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P14_Msk (_U_(0x1) << PIO_PER_P14_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P14(value) (PIO_PER_P14_Msk & ((value) << PIO_PER_P14_Pos)) +#define PIO_PER_P15_Pos _U_(15) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P15_Msk (_U_(0x1) << PIO_PER_P15_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P15(value) (PIO_PER_P15_Msk & ((value) << PIO_PER_P15_Pos)) +#define PIO_PER_P16_Pos _U_(16) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P16_Msk (_U_(0x1) << PIO_PER_P16_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P16(value) (PIO_PER_P16_Msk & ((value) << PIO_PER_P16_Pos)) +#define PIO_PER_P17_Pos _U_(17) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P17_Msk (_U_(0x1) << PIO_PER_P17_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P17(value) (PIO_PER_P17_Msk & ((value) << PIO_PER_P17_Pos)) +#define PIO_PER_P18_Pos _U_(18) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P18_Msk (_U_(0x1) << PIO_PER_P18_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P18(value) (PIO_PER_P18_Msk & ((value) << PIO_PER_P18_Pos)) +#define PIO_PER_P19_Pos _U_(19) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P19_Msk (_U_(0x1) << PIO_PER_P19_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P19(value) (PIO_PER_P19_Msk & ((value) << PIO_PER_P19_Pos)) +#define PIO_PER_P20_Pos _U_(20) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P20_Msk (_U_(0x1) << PIO_PER_P20_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P20(value) (PIO_PER_P20_Msk & ((value) << PIO_PER_P20_Pos)) +#define PIO_PER_P21_Pos _U_(21) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P21_Msk (_U_(0x1) << PIO_PER_P21_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P21(value) (PIO_PER_P21_Msk & ((value) << PIO_PER_P21_Pos)) +#define PIO_PER_P22_Pos _U_(22) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P22_Msk (_U_(0x1) << PIO_PER_P22_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P22(value) (PIO_PER_P22_Msk & ((value) << PIO_PER_P22_Pos)) +#define PIO_PER_P23_Pos _U_(23) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P23_Msk (_U_(0x1) << PIO_PER_P23_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P23(value) (PIO_PER_P23_Msk & ((value) << PIO_PER_P23_Pos)) +#define PIO_PER_P24_Pos _U_(24) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P24_Msk (_U_(0x1) << PIO_PER_P24_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P24(value) (PIO_PER_P24_Msk & ((value) << PIO_PER_P24_Pos)) +#define PIO_PER_P25_Pos _U_(25) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P25_Msk (_U_(0x1) << PIO_PER_P25_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P25(value) (PIO_PER_P25_Msk & ((value) << PIO_PER_P25_Pos)) +#define PIO_PER_P26_Pos _U_(26) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P26_Msk (_U_(0x1) << PIO_PER_P26_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P26(value) (PIO_PER_P26_Msk & ((value) << PIO_PER_P26_Pos)) +#define PIO_PER_P27_Pos _U_(27) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P27_Msk (_U_(0x1) << PIO_PER_P27_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P27(value) (PIO_PER_P27_Msk & ((value) << PIO_PER_P27_Pos)) +#define PIO_PER_P28_Pos _U_(28) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P28_Msk (_U_(0x1) << PIO_PER_P28_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P28(value) (PIO_PER_P28_Msk & ((value) << PIO_PER_P28_Pos)) +#define PIO_PER_P29_Pos _U_(29) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P29_Msk (_U_(0x1) << PIO_PER_P29_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P29(value) (PIO_PER_P29_Msk & ((value) << PIO_PER_P29_Pos)) +#define PIO_PER_P30_Pos _U_(30) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P30_Msk (_U_(0x1) << PIO_PER_P30_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P30(value) (PIO_PER_P30_Msk & ((value) << PIO_PER_P30_Pos)) +#define PIO_PER_P31_Pos _U_(31) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P31_Msk (_U_(0x1) << PIO_PER_P31_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P31(value) (PIO_PER_P31_Msk & ((value) << PIO_PER_P31_Pos)) +#define PIO_PER_Msk _U_(0xFFFFFFFF) /**< (PIO_PER) Register Mask */ + +#define PIO_PER_P_Pos _U_(0) /**< (PIO_PER Position) PIO Enable */ +#define PIO_PER_P_Msk (_U_(0xFFFFFFFF) << PIO_PER_P_Pos) /**< (PIO_PER Mask) P */ +#define PIO_PER_P(value) (PIO_PER_P_Msk & ((value) << PIO_PER_P_Pos)) + +/* -------- PIO_PDR : (PIO Offset: 0x04) ( /W 32) PIO Disable Register -------- */ +#define PIO_PDR_P0_Pos _U_(0) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P0_Msk (_U_(0x1) << PIO_PDR_P0_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P0(value) (PIO_PDR_P0_Msk & ((value) << PIO_PDR_P0_Pos)) +#define PIO_PDR_P1_Pos _U_(1) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P1_Msk (_U_(0x1) << PIO_PDR_P1_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P1(value) (PIO_PDR_P1_Msk & ((value) << PIO_PDR_P1_Pos)) +#define PIO_PDR_P2_Pos _U_(2) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P2_Msk (_U_(0x1) << PIO_PDR_P2_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P2(value) (PIO_PDR_P2_Msk & ((value) << PIO_PDR_P2_Pos)) +#define PIO_PDR_P3_Pos _U_(3) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P3_Msk (_U_(0x1) << PIO_PDR_P3_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P3(value) (PIO_PDR_P3_Msk & ((value) << PIO_PDR_P3_Pos)) +#define PIO_PDR_P4_Pos _U_(4) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P4_Msk (_U_(0x1) << PIO_PDR_P4_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P4(value) (PIO_PDR_P4_Msk & ((value) << PIO_PDR_P4_Pos)) +#define PIO_PDR_P5_Pos _U_(5) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P5_Msk (_U_(0x1) << PIO_PDR_P5_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P5(value) (PIO_PDR_P5_Msk & ((value) << PIO_PDR_P5_Pos)) +#define PIO_PDR_P6_Pos _U_(6) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P6_Msk (_U_(0x1) << PIO_PDR_P6_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P6(value) (PIO_PDR_P6_Msk & ((value) << PIO_PDR_P6_Pos)) +#define PIO_PDR_P7_Pos _U_(7) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P7_Msk (_U_(0x1) << PIO_PDR_P7_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P7(value) (PIO_PDR_P7_Msk & ((value) << PIO_PDR_P7_Pos)) +#define PIO_PDR_P8_Pos _U_(8) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P8_Msk (_U_(0x1) << PIO_PDR_P8_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P8(value) (PIO_PDR_P8_Msk & ((value) << PIO_PDR_P8_Pos)) +#define PIO_PDR_P9_Pos _U_(9) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P9_Msk (_U_(0x1) << PIO_PDR_P9_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P9(value) (PIO_PDR_P9_Msk & ((value) << PIO_PDR_P9_Pos)) +#define PIO_PDR_P10_Pos _U_(10) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P10_Msk (_U_(0x1) << PIO_PDR_P10_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P10(value) (PIO_PDR_P10_Msk & ((value) << PIO_PDR_P10_Pos)) +#define PIO_PDR_P11_Pos _U_(11) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P11_Msk (_U_(0x1) << PIO_PDR_P11_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P11(value) (PIO_PDR_P11_Msk & ((value) << PIO_PDR_P11_Pos)) +#define PIO_PDR_P12_Pos _U_(12) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P12_Msk (_U_(0x1) << PIO_PDR_P12_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P12(value) (PIO_PDR_P12_Msk & ((value) << PIO_PDR_P12_Pos)) +#define PIO_PDR_P13_Pos _U_(13) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P13_Msk (_U_(0x1) << PIO_PDR_P13_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P13(value) (PIO_PDR_P13_Msk & ((value) << PIO_PDR_P13_Pos)) +#define PIO_PDR_P14_Pos _U_(14) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P14_Msk (_U_(0x1) << PIO_PDR_P14_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P14(value) (PIO_PDR_P14_Msk & ((value) << PIO_PDR_P14_Pos)) +#define PIO_PDR_P15_Pos _U_(15) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P15_Msk (_U_(0x1) << PIO_PDR_P15_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P15(value) (PIO_PDR_P15_Msk & ((value) << PIO_PDR_P15_Pos)) +#define PIO_PDR_P16_Pos _U_(16) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P16_Msk (_U_(0x1) << PIO_PDR_P16_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P16(value) (PIO_PDR_P16_Msk & ((value) << PIO_PDR_P16_Pos)) +#define PIO_PDR_P17_Pos _U_(17) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P17_Msk (_U_(0x1) << PIO_PDR_P17_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P17(value) (PIO_PDR_P17_Msk & ((value) << PIO_PDR_P17_Pos)) +#define PIO_PDR_P18_Pos _U_(18) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P18_Msk (_U_(0x1) << PIO_PDR_P18_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P18(value) (PIO_PDR_P18_Msk & ((value) << PIO_PDR_P18_Pos)) +#define PIO_PDR_P19_Pos _U_(19) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P19_Msk (_U_(0x1) << PIO_PDR_P19_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P19(value) (PIO_PDR_P19_Msk & ((value) << PIO_PDR_P19_Pos)) +#define PIO_PDR_P20_Pos _U_(20) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P20_Msk (_U_(0x1) << PIO_PDR_P20_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P20(value) (PIO_PDR_P20_Msk & ((value) << PIO_PDR_P20_Pos)) +#define PIO_PDR_P21_Pos _U_(21) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P21_Msk (_U_(0x1) << PIO_PDR_P21_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P21(value) (PIO_PDR_P21_Msk & ((value) << PIO_PDR_P21_Pos)) +#define PIO_PDR_P22_Pos _U_(22) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P22_Msk (_U_(0x1) << PIO_PDR_P22_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P22(value) (PIO_PDR_P22_Msk & ((value) << PIO_PDR_P22_Pos)) +#define PIO_PDR_P23_Pos _U_(23) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P23_Msk (_U_(0x1) << PIO_PDR_P23_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P23(value) (PIO_PDR_P23_Msk & ((value) << PIO_PDR_P23_Pos)) +#define PIO_PDR_P24_Pos _U_(24) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P24_Msk (_U_(0x1) << PIO_PDR_P24_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P24(value) (PIO_PDR_P24_Msk & ((value) << PIO_PDR_P24_Pos)) +#define PIO_PDR_P25_Pos _U_(25) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P25_Msk (_U_(0x1) << PIO_PDR_P25_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P25(value) (PIO_PDR_P25_Msk & ((value) << PIO_PDR_P25_Pos)) +#define PIO_PDR_P26_Pos _U_(26) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P26_Msk (_U_(0x1) << PIO_PDR_P26_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P26(value) (PIO_PDR_P26_Msk & ((value) << PIO_PDR_P26_Pos)) +#define PIO_PDR_P27_Pos _U_(27) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P27_Msk (_U_(0x1) << PIO_PDR_P27_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P27(value) (PIO_PDR_P27_Msk & ((value) << PIO_PDR_P27_Pos)) +#define PIO_PDR_P28_Pos _U_(28) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P28_Msk (_U_(0x1) << PIO_PDR_P28_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P28(value) (PIO_PDR_P28_Msk & ((value) << PIO_PDR_P28_Pos)) +#define PIO_PDR_P29_Pos _U_(29) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P29_Msk (_U_(0x1) << PIO_PDR_P29_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P29(value) (PIO_PDR_P29_Msk & ((value) << PIO_PDR_P29_Pos)) +#define PIO_PDR_P30_Pos _U_(30) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P30_Msk (_U_(0x1) << PIO_PDR_P30_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P30(value) (PIO_PDR_P30_Msk & ((value) << PIO_PDR_P30_Pos)) +#define PIO_PDR_P31_Pos _U_(31) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P31_Msk (_U_(0x1) << PIO_PDR_P31_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P31(value) (PIO_PDR_P31_Msk & ((value) << PIO_PDR_P31_Pos)) +#define PIO_PDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDR) Register Mask */ + +#define PIO_PDR_P_Pos _U_(0) /**< (PIO_PDR Position) PIO Disable */ +#define PIO_PDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDR_P_Pos) /**< (PIO_PDR Mask) P */ +#define PIO_PDR_P(value) (PIO_PDR_P_Msk & ((value) << PIO_PDR_P_Pos)) + +/* -------- PIO_PSR : (PIO Offset: 0x08) ( R/ 32) PIO Status Register -------- */ +#define PIO_PSR_P0_Pos _U_(0) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P0_Msk (_U_(0x1) << PIO_PSR_P0_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P0(value) (PIO_PSR_P0_Msk & ((value) << PIO_PSR_P0_Pos)) +#define PIO_PSR_P1_Pos _U_(1) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P1_Msk (_U_(0x1) << PIO_PSR_P1_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P1(value) (PIO_PSR_P1_Msk & ((value) << PIO_PSR_P1_Pos)) +#define PIO_PSR_P2_Pos _U_(2) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P2_Msk (_U_(0x1) << PIO_PSR_P2_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P2(value) (PIO_PSR_P2_Msk & ((value) << PIO_PSR_P2_Pos)) +#define PIO_PSR_P3_Pos _U_(3) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P3_Msk (_U_(0x1) << PIO_PSR_P3_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P3(value) (PIO_PSR_P3_Msk & ((value) << PIO_PSR_P3_Pos)) +#define PIO_PSR_P4_Pos _U_(4) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P4_Msk (_U_(0x1) << PIO_PSR_P4_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P4(value) (PIO_PSR_P4_Msk & ((value) << PIO_PSR_P4_Pos)) +#define PIO_PSR_P5_Pos _U_(5) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P5_Msk (_U_(0x1) << PIO_PSR_P5_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P5(value) (PIO_PSR_P5_Msk & ((value) << PIO_PSR_P5_Pos)) +#define PIO_PSR_P6_Pos _U_(6) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P6_Msk (_U_(0x1) << PIO_PSR_P6_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P6(value) (PIO_PSR_P6_Msk & ((value) << PIO_PSR_P6_Pos)) +#define PIO_PSR_P7_Pos _U_(7) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P7_Msk (_U_(0x1) << PIO_PSR_P7_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P7(value) (PIO_PSR_P7_Msk & ((value) << PIO_PSR_P7_Pos)) +#define PIO_PSR_P8_Pos _U_(8) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P8_Msk (_U_(0x1) << PIO_PSR_P8_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P8(value) (PIO_PSR_P8_Msk & ((value) << PIO_PSR_P8_Pos)) +#define PIO_PSR_P9_Pos _U_(9) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P9_Msk (_U_(0x1) << PIO_PSR_P9_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P9(value) (PIO_PSR_P9_Msk & ((value) << PIO_PSR_P9_Pos)) +#define PIO_PSR_P10_Pos _U_(10) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P10_Msk (_U_(0x1) << PIO_PSR_P10_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P10(value) (PIO_PSR_P10_Msk & ((value) << PIO_PSR_P10_Pos)) +#define PIO_PSR_P11_Pos _U_(11) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P11_Msk (_U_(0x1) << PIO_PSR_P11_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P11(value) (PIO_PSR_P11_Msk & ((value) << PIO_PSR_P11_Pos)) +#define PIO_PSR_P12_Pos _U_(12) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P12_Msk (_U_(0x1) << PIO_PSR_P12_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P12(value) (PIO_PSR_P12_Msk & ((value) << PIO_PSR_P12_Pos)) +#define PIO_PSR_P13_Pos _U_(13) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P13_Msk (_U_(0x1) << PIO_PSR_P13_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P13(value) (PIO_PSR_P13_Msk & ((value) << PIO_PSR_P13_Pos)) +#define PIO_PSR_P14_Pos _U_(14) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P14_Msk (_U_(0x1) << PIO_PSR_P14_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P14(value) (PIO_PSR_P14_Msk & ((value) << PIO_PSR_P14_Pos)) +#define PIO_PSR_P15_Pos _U_(15) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P15_Msk (_U_(0x1) << PIO_PSR_P15_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P15(value) (PIO_PSR_P15_Msk & ((value) << PIO_PSR_P15_Pos)) +#define PIO_PSR_P16_Pos _U_(16) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P16_Msk (_U_(0x1) << PIO_PSR_P16_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P16(value) (PIO_PSR_P16_Msk & ((value) << PIO_PSR_P16_Pos)) +#define PIO_PSR_P17_Pos _U_(17) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P17_Msk (_U_(0x1) << PIO_PSR_P17_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P17(value) (PIO_PSR_P17_Msk & ((value) << PIO_PSR_P17_Pos)) +#define PIO_PSR_P18_Pos _U_(18) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P18_Msk (_U_(0x1) << PIO_PSR_P18_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P18(value) (PIO_PSR_P18_Msk & ((value) << PIO_PSR_P18_Pos)) +#define PIO_PSR_P19_Pos _U_(19) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P19_Msk (_U_(0x1) << PIO_PSR_P19_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P19(value) (PIO_PSR_P19_Msk & ((value) << PIO_PSR_P19_Pos)) +#define PIO_PSR_P20_Pos _U_(20) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P20_Msk (_U_(0x1) << PIO_PSR_P20_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P20(value) (PIO_PSR_P20_Msk & ((value) << PIO_PSR_P20_Pos)) +#define PIO_PSR_P21_Pos _U_(21) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P21_Msk (_U_(0x1) << PIO_PSR_P21_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P21(value) (PIO_PSR_P21_Msk & ((value) << PIO_PSR_P21_Pos)) +#define PIO_PSR_P22_Pos _U_(22) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P22_Msk (_U_(0x1) << PIO_PSR_P22_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P22(value) (PIO_PSR_P22_Msk & ((value) << PIO_PSR_P22_Pos)) +#define PIO_PSR_P23_Pos _U_(23) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P23_Msk (_U_(0x1) << PIO_PSR_P23_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P23(value) (PIO_PSR_P23_Msk & ((value) << PIO_PSR_P23_Pos)) +#define PIO_PSR_P24_Pos _U_(24) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P24_Msk (_U_(0x1) << PIO_PSR_P24_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P24(value) (PIO_PSR_P24_Msk & ((value) << PIO_PSR_P24_Pos)) +#define PIO_PSR_P25_Pos _U_(25) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P25_Msk (_U_(0x1) << PIO_PSR_P25_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P25(value) (PIO_PSR_P25_Msk & ((value) << PIO_PSR_P25_Pos)) +#define PIO_PSR_P26_Pos _U_(26) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P26_Msk (_U_(0x1) << PIO_PSR_P26_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P26(value) (PIO_PSR_P26_Msk & ((value) << PIO_PSR_P26_Pos)) +#define PIO_PSR_P27_Pos _U_(27) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P27_Msk (_U_(0x1) << PIO_PSR_P27_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P27(value) (PIO_PSR_P27_Msk & ((value) << PIO_PSR_P27_Pos)) +#define PIO_PSR_P28_Pos _U_(28) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P28_Msk (_U_(0x1) << PIO_PSR_P28_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P28(value) (PIO_PSR_P28_Msk & ((value) << PIO_PSR_P28_Pos)) +#define PIO_PSR_P29_Pos _U_(29) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P29_Msk (_U_(0x1) << PIO_PSR_P29_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P29(value) (PIO_PSR_P29_Msk & ((value) << PIO_PSR_P29_Pos)) +#define PIO_PSR_P30_Pos _U_(30) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P30_Msk (_U_(0x1) << PIO_PSR_P30_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P30(value) (PIO_PSR_P30_Msk & ((value) << PIO_PSR_P30_Pos)) +#define PIO_PSR_P31_Pos _U_(31) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P31_Msk (_U_(0x1) << PIO_PSR_P31_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P31(value) (PIO_PSR_P31_Msk & ((value) << PIO_PSR_P31_Pos)) +#define PIO_PSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PSR) Register Mask */ + +#define PIO_PSR_P_Pos _U_(0) /**< (PIO_PSR Position) PIO Status */ +#define PIO_PSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PSR_P_Pos) /**< (PIO_PSR Mask) P */ +#define PIO_PSR_P(value) (PIO_PSR_P_Msk & ((value) << PIO_PSR_P_Pos)) + +/* -------- PIO_OER : (PIO Offset: 0x10) ( /W 32) Output Enable Register -------- */ +#define PIO_OER_P0_Pos _U_(0) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P0_Msk (_U_(0x1) << PIO_OER_P0_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P0(value) (PIO_OER_P0_Msk & ((value) << PIO_OER_P0_Pos)) +#define PIO_OER_P1_Pos _U_(1) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P1_Msk (_U_(0x1) << PIO_OER_P1_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P1(value) (PIO_OER_P1_Msk & ((value) << PIO_OER_P1_Pos)) +#define PIO_OER_P2_Pos _U_(2) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P2_Msk (_U_(0x1) << PIO_OER_P2_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P2(value) (PIO_OER_P2_Msk & ((value) << PIO_OER_P2_Pos)) +#define PIO_OER_P3_Pos _U_(3) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P3_Msk (_U_(0x1) << PIO_OER_P3_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P3(value) (PIO_OER_P3_Msk & ((value) << PIO_OER_P3_Pos)) +#define PIO_OER_P4_Pos _U_(4) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P4_Msk (_U_(0x1) << PIO_OER_P4_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P4(value) (PIO_OER_P4_Msk & ((value) << PIO_OER_P4_Pos)) +#define PIO_OER_P5_Pos _U_(5) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P5_Msk (_U_(0x1) << PIO_OER_P5_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P5(value) (PIO_OER_P5_Msk & ((value) << PIO_OER_P5_Pos)) +#define PIO_OER_P6_Pos _U_(6) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P6_Msk (_U_(0x1) << PIO_OER_P6_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P6(value) (PIO_OER_P6_Msk & ((value) << PIO_OER_P6_Pos)) +#define PIO_OER_P7_Pos _U_(7) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P7_Msk (_U_(0x1) << PIO_OER_P7_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P7(value) (PIO_OER_P7_Msk & ((value) << PIO_OER_P7_Pos)) +#define PIO_OER_P8_Pos _U_(8) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P8_Msk (_U_(0x1) << PIO_OER_P8_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P8(value) (PIO_OER_P8_Msk & ((value) << PIO_OER_P8_Pos)) +#define PIO_OER_P9_Pos _U_(9) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P9_Msk (_U_(0x1) << PIO_OER_P9_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P9(value) (PIO_OER_P9_Msk & ((value) << PIO_OER_P9_Pos)) +#define PIO_OER_P10_Pos _U_(10) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P10_Msk (_U_(0x1) << PIO_OER_P10_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P10(value) (PIO_OER_P10_Msk & ((value) << PIO_OER_P10_Pos)) +#define PIO_OER_P11_Pos _U_(11) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P11_Msk (_U_(0x1) << PIO_OER_P11_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P11(value) (PIO_OER_P11_Msk & ((value) << PIO_OER_P11_Pos)) +#define PIO_OER_P12_Pos _U_(12) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P12_Msk (_U_(0x1) << PIO_OER_P12_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P12(value) (PIO_OER_P12_Msk & ((value) << PIO_OER_P12_Pos)) +#define PIO_OER_P13_Pos _U_(13) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P13_Msk (_U_(0x1) << PIO_OER_P13_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P13(value) (PIO_OER_P13_Msk & ((value) << PIO_OER_P13_Pos)) +#define PIO_OER_P14_Pos _U_(14) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P14_Msk (_U_(0x1) << PIO_OER_P14_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P14(value) (PIO_OER_P14_Msk & ((value) << PIO_OER_P14_Pos)) +#define PIO_OER_P15_Pos _U_(15) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P15_Msk (_U_(0x1) << PIO_OER_P15_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P15(value) (PIO_OER_P15_Msk & ((value) << PIO_OER_P15_Pos)) +#define PIO_OER_P16_Pos _U_(16) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P16_Msk (_U_(0x1) << PIO_OER_P16_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P16(value) (PIO_OER_P16_Msk & ((value) << PIO_OER_P16_Pos)) +#define PIO_OER_P17_Pos _U_(17) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P17_Msk (_U_(0x1) << PIO_OER_P17_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P17(value) (PIO_OER_P17_Msk & ((value) << PIO_OER_P17_Pos)) +#define PIO_OER_P18_Pos _U_(18) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P18_Msk (_U_(0x1) << PIO_OER_P18_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P18(value) (PIO_OER_P18_Msk & ((value) << PIO_OER_P18_Pos)) +#define PIO_OER_P19_Pos _U_(19) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P19_Msk (_U_(0x1) << PIO_OER_P19_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P19(value) (PIO_OER_P19_Msk & ((value) << PIO_OER_P19_Pos)) +#define PIO_OER_P20_Pos _U_(20) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P20_Msk (_U_(0x1) << PIO_OER_P20_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P20(value) (PIO_OER_P20_Msk & ((value) << PIO_OER_P20_Pos)) +#define PIO_OER_P21_Pos _U_(21) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P21_Msk (_U_(0x1) << PIO_OER_P21_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P21(value) (PIO_OER_P21_Msk & ((value) << PIO_OER_P21_Pos)) +#define PIO_OER_P22_Pos _U_(22) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P22_Msk (_U_(0x1) << PIO_OER_P22_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P22(value) (PIO_OER_P22_Msk & ((value) << PIO_OER_P22_Pos)) +#define PIO_OER_P23_Pos _U_(23) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P23_Msk (_U_(0x1) << PIO_OER_P23_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P23(value) (PIO_OER_P23_Msk & ((value) << PIO_OER_P23_Pos)) +#define PIO_OER_P24_Pos _U_(24) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P24_Msk (_U_(0x1) << PIO_OER_P24_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P24(value) (PIO_OER_P24_Msk & ((value) << PIO_OER_P24_Pos)) +#define PIO_OER_P25_Pos _U_(25) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P25_Msk (_U_(0x1) << PIO_OER_P25_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P25(value) (PIO_OER_P25_Msk & ((value) << PIO_OER_P25_Pos)) +#define PIO_OER_P26_Pos _U_(26) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P26_Msk (_U_(0x1) << PIO_OER_P26_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P26(value) (PIO_OER_P26_Msk & ((value) << PIO_OER_P26_Pos)) +#define PIO_OER_P27_Pos _U_(27) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P27_Msk (_U_(0x1) << PIO_OER_P27_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P27(value) (PIO_OER_P27_Msk & ((value) << PIO_OER_P27_Pos)) +#define PIO_OER_P28_Pos _U_(28) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P28_Msk (_U_(0x1) << PIO_OER_P28_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P28(value) (PIO_OER_P28_Msk & ((value) << PIO_OER_P28_Pos)) +#define PIO_OER_P29_Pos _U_(29) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P29_Msk (_U_(0x1) << PIO_OER_P29_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P29(value) (PIO_OER_P29_Msk & ((value) << PIO_OER_P29_Pos)) +#define PIO_OER_P30_Pos _U_(30) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P30_Msk (_U_(0x1) << PIO_OER_P30_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P30(value) (PIO_OER_P30_Msk & ((value) << PIO_OER_P30_Pos)) +#define PIO_OER_P31_Pos _U_(31) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P31_Msk (_U_(0x1) << PIO_OER_P31_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P31(value) (PIO_OER_P31_Msk & ((value) << PIO_OER_P31_Pos)) +#define PIO_OER_Msk _U_(0xFFFFFFFF) /**< (PIO_OER) Register Mask */ + +#define PIO_OER_P_Pos _U_(0) /**< (PIO_OER Position) Output Enable */ +#define PIO_OER_P_Msk (_U_(0xFFFFFFFF) << PIO_OER_P_Pos) /**< (PIO_OER Mask) P */ +#define PIO_OER_P(value) (PIO_OER_P_Msk & ((value) << PIO_OER_P_Pos)) + +/* -------- PIO_ODR : (PIO Offset: 0x14) ( /W 32) Output Disable Register -------- */ +#define PIO_ODR_P0_Pos _U_(0) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P0_Msk (_U_(0x1) << PIO_ODR_P0_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P0(value) (PIO_ODR_P0_Msk & ((value) << PIO_ODR_P0_Pos)) +#define PIO_ODR_P1_Pos _U_(1) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P1_Msk (_U_(0x1) << PIO_ODR_P1_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P1(value) (PIO_ODR_P1_Msk & ((value) << PIO_ODR_P1_Pos)) +#define PIO_ODR_P2_Pos _U_(2) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P2_Msk (_U_(0x1) << PIO_ODR_P2_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P2(value) (PIO_ODR_P2_Msk & ((value) << PIO_ODR_P2_Pos)) +#define PIO_ODR_P3_Pos _U_(3) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P3_Msk (_U_(0x1) << PIO_ODR_P3_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P3(value) (PIO_ODR_P3_Msk & ((value) << PIO_ODR_P3_Pos)) +#define PIO_ODR_P4_Pos _U_(4) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P4_Msk (_U_(0x1) << PIO_ODR_P4_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P4(value) (PIO_ODR_P4_Msk & ((value) << PIO_ODR_P4_Pos)) +#define PIO_ODR_P5_Pos _U_(5) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P5_Msk (_U_(0x1) << PIO_ODR_P5_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P5(value) (PIO_ODR_P5_Msk & ((value) << PIO_ODR_P5_Pos)) +#define PIO_ODR_P6_Pos _U_(6) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P6_Msk (_U_(0x1) << PIO_ODR_P6_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P6(value) (PIO_ODR_P6_Msk & ((value) << PIO_ODR_P6_Pos)) +#define PIO_ODR_P7_Pos _U_(7) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P7_Msk (_U_(0x1) << PIO_ODR_P7_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P7(value) (PIO_ODR_P7_Msk & ((value) << PIO_ODR_P7_Pos)) +#define PIO_ODR_P8_Pos _U_(8) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P8_Msk (_U_(0x1) << PIO_ODR_P8_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P8(value) (PIO_ODR_P8_Msk & ((value) << PIO_ODR_P8_Pos)) +#define PIO_ODR_P9_Pos _U_(9) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P9_Msk (_U_(0x1) << PIO_ODR_P9_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P9(value) (PIO_ODR_P9_Msk & ((value) << PIO_ODR_P9_Pos)) +#define PIO_ODR_P10_Pos _U_(10) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P10_Msk (_U_(0x1) << PIO_ODR_P10_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P10(value) (PIO_ODR_P10_Msk & ((value) << PIO_ODR_P10_Pos)) +#define PIO_ODR_P11_Pos _U_(11) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P11_Msk (_U_(0x1) << PIO_ODR_P11_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P11(value) (PIO_ODR_P11_Msk & ((value) << PIO_ODR_P11_Pos)) +#define PIO_ODR_P12_Pos _U_(12) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P12_Msk (_U_(0x1) << PIO_ODR_P12_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P12(value) (PIO_ODR_P12_Msk & ((value) << PIO_ODR_P12_Pos)) +#define PIO_ODR_P13_Pos _U_(13) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P13_Msk (_U_(0x1) << PIO_ODR_P13_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P13(value) (PIO_ODR_P13_Msk & ((value) << PIO_ODR_P13_Pos)) +#define PIO_ODR_P14_Pos _U_(14) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P14_Msk (_U_(0x1) << PIO_ODR_P14_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P14(value) (PIO_ODR_P14_Msk & ((value) << PIO_ODR_P14_Pos)) +#define PIO_ODR_P15_Pos _U_(15) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P15_Msk (_U_(0x1) << PIO_ODR_P15_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P15(value) (PIO_ODR_P15_Msk & ((value) << PIO_ODR_P15_Pos)) +#define PIO_ODR_P16_Pos _U_(16) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P16_Msk (_U_(0x1) << PIO_ODR_P16_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P16(value) (PIO_ODR_P16_Msk & ((value) << PIO_ODR_P16_Pos)) +#define PIO_ODR_P17_Pos _U_(17) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P17_Msk (_U_(0x1) << PIO_ODR_P17_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P17(value) (PIO_ODR_P17_Msk & ((value) << PIO_ODR_P17_Pos)) +#define PIO_ODR_P18_Pos _U_(18) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P18_Msk (_U_(0x1) << PIO_ODR_P18_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P18(value) (PIO_ODR_P18_Msk & ((value) << PIO_ODR_P18_Pos)) +#define PIO_ODR_P19_Pos _U_(19) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P19_Msk (_U_(0x1) << PIO_ODR_P19_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P19(value) (PIO_ODR_P19_Msk & ((value) << PIO_ODR_P19_Pos)) +#define PIO_ODR_P20_Pos _U_(20) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P20_Msk (_U_(0x1) << PIO_ODR_P20_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P20(value) (PIO_ODR_P20_Msk & ((value) << PIO_ODR_P20_Pos)) +#define PIO_ODR_P21_Pos _U_(21) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P21_Msk (_U_(0x1) << PIO_ODR_P21_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P21(value) (PIO_ODR_P21_Msk & ((value) << PIO_ODR_P21_Pos)) +#define PIO_ODR_P22_Pos _U_(22) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P22_Msk (_U_(0x1) << PIO_ODR_P22_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P22(value) (PIO_ODR_P22_Msk & ((value) << PIO_ODR_P22_Pos)) +#define PIO_ODR_P23_Pos _U_(23) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P23_Msk (_U_(0x1) << PIO_ODR_P23_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P23(value) (PIO_ODR_P23_Msk & ((value) << PIO_ODR_P23_Pos)) +#define PIO_ODR_P24_Pos _U_(24) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P24_Msk (_U_(0x1) << PIO_ODR_P24_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P24(value) (PIO_ODR_P24_Msk & ((value) << PIO_ODR_P24_Pos)) +#define PIO_ODR_P25_Pos _U_(25) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P25_Msk (_U_(0x1) << PIO_ODR_P25_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P25(value) (PIO_ODR_P25_Msk & ((value) << PIO_ODR_P25_Pos)) +#define PIO_ODR_P26_Pos _U_(26) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P26_Msk (_U_(0x1) << PIO_ODR_P26_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P26(value) (PIO_ODR_P26_Msk & ((value) << PIO_ODR_P26_Pos)) +#define PIO_ODR_P27_Pos _U_(27) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P27_Msk (_U_(0x1) << PIO_ODR_P27_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P27(value) (PIO_ODR_P27_Msk & ((value) << PIO_ODR_P27_Pos)) +#define PIO_ODR_P28_Pos _U_(28) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P28_Msk (_U_(0x1) << PIO_ODR_P28_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P28(value) (PIO_ODR_P28_Msk & ((value) << PIO_ODR_P28_Pos)) +#define PIO_ODR_P29_Pos _U_(29) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P29_Msk (_U_(0x1) << PIO_ODR_P29_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P29(value) (PIO_ODR_P29_Msk & ((value) << PIO_ODR_P29_Pos)) +#define PIO_ODR_P30_Pos _U_(30) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P30_Msk (_U_(0x1) << PIO_ODR_P30_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P30(value) (PIO_ODR_P30_Msk & ((value) << PIO_ODR_P30_Pos)) +#define PIO_ODR_P31_Pos _U_(31) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P31_Msk (_U_(0x1) << PIO_ODR_P31_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P31(value) (PIO_ODR_P31_Msk & ((value) << PIO_ODR_P31_Pos)) +#define PIO_ODR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODR) Register Mask */ + +#define PIO_ODR_P_Pos _U_(0) /**< (PIO_ODR Position) Output Disable */ +#define PIO_ODR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODR_P_Pos) /**< (PIO_ODR Mask) P */ +#define PIO_ODR_P(value) (PIO_ODR_P_Msk & ((value) << PIO_ODR_P_Pos)) + +/* -------- PIO_OSR : (PIO Offset: 0x18) ( R/ 32) Output Status Register -------- */ +#define PIO_OSR_P0_Pos _U_(0) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P0_Msk (_U_(0x1) << PIO_OSR_P0_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P0(value) (PIO_OSR_P0_Msk & ((value) << PIO_OSR_P0_Pos)) +#define PIO_OSR_P1_Pos _U_(1) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P1_Msk (_U_(0x1) << PIO_OSR_P1_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P1(value) (PIO_OSR_P1_Msk & ((value) << PIO_OSR_P1_Pos)) +#define PIO_OSR_P2_Pos _U_(2) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P2_Msk (_U_(0x1) << PIO_OSR_P2_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P2(value) (PIO_OSR_P2_Msk & ((value) << PIO_OSR_P2_Pos)) +#define PIO_OSR_P3_Pos _U_(3) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P3_Msk (_U_(0x1) << PIO_OSR_P3_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P3(value) (PIO_OSR_P3_Msk & ((value) << PIO_OSR_P3_Pos)) +#define PIO_OSR_P4_Pos _U_(4) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P4_Msk (_U_(0x1) << PIO_OSR_P4_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P4(value) (PIO_OSR_P4_Msk & ((value) << PIO_OSR_P4_Pos)) +#define PIO_OSR_P5_Pos _U_(5) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P5_Msk (_U_(0x1) << PIO_OSR_P5_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P5(value) (PIO_OSR_P5_Msk & ((value) << PIO_OSR_P5_Pos)) +#define PIO_OSR_P6_Pos _U_(6) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P6_Msk (_U_(0x1) << PIO_OSR_P6_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P6(value) (PIO_OSR_P6_Msk & ((value) << PIO_OSR_P6_Pos)) +#define PIO_OSR_P7_Pos _U_(7) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P7_Msk (_U_(0x1) << PIO_OSR_P7_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P7(value) (PIO_OSR_P7_Msk & ((value) << PIO_OSR_P7_Pos)) +#define PIO_OSR_P8_Pos _U_(8) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P8_Msk (_U_(0x1) << PIO_OSR_P8_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P8(value) (PIO_OSR_P8_Msk & ((value) << PIO_OSR_P8_Pos)) +#define PIO_OSR_P9_Pos _U_(9) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P9_Msk (_U_(0x1) << PIO_OSR_P9_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P9(value) (PIO_OSR_P9_Msk & ((value) << PIO_OSR_P9_Pos)) +#define PIO_OSR_P10_Pos _U_(10) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P10_Msk (_U_(0x1) << PIO_OSR_P10_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P10(value) (PIO_OSR_P10_Msk & ((value) << PIO_OSR_P10_Pos)) +#define PIO_OSR_P11_Pos _U_(11) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P11_Msk (_U_(0x1) << PIO_OSR_P11_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P11(value) (PIO_OSR_P11_Msk & ((value) << PIO_OSR_P11_Pos)) +#define PIO_OSR_P12_Pos _U_(12) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P12_Msk (_U_(0x1) << PIO_OSR_P12_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P12(value) (PIO_OSR_P12_Msk & ((value) << PIO_OSR_P12_Pos)) +#define PIO_OSR_P13_Pos _U_(13) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P13_Msk (_U_(0x1) << PIO_OSR_P13_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P13(value) (PIO_OSR_P13_Msk & ((value) << PIO_OSR_P13_Pos)) +#define PIO_OSR_P14_Pos _U_(14) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P14_Msk (_U_(0x1) << PIO_OSR_P14_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P14(value) (PIO_OSR_P14_Msk & ((value) << PIO_OSR_P14_Pos)) +#define PIO_OSR_P15_Pos _U_(15) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P15_Msk (_U_(0x1) << PIO_OSR_P15_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P15(value) (PIO_OSR_P15_Msk & ((value) << PIO_OSR_P15_Pos)) +#define PIO_OSR_P16_Pos _U_(16) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P16_Msk (_U_(0x1) << PIO_OSR_P16_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P16(value) (PIO_OSR_P16_Msk & ((value) << PIO_OSR_P16_Pos)) +#define PIO_OSR_P17_Pos _U_(17) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P17_Msk (_U_(0x1) << PIO_OSR_P17_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P17(value) (PIO_OSR_P17_Msk & ((value) << PIO_OSR_P17_Pos)) +#define PIO_OSR_P18_Pos _U_(18) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P18_Msk (_U_(0x1) << PIO_OSR_P18_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P18(value) (PIO_OSR_P18_Msk & ((value) << PIO_OSR_P18_Pos)) +#define PIO_OSR_P19_Pos _U_(19) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P19_Msk (_U_(0x1) << PIO_OSR_P19_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P19(value) (PIO_OSR_P19_Msk & ((value) << PIO_OSR_P19_Pos)) +#define PIO_OSR_P20_Pos _U_(20) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P20_Msk (_U_(0x1) << PIO_OSR_P20_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P20(value) (PIO_OSR_P20_Msk & ((value) << PIO_OSR_P20_Pos)) +#define PIO_OSR_P21_Pos _U_(21) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P21_Msk (_U_(0x1) << PIO_OSR_P21_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P21(value) (PIO_OSR_P21_Msk & ((value) << PIO_OSR_P21_Pos)) +#define PIO_OSR_P22_Pos _U_(22) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P22_Msk (_U_(0x1) << PIO_OSR_P22_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P22(value) (PIO_OSR_P22_Msk & ((value) << PIO_OSR_P22_Pos)) +#define PIO_OSR_P23_Pos _U_(23) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P23_Msk (_U_(0x1) << PIO_OSR_P23_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P23(value) (PIO_OSR_P23_Msk & ((value) << PIO_OSR_P23_Pos)) +#define PIO_OSR_P24_Pos _U_(24) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P24_Msk (_U_(0x1) << PIO_OSR_P24_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P24(value) (PIO_OSR_P24_Msk & ((value) << PIO_OSR_P24_Pos)) +#define PIO_OSR_P25_Pos _U_(25) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P25_Msk (_U_(0x1) << PIO_OSR_P25_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P25(value) (PIO_OSR_P25_Msk & ((value) << PIO_OSR_P25_Pos)) +#define PIO_OSR_P26_Pos _U_(26) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P26_Msk (_U_(0x1) << PIO_OSR_P26_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P26(value) (PIO_OSR_P26_Msk & ((value) << PIO_OSR_P26_Pos)) +#define PIO_OSR_P27_Pos _U_(27) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P27_Msk (_U_(0x1) << PIO_OSR_P27_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P27(value) (PIO_OSR_P27_Msk & ((value) << PIO_OSR_P27_Pos)) +#define PIO_OSR_P28_Pos _U_(28) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P28_Msk (_U_(0x1) << PIO_OSR_P28_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P28(value) (PIO_OSR_P28_Msk & ((value) << PIO_OSR_P28_Pos)) +#define PIO_OSR_P29_Pos _U_(29) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P29_Msk (_U_(0x1) << PIO_OSR_P29_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P29(value) (PIO_OSR_P29_Msk & ((value) << PIO_OSR_P29_Pos)) +#define PIO_OSR_P30_Pos _U_(30) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P30_Msk (_U_(0x1) << PIO_OSR_P30_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P30(value) (PIO_OSR_P30_Msk & ((value) << PIO_OSR_P30_Pos)) +#define PIO_OSR_P31_Pos _U_(31) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P31_Msk (_U_(0x1) << PIO_OSR_P31_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P31(value) (PIO_OSR_P31_Msk & ((value) << PIO_OSR_P31_Pos)) +#define PIO_OSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OSR) Register Mask */ + +#define PIO_OSR_P_Pos _U_(0) /**< (PIO_OSR Position) Output Status */ +#define PIO_OSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OSR_P_Pos) /**< (PIO_OSR Mask) P */ +#define PIO_OSR_P(value) (PIO_OSR_P_Msk & ((value) << PIO_OSR_P_Pos)) + +/* -------- PIO_IFER : (PIO Offset: 0x20) ( /W 32) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0_Pos _U_(0) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P0_Msk (_U_(0x1) << PIO_IFER_P0_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P0(value) (PIO_IFER_P0_Msk & ((value) << PIO_IFER_P0_Pos)) +#define PIO_IFER_P1_Pos _U_(1) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P1_Msk (_U_(0x1) << PIO_IFER_P1_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P1(value) (PIO_IFER_P1_Msk & ((value) << PIO_IFER_P1_Pos)) +#define PIO_IFER_P2_Pos _U_(2) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P2_Msk (_U_(0x1) << PIO_IFER_P2_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P2(value) (PIO_IFER_P2_Msk & ((value) << PIO_IFER_P2_Pos)) +#define PIO_IFER_P3_Pos _U_(3) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P3_Msk (_U_(0x1) << PIO_IFER_P3_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P3(value) (PIO_IFER_P3_Msk & ((value) << PIO_IFER_P3_Pos)) +#define PIO_IFER_P4_Pos _U_(4) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P4_Msk (_U_(0x1) << PIO_IFER_P4_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P4(value) (PIO_IFER_P4_Msk & ((value) << PIO_IFER_P4_Pos)) +#define PIO_IFER_P5_Pos _U_(5) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P5_Msk (_U_(0x1) << PIO_IFER_P5_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P5(value) (PIO_IFER_P5_Msk & ((value) << PIO_IFER_P5_Pos)) +#define PIO_IFER_P6_Pos _U_(6) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P6_Msk (_U_(0x1) << PIO_IFER_P6_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P6(value) (PIO_IFER_P6_Msk & ((value) << PIO_IFER_P6_Pos)) +#define PIO_IFER_P7_Pos _U_(7) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P7_Msk (_U_(0x1) << PIO_IFER_P7_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P7(value) (PIO_IFER_P7_Msk & ((value) << PIO_IFER_P7_Pos)) +#define PIO_IFER_P8_Pos _U_(8) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P8_Msk (_U_(0x1) << PIO_IFER_P8_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P8(value) (PIO_IFER_P8_Msk & ((value) << PIO_IFER_P8_Pos)) +#define PIO_IFER_P9_Pos _U_(9) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P9_Msk (_U_(0x1) << PIO_IFER_P9_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P9(value) (PIO_IFER_P9_Msk & ((value) << PIO_IFER_P9_Pos)) +#define PIO_IFER_P10_Pos _U_(10) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P10_Msk (_U_(0x1) << PIO_IFER_P10_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P10(value) (PIO_IFER_P10_Msk & ((value) << PIO_IFER_P10_Pos)) +#define PIO_IFER_P11_Pos _U_(11) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P11_Msk (_U_(0x1) << PIO_IFER_P11_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P11(value) (PIO_IFER_P11_Msk & ((value) << PIO_IFER_P11_Pos)) +#define PIO_IFER_P12_Pos _U_(12) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P12_Msk (_U_(0x1) << PIO_IFER_P12_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P12(value) (PIO_IFER_P12_Msk & ((value) << PIO_IFER_P12_Pos)) +#define PIO_IFER_P13_Pos _U_(13) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P13_Msk (_U_(0x1) << PIO_IFER_P13_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P13(value) (PIO_IFER_P13_Msk & ((value) << PIO_IFER_P13_Pos)) +#define PIO_IFER_P14_Pos _U_(14) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P14_Msk (_U_(0x1) << PIO_IFER_P14_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P14(value) (PIO_IFER_P14_Msk & ((value) << PIO_IFER_P14_Pos)) +#define PIO_IFER_P15_Pos _U_(15) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P15_Msk (_U_(0x1) << PIO_IFER_P15_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P15(value) (PIO_IFER_P15_Msk & ((value) << PIO_IFER_P15_Pos)) +#define PIO_IFER_P16_Pos _U_(16) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P16_Msk (_U_(0x1) << PIO_IFER_P16_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P16(value) (PIO_IFER_P16_Msk & ((value) << PIO_IFER_P16_Pos)) +#define PIO_IFER_P17_Pos _U_(17) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P17_Msk (_U_(0x1) << PIO_IFER_P17_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P17(value) (PIO_IFER_P17_Msk & ((value) << PIO_IFER_P17_Pos)) +#define PIO_IFER_P18_Pos _U_(18) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P18_Msk (_U_(0x1) << PIO_IFER_P18_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P18(value) (PIO_IFER_P18_Msk & ((value) << PIO_IFER_P18_Pos)) +#define PIO_IFER_P19_Pos _U_(19) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P19_Msk (_U_(0x1) << PIO_IFER_P19_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P19(value) (PIO_IFER_P19_Msk & ((value) << PIO_IFER_P19_Pos)) +#define PIO_IFER_P20_Pos _U_(20) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P20_Msk (_U_(0x1) << PIO_IFER_P20_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P20(value) (PIO_IFER_P20_Msk & ((value) << PIO_IFER_P20_Pos)) +#define PIO_IFER_P21_Pos _U_(21) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P21_Msk (_U_(0x1) << PIO_IFER_P21_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P21(value) (PIO_IFER_P21_Msk & ((value) << PIO_IFER_P21_Pos)) +#define PIO_IFER_P22_Pos _U_(22) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P22_Msk (_U_(0x1) << PIO_IFER_P22_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P22(value) (PIO_IFER_P22_Msk & ((value) << PIO_IFER_P22_Pos)) +#define PIO_IFER_P23_Pos _U_(23) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P23_Msk (_U_(0x1) << PIO_IFER_P23_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P23(value) (PIO_IFER_P23_Msk & ((value) << PIO_IFER_P23_Pos)) +#define PIO_IFER_P24_Pos _U_(24) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P24_Msk (_U_(0x1) << PIO_IFER_P24_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P24(value) (PIO_IFER_P24_Msk & ((value) << PIO_IFER_P24_Pos)) +#define PIO_IFER_P25_Pos _U_(25) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P25_Msk (_U_(0x1) << PIO_IFER_P25_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P25(value) (PIO_IFER_P25_Msk & ((value) << PIO_IFER_P25_Pos)) +#define PIO_IFER_P26_Pos _U_(26) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P26_Msk (_U_(0x1) << PIO_IFER_P26_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P26(value) (PIO_IFER_P26_Msk & ((value) << PIO_IFER_P26_Pos)) +#define PIO_IFER_P27_Pos _U_(27) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P27_Msk (_U_(0x1) << PIO_IFER_P27_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P27(value) (PIO_IFER_P27_Msk & ((value) << PIO_IFER_P27_Pos)) +#define PIO_IFER_P28_Pos _U_(28) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P28_Msk (_U_(0x1) << PIO_IFER_P28_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P28(value) (PIO_IFER_P28_Msk & ((value) << PIO_IFER_P28_Pos)) +#define PIO_IFER_P29_Pos _U_(29) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P29_Msk (_U_(0x1) << PIO_IFER_P29_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P29(value) (PIO_IFER_P29_Msk & ((value) << PIO_IFER_P29_Pos)) +#define PIO_IFER_P30_Pos _U_(30) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P30_Msk (_U_(0x1) << PIO_IFER_P30_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P30(value) (PIO_IFER_P30_Msk & ((value) << PIO_IFER_P30_Pos)) +#define PIO_IFER_P31_Pos _U_(31) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P31_Msk (_U_(0x1) << PIO_IFER_P31_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P31(value) (PIO_IFER_P31_Msk & ((value) << PIO_IFER_P31_Pos)) +#define PIO_IFER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFER) Register Mask */ + +#define PIO_IFER_P_Pos _U_(0) /**< (PIO_IFER Position) Input Filter Enable */ +#define PIO_IFER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFER_P_Pos) /**< (PIO_IFER Mask) P */ +#define PIO_IFER_P(value) (PIO_IFER_P_Msk & ((value) << PIO_IFER_P_Pos)) + +/* -------- PIO_IFDR : (PIO Offset: 0x24) ( /W 32) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0_Pos _U_(0) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P0_Msk (_U_(0x1) << PIO_IFDR_P0_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P0(value) (PIO_IFDR_P0_Msk & ((value) << PIO_IFDR_P0_Pos)) +#define PIO_IFDR_P1_Pos _U_(1) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P1_Msk (_U_(0x1) << PIO_IFDR_P1_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P1(value) (PIO_IFDR_P1_Msk & ((value) << PIO_IFDR_P1_Pos)) +#define PIO_IFDR_P2_Pos _U_(2) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P2_Msk (_U_(0x1) << PIO_IFDR_P2_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P2(value) (PIO_IFDR_P2_Msk & ((value) << PIO_IFDR_P2_Pos)) +#define PIO_IFDR_P3_Pos _U_(3) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P3_Msk (_U_(0x1) << PIO_IFDR_P3_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P3(value) (PIO_IFDR_P3_Msk & ((value) << PIO_IFDR_P3_Pos)) +#define PIO_IFDR_P4_Pos _U_(4) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P4_Msk (_U_(0x1) << PIO_IFDR_P4_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P4(value) (PIO_IFDR_P4_Msk & ((value) << PIO_IFDR_P4_Pos)) +#define PIO_IFDR_P5_Pos _U_(5) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P5_Msk (_U_(0x1) << PIO_IFDR_P5_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P5(value) (PIO_IFDR_P5_Msk & ((value) << PIO_IFDR_P5_Pos)) +#define PIO_IFDR_P6_Pos _U_(6) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P6_Msk (_U_(0x1) << PIO_IFDR_P6_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P6(value) (PIO_IFDR_P6_Msk & ((value) << PIO_IFDR_P6_Pos)) +#define PIO_IFDR_P7_Pos _U_(7) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P7_Msk (_U_(0x1) << PIO_IFDR_P7_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P7(value) (PIO_IFDR_P7_Msk & ((value) << PIO_IFDR_P7_Pos)) +#define PIO_IFDR_P8_Pos _U_(8) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P8_Msk (_U_(0x1) << PIO_IFDR_P8_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P8(value) (PIO_IFDR_P8_Msk & ((value) << PIO_IFDR_P8_Pos)) +#define PIO_IFDR_P9_Pos _U_(9) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P9_Msk (_U_(0x1) << PIO_IFDR_P9_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P9(value) (PIO_IFDR_P9_Msk & ((value) << PIO_IFDR_P9_Pos)) +#define PIO_IFDR_P10_Pos _U_(10) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P10_Msk (_U_(0x1) << PIO_IFDR_P10_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P10(value) (PIO_IFDR_P10_Msk & ((value) << PIO_IFDR_P10_Pos)) +#define PIO_IFDR_P11_Pos _U_(11) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P11_Msk (_U_(0x1) << PIO_IFDR_P11_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P11(value) (PIO_IFDR_P11_Msk & ((value) << PIO_IFDR_P11_Pos)) +#define PIO_IFDR_P12_Pos _U_(12) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P12_Msk (_U_(0x1) << PIO_IFDR_P12_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P12(value) (PIO_IFDR_P12_Msk & ((value) << PIO_IFDR_P12_Pos)) +#define PIO_IFDR_P13_Pos _U_(13) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P13_Msk (_U_(0x1) << PIO_IFDR_P13_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P13(value) (PIO_IFDR_P13_Msk & ((value) << PIO_IFDR_P13_Pos)) +#define PIO_IFDR_P14_Pos _U_(14) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P14_Msk (_U_(0x1) << PIO_IFDR_P14_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P14(value) (PIO_IFDR_P14_Msk & ((value) << PIO_IFDR_P14_Pos)) +#define PIO_IFDR_P15_Pos _U_(15) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P15_Msk (_U_(0x1) << PIO_IFDR_P15_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P15(value) (PIO_IFDR_P15_Msk & ((value) << PIO_IFDR_P15_Pos)) +#define PIO_IFDR_P16_Pos _U_(16) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P16_Msk (_U_(0x1) << PIO_IFDR_P16_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P16(value) (PIO_IFDR_P16_Msk & ((value) << PIO_IFDR_P16_Pos)) +#define PIO_IFDR_P17_Pos _U_(17) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P17_Msk (_U_(0x1) << PIO_IFDR_P17_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P17(value) (PIO_IFDR_P17_Msk & ((value) << PIO_IFDR_P17_Pos)) +#define PIO_IFDR_P18_Pos _U_(18) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P18_Msk (_U_(0x1) << PIO_IFDR_P18_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P18(value) (PIO_IFDR_P18_Msk & ((value) << PIO_IFDR_P18_Pos)) +#define PIO_IFDR_P19_Pos _U_(19) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P19_Msk (_U_(0x1) << PIO_IFDR_P19_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P19(value) (PIO_IFDR_P19_Msk & ((value) << PIO_IFDR_P19_Pos)) +#define PIO_IFDR_P20_Pos _U_(20) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P20_Msk (_U_(0x1) << PIO_IFDR_P20_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P20(value) (PIO_IFDR_P20_Msk & ((value) << PIO_IFDR_P20_Pos)) +#define PIO_IFDR_P21_Pos _U_(21) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P21_Msk (_U_(0x1) << PIO_IFDR_P21_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P21(value) (PIO_IFDR_P21_Msk & ((value) << PIO_IFDR_P21_Pos)) +#define PIO_IFDR_P22_Pos _U_(22) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P22_Msk (_U_(0x1) << PIO_IFDR_P22_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P22(value) (PIO_IFDR_P22_Msk & ((value) << PIO_IFDR_P22_Pos)) +#define PIO_IFDR_P23_Pos _U_(23) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P23_Msk (_U_(0x1) << PIO_IFDR_P23_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P23(value) (PIO_IFDR_P23_Msk & ((value) << PIO_IFDR_P23_Pos)) +#define PIO_IFDR_P24_Pos _U_(24) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P24_Msk (_U_(0x1) << PIO_IFDR_P24_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P24(value) (PIO_IFDR_P24_Msk & ((value) << PIO_IFDR_P24_Pos)) +#define PIO_IFDR_P25_Pos _U_(25) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P25_Msk (_U_(0x1) << PIO_IFDR_P25_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P25(value) (PIO_IFDR_P25_Msk & ((value) << PIO_IFDR_P25_Pos)) +#define PIO_IFDR_P26_Pos _U_(26) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P26_Msk (_U_(0x1) << PIO_IFDR_P26_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P26(value) (PIO_IFDR_P26_Msk & ((value) << PIO_IFDR_P26_Pos)) +#define PIO_IFDR_P27_Pos _U_(27) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P27_Msk (_U_(0x1) << PIO_IFDR_P27_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P27(value) (PIO_IFDR_P27_Msk & ((value) << PIO_IFDR_P27_Pos)) +#define PIO_IFDR_P28_Pos _U_(28) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P28_Msk (_U_(0x1) << PIO_IFDR_P28_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P28(value) (PIO_IFDR_P28_Msk & ((value) << PIO_IFDR_P28_Pos)) +#define PIO_IFDR_P29_Pos _U_(29) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P29_Msk (_U_(0x1) << PIO_IFDR_P29_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P29(value) (PIO_IFDR_P29_Msk & ((value) << PIO_IFDR_P29_Pos)) +#define PIO_IFDR_P30_Pos _U_(30) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P30_Msk (_U_(0x1) << PIO_IFDR_P30_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P30(value) (PIO_IFDR_P30_Msk & ((value) << PIO_IFDR_P30_Pos)) +#define PIO_IFDR_P31_Pos _U_(31) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P31_Msk (_U_(0x1) << PIO_IFDR_P31_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P31(value) (PIO_IFDR_P31_Msk & ((value) << PIO_IFDR_P31_Pos)) +#define PIO_IFDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFDR) Register Mask */ + +#define PIO_IFDR_P_Pos _U_(0) /**< (PIO_IFDR Position) Input Filter Disable */ +#define PIO_IFDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFDR_P_Pos) /**< (PIO_IFDR Mask) P */ +#define PIO_IFDR_P(value) (PIO_IFDR_P_Msk & ((value) << PIO_IFDR_P_Pos)) + +/* -------- PIO_IFSR : (PIO Offset: 0x28) ( R/ 32) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0_Pos _U_(0) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P0_Msk (_U_(0x1) << PIO_IFSR_P0_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P0(value) (PIO_IFSR_P0_Msk & ((value) << PIO_IFSR_P0_Pos)) +#define PIO_IFSR_P1_Pos _U_(1) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P1_Msk (_U_(0x1) << PIO_IFSR_P1_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P1(value) (PIO_IFSR_P1_Msk & ((value) << PIO_IFSR_P1_Pos)) +#define PIO_IFSR_P2_Pos _U_(2) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P2_Msk (_U_(0x1) << PIO_IFSR_P2_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P2(value) (PIO_IFSR_P2_Msk & ((value) << PIO_IFSR_P2_Pos)) +#define PIO_IFSR_P3_Pos _U_(3) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P3_Msk (_U_(0x1) << PIO_IFSR_P3_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P3(value) (PIO_IFSR_P3_Msk & ((value) << PIO_IFSR_P3_Pos)) +#define PIO_IFSR_P4_Pos _U_(4) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P4_Msk (_U_(0x1) << PIO_IFSR_P4_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P4(value) (PIO_IFSR_P4_Msk & ((value) << PIO_IFSR_P4_Pos)) +#define PIO_IFSR_P5_Pos _U_(5) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P5_Msk (_U_(0x1) << PIO_IFSR_P5_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P5(value) (PIO_IFSR_P5_Msk & ((value) << PIO_IFSR_P5_Pos)) +#define PIO_IFSR_P6_Pos _U_(6) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P6_Msk (_U_(0x1) << PIO_IFSR_P6_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P6(value) (PIO_IFSR_P6_Msk & ((value) << PIO_IFSR_P6_Pos)) +#define PIO_IFSR_P7_Pos _U_(7) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P7_Msk (_U_(0x1) << PIO_IFSR_P7_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P7(value) (PIO_IFSR_P7_Msk & ((value) << PIO_IFSR_P7_Pos)) +#define PIO_IFSR_P8_Pos _U_(8) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P8_Msk (_U_(0x1) << PIO_IFSR_P8_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P8(value) (PIO_IFSR_P8_Msk & ((value) << PIO_IFSR_P8_Pos)) +#define PIO_IFSR_P9_Pos _U_(9) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P9_Msk (_U_(0x1) << PIO_IFSR_P9_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P9(value) (PIO_IFSR_P9_Msk & ((value) << PIO_IFSR_P9_Pos)) +#define PIO_IFSR_P10_Pos _U_(10) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P10_Msk (_U_(0x1) << PIO_IFSR_P10_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P10(value) (PIO_IFSR_P10_Msk & ((value) << PIO_IFSR_P10_Pos)) +#define PIO_IFSR_P11_Pos _U_(11) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P11_Msk (_U_(0x1) << PIO_IFSR_P11_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P11(value) (PIO_IFSR_P11_Msk & ((value) << PIO_IFSR_P11_Pos)) +#define PIO_IFSR_P12_Pos _U_(12) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P12_Msk (_U_(0x1) << PIO_IFSR_P12_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P12(value) (PIO_IFSR_P12_Msk & ((value) << PIO_IFSR_P12_Pos)) +#define PIO_IFSR_P13_Pos _U_(13) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P13_Msk (_U_(0x1) << PIO_IFSR_P13_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P13(value) (PIO_IFSR_P13_Msk & ((value) << PIO_IFSR_P13_Pos)) +#define PIO_IFSR_P14_Pos _U_(14) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P14_Msk (_U_(0x1) << PIO_IFSR_P14_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P14(value) (PIO_IFSR_P14_Msk & ((value) << PIO_IFSR_P14_Pos)) +#define PIO_IFSR_P15_Pos _U_(15) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P15_Msk (_U_(0x1) << PIO_IFSR_P15_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P15(value) (PIO_IFSR_P15_Msk & ((value) << PIO_IFSR_P15_Pos)) +#define PIO_IFSR_P16_Pos _U_(16) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P16_Msk (_U_(0x1) << PIO_IFSR_P16_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P16(value) (PIO_IFSR_P16_Msk & ((value) << PIO_IFSR_P16_Pos)) +#define PIO_IFSR_P17_Pos _U_(17) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P17_Msk (_U_(0x1) << PIO_IFSR_P17_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P17(value) (PIO_IFSR_P17_Msk & ((value) << PIO_IFSR_P17_Pos)) +#define PIO_IFSR_P18_Pos _U_(18) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P18_Msk (_U_(0x1) << PIO_IFSR_P18_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P18(value) (PIO_IFSR_P18_Msk & ((value) << PIO_IFSR_P18_Pos)) +#define PIO_IFSR_P19_Pos _U_(19) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P19_Msk (_U_(0x1) << PIO_IFSR_P19_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P19(value) (PIO_IFSR_P19_Msk & ((value) << PIO_IFSR_P19_Pos)) +#define PIO_IFSR_P20_Pos _U_(20) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P20_Msk (_U_(0x1) << PIO_IFSR_P20_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P20(value) (PIO_IFSR_P20_Msk & ((value) << PIO_IFSR_P20_Pos)) +#define PIO_IFSR_P21_Pos _U_(21) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P21_Msk (_U_(0x1) << PIO_IFSR_P21_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P21(value) (PIO_IFSR_P21_Msk & ((value) << PIO_IFSR_P21_Pos)) +#define PIO_IFSR_P22_Pos _U_(22) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P22_Msk (_U_(0x1) << PIO_IFSR_P22_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P22(value) (PIO_IFSR_P22_Msk & ((value) << PIO_IFSR_P22_Pos)) +#define PIO_IFSR_P23_Pos _U_(23) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P23_Msk (_U_(0x1) << PIO_IFSR_P23_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P23(value) (PIO_IFSR_P23_Msk & ((value) << PIO_IFSR_P23_Pos)) +#define PIO_IFSR_P24_Pos _U_(24) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P24_Msk (_U_(0x1) << PIO_IFSR_P24_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P24(value) (PIO_IFSR_P24_Msk & ((value) << PIO_IFSR_P24_Pos)) +#define PIO_IFSR_P25_Pos _U_(25) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P25_Msk (_U_(0x1) << PIO_IFSR_P25_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P25(value) (PIO_IFSR_P25_Msk & ((value) << PIO_IFSR_P25_Pos)) +#define PIO_IFSR_P26_Pos _U_(26) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P26_Msk (_U_(0x1) << PIO_IFSR_P26_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P26(value) (PIO_IFSR_P26_Msk & ((value) << PIO_IFSR_P26_Pos)) +#define PIO_IFSR_P27_Pos _U_(27) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P27_Msk (_U_(0x1) << PIO_IFSR_P27_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P27(value) (PIO_IFSR_P27_Msk & ((value) << PIO_IFSR_P27_Pos)) +#define PIO_IFSR_P28_Pos _U_(28) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P28_Msk (_U_(0x1) << PIO_IFSR_P28_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P28(value) (PIO_IFSR_P28_Msk & ((value) << PIO_IFSR_P28_Pos)) +#define PIO_IFSR_P29_Pos _U_(29) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P29_Msk (_U_(0x1) << PIO_IFSR_P29_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P29(value) (PIO_IFSR_P29_Msk & ((value) << PIO_IFSR_P29_Pos)) +#define PIO_IFSR_P30_Pos _U_(30) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P30_Msk (_U_(0x1) << PIO_IFSR_P30_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P30(value) (PIO_IFSR_P30_Msk & ((value) << PIO_IFSR_P30_Pos)) +#define PIO_IFSR_P31_Pos _U_(31) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P31_Msk (_U_(0x1) << PIO_IFSR_P31_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P31(value) (PIO_IFSR_P31_Msk & ((value) << PIO_IFSR_P31_Pos)) +#define PIO_IFSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSR) Register Mask */ + +#define PIO_IFSR_P_Pos _U_(0) /**< (PIO_IFSR Position) Input Filter Status */ +#define PIO_IFSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSR_P_Pos) /**< (PIO_IFSR Mask) P */ +#define PIO_IFSR_P(value) (PIO_IFSR_P_Msk & ((value) << PIO_IFSR_P_Pos)) + +/* -------- PIO_SODR : (PIO Offset: 0x30) ( /W 32) Set Output Data Register -------- */ +#define PIO_SODR_P0_Pos _U_(0) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P0_Msk (_U_(0x1) << PIO_SODR_P0_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P0(value) (PIO_SODR_P0_Msk & ((value) << PIO_SODR_P0_Pos)) +#define PIO_SODR_P1_Pos _U_(1) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P1_Msk (_U_(0x1) << PIO_SODR_P1_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P1(value) (PIO_SODR_P1_Msk & ((value) << PIO_SODR_P1_Pos)) +#define PIO_SODR_P2_Pos _U_(2) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P2_Msk (_U_(0x1) << PIO_SODR_P2_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P2(value) (PIO_SODR_P2_Msk & ((value) << PIO_SODR_P2_Pos)) +#define PIO_SODR_P3_Pos _U_(3) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P3_Msk (_U_(0x1) << PIO_SODR_P3_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P3(value) (PIO_SODR_P3_Msk & ((value) << PIO_SODR_P3_Pos)) +#define PIO_SODR_P4_Pos _U_(4) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P4_Msk (_U_(0x1) << PIO_SODR_P4_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P4(value) (PIO_SODR_P4_Msk & ((value) << PIO_SODR_P4_Pos)) +#define PIO_SODR_P5_Pos _U_(5) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P5_Msk (_U_(0x1) << PIO_SODR_P5_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P5(value) (PIO_SODR_P5_Msk & ((value) << PIO_SODR_P5_Pos)) +#define PIO_SODR_P6_Pos _U_(6) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P6_Msk (_U_(0x1) << PIO_SODR_P6_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P6(value) (PIO_SODR_P6_Msk & ((value) << PIO_SODR_P6_Pos)) +#define PIO_SODR_P7_Pos _U_(7) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P7_Msk (_U_(0x1) << PIO_SODR_P7_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P7(value) (PIO_SODR_P7_Msk & ((value) << PIO_SODR_P7_Pos)) +#define PIO_SODR_P8_Pos _U_(8) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P8_Msk (_U_(0x1) << PIO_SODR_P8_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P8(value) (PIO_SODR_P8_Msk & ((value) << PIO_SODR_P8_Pos)) +#define PIO_SODR_P9_Pos _U_(9) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P9_Msk (_U_(0x1) << PIO_SODR_P9_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P9(value) (PIO_SODR_P9_Msk & ((value) << PIO_SODR_P9_Pos)) +#define PIO_SODR_P10_Pos _U_(10) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P10_Msk (_U_(0x1) << PIO_SODR_P10_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P10(value) (PIO_SODR_P10_Msk & ((value) << PIO_SODR_P10_Pos)) +#define PIO_SODR_P11_Pos _U_(11) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P11_Msk (_U_(0x1) << PIO_SODR_P11_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P11(value) (PIO_SODR_P11_Msk & ((value) << PIO_SODR_P11_Pos)) +#define PIO_SODR_P12_Pos _U_(12) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P12_Msk (_U_(0x1) << PIO_SODR_P12_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P12(value) (PIO_SODR_P12_Msk & ((value) << PIO_SODR_P12_Pos)) +#define PIO_SODR_P13_Pos _U_(13) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P13_Msk (_U_(0x1) << PIO_SODR_P13_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P13(value) (PIO_SODR_P13_Msk & ((value) << PIO_SODR_P13_Pos)) +#define PIO_SODR_P14_Pos _U_(14) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P14_Msk (_U_(0x1) << PIO_SODR_P14_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P14(value) (PIO_SODR_P14_Msk & ((value) << PIO_SODR_P14_Pos)) +#define PIO_SODR_P15_Pos _U_(15) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P15_Msk (_U_(0x1) << PIO_SODR_P15_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P15(value) (PIO_SODR_P15_Msk & ((value) << PIO_SODR_P15_Pos)) +#define PIO_SODR_P16_Pos _U_(16) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P16_Msk (_U_(0x1) << PIO_SODR_P16_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P16(value) (PIO_SODR_P16_Msk & ((value) << PIO_SODR_P16_Pos)) +#define PIO_SODR_P17_Pos _U_(17) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P17_Msk (_U_(0x1) << PIO_SODR_P17_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P17(value) (PIO_SODR_P17_Msk & ((value) << PIO_SODR_P17_Pos)) +#define PIO_SODR_P18_Pos _U_(18) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P18_Msk (_U_(0x1) << PIO_SODR_P18_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P18(value) (PIO_SODR_P18_Msk & ((value) << PIO_SODR_P18_Pos)) +#define PIO_SODR_P19_Pos _U_(19) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P19_Msk (_U_(0x1) << PIO_SODR_P19_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P19(value) (PIO_SODR_P19_Msk & ((value) << PIO_SODR_P19_Pos)) +#define PIO_SODR_P20_Pos _U_(20) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P20_Msk (_U_(0x1) << PIO_SODR_P20_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P20(value) (PIO_SODR_P20_Msk & ((value) << PIO_SODR_P20_Pos)) +#define PIO_SODR_P21_Pos _U_(21) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P21_Msk (_U_(0x1) << PIO_SODR_P21_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P21(value) (PIO_SODR_P21_Msk & ((value) << PIO_SODR_P21_Pos)) +#define PIO_SODR_P22_Pos _U_(22) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P22_Msk (_U_(0x1) << PIO_SODR_P22_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P22(value) (PIO_SODR_P22_Msk & ((value) << PIO_SODR_P22_Pos)) +#define PIO_SODR_P23_Pos _U_(23) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P23_Msk (_U_(0x1) << PIO_SODR_P23_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P23(value) (PIO_SODR_P23_Msk & ((value) << PIO_SODR_P23_Pos)) +#define PIO_SODR_P24_Pos _U_(24) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P24_Msk (_U_(0x1) << PIO_SODR_P24_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P24(value) (PIO_SODR_P24_Msk & ((value) << PIO_SODR_P24_Pos)) +#define PIO_SODR_P25_Pos _U_(25) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P25_Msk (_U_(0x1) << PIO_SODR_P25_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P25(value) (PIO_SODR_P25_Msk & ((value) << PIO_SODR_P25_Pos)) +#define PIO_SODR_P26_Pos _U_(26) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P26_Msk (_U_(0x1) << PIO_SODR_P26_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P26(value) (PIO_SODR_P26_Msk & ((value) << PIO_SODR_P26_Pos)) +#define PIO_SODR_P27_Pos _U_(27) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P27_Msk (_U_(0x1) << PIO_SODR_P27_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P27(value) (PIO_SODR_P27_Msk & ((value) << PIO_SODR_P27_Pos)) +#define PIO_SODR_P28_Pos _U_(28) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P28_Msk (_U_(0x1) << PIO_SODR_P28_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P28(value) (PIO_SODR_P28_Msk & ((value) << PIO_SODR_P28_Pos)) +#define PIO_SODR_P29_Pos _U_(29) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P29_Msk (_U_(0x1) << PIO_SODR_P29_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P29(value) (PIO_SODR_P29_Msk & ((value) << PIO_SODR_P29_Pos)) +#define PIO_SODR_P30_Pos _U_(30) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P30_Msk (_U_(0x1) << PIO_SODR_P30_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P30(value) (PIO_SODR_P30_Msk & ((value) << PIO_SODR_P30_Pos)) +#define PIO_SODR_P31_Pos _U_(31) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P31_Msk (_U_(0x1) << PIO_SODR_P31_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P31(value) (PIO_SODR_P31_Msk & ((value) << PIO_SODR_P31_Pos)) +#define PIO_SODR_Msk _U_(0xFFFFFFFF) /**< (PIO_SODR) Register Mask */ + +#define PIO_SODR_P_Pos _U_(0) /**< (PIO_SODR Position) Set Output Data */ +#define PIO_SODR_P_Msk (_U_(0xFFFFFFFF) << PIO_SODR_P_Pos) /**< (PIO_SODR Mask) P */ +#define PIO_SODR_P(value) (PIO_SODR_P_Msk & ((value) << PIO_SODR_P_Pos)) + +/* -------- PIO_CODR : (PIO Offset: 0x34) ( /W 32) Clear Output Data Register -------- */ +#define PIO_CODR_P0_Pos _U_(0) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P0_Msk (_U_(0x1) << PIO_CODR_P0_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P0(value) (PIO_CODR_P0_Msk & ((value) << PIO_CODR_P0_Pos)) +#define PIO_CODR_P1_Pos _U_(1) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P1_Msk (_U_(0x1) << PIO_CODR_P1_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P1(value) (PIO_CODR_P1_Msk & ((value) << PIO_CODR_P1_Pos)) +#define PIO_CODR_P2_Pos _U_(2) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P2_Msk (_U_(0x1) << PIO_CODR_P2_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P2(value) (PIO_CODR_P2_Msk & ((value) << PIO_CODR_P2_Pos)) +#define PIO_CODR_P3_Pos _U_(3) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P3_Msk (_U_(0x1) << PIO_CODR_P3_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P3(value) (PIO_CODR_P3_Msk & ((value) << PIO_CODR_P3_Pos)) +#define PIO_CODR_P4_Pos _U_(4) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P4_Msk (_U_(0x1) << PIO_CODR_P4_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P4(value) (PIO_CODR_P4_Msk & ((value) << PIO_CODR_P4_Pos)) +#define PIO_CODR_P5_Pos _U_(5) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P5_Msk (_U_(0x1) << PIO_CODR_P5_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P5(value) (PIO_CODR_P5_Msk & ((value) << PIO_CODR_P5_Pos)) +#define PIO_CODR_P6_Pos _U_(6) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P6_Msk (_U_(0x1) << PIO_CODR_P6_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P6(value) (PIO_CODR_P6_Msk & ((value) << PIO_CODR_P6_Pos)) +#define PIO_CODR_P7_Pos _U_(7) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P7_Msk (_U_(0x1) << PIO_CODR_P7_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P7(value) (PIO_CODR_P7_Msk & ((value) << PIO_CODR_P7_Pos)) +#define PIO_CODR_P8_Pos _U_(8) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P8_Msk (_U_(0x1) << PIO_CODR_P8_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P8(value) (PIO_CODR_P8_Msk & ((value) << PIO_CODR_P8_Pos)) +#define PIO_CODR_P9_Pos _U_(9) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P9_Msk (_U_(0x1) << PIO_CODR_P9_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P9(value) (PIO_CODR_P9_Msk & ((value) << PIO_CODR_P9_Pos)) +#define PIO_CODR_P10_Pos _U_(10) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P10_Msk (_U_(0x1) << PIO_CODR_P10_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P10(value) (PIO_CODR_P10_Msk & ((value) << PIO_CODR_P10_Pos)) +#define PIO_CODR_P11_Pos _U_(11) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P11_Msk (_U_(0x1) << PIO_CODR_P11_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P11(value) (PIO_CODR_P11_Msk & ((value) << PIO_CODR_P11_Pos)) +#define PIO_CODR_P12_Pos _U_(12) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P12_Msk (_U_(0x1) << PIO_CODR_P12_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P12(value) (PIO_CODR_P12_Msk & ((value) << PIO_CODR_P12_Pos)) +#define PIO_CODR_P13_Pos _U_(13) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P13_Msk (_U_(0x1) << PIO_CODR_P13_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P13(value) (PIO_CODR_P13_Msk & ((value) << PIO_CODR_P13_Pos)) +#define PIO_CODR_P14_Pos _U_(14) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P14_Msk (_U_(0x1) << PIO_CODR_P14_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P14(value) (PIO_CODR_P14_Msk & ((value) << PIO_CODR_P14_Pos)) +#define PIO_CODR_P15_Pos _U_(15) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P15_Msk (_U_(0x1) << PIO_CODR_P15_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P15(value) (PIO_CODR_P15_Msk & ((value) << PIO_CODR_P15_Pos)) +#define PIO_CODR_P16_Pos _U_(16) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P16_Msk (_U_(0x1) << PIO_CODR_P16_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P16(value) (PIO_CODR_P16_Msk & ((value) << PIO_CODR_P16_Pos)) +#define PIO_CODR_P17_Pos _U_(17) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P17_Msk (_U_(0x1) << PIO_CODR_P17_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P17(value) (PIO_CODR_P17_Msk & ((value) << PIO_CODR_P17_Pos)) +#define PIO_CODR_P18_Pos _U_(18) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P18_Msk (_U_(0x1) << PIO_CODR_P18_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P18(value) (PIO_CODR_P18_Msk & ((value) << PIO_CODR_P18_Pos)) +#define PIO_CODR_P19_Pos _U_(19) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P19_Msk (_U_(0x1) << PIO_CODR_P19_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P19(value) (PIO_CODR_P19_Msk & ((value) << PIO_CODR_P19_Pos)) +#define PIO_CODR_P20_Pos _U_(20) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P20_Msk (_U_(0x1) << PIO_CODR_P20_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P20(value) (PIO_CODR_P20_Msk & ((value) << PIO_CODR_P20_Pos)) +#define PIO_CODR_P21_Pos _U_(21) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P21_Msk (_U_(0x1) << PIO_CODR_P21_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P21(value) (PIO_CODR_P21_Msk & ((value) << PIO_CODR_P21_Pos)) +#define PIO_CODR_P22_Pos _U_(22) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P22_Msk (_U_(0x1) << PIO_CODR_P22_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P22(value) (PIO_CODR_P22_Msk & ((value) << PIO_CODR_P22_Pos)) +#define PIO_CODR_P23_Pos _U_(23) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P23_Msk (_U_(0x1) << PIO_CODR_P23_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P23(value) (PIO_CODR_P23_Msk & ((value) << PIO_CODR_P23_Pos)) +#define PIO_CODR_P24_Pos _U_(24) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P24_Msk (_U_(0x1) << PIO_CODR_P24_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P24(value) (PIO_CODR_P24_Msk & ((value) << PIO_CODR_P24_Pos)) +#define PIO_CODR_P25_Pos _U_(25) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P25_Msk (_U_(0x1) << PIO_CODR_P25_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P25(value) (PIO_CODR_P25_Msk & ((value) << PIO_CODR_P25_Pos)) +#define PIO_CODR_P26_Pos _U_(26) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P26_Msk (_U_(0x1) << PIO_CODR_P26_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P26(value) (PIO_CODR_P26_Msk & ((value) << PIO_CODR_P26_Pos)) +#define PIO_CODR_P27_Pos _U_(27) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P27_Msk (_U_(0x1) << PIO_CODR_P27_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P27(value) (PIO_CODR_P27_Msk & ((value) << PIO_CODR_P27_Pos)) +#define PIO_CODR_P28_Pos _U_(28) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P28_Msk (_U_(0x1) << PIO_CODR_P28_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P28(value) (PIO_CODR_P28_Msk & ((value) << PIO_CODR_P28_Pos)) +#define PIO_CODR_P29_Pos _U_(29) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P29_Msk (_U_(0x1) << PIO_CODR_P29_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P29(value) (PIO_CODR_P29_Msk & ((value) << PIO_CODR_P29_Pos)) +#define PIO_CODR_P30_Pos _U_(30) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P30_Msk (_U_(0x1) << PIO_CODR_P30_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P30(value) (PIO_CODR_P30_Msk & ((value) << PIO_CODR_P30_Pos)) +#define PIO_CODR_P31_Pos _U_(31) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P31_Msk (_U_(0x1) << PIO_CODR_P31_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P31(value) (PIO_CODR_P31_Msk & ((value) << PIO_CODR_P31_Pos)) +#define PIO_CODR_Msk _U_(0xFFFFFFFF) /**< (PIO_CODR) Register Mask */ + +#define PIO_CODR_P_Pos _U_(0) /**< (PIO_CODR Position) Clear Output Data */ +#define PIO_CODR_P_Msk (_U_(0xFFFFFFFF) << PIO_CODR_P_Pos) /**< (PIO_CODR Mask) P */ +#define PIO_CODR_P(value) (PIO_CODR_P_Msk & ((value) << PIO_CODR_P_Pos)) + +/* -------- PIO_ODSR : (PIO Offset: 0x38) (R/W 32) Output Data Status Register -------- */ +#define PIO_ODSR_P0_Pos _U_(0) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P0_Msk (_U_(0x1) << PIO_ODSR_P0_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P0(value) (PIO_ODSR_P0_Msk & ((value) << PIO_ODSR_P0_Pos)) +#define PIO_ODSR_P1_Pos _U_(1) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P1_Msk (_U_(0x1) << PIO_ODSR_P1_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P1(value) (PIO_ODSR_P1_Msk & ((value) << PIO_ODSR_P1_Pos)) +#define PIO_ODSR_P2_Pos _U_(2) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P2_Msk (_U_(0x1) << PIO_ODSR_P2_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P2(value) (PIO_ODSR_P2_Msk & ((value) << PIO_ODSR_P2_Pos)) +#define PIO_ODSR_P3_Pos _U_(3) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P3_Msk (_U_(0x1) << PIO_ODSR_P3_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P3(value) (PIO_ODSR_P3_Msk & ((value) << PIO_ODSR_P3_Pos)) +#define PIO_ODSR_P4_Pos _U_(4) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P4_Msk (_U_(0x1) << PIO_ODSR_P4_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P4(value) (PIO_ODSR_P4_Msk & ((value) << PIO_ODSR_P4_Pos)) +#define PIO_ODSR_P5_Pos _U_(5) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P5_Msk (_U_(0x1) << PIO_ODSR_P5_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P5(value) (PIO_ODSR_P5_Msk & ((value) << PIO_ODSR_P5_Pos)) +#define PIO_ODSR_P6_Pos _U_(6) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P6_Msk (_U_(0x1) << PIO_ODSR_P6_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P6(value) (PIO_ODSR_P6_Msk & ((value) << PIO_ODSR_P6_Pos)) +#define PIO_ODSR_P7_Pos _U_(7) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P7_Msk (_U_(0x1) << PIO_ODSR_P7_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P7(value) (PIO_ODSR_P7_Msk & ((value) << PIO_ODSR_P7_Pos)) +#define PIO_ODSR_P8_Pos _U_(8) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P8_Msk (_U_(0x1) << PIO_ODSR_P8_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P8(value) (PIO_ODSR_P8_Msk & ((value) << PIO_ODSR_P8_Pos)) +#define PIO_ODSR_P9_Pos _U_(9) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P9_Msk (_U_(0x1) << PIO_ODSR_P9_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P9(value) (PIO_ODSR_P9_Msk & ((value) << PIO_ODSR_P9_Pos)) +#define PIO_ODSR_P10_Pos _U_(10) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P10_Msk (_U_(0x1) << PIO_ODSR_P10_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P10(value) (PIO_ODSR_P10_Msk & ((value) << PIO_ODSR_P10_Pos)) +#define PIO_ODSR_P11_Pos _U_(11) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P11_Msk (_U_(0x1) << PIO_ODSR_P11_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P11(value) (PIO_ODSR_P11_Msk & ((value) << PIO_ODSR_P11_Pos)) +#define PIO_ODSR_P12_Pos _U_(12) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P12_Msk (_U_(0x1) << PIO_ODSR_P12_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P12(value) (PIO_ODSR_P12_Msk & ((value) << PIO_ODSR_P12_Pos)) +#define PIO_ODSR_P13_Pos _U_(13) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P13_Msk (_U_(0x1) << PIO_ODSR_P13_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P13(value) (PIO_ODSR_P13_Msk & ((value) << PIO_ODSR_P13_Pos)) +#define PIO_ODSR_P14_Pos _U_(14) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P14_Msk (_U_(0x1) << PIO_ODSR_P14_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P14(value) (PIO_ODSR_P14_Msk & ((value) << PIO_ODSR_P14_Pos)) +#define PIO_ODSR_P15_Pos _U_(15) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P15_Msk (_U_(0x1) << PIO_ODSR_P15_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P15(value) (PIO_ODSR_P15_Msk & ((value) << PIO_ODSR_P15_Pos)) +#define PIO_ODSR_P16_Pos _U_(16) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P16_Msk (_U_(0x1) << PIO_ODSR_P16_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P16(value) (PIO_ODSR_P16_Msk & ((value) << PIO_ODSR_P16_Pos)) +#define PIO_ODSR_P17_Pos _U_(17) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P17_Msk (_U_(0x1) << PIO_ODSR_P17_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P17(value) (PIO_ODSR_P17_Msk & ((value) << PIO_ODSR_P17_Pos)) +#define PIO_ODSR_P18_Pos _U_(18) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P18_Msk (_U_(0x1) << PIO_ODSR_P18_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P18(value) (PIO_ODSR_P18_Msk & ((value) << PIO_ODSR_P18_Pos)) +#define PIO_ODSR_P19_Pos _U_(19) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P19_Msk (_U_(0x1) << PIO_ODSR_P19_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P19(value) (PIO_ODSR_P19_Msk & ((value) << PIO_ODSR_P19_Pos)) +#define PIO_ODSR_P20_Pos _U_(20) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P20_Msk (_U_(0x1) << PIO_ODSR_P20_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P20(value) (PIO_ODSR_P20_Msk & ((value) << PIO_ODSR_P20_Pos)) +#define PIO_ODSR_P21_Pos _U_(21) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P21_Msk (_U_(0x1) << PIO_ODSR_P21_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P21(value) (PIO_ODSR_P21_Msk & ((value) << PIO_ODSR_P21_Pos)) +#define PIO_ODSR_P22_Pos _U_(22) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P22_Msk (_U_(0x1) << PIO_ODSR_P22_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P22(value) (PIO_ODSR_P22_Msk & ((value) << PIO_ODSR_P22_Pos)) +#define PIO_ODSR_P23_Pos _U_(23) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P23_Msk (_U_(0x1) << PIO_ODSR_P23_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P23(value) (PIO_ODSR_P23_Msk & ((value) << PIO_ODSR_P23_Pos)) +#define PIO_ODSR_P24_Pos _U_(24) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P24_Msk (_U_(0x1) << PIO_ODSR_P24_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P24(value) (PIO_ODSR_P24_Msk & ((value) << PIO_ODSR_P24_Pos)) +#define PIO_ODSR_P25_Pos _U_(25) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P25_Msk (_U_(0x1) << PIO_ODSR_P25_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P25(value) (PIO_ODSR_P25_Msk & ((value) << PIO_ODSR_P25_Pos)) +#define PIO_ODSR_P26_Pos _U_(26) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P26_Msk (_U_(0x1) << PIO_ODSR_P26_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P26(value) (PIO_ODSR_P26_Msk & ((value) << PIO_ODSR_P26_Pos)) +#define PIO_ODSR_P27_Pos _U_(27) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P27_Msk (_U_(0x1) << PIO_ODSR_P27_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P27(value) (PIO_ODSR_P27_Msk & ((value) << PIO_ODSR_P27_Pos)) +#define PIO_ODSR_P28_Pos _U_(28) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P28_Msk (_U_(0x1) << PIO_ODSR_P28_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P28(value) (PIO_ODSR_P28_Msk & ((value) << PIO_ODSR_P28_Pos)) +#define PIO_ODSR_P29_Pos _U_(29) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P29_Msk (_U_(0x1) << PIO_ODSR_P29_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P29(value) (PIO_ODSR_P29_Msk & ((value) << PIO_ODSR_P29_Pos)) +#define PIO_ODSR_P30_Pos _U_(30) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P30_Msk (_U_(0x1) << PIO_ODSR_P30_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P30(value) (PIO_ODSR_P30_Msk & ((value) << PIO_ODSR_P30_Pos)) +#define PIO_ODSR_P31_Pos _U_(31) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P31_Msk (_U_(0x1) << PIO_ODSR_P31_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P31(value) (PIO_ODSR_P31_Msk & ((value) << PIO_ODSR_P31_Pos)) +#define PIO_ODSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODSR) Register Mask */ + +#define PIO_ODSR_P_Pos _U_(0) /**< (PIO_ODSR Position) Output Data Status */ +#define PIO_ODSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODSR_P_Pos) /**< (PIO_ODSR Mask) P */ +#define PIO_ODSR_P(value) (PIO_ODSR_P_Msk & ((value) << PIO_ODSR_P_Pos)) + +/* -------- PIO_PDSR : (PIO Offset: 0x3C) ( R/ 32) Pin Data Status Register -------- */ +#define PIO_PDSR_P0_Pos _U_(0) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P0_Msk (_U_(0x1) << PIO_PDSR_P0_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P0(value) (PIO_PDSR_P0_Msk & ((value) << PIO_PDSR_P0_Pos)) +#define PIO_PDSR_P1_Pos _U_(1) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P1_Msk (_U_(0x1) << PIO_PDSR_P1_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P1(value) (PIO_PDSR_P1_Msk & ((value) << PIO_PDSR_P1_Pos)) +#define PIO_PDSR_P2_Pos _U_(2) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P2_Msk (_U_(0x1) << PIO_PDSR_P2_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P2(value) (PIO_PDSR_P2_Msk & ((value) << PIO_PDSR_P2_Pos)) +#define PIO_PDSR_P3_Pos _U_(3) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P3_Msk (_U_(0x1) << PIO_PDSR_P3_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P3(value) (PIO_PDSR_P3_Msk & ((value) << PIO_PDSR_P3_Pos)) +#define PIO_PDSR_P4_Pos _U_(4) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P4_Msk (_U_(0x1) << PIO_PDSR_P4_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P4(value) (PIO_PDSR_P4_Msk & ((value) << PIO_PDSR_P4_Pos)) +#define PIO_PDSR_P5_Pos _U_(5) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P5_Msk (_U_(0x1) << PIO_PDSR_P5_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P5(value) (PIO_PDSR_P5_Msk & ((value) << PIO_PDSR_P5_Pos)) +#define PIO_PDSR_P6_Pos _U_(6) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P6_Msk (_U_(0x1) << PIO_PDSR_P6_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P6(value) (PIO_PDSR_P6_Msk & ((value) << PIO_PDSR_P6_Pos)) +#define PIO_PDSR_P7_Pos _U_(7) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P7_Msk (_U_(0x1) << PIO_PDSR_P7_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P7(value) (PIO_PDSR_P7_Msk & ((value) << PIO_PDSR_P7_Pos)) +#define PIO_PDSR_P8_Pos _U_(8) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P8_Msk (_U_(0x1) << PIO_PDSR_P8_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P8(value) (PIO_PDSR_P8_Msk & ((value) << PIO_PDSR_P8_Pos)) +#define PIO_PDSR_P9_Pos _U_(9) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P9_Msk (_U_(0x1) << PIO_PDSR_P9_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P9(value) (PIO_PDSR_P9_Msk & ((value) << PIO_PDSR_P9_Pos)) +#define PIO_PDSR_P10_Pos _U_(10) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P10_Msk (_U_(0x1) << PIO_PDSR_P10_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P10(value) (PIO_PDSR_P10_Msk & ((value) << PIO_PDSR_P10_Pos)) +#define PIO_PDSR_P11_Pos _U_(11) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P11_Msk (_U_(0x1) << PIO_PDSR_P11_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P11(value) (PIO_PDSR_P11_Msk & ((value) << PIO_PDSR_P11_Pos)) +#define PIO_PDSR_P12_Pos _U_(12) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P12_Msk (_U_(0x1) << PIO_PDSR_P12_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P12(value) (PIO_PDSR_P12_Msk & ((value) << PIO_PDSR_P12_Pos)) +#define PIO_PDSR_P13_Pos _U_(13) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P13_Msk (_U_(0x1) << PIO_PDSR_P13_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P13(value) (PIO_PDSR_P13_Msk & ((value) << PIO_PDSR_P13_Pos)) +#define PIO_PDSR_P14_Pos _U_(14) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P14_Msk (_U_(0x1) << PIO_PDSR_P14_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P14(value) (PIO_PDSR_P14_Msk & ((value) << PIO_PDSR_P14_Pos)) +#define PIO_PDSR_P15_Pos _U_(15) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P15_Msk (_U_(0x1) << PIO_PDSR_P15_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P15(value) (PIO_PDSR_P15_Msk & ((value) << PIO_PDSR_P15_Pos)) +#define PIO_PDSR_P16_Pos _U_(16) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P16_Msk (_U_(0x1) << PIO_PDSR_P16_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P16(value) (PIO_PDSR_P16_Msk & ((value) << PIO_PDSR_P16_Pos)) +#define PIO_PDSR_P17_Pos _U_(17) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P17_Msk (_U_(0x1) << PIO_PDSR_P17_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P17(value) (PIO_PDSR_P17_Msk & ((value) << PIO_PDSR_P17_Pos)) +#define PIO_PDSR_P18_Pos _U_(18) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P18_Msk (_U_(0x1) << PIO_PDSR_P18_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P18(value) (PIO_PDSR_P18_Msk & ((value) << PIO_PDSR_P18_Pos)) +#define PIO_PDSR_P19_Pos _U_(19) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P19_Msk (_U_(0x1) << PIO_PDSR_P19_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P19(value) (PIO_PDSR_P19_Msk & ((value) << PIO_PDSR_P19_Pos)) +#define PIO_PDSR_P20_Pos _U_(20) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P20_Msk (_U_(0x1) << PIO_PDSR_P20_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P20(value) (PIO_PDSR_P20_Msk & ((value) << PIO_PDSR_P20_Pos)) +#define PIO_PDSR_P21_Pos _U_(21) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P21_Msk (_U_(0x1) << PIO_PDSR_P21_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P21(value) (PIO_PDSR_P21_Msk & ((value) << PIO_PDSR_P21_Pos)) +#define PIO_PDSR_P22_Pos _U_(22) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P22_Msk (_U_(0x1) << PIO_PDSR_P22_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P22(value) (PIO_PDSR_P22_Msk & ((value) << PIO_PDSR_P22_Pos)) +#define PIO_PDSR_P23_Pos _U_(23) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P23_Msk (_U_(0x1) << PIO_PDSR_P23_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P23(value) (PIO_PDSR_P23_Msk & ((value) << PIO_PDSR_P23_Pos)) +#define PIO_PDSR_P24_Pos _U_(24) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P24_Msk (_U_(0x1) << PIO_PDSR_P24_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P24(value) (PIO_PDSR_P24_Msk & ((value) << PIO_PDSR_P24_Pos)) +#define PIO_PDSR_P25_Pos _U_(25) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P25_Msk (_U_(0x1) << PIO_PDSR_P25_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P25(value) (PIO_PDSR_P25_Msk & ((value) << PIO_PDSR_P25_Pos)) +#define PIO_PDSR_P26_Pos _U_(26) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P26_Msk (_U_(0x1) << PIO_PDSR_P26_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P26(value) (PIO_PDSR_P26_Msk & ((value) << PIO_PDSR_P26_Pos)) +#define PIO_PDSR_P27_Pos _U_(27) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P27_Msk (_U_(0x1) << PIO_PDSR_P27_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P27(value) (PIO_PDSR_P27_Msk & ((value) << PIO_PDSR_P27_Pos)) +#define PIO_PDSR_P28_Pos _U_(28) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P28_Msk (_U_(0x1) << PIO_PDSR_P28_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P28(value) (PIO_PDSR_P28_Msk & ((value) << PIO_PDSR_P28_Pos)) +#define PIO_PDSR_P29_Pos _U_(29) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P29_Msk (_U_(0x1) << PIO_PDSR_P29_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P29(value) (PIO_PDSR_P29_Msk & ((value) << PIO_PDSR_P29_Pos)) +#define PIO_PDSR_P30_Pos _U_(30) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P30_Msk (_U_(0x1) << PIO_PDSR_P30_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P30(value) (PIO_PDSR_P30_Msk & ((value) << PIO_PDSR_P30_Pos)) +#define PIO_PDSR_P31_Pos _U_(31) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P31_Msk (_U_(0x1) << PIO_PDSR_P31_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P31(value) (PIO_PDSR_P31_Msk & ((value) << PIO_PDSR_P31_Pos)) +#define PIO_PDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDSR) Register Mask */ + +#define PIO_PDSR_P_Pos _U_(0) /**< (PIO_PDSR Position) Output Data Status */ +#define PIO_PDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDSR_P_Pos) /**< (PIO_PDSR Mask) P */ +#define PIO_PDSR_P(value) (PIO_PDSR_P_Msk & ((value) << PIO_PDSR_P_Pos)) + +/* -------- PIO_IER : (PIO Offset: 0x40) ( /W 32) Interrupt Enable Register -------- */ +#define PIO_IER_P0_Pos _U_(0) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P0_Msk (_U_(0x1) << PIO_IER_P0_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P0(value) (PIO_IER_P0_Msk & ((value) << PIO_IER_P0_Pos)) +#define PIO_IER_P1_Pos _U_(1) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P1_Msk (_U_(0x1) << PIO_IER_P1_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P1(value) (PIO_IER_P1_Msk & ((value) << PIO_IER_P1_Pos)) +#define PIO_IER_P2_Pos _U_(2) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P2_Msk (_U_(0x1) << PIO_IER_P2_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P2(value) (PIO_IER_P2_Msk & ((value) << PIO_IER_P2_Pos)) +#define PIO_IER_P3_Pos _U_(3) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P3_Msk (_U_(0x1) << PIO_IER_P3_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P3(value) (PIO_IER_P3_Msk & ((value) << PIO_IER_P3_Pos)) +#define PIO_IER_P4_Pos _U_(4) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P4_Msk (_U_(0x1) << PIO_IER_P4_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P4(value) (PIO_IER_P4_Msk & ((value) << PIO_IER_P4_Pos)) +#define PIO_IER_P5_Pos _U_(5) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P5_Msk (_U_(0x1) << PIO_IER_P5_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P5(value) (PIO_IER_P5_Msk & ((value) << PIO_IER_P5_Pos)) +#define PIO_IER_P6_Pos _U_(6) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P6_Msk (_U_(0x1) << PIO_IER_P6_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P6(value) (PIO_IER_P6_Msk & ((value) << PIO_IER_P6_Pos)) +#define PIO_IER_P7_Pos _U_(7) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P7_Msk (_U_(0x1) << PIO_IER_P7_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P7(value) (PIO_IER_P7_Msk & ((value) << PIO_IER_P7_Pos)) +#define PIO_IER_P8_Pos _U_(8) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P8_Msk (_U_(0x1) << PIO_IER_P8_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P8(value) (PIO_IER_P8_Msk & ((value) << PIO_IER_P8_Pos)) +#define PIO_IER_P9_Pos _U_(9) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P9_Msk (_U_(0x1) << PIO_IER_P9_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P9(value) (PIO_IER_P9_Msk & ((value) << PIO_IER_P9_Pos)) +#define PIO_IER_P10_Pos _U_(10) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P10_Msk (_U_(0x1) << PIO_IER_P10_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P10(value) (PIO_IER_P10_Msk & ((value) << PIO_IER_P10_Pos)) +#define PIO_IER_P11_Pos _U_(11) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P11_Msk (_U_(0x1) << PIO_IER_P11_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P11(value) (PIO_IER_P11_Msk & ((value) << PIO_IER_P11_Pos)) +#define PIO_IER_P12_Pos _U_(12) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P12_Msk (_U_(0x1) << PIO_IER_P12_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P12(value) (PIO_IER_P12_Msk & ((value) << PIO_IER_P12_Pos)) +#define PIO_IER_P13_Pos _U_(13) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P13_Msk (_U_(0x1) << PIO_IER_P13_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P13(value) (PIO_IER_P13_Msk & ((value) << PIO_IER_P13_Pos)) +#define PIO_IER_P14_Pos _U_(14) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P14_Msk (_U_(0x1) << PIO_IER_P14_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P14(value) (PIO_IER_P14_Msk & ((value) << PIO_IER_P14_Pos)) +#define PIO_IER_P15_Pos _U_(15) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P15_Msk (_U_(0x1) << PIO_IER_P15_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P15(value) (PIO_IER_P15_Msk & ((value) << PIO_IER_P15_Pos)) +#define PIO_IER_P16_Pos _U_(16) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P16_Msk (_U_(0x1) << PIO_IER_P16_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P16(value) (PIO_IER_P16_Msk & ((value) << PIO_IER_P16_Pos)) +#define PIO_IER_P17_Pos _U_(17) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P17_Msk (_U_(0x1) << PIO_IER_P17_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P17(value) (PIO_IER_P17_Msk & ((value) << PIO_IER_P17_Pos)) +#define PIO_IER_P18_Pos _U_(18) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P18_Msk (_U_(0x1) << PIO_IER_P18_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P18(value) (PIO_IER_P18_Msk & ((value) << PIO_IER_P18_Pos)) +#define PIO_IER_P19_Pos _U_(19) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P19_Msk (_U_(0x1) << PIO_IER_P19_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P19(value) (PIO_IER_P19_Msk & ((value) << PIO_IER_P19_Pos)) +#define PIO_IER_P20_Pos _U_(20) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P20_Msk (_U_(0x1) << PIO_IER_P20_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P20(value) (PIO_IER_P20_Msk & ((value) << PIO_IER_P20_Pos)) +#define PIO_IER_P21_Pos _U_(21) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P21_Msk (_U_(0x1) << PIO_IER_P21_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P21(value) (PIO_IER_P21_Msk & ((value) << PIO_IER_P21_Pos)) +#define PIO_IER_P22_Pos _U_(22) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P22_Msk (_U_(0x1) << PIO_IER_P22_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P22(value) (PIO_IER_P22_Msk & ((value) << PIO_IER_P22_Pos)) +#define PIO_IER_P23_Pos _U_(23) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P23_Msk (_U_(0x1) << PIO_IER_P23_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P23(value) (PIO_IER_P23_Msk & ((value) << PIO_IER_P23_Pos)) +#define PIO_IER_P24_Pos _U_(24) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P24_Msk (_U_(0x1) << PIO_IER_P24_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P24(value) (PIO_IER_P24_Msk & ((value) << PIO_IER_P24_Pos)) +#define PIO_IER_P25_Pos _U_(25) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P25_Msk (_U_(0x1) << PIO_IER_P25_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P25(value) (PIO_IER_P25_Msk & ((value) << PIO_IER_P25_Pos)) +#define PIO_IER_P26_Pos _U_(26) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P26_Msk (_U_(0x1) << PIO_IER_P26_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P26(value) (PIO_IER_P26_Msk & ((value) << PIO_IER_P26_Pos)) +#define PIO_IER_P27_Pos _U_(27) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P27_Msk (_U_(0x1) << PIO_IER_P27_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P27(value) (PIO_IER_P27_Msk & ((value) << PIO_IER_P27_Pos)) +#define PIO_IER_P28_Pos _U_(28) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P28_Msk (_U_(0x1) << PIO_IER_P28_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P28(value) (PIO_IER_P28_Msk & ((value) << PIO_IER_P28_Pos)) +#define PIO_IER_P29_Pos _U_(29) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P29_Msk (_U_(0x1) << PIO_IER_P29_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P29(value) (PIO_IER_P29_Msk & ((value) << PIO_IER_P29_Pos)) +#define PIO_IER_P30_Pos _U_(30) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P30_Msk (_U_(0x1) << PIO_IER_P30_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P30(value) (PIO_IER_P30_Msk & ((value) << PIO_IER_P30_Pos)) +#define PIO_IER_P31_Pos _U_(31) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P31_Msk (_U_(0x1) << PIO_IER_P31_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P31(value) (PIO_IER_P31_Msk & ((value) << PIO_IER_P31_Pos)) +#define PIO_IER_Msk _U_(0xFFFFFFFF) /**< (PIO_IER) Register Mask */ + +#define PIO_IER_P_Pos _U_(0) /**< (PIO_IER Position) Input Change Interrupt Enable */ +#define PIO_IER_P_Msk (_U_(0xFFFFFFFF) << PIO_IER_P_Pos) /**< (PIO_IER Mask) P */ +#define PIO_IER_P(value) (PIO_IER_P_Msk & ((value) << PIO_IER_P_Pos)) + +/* -------- PIO_IDR : (PIO Offset: 0x44) ( /W 32) Interrupt Disable Register -------- */ +#define PIO_IDR_P0_Pos _U_(0) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P0_Msk (_U_(0x1) << PIO_IDR_P0_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P0(value) (PIO_IDR_P0_Msk & ((value) << PIO_IDR_P0_Pos)) +#define PIO_IDR_P1_Pos _U_(1) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P1_Msk (_U_(0x1) << PIO_IDR_P1_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P1(value) (PIO_IDR_P1_Msk & ((value) << PIO_IDR_P1_Pos)) +#define PIO_IDR_P2_Pos _U_(2) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P2_Msk (_U_(0x1) << PIO_IDR_P2_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P2(value) (PIO_IDR_P2_Msk & ((value) << PIO_IDR_P2_Pos)) +#define PIO_IDR_P3_Pos _U_(3) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P3_Msk (_U_(0x1) << PIO_IDR_P3_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P3(value) (PIO_IDR_P3_Msk & ((value) << PIO_IDR_P3_Pos)) +#define PIO_IDR_P4_Pos _U_(4) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P4_Msk (_U_(0x1) << PIO_IDR_P4_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P4(value) (PIO_IDR_P4_Msk & ((value) << PIO_IDR_P4_Pos)) +#define PIO_IDR_P5_Pos _U_(5) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P5_Msk (_U_(0x1) << PIO_IDR_P5_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P5(value) (PIO_IDR_P5_Msk & ((value) << PIO_IDR_P5_Pos)) +#define PIO_IDR_P6_Pos _U_(6) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P6_Msk (_U_(0x1) << PIO_IDR_P6_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P6(value) (PIO_IDR_P6_Msk & ((value) << PIO_IDR_P6_Pos)) +#define PIO_IDR_P7_Pos _U_(7) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P7_Msk (_U_(0x1) << PIO_IDR_P7_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P7(value) (PIO_IDR_P7_Msk & ((value) << PIO_IDR_P7_Pos)) +#define PIO_IDR_P8_Pos _U_(8) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P8_Msk (_U_(0x1) << PIO_IDR_P8_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P8(value) (PIO_IDR_P8_Msk & ((value) << PIO_IDR_P8_Pos)) +#define PIO_IDR_P9_Pos _U_(9) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P9_Msk (_U_(0x1) << PIO_IDR_P9_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P9(value) (PIO_IDR_P9_Msk & ((value) << PIO_IDR_P9_Pos)) +#define PIO_IDR_P10_Pos _U_(10) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P10_Msk (_U_(0x1) << PIO_IDR_P10_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P10(value) (PIO_IDR_P10_Msk & ((value) << PIO_IDR_P10_Pos)) +#define PIO_IDR_P11_Pos _U_(11) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P11_Msk (_U_(0x1) << PIO_IDR_P11_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P11(value) (PIO_IDR_P11_Msk & ((value) << PIO_IDR_P11_Pos)) +#define PIO_IDR_P12_Pos _U_(12) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P12_Msk (_U_(0x1) << PIO_IDR_P12_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P12(value) (PIO_IDR_P12_Msk & ((value) << PIO_IDR_P12_Pos)) +#define PIO_IDR_P13_Pos _U_(13) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P13_Msk (_U_(0x1) << PIO_IDR_P13_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P13(value) (PIO_IDR_P13_Msk & ((value) << PIO_IDR_P13_Pos)) +#define PIO_IDR_P14_Pos _U_(14) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P14_Msk (_U_(0x1) << PIO_IDR_P14_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P14(value) (PIO_IDR_P14_Msk & ((value) << PIO_IDR_P14_Pos)) +#define PIO_IDR_P15_Pos _U_(15) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P15_Msk (_U_(0x1) << PIO_IDR_P15_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P15(value) (PIO_IDR_P15_Msk & ((value) << PIO_IDR_P15_Pos)) +#define PIO_IDR_P16_Pos _U_(16) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P16_Msk (_U_(0x1) << PIO_IDR_P16_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P16(value) (PIO_IDR_P16_Msk & ((value) << PIO_IDR_P16_Pos)) +#define PIO_IDR_P17_Pos _U_(17) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P17_Msk (_U_(0x1) << PIO_IDR_P17_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P17(value) (PIO_IDR_P17_Msk & ((value) << PIO_IDR_P17_Pos)) +#define PIO_IDR_P18_Pos _U_(18) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P18_Msk (_U_(0x1) << PIO_IDR_P18_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P18(value) (PIO_IDR_P18_Msk & ((value) << PIO_IDR_P18_Pos)) +#define PIO_IDR_P19_Pos _U_(19) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P19_Msk (_U_(0x1) << PIO_IDR_P19_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P19(value) (PIO_IDR_P19_Msk & ((value) << PIO_IDR_P19_Pos)) +#define PIO_IDR_P20_Pos _U_(20) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P20_Msk (_U_(0x1) << PIO_IDR_P20_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P20(value) (PIO_IDR_P20_Msk & ((value) << PIO_IDR_P20_Pos)) +#define PIO_IDR_P21_Pos _U_(21) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P21_Msk (_U_(0x1) << PIO_IDR_P21_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P21(value) (PIO_IDR_P21_Msk & ((value) << PIO_IDR_P21_Pos)) +#define PIO_IDR_P22_Pos _U_(22) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P22_Msk (_U_(0x1) << PIO_IDR_P22_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P22(value) (PIO_IDR_P22_Msk & ((value) << PIO_IDR_P22_Pos)) +#define PIO_IDR_P23_Pos _U_(23) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P23_Msk (_U_(0x1) << PIO_IDR_P23_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P23(value) (PIO_IDR_P23_Msk & ((value) << PIO_IDR_P23_Pos)) +#define PIO_IDR_P24_Pos _U_(24) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P24_Msk (_U_(0x1) << PIO_IDR_P24_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P24(value) (PIO_IDR_P24_Msk & ((value) << PIO_IDR_P24_Pos)) +#define PIO_IDR_P25_Pos _U_(25) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P25_Msk (_U_(0x1) << PIO_IDR_P25_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P25(value) (PIO_IDR_P25_Msk & ((value) << PIO_IDR_P25_Pos)) +#define PIO_IDR_P26_Pos _U_(26) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P26_Msk (_U_(0x1) << PIO_IDR_P26_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P26(value) (PIO_IDR_P26_Msk & ((value) << PIO_IDR_P26_Pos)) +#define PIO_IDR_P27_Pos _U_(27) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P27_Msk (_U_(0x1) << PIO_IDR_P27_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P27(value) (PIO_IDR_P27_Msk & ((value) << PIO_IDR_P27_Pos)) +#define PIO_IDR_P28_Pos _U_(28) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P28_Msk (_U_(0x1) << PIO_IDR_P28_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P28(value) (PIO_IDR_P28_Msk & ((value) << PIO_IDR_P28_Pos)) +#define PIO_IDR_P29_Pos _U_(29) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P29_Msk (_U_(0x1) << PIO_IDR_P29_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P29(value) (PIO_IDR_P29_Msk & ((value) << PIO_IDR_P29_Pos)) +#define PIO_IDR_P30_Pos _U_(30) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P30_Msk (_U_(0x1) << PIO_IDR_P30_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P30(value) (PIO_IDR_P30_Msk & ((value) << PIO_IDR_P30_Pos)) +#define PIO_IDR_P31_Pos _U_(31) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P31_Msk (_U_(0x1) << PIO_IDR_P31_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P31(value) (PIO_IDR_P31_Msk & ((value) << PIO_IDR_P31_Pos)) +#define PIO_IDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IDR) Register Mask */ + +#define PIO_IDR_P_Pos _U_(0) /**< (PIO_IDR Position) Input Change Interrupt Disable */ +#define PIO_IDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IDR_P_Pos) /**< (PIO_IDR Mask) P */ +#define PIO_IDR_P(value) (PIO_IDR_P_Msk & ((value) << PIO_IDR_P_Pos)) + +/* -------- PIO_IMR : (PIO Offset: 0x48) ( R/ 32) Interrupt Mask Register -------- */ +#define PIO_IMR_P0_Pos _U_(0) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P0_Msk (_U_(0x1) << PIO_IMR_P0_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P0(value) (PIO_IMR_P0_Msk & ((value) << PIO_IMR_P0_Pos)) +#define PIO_IMR_P1_Pos _U_(1) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P1_Msk (_U_(0x1) << PIO_IMR_P1_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P1(value) (PIO_IMR_P1_Msk & ((value) << PIO_IMR_P1_Pos)) +#define PIO_IMR_P2_Pos _U_(2) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P2_Msk (_U_(0x1) << PIO_IMR_P2_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P2(value) (PIO_IMR_P2_Msk & ((value) << PIO_IMR_P2_Pos)) +#define PIO_IMR_P3_Pos _U_(3) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P3_Msk (_U_(0x1) << PIO_IMR_P3_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P3(value) (PIO_IMR_P3_Msk & ((value) << PIO_IMR_P3_Pos)) +#define PIO_IMR_P4_Pos _U_(4) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P4_Msk (_U_(0x1) << PIO_IMR_P4_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P4(value) (PIO_IMR_P4_Msk & ((value) << PIO_IMR_P4_Pos)) +#define PIO_IMR_P5_Pos _U_(5) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P5_Msk (_U_(0x1) << PIO_IMR_P5_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P5(value) (PIO_IMR_P5_Msk & ((value) << PIO_IMR_P5_Pos)) +#define PIO_IMR_P6_Pos _U_(6) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P6_Msk (_U_(0x1) << PIO_IMR_P6_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P6(value) (PIO_IMR_P6_Msk & ((value) << PIO_IMR_P6_Pos)) +#define PIO_IMR_P7_Pos _U_(7) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P7_Msk (_U_(0x1) << PIO_IMR_P7_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P7(value) (PIO_IMR_P7_Msk & ((value) << PIO_IMR_P7_Pos)) +#define PIO_IMR_P8_Pos _U_(8) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P8_Msk (_U_(0x1) << PIO_IMR_P8_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P8(value) (PIO_IMR_P8_Msk & ((value) << PIO_IMR_P8_Pos)) +#define PIO_IMR_P9_Pos _U_(9) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P9_Msk (_U_(0x1) << PIO_IMR_P9_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P9(value) (PIO_IMR_P9_Msk & ((value) << PIO_IMR_P9_Pos)) +#define PIO_IMR_P10_Pos _U_(10) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P10_Msk (_U_(0x1) << PIO_IMR_P10_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P10(value) (PIO_IMR_P10_Msk & ((value) << PIO_IMR_P10_Pos)) +#define PIO_IMR_P11_Pos _U_(11) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P11_Msk (_U_(0x1) << PIO_IMR_P11_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P11(value) (PIO_IMR_P11_Msk & ((value) << PIO_IMR_P11_Pos)) +#define PIO_IMR_P12_Pos _U_(12) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P12_Msk (_U_(0x1) << PIO_IMR_P12_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P12(value) (PIO_IMR_P12_Msk & ((value) << PIO_IMR_P12_Pos)) +#define PIO_IMR_P13_Pos _U_(13) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P13_Msk (_U_(0x1) << PIO_IMR_P13_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P13(value) (PIO_IMR_P13_Msk & ((value) << PIO_IMR_P13_Pos)) +#define PIO_IMR_P14_Pos _U_(14) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P14_Msk (_U_(0x1) << PIO_IMR_P14_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P14(value) (PIO_IMR_P14_Msk & ((value) << PIO_IMR_P14_Pos)) +#define PIO_IMR_P15_Pos _U_(15) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P15_Msk (_U_(0x1) << PIO_IMR_P15_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P15(value) (PIO_IMR_P15_Msk & ((value) << PIO_IMR_P15_Pos)) +#define PIO_IMR_P16_Pos _U_(16) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P16_Msk (_U_(0x1) << PIO_IMR_P16_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P16(value) (PIO_IMR_P16_Msk & ((value) << PIO_IMR_P16_Pos)) +#define PIO_IMR_P17_Pos _U_(17) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P17_Msk (_U_(0x1) << PIO_IMR_P17_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P17(value) (PIO_IMR_P17_Msk & ((value) << PIO_IMR_P17_Pos)) +#define PIO_IMR_P18_Pos _U_(18) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P18_Msk (_U_(0x1) << PIO_IMR_P18_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P18(value) (PIO_IMR_P18_Msk & ((value) << PIO_IMR_P18_Pos)) +#define PIO_IMR_P19_Pos _U_(19) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P19_Msk (_U_(0x1) << PIO_IMR_P19_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P19(value) (PIO_IMR_P19_Msk & ((value) << PIO_IMR_P19_Pos)) +#define PIO_IMR_P20_Pos _U_(20) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P20_Msk (_U_(0x1) << PIO_IMR_P20_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P20(value) (PIO_IMR_P20_Msk & ((value) << PIO_IMR_P20_Pos)) +#define PIO_IMR_P21_Pos _U_(21) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P21_Msk (_U_(0x1) << PIO_IMR_P21_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P21(value) (PIO_IMR_P21_Msk & ((value) << PIO_IMR_P21_Pos)) +#define PIO_IMR_P22_Pos _U_(22) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P22_Msk (_U_(0x1) << PIO_IMR_P22_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P22(value) (PIO_IMR_P22_Msk & ((value) << PIO_IMR_P22_Pos)) +#define PIO_IMR_P23_Pos _U_(23) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P23_Msk (_U_(0x1) << PIO_IMR_P23_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P23(value) (PIO_IMR_P23_Msk & ((value) << PIO_IMR_P23_Pos)) +#define PIO_IMR_P24_Pos _U_(24) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P24_Msk (_U_(0x1) << PIO_IMR_P24_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P24(value) (PIO_IMR_P24_Msk & ((value) << PIO_IMR_P24_Pos)) +#define PIO_IMR_P25_Pos _U_(25) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P25_Msk (_U_(0x1) << PIO_IMR_P25_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P25(value) (PIO_IMR_P25_Msk & ((value) << PIO_IMR_P25_Pos)) +#define PIO_IMR_P26_Pos _U_(26) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P26_Msk (_U_(0x1) << PIO_IMR_P26_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P26(value) (PIO_IMR_P26_Msk & ((value) << PIO_IMR_P26_Pos)) +#define PIO_IMR_P27_Pos _U_(27) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P27_Msk (_U_(0x1) << PIO_IMR_P27_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P27(value) (PIO_IMR_P27_Msk & ((value) << PIO_IMR_P27_Pos)) +#define PIO_IMR_P28_Pos _U_(28) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P28_Msk (_U_(0x1) << PIO_IMR_P28_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P28(value) (PIO_IMR_P28_Msk & ((value) << PIO_IMR_P28_Pos)) +#define PIO_IMR_P29_Pos _U_(29) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P29_Msk (_U_(0x1) << PIO_IMR_P29_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P29(value) (PIO_IMR_P29_Msk & ((value) << PIO_IMR_P29_Pos)) +#define PIO_IMR_P30_Pos _U_(30) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P30_Msk (_U_(0x1) << PIO_IMR_P30_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P30(value) (PIO_IMR_P30_Msk & ((value) << PIO_IMR_P30_Pos)) +#define PIO_IMR_P31_Pos _U_(31) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P31_Msk (_U_(0x1) << PIO_IMR_P31_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P31(value) (PIO_IMR_P31_Msk & ((value) << PIO_IMR_P31_Pos)) +#define PIO_IMR_Msk _U_(0xFFFFFFFF) /**< (PIO_IMR) Register Mask */ + +#define PIO_IMR_P_Pos _U_(0) /**< (PIO_IMR Position) Input Change Interrupt Mask */ +#define PIO_IMR_P_Msk (_U_(0xFFFFFFFF) << PIO_IMR_P_Pos) /**< (PIO_IMR Mask) P */ +#define PIO_IMR_P(value) (PIO_IMR_P_Msk & ((value) << PIO_IMR_P_Pos)) + +/* -------- PIO_ISR : (PIO Offset: 0x4C) ( R/ 32) Interrupt Status Register -------- */ +#define PIO_ISR_P0_Pos _U_(0) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P0_Msk (_U_(0x1) << PIO_ISR_P0_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P0(value) (PIO_ISR_P0_Msk & ((value) << PIO_ISR_P0_Pos)) +#define PIO_ISR_P1_Pos _U_(1) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P1_Msk (_U_(0x1) << PIO_ISR_P1_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P1(value) (PIO_ISR_P1_Msk & ((value) << PIO_ISR_P1_Pos)) +#define PIO_ISR_P2_Pos _U_(2) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P2_Msk (_U_(0x1) << PIO_ISR_P2_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P2(value) (PIO_ISR_P2_Msk & ((value) << PIO_ISR_P2_Pos)) +#define PIO_ISR_P3_Pos _U_(3) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P3_Msk (_U_(0x1) << PIO_ISR_P3_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P3(value) (PIO_ISR_P3_Msk & ((value) << PIO_ISR_P3_Pos)) +#define PIO_ISR_P4_Pos _U_(4) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P4_Msk (_U_(0x1) << PIO_ISR_P4_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P4(value) (PIO_ISR_P4_Msk & ((value) << PIO_ISR_P4_Pos)) +#define PIO_ISR_P5_Pos _U_(5) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P5_Msk (_U_(0x1) << PIO_ISR_P5_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P5(value) (PIO_ISR_P5_Msk & ((value) << PIO_ISR_P5_Pos)) +#define PIO_ISR_P6_Pos _U_(6) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P6_Msk (_U_(0x1) << PIO_ISR_P6_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P6(value) (PIO_ISR_P6_Msk & ((value) << PIO_ISR_P6_Pos)) +#define PIO_ISR_P7_Pos _U_(7) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P7_Msk (_U_(0x1) << PIO_ISR_P7_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P7(value) (PIO_ISR_P7_Msk & ((value) << PIO_ISR_P7_Pos)) +#define PIO_ISR_P8_Pos _U_(8) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P8_Msk (_U_(0x1) << PIO_ISR_P8_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P8(value) (PIO_ISR_P8_Msk & ((value) << PIO_ISR_P8_Pos)) +#define PIO_ISR_P9_Pos _U_(9) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P9_Msk (_U_(0x1) << PIO_ISR_P9_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P9(value) (PIO_ISR_P9_Msk & ((value) << PIO_ISR_P9_Pos)) +#define PIO_ISR_P10_Pos _U_(10) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P10_Msk (_U_(0x1) << PIO_ISR_P10_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P10(value) (PIO_ISR_P10_Msk & ((value) << PIO_ISR_P10_Pos)) +#define PIO_ISR_P11_Pos _U_(11) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P11_Msk (_U_(0x1) << PIO_ISR_P11_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P11(value) (PIO_ISR_P11_Msk & ((value) << PIO_ISR_P11_Pos)) +#define PIO_ISR_P12_Pos _U_(12) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P12_Msk (_U_(0x1) << PIO_ISR_P12_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P12(value) (PIO_ISR_P12_Msk & ((value) << PIO_ISR_P12_Pos)) +#define PIO_ISR_P13_Pos _U_(13) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P13_Msk (_U_(0x1) << PIO_ISR_P13_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P13(value) (PIO_ISR_P13_Msk & ((value) << PIO_ISR_P13_Pos)) +#define PIO_ISR_P14_Pos _U_(14) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P14_Msk (_U_(0x1) << PIO_ISR_P14_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P14(value) (PIO_ISR_P14_Msk & ((value) << PIO_ISR_P14_Pos)) +#define PIO_ISR_P15_Pos _U_(15) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P15_Msk (_U_(0x1) << PIO_ISR_P15_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P15(value) (PIO_ISR_P15_Msk & ((value) << PIO_ISR_P15_Pos)) +#define PIO_ISR_P16_Pos _U_(16) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P16_Msk (_U_(0x1) << PIO_ISR_P16_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P16(value) (PIO_ISR_P16_Msk & ((value) << PIO_ISR_P16_Pos)) +#define PIO_ISR_P17_Pos _U_(17) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P17_Msk (_U_(0x1) << PIO_ISR_P17_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P17(value) (PIO_ISR_P17_Msk & ((value) << PIO_ISR_P17_Pos)) +#define PIO_ISR_P18_Pos _U_(18) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P18_Msk (_U_(0x1) << PIO_ISR_P18_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P18(value) (PIO_ISR_P18_Msk & ((value) << PIO_ISR_P18_Pos)) +#define PIO_ISR_P19_Pos _U_(19) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P19_Msk (_U_(0x1) << PIO_ISR_P19_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P19(value) (PIO_ISR_P19_Msk & ((value) << PIO_ISR_P19_Pos)) +#define PIO_ISR_P20_Pos _U_(20) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P20_Msk (_U_(0x1) << PIO_ISR_P20_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P20(value) (PIO_ISR_P20_Msk & ((value) << PIO_ISR_P20_Pos)) +#define PIO_ISR_P21_Pos _U_(21) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P21_Msk (_U_(0x1) << PIO_ISR_P21_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P21(value) (PIO_ISR_P21_Msk & ((value) << PIO_ISR_P21_Pos)) +#define PIO_ISR_P22_Pos _U_(22) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P22_Msk (_U_(0x1) << PIO_ISR_P22_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P22(value) (PIO_ISR_P22_Msk & ((value) << PIO_ISR_P22_Pos)) +#define PIO_ISR_P23_Pos _U_(23) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P23_Msk (_U_(0x1) << PIO_ISR_P23_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P23(value) (PIO_ISR_P23_Msk & ((value) << PIO_ISR_P23_Pos)) +#define PIO_ISR_P24_Pos _U_(24) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P24_Msk (_U_(0x1) << PIO_ISR_P24_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P24(value) (PIO_ISR_P24_Msk & ((value) << PIO_ISR_P24_Pos)) +#define PIO_ISR_P25_Pos _U_(25) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P25_Msk (_U_(0x1) << PIO_ISR_P25_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P25(value) (PIO_ISR_P25_Msk & ((value) << PIO_ISR_P25_Pos)) +#define PIO_ISR_P26_Pos _U_(26) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P26_Msk (_U_(0x1) << PIO_ISR_P26_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P26(value) (PIO_ISR_P26_Msk & ((value) << PIO_ISR_P26_Pos)) +#define PIO_ISR_P27_Pos _U_(27) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P27_Msk (_U_(0x1) << PIO_ISR_P27_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P27(value) (PIO_ISR_P27_Msk & ((value) << PIO_ISR_P27_Pos)) +#define PIO_ISR_P28_Pos _U_(28) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P28_Msk (_U_(0x1) << PIO_ISR_P28_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P28(value) (PIO_ISR_P28_Msk & ((value) << PIO_ISR_P28_Pos)) +#define PIO_ISR_P29_Pos _U_(29) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P29_Msk (_U_(0x1) << PIO_ISR_P29_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P29(value) (PIO_ISR_P29_Msk & ((value) << PIO_ISR_P29_Pos)) +#define PIO_ISR_P30_Pos _U_(30) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P30_Msk (_U_(0x1) << PIO_ISR_P30_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P30(value) (PIO_ISR_P30_Msk & ((value) << PIO_ISR_P30_Pos)) +#define PIO_ISR_P31_Pos _U_(31) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P31_Msk (_U_(0x1) << PIO_ISR_P31_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P31(value) (PIO_ISR_P31_Msk & ((value) << PIO_ISR_P31_Pos)) +#define PIO_ISR_Msk _U_(0xFFFFFFFF) /**< (PIO_ISR) Register Mask */ + +#define PIO_ISR_P_Pos _U_(0) /**< (PIO_ISR Position) Input Change Interrupt Status */ +#define PIO_ISR_P_Msk (_U_(0xFFFFFFFF) << PIO_ISR_P_Pos) /**< (PIO_ISR Mask) P */ +#define PIO_ISR_P(value) (PIO_ISR_P_Msk & ((value) << PIO_ISR_P_Pos)) + +/* -------- PIO_MDER : (PIO Offset: 0x50) ( /W 32) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0_Pos _U_(0) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P0_Msk (_U_(0x1) << PIO_MDER_P0_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P0(value) (PIO_MDER_P0_Msk & ((value) << PIO_MDER_P0_Pos)) +#define PIO_MDER_P1_Pos _U_(1) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P1_Msk (_U_(0x1) << PIO_MDER_P1_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P1(value) (PIO_MDER_P1_Msk & ((value) << PIO_MDER_P1_Pos)) +#define PIO_MDER_P2_Pos _U_(2) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P2_Msk (_U_(0x1) << PIO_MDER_P2_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P2(value) (PIO_MDER_P2_Msk & ((value) << PIO_MDER_P2_Pos)) +#define PIO_MDER_P3_Pos _U_(3) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P3_Msk (_U_(0x1) << PIO_MDER_P3_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P3(value) (PIO_MDER_P3_Msk & ((value) << PIO_MDER_P3_Pos)) +#define PIO_MDER_P4_Pos _U_(4) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P4_Msk (_U_(0x1) << PIO_MDER_P4_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P4(value) (PIO_MDER_P4_Msk & ((value) << PIO_MDER_P4_Pos)) +#define PIO_MDER_P5_Pos _U_(5) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P5_Msk (_U_(0x1) << PIO_MDER_P5_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P5(value) (PIO_MDER_P5_Msk & ((value) << PIO_MDER_P5_Pos)) +#define PIO_MDER_P6_Pos _U_(6) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P6_Msk (_U_(0x1) << PIO_MDER_P6_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P6(value) (PIO_MDER_P6_Msk & ((value) << PIO_MDER_P6_Pos)) +#define PIO_MDER_P7_Pos _U_(7) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P7_Msk (_U_(0x1) << PIO_MDER_P7_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P7(value) (PIO_MDER_P7_Msk & ((value) << PIO_MDER_P7_Pos)) +#define PIO_MDER_P8_Pos _U_(8) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P8_Msk (_U_(0x1) << PIO_MDER_P8_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P8(value) (PIO_MDER_P8_Msk & ((value) << PIO_MDER_P8_Pos)) +#define PIO_MDER_P9_Pos _U_(9) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P9_Msk (_U_(0x1) << PIO_MDER_P9_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P9(value) (PIO_MDER_P9_Msk & ((value) << PIO_MDER_P9_Pos)) +#define PIO_MDER_P10_Pos _U_(10) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P10_Msk (_U_(0x1) << PIO_MDER_P10_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P10(value) (PIO_MDER_P10_Msk & ((value) << PIO_MDER_P10_Pos)) +#define PIO_MDER_P11_Pos _U_(11) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P11_Msk (_U_(0x1) << PIO_MDER_P11_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P11(value) (PIO_MDER_P11_Msk & ((value) << PIO_MDER_P11_Pos)) +#define PIO_MDER_P12_Pos _U_(12) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P12_Msk (_U_(0x1) << PIO_MDER_P12_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P12(value) (PIO_MDER_P12_Msk & ((value) << PIO_MDER_P12_Pos)) +#define PIO_MDER_P13_Pos _U_(13) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P13_Msk (_U_(0x1) << PIO_MDER_P13_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P13(value) (PIO_MDER_P13_Msk & ((value) << PIO_MDER_P13_Pos)) +#define PIO_MDER_P14_Pos _U_(14) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P14_Msk (_U_(0x1) << PIO_MDER_P14_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P14(value) (PIO_MDER_P14_Msk & ((value) << PIO_MDER_P14_Pos)) +#define PIO_MDER_P15_Pos _U_(15) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P15_Msk (_U_(0x1) << PIO_MDER_P15_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P15(value) (PIO_MDER_P15_Msk & ((value) << PIO_MDER_P15_Pos)) +#define PIO_MDER_P16_Pos _U_(16) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P16_Msk (_U_(0x1) << PIO_MDER_P16_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P16(value) (PIO_MDER_P16_Msk & ((value) << PIO_MDER_P16_Pos)) +#define PIO_MDER_P17_Pos _U_(17) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P17_Msk (_U_(0x1) << PIO_MDER_P17_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P17(value) (PIO_MDER_P17_Msk & ((value) << PIO_MDER_P17_Pos)) +#define PIO_MDER_P18_Pos _U_(18) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P18_Msk (_U_(0x1) << PIO_MDER_P18_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P18(value) (PIO_MDER_P18_Msk & ((value) << PIO_MDER_P18_Pos)) +#define PIO_MDER_P19_Pos _U_(19) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P19_Msk (_U_(0x1) << PIO_MDER_P19_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P19(value) (PIO_MDER_P19_Msk & ((value) << PIO_MDER_P19_Pos)) +#define PIO_MDER_P20_Pos _U_(20) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P20_Msk (_U_(0x1) << PIO_MDER_P20_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P20(value) (PIO_MDER_P20_Msk & ((value) << PIO_MDER_P20_Pos)) +#define PIO_MDER_P21_Pos _U_(21) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P21_Msk (_U_(0x1) << PIO_MDER_P21_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P21(value) (PIO_MDER_P21_Msk & ((value) << PIO_MDER_P21_Pos)) +#define PIO_MDER_P22_Pos _U_(22) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P22_Msk (_U_(0x1) << PIO_MDER_P22_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P22(value) (PIO_MDER_P22_Msk & ((value) << PIO_MDER_P22_Pos)) +#define PIO_MDER_P23_Pos _U_(23) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P23_Msk (_U_(0x1) << PIO_MDER_P23_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P23(value) (PIO_MDER_P23_Msk & ((value) << PIO_MDER_P23_Pos)) +#define PIO_MDER_P24_Pos _U_(24) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P24_Msk (_U_(0x1) << PIO_MDER_P24_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P24(value) (PIO_MDER_P24_Msk & ((value) << PIO_MDER_P24_Pos)) +#define PIO_MDER_P25_Pos _U_(25) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P25_Msk (_U_(0x1) << PIO_MDER_P25_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P25(value) (PIO_MDER_P25_Msk & ((value) << PIO_MDER_P25_Pos)) +#define PIO_MDER_P26_Pos _U_(26) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P26_Msk (_U_(0x1) << PIO_MDER_P26_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P26(value) (PIO_MDER_P26_Msk & ((value) << PIO_MDER_P26_Pos)) +#define PIO_MDER_P27_Pos _U_(27) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P27_Msk (_U_(0x1) << PIO_MDER_P27_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P27(value) (PIO_MDER_P27_Msk & ((value) << PIO_MDER_P27_Pos)) +#define PIO_MDER_P28_Pos _U_(28) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P28_Msk (_U_(0x1) << PIO_MDER_P28_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P28(value) (PIO_MDER_P28_Msk & ((value) << PIO_MDER_P28_Pos)) +#define PIO_MDER_P29_Pos _U_(29) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P29_Msk (_U_(0x1) << PIO_MDER_P29_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P29(value) (PIO_MDER_P29_Msk & ((value) << PIO_MDER_P29_Pos)) +#define PIO_MDER_P30_Pos _U_(30) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P30_Msk (_U_(0x1) << PIO_MDER_P30_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P30(value) (PIO_MDER_P30_Msk & ((value) << PIO_MDER_P30_Pos)) +#define PIO_MDER_P31_Pos _U_(31) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P31_Msk (_U_(0x1) << PIO_MDER_P31_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P31(value) (PIO_MDER_P31_Msk & ((value) << PIO_MDER_P31_Pos)) +#define PIO_MDER_Msk _U_(0xFFFFFFFF) /**< (PIO_MDER) Register Mask */ + +#define PIO_MDER_P_Pos _U_(0) /**< (PIO_MDER Position) Multi-drive Enable */ +#define PIO_MDER_P_Msk (_U_(0xFFFFFFFF) << PIO_MDER_P_Pos) /**< (PIO_MDER Mask) P */ +#define PIO_MDER_P(value) (PIO_MDER_P_Msk & ((value) << PIO_MDER_P_Pos)) + +/* -------- PIO_MDDR : (PIO Offset: 0x54) ( /W 32) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0_Pos _U_(0) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P0_Msk (_U_(0x1) << PIO_MDDR_P0_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P0(value) (PIO_MDDR_P0_Msk & ((value) << PIO_MDDR_P0_Pos)) +#define PIO_MDDR_P1_Pos _U_(1) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P1_Msk (_U_(0x1) << PIO_MDDR_P1_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P1(value) (PIO_MDDR_P1_Msk & ((value) << PIO_MDDR_P1_Pos)) +#define PIO_MDDR_P2_Pos _U_(2) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P2_Msk (_U_(0x1) << PIO_MDDR_P2_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P2(value) (PIO_MDDR_P2_Msk & ((value) << PIO_MDDR_P2_Pos)) +#define PIO_MDDR_P3_Pos _U_(3) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P3_Msk (_U_(0x1) << PIO_MDDR_P3_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P3(value) (PIO_MDDR_P3_Msk & ((value) << PIO_MDDR_P3_Pos)) +#define PIO_MDDR_P4_Pos _U_(4) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P4_Msk (_U_(0x1) << PIO_MDDR_P4_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P4(value) (PIO_MDDR_P4_Msk & ((value) << PIO_MDDR_P4_Pos)) +#define PIO_MDDR_P5_Pos _U_(5) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P5_Msk (_U_(0x1) << PIO_MDDR_P5_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P5(value) (PIO_MDDR_P5_Msk & ((value) << PIO_MDDR_P5_Pos)) +#define PIO_MDDR_P6_Pos _U_(6) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P6_Msk (_U_(0x1) << PIO_MDDR_P6_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P6(value) (PIO_MDDR_P6_Msk & ((value) << PIO_MDDR_P6_Pos)) +#define PIO_MDDR_P7_Pos _U_(7) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P7_Msk (_U_(0x1) << PIO_MDDR_P7_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P7(value) (PIO_MDDR_P7_Msk & ((value) << PIO_MDDR_P7_Pos)) +#define PIO_MDDR_P8_Pos _U_(8) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P8_Msk (_U_(0x1) << PIO_MDDR_P8_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P8(value) (PIO_MDDR_P8_Msk & ((value) << PIO_MDDR_P8_Pos)) +#define PIO_MDDR_P9_Pos _U_(9) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P9_Msk (_U_(0x1) << PIO_MDDR_P9_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P9(value) (PIO_MDDR_P9_Msk & ((value) << PIO_MDDR_P9_Pos)) +#define PIO_MDDR_P10_Pos _U_(10) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P10_Msk (_U_(0x1) << PIO_MDDR_P10_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P10(value) (PIO_MDDR_P10_Msk & ((value) << PIO_MDDR_P10_Pos)) +#define PIO_MDDR_P11_Pos _U_(11) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P11_Msk (_U_(0x1) << PIO_MDDR_P11_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P11(value) (PIO_MDDR_P11_Msk & ((value) << PIO_MDDR_P11_Pos)) +#define PIO_MDDR_P12_Pos _U_(12) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P12_Msk (_U_(0x1) << PIO_MDDR_P12_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P12(value) (PIO_MDDR_P12_Msk & ((value) << PIO_MDDR_P12_Pos)) +#define PIO_MDDR_P13_Pos _U_(13) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P13_Msk (_U_(0x1) << PIO_MDDR_P13_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P13(value) (PIO_MDDR_P13_Msk & ((value) << PIO_MDDR_P13_Pos)) +#define PIO_MDDR_P14_Pos _U_(14) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P14_Msk (_U_(0x1) << PIO_MDDR_P14_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P14(value) (PIO_MDDR_P14_Msk & ((value) << PIO_MDDR_P14_Pos)) +#define PIO_MDDR_P15_Pos _U_(15) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P15_Msk (_U_(0x1) << PIO_MDDR_P15_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P15(value) (PIO_MDDR_P15_Msk & ((value) << PIO_MDDR_P15_Pos)) +#define PIO_MDDR_P16_Pos _U_(16) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P16_Msk (_U_(0x1) << PIO_MDDR_P16_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P16(value) (PIO_MDDR_P16_Msk & ((value) << PIO_MDDR_P16_Pos)) +#define PIO_MDDR_P17_Pos _U_(17) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P17_Msk (_U_(0x1) << PIO_MDDR_P17_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P17(value) (PIO_MDDR_P17_Msk & ((value) << PIO_MDDR_P17_Pos)) +#define PIO_MDDR_P18_Pos _U_(18) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P18_Msk (_U_(0x1) << PIO_MDDR_P18_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P18(value) (PIO_MDDR_P18_Msk & ((value) << PIO_MDDR_P18_Pos)) +#define PIO_MDDR_P19_Pos _U_(19) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P19_Msk (_U_(0x1) << PIO_MDDR_P19_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P19(value) (PIO_MDDR_P19_Msk & ((value) << PIO_MDDR_P19_Pos)) +#define PIO_MDDR_P20_Pos _U_(20) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P20_Msk (_U_(0x1) << PIO_MDDR_P20_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P20(value) (PIO_MDDR_P20_Msk & ((value) << PIO_MDDR_P20_Pos)) +#define PIO_MDDR_P21_Pos _U_(21) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P21_Msk (_U_(0x1) << PIO_MDDR_P21_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P21(value) (PIO_MDDR_P21_Msk & ((value) << PIO_MDDR_P21_Pos)) +#define PIO_MDDR_P22_Pos _U_(22) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P22_Msk (_U_(0x1) << PIO_MDDR_P22_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P22(value) (PIO_MDDR_P22_Msk & ((value) << PIO_MDDR_P22_Pos)) +#define PIO_MDDR_P23_Pos _U_(23) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P23_Msk (_U_(0x1) << PIO_MDDR_P23_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P23(value) (PIO_MDDR_P23_Msk & ((value) << PIO_MDDR_P23_Pos)) +#define PIO_MDDR_P24_Pos _U_(24) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P24_Msk (_U_(0x1) << PIO_MDDR_P24_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P24(value) (PIO_MDDR_P24_Msk & ((value) << PIO_MDDR_P24_Pos)) +#define PIO_MDDR_P25_Pos _U_(25) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P25_Msk (_U_(0x1) << PIO_MDDR_P25_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P25(value) (PIO_MDDR_P25_Msk & ((value) << PIO_MDDR_P25_Pos)) +#define PIO_MDDR_P26_Pos _U_(26) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P26_Msk (_U_(0x1) << PIO_MDDR_P26_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P26(value) (PIO_MDDR_P26_Msk & ((value) << PIO_MDDR_P26_Pos)) +#define PIO_MDDR_P27_Pos _U_(27) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P27_Msk (_U_(0x1) << PIO_MDDR_P27_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P27(value) (PIO_MDDR_P27_Msk & ((value) << PIO_MDDR_P27_Pos)) +#define PIO_MDDR_P28_Pos _U_(28) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P28_Msk (_U_(0x1) << PIO_MDDR_P28_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P28(value) (PIO_MDDR_P28_Msk & ((value) << PIO_MDDR_P28_Pos)) +#define PIO_MDDR_P29_Pos _U_(29) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P29_Msk (_U_(0x1) << PIO_MDDR_P29_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P29(value) (PIO_MDDR_P29_Msk & ((value) << PIO_MDDR_P29_Pos)) +#define PIO_MDDR_P30_Pos _U_(30) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P30_Msk (_U_(0x1) << PIO_MDDR_P30_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P30(value) (PIO_MDDR_P30_Msk & ((value) << PIO_MDDR_P30_Pos)) +#define PIO_MDDR_P31_Pos _U_(31) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P31_Msk (_U_(0x1) << PIO_MDDR_P31_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P31(value) (PIO_MDDR_P31_Msk & ((value) << PIO_MDDR_P31_Pos)) +#define PIO_MDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDDR) Register Mask */ + +#define PIO_MDDR_P_Pos _U_(0) /**< (PIO_MDDR Position) Multi-drive Disable */ +#define PIO_MDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDDR_P_Pos) /**< (PIO_MDDR Mask) P */ +#define PIO_MDDR_P(value) (PIO_MDDR_P_Msk & ((value) << PIO_MDDR_P_Pos)) + +/* -------- PIO_MDSR : (PIO Offset: 0x58) ( R/ 32) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0_Pos _U_(0) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P0_Msk (_U_(0x1) << PIO_MDSR_P0_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P0(value) (PIO_MDSR_P0_Msk & ((value) << PIO_MDSR_P0_Pos)) +#define PIO_MDSR_P1_Pos _U_(1) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P1_Msk (_U_(0x1) << PIO_MDSR_P1_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P1(value) (PIO_MDSR_P1_Msk & ((value) << PIO_MDSR_P1_Pos)) +#define PIO_MDSR_P2_Pos _U_(2) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P2_Msk (_U_(0x1) << PIO_MDSR_P2_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P2(value) (PIO_MDSR_P2_Msk & ((value) << PIO_MDSR_P2_Pos)) +#define PIO_MDSR_P3_Pos _U_(3) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P3_Msk (_U_(0x1) << PIO_MDSR_P3_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P3(value) (PIO_MDSR_P3_Msk & ((value) << PIO_MDSR_P3_Pos)) +#define PIO_MDSR_P4_Pos _U_(4) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P4_Msk (_U_(0x1) << PIO_MDSR_P4_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P4(value) (PIO_MDSR_P4_Msk & ((value) << PIO_MDSR_P4_Pos)) +#define PIO_MDSR_P5_Pos _U_(5) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P5_Msk (_U_(0x1) << PIO_MDSR_P5_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P5(value) (PIO_MDSR_P5_Msk & ((value) << PIO_MDSR_P5_Pos)) +#define PIO_MDSR_P6_Pos _U_(6) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P6_Msk (_U_(0x1) << PIO_MDSR_P6_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P6(value) (PIO_MDSR_P6_Msk & ((value) << PIO_MDSR_P6_Pos)) +#define PIO_MDSR_P7_Pos _U_(7) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P7_Msk (_U_(0x1) << PIO_MDSR_P7_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P7(value) (PIO_MDSR_P7_Msk & ((value) << PIO_MDSR_P7_Pos)) +#define PIO_MDSR_P8_Pos _U_(8) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P8_Msk (_U_(0x1) << PIO_MDSR_P8_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P8(value) (PIO_MDSR_P8_Msk & ((value) << PIO_MDSR_P8_Pos)) +#define PIO_MDSR_P9_Pos _U_(9) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P9_Msk (_U_(0x1) << PIO_MDSR_P9_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P9(value) (PIO_MDSR_P9_Msk & ((value) << PIO_MDSR_P9_Pos)) +#define PIO_MDSR_P10_Pos _U_(10) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P10_Msk (_U_(0x1) << PIO_MDSR_P10_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P10(value) (PIO_MDSR_P10_Msk & ((value) << PIO_MDSR_P10_Pos)) +#define PIO_MDSR_P11_Pos _U_(11) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P11_Msk (_U_(0x1) << PIO_MDSR_P11_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P11(value) (PIO_MDSR_P11_Msk & ((value) << PIO_MDSR_P11_Pos)) +#define PIO_MDSR_P12_Pos _U_(12) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P12_Msk (_U_(0x1) << PIO_MDSR_P12_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P12(value) (PIO_MDSR_P12_Msk & ((value) << PIO_MDSR_P12_Pos)) +#define PIO_MDSR_P13_Pos _U_(13) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P13_Msk (_U_(0x1) << PIO_MDSR_P13_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P13(value) (PIO_MDSR_P13_Msk & ((value) << PIO_MDSR_P13_Pos)) +#define PIO_MDSR_P14_Pos _U_(14) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P14_Msk (_U_(0x1) << PIO_MDSR_P14_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P14(value) (PIO_MDSR_P14_Msk & ((value) << PIO_MDSR_P14_Pos)) +#define PIO_MDSR_P15_Pos _U_(15) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P15_Msk (_U_(0x1) << PIO_MDSR_P15_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P15(value) (PIO_MDSR_P15_Msk & ((value) << PIO_MDSR_P15_Pos)) +#define PIO_MDSR_P16_Pos _U_(16) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P16_Msk (_U_(0x1) << PIO_MDSR_P16_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P16(value) (PIO_MDSR_P16_Msk & ((value) << PIO_MDSR_P16_Pos)) +#define PIO_MDSR_P17_Pos _U_(17) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P17_Msk (_U_(0x1) << PIO_MDSR_P17_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P17(value) (PIO_MDSR_P17_Msk & ((value) << PIO_MDSR_P17_Pos)) +#define PIO_MDSR_P18_Pos _U_(18) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P18_Msk (_U_(0x1) << PIO_MDSR_P18_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P18(value) (PIO_MDSR_P18_Msk & ((value) << PIO_MDSR_P18_Pos)) +#define PIO_MDSR_P19_Pos _U_(19) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P19_Msk (_U_(0x1) << PIO_MDSR_P19_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P19(value) (PIO_MDSR_P19_Msk & ((value) << PIO_MDSR_P19_Pos)) +#define PIO_MDSR_P20_Pos _U_(20) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P20_Msk (_U_(0x1) << PIO_MDSR_P20_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P20(value) (PIO_MDSR_P20_Msk & ((value) << PIO_MDSR_P20_Pos)) +#define PIO_MDSR_P21_Pos _U_(21) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P21_Msk (_U_(0x1) << PIO_MDSR_P21_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P21(value) (PIO_MDSR_P21_Msk & ((value) << PIO_MDSR_P21_Pos)) +#define PIO_MDSR_P22_Pos _U_(22) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P22_Msk (_U_(0x1) << PIO_MDSR_P22_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P22(value) (PIO_MDSR_P22_Msk & ((value) << PIO_MDSR_P22_Pos)) +#define PIO_MDSR_P23_Pos _U_(23) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P23_Msk (_U_(0x1) << PIO_MDSR_P23_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P23(value) (PIO_MDSR_P23_Msk & ((value) << PIO_MDSR_P23_Pos)) +#define PIO_MDSR_P24_Pos _U_(24) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P24_Msk (_U_(0x1) << PIO_MDSR_P24_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P24(value) (PIO_MDSR_P24_Msk & ((value) << PIO_MDSR_P24_Pos)) +#define PIO_MDSR_P25_Pos _U_(25) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P25_Msk (_U_(0x1) << PIO_MDSR_P25_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P25(value) (PIO_MDSR_P25_Msk & ((value) << PIO_MDSR_P25_Pos)) +#define PIO_MDSR_P26_Pos _U_(26) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P26_Msk (_U_(0x1) << PIO_MDSR_P26_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P26(value) (PIO_MDSR_P26_Msk & ((value) << PIO_MDSR_P26_Pos)) +#define PIO_MDSR_P27_Pos _U_(27) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P27_Msk (_U_(0x1) << PIO_MDSR_P27_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P27(value) (PIO_MDSR_P27_Msk & ((value) << PIO_MDSR_P27_Pos)) +#define PIO_MDSR_P28_Pos _U_(28) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P28_Msk (_U_(0x1) << PIO_MDSR_P28_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P28(value) (PIO_MDSR_P28_Msk & ((value) << PIO_MDSR_P28_Pos)) +#define PIO_MDSR_P29_Pos _U_(29) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P29_Msk (_U_(0x1) << PIO_MDSR_P29_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P29(value) (PIO_MDSR_P29_Msk & ((value) << PIO_MDSR_P29_Pos)) +#define PIO_MDSR_P30_Pos _U_(30) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P30_Msk (_U_(0x1) << PIO_MDSR_P30_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P30(value) (PIO_MDSR_P30_Msk & ((value) << PIO_MDSR_P30_Pos)) +#define PIO_MDSR_P31_Pos _U_(31) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P31_Msk (_U_(0x1) << PIO_MDSR_P31_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P31(value) (PIO_MDSR_P31_Msk & ((value) << PIO_MDSR_P31_Pos)) +#define PIO_MDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDSR) Register Mask */ + +#define PIO_MDSR_P_Pos _U_(0) /**< (PIO_MDSR Position) Multi-drive Status */ +#define PIO_MDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDSR_P_Pos) /**< (PIO_MDSR Mask) P */ +#define PIO_MDSR_P(value) (PIO_MDSR_P_Msk & ((value) << PIO_MDSR_P_Pos)) + +/* -------- PIO_PUDR : (PIO Offset: 0x60) ( /W 32) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0_Pos _U_(0) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P0_Msk (_U_(0x1) << PIO_PUDR_P0_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P0(value) (PIO_PUDR_P0_Msk & ((value) << PIO_PUDR_P0_Pos)) +#define PIO_PUDR_P1_Pos _U_(1) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P1_Msk (_U_(0x1) << PIO_PUDR_P1_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P1(value) (PIO_PUDR_P1_Msk & ((value) << PIO_PUDR_P1_Pos)) +#define PIO_PUDR_P2_Pos _U_(2) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P2_Msk (_U_(0x1) << PIO_PUDR_P2_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P2(value) (PIO_PUDR_P2_Msk & ((value) << PIO_PUDR_P2_Pos)) +#define PIO_PUDR_P3_Pos _U_(3) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P3_Msk (_U_(0x1) << PIO_PUDR_P3_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P3(value) (PIO_PUDR_P3_Msk & ((value) << PIO_PUDR_P3_Pos)) +#define PIO_PUDR_P4_Pos _U_(4) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P4_Msk (_U_(0x1) << PIO_PUDR_P4_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P4(value) (PIO_PUDR_P4_Msk & ((value) << PIO_PUDR_P4_Pos)) +#define PIO_PUDR_P5_Pos _U_(5) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P5_Msk (_U_(0x1) << PIO_PUDR_P5_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P5(value) (PIO_PUDR_P5_Msk & ((value) << PIO_PUDR_P5_Pos)) +#define PIO_PUDR_P6_Pos _U_(6) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P6_Msk (_U_(0x1) << PIO_PUDR_P6_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P6(value) (PIO_PUDR_P6_Msk & ((value) << PIO_PUDR_P6_Pos)) +#define PIO_PUDR_P7_Pos _U_(7) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P7_Msk (_U_(0x1) << PIO_PUDR_P7_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P7(value) (PIO_PUDR_P7_Msk & ((value) << PIO_PUDR_P7_Pos)) +#define PIO_PUDR_P8_Pos _U_(8) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P8_Msk (_U_(0x1) << PIO_PUDR_P8_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P8(value) (PIO_PUDR_P8_Msk & ((value) << PIO_PUDR_P8_Pos)) +#define PIO_PUDR_P9_Pos _U_(9) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P9_Msk (_U_(0x1) << PIO_PUDR_P9_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P9(value) (PIO_PUDR_P9_Msk & ((value) << PIO_PUDR_P9_Pos)) +#define PIO_PUDR_P10_Pos _U_(10) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P10_Msk (_U_(0x1) << PIO_PUDR_P10_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P10(value) (PIO_PUDR_P10_Msk & ((value) << PIO_PUDR_P10_Pos)) +#define PIO_PUDR_P11_Pos _U_(11) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P11_Msk (_U_(0x1) << PIO_PUDR_P11_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P11(value) (PIO_PUDR_P11_Msk & ((value) << PIO_PUDR_P11_Pos)) +#define PIO_PUDR_P12_Pos _U_(12) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P12_Msk (_U_(0x1) << PIO_PUDR_P12_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P12(value) (PIO_PUDR_P12_Msk & ((value) << PIO_PUDR_P12_Pos)) +#define PIO_PUDR_P13_Pos _U_(13) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P13_Msk (_U_(0x1) << PIO_PUDR_P13_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P13(value) (PIO_PUDR_P13_Msk & ((value) << PIO_PUDR_P13_Pos)) +#define PIO_PUDR_P14_Pos _U_(14) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P14_Msk (_U_(0x1) << PIO_PUDR_P14_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P14(value) (PIO_PUDR_P14_Msk & ((value) << PIO_PUDR_P14_Pos)) +#define PIO_PUDR_P15_Pos _U_(15) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P15_Msk (_U_(0x1) << PIO_PUDR_P15_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P15(value) (PIO_PUDR_P15_Msk & ((value) << PIO_PUDR_P15_Pos)) +#define PIO_PUDR_P16_Pos _U_(16) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P16_Msk (_U_(0x1) << PIO_PUDR_P16_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P16(value) (PIO_PUDR_P16_Msk & ((value) << PIO_PUDR_P16_Pos)) +#define PIO_PUDR_P17_Pos _U_(17) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P17_Msk (_U_(0x1) << PIO_PUDR_P17_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P17(value) (PIO_PUDR_P17_Msk & ((value) << PIO_PUDR_P17_Pos)) +#define PIO_PUDR_P18_Pos _U_(18) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P18_Msk (_U_(0x1) << PIO_PUDR_P18_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P18(value) (PIO_PUDR_P18_Msk & ((value) << PIO_PUDR_P18_Pos)) +#define PIO_PUDR_P19_Pos _U_(19) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P19_Msk (_U_(0x1) << PIO_PUDR_P19_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P19(value) (PIO_PUDR_P19_Msk & ((value) << PIO_PUDR_P19_Pos)) +#define PIO_PUDR_P20_Pos _U_(20) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P20_Msk (_U_(0x1) << PIO_PUDR_P20_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P20(value) (PIO_PUDR_P20_Msk & ((value) << PIO_PUDR_P20_Pos)) +#define PIO_PUDR_P21_Pos _U_(21) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P21_Msk (_U_(0x1) << PIO_PUDR_P21_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P21(value) (PIO_PUDR_P21_Msk & ((value) << PIO_PUDR_P21_Pos)) +#define PIO_PUDR_P22_Pos _U_(22) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P22_Msk (_U_(0x1) << PIO_PUDR_P22_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P22(value) (PIO_PUDR_P22_Msk & ((value) << PIO_PUDR_P22_Pos)) +#define PIO_PUDR_P23_Pos _U_(23) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P23_Msk (_U_(0x1) << PIO_PUDR_P23_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P23(value) (PIO_PUDR_P23_Msk & ((value) << PIO_PUDR_P23_Pos)) +#define PIO_PUDR_P24_Pos _U_(24) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P24_Msk (_U_(0x1) << PIO_PUDR_P24_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P24(value) (PIO_PUDR_P24_Msk & ((value) << PIO_PUDR_P24_Pos)) +#define PIO_PUDR_P25_Pos _U_(25) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P25_Msk (_U_(0x1) << PIO_PUDR_P25_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P25(value) (PIO_PUDR_P25_Msk & ((value) << PIO_PUDR_P25_Pos)) +#define PIO_PUDR_P26_Pos _U_(26) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P26_Msk (_U_(0x1) << PIO_PUDR_P26_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P26(value) (PIO_PUDR_P26_Msk & ((value) << PIO_PUDR_P26_Pos)) +#define PIO_PUDR_P27_Pos _U_(27) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P27_Msk (_U_(0x1) << PIO_PUDR_P27_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P27(value) (PIO_PUDR_P27_Msk & ((value) << PIO_PUDR_P27_Pos)) +#define PIO_PUDR_P28_Pos _U_(28) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P28_Msk (_U_(0x1) << PIO_PUDR_P28_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P28(value) (PIO_PUDR_P28_Msk & ((value) << PIO_PUDR_P28_Pos)) +#define PIO_PUDR_P29_Pos _U_(29) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P29_Msk (_U_(0x1) << PIO_PUDR_P29_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P29(value) (PIO_PUDR_P29_Msk & ((value) << PIO_PUDR_P29_Pos)) +#define PIO_PUDR_P30_Pos _U_(30) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P30_Msk (_U_(0x1) << PIO_PUDR_P30_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P30(value) (PIO_PUDR_P30_Msk & ((value) << PIO_PUDR_P30_Pos)) +#define PIO_PUDR_P31_Pos _U_(31) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P31_Msk (_U_(0x1) << PIO_PUDR_P31_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P31(value) (PIO_PUDR_P31_Msk & ((value) << PIO_PUDR_P31_Pos)) +#define PIO_PUDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUDR) Register Mask */ + +#define PIO_PUDR_P_Pos _U_(0) /**< (PIO_PUDR Position) Pull-Up Disable */ +#define PIO_PUDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUDR_P_Pos) /**< (PIO_PUDR Mask) P */ +#define PIO_PUDR_P(value) (PIO_PUDR_P_Msk & ((value) << PIO_PUDR_P_Pos)) + +/* -------- PIO_PUER : (PIO Offset: 0x64) ( /W 32) Pull-up Enable Register -------- */ +#define PIO_PUER_P0_Pos _U_(0) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P0_Msk (_U_(0x1) << PIO_PUER_P0_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P0(value) (PIO_PUER_P0_Msk & ((value) << PIO_PUER_P0_Pos)) +#define PIO_PUER_P1_Pos _U_(1) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P1_Msk (_U_(0x1) << PIO_PUER_P1_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P1(value) (PIO_PUER_P1_Msk & ((value) << PIO_PUER_P1_Pos)) +#define PIO_PUER_P2_Pos _U_(2) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P2_Msk (_U_(0x1) << PIO_PUER_P2_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P2(value) (PIO_PUER_P2_Msk & ((value) << PIO_PUER_P2_Pos)) +#define PIO_PUER_P3_Pos _U_(3) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P3_Msk (_U_(0x1) << PIO_PUER_P3_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P3(value) (PIO_PUER_P3_Msk & ((value) << PIO_PUER_P3_Pos)) +#define PIO_PUER_P4_Pos _U_(4) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P4_Msk (_U_(0x1) << PIO_PUER_P4_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P4(value) (PIO_PUER_P4_Msk & ((value) << PIO_PUER_P4_Pos)) +#define PIO_PUER_P5_Pos _U_(5) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P5_Msk (_U_(0x1) << PIO_PUER_P5_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P5(value) (PIO_PUER_P5_Msk & ((value) << PIO_PUER_P5_Pos)) +#define PIO_PUER_P6_Pos _U_(6) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P6_Msk (_U_(0x1) << PIO_PUER_P6_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P6(value) (PIO_PUER_P6_Msk & ((value) << PIO_PUER_P6_Pos)) +#define PIO_PUER_P7_Pos _U_(7) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P7_Msk (_U_(0x1) << PIO_PUER_P7_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P7(value) (PIO_PUER_P7_Msk & ((value) << PIO_PUER_P7_Pos)) +#define PIO_PUER_P8_Pos _U_(8) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P8_Msk (_U_(0x1) << PIO_PUER_P8_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P8(value) (PIO_PUER_P8_Msk & ((value) << PIO_PUER_P8_Pos)) +#define PIO_PUER_P9_Pos _U_(9) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P9_Msk (_U_(0x1) << PIO_PUER_P9_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P9(value) (PIO_PUER_P9_Msk & ((value) << PIO_PUER_P9_Pos)) +#define PIO_PUER_P10_Pos _U_(10) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P10_Msk (_U_(0x1) << PIO_PUER_P10_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P10(value) (PIO_PUER_P10_Msk & ((value) << PIO_PUER_P10_Pos)) +#define PIO_PUER_P11_Pos _U_(11) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P11_Msk (_U_(0x1) << PIO_PUER_P11_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P11(value) (PIO_PUER_P11_Msk & ((value) << PIO_PUER_P11_Pos)) +#define PIO_PUER_P12_Pos _U_(12) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P12_Msk (_U_(0x1) << PIO_PUER_P12_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P12(value) (PIO_PUER_P12_Msk & ((value) << PIO_PUER_P12_Pos)) +#define PIO_PUER_P13_Pos _U_(13) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P13_Msk (_U_(0x1) << PIO_PUER_P13_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P13(value) (PIO_PUER_P13_Msk & ((value) << PIO_PUER_P13_Pos)) +#define PIO_PUER_P14_Pos _U_(14) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P14_Msk (_U_(0x1) << PIO_PUER_P14_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P14(value) (PIO_PUER_P14_Msk & ((value) << PIO_PUER_P14_Pos)) +#define PIO_PUER_P15_Pos _U_(15) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P15_Msk (_U_(0x1) << PIO_PUER_P15_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P15(value) (PIO_PUER_P15_Msk & ((value) << PIO_PUER_P15_Pos)) +#define PIO_PUER_P16_Pos _U_(16) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P16_Msk (_U_(0x1) << PIO_PUER_P16_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P16(value) (PIO_PUER_P16_Msk & ((value) << PIO_PUER_P16_Pos)) +#define PIO_PUER_P17_Pos _U_(17) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P17_Msk (_U_(0x1) << PIO_PUER_P17_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P17(value) (PIO_PUER_P17_Msk & ((value) << PIO_PUER_P17_Pos)) +#define PIO_PUER_P18_Pos _U_(18) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P18_Msk (_U_(0x1) << PIO_PUER_P18_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P18(value) (PIO_PUER_P18_Msk & ((value) << PIO_PUER_P18_Pos)) +#define PIO_PUER_P19_Pos _U_(19) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P19_Msk (_U_(0x1) << PIO_PUER_P19_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P19(value) (PIO_PUER_P19_Msk & ((value) << PIO_PUER_P19_Pos)) +#define PIO_PUER_P20_Pos _U_(20) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P20_Msk (_U_(0x1) << PIO_PUER_P20_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P20(value) (PIO_PUER_P20_Msk & ((value) << PIO_PUER_P20_Pos)) +#define PIO_PUER_P21_Pos _U_(21) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P21_Msk (_U_(0x1) << PIO_PUER_P21_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P21(value) (PIO_PUER_P21_Msk & ((value) << PIO_PUER_P21_Pos)) +#define PIO_PUER_P22_Pos _U_(22) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P22_Msk (_U_(0x1) << PIO_PUER_P22_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P22(value) (PIO_PUER_P22_Msk & ((value) << PIO_PUER_P22_Pos)) +#define PIO_PUER_P23_Pos _U_(23) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P23_Msk (_U_(0x1) << PIO_PUER_P23_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P23(value) (PIO_PUER_P23_Msk & ((value) << PIO_PUER_P23_Pos)) +#define PIO_PUER_P24_Pos _U_(24) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P24_Msk (_U_(0x1) << PIO_PUER_P24_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P24(value) (PIO_PUER_P24_Msk & ((value) << PIO_PUER_P24_Pos)) +#define PIO_PUER_P25_Pos _U_(25) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P25_Msk (_U_(0x1) << PIO_PUER_P25_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P25(value) (PIO_PUER_P25_Msk & ((value) << PIO_PUER_P25_Pos)) +#define PIO_PUER_P26_Pos _U_(26) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P26_Msk (_U_(0x1) << PIO_PUER_P26_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P26(value) (PIO_PUER_P26_Msk & ((value) << PIO_PUER_P26_Pos)) +#define PIO_PUER_P27_Pos _U_(27) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P27_Msk (_U_(0x1) << PIO_PUER_P27_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P27(value) (PIO_PUER_P27_Msk & ((value) << PIO_PUER_P27_Pos)) +#define PIO_PUER_P28_Pos _U_(28) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P28_Msk (_U_(0x1) << PIO_PUER_P28_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P28(value) (PIO_PUER_P28_Msk & ((value) << PIO_PUER_P28_Pos)) +#define PIO_PUER_P29_Pos _U_(29) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P29_Msk (_U_(0x1) << PIO_PUER_P29_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P29(value) (PIO_PUER_P29_Msk & ((value) << PIO_PUER_P29_Pos)) +#define PIO_PUER_P30_Pos _U_(30) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P30_Msk (_U_(0x1) << PIO_PUER_P30_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P30(value) (PIO_PUER_P30_Msk & ((value) << PIO_PUER_P30_Pos)) +#define PIO_PUER_P31_Pos _U_(31) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P31_Msk (_U_(0x1) << PIO_PUER_P31_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P31(value) (PIO_PUER_P31_Msk & ((value) << PIO_PUER_P31_Pos)) +#define PIO_PUER_Msk _U_(0xFFFFFFFF) /**< (PIO_PUER) Register Mask */ + +#define PIO_PUER_P_Pos _U_(0) /**< (PIO_PUER Position) Pull-Up Enable */ +#define PIO_PUER_P_Msk (_U_(0xFFFFFFFF) << PIO_PUER_P_Pos) /**< (PIO_PUER Mask) P */ +#define PIO_PUER_P(value) (PIO_PUER_P_Msk & ((value) << PIO_PUER_P_Pos)) + +/* -------- PIO_PUSR : (PIO Offset: 0x68) ( R/ 32) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0_Pos _U_(0) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P0_Msk (_U_(0x1) << PIO_PUSR_P0_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P0(value) (PIO_PUSR_P0_Msk & ((value) << PIO_PUSR_P0_Pos)) +#define PIO_PUSR_P1_Pos _U_(1) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P1_Msk (_U_(0x1) << PIO_PUSR_P1_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P1(value) (PIO_PUSR_P1_Msk & ((value) << PIO_PUSR_P1_Pos)) +#define PIO_PUSR_P2_Pos _U_(2) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P2_Msk (_U_(0x1) << PIO_PUSR_P2_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P2(value) (PIO_PUSR_P2_Msk & ((value) << PIO_PUSR_P2_Pos)) +#define PIO_PUSR_P3_Pos _U_(3) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P3_Msk (_U_(0x1) << PIO_PUSR_P3_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P3(value) (PIO_PUSR_P3_Msk & ((value) << PIO_PUSR_P3_Pos)) +#define PIO_PUSR_P4_Pos _U_(4) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P4_Msk (_U_(0x1) << PIO_PUSR_P4_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P4(value) (PIO_PUSR_P4_Msk & ((value) << PIO_PUSR_P4_Pos)) +#define PIO_PUSR_P5_Pos _U_(5) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P5_Msk (_U_(0x1) << PIO_PUSR_P5_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P5(value) (PIO_PUSR_P5_Msk & ((value) << PIO_PUSR_P5_Pos)) +#define PIO_PUSR_P6_Pos _U_(6) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P6_Msk (_U_(0x1) << PIO_PUSR_P6_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P6(value) (PIO_PUSR_P6_Msk & ((value) << PIO_PUSR_P6_Pos)) +#define PIO_PUSR_P7_Pos _U_(7) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P7_Msk (_U_(0x1) << PIO_PUSR_P7_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P7(value) (PIO_PUSR_P7_Msk & ((value) << PIO_PUSR_P7_Pos)) +#define PIO_PUSR_P8_Pos _U_(8) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P8_Msk (_U_(0x1) << PIO_PUSR_P8_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P8(value) (PIO_PUSR_P8_Msk & ((value) << PIO_PUSR_P8_Pos)) +#define PIO_PUSR_P9_Pos _U_(9) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P9_Msk (_U_(0x1) << PIO_PUSR_P9_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P9(value) (PIO_PUSR_P9_Msk & ((value) << PIO_PUSR_P9_Pos)) +#define PIO_PUSR_P10_Pos _U_(10) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P10_Msk (_U_(0x1) << PIO_PUSR_P10_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P10(value) (PIO_PUSR_P10_Msk & ((value) << PIO_PUSR_P10_Pos)) +#define PIO_PUSR_P11_Pos _U_(11) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P11_Msk (_U_(0x1) << PIO_PUSR_P11_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P11(value) (PIO_PUSR_P11_Msk & ((value) << PIO_PUSR_P11_Pos)) +#define PIO_PUSR_P12_Pos _U_(12) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P12_Msk (_U_(0x1) << PIO_PUSR_P12_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P12(value) (PIO_PUSR_P12_Msk & ((value) << PIO_PUSR_P12_Pos)) +#define PIO_PUSR_P13_Pos _U_(13) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P13_Msk (_U_(0x1) << PIO_PUSR_P13_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P13(value) (PIO_PUSR_P13_Msk & ((value) << PIO_PUSR_P13_Pos)) +#define PIO_PUSR_P14_Pos _U_(14) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P14_Msk (_U_(0x1) << PIO_PUSR_P14_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P14(value) (PIO_PUSR_P14_Msk & ((value) << PIO_PUSR_P14_Pos)) +#define PIO_PUSR_P15_Pos _U_(15) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P15_Msk (_U_(0x1) << PIO_PUSR_P15_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P15(value) (PIO_PUSR_P15_Msk & ((value) << PIO_PUSR_P15_Pos)) +#define PIO_PUSR_P16_Pos _U_(16) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P16_Msk (_U_(0x1) << PIO_PUSR_P16_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P16(value) (PIO_PUSR_P16_Msk & ((value) << PIO_PUSR_P16_Pos)) +#define PIO_PUSR_P17_Pos _U_(17) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P17_Msk (_U_(0x1) << PIO_PUSR_P17_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P17(value) (PIO_PUSR_P17_Msk & ((value) << PIO_PUSR_P17_Pos)) +#define PIO_PUSR_P18_Pos _U_(18) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P18_Msk (_U_(0x1) << PIO_PUSR_P18_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P18(value) (PIO_PUSR_P18_Msk & ((value) << PIO_PUSR_P18_Pos)) +#define PIO_PUSR_P19_Pos _U_(19) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P19_Msk (_U_(0x1) << PIO_PUSR_P19_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P19(value) (PIO_PUSR_P19_Msk & ((value) << PIO_PUSR_P19_Pos)) +#define PIO_PUSR_P20_Pos _U_(20) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P20_Msk (_U_(0x1) << PIO_PUSR_P20_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P20(value) (PIO_PUSR_P20_Msk & ((value) << PIO_PUSR_P20_Pos)) +#define PIO_PUSR_P21_Pos _U_(21) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P21_Msk (_U_(0x1) << PIO_PUSR_P21_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P21(value) (PIO_PUSR_P21_Msk & ((value) << PIO_PUSR_P21_Pos)) +#define PIO_PUSR_P22_Pos _U_(22) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P22_Msk (_U_(0x1) << PIO_PUSR_P22_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P22(value) (PIO_PUSR_P22_Msk & ((value) << PIO_PUSR_P22_Pos)) +#define PIO_PUSR_P23_Pos _U_(23) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P23_Msk (_U_(0x1) << PIO_PUSR_P23_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P23(value) (PIO_PUSR_P23_Msk & ((value) << PIO_PUSR_P23_Pos)) +#define PIO_PUSR_P24_Pos _U_(24) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P24_Msk (_U_(0x1) << PIO_PUSR_P24_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P24(value) (PIO_PUSR_P24_Msk & ((value) << PIO_PUSR_P24_Pos)) +#define PIO_PUSR_P25_Pos _U_(25) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P25_Msk (_U_(0x1) << PIO_PUSR_P25_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P25(value) (PIO_PUSR_P25_Msk & ((value) << PIO_PUSR_P25_Pos)) +#define PIO_PUSR_P26_Pos _U_(26) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P26_Msk (_U_(0x1) << PIO_PUSR_P26_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P26(value) (PIO_PUSR_P26_Msk & ((value) << PIO_PUSR_P26_Pos)) +#define PIO_PUSR_P27_Pos _U_(27) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P27_Msk (_U_(0x1) << PIO_PUSR_P27_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P27(value) (PIO_PUSR_P27_Msk & ((value) << PIO_PUSR_P27_Pos)) +#define PIO_PUSR_P28_Pos _U_(28) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P28_Msk (_U_(0x1) << PIO_PUSR_P28_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P28(value) (PIO_PUSR_P28_Msk & ((value) << PIO_PUSR_P28_Pos)) +#define PIO_PUSR_P29_Pos _U_(29) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P29_Msk (_U_(0x1) << PIO_PUSR_P29_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P29(value) (PIO_PUSR_P29_Msk & ((value) << PIO_PUSR_P29_Pos)) +#define PIO_PUSR_P30_Pos _U_(30) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P30_Msk (_U_(0x1) << PIO_PUSR_P30_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P30(value) (PIO_PUSR_P30_Msk & ((value) << PIO_PUSR_P30_Pos)) +#define PIO_PUSR_P31_Pos _U_(31) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P31_Msk (_U_(0x1) << PIO_PUSR_P31_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P31(value) (PIO_PUSR_P31_Msk & ((value) << PIO_PUSR_P31_Pos)) +#define PIO_PUSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUSR) Register Mask */ + +#define PIO_PUSR_P_Pos _U_(0) /**< (PIO_PUSR Position) Pull-Up Status */ +#define PIO_PUSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUSR_P_Pos) /**< (PIO_PUSR Mask) P */ +#define PIO_PUSR_P(value) (PIO_PUSR_P_Msk & ((value) << PIO_PUSR_P_Pos)) + +/* -------- PIO_ABCDSR : (PIO Offset: 0x70) (R/W 32) Peripheral ABCD Select Register 0 -------- */ +#define PIO_ABCDSR_P0_Pos _U_(0) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P0_Msk (_U_(0x1) << PIO_ABCDSR_P0_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P0(value) (PIO_ABCDSR_P0_Msk & ((value) << PIO_ABCDSR_P0_Pos)) +#define PIO_ABCDSR_P1_Pos _U_(1) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P1_Msk (_U_(0x1) << PIO_ABCDSR_P1_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P1(value) (PIO_ABCDSR_P1_Msk & ((value) << PIO_ABCDSR_P1_Pos)) +#define PIO_ABCDSR_P2_Pos _U_(2) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P2_Msk (_U_(0x1) << PIO_ABCDSR_P2_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P2(value) (PIO_ABCDSR_P2_Msk & ((value) << PIO_ABCDSR_P2_Pos)) +#define PIO_ABCDSR_P3_Pos _U_(3) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P3_Msk (_U_(0x1) << PIO_ABCDSR_P3_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P3(value) (PIO_ABCDSR_P3_Msk & ((value) << PIO_ABCDSR_P3_Pos)) +#define PIO_ABCDSR_P4_Pos _U_(4) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P4_Msk (_U_(0x1) << PIO_ABCDSR_P4_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P4(value) (PIO_ABCDSR_P4_Msk & ((value) << PIO_ABCDSR_P4_Pos)) +#define PIO_ABCDSR_P5_Pos _U_(5) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P5_Msk (_U_(0x1) << PIO_ABCDSR_P5_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P5(value) (PIO_ABCDSR_P5_Msk & ((value) << PIO_ABCDSR_P5_Pos)) +#define PIO_ABCDSR_P6_Pos _U_(6) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P6_Msk (_U_(0x1) << PIO_ABCDSR_P6_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P6(value) (PIO_ABCDSR_P6_Msk & ((value) << PIO_ABCDSR_P6_Pos)) +#define PIO_ABCDSR_P7_Pos _U_(7) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P7_Msk (_U_(0x1) << PIO_ABCDSR_P7_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P7(value) (PIO_ABCDSR_P7_Msk & ((value) << PIO_ABCDSR_P7_Pos)) +#define PIO_ABCDSR_P8_Pos _U_(8) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P8_Msk (_U_(0x1) << PIO_ABCDSR_P8_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P8(value) (PIO_ABCDSR_P8_Msk & ((value) << PIO_ABCDSR_P8_Pos)) +#define PIO_ABCDSR_P9_Pos _U_(9) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P9_Msk (_U_(0x1) << PIO_ABCDSR_P9_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P9(value) (PIO_ABCDSR_P9_Msk & ((value) << PIO_ABCDSR_P9_Pos)) +#define PIO_ABCDSR_P10_Pos _U_(10) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P10_Msk (_U_(0x1) << PIO_ABCDSR_P10_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P10(value) (PIO_ABCDSR_P10_Msk & ((value) << PIO_ABCDSR_P10_Pos)) +#define PIO_ABCDSR_P11_Pos _U_(11) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P11_Msk (_U_(0x1) << PIO_ABCDSR_P11_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P11(value) (PIO_ABCDSR_P11_Msk & ((value) << PIO_ABCDSR_P11_Pos)) +#define PIO_ABCDSR_P12_Pos _U_(12) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P12_Msk (_U_(0x1) << PIO_ABCDSR_P12_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P12(value) (PIO_ABCDSR_P12_Msk & ((value) << PIO_ABCDSR_P12_Pos)) +#define PIO_ABCDSR_P13_Pos _U_(13) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P13_Msk (_U_(0x1) << PIO_ABCDSR_P13_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P13(value) (PIO_ABCDSR_P13_Msk & ((value) << PIO_ABCDSR_P13_Pos)) +#define PIO_ABCDSR_P14_Pos _U_(14) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P14_Msk (_U_(0x1) << PIO_ABCDSR_P14_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P14(value) (PIO_ABCDSR_P14_Msk & ((value) << PIO_ABCDSR_P14_Pos)) +#define PIO_ABCDSR_P15_Pos _U_(15) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P15_Msk (_U_(0x1) << PIO_ABCDSR_P15_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P15(value) (PIO_ABCDSR_P15_Msk & ((value) << PIO_ABCDSR_P15_Pos)) +#define PIO_ABCDSR_P16_Pos _U_(16) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P16_Msk (_U_(0x1) << PIO_ABCDSR_P16_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P16(value) (PIO_ABCDSR_P16_Msk & ((value) << PIO_ABCDSR_P16_Pos)) +#define PIO_ABCDSR_P17_Pos _U_(17) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P17_Msk (_U_(0x1) << PIO_ABCDSR_P17_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P17(value) (PIO_ABCDSR_P17_Msk & ((value) << PIO_ABCDSR_P17_Pos)) +#define PIO_ABCDSR_P18_Pos _U_(18) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P18_Msk (_U_(0x1) << PIO_ABCDSR_P18_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P18(value) (PIO_ABCDSR_P18_Msk & ((value) << PIO_ABCDSR_P18_Pos)) +#define PIO_ABCDSR_P19_Pos _U_(19) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P19_Msk (_U_(0x1) << PIO_ABCDSR_P19_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P19(value) (PIO_ABCDSR_P19_Msk & ((value) << PIO_ABCDSR_P19_Pos)) +#define PIO_ABCDSR_P20_Pos _U_(20) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P20_Msk (_U_(0x1) << PIO_ABCDSR_P20_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P20(value) (PIO_ABCDSR_P20_Msk & ((value) << PIO_ABCDSR_P20_Pos)) +#define PIO_ABCDSR_P21_Pos _U_(21) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P21_Msk (_U_(0x1) << PIO_ABCDSR_P21_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P21(value) (PIO_ABCDSR_P21_Msk & ((value) << PIO_ABCDSR_P21_Pos)) +#define PIO_ABCDSR_P22_Pos _U_(22) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P22_Msk (_U_(0x1) << PIO_ABCDSR_P22_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P22(value) (PIO_ABCDSR_P22_Msk & ((value) << PIO_ABCDSR_P22_Pos)) +#define PIO_ABCDSR_P23_Pos _U_(23) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P23_Msk (_U_(0x1) << PIO_ABCDSR_P23_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P23(value) (PIO_ABCDSR_P23_Msk & ((value) << PIO_ABCDSR_P23_Pos)) +#define PIO_ABCDSR_P24_Pos _U_(24) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P24_Msk (_U_(0x1) << PIO_ABCDSR_P24_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P24(value) (PIO_ABCDSR_P24_Msk & ((value) << PIO_ABCDSR_P24_Pos)) +#define PIO_ABCDSR_P25_Pos _U_(25) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P25_Msk (_U_(0x1) << PIO_ABCDSR_P25_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P25(value) (PIO_ABCDSR_P25_Msk & ((value) << PIO_ABCDSR_P25_Pos)) +#define PIO_ABCDSR_P26_Pos _U_(26) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P26_Msk (_U_(0x1) << PIO_ABCDSR_P26_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P26(value) (PIO_ABCDSR_P26_Msk & ((value) << PIO_ABCDSR_P26_Pos)) +#define PIO_ABCDSR_P27_Pos _U_(27) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P27_Msk (_U_(0x1) << PIO_ABCDSR_P27_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P27(value) (PIO_ABCDSR_P27_Msk & ((value) << PIO_ABCDSR_P27_Pos)) +#define PIO_ABCDSR_P28_Pos _U_(28) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P28_Msk (_U_(0x1) << PIO_ABCDSR_P28_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P28(value) (PIO_ABCDSR_P28_Msk & ((value) << PIO_ABCDSR_P28_Pos)) +#define PIO_ABCDSR_P29_Pos _U_(29) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P29_Msk (_U_(0x1) << PIO_ABCDSR_P29_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P29(value) (PIO_ABCDSR_P29_Msk & ((value) << PIO_ABCDSR_P29_Pos)) +#define PIO_ABCDSR_P30_Pos _U_(30) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P30_Msk (_U_(0x1) << PIO_ABCDSR_P30_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P30(value) (PIO_ABCDSR_P30_Msk & ((value) << PIO_ABCDSR_P30_Pos)) +#define PIO_ABCDSR_P31_Pos _U_(31) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P31_Msk (_U_(0x1) << PIO_ABCDSR_P31_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P31(value) (PIO_ABCDSR_P31_Msk & ((value) << PIO_ABCDSR_P31_Pos)) +#define PIO_ABCDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ABCDSR) Register Mask */ + +#define PIO_ABCDSR_P_Pos _U_(0) /**< (PIO_ABCDSR Position) Peripheral Select */ +#define PIO_ABCDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ABCDSR_P_Pos) /**< (PIO_ABCDSR Mask) P */ +#define PIO_ABCDSR_P(value) (PIO_ABCDSR_P_Msk & ((value) << PIO_ABCDSR_P_Pos)) + +/* -------- PIO_IFSCDR : (PIO Offset: 0x80) ( /W 32) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0_Pos _U_(0) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P0_Msk (_U_(0x1) << PIO_IFSCDR_P0_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P0(value) (PIO_IFSCDR_P0_Msk & ((value) << PIO_IFSCDR_P0_Pos)) +#define PIO_IFSCDR_P1_Pos _U_(1) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P1_Msk (_U_(0x1) << PIO_IFSCDR_P1_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P1(value) (PIO_IFSCDR_P1_Msk & ((value) << PIO_IFSCDR_P1_Pos)) +#define PIO_IFSCDR_P2_Pos _U_(2) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P2_Msk (_U_(0x1) << PIO_IFSCDR_P2_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P2(value) (PIO_IFSCDR_P2_Msk & ((value) << PIO_IFSCDR_P2_Pos)) +#define PIO_IFSCDR_P3_Pos _U_(3) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P3_Msk (_U_(0x1) << PIO_IFSCDR_P3_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P3(value) (PIO_IFSCDR_P3_Msk & ((value) << PIO_IFSCDR_P3_Pos)) +#define PIO_IFSCDR_P4_Pos _U_(4) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P4_Msk (_U_(0x1) << PIO_IFSCDR_P4_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P4(value) (PIO_IFSCDR_P4_Msk & ((value) << PIO_IFSCDR_P4_Pos)) +#define PIO_IFSCDR_P5_Pos _U_(5) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P5_Msk (_U_(0x1) << PIO_IFSCDR_P5_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P5(value) (PIO_IFSCDR_P5_Msk & ((value) << PIO_IFSCDR_P5_Pos)) +#define PIO_IFSCDR_P6_Pos _U_(6) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P6_Msk (_U_(0x1) << PIO_IFSCDR_P6_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P6(value) (PIO_IFSCDR_P6_Msk & ((value) << PIO_IFSCDR_P6_Pos)) +#define PIO_IFSCDR_P7_Pos _U_(7) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P7_Msk (_U_(0x1) << PIO_IFSCDR_P7_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P7(value) (PIO_IFSCDR_P7_Msk & ((value) << PIO_IFSCDR_P7_Pos)) +#define PIO_IFSCDR_P8_Pos _U_(8) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P8_Msk (_U_(0x1) << PIO_IFSCDR_P8_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P8(value) (PIO_IFSCDR_P8_Msk & ((value) << PIO_IFSCDR_P8_Pos)) +#define PIO_IFSCDR_P9_Pos _U_(9) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P9_Msk (_U_(0x1) << PIO_IFSCDR_P9_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P9(value) (PIO_IFSCDR_P9_Msk & ((value) << PIO_IFSCDR_P9_Pos)) +#define PIO_IFSCDR_P10_Pos _U_(10) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P10_Msk (_U_(0x1) << PIO_IFSCDR_P10_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P10(value) (PIO_IFSCDR_P10_Msk & ((value) << PIO_IFSCDR_P10_Pos)) +#define PIO_IFSCDR_P11_Pos _U_(11) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P11_Msk (_U_(0x1) << PIO_IFSCDR_P11_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P11(value) (PIO_IFSCDR_P11_Msk & ((value) << PIO_IFSCDR_P11_Pos)) +#define PIO_IFSCDR_P12_Pos _U_(12) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P12_Msk (_U_(0x1) << PIO_IFSCDR_P12_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P12(value) (PIO_IFSCDR_P12_Msk & ((value) << PIO_IFSCDR_P12_Pos)) +#define PIO_IFSCDR_P13_Pos _U_(13) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P13_Msk (_U_(0x1) << PIO_IFSCDR_P13_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P13(value) (PIO_IFSCDR_P13_Msk & ((value) << PIO_IFSCDR_P13_Pos)) +#define PIO_IFSCDR_P14_Pos _U_(14) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P14_Msk (_U_(0x1) << PIO_IFSCDR_P14_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P14(value) (PIO_IFSCDR_P14_Msk & ((value) << PIO_IFSCDR_P14_Pos)) +#define PIO_IFSCDR_P15_Pos _U_(15) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P15_Msk (_U_(0x1) << PIO_IFSCDR_P15_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P15(value) (PIO_IFSCDR_P15_Msk & ((value) << PIO_IFSCDR_P15_Pos)) +#define PIO_IFSCDR_P16_Pos _U_(16) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P16_Msk (_U_(0x1) << PIO_IFSCDR_P16_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P16(value) (PIO_IFSCDR_P16_Msk & ((value) << PIO_IFSCDR_P16_Pos)) +#define PIO_IFSCDR_P17_Pos _U_(17) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P17_Msk (_U_(0x1) << PIO_IFSCDR_P17_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P17(value) (PIO_IFSCDR_P17_Msk & ((value) << PIO_IFSCDR_P17_Pos)) +#define PIO_IFSCDR_P18_Pos _U_(18) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P18_Msk (_U_(0x1) << PIO_IFSCDR_P18_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P18(value) (PIO_IFSCDR_P18_Msk & ((value) << PIO_IFSCDR_P18_Pos)) +#define PIO_IFSCDR_P19_Pos _U_(19) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P19_Msk (_U_(0x1) << PIO_IFSCDR_P19_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P19(value) (PIO_IFSCDR_P19_Msk & ((value) << PIO_IFSCDR_P19_Pos)) +#define PIO_IFSCDR_P20_Pos _U_(20) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P20_Msk (_U_(0x1) << PIO_IFSCDR_P20_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P20(value) (PIO_IFSCDR_P20_Msk & ((value) << PIO_IFSCDR_P20_Pos)) +#define PIO_IFSCDR_P21_Pos _U_(21) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P21_Msk (_U_(0x1) << PIO_IFSCDR_P21_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P21(value) (PIO_IFSCDR_P21_Msk & ((value) << PIO_IFSCDR_P21_Pos)) +#define PIO_IFSCDR_P22_Pos _U_(22) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P22_Msk (_U_(0x1) << PIO_IFSCDR_P22_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P22(value) (PIO_IFSCDR_P22_Msk & ((value) << PIO_IFSCDR_P22_Pos)) +#define PIO_IFSCDR_P23_Pos _U_(23) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P23_Msk (_U_(0x1) << PIO_IFSCDR_P23_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P23(value) (PIO_IFSCDR_P23_Msk & ((value) << PIO_IFSCDR_P23_Pos)) +#define PIO_IFSCDR_P24_Pos _U_(24) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P24_Msk (_U_(0x1) << PIO_IFSCDR_P24_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P24(value) (PIO_IFSCDR_P24_Msk & ((value) << PIO_IFSCDR_P24_Pos)) +#define PIO_IFSCDR_P25_Pos _U_(25) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P25_Msk (_U_(0x1) << PIO_IFSCDR_P25_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P25(value) (PIO_IFSCDR_P25_Msk & ((value) << PIO_IFSCDR_P25_Pos)) +#define PIO_IFSCDR_P26_Pos _U_(26) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P26_Msk (_U_(0x1) << PIO_IFSCDR_P26_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P26(value) (PIO_IFSCDR_P26_Msk & ((value) << PIO_IFSCDR_P26_Pos)) +#define PIO_IFSCDR_P27_Pos _U_(27) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P27_Msk (_U_(0x1) << PIO_IFSCDR_P27_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P27(value) (PIO_IFSCDR_P27_Msk & ((value) << PIO_IFSCDR_P27_Pos)) +#define PIO_IFSCDR_P28_Pos _U_(28) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P28_Msk (_U_(0x1) << PIO_IFSCDR_P28_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P28(value) (PIO_IFSCDR_P28_Msk & ((value) << PIO_IFSCDR_P28_Pos)) +#define PIO_IFSCDR_P29_Pos _U_(29) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P29_Msk (_U_(0x1) << PIO_IFSCDR_P29_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P29(value) (PIO_IFSCDR_P29_Msk & ((value) << PIO_IFSCDR_P29_Pos)) +#define PIO_IFSCDR_P30_Pos _U_(30) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P30_Msk (_U_(0x1) << PIO_IFSCDR_P30_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P30(value) (PIO_IFSCDR_P30_Msk & ((value) << PIO_IFSCDR_P30_Pos)) +#define PIO_IFSCDR_P31_Pos _U_(31) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P31_Msk (_U_(0x1) << PIO_IFSCDR_P31_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P31(value) (PIO_IFSCDR_P31_Msk & ((value) << PIO_IFSCDR_P31_Pos)) +#define PIO_IFSCDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCDR) Register Mask */ + +#define PIO_IFSCDR_P_Pos _U_(0) /**< (PIO_IFSCDR Position) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCDR_P_Pos) /**< (PIO_IFSCDR Mask) P */ +#define PIO_IFSCDR_P(value) (PIO_IFSCDR_P_Msk & ((value) << PIO_IFSCDR_P_Pos)) + +/* -------- PIO_IFSCER : (PIO Offset: 0x84) ( /W 32) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0_Pos _U_(0) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P0_Msk (_U_(0x1) << PIO_IFSCER_P0_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P0(value) (PIO_IFSCER_P0_Msk & ((value) << PIO_IFSCER_P0_Pos)) +#define PIO_IFSCER_P1_Pos _U_(1) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P1_Msk (_U_(0x1) << PIO_IFSCER_P1_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P1(value) (PIO_IFSCER_P1_Msk & ((value) << PIO_IFSCER_P1_Pos)) +#define PIO_IFSCER_P2_Pos _U_(2) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P2_Msk (_U_(0x1) << PIO_IFSCER_P2_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P2(value) (PIO_IFSCER_P2_Msk & ((value) << PIO_IFSCER_P2_Pos)) +#define PIO_IFSCER_P3_Pos _U_(3) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P3_Msk (_U_(0x1) << PIO_IFSCER_P3_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P3(value) (PIO_IFSCER_P3_Msk & ((value) << PIO_IFSCER_P3_Pos)) +#define PIO_IFSCER_P4_Pos _U_(4) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P4_Msk (_U_(0x1) << PIO_IFSCER_P4_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P4(value) (PIO_IFSCER_P4_Msk & ((value) << PIO_IFSCER_P4_Pos)) +#define PIO_IFSCER_P5_Pos _U_(5) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P5_Msk (_U_(0x1) << PIO_IFSCER_P5_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P5(value) (PIO_IFSCER_P5_Msk & ((value) << PIO_IFSCER_P5_Pos)) +#define PIO_IFSCER_P6_Pos _U_(6) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P6_Msk (_U_(0x1) << PIO_IFSCER_P6_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P6(value) (PIO_IFSCER_P6_Msk & ((value) << PIO_IFSCER_P6_Pos)) +#define PIO_IFSCER_P7_Pos _U_(7) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P7_Msk (_U_(0x1) << PIO_IFSCER_P7_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P7(value) (PIO_IFSCER_P7_Msk & ((value) << PIO_IFSCER_P7_Pos)) +#define PIO_IFSCER_P8_Pos _U_(8) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P8_Msk (_U_(0x1) << PIO_IFSCER_P8_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P8(value) (PIO_IFSCER_P8_Msk & ((value) << PIO_IFSCER_P8_Pos)) +#define PIO_IFSCER_P9_Pos _U_(9) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P9_Msk (_U_(0x1) << PIO_IFSCER_P9_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P9(value) (PIO_IFSCER_P9_Msk & ((value) << PIO_IFSCER_P9_Pos)) +#define PIO_IFSCER_P10_Pos _U_(10) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P10_Msk (_U_(0x1) << PIO_IFSCER_P10_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P10(value) (PIO_IFSCER_P10_Msk & ((value) << PIO_IFSCER_P10_Pos)) +#define PIO_IFSCER_P11_Pos _U_(11) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P11_Msk (_U_(0x1) << PIO_IFSCER_P11_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P11(value) (PIO_IFSCER_P11_Msk & ((value) << PIO_IFSCER_P11_Pos)) +#define PIO_IFSCER_P12_Pos _U_(12) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P12_Msk (_U_(0x1) << PIO_IFSCER_P12_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P12(value) (PIO_IFSCER_P12_Msk & ((value) << PIO_IFSCER_P12_Pos)) +#define PIO_IFSCER_P13_Pos _U_(13) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P13_Msk (_U_(0x1) << PIO_IFSCER_P13_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P13(value) (PIO_IFSCER_P13_Msk & ((value) << PIO_IFSCER_P13_Pos)) +#define PIO_IFSCER_P14_Pos _U_(14) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P14_Msk (_U_(0x1) << PIO_IFSCER_P14_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P14(value) (PIO_IFSCER_P14_Msk & ((value) << PIO_IFSCER_P14_Pos)) +#define PIO_IFSCER_P15_Pos _U_(15) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P15_Msk (_U_(0x1) << PIO_IFSCER_P15_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P15(value) (PIO_IFSCER_P15_Msk & ((value) << PIO_IFSCER_P15_Pos)) +#define PIO_IFSCER_P16_Pos _U_(16) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P16_Msk (_U_(0x1) << PIO_IFSCER_P16_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P16(value) (PIO_IFSCER_P16_Msk & ((value) << PIO_IFSCER_P16_Pos)) +#define PIO_IFSCER_P17_Pos _U_(17) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P17_Msk (_U_(0x1) << PIO_IFSCER_P17_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P17(value) (PIO_IFSCER_P17_Msk & ((value) << PIO_IFSCER_P17_Pos)) +#define PIO_IFSCER_P18_Pos _U_(18) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P18_Msk (_U_(0x1) << PIO_IFSCER_P18_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P18(value) (PIO_IFSCER_P18_Msk & ((value) << PIO_IFSCER_P18_Pos)) +#define PIO_IFSCER_P19_Pos _U_(19) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P19_Msk (_U_(0x1) << PIO_IFSCER_P19_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P19(value) (PIO_IFSCER_P19_Msk & ((value) << PIO_IFSCER_P19_Pos)) +#define PIO_IFSCER_P20_Pos _U_(20) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P20_Msk (_U_(0x1) << PIO_IFSCER_P20_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P20(value) (PIO_IFSCER_P20_Msk & ((value) << PIO_IFSCER_P20_Pos)) +#define PIO_IFSCER_P21_Pos _U_(21) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P21_Msk (_U_(0x1) << PIO_IFSCER_P21_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P21(value) (PIO_IFSCER_P21_Msk & ((value) << PIO_IFSCER_P21_Pos)) +#define PIO_IFSCER_P22_Pos _U_(22) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P22_Msk (_U_(0x1) << PIO_IFSCER_P22_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P22(value) (PIO_IFSCER_P22_Msk & ((value) << PIO_IFSCER_P22_Pos)) +#define PIO_IFSCER_P23_Pos _U_(23) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P23_Msk (_U_(0x1) << PIO_IFSCER_P23_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P23(value) (PIO_IFSCER_P23_Msk & ((value) << PIO_IFSCER_P23_Pos)) +#define PIO_IFSCER_P24_Pos _U_(24) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P24_Msk (_U_(0x1) << PIO_IFSCER_P24_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P24(value) (PIO_IFSCER_P24_Msk & ((value) << PIO_IFSCER_P24_Pos)) +#define PIO_IFSCER_P25_Pos _U_(25) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P25_Msk (_U_(0x1) << PIO_IFSCER_P25_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P25(value) (PIO_IFSCER_P25_Msk & ((value) << PIO_IFSCER_P25_Pos)) +#define PIO_IFSCER_P26_Pos _U_(26) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P26_Msk (_U_(0x1) << PIO_IFSCER_P26_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P26(value) (PIO_IFSCER_P26_Msk & ((value) << PIO_IFSCER_P26_Pos)) +#define PIO_IFSCER_P27_Pos _U_(27) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P27_Msk (_U_(0x1) << PIO_IFSCER_P27_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P27(value) (PIO_IFSCER_P27_Msk & ((value) << PIO_IFSCER_P27_Pos)) +#define PIO_IFSCER_P28_Pos _U_(28) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P28_Msk (_U_(0x1) << PIO_IFSCER_P28_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P28(value) (PIO_IFSCER_P28_Msk & ((value) << PIO_IFSCER_P28_Pos)) +#define PIO_IFSCER_P29_Pos _U_(29) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P29_Msk (_U_(0x1) << PIO_IFSCER_P29_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P29(value) (PIO_IFSCER_P29_Msk & ((value) << PIO_IFSCER_P29_Pos)) +#define PIO_IFSCER_P30_Pos _U_(30) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P30_Msk (_U_(0x1) << PIO_IFSCER_P30_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P30(value) (PIO_IFSCER_P30_Msk & ((value) << PIO_IFSCER_P30_Pos)) +#define PIO_IFSCER_P31_Pos _U_(31) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P31_Msk (_U_(0x1) << PIO_IFSCER_P31_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P31(value) (PIO_IFSCER_P31_Msk & ((value) << PIO_IFSCER_P31_Pos)) +#define PIO_IFSCER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCER) Register Mask */ + +#define PIO_IFSCER_P_Pos _U_(0) /**< (PIO_IFSCER Position) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCER_P_Pos) /**< (PIO_IFSCER Mask) P */ +#define PIO_IFSCER_P(value) (PIO_IFSCER_P_Msk & ((value) << PIO_IFSCER_P_Pos)) + +/* -------- PIO_IFSCSR : (PIO Offset: 0x88) ( R/ 32) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0_Pos _U_(0) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P0_Msk (_U_(0x1) << PIO_IFSCSR_P0_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P0(value) (PIO_IFSCSR_P0_Msk & ((value) << PIO_IFSCSR_P0_Pos)) +#define PIO_IFSCSR_P1_Pos _U_(1) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P1_Msk (_U_(0x1) << PIO_IFSCSR_P1_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P1(value) (PIO_IFSCSR_P1_Msk & ((value) << PIO_IFSCSR_P1_Pos)) +#define PIO_IFSCSR_P2_Pos _U_(2) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P2_Msk (_U_(0x1) << PIO_IFSCSR_P2_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P2(value) (PIO_IFSCSR_P2_Msk & ((value) << PIO_IFSCSR_P2_Pos)) +#define PIO_IFSCSR_P3_Pos _U_(3) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P3_Msk (_U_(0x1) << PIO_IFSCSR_P3_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P3(value) (PIO_IFSCSR_P3_Msk & ((value) << PIO_IFSCSR_P3_Pos)) +#define PIO_IFSCSR_P4_Pos _U_(4) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P4_Msk (_U_(0x1) << PIO_IFSCSR_P4_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P4(value) (PIO_IFSCSR_P4_Msk & ((value) << PIO_IFSCSR_P4_Pos)) +#define PIO_IFSCSR_P5_Pos _U_(5) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P5_Msk (_U_(0x1) << PIO_IFSCSR_P5_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P5(value) (PIO_IFSCSR_P5_Msk & ((value) << PIO_IFSCSR_P5_Pos)) +#define PIO_IFSCSR_P6_Pos _U_(6) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P6_Msk (_U_(0x1) << PIO_IFSCSR_P6_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P6(value) (PIO_IFSCSR_P6_Msk & ((value) << PIO_IFSCSR_P6_Pos)) +#define PIO_IFSCSR_P7_Pos _U_(7) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P7_Msk (_U_(0x1) << PIO_IFSCSR_P7_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P7(value) (PIO_IFSCSR_P7_Msk & ((value) << PIO_IFSCSR_P7_Pos)) +#define PIO_IFSCSR_P8_Pos _U_(8) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P8_Msk (_U_(0x1) << PIO_IFSCSR_P8_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P8(value) (PIO_IFSCSR_P8_Msk & ((value) << PIO_IFSCSR_P8_Pos)) +#define PIO_IFSCSR_P9_Pos _U_(9) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P9_Msk (_U_(0x1) << PIO_IFSCSR_P9_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P9(value) (PIO_IFSCSR_P9_Msk & ((value) << PIO_IFSCSR_P9_Pos)) +#define PIO_IFSCSR_P10_Pos _U_(10) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P10_Msk (_U_(0x1) << PIO_IFSCSR_P10_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P10(value) (PIO_IFSCSR_P10_Msk & ((value) << PIO_IFSCSR_P10_Pos)) +#define PIO_IFSCSR_P11_Pos _U_(11) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P11_Msk (_U_(0x1) << PIO_IFSCSR_P11_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P11(value) (PIO_IFSCSR_P11_Msk & ((value) << PIO_IFSCSR_P11_Pos)) +#define PIO_IFSCSR_P12_Pos _U_(12) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P12_Msk (_U_(0x1) << PIO_IFSCSR_P12_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P12(value) (PIO_IFSCSR_P12_Msk & ((value) << PIO_IFSCSR_P12_Pos)) +#define PIO_IFSCSR_P13_Pos _U_(13) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P13_Msk (_U_(0x1) << PIO_IFSCSR_P13_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P13(value) (PIO_IFSCSR_P13_Msk & ((value) << PIO_IFSCSR_P13_Pos)) +#define PIO_IFSCSR_P14_Pos _U_(14) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P14_Msk (_U_(0x1) << PIO_IFSCSR_P14_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P14(value) (PIO_IFSCSR_P14_Msk & ((value) << PIO_IFSCSR_P14_Pos)) +#define PIO_IFSCSR_P15_Pos _U_(15) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P15_Msk (_U_(0x1) << PIO_IFSCSR_P15_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P15(value) (PIO_IFSCSR_P15_Msk & ((value) << PIO_IFSCSR_P15_Pos)) +#define PIO_IFSCSR_P16_Pos _U_(16) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P16_Msk (_U_(0x1) << PIO_IFSCSR_P16_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P16(value) (PIO_IFSCSR_P16_Msk & ((value) << PIO_IFSCSR_P16_Pos)) +#define PIO_IFSCSR_P17_Pos _U_(17) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P17_Msk (_U_(0x1) << PIO_IFSCSR_P17_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P17(value) (PIO_IFSCSR_P17_Msk & ((value) << PIO_IFSCSR_P17_Pos)) +#define PIO_IFSCSR_P18_Pos _U_(18) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P18_Msk (_U_(0x1) << PIO_IFSCSR_P18_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P18(value) (PIO_IFSCSR_P18_Msk & ((value) << PIO_IFSCSR_P18_Pos)) +#define PIO_IFSCSR_P19_Pos _U_(19) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P19_Msk (_U_(0x1) << PIO_IFSCSR_P19_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P19(value) (PIO_IFSCSR_P19_Msk & ((value) << PIO_IFSCSR_P19_Pos)) +#define PIO_IFSCSR_P20_Pos _U_(20) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P20_Msk (_U_(0x1) << PIO_IFSCSR_P20_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P20(value) (PIO_IFSCSR_P20_Msk & ((value) << PIO_IFSCSR_P20_Pos)) +#define PIO_IFSCSR_P21_Pos _U_(21) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P21_Msk (_U_(0x1) << PIO_IFSCSR_P21_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P21(value) (PIO_IFSCSR_P21_Msk & ((value) << PIO_IFSCSR_P21_Pos)) +#define PIO_IFSCSR_P22_Pos _U_(22) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P22_Msk (_U_(0x1) << PIO_IFSCSR_P22_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P22(value) (PIO_IFSCSR_P22_Msk & ((value) << PIO_IFSCSR_P22_Pos)) +#define PIO_IFSCSR_P23_Pos _U_(23) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P23_Msk (_U_(0x1) << PIO_IFSCSR_P23_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P23(value) (PIO_IFSCSR_P23_Msk & ((value) << PIO_IFSCSR_P23_Pos)) +#define PIO_IFSCSR_P24_Pos _U_(24) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P24_Msk (_U_(0x1) << PIO_IFSCSR_P24_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P24(value) (PIO_IFSCSR_P24_Msk & ((value) << PIO_IFSCSR_P24_Pos)) +#define PIO_IFSCSR_P25_Pos _U_(25) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P25_Msk (_U_(0x1) << PIO_IFSCSR_P25_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P25(value) (PIO_IFSCSR_P25_Msk & ((value) << PIO_IFSCSR_P25_Pos)) +#define PIO_IFSCSR_P26_Pos _U_(26) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P26_Msk (_U_(0x1) << PIO_IFSCSR_P26_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P26(value) (PIO_IFSCSR_P26_Msk & ((value) << PIO_IFSCSR_P26_Pos)) +#define PIO_IFSCSR_P27_Pos _U_(27) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P27_Msk (_U_(0x1) << PIO_IFSCSR_P27_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P27(value) (PIO_IFSCSR_P27_Msk & ((value) << PIO_IFSCSR_P27_Pos)) +#define PIO_IFSCSR_P28_Pos _U_(28) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P28_Msk (_U_(0x1) << PIO_IFSCSR_P28_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P28(value) (PIO_IFSCSR_P28_Msk & ((value) << PIO_IFSCSR_P28_Pos)) +#define PIO_IFSCSR_P29_Pos _U_(29) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P29_Msk (_U_(0x1) << PIO_IFSCSR_P29_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P29(value) (PIO_IFSCSR_P29_Msk & ((value) << PIO_IFSCSR_P29_Pos)) +#define PIO_IFSCSR_P30_Pos _U_(30) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P30_Msk (_U_(0x1) << PIO_IFSCSR_P30_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P30(value) (PIO_IFSCSR_P30_Msk & ((value) << PIO_IFSCSR_P30_Pos)) +#define PIO_IFSCSR_P31_Pos _U_(31) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P31_Msk (_U_(0x1) << PIO_IFSCSR_P31_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P31(value) (PIO_IFSCSR_P31_Msk & ((value) << PIO_IFSCSR_P31_Pos)) +#define PIO_IFSCSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCSR) Register Mask */ + +#define PIO_IFSCSR_P_Pos _U_(0) /**< (PIO_IFSCSR Position) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCSR_P_Pos) /**< (PIO_IFSCSR Mask) P */ +#define PIO_IFSCSR_P(value) (PIO_IFSCSR_P_Msk & ((value) << PIO_IFSCSR_P_Pos)) + +/* -------- PIO_SCDR : (PIO Offset: 0x8C) (R/W 32) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos _U_(0) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Position */ +#define PIO_SCDR_DIV_Msk (_U_(0x3FFF) << PIO_SCDR_DIV_Pos) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Mask */ +#define PIO_SCDR_DIV(value) (PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)) +#define PIO_SCDR_Msk _U_(0x00003FFF) /**< (PIO_SCDR) Register Mask */ + + +/* -------- PIO_PPDDR : (PIO Offset: 0x90) ( /W 32) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0_Pos _U_(0) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P0_Msk (_U_(0x1) << PIO_PPDDR_P0_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P0(value) (PIO_PPDDR_P0_Msk & ((value) << PIO_PPDDR_P0_Pos)) +#define PIO_PPDDR_P1_Pos _U_(1) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P1_Msk (_U_(0x1) << PIO_PPDDR_P1_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P1(value) (PIO_PPDDR_P1_Msk & ((value) << PIO_PPDDR_P1_Pos)) +#define PIO_PPDDR_P2_Pos _U_(2) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P2_Msk (_U_(0x1) << PIO_PPDDR_P2_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P2(value) (PIO_PPDDR_P2_Msk & ((value) << PIO_PPDDR_P2_Pos)) +#define PIO_PPDDR_P3_Pos _U_(3) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P3_Msk (_U_(0x1) << PIO_PPDDR_P3_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P3(value) (PIO_PPDDR_P3_Msk & ((value) << PIO_PPDDR_P3_Pos)) +#define PIO_PPDDR_P4_Pos _U_(4) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P4_Msk (_U_(0x1) << PIO_PPDDR_P4_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P4(value) (PIO_PPDDR_P4_Msk & ((value) << PIO_PPDDR_P4_Pos)) +#define PIO_PPDDR_P5_Pos _U_(5) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P5_Msk (_U_(0x1) << PIO_PPDDR_P5_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P5(value) (PIO_PPDDR_P5_Msk & ((value) << PIO_PPDDR_P5_Pos)) +#define PIO_PPDDR_P6_Pos _U_(6) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P6_Msk (_U_(0x1) << PIO_PPDDR_P6_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P6(value) (PIO_PPDDR_P6_Msk & ((value) << PIO_PPDDR_P6_Pos)) +#define PIO_PPDDR_P7_Pos _U_(7) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P7_Msk (_U_(0x1) << PIO_PPDDR_P7_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P7(value) (PIO_PPDDR_P7_Msk & ((value) << PIO_PPDDR_P7_Pos)) +#define PIO_PPDDR_P8_Pos _U_(8) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P8_Msk (_U_(0x1) << PIO_PPDDR_P8_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P8(value) (PIO_PPDDR_P8_Msk & ((value) << PIO_PPDDR_P8_Pos)) +#define PIO_PPDDR_P9_Pos _U_(9) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P9_Msk (_U_(0x1) << PIO_PPDDR_P9_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P9(value) (PIO_PPDDR_P9_Msk & ((value) << PIO_PPDDR_P9_Pos)) +#define PIO_PPDDR_P10_Pos _U_(10) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P10_Msk (_U_(0x1) << PIO_PPDDR_P10_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P10(value) (PIO_PPDDR_P10_Msk & ((value) << PIO_PPDDR_P10_Pos)) +#define PIO_PPDDR_P11_Pos _U_(11) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P11_Msk (_U_(0x1) << PIO_PPDDR_P11_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P11(value) (PIO_PPDDR_P11_Msk & ((value) << PIO_PPDDR_P11_Pos)) +#define PIO_PPDDR_P12_Pos _U_(12) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P12_Msk (_U_(0x1) << PIO_PPDDR_P12_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P12(value) (PIO_PPDDR_P12_Msk & ((value) << PIO_PPDDR_P12_Pos)) +#define PIO_PPDDR_P13_Pos _U_(13) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P13_Msk (_U_(0x1) << PIO_PPDDR_P13_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P13(value) (PIO_PPDDR_P13_Msk & ((value) << PIO_PPDDR_P13_Pos)) +#define PIO_PPDDR_P14_Pos _U_(14) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P14_Msk (_U_(0x1) << PIO_PPDDR_P14_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P14(value) (PIO_PPDDR_P14_Msk & ((value) << PIO_PPDDR_P14_Pos)) +#define PIO_PPDDR_P15_Pos _U_(15) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P15_Msk (_U_(0x1) << PIO_PPDDR_P15_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P15(value) (PIO_PPDDR_P15_Msk & ((value) << PIO_PPDDR_P15_Pos)) +#define PIO_PPDDR_P16_Pos _U_(16) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P16_Msk (_U_(0x1) << PIO_PPDDR_P16_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P16(value) (PIO_PPDDR_P16_Msk & ((value) << PIO_PPDDR_P16_Pos)) +#define PIO_PPDDR_P17_Pos _U_(17) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P17_Msk (_U_(0x1) << PIO_PPDDR_P17_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P17(value) (PIO_PPDDR_P17_Msk & ((value) << PIO_PPDDR_P17_Pos)) +#define PIO_PPDDR_P18_Pos _U_(18) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P18_Msk (_U_(0x1) << PIO_PPDDR_P18_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P18(value) (PIO_PPDDR_P18_Msk & ((value) << PIO_PPDDR_P18_Pos)) +#define PIO_PPDDR_P19_Pos _U_(19) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P19_Msk (_U_(0x1) << PIO_PPDDR_P19_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P19(value) (PIO_PPDDR_P19_Msk & ((value) << PIO_PPDDR_P19_Pos)) +#define PIO_PPDDR_P20_Pos _U_(20) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P20_Msk (_U_(0x1) << PIO_PPDDR_P20_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P20(value) (PIO_PPDDR_P20_Msk & ((value) << PIO_PPDDR_P20_Pos)) +#define PIO_PPDDR_P21_Pos _U_(21) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P21_Msk (_U_(0x1) << PIO_PPDDR_P21_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P21(value) (PIO_PPDDR_P21_Msk & ((value) << PIO_PPDDR_P21_Pos)) +#define PIO_PPDDR_P22_Pos _U_(22) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P22_Msk (_U_(0x1) << PIO_PPDDR_P22_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P22(value) (PIO_PPDDR_P22_Msk & ((value) << PIO_PPDDR_P22_Pos)) +#define PIO_PPDDR_P23_Pos _U_(23) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P23_Msk (_U_(0x1) << PIO_PPDDR_P23_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P23(value) (PIO_PPDDR_P23_Msk & ((value) << PIO_PPDDR_P23_Pos)) +#define PIO_PPDDR_P24_Pos _U_(24) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P24_Msk (_U_(0x1) << PIO_PPDDR_P24_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P24(value) (PIO_PPDDR_P24_Msk & ((value) << PIO_PPDDR_P24_Pos)) +#define PIO_PPDDR_P25_Pos _U_(25) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P25_Msk (_U_(0x1) << PIO_PPDDR_P25_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P25(value) (PIO_PPDDR_P25_Msk & ((value) << PIO_PPDDR_P25_Pos)) +#define PIO_PPDDR_P26_Pos _U_(26) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P26_Msk (_U_(0x1) << PIO_PPDDR_P26_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P26(value) (PIO_PPDDR_P26_Msk & ((value) << PIO_PPDDR_P26_Pos)) +#define PIO_PPDDR_P27_Pos _U_(27) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P27_Msk (_U_(0x1) << PIO_PPDDR_P27_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P27(value) (PIO_PPDDR_P27_Msk & ((value) << PIO_PPDDR_P27_Pos)) +#define PIO_PPDDR_P28_Pos _U_(28) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P28_Msk (_U_(0x1) << PIO_PPDDR_P28_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P28(value) (PIO_PPDDR_P28_Msk & ((value) << PIO_PPDDR_P28_Pos)) +#define PIO_PPDDR_P29_Pos _U_(29) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P29_Msk (_U_(0x1) << PIO_PPDDR_P29_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P29(value) (PIO_PPDDR_P29_Msk & ((value) << PIO_PPDDR_P29_Pos)) +#define PIO_PPDDR_P30_Pos _U_(30) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P30_Msk (_U_(0x1) << PIO_PPDDR_P30_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P30(value) (PIO_PPDDR_P30_Msk & ((value) << PIO_PPDDR_P30_Pos)) +#define PIO_PPDDR_P31_Pos _U_(31) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P31_Msk (_U_(0x1) << PIO_PPDDR_P31_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P31(value) (PIO_PPDDR_P31_Msk & ((value) << PIO_PPDDR_P31_Pos)) +#define PIO_PPDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDDR) Register Mask */ + +#define PIO_PPDDR_P_Pos _U_(0) /**< (PIO_PPDDR Position) Pull-Down Disable */ +#define PIO_PPDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDDR_P_Pos) /**< (PIO_PPDDR Mask) P */ +#define PIO_PPDDR_P(value) (PIO_PPDDR_P_Msk & ((value) << PIO_PPDDR_P_Pos)) + +/* -------- PIO_PPDER : (PIO Offset: 0x94) ( /W 32) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0_Pos _U_(0) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P0_Msk (_U_(0x1) << PIO_PPDER_P0_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P0(value) (PIO_PPDER_P0_Msk & ((value) << PIO_PPDER_P0_Pos)) +#define PIO_PPDER_P1_Pos _U_(1) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P1_Msk (_U_(0x1) << PIO_PPDER_P1_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P1(value) (PIO_PPDER_P1_Msk & ((value) << PIO_PPDER_P1_Pos)) +#define PIO_PPDER_P2_Pos _U_(2) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P2_Msk (_U_(0x1) << PIO_PPDER_P2_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P2(value) (PIO_PPDER_P2_Msk & ((value) << PIO_PPDER_P2_Pos)) +#define PIO_PPDER_P3_Pos _U_(3) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P3_Msk (_U_(0x1) << PIO_PPDER_P3_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P3(value) (PIO_PPDER_P3_Msk & ((value) << PIO_PPDER_P3_Pos)) +#define PIO_PPDER_P4_Pos _U_(4) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P4_Msk (_U_(0x1) << PIO_PPDER_P4_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P4(value) (PIO_PPDER_P4_Msk & ((value) << PIO_PPDER_P4_Pos)) +#define PIO_PPDER_P5_Pos _U_(5) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P5_Msk (_U_(0x1) << PIO_PPDER_P5_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P5(value) (PIO_PPDER_P5_Msk & ((value) << PIO_PPDER_P5_Pos)) +#define PIO_PPDER_P6_Pos _U_(6) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P6_Msk (_U_(0x1) << PIO_PPDER_P6_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P6(value) (PIO_PPDER_P6_Msk & ((value) << PIO_PPDER_P6_Pos)) +#define PIO_PPDER_P7_Pos _U_(7) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P7_Msk (_U_(0x1) << PIO_PPDER_P7_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P7(value) (PIO_PPDER_P7_Msk & ((value) << PIO_PPDER_P7_Pos)) +#define PIO_PPDER_P8_Pos _U_(8) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P8_Msk (_U_(0x1) << PIO_PPDER_P8_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P8(value) (PIO_PPDER_P8_Msk & ((value) << PIO_PPDER_P8_Pos)) +#define PIO_PPDER_P9_Pos _U_(9) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P9_Msk (_U_(0x1) << PIO_PPDER_P9_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P9(value) (PIO_PPDER_P9_Msk & ((value) << PIO_PPDER_P9_Pos)) +#define PIO_PPDER_P10_Pos _U_(10) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P10_Msk (_U_(0x1) << PIO_PPDER_P10_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P10(value) (PIO_PPDER_P10_Msk & ((value) << PIO_PPDER_P10_Pos)) +#define PIO_PPDER_P11_Pos _U_(11) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P11_Msk (_U_(0x1) << PIO_PPDER_P11_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P11(value) (PIO_PPDER_P11_Msk & ((value) << PIO_PPDER_P11_Pos)) +#define PIO_PPDER_P12_Pos _U_(12) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P12_Msk (_U_(0x1) << PIO_PPDER_P12_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P12(value) (PIO_PPDER_P12_Msk & ((value) << PIO_PPDER_P12_Pos)) +#define PIO_PPDER_P13_Pos _U_(13) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P13_Msk (_U_(0x1) << PIO_PPDER_P13_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P13(value) (PIO_PPDER_P13_Msk & ((value) << PIO_PPDER_P13_Pos)) +#define PIO_PPDER_P14_Pos _U_(14) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P14_Msk (_U_(0x1) << PIO_PPDER_P14_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P14(value) (PIO_PPDER_P14_Msk & ((value) << PIO_PPDER_P14_Pos)) +#define PIO_PPDER_P15_Pos _U_(15) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P15_Msk (_U_(0x1) << PIO_PPDER_P15_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P15(value) (PIO_PPDER_P15_Msk & ((value) << PIO_PPDER_P15_Pos)) +#define PIO_PPDER_P16_Pos _U_(16) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P16_Msk (_U_(0x1) << PIO_PPDER_P16_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P16(value) (PIO_PPDER_P16_Msk & ((value) << PIO_PPDER_P16_Pos)) +#define PIO_PPDER_P17_Pos _U_(17) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P17_Msk (_U_(0x1) << PIO_PPDER_P17_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P17(value) (PIO_PPDER_P17_Msk & ((value) << PIO_PPDER_P17_Pos)) +#define PIO_PPDER_P18_Pos _U_(18) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P18_Msk (_U_(0x1) << PIO_PPDER_P18_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P18(value) (PIO_PPDER_P18_Msk & ((value) << PIO_PPDER_P18_Pos)) +#define PIO_PPDER_P19_Pos _U_(19) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P19_Msk (_U_(0x1) << PIO_PPDER_P19_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P19(value) (PIO_PPDER_P19_Msk & ((value) << PIO_PPDER_P19_Pos)) +#define PIO_PPDER_P20_Pos _U_(20) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P20_Msk (_U_(0x1) << PIO_PPDER_P20_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P20(value) (PIO_PPDER_P20_Msk & ((value) << PIO_PPDER_P20_Pos)) +#define PIO_PPDER_P21_Pos _U_(21) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P21_Msk (_U_(0x1) << PIO_PPDER_P21_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P21(value) (PIO_PPDER_P21_Msk & ((value) << PIO_PPDER_P21_Pos)) +#define PIO_PPDER_P22_Pos _U_(22) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P22_Msk (_U_(0x1) << PIO_PPDER_P22_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P22(value) (PIO_PPDER_P22_Msk & ((value) << PIO_PPDER_P22_Pos)) +#define PIO_PPDER_P23_Pos _U_(23) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P23_Msk (_U_(0x1) << PIO_PPDER_P23_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P23(value) (PIO_PPDER_P23_Msk & ((value) << PIO_PPDER_P23_Pos)) +#define PIO_PPDER_P24_Pos _U_(24) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P24_Msk (_U_(0x1) << PIO_PPDER_P24_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P24(value) (PIO_PPDER_P24_Msk & ((value) << PIO_PPDER_P24_Pos)) +#define PIO_PPDER_P25_Pos _U_(25) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P25_Msk (_U_(0x1) << PIO_PPDER_P25_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P25(value) (PIO_PPDER_P25_Msk & ((value) << PIO_PPDER_P25_Pos)) +#define PIO_PPDER_P26_Pos _U_(26) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P26_Msk (_U_(0x1) << PIO_PPDER_P26_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P26(value) (PIO_PPDER_P26_Msk & ((value) << PIO_PPDER_P26_Pos)) +#define PIO_PPDER_P27_Pos _U_(27) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P27_Msk (_U_(0x1) << PIO_PPDER_P27_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P27(value) (PIO_PPDER_P27_Msk & ((value) << PIO_PPDER_P27_Pos)) +#define PIO_PPDER_P28_Pos _U_(28) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P28_Msk (_U_(0x1) << PIO_PPDER_P28_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P28(value) (PIO_PPDER_P28_Msk & ((value) << PIO_PPDER_P28_Pos)) +#define PIO_PPDER_P29_Pos _U_(29) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P29_Msk (_U_(0x1) << PIO_PPDER_P29_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P29(value) (PIO_PPDER_P29_Msk & ((value) << PIO_PPDER_P29_Pos)) +#define PIO_PPDER_P30_Pos _U_(30) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P30_Msk (_U_(0x1) << PIO_PPDER_P30_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P30(value) (PIO_PPDER_P30_Msk & ((value) << PIO_PPDER_P30_Pos)) +#define PIO_PPDER_P31_Pos _U_(31) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P31_Msk (_U_(0x1) << PIO_PPDER_P31_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P31(value) (PIO_PPDER_P31_Msk & ((value) << PIO_PPDER_P31_Pos)) +#define PIO_PPDER_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDER) Register Mask */ + +#define PIO_PPDER_P_Pos _U_(0) /**< (PIO_PPDER Position) Pull-Down Enable */ +#define PIO_PPDER_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDER_P_Pos) /**< (PIO_PPDER Mask) P */ +#define PIO_PPDER_P(value) (PIO_PPDER_P_Msk & ((value) << PIO_PPDER_P_Pos)) + +/* -------- PIO_PPDSR : (PIO Offset: 0x98) ( R/ 32) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0_Pos _U_(0) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P0_Msk (_U_(0x1) << PIO_PPDSR_P0_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P0(value) (PIO_PPDSR_P0_Msk & ((value) << PIO_PPDSR_P0_Pos)) +#define PIO_PPDSR_P1_Pos _U_(1) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P1_Msk (_U_(0x1) << PIO_PPDSR_P1_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P1(value) (PIO_PPDSR_P1_Msk & ((value) << PIO_PPDSR_P1_Pos)) +#define PIO_PPDSR_P2_Pos _U_(2) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P2_Msk (_U_(0x1) << PIO_PPDSR_P2_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P2(value) (PIO_PPDSR_P2_Msk & ((value) << PIO_PPDSR_P2_Pos)) +#define PIO_PPDSR_P3_Pos _U_(3) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P3_Msk (_U_(0x1) << PIO_PPDSR_P3_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P3(value) (PIO_PPDSR_P3_Msk & ((value) << PIO_PPDSR_P3_Pos)) +#define PIO_PPDSR_P4_Pos _U_(4) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P4_Msk (_U_(0x1) << PIO_PPDSR_P4_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P4(value) (PIO_PPDSR_P4_Msk & ((value) << PIO_PPDSR_P4_Pos)) +#define PIO_PPDSR_P5_Pos _U_(5) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P5_Msk (_U_(0x1) << PIO_PPDSR_P5_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P5(value) (PIO_PPDSR_P5_Msk & ((value) << PIO_PPDSR_P5_Pos)) +#define PIO_PPDSR_P6_Pos _U_(6) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P6_Msk (_U_(0x1) << PIO_PPDSR_P6_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P6(value) (PIO_PPDSR_P6_Msk & ((value) << PIO_PPDSR_P6_Pos)) +#define PIO_PPDSR_P7_Pos _U_(7) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P7_Msk (_U_(0x1) << PIO_PPDSR_P7_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P7(value) (PIO_PPDSR_P7_Msk & ((value) << PIO_PPDSR_P7_Pos)) +#define PIO_PPDSR_P8_Pos _U_(8) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P8_Msk (_U_(0x1) << PIO_PPDSR_P8_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P8(value) (PIO_PPDSR_P8_Msk & ((value) << PIO_PPDSR_P8_Pos)) +#define PIO_PPDSR_P9_Pos _U_(9) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P9_Msk (_U_(0x1) << PIO_PPDSR_P9_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P9(value) (PIO_PPDSR_P9_Msk & ((value) << PIO_PPDSR_P9_Pos)) +#define PIO_PPDSR_P10_Pos _U_(10) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P10_Msk (_U_(0x1) << PIO_PPDSR_P10_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P10(value) (PIO_PPDSR_P10_Msk & ((value) << PIO_PPDSR_P10_Pos)) +#define PIO_PPDSR_P11_Pos _U_(11) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P11_Msk (_U_(0x1) << PIO_PPDSR_P11_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P11(value) (PIO_PPDSR_P11_Msk & ((value) << PIO_PPDSR_P11_Pos)) +#define PIO_PPDSR_P12_Pos _U_(12) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P12_Msk (_U_(0x1) << PIO_PPDSR_P12_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P12(value) (PIO_PPDSR_P12_Msk & ((value) << PIO_PPDSR_P12_Pos)) +#define PIO_PPDSR_P13_Pos _U_(13) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P13_Msk (_U_(0x1) << PIO_PPDSR_P13_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P13(value) (PIO_PPDSR_P13_Msk & ((value) << PIO_PPDSR_P13_Pos)) +#define PIO_PPDSR_P14_Pos _U_(14) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P14_Msk (_U_(0x1) << PIO_PPDSR_P14_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P14(value) (PIO_PPDSR_P14_Msk & ((value) << PIO_PPDSR_P14_Pos)) +#define PIO_PPDSR_P15_Pos _U_(15) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P15_Msk (_U_(0x1) << PIO_PPDSR_P15_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P15(value) (PIO_PPDSR_P15_Msk & ((value) << PIO_PPDSR_P15_Pos)) +#define PIO_PPDSR_P16_Pos _U_(16) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P16_Msk (_U_(0x1) << PIO_PPDSR_P16_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P16(value) (PIO_PPDSR_P16_Msk & ((value) << PIO_PPDSR_P16_Pos)) +#define PIO_PPDSR_P17_Pos _U_(17) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P17_Msk (_U_(0x1) << PIO_PPDSR_P17_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P17(value) (PIO_PPDSR_P17_Msk & ((value) << PIO_PPDSR_P17_Pos)) +#define PIO_PPDSR_P18_Pos _U_(18) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P18_Msk (_U_(0x1) << PIO_PPDSR_P18_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P18(value) (PIO_PPDSR_P18_Msk & ((value) << PIO_PPDSR_P18_Pos)) +#define PIO_PPDSR_P19_Pos _U_(19) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P19_Msk (_U_(0x1) << PIO_PPDSR_P19_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P19(value) (PIO_PPDSR_P19_Msk & ((value) << PIO_PPDSR_P19_Pos)) +#define PIO_PPDSR_P20_Pos _U_(20) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P20_Msk (_U_(0x1) << PIO_PPDSR_P20_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P20(value) (PIO_PPDSR_P20_Msk & ((value) << PIO_PPDSR_P20_Pos)) +#define PIO_PPDSR_P21_Pos _U_(21) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P21_Msk (_U_(0x1) << PIO_PPDSR_P21_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P21(value) (PIO_PPDSR_P21_Msk & ((value) << PIO_PPDSR_P21_Pos)) +#define PIO_PPDSR_P22_Pos _U_(22) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P22_Msk (_U_(0x1) << PIO_PPDSR_P22_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P22(value) (PIO_PPDSR_P22_Msk & ((value) << PIO_PPDSR_P22_Pos)) +#define PIO_PPDSR_P23_Pos _U_(23) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P23_Msk (_U_(0x1) << PIO_PPDSR_P23_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P23(value) (PIO_PPDSR_P23_Msk & ((value) << PIO_PPDSR_P23_Pos)) +#define PIO_PPDSR_P24_Pos _U_(24) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P24_Msk (_U_(0x1) << PIO_PPDSR_P24_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P24(value) (PIO_PPDSR_P24_Msk & ((value) << PIO_PPDSR_P24_Pos)) +#define PIO_PPDSR_P25_Pos _U_(25) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P25_Msk (_U_(0x1) << PIO_PPDSR_P25_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P25(value) (PIO_PPDSR_P25_Msk & ((value) << PIO_PPDSR_P25_Pos)) +#define PIO_PPDSR_P26_Pos _U_(26) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P26_Msk (_U_(0x1) << PIO_PPDSR_P26_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P26(value) (PIO_PPDSR_P26_Msk & ((value) << PIO_PPDSR_P26_Pos)) +#define PIO_PPDSR_P27_Pos _U_(27) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P27_Msk (_U_(0x1) << PIO_PPDSR_P27_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P27(value) (PIO_PPDSR_P27_Msk & ((value) << PIO_PPDSR_P27_Pos)) +#define PIO_PPDSR_P28_Pos _U_(28) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P28_Msk (_U_(0x1) << PIO_PPDSR_P28_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P28(value) (PIO_PPDSR_P28_Msk & ((value) << PIO_PPDSR_P28_Pos)) +#define PIO_PPDSR_P29_Pos _U_(29) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P29_Msk (_U_(0x1) << PIO_PPDSR_P29_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P29(value) (PIO_PPDSR_P29_Msk & ((value) << PIO_PPDSR_P29_Pos)) +#define PIO_PPDSR_P30_Pos _U_(30) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P30_Msk (_U_(0x1) << PIO_PPDSR_P30_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P30(value) (PIO_PPDSR_P30_Msk & ((value) << PIO_PPDSR_P30_Pos)) +#define PIO_PPDSR_P31_Pos _U_(31) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P31_Msk (_U_(0x1) << PIO_PPDSR_P31_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P31(value) (PIO_PPDSR_P31_Msk & ((value) << PIO_PPDSR_P31_Pos)) +#define PIO_PPDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDSR) Register Mask */ + +#define PIO_PPDSR_P_Pos _U_(0) /**< (PIO_PPDSR Position) Pull-Down Status */ +#define PIO_PPDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDSR_P_Pos) /**< (PIO_PPDSR Mask) P */ +#define PIO_PPDSR_P(value) (PIO_PPDSR_P_Msk & ((value) << PIO_PPDSR_P_Pos)) + +/* -------- PIO_OWER : (PIO Offset: 0xA0) ( /W 32) Output Write Enable -------- */ +#define PIO_OWER_P0_Pos _U_(0) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P0_Msk (_U_(0x1) << PIO_OWER_P0_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P0(value) (PIO_OWER_P0_Msk & ((value) << PIO_OWER_P0_Pos)) +#define PIO_OWER_P1_Pos _U_(1) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P1_Msk (_U_(0x1) << PIO_OWER_P1_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P1(value) (PIO_OWER_P1_Msk & ((value) << PIO_OWER_P1_Pos)) +#define PIO_OWER_P2_Pos _U_(2) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P2_Msk (_U_(0x1) << PIO_OWER_P2_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P2(value) (PIO_OWER_P2_Msk & ((value) << PIO_OWER_P2_Pos)) +#define PIO_OWER_P3_Pos _U_(3) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P3_Msk (_U_(0x1) << PIO_OWER_P3_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P3(value) (PIO_OWER_P3_Msk & ((value) << PIO_OWER_P3_Pos)) +#define PIO_OWER_P4_Pos _U_(4) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P4_Msk (_U_(0x1) << PIO_OWER_P4_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P4(value) (PIO_OWER_P4_Msk & ((value) << PIO_OWER_P4_Pos)) +#define PIO_OWER_P5_Pos _U_(5) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P5_Msk (_U_(0x1) << PIO_OWER_P5_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P5(value) (PIO_OWER_P5_Msk & ((value) << PIO_OWER_P5_Pos)) +#define PIO_OWER_P6_Pos _U_(6) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P6_Msk (_U_(0x1) << PIO_OWER_P6_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P6(value) (PIO_OWER_P6_Msk & ((value) << PIO_OWER_P6_Pos)) +#define PIO_OWER_P7_Pos _U_(7) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P7_Msk (_U_(0x1) << PIO_OWER_P7_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P7(value) (PIO_OWER_P7_Msk & ((value) << PIO_OWER_P7_Pos)) +#define PIO_OWER_P8_Pos _U_(8) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P8_Msk (_U_(0x1) << PIO_OWER_P8_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P8(value) (PIO_OWER_P8_Msk & ((value) << PIO_OWER_P8_Pos)) +#define PIO_OWER_P9_Pos _U_(9) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P9_Msk (_U_(0x1) << PIO_OWER_P9_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P9(value) (PIO_OWER_P9_Msk & ((value) << PIO_OWER_P9_Pos)) +#define PIO_OWER_P10_Pos _U_(10) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P10_Msk (_U_(0x1) << PIO_OWER_P10_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P10(value) (PIO_OWER_P10_Msk & ((value) << PIO_OWER_P10_Pos)) +#define PIO_OWER_P11_Pos _U_(11) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P11_Msk (_U_(0x1) << PIO_OWER_P11_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P11(value) (PIO_OWER_P11_Msk & ((value) << PIO_OWER_P11_Pos)) +#define PIO_OWER_P12_Pos _U_(12) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P12_Msk (_U_(0x1) << PIO_OWER_P12_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P12(value) (PIO_OWER_P12_Msk & ((value) << PIO_OWER_P12_Pos)) +#define PIO_OWER_P13_Pos _U_(13) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P13_Msk (_U_(0x1) << PIO_OWER_P13_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P13(value) (PIO_OWER_P13_Msk & ((value) << PIO_OWER_P13_Pos)) +#define PIO_OWER_P14_Pos _U_(14) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P14_Msk (_U_(0x1) << PIO_OWER_P14_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P14(value) (PIO_OWER_P14_Msk & ((value) << PIO_OWER_P14_Pos)) +#define PIO_OWER_P15_Pos _U_(15) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P15_Msk (_U_(0x1) << PIO_OWER_P15_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P15(value) (PIO_OWER_P15_Msk & ((value) << PIO_OWER_P15_Pos)) +#define PIO_OWER_P16_Pos _U_(16) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P16_Msk (_U_(0x1) << PIO_OWER_P16_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P16(value) (PIO_OWER_P16_Msk & ((value) << PIO_OWER_P16_Pos)) +#define PIO_OWER_P17_Pos _U_(17) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P17_Msk (_U_(0x1) << PIO_OWER_P17_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P17(value) (PIO_OWER_P17_Msk & ((value) << PIO_OWER_P17_Pos)) +#define PIO_OWER_P18_Pos _U_(18) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P18_Msk (_U_(0x1) << PIO_OWER_P18_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P18(value) (PIO_OWER_P18_Msk & ((value) << PIO_OWER_P18_Pos)) +#define PIO_OWER_P19_Pos _U_(19) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P19_Msk (_U_(0x1) << PIO_OWER_P19_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P19(value) (PIO_OWER_P19_Msk & ((value) << PIO_OWER_P19_Pos)) +#define PIO_OWER_P20_Pos _U_(20) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P20_Msk (_U_(0x1) << PIO_OWER_P20_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P20(value) (PIO_OWER_P20_Msk & ((value) << PIO_OWER_P20_Pos)) +#define PIO_OWER_P21_Pos _U_(21) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P21_Msk (_U_(0x1) << PIO_OWER_P21_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P21(value) (PIO_OWER_P21_Msk & ((value) << PIO_OWER_P21_Pos)) +#define PIO_OWER_P22_Pos _U_(22) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P22_Msk (_U_(0x1) << PIO_OWER_P22_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P22(value) (PIO_OWER_P22_Msk & ((value) << PIO_OWER_P22_Pos)) +#define PIO_OWER_P23_Pos _U_(23) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P23_Msk (_U_(0x1) << PIO_OWER_P23_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P23(value) (PIO_OWER_P23_Msk & ((value) << PIO_OWER_P23_Pos)) +#define PIO_OWER_P24_Pos _U_(24) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P24_Msk (_U_(0x1) << PIO_OWER_P24_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P24(value) (PIO_OWER_P24_Msk & ((value) << PIO_OWER_P24_Pos)) +#define PIO_OWER_P25_Pos _U_(25) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P25_Msk (_U_(0x1) << PIO_OWER_P25_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P25(value) (PIO_OWER_P25_Msk & ((value) << PIO_OWER_P25_Pos)) +#define PIO_OWER_P26_Pos _U_(26) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P26_Msk (_U_(0x1) << PIO_OWER_P26_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P26(value) (PIO_OWER_P26_Msk & ((value) << PIO_OWER_P26_Pos)) +#define PIO_OWER_P27_Pos _U_(27) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P27_Msk (_U_(0x1) << PIO_OWER_P27_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P27(value) (PIO_OWER_P27_Msk & ((value) << PIO_OWER_P27_Pos)) +#define PIO_OWER_P28_Pos _U_(28) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P28_Msk (_U_(0x1) << PIO_OWER_P28_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P28(value) (PIO_OWER_P28_Msk & ((value) << PIO_OWER_P28_Pos)) +#define PIO_OWER_P29_Pos _U_(29) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P29_Msk (_U_(0x1) << PIO_OWER_P29_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P29(value) (PIO_OWER_P29_Msk & ((value) << PIO_OWER_P29_Pos)) +#define PIO_OWER_P30_Pos _U_(30) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P30_Msk (_U_(0x1) << PIO_OWER_P30_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P30(value) (PIO_OWER_P30_Msk & ((value) << PIO_OWER_P30_Pos)) +#define PIO_OWER_P31_Pos _U_(31) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P31_Msk (_U_(0x1) << PIO_OWER_P31_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P31(value) (PIO_OWER_P31_Msk & ((value) << PIO_OWER_P31_Pos)) +#define PIO_OWER_Msk _U_(0xFFFFFFFF) /**< (PIO_OWER) Register Mask */ + +#define PIO_OWER_P_Pos _U_(0) /**< (PIO_OWER Position) Output Write Enable */ +#define PIO_OWER_P_Msk (_U_(0xFFFFFFFF) << PIO_OWER_P_Pos) /**< (PIO_OWER Mask) P */ +#define PIO_OWER_P(value) (PIO_OWER_P_Msk & ((value) << PIO_OWER_P_Pos)) + +/* -------- PIO_OWDR : (PIO Offset: 0xA4) ( /W 32) Output Write Disable -------- */ +#define PIO_OWDR_P0_Pos _U_(0) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P0_Msk (_U_(0x1) << PIO_OWDR_P0_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P0(value) (PIO_OWDR_P0_Msk & ((value) << PIO_OWDR_P0_Pos)) +#define PIO_OWDR_P1_Pos _U_(1) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P1_Msk (_U_(0x1) << PIO_OWDR_P1_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P1(value) (PIO_OWDR_P1_Msk & ((value) << PIO_OWDR_P1_Pos)) +#define PIO_OWDR_P2_Pos _U_(2) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P2_Msk (_U_(0x1) << PIO_OWDR_P2_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P2(value) (PIO_OWDR_P2_Msk & ((value) << PIO_OWDR_P2_Pos)) +#define PIO_OWDR_P3_Pos _U_(3) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P3_Msk (_U_(0x1) << PIO_OWDR_P3_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P3(value) (PIO_OWDR_P3_Msk & ((value) << PIO_OWDR_P3_Pos)) +#define PIO_OWDR_P4_Pos _U_(4) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P4_Msk (_U_(0x1) << PIO_OWDR_P4_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P4(value) (PIO_OWDR_P4_Msk & ((value) << PIO_OWDR_P4_Pos)) +#define PIO_OWDR_P5_Pos _U_(5) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P5_Msk (_U_(0x1) << PIO_OWDR_P5_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P5(value) (PIO_OWDR_P5_Msk & ((value) << PIO_OWDR_P5_Pos)) +#define PIO_OWDR_P6_Pos _U_(6) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P6_Msk (_U_(0x1) << PIO_OWDR_P6_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P6(value) (PIO_OWDR_P6_Msk & ((value) << PIO_OWDR_P6_Pos)) +#define PIO_OWDR_P7_Pos _U_(7) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P7_Msk (_U_(0x1) << PIO_OWDR_P7_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P7(value) (PIO_OWDR_P7_Msk & ((value) << PIO_OWDR_P7_Pos)) +#define PIO_OWDR_P8_Pos _U_(8) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P8_Msk (_U_(0x1) << PIO_OWDR_P8_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P8(value) (PIO_OWDR_P8_Msk & ((value) << PIO_OWDR_P8_Pos)) +#define PIO_OWDR_P9_Pos _U_(9) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P9_Msk (_U_(0x1) << PIO_OWDR_P9_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P9(value) (PIO_OWDR_P9_Msk & ((value) << PIO_OWDR_P9_Pos)) +#define PIO_OWDR_P10_Pos _U_(10) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P10_Msk (_U_(0x1) << PIO_OWDR_P10_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P10(value) (PIO_OWDR_P10_Msk & ((value) << PIO_OWDR_P10_Pos)) +#define PIO_OWDR_P11_Pos _U_(11) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P11_Msk (_U_(0x1) << PIO_OWDR_P11_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P11(value) (PIO_OWDR_P11_Msk & ((value) << PIO_OWDR_P11_Pos)) +#define PIO_OWDR_P12_Pos _U_(12) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P12_Msk (_U_(0x1) << PIO_OWDR_P12_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P12(value) (PIO_OWDR_P12_Msk & ((value) << PIO_OWDR_P12_Pos)) +#define PIO_OWDR_P13_Pos _U_(13) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P13_Msk (_U_(0x1) << PIO_OWDR_P13_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P13(value) (PIO_OWDR_P13_Msk & ((value) << PIO_OWDR_P13_Pos)) +#define PIO_OWDR_P14_Pos _U_(14) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P14_Msk (_U_(0x1) << PIO_OWDR_P14_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P14(value) (PIO_OWDR_P14_Msk & ((value) << PIO_OWDR_P14_Pos)) +#define PIO_OWDR_P15_Pos _U_(15) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P15_Msk (_U_(0x1) << PIO_OWDR_P15_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P15(value) (PIO_OWDR_P15_Msk & ((value) << PIO_OWDR_P15_Pos)) +#define PIO_OWDR_P16_Pos _U_(16) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P16_Msk (_U_(0x1) << PIO_OWDR_P16_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P16(value) (PIO_OWDR_P16_Msk & ((value) << PIO_OWDR_P16_Pos)) +#define PIO_OWDR_P17_Pos _U_(17) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P17_Msk (_U_(0x1) << PIO_OWDR_P17_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P17(value) (PIO_OWDR_P17_Msk & ((value) << PIO_OWDR_P17_Pos)) +#define PIO_OWDR_P18_Pos _U_(18) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P18_Msk (_U_(0x1) << PIO_OWDR_P18_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P18(value) (PIO_OWDR_P18_Msk & ((value) << PIO_OWDR_P18_Pos)) +#define PIO_OWDR_P19_Pos _U_(19) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P19_Msk (_U_(0x1) << PIO_OWDR_P19_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P19(value) (PIO_OWDR_P19_Msk & ((value) << PIO_OWDR_P19_Pos)) +#define PIO_OWDR_P20_Pos _U_(20) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P20_Msk (_U_(0x1) << PIO_OWDR_P20_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P20(value) (PIO_OWDR_P20_Msk & ((value) << PIO_OWDR_P20_Pos)) +#define PIO_OWDR_P21_Pos _U_(21) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P21_Msk (_U_(0x1) << PIO_OWDR_P21_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P21(value) (PIO_OWDR_P21_Msk & ((value) << PIO_OWDR_P21_Pos)) +#define PIO_OWDR_P22_Pos _U_(22) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P22_Msk (_U_(0x1) << PIO_OWDR_P22_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P22(value) (PIO_OWDR_P22_Msk & ((value) << PIO_OWDR_P22_Pos)) +#define PIO_OWDR_P23_Pos _U_(23) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P23_Msk (_U_(0x1) << PIO_OWDR_P23_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P23(value) (PIO_OWDR_P23_Msk & ((value) << PIO_OWDR_P23_Pos)) +#define PIO_OWDR_P24_Pos _U_(24) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P24_Msk (_U_(0x1) << PIO_OWDR_P24_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P24(value) (PIO_OWDR_P24_Msk & ((value) << PIO_OWDR_P24_Pos)) +#define PIO_OWDR_P25_Pos _U_(25) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P25_Msk (_U_(0x1) << PIO_OWDR_P25_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P25(value) (PIO_OWDR_P25_Msk & ((value) << PIO_OWDR_P25_Pos)) +#define PIO_OWDR_P26_Pos _U_(26) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P26_Msk (_U_(0x1) << PIO_OWDR_P26_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P26(value) (PIO_OWDR_P26_Msk & ((value) << PIO_OWDR_P26_Pos)) +#define PIO_OWDR_P27_Pos _U_(27) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P27_Msk (_U_(0x1) << PIO_OWDR_P27_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P27(value) (PIO_OWDR_P27_Msk & ((value) << PIO_OWDR_P27_Pos)) +#define PIO_OWDR_P28_Pos _U_(28) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P28_Msk (_U_(0x1) << PIO_OWDR_P28_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P28(value) (PIO_OWDR_P28_Msk & ((value) << PIO_OWDR_P28_Pos)) +#define PIO_OWDR_P29_Pos _U_(29) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P29_Msk (_U_(0x1) << PIO_OWDR_P29_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P29(value) (PIO_OWDR_P29_Msk & ((value) << PIO_OWDR_P29_Pos)) +#define PIO_OWDR_P30_Pos _U_(30) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P30_Msk (_U_(0x1) << PIO_OWDR_P30_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P30(value) (PIO_OWDR_P30_Msk & ((value) << PIO_OWDR_P30_Pos)) +#define PIO_OWDR_P31_Pos _U_(31) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P31_Msk (_U_(0x1) << PIO_OWDR_P31_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P31(value) (PIO_OWDR_P31_Msk & ((value) << PIO_OWDR_P31_Pos)) +#define PIO_OWDR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWDR) Register Mask */ + +#define PIO_OWDR_P_Pos _U_(0) /**< (PIO_OWDR Position) Output Write Disable */ +#define PIO_OWDR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWDR_P_Pos) /**< (PIO_OWDR Mask) P */ +#define PIO_OWDR_P(value) (PIO_OWDR_P_Msk & ((value) << PIO_OWDR_P_Pos)) + +/* -------- PIO_OWSR : (PIO Offset: 0xA8) ( R/ 32) Output Write Status Register -------- */ +#define PIO_OWSR_P0_Pos _U_(0) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P0_Msk (_U_(0x1) << PIO_OWSR_P0_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P0(value) (PIO_OWSR_P0_Msk & ((value) << PIO_OWSR_P0_Pos)) +#define PIO_OWSR_P1_Pos _U_(1) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P1_Msk (_U_(0x1) << PIO_OWSR_P1_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P1(value) (PIO_OWSR_P1_Msk & ((value) << PIO_OWSR_P1_Pos)) +#define PIO_OWSR_P2_Pos _U_(2) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P2_Msk (_U_(0x1) << PIO_OWSR_P2_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P2(value) (PIO_OWSR_P2_Msk & ((value) << PIO_OWSR_P2_Pos)) +#define PIO_OWSR_P3_Pos _U_(3) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P3_Msk (_U_(0x1) << PIO_OWSR_P3_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P3(value) (PIO_OWSR_P3_Msk & ((value) << PIO_OWSR_P3_Pos)) +#define PIO_OWSR_P4_Pos _U_(4) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P4_Msk (_U_(0x1) << PIO_OWSR_P4_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P4(value) (PIO_OWSR_P4_Msk & ((value) << PIO_OWSR_P4_Pos)) +#define PIO_OWSR_P5_Pos _U_(5) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P5_Msk (_U_(0x1) << PIO_OWSR_P5_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P5(value) (PIO_OWSR_P5_Msk & ((value) << PIO_OWSR_P5_Pos)) +#define PIO_OWSR_P6_Pos _U_(6) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P6_Msk (_U_(0x1) << PIO_OWSR_P6_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P6(value) (PIO_OWSR_P6_Msk & ((value) << PIO_OWSR_P6_Pos)) +#define PIO_OWSR_P7_Pos _U_(7) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P7_Msk (_U_(0x1) << PIO_OWSR_P7_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P7(value) (PIO_OWSR_P7_Msk & ((value) << PIO_OWSR_P7_Pos)) +#define PIO_OWSR_P8_Pos _U_(8) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P8_Msk (_U_(0x1) << PIO_OWSR_P8_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P8(value) (PIO_OWSR_P8_Msk & ((value) << PIO_OWSR_P8_Pos)) +#define PIO_OWSR_P9_Pos _U_(9) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P9_Msk (_U_(0x1) << PIO_OWSR_P9_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P9(value) (PIO_OWSR_P9_Msk & ((value) << PIO_OWSR_P9_Pos)) +#define PIO_OWSR_P10_Pos _U_(10) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P10_Msk (_U_(0x1) << PIO_OWSR_P10_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P10(value) (PIO_OWSR_P10_Msk & ((value) << PIO_OWSR_P10_Pos)) +#define PIO_OWSR_P11_Pos _U_(11) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P11_Msk (_U_(0x1) << PIO_OWSR_P11_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P11(value) (PIO_OWSR_P11_Msk & ((value) << PIO_OWSR_P11_Pos)) +#define PIO_OWSR_P12_Pos _U_(12) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P12_Msk (_U_(0x1) << PIO_OWSR_P12_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P12(value) (PIO_OWSR_P12_Msk & ((value) << PIO_OWSR_P12_Pos)) +#define PIO_OWSR_P13_Pos _U_(13) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P13_Msk (_U_(0x1) << PIO_OWSR_P13_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P13(value) (PIO_OWSR_P13_Msk & ((value) << PIO_OWSR_P13_Pos)) +#define PIO_OWSR_P14_Pos _U_(14) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P14_Msk (_U_(0x1) << PIO_OWSR_P14_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P14(value) (PIO_OWSR_P14_Msk & ((value) << PIO_OWSR_P14_Pos)) +#define PIO_OWSR_P15_Pos _U_(15) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P15_Msk (_U_(0x1) << PIO_OWSR_P15_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P15(value) (PIO_OWSR_P15_Msk & ((value) << PIO_OWSR_P15_Pos)) +#define PIO_OWSR_P16_Pos _U_(16) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P16_Msk (_U_(0x1) << PIO_OWSR_P16_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P16(value) (PIO_OWSR_P16_Msk & ((value) << PIO_OWSR_P16_Pos)) +#define PIO_OWSR_P17_Pos _U_(17) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P17_Msk (_U_(0x1) << PIO_OWSR_P17_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P17(value) (PIO_OWSR_P17_Msk & ((value) << PIO_OWSR_P17_Pos)) +#define PIO_OWSR_P18_Pos _U_(18) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P18_Msk (_U_(0x1) << PIO_OWSR_P18_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P18(value) (PIO_OWSR_P18_Msk & ((value) << PIO_OWSR_P18_Pos)) +#define PIO_OWSR_P19_Pos _U_(19) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P19_Msk (_U_(0x1) << PIO_OWSR_P19_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P19(value) (PIO_OWSR_P19_Msk & ((value) << PIO_OWSR_P19_Pos)) +#define PIO_OWSR_P20_Pos _U_(20) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P20_Msk (_U_(0x1) << PIO_OWSR_P20_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P20(value) (PIO_OWSR_P20_Msk & ((value) << PIO_OWSR_P20_Pos)) +#define PIO_OWSR_P21_Pos _U_(21) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P21_Msk (_U_(0x1) << PIO_OWSR_P21_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P21(value) (PIO_OWSR_P21_Msk & ((value) << PIO_OWSR_P21_Pos)) +#define PIO_OWSR_P22_Pos _U_(22) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P22_Msk (_U_(0x1) << PIO_OWSR_P22_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P22(value) (PIO_OWSR_P22_Msk & ((value) << PIO_OWSR_P22_Pos)) +#define PIO_OWSR_P23_Pos _U_(23) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P23_Msk (_U_(0x1) << PIO_OWSR_P23_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P23(value) (PIO_OWSR_P23_Msk & ((value) << PIO_OWSR_P23_Pos)) +#define PIO_OWSR_P24_Pos _U_(24) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P24_Msk (_U_(0x1) << PIO_OWSR_P24_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P24(value) (PIO_OWSR_P24_Msk & ((value) << PIO_OWSR_P24_Pos)) +#define PIO_OWSR_P25_Pos _U_(25) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P25_Msk (_U_(0x1) << PIO_OWSR_P25_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P25(value) (PIO_OWSR_P25_Msk & ((value) << PIO_OWSR_P25_Pos)) +#define PIO_OWSR_P26_Pos _U_(26) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P26_Msk (_U_(0x1) << PIO_OWSR_P26_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P26(value) (PIO_OWSR_P26_Msk & ((value) << PIO_OWSR_P26_Pos)) +#define PIO_OWSR_P27_Pos _U_(27) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P27_Msk (_U_(0x1) << PIO_OWSR_P27_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P27(value) (PIO_OWSR_P27_Msk & ((value) << PIO_OWSR_P27_Pos)) +#define PIO_OWSR_P28_Pos _U_(28) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P28_Msk (_U_(0x1) << PIO_OWSR_P28_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P28(value) (PIO_OWSR_P28_Msk & ((value) << PIO_OWSR_P28_Pos)) +#define PIO_OWSR_P29_Pos _U_(29) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P29_Msk (_U_(0x1) << PIO_OWSR_P29_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P29(value) (PIO_OWSR_P29_Msk & ((value) << PIO_OWSR_P29_Pos)) +#define PIO_OWSR_P30_Pos _U_(30) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P30_Msk (_U_(0x1) << PIO_OWSR_P30_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P30(value) (PIO_OWSR_P30_Msk & ((value) << PIO_OWSR_P30_Pos)) +#define PIO_OWSR_P31_Pos _U_(31) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P31_Msk (_U_(0x1) << PIO_OWSR_P31_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P31(value) (PIO_OWSR_P31_Msk & ((value) << PIO_OWSR_P31_Pos)) +#define PIO_OWSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWSR) Register Mask */ + +#define PIO_OWSR_P_Pos _U_(0) /**< (PIO_OWSR Position) Output Write Status */ +#define PIO_OWSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWSR_P_Pos) /**< (PIO_OWSR Mask) P */ +#define PIO_OWSR_P(value) (PIO_OWSR_P_Msk & ((value) << PIO_OWSR_P_Pos)) + +/* -------- PIO_AIMER : (PIO Offset: 0xB0) ( /W 32) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0_Pos _U_(0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P0_Msk (_U_(0x1) << PIO_AIMER_P0_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P0(value) (PIO_AIMER_P0_Msk & ((value) << PIO_AIMER_P0_Pos)) +#define PIO_AIMER_P1_Pos _U_(1) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P1_Msk (_U_(0x1) << PIO_AIMER_P1_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P1(value) (PIO_AIMER_P1_Msk & ((value) << PIO_AIMER_P1_Pos)) +#define PIO_AIMER_P2_Pos _U_(2) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P2_Msk (_U_(0x1) << PIO_AIMER_P2_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P2(value) (PIO_AIMER_P2_Msk & ((value) << PIO_AIMER_P2_Pos)) +#define PIO_AIMER_P3_Pos _U_(3) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P3_Msk (_U_(0x1) << PIO_AIMER_P3_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P3(value) (PIO_AIMER_P3_Msk & ((value) << PIO_AIMER_P3_Pos)) +#define PIO_AIMER_P4_Pos _U_(4) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P4_Msk (_U_(0x1) << PIO_AIMER_P4_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P4(value) (PIO_AIMER_P4_Msk & ((value) << PIO_AIMER_P4_Pos)) +#define PIO_AIMER_P5_Pos _U_(5) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P5_Msk (_U_(0x1) << PIO_AIMER_P5_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P5(value) (PIO_AIMER_P5_Msk & ((value) << PIO_AIMER_P5_Pos)) +#define PIO_AIMER_P6_Pos _U_(6) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P6_Msk (_U_(0x1) << PIO_AIMER_P6_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P6(value) (PIO_AIMER_P6_Msk & ((value) << PIO_AIMER_P6_Pos)) +#define PIO_AIMER_P7_Pos _U_(7) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P7_Msk (_U_(0x1) << PIO_AIMER_P7_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P7(value) (PIO_AIMER_P7_Msk & ((value) << PIO_AIMER_P7_Pos)) +#define PIO_AIMER_P8_Pos _U_(8) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P8_Msk (_U_(0x1) << PIO_AIMER_P8_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P8(value) (PIO_AIMER_P8_Msk & ((value) << PIO_AIMER_P8_Pos)) +#define PIO_AIMER_P9_Pos _U_(9) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P9_Msk (_U_(0x1) << PIO_AIMER_P9_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P9(value) (PIO_AIMER_P9_Msk & ((value) << PIO_AIMER_P9_Pos)) +#define PIO_AIMER_P10_Pos _U_(10) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P10_Msk (_U_(0x1) << PIO_AIMER_P10_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P10(value) (PIO_AIMER_P10_Msk & ((value) << PIO_AIMER_P10_Pos)) +#define PIO_AIMER_P11_Pos _U_(11) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P11_Msk (_U_(0x1) << PIO_AIMER_P11_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P11(value) (PIO_AIMER_P11_Msk & ((value) << PIO_AIMER_P11_Pos)) +#define PIO_AIMER_P12_Pos _U_(12) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P12_Msk (_U_(0x1) << PIO_AIMER_P12_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P12(value) (PIO_AIMER_P12_Msk & ((value) << PIO_AIMER_P12_Pos)) +#define PIO_AIMER_P13_Pos _U_(13) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P13_Msk (_U_(0x1) << PIO_AIMER_P13_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P13(value) (PIO_AIMER_P13_Msk & ((value) << PIO_AIMER_P13_Pos)) +#define PIO_AIMER_P14_Pos _U_(14) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P14_Msk (_U_(0x1) << PIO_AIMER_P14_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P14(value) (PIO_AIMER_P14_Msk & ((value) << PIO_AIMER_P14_Pos)) +#define PIO_AIMER_P15_Pos _U_(15) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P15_Msk (_U_(0x1) << PIO_AIMER_P15_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P15(value) (PIO_AIMER_P15_Msk & ((value) << PIO_AIMER_P15_Pos)) +#define PIO_AIMER_P16_Pos _U_(16) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P16_Msk (_U_(0x1) << PIO_AIMER_P16_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P16(value) (PIO_AIMER_P16_Msk & ((value) << PIO_AIMER_P16_Pos)) +#define PIO_AIMER_P17_Pos _U_(17) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P17_Msk (_U_(0x1) << PIO_AIMER_P17_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P17(value) (PIO_AIMER_P17_Msk & ((value) << PIO_AIMER_P17_Pos)) +#define PIO_AIMER_P18_Pos _U_(18) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P18_Msk (_U_(0x1) << PIO_AIMER_P18_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P18(value) (PIO_AIMER_P18_Msk & ((value) << PIO_AIMER_P18_Pos)) +#define PIO_AIMER_P19_Pos _U_(19) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P19_Msk (_U_(0x1) << PIO_AIMER_P19_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P19(value) (PIO_AIMER_P19_Msk & ((value) << PIO_AIMER_P19_Pos)) +#define PIO_AIMER_P20_Pos _U_(20) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P20_Msk (_U_(0x1) << PIO_AIMER_P20_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P20(value) (PIO_AIMER_P20_Msk & ((value) << PIO_AIMER_P20_Pos)) +#define PIO_AIMER_P21_Pos _U_(21) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P21_Msk (_U_(0x1) << PIO_AIMER_P21_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P21(value) (PIO_AIMER_P21_Msk & ((value) << PIO_AIMER_P21_Pos)) +#define PIO_AIMER_P22_Pos _U_(22) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P22_Msk (_U_(0x1) << PIO_AIMER_P22_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P22(value) (PIO_AIMER_P22_Msk & ((value) << PIO_AIMER_P22_Pos)) +#define PIO_AIMER_P23_Pos _U_(23) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P23_Msk (_U_(0x1) << PIO_AIMER_P23_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P23(value) (PIO_AIMER_P23_Msk & ((value) << PIO_AIMER_P23_Pos)) +#define PIO_AIMER_P24_Pos _U_(24) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P24_Msk (_U_(0x1) << PIO_AIMER_P24_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P24(value) (PIO_AIMER_P24_Msk & ((value) << PIO_AIMER_P24_Pos)) +#define PIO_AIMER_P25_Pos _U_(25) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P25_Msk (_U_(0x1) << PIO_AIMER_P25_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P25(value) (PIO_AIMER_P25_Msk & ((value) << PIO_AIMER_P25_Pos)) +#define PIO_AIMER_P26_Pos _U_(26) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P26_Msk (_U_(0x1) << PIO_AIMER_P26_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P26(value) (PIO_AIMER_P26_Msk & ((value) << PIO_AIMER_P26_Pos)) +#define PIO_AIMER_P27_Pos _U_(27) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P27_Msk (_U_(0x1) << PIO_AIMER_P27_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P27(value) (PIO_AIMER_P27_Msk & ((value) << PIO_AIMER_P27_Pos)) +#define PIO_AIMER_P28_Pos _U_(28) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P28_Msk (_U_(0x1) << PIO_AIMER_P28_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P28(value) (PIO_AIMER_P28_Msk & ((value) << PIO_AIMER_P28_Pos)) +#define PIO_AIMER_P29_Pos _U_(29) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P29_Msk (_U_(0x1) << PIO_AIMER_P29_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P29(value) (PIO_AIMER_P29_Msk & ((value) << PIO_AIMER_P29_Pos)) +#define PIO_AIMER_P30_Pos _U_(30) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P30_Msk (_U_(0x1) << PIO_AIMER_P30_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P30(value) (PIO_AIMER_P30_Msk & ((value) << PIO_AIMER_P30_Pos)) +#define PIO_AIMER_P31_Pos _U_(31) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P31_Msk (_U_(0x1) << PIO_AIMER_P31_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P31(value) (PIO_AIMER_P31_Msk & ((value) << PIO_AIMER_P31_Pos)) +#define PIO_AIMER_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMER) Register Mask */ + +#define PIO_AIMER_P_Pos _U_(0) /**< (PIO_AIMER Position) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMER_P_Pos) /**< (PIO_AIMER Mask) P */ +#define PIO_AIMER_P(value) (PIO_AIMER_P_Msk & ((value) << PIO_AIMER_P_Pos)) + +/* -------- PIO_AIMDR : (PIO Offset: 0xB4) ( /W 32) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0_Pos _U_(0) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P0_Msk (_U_(0x1) << PIO_AIMDR_P0_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P0(value) (PIO_AIMDR_P0_Msk & ((value) << PIO_AIMDR_P0_Pos)) +#define PIO_AIMDR_P1_Pos _U_(1) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P1_Msk (_U_(0x1) << PIO_AIMDR_P1_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P1(value) (PIO_AIMDR_P1_Msk & ((value) << PIO_AIMDR_P1_Pos)) +#define PIO_AIMDR_P2_Pos _U_(2) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P2_Msk (_U_(0x1) << PIO_AIMDR_P2_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P2(value) (PIO_AIMDR_P2_Msk & ((value) << PIO_AIMDR_P2_Pos)) +#define PIO_AIMDR_P3_Pos _U_(3) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P3_Msk (_U_(0x1) << PIO_AIMDR_P3_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P3(value) (PIO_AIMDR_P3_Msk & ((value) << PIO_AIMDR_P3_Pos)) +#define PIO_AIMDR_P4_Pos _U_(4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P4_Msk (_U_(0x1) << PIO_AIMDR_P4_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P4(value) (PIO_AIMDR_P4_Msk & ((value) << PIO_AIMDR_P4_Pos)) +#define PIO_AIMDR_P5_Pos _U_(5) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P5_Msk (_U_(0x1) << PIO_AIMDR_P5_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P5(value) (PIO_AIMDR_P5_Msk & ((value) << PIO_AIMDR_P5_Pos)) +#define PIO_AIMDR_P6_Pos _U_(6) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P6_Msk (_U_(0x1) << PIO_AIMDR_P6_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P6(value) (PIO_AIMDR_P6_Msk & ((value) << PIO_AIMDR_P6_Pos)) +#define PIO_AIMDR_P7_Pos _U_(7) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P7_Msk (_U_(0x1) << PIO_AIMDR_P7_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P7(value) (PIO_AIMDR_P7_Msk & ((value) << PIO_AIMDR_P7_Pos)) +#define PIO_AIMDR_P8_Pos _U_(8) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P8_Msk (_U_(0x1) << PIO_AIMDR_P8_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P8(value) (PIO_AIMDR_P8_Msk & ((value) << PIO_AIMDR_P8_Pos)) +#define PIO_AIMDR_P9_Pos _U_(9) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P9_Msk (_U_(0x1) << PIO_AIMDR_P9_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P9(value) (PIO_AIMDR_P9_Msk & ((value) << PIO_AIMDR_P9_Pos)) +#define PIO_AIMDR_P10_Pos _U_(10) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P10_Msk (_U_(0x1) << PIO_AIMDR_P10_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P10(value) (PIO_AIMDR_P10_Msk & ((value) << PIO_AIMDR_P10_Pos)) +#define PIO_AIMDR_P11_Pos _U_(11) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P11_Msk (_U_(0x1) << PIO_AIMDR_P11_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P11(value) (PIO_AIMDR_P11_Msk & ((value) << PIO_AIMDR_P11_Pos)) +#define PIO_AIMDR_P12_Pos _U_(12) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P12_Msk (_U_(0x1) << PIO_AIMDR_P12_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P12(value) (PIO_AIMDR_P12_Msk & ((value) << PIO_AIMDR_P12_Pos)) +#define PIO_AIMDR_P13_Pos _U_(13) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P13_Msk (_U_(0x1) << PIO_AIMDR_P13_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P13(value) (PIO_AIMDR_P13_Msk & ((value) << PIO_AIMDR_P13_Pos)) +#define PIO_AIMDR_P14_Pos _U_(14) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P14_Msk (_U_(0x1) << PIO_AIMDR_P14_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P14(value) (PIO_AIMDR_P14_Msk & ((value) << PIO_AIMDR_P14_Pos)) +#define PIO_AIMDR_P15_Pos _U_(15) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P15_Msk (_U_(0x1) << PIO_AIMDR_P15_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P15(value) (PIO_AIMDR_P15_Msk & ((value) << PIO_AIMDR_P15_Pos)) +#define PIO_AIMDR_P16_Pos _U_(16) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P16_Msk (_U_(0x1) << PIO_AIMDR_P16_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P16(value) (PIO_AIMDR_P16_Msk & ((value) << PIO_AIMDR_P16_Pos)) +#define PIO_AIMDR_P17_Pos _U_(17) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P17_Msk (_U_(0x1) << PIO_AIMDR_P17_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P17(value) (PIO_AIMDR_P17_Msk & ((value) << PIO_AIMDR_P17_Pos)) +#define PIO_AIMDR_P18_Pos _U_(18) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P18_Msk (_U_(0x1) << PIO_AIMDR_P18_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P18(value) (PIO_AIMDR_P18_Msk & ((value) << PIO_AIMDR_P18_Pos)) +#define PIO_AIMDR_P19_Pos _U_(19) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P19_Msk (_U_(0x1) << PIO_AIMDR_P19_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P19(value) (PIO_AIMDR_P19_Msk & ((value) << PIO_AIMDR_P19_Pos)) +#define PIO_AIMDR_P20_Pos _U_(20) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P20_Msk (_U_(0x1) << PIO_AIMDR_P20_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P20(value) (PIO_AIMDR_P20_Msk & ((value) << PIO_AIMDR_P20_Pos)) +#define PIO_AIMDR_P21_Pos _U_(21) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P21_Msk (_U_(0x1) << PIO_AIMDR_P21_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P21(value) (PIO_AIMDR_P21_Msk & ((value) << PIO_AIMDR_P21_Pos)) +#define PIO_AIMDR_P22_Pos _U_(22) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P22_Msk (_U_(0x1) << PIO_AIMDR_P22_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P22(value) (PIO_AIMDR_P22_Msk & ((value) << PIO_AIMDR_P22_Pos)) +#define PIO_AIMDR_P23_Pos _U_(23) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P23_Msk (_U_(0x1) << PIO_AIMDR_P23_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P23(value) (PIO_AIMDR_P23_Msk & ((value) << PIO_AIMDR_P23_Pos)) +#define PIO_AIMDR_P24_Pos _U_(24) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P24_Msk (_U_(0x1) << PIO_AIMDR_P24_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P24(value) (PIO_AIMDR_P24_Msk & ((value) << PIO_AIMDR_P24_Pos)) +#define PIO_AIMDR_P25_Pos _U_(25) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P25_Msk (_U_(0x1) << PIO_AIMDR_P25_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P25(value) (PIO_AIMDR_P25_Msk & ((value) << PIO_AIMDR_P25_Pos)) +#define PIO_AIMDR_P26_Pos _U_(26) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P26_Msk (_U_(0x1) << PIO_AIMDR_P26_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P26(value) (PIO_AIMDR_P26_Msk & ((value) << PIO_AIMDR_P26_Pos)) +#define PIO_AIMDR_P27_Pos _U_(27) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P27_Msk (_U_(0x1) << PIO_AIMDR_P27_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P27(value) (PIO_AIMDR_P27_Msk & ((value) << PIO_AIMDR_P27_Pos)) +#define PIO_AIMDR_P28_Pos _U_(28) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P28_Msk (_U_(0x1) << PIO_AIMDR_P28_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P28(value) (PIO_AIMDR_P28_Msk & ((value) << PIO_AIMDR_P28_Pos)) +#define PIO_AIMDR_P29_Pos _U_(29) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P29_Msk (_U_(0x1) << PIO_AIMDR_P29_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P29(value) (PIO_AIMDR_P29_Msk & ((value) << PIO_AIMDR_P29_Pos)) +#define PIO_AIMDR_P30_Pos _U_(30) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P30_Msk (_U_(0x1) << PIO_AIMDR_P30_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P30(value) (PIO_AIMDR_P30_Msk & ((value) << PIO_AIMDR_P30_Pos)) +#define PIO_AIMDR_P31_Pos _U_(31) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P31_Msk (_U_(0x1) << PIO_AIMDR_P31_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P31(value) (PIO_AIMDR_P31_Msk & ((value) << PIO_AIMDR_P31_Pos)) +#define PIO_AIMDR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMDR) Register Mask */ + +#define PIO_AIMDR_P_Pos _U_(0) /**< (PIO_AIMDR Position) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMDR_P_Pos) /**< (PIO_AIMDR Mask) P */ +#define PIO_AIMDR_P(value) (PIO_AIMDR_P_Msk & ((value) << PIO_AIMDR_P_Pos)) + +/* -------- PIO_AIMMR : (PIO Offset: 0xB8) ( R/ 32) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0_Pos _U_(0) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P0_Msk (_U_(0x1) << PIO_AIMMR_P0_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P0(value) (PIO_AIMMR_P0_Msk & ((value) << PIO_AIMMR_P0_Pos)) +#define PIO_AIMMR_P1_Pos _U_(1) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P1_Msk (_U_(0x1) << PIO_AIMMR_P1_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P1(value) (PIO_AIMMR_P1_Msk & ((value) << PIO_AIMMR_P1_Pos)) +#define PIO_AIMMR_P2_Pos _U_(2) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P2_Msk (_U_(0x1) << PIO_AIMMR_P2_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P2(value) (PIO_AIMMR_P2_Msk & ((value) << PIO_AIMMR_P2_Pos)) +#define PIO_AIMMR_P3_Pos _U_(3) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P3_Msk (_U_(0x1) << PIO_AIMMR_P3_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P3(value) (PIO_AIMMR_P3_Msk & ((value) << PIO_AIMMR_P3_Pos)) +#define PIO_AIMMR_P4_Pos _U_(4) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P4_Msk (_U_(0x1) << PIO_AIMMR_P4_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P4(value) (PIO_AIMMR_P4_Msk & ((value) << PIO_AIMMR_P4_Pos)) +#define PIO_AIMMR_P5_Pos _U_(5) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P5_Msk (_U_(0x1) << PIO_AIMMR_P5_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P5(value) (PIO_AIMMR_P5_Msk & ((value) << PIO_AIMMR_P5_Pos)) +#define PIO_AIMMR_P6_Pos _U_(6) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P6_Msk (_U_(0x1) << PIO_AIMMR_P6_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P6(value) (PIO_AIMMR_P6_Msk & ((value) << PIO_AIMMR_P6_Pos)) +#define PIO_AIMMR_P7_Pos _U_(7) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P7_Msk (_U_(0x1) << PIO_AIMMR_P7_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P7(value) (PIO_AIMMR_P7_Msk & ((value) << PIO_AIMMR_P7_Pos)) +#define PIO_AIMMR_P8_Pos _U_(8) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P8_Msk (_U_(0x1) << PIO_AIMMR_P8_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P8(value) (PIO_AIMMR_P8_Msk & ((value) << PIO_AIMMR_P8_Pos)) +#define PIO_AIMMR_P9_Pos _U_(9) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P9_Msk (_U_(0x1) << PIO_AIMMR_P9_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P9(value) (PIO_AIMMR_P9_Msk & ((value) << PIO_AIMMR_P9_Pos)) +#define PIO_AIMMR_P10_Pos _U_(10) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P10_Msk (_U_(0x1) << PIO_AIMMR_P10_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P10(value) (PIO_AIMMR_P10_Msk & ((value) << PIO_AIMMR_P10_Pos)) +#define PIO_AIMMR_P11_Pos _U_(11) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P11_Msk (_U_(0x1) << PIO_AIMMR_P11_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P11(value) (PIO_AIMMR_P11_Msk & ((value) << PIO_AIMMR_P11_Pos)) +#define PIO_AIMMR_P12_Pos _U_(12) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P12_Msk (_U_(0x1) << PIO_AIMMR_P12_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P12(value) (PIO_AIMMR_P12_Msk & ((value) << PIO_AIMMR_P12_Pos)) +#define PIO_AIMMR_P13_Pos _U_(13) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P13_Msk (_U_(0x1) << PIO_AIMMR_P13_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P13(value) (PIO_AIMMR_P13_Msk & ((value) << PIO_AIMMR_P13_Pos)) +#define PIO_AIMMR_P14_Pos _U_(14) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P14_Msk (_U_(0x1) << PIO_AIMMR_P14_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P14(value) (PIO_AIMMR_P14_Msk & ((value) << PIO_AIMMR_P14_Pos)) +#define PIO_AIMMR_P15_Pos _U_(15) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P15_Msk (_U_(0x1) << PIO_AIMMR_P15_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P15(value) (PIO_AIMMR_P15_Msk & ((value) << PIO_AIMMR_P15_Pos)) +#define PIO_AIMMR_P16_Pos _U_(16) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P16_Msk (_U_(0x1) << PIO_AIMMR_P16_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P16(value) (PIO_AIMMR_P16_Msk & ((value) << PIO_AIMMR_P16_Pos)) +#define PIO_AIMMR_P17_Pos _U_(17) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P17_Msk (_U_(0x1) << PIO_AIMMR_P17_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P17(value) (PIO_AIMMR_P17_Msk & ((value) << PIO_AIMMR_P17_Pos)) +#define PIO_AIMMR_P18_Pos _U_(18) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P18_Msk (_U_(0x1) << PIO_AIMMR_P18_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P18(value) (PIO_AIMMR_P18_Msk & ((value) << PIO_AIMMR_P18_Pos)) +#define PIO_AIMMR_P19_Pos _U_(19) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P19_Msk (_U_(0x1) << PIO_AIMMR_P19_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P19(value) (PIO_AIMMR_P19_Msk & ((value) << PIO_AIMMR_P19_Pos)) +#define PIO_AIMMR_P20_Pos _U_(20) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P20_Msk (_U_(0x1) << PIO_AIMMR_P20_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P20(value) (PIO_AIMMR_P20_Msk & ((value) << PIO_AIMMR_P20_Pos)) +#define PIO_AIMMR_P21_Pos _U_(21) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P21_Msk (_U_(0x1) << PIO_AIMMR_P21_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P21(value) (PIO_AIMMR_P21_Msk & ((value) << PIO_AIMMR_P21_Pos)) +#define PIO_AIMMR_P22_Pos _U_(22) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P22_Msk (_U_(0x1) << PIO_AIMMR_P22_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P22(value) (PIO_AIMMR_P22_Msk & ((value) << PIO_AIMMR_P22_Pos)) +#define PIO_AIMMR_P23_Pos _U_(23) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P23_Msk (_U_(0x1) << PIO_AIMMR_P23_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P23(value) (PIO_AIMMR_P23_Msk & ((value) << PIO_AIMMR_P23_Pos)) +#define PIO_AIMMR_P24_Pos _U_(24) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P24_Msk (_U_(0x1) << PIO_AIMMR_P24_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P24(value) (PIO_AIMMR_P24_Msk & ((value) << PIO_AIMMR_P24_Pos)) +#define PIO_AIMMR_P25_Pos _U_(25) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P25_Msk (_U_(0x1) << PIO_AIMMR_P25_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P25(value) (PIO_AIMMR_P25_Msk & ((value) << PIO_AIMMR_P25_Pos)) +#define PIO_AIMMR_P26_Pos _U_(26) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P26_Msk (_U_(0x1) << PIO_AIMMR_P26_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P26(value) (PIO_AIMMR_P26_Msk & ((value) << PIO_AIMMR_P26_Pos)) +#define PIO_AIMMR_P27_Pos _U_(27) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P27_Msk (_U_(0x1) << PIO_AIMMR_P27_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P27(value) (PIO_AIMMR_P27_Msk & ((value) << PIO_AIMMR_P27_Pos)) +#define PIO_AIMMR_P28_Pos _U_(28) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P28_Msk (_U_(0x1) << PIO_AIMMR_P28_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P28(value) (PIO_AIMMR_P28_Msk & ((value) << PIO_AIMMR_P28_Pos)) +#define PIO_AIMMR_P29_Pos _U_(29) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P29_Msk (_U_(0x1) << PIO_AIMMR_P29_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P29(value) (PIO_AIMMR_P29_Msk & ((value) << PIO_AIMMR_P29_Pos)) +#define PIO_AIMMR_P30_Pos _U_(30) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P30_Msk (_U_(0x1) << PIO_AIMMR_P30_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P30(value) (PIO_AIMMR_P30_Msk & ((value) << PIO_AIMMR_P30_Pos)) +#define PIO_AIMMR_P31_Pos _U_(31) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P31_Msk (_U_(0x1) << PIO_AIMMR_P31_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P31(value) (PIO_AIMMR_P31_Msk & ((value) << PIO_AIMMR_P31_Pos)) +#define PIO_AIMMR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMMR) Register Mask */ + +#define PIO_AIMMR_P_Pos _U_(0) /**< (PIO_AIMMR Position) IO Line Index */ +#define PIO_AIMMR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMMR_P_Pos) /**< (PIO_AIMMR Mask) P */ +#define PIO_AIMMR_P(value) (PIO_AIMMR_P_Msk & ((value) << PIO_AIMMR_P_Pos)) + +/* -------- PIO_ESR : (PIO Offset: 0xC0) ( /W 32) Edge Select Register -------- */ +#define PIO_ESR_P0_Pos _U_(0) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P0_Msk (_U_(0x1) << PIO_ESR_P0_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P0(value) (PIO_ESR_P0_Msk & ((value) << PIO_ESR_P0_Pos)) +#define PIO_ESR_P1_Pos _U_(1) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P1_Msk (_U_(0x1) << PIO_ESR_P1_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P1(value) (PIO_ESR_P1_Msk & ((value) << PIO_ESR_P1_Pos)) +#define PIO_ESR_P2_Pos _U_(2) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P2_Msk (_U_(0x1) << PIO_ESR_P2_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P2(value) (PIO_ESR_P2_Msk & ((value) << PIO_ESR_P2_Pos)) +#define PIO_ESR_P3_Pos _U_(3) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P3_Msk (_U_(0x1) << PIO_ESR_P3_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P3(value) (PIO_ESR_P3_Msk & ((value) << PIO_ESR_P3_Pos)) +#define PIO_ESR_P4_Pos _U_(4) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P4_Msk (_U_(0x1) << PIO_ESR_P4_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P4(value) (PIO_ESR_P4_Msk & ((value) << PIO_ESR_P4_Pos)) +#define PIO_ESR_P5_Pos _U_(5) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P5_Msk (_U_(0x1) << PIO_ESR_P5_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P5(value) (PIO_ESR_P5_Msk & ((value) << PIO_ESR_P5_Pos)) +#define PIO_ESR_P6_Pos _U_(6) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P6_Msk (_U_(0x1) << PIO_ESR_P6_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P6(value) (PIO_ESR_P6_Msk & ((value) << PIO_ESR_P6_Pos)) +#define PIO_ESR_P7_Pos _U_(7) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P7_Msk (_U_(0x1) << PIO_ESR_P7_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P7(value) (PIO_ESR_P7_Msk & ((value) << PIO_ESR_P7_Pos)) +#define PIO_ESR_P8_Pos _U_(8) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P8_Msk (_U_(0x1) << PIO_ESR_P8_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P8(value) (PIO_ESR_P8_Msk & ((value) << PIO_ESR_P8_Pos)) +#define PIO_ESR_P9_Pos _U_(9) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P9_Msk (_U_(0x1) << PIO_ESR_P9_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P9(value) (PIO_ESR_P9_Msk & ((value) << PIO_ESR_P9_Pos)) +#define PIO_ESR_P10_Pos _U_(10) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P10_Msk (_U_(0x1) << PIO_ESR_P10_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P10(value) (PIO_ESR_P10_Msk & ((value) << PIO_ESR_P10_Pos)) +#define PIO_ESR_P11_Pos _U_(11) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P11_Msk (_U_(0x1) << PIO_ESR_P11_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P11(value) (PIO_ESR_P11_Msk & ((value) << PIO_ESR_P11_Pos)) +#define PIO_ESR_P12_Pos _U_(12) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P12_Msk (_U_(0x1) << PIO_ESR_P12_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P12(value) (PIO_ESR_P12_Msk & ((value) << PIO_ESR_P12_Pos)) +#define PIO_ESR_P13_Pos _U_(13) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P13_Msk (_U_(0x1) << PIO_ESR_P13_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P13(value) (PIO_ESR_P13_Msk & ((value) << PIO_ESR_P13_Pos)) +#define PIO_ESR_P14_Pos _U_(14) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P14_Msk (_U_(0x1) << PIO_ESR_P14_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P14(value) (PIO_ESR_P14_Msk & ((value) << PIO_ESR_P14_Pos)) +#define PIO_ESR_P15_Pos _U_(15) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P15_Msk (_U_(0x1) << PIO_ESR_P15_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P15(value) (PIO_ESR_P15_Msk & ((value) << PIO_ESR_P15_Pos)) +#define PIO_ESR_P16_Pos _U_(16) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P16_Msk (_U_(0x1) << PIO_ESR_P16_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P16(value) (PIO_ESR_P16_Msk & ((value) << PIO_ESR_P16_Pos)) +#define PIO_ESR_P17_Pos _U_(17) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P17_Msk (_U_(0x1) << PIO_ESR_P17_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P17(value) (PIO_ESR_P17_Msk & ((value) << PIO_ESR_P17_Pos)) +#define PIO_ESR_P18_Pos _U_(18) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P18_Msk (_U_(0x1) << PIO_ESR_P18_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P18(value) (PIO_ESR_P18_Msk & ((value) << PIO_ESR_P18_Pos)) +#define PIO_ESR_P19_Pos _U_(19) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P19_Msk (_U_(0x1) << PIO_ESR_P19_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P19(value) (PIO_ESR_P19_Msk & ((value) << PIO_ESR_P19_Pos)) +#define PIO_ESR_P20_Pos _U_(20) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P20_Msk (_U_(0x1) << PIO_ESR_P20_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P20(value) (PIO_ESR_P20_Msk & ((value) << PIO_ESR_P20_Pos)) +#define PIO_ESR_P21_Pos _U_(21) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P21_Msk (_U_(0x1) << PIO_ESR_P21_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P21(value) (PIO_ESR_P21_Msk & ((value) << PIO_ESR_P21_Pos)) +#define PIO_ESR_P22_Pos _U_(22) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P22_Msk (_U_(0x1) << PIO_ESR_P22_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P22(value) (PIO_ESR_P22_Msk & ((value) << PIO_ESR_P22_Pos)) +#define PIO_ESR_P23_Pos _U_(23) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P23_Msk (_U_(0x1) << PIO_ESR_P23_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P23(value) (PIO_ESR_P23_Msk & ((value) << PIO_ESR_P23_Pos)) +#define PIO_ESR_P24_Pos _U_(24) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P24_Msk (_U_(0x1) << PIO_ESR_P24_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P24(value) (PIO_ESR_P24_Msk & ((value) << PIO_ESR_P24_Pos)) +#define PIO_ESR_P25_Pos _U_(25) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P25_Msk (_U_(0x1) << PIO_ESR_P25_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P25(value) (PIO_ESR_P25_Msk & ((value) << PIO_ESR_P25_Pos)) +#define PIO_ESR_P26_Pos _U_(26) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P26_Msk (_U_(0x1) << PIO_ESR_P26_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P26(value) (PIO_ESR_P26_Msk & ((value) << PIO_ESR_P26_Pos)) +#define PIO_ESR_P27_Pos _U_(27) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P27_Msk (_U_(0x1) << PIO_ESR_P27_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P27(value) (PIO_ESR_P27_Msk & ((value) << PIO_ESR_P27_Pos)) +#define PIO_ESR_P28_Pos _U_(28) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P28_Msk (_U_(0x1) << PIO_ESR_P28_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P28(value) (PIO_ESR_P28_Msk & ((value) << PIO_ESR_P28_Pos)) +#define PIO_ESR_P29_Pos _U_(29) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P29_Msk (_U_(0x1) << PIO_ESR_P29_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P29(value) (PIO_ESR_P29_Msk & ((value) << PIO_ESR_P29_Pos)) +#define PIO_ESR_P30_Pos _U_(30) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P30_Msk (_U_(0x1) << PIO_ESR_P30_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P30(value) (PIO_ESR_P30_Msk & ((value) << PIO_ESR_P30_Pos)) +#define PIO_ESR_P31_Pos _U_(31) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P31_Msk (_U_(0x1) << PIO_ESR_P31_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P31(value) (PIO_ESR_P31_Msk & ((value) << PIO_ESR_P31_Pos)) +#define PIO_ESR_Msk _U_(0xFFFFFFFF) /**< (PIO_ESR) Register Mask */ + +#define PIO_ESR_P_Pos _U_(0) /**< (PIO_ESR Position) Edge Interrupt Selection */ +#define PIO_ESR_P_Msk (_U_(0xFFFFFFFF) << PIO_ESR_P_Pos) /**< (PIO_ESR Mask) P */ +#define PIO_ESR_P(value) (PIO_ESR_P_Msk & ((value) << PIO_ESR_P_Pos)) + +/* -------- PIO_LSR : (PIO Offset: 0xC4) ( /W 32) Level Select Register -------- */ +#define PIO_LSR_P0_Pos _U_(0) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P0_Msk (_U_(0x1) << PIO_LSR_P0_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P0(value) (PIO_LSR_P0_Msk & ((value) << PIO_LSR_P0_Pos)) +#define PIO_LSR_P1_Pos _U_(1) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P1_Msk (_U_(0x1) << PIO_LSR_P1_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P1(value) (PIO_LSR_P1_Msk & ((value) << PIO_LSR_P1_Pos)) +#define PIO_LSR_P2_Pos _U_(2) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P2_Msk (_U_(0x1) << PIO_LSR_P2_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P2(value) (PIO_LSR_P2_Msk & ((value) << PIO_LSR_P2_Pos)) +#define PIO_LSR_P3_Pos _U_(3) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P3_Msk (_U_(0x1) << PIO_LSR_P3_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P3(value) (PIO_LSR_P3_Msk & ((value) << PIO_LSR_P3_Pos)) +#define PIO_LSR_P4_Pos _U_(4) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P4_Msk (_U_(0x1) << PIO_LSR_P4_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P4(value) (PIO_LSR_P4_Msk & ((value) << PIO_LSR_P4_Pos)) +#define PIO_LSR_P5_Pos _U_(5) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P5_Msk (_U_(0x1) << PIO_LSR_P5_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P5(value) (PIO_LSR_P5_Msk & ((value) << PIO_LSR_P5_Pos)) +#define PIO_LSR_P6_Pos _U_(6) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P6_Msk (_U_(0x1) << PIO_LSR_P6_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P6(value) (PIO_LSR_P6_Msk & ((value) << PIO_LSR_P6_Pos)) +#define PIO_LSR_P7_Pos _U_(7) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P7_Msk (_U_(0x1) << PIO_LSR_P7_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P7(value) (PIO_LSR_P7_Msk & ((value) << PIO_LSR_P7_Pos)) +#define PIO_LSR_P8_Pos _U_(8) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P8_Msk (_U_(0x1) << PIO_LSR_P8_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P8(value) (PIO_LSR_P8_Msk & ((value) << PIO_LSR_P8_Pos)) +#define PIO_LSR_P9_Pos _U_(9) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P9_Msk (_U_(0x1) << PIO_LSR_P9_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P9(value) (PIO_LSR_P9_Msk & ((value) << PIO_LSR_P9_Pos)) +#define PIO_LSR_P10_Pos _U_(10) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P10_Msk (_U_(0x1) << PIO_LSR_P10_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P10(value) (PIO_LSR_P10_Msk & ((value) << PIO_LSR_P10_Pos)) +#define PIO_LSR_P11_Pos _U_(11) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P11_Msk (_U_(0x1) << PIO_LSR_P11_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P11(value) (PIO_LSR_P11_Msk & ((value) << PIO_LSR_P11_Pos)) +#define PIO_LSR_P12_Pos _U_(12) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P12_Msk (_U_(0x1) << PIO_LSR_P12_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P12(value) (PIO_LSR_P12_Msk & ((value) << PIO_LSR_P12_Pos)) +#define PIO_LSR_P13_Pos _U_(13) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P13_Msk (_U_(0x1) << PIO_LSR_P13_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P13(value) (PIO_LSR_P13_Msk & ((value) << PIO_LSR_P13_Pos)) +#define PIO_LSR_P14_Pos _U_(14) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P14_Msk (_U_(0x1) << PIO_LSR_P14_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P14(value) (PIO_LSR_P14_Msk & ((value) << PIO_LSR_P14_Pos)) +#define PIO_LSR_P15_Pos _U_(15) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P15_Msk (_U_(0x1) << PIO_LSR_P15_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P15(value) (PIO_LSR_P15_Msk & ((value) << PIO_LSR_P15_Pos)) +#define PIO_LSR_P16_Pos _U_(16) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P16_Msk (_U_(0x1) << PIO_LSR_P16_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P16(value) (PIO_LSR_P16_Msk & ((value) << PIO_LSR_P16_Pos)) +#define PIO_LSR_P17_Pos _U_(17) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P17_Msk (_U_(0x1) << PIO_LSR_P17_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P17(value) (PIO_LSR_P17_Msk & ((value) << PIO_LSR_P17_Pos)) +#define PIO_LSR_P18_Pos _U_(18) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P18_Msk (_U_(0x1) << PIO_LSR_P18_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P18(value) (PIO_LSR_P18_Msk & ((value) << PIO_LSR_P18_Pos)) +#define PIO_LSR_P19_Pos _U_(19) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P19_Msk (_U_(0x1) << PIO_LSR_P19_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P19(value) (PIO_LSR_P19_Msk & ((value) << PIO_LSR_P19_Pos)) +#define PIO_LSR_P20_Pos _U_(20) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P20_Msk (_U_(0x1) << PIO_LSR_P20_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P20(value) (PIO_LSR_P20_Msk & ((value) << PIO_LSR_P20_Pos)) +#define PIO_LSR_P21_Pos _U_(21) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P21_Msk (_U_(0x1) << PIO_LSR_P21_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P21(value) (PIO_LSR_P21_Msk & ((value) << PIO_LSR_P21_Pos)) +#define PIO_LSR_P22_Pos _U_(22) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P22_Msk (_U_(0x1) << PIO_LSR_P22_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P22(value) (PIO_LSR_P22_Msk & ((value) << PIO_LSR_P22_Pos)) +#define PIO_LSR_P23_Pos _U_(23) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P23_Msk (_U_(0x1) << PIO_LSR_P23_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P23(value) (PIO_LSR_P23_Msk & ((value) << PIO_LSR_P23_Pos)) +#define PIO_LSR_P24_Pos _U_(24) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P24_Msk (_U_(0x1) << PIO_LSR_P24_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P24(value) (PIO_LSR_P24_Msk & ((value) << PIO_LSR_P24_Pos)) +#define PIO_LSR_P25_Pos _U_(25) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P25_Msk (_U_(0x1) << PIO_LSR_P25_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P25(value) (PIO_LSR_P25_Msk & ((value) << PIO_LSR_P25_Pos)) +#define PIO_LSR_P26_Pos _U_(26) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P26_Msk (_U_(0x1) << PIO_LSR_P26_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P26(value) (PIO_LSR_P26_Msk & ((value) << PIO_LSR_P26_Pos)) +#define PIO_LSR_P27_Pos _U_(27) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P27_Msk (_U_(0x1) << PIO_LSR_P27_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P27(value) (PIO_LSR_P27_Msk & ((value) << PIO_LSR_P27_Pos)) +#define PIO_LSR_P28_Pos _U_(28) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P28_Msk (_U_(0x1) << PIO_LSR_P28_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P28(value) (PIO_LSR_P28_Msk & ((value) << PIO_LSR_P28_Pos)) +#define PIO_LSR_P29_Pos _U_(29) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P29_Msk (_U_(0x1) << PIO_LSR_P29_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P29(value) (PIO_LSR_P29_Msk & ((value) << PIO_LSR_P29_Pos)) +#define PIO_LSR_P30_Pos _U_(30) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P30_Msk (_U_(0x1) << PIO_LSR_P30_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P30(value) (PIO_LSR_P30_Msk & ((value) << PIO_LSR_P30_Pos)) +#define PIO_LSR_P31_Pos _U_(31) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P31_Msk (_U_(0x1) << PIO_LSR_P31_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P31(value) (PIO_LSR_P31_Msk & ((value) << PIO_LSR_P31_Pos)) +#define PIO_LSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LSR) Register Mask */ + +#define PIO_LSR_P_Pos _U_(0) /**< (PIO_LSR Position) Level Interrupt Selection */ +#define PIO_LSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LSR_P_Pos) /**< (PIO_LSR Mask) P */ +#define PIO_LSR_P(value) (PIO_LSR_P_Msk & ((value) << PIO_LSR_P_Pos)) + +/* -------- PIO_ELSR : (PIO Offset: 0xC8) ( R/ 32) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0_Pos _U_(0) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P0_Msk (_U_(0x1) << PIO_ELSR_P0_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P0(value) (PIO_ELSR_P0_Msk & ((value) << PIO_ELSR_P0_Pos)) +#define PIO_ELSR_P1_Pos _U_(1) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P1_Msk (_U_(0x1) << PIO_ELSR_P1_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P1(value) (PIO_ELSR_P1_Msk & ((value) << PIO_ELSR_P1_Pos)) +#define PIO_ELSR_P2_Pos _U_(2) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P2_Msk (_U_(0x1) << PIO_ELSR_P2_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P2(value) (PIO_ELSR_P2_Msk & ((value) << PIO_ELSR_P2_Pos)) +#define PIO_ELSR_P3_Pos _U_(3) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P3_Msk (_U_(0x1) << PIO_ELSR_P3_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P3(value) (PIO_ELSR_P3_Msk & ((value) << PIO_ELSR_P3_Pos)) +#define PIO_ELSR_P4_Pos _U_(4) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P4_Msk (_U_(0x1) << PIO_ELSR_P4_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P4(value) (PIO_ELSR_P4_Msk & ((value) << PIO_ELSR_P4_Pos)) +#define PIO_ELSR_P5_Pos _U_(5) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P5_Msk (_U_(0x1) << PIO_ELSR_P5_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P5(value) (PIO_ELSR_P5_Msk & ((value) << PIO_ELSR_P5_Pos)) +#define PIO_ELSR_P6_Pos _U_(6) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P6_Msk (_U_(0x1) << PIO_ELSR_P6_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P6(value) (PIO_ELSR_P6_Msk & ((value) << PIO_ELSR_P6_Pos)) +#define PIO_ELSR_P7_Pos _U_(7) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P7_Msk (_U_(0x1) << PIO_ELSR_P7_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P7(value) (PIO_ELSR_P7_Msk & ((value) << PIO_ELSR_P7_Pos)) +#define PIO_ELSR_P8_Pos _U_(8) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P8_Msk (_U_(0x1) << PIO_ELSR_P8_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P8(value) (PIO_ELSR_P8_Msk & ((value) << PIO_ELSR_P8_Pos)) +#define PIO_ELSR_P9_Pos _U_(9) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P9_Msk (_U_(0x1) << PIO_ELSR_P9_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P9(value) (PIO_ELSR_P9_Msk & ((value) << PIO_ELSR_P9_Pos)) +#define PIO_ELSR_P10_Pos _U_(10) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P10_Msk (_U_(0x1) << PIO_ELSR_P10_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P10(value) (PIO_ELSR_P10_Msk & ((value) << PIO_ELSR_P10_Pos)) +#define PIO_ELSR_P11_Pos _U_(11) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P11_Msk (_U_(0x1) << PIO_ELSR_P11_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P11(value) (PIO_ELSR_P11_Msk & ((value) << PIO_ELSR_P11_Pos)) +#define PIO_ELSR_P12_Pos _U_(12) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P12_Msk (_U_(0x1) << PIO_ELSR_P12_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P12(value) (PIO_ELSR_P12_Msk & ((value) << PIO_ELSR_P12_Pos)) +#define PIO_ELSR_P13_Pos _U_(13) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P13_Msk (_U_(0x1) << PIO_ELSR_P13_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P13(value) (PIO_ELSR_P13_Msk & ((value) << PIO_ELSR_P13_Pos)) +#define PIO_ELSR_P14_Pos _U_(14) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P14_Msk (_U_(0x1) << PIO_ELSR_P14_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P14(value) (PIO_ELSR_P14_Msk & ((value) << PIO_ELSR_P14_Pos)) +#define PIO_ELSR_P15_Pos _U_(15) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P15_Msk (_U_(0x1) << PIO_ELSR_P15_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P15(value) (PIO_ELSR_P15_Msk & ((value) << PIO_ELSR_P15_Pos)) +#define PIO_ELSR_P16_Pos _U_(16) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P16_Msk (_U_(0x1) << PIO_ELSR_P16_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P16(value) (PIO_ELSR_P16_Msk & ((value) << PIO_ELSR_P16_Pos)) +#define PIO_ELSR_P17_Pos _U_(17) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P17_Msk (_U_(0x1) << PIO_ELSR_P17_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P17(value) (PIO_ELSR_P17_Msk & ((value) << PIO_ELSR_P17_Pos)) +#define PIO_ELSR_P18_Pos _U_(18) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P18_Msk (_U_(0x1) << PIO_ELSR_P18_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P18(value) (PIO_ELSR_P18_Msk & ((value) << PIO_ELSR_P18_Pos)) +#define PIO_ELSR_P19_Pos _U_(19) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P19_Msk (_U_(0x1) << PIO_ELSR_P19_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P19(value) (PIO_ELSR_P19_Msk & ((value) << PIO_ELSR_P19_Pos)) +#define PIO_ELSR_P20_Pos _U_(20) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P20_Msk (_U_(0x1) << PIO_ELSR_P20_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P20(value) (PIO_ELSR_P20_Msk & ((value) << PIO_ELSR_P20_Pos)) +#define PIO_ELSR_P21_Pos _U_(21) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P21_Msk (_U_(0x1) << PIO_ELSR_P21_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P21(value) (PIO_ELSR_P21_Msk & ((value) << PIO_ELSR_P21_Pos)) +#define PIO_ELSR_P22_Pos _U_(22) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P22_Msk (_U_(0x1) << PIO_ELSR_P22_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P22(value) (PIO_ELSR_P22_Msk & ((value) << PIO_ELSR_P22_Pos)) +#define PIO_ELSR_P23_Pos _U_(23) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P23_Msk (_U_(0x1) << PIO_ELSR_P23_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P23(value) (PIO_ELSR_P23_Msk & ((value) << PIO_ELSR_P23_Pos)) +#define PIO_ELSR_P24_Pos _U_(24) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P24_Msk (_U_(0x1) << PIO_ELSR_P24_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P24(value) (PIO_ELSR_P24_Msk & ((value) << PIO_ELSR_P24_Pos)) +#define PIO_ELSR_P25_Pos _U_(25) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P25_Msk (_U_(0x1) << PIO_ELSR_P25_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P25(value) (PIO_ELSR_P25_Msk & ((value) << PIO_ELSR_P25_Pos)) +#define PIO_ELSR_P26_Pos _U_(26) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P26_Msk (_U_(0x1) << PIO_ELSR_P26_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P26(value) (PIO_ELSR_P26_Msk & ((value) << PIO_ELSR_P26_Pos)) +#define PIO_ELSR_P27_Pos _U_(27) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P27_Msk (_U_(0x1) << PIO_ELSR_P27_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P27(value) (PIO_ELSR_P27_Msk & ((value) << PIO_ELSR_P27_Pos)) +#define PIO_ELSR_P28_Pos _U_(28) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P28_Msk (_U_(0x1) << PIO_ELSR_P28_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P28(value) (PIO_ELSR_P28_Msk & ((value) << PIO_ELSR_P28_Pos)) +#define PIO_ELSR_P29_Pos _U_(29) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P29_Msk (_U_(0x1) << PIO_ELSR_P29_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P29(value) (PIO_ELSR_P29_Msk & ((value) << PIO_ELSR_P29_Pos)) +#define PIO_ELSR_P30_Pos _U_(30) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P30_Msk (_U_(0x1) << PIO_ELSR_P30_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P30(value) (PIO_ELSR_P30_Msk & ((value) << PIO_ELSR_P30_Pos)) +#define PIO_ELSR_P31_Pos _U_(31) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P31_Msk (_U_(0x1) << PIO_ELSR_P31_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P31(value) (PIO_ELSR_P31_Msk & ((value) << PIO_ELSR_P31_Pos)) +#define PIO_ELSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ELSR) Register Mask */ + +#define PIO_ELSR_P_Pos _U_(0) /**< (PIO_ELSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ELSR_P_Pos) /**< (PIO_ELSR Mask) P */ +#define PIO_ELSR_P(value) (PIO_ELSR_P_Msk & ((value) << PIO_ELSR_P_Pos)) + +/* -------- PIO_FELLSR : (PIO Offset: 0xD0) ( /W 32) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0_Pos _U_(0) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P0_Msk (_U_(0x1) << PIO_FELLSR_P0_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P0(value) (PIO_FELLSR_P0_Msk & ((value) << PIO_FELLSR_P0_Pos)) +#define PIO_FELLSR_P1_Pos _U_(1) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P1_Msk (_U_(0x1) << PIO_FELLSR_P1_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P1(value) (PIO_FELLSR_P1_Msk & ((value) << PIO_FELLSR_P1_Pos)) +#define PIO_FELLSR_P2_Pos _U_(2) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P2_Msk (_U_(0x1) << PIO_FELLSR_P2_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P2(value) (PIO_FELLSR_P2_Msk & ((value) << PIO_FELLSR_P2_Pos)) +#define PIO_FELLSR_P3_Pos _U_(3) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P3_Msk (_U_(0x1) << PIO_FELLSR_P3_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P3(value) (PIO_FELLSR_P3_Msk & ((value) << PIO_FELLSR_P3_Pos)) +#define PIO_FELLSR_P4_Pos _U_(4) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P4_Msk (_U_(0x1) << PIO_FELLSR_P4_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P4(value) (PIO_FELLSR_P4_Msk & ((value) << PIO_FELLSR_P4_Pos)) +#define PIO_FELLSR_P5_Pos _U_(5) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P5_Msk (_U_(0x1) << PIO_FELLSR_P5_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P5(value) (PIO_FELLSR_P5_Msk & ((value) << PIO_FELLSR_P5_Pos)) +#define PIO_FELLSR_P6_Pos _U_(6) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P6_Msk (_U_(0x1) << PIO_FELLSR_P6_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P6(value) (PIO_FELLSR_P6_Msk & ((value) << PIO_FELLSR_P6_Pos)) +#define PIO_FELLSR_P7_Pos _U_(7) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P7_Msk (_U_(0x1) << PIO_FELLSR_P7_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P7(value) (PIO_FELLSR_P7_Msk & ((value) << PIO_FELLSR_P7_Pos)) +#define PIO_FELLSR_P8_Pos _U_(8) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P8_Msk (_U_(0x1) << PIO_FELLSR_P8_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P8(value) (PIO_FELLSR_P8_Msk & ((value) << PIO_FELLSR_P8_Pos)) +#define PIO_FELLSR_P9_Pos _U_(9) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P9_Msk (_U_(0x1) << PIO_FELLSR_P9_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P9(value) (PIO_FELLSR_P9_Msk & ((value) << PIO_FELLSR_P9_Pos)) +#define PIO_FELLSR_P10_Pos _U_(10) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P10_Msk (_U_(0x1) << PIO_FELLSR_P10_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P10(value) (PIO_FELLSR_P10_Msk & ((value) << PIO_FELLSR_P10_Pos)) +#define PIO_FELLSR_P11_Pos _U_(11) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P11_Msk (_U_(0x1) << PIO_FELLSR_P11_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P11(value) (PIO_FELLSR_P11_Msk & ((value) << PIO_FELLSR_P11_Pos)) +#define PIO_FELLSR_P12_Pos _U_(12) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P12_Msk (_U_(0x1) << PIO_FELLSR_P12_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P12(value) (PIO_FELLSR_P12_Msk & ((value) << PIO_FELLSR_P12_Pos)) +#define PIO_FELLSR_P13_Pos _U_(13) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P13_Msk (_U_(0x1) << PIO_FELLSR_P13_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P13(value) (PIO_FELLSR_P13_Msk & ((value) << PIO_FELLSR_P13_Pos)) +#define PIO_FELLSR_P14_Pos _U_(14) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P14_Msk (_U_(0x1) << PIO_FELLSR_P14_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P14(value) (PIO_FELLSR_P14_Msk & ((value) << PIO_FELLSR_P14_Pos)) +#define PIO_FELLSR_P15_Pos _U_(15) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P15_Msk (_U_(0x1) << PIO_FELLSR_P15_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P15(value) (PIO_FELLSR_P15_Msk & ((value) << PIO_FELLSR_P15_Pos)) +#define PIO_FELLSR_P16_Pos _U_(16) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P16_Msk (_U_(0x1) << PIO_FELLSR_P16_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P16(value) (PIO_FELLSR_P16_Msk & ((value) << PIO_FELLSR_P16_Pos)) +#define PIO_FELLSR_P17_Pos _U_(17) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P17_Msk (_U_(0x1) << PIO_FELLSR_P17_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P17(value) (PIO_FELLSR_P17_Msk & ((value) << PIO_FELLSR_P17_Pos)) +#define PIO_FELLSR_P18_Pos _U_(18) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P18_Msk (_U_(0x1) << PIO_FELLSR_P18_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P18(value) (PIO_FELLSR_P18_Msk & ((value) << PIO_FELLSR_P18_Pos)) +#define PIO_FELLSR_P19_Pos _U_(19) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P19_Msk (_U_(0x1) << PIO_FELLSR_P19_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P19(value) (PIO_FELLSR_P19_Msk & ((value) << PIO_FELLSR_P19_Pos)) +#define PIO_FELLSR_P20_Pos _U_(20) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P20_Msk (_U_(0x1) << PIO_FELLSR_P20_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P20(value) (PIO_FELLSR_P20_Msk & ((value) << PIO_FELLSR_P20_Pos)) +#define PIO_FELLSR_P21_Pos _U_(21) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P21_Msk (_U_(0x1) << PIO_FELLSR_P21_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P21(value) (PIO_FELLSR_P21_Msk & ((value) << PIO_FELLSR_P21_Pos)) +#define PIO_FELLSR_P22_Pos _U_(22) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P22_Msk (_U_(0x1) << PIO_FELLSR_P22_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P22(value) (PIO_FELLSR_P22_Msk & ((value) << PIO_FELLSR_P22_Pos)) +#define PIO_FELLSR_P23_Pos _U_(23) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P23_Msk (_U_(0x1) << PIO_FELLSR_P23_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P23(value) (PIO_FELLSR_P23_Msk & ((value) << PIO_FELLSR_P23_Pos)) +#define PIO_FELLSR_P24_Pos _U_(24) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P24_Msk (_U_(0x1) << PIO_FELLSR_P24_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P24(value) (PIO_FELLSR_P24_Msk & ((value) << PIO_FELLSR_P24_Pos)) +#define PIO_FELLSR_P25_Pos _U_(25) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P25_Msk (_U_(0x1) << PIO_FELLSR_P25_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P25(value) (PIO_FELLSR_P25_Msk & ((value) << PIO_FELLSR_P25_Pos)) +#define PIO_FELLSR_P26_Pos _U_(26) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P26_Msk (_U_(0x1) << PIO_FELLSR_P26_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P26(value) (PIO_FELLSR_P26_Msk & ((value) << PIO_FELLSR_P26_Pos)) +#define PIO_FELLSR_P27_Pos _U_(27) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P27_Msk (_U_(0x1) << PIO_FELLSR_P27_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P27(value) (PIO_FELLSR_P27_Msk & ((value) << PIO_FELLSR_P27_Pos)) +#define PIO_FELLSR_P28_Pos _U_(28) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P28_Msk (_U_(0x1) << PIO_FELLSR_P28_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P28(value) (PIO_FELLSR_P28_Msk & ((value) << PIO_FELLSR_P28_Pos)) +#define PIO_FELLSR_P29_Pos _U_(29) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P29_Msk (_U_(0x1) << PIO_FELLSR_P29_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P29(value) (PIO_FELLSR_P29_Msk & ((value) << PIO_FELLSR_P29_Pos)) +#define PIO_FELLSR_P30_Pos _U_(30) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P30_Msk (_U_(0x1) << PIO_FELLSR_P30_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P30(value) (PIO_FELLSR_P30_Msk & ((value) << PIO_FELLSR_P30_Pos)) +#define PIO_FELLSR_P31_Pos _U_(31) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P31_Msk (_U_(0x1) << PIO_FELLSR_P31_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P31(value) (PIO_FELLSR_P31_Msk & ((value) << PIO_FELLSR_P31_Pos)) +#define PIO_FELLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FELLSR) Register Mask */ + +#define PIO_FELLSR_P_Pos _U_(0) /**< (PIO_FELLSR Position) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FELLSR_P_Pos) /**< (PIO_FELLSR Mask) P */ +#define PIO_FELLSR_P(value) (PIO_FELLSR_P_Msk & ((value) << PIO_FELLSR_P_Pos)) + +/* -------- PIO_REHLSR : (PIO Offset: 0xD4) ( /W 32) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0_Pos _U_(0) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P0_Msk (_U_(0x1) << PIO_REHLSR_P0_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P0(value) (PIO_REHLSR_P0_Msk & ((value) << PIO_REHLSR_P0_Pos)) +#define PIO_REHLSR_P1_Pos _U_(1) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P1_Msk (_U_(0x1) << PIO_REHLSR_P1_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P1(value) (PIO_REHLSR_P1_Msk & ((value) << PIO_REHLSR_P1_Pos)) +#define PIO_REHLSR_P2_Pos _U_(2) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P2_Msk (_U_(0x1) << PIO_REHLSR_P2_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P2(value) (PIO_REHLSR_P2_Msk & ((value) << PIO_REHLSR_P2_Pos)) +#define PIO_REHLSR_P3_Pos _U_(3) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P3_Msk (_U_(0x1) << PIO_REHLSR_P3_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P3(value) (PIO_REHLSR_P3_Msk & ((value) << PIO_REHLSR_P3_Pos)) +#define PIO_REHLSR_P4_Pos _U_(4) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P4_Msk (_U_(0x1) << PIO_REHLSR_P4_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P4(value) (PIO_REHLSR_P4_Msk & ((value) << PIO_REHLSR_P4_Pos)) +#define PIO_REHLSR_P5_Pos _U_(5) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P5_Msk (_U_(0x1) << PIO_REHLSR_P5_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P5(value) (PIO_REHLSR_P5_Msk & ((value) << PIO_REHLSR_P5_Pos)) +#define PIO_REHLSR_P6_Pos _U_(6) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P6_Msk (_U_(0x1) << PIO_REHLSR_P6_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P6(value) (PIO_REHLSR_P6_Msk & ((value) << PIO_REHLSR_P6_Pos)) +#define PIO_REHLSR_P7_Pos _U_(7) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P7_Msk (_U_(0x1) << PIO_REHLSR_P7_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P7(value) (PIO_REHLSR_P7_Msk & ((value) << PIO_REHLSR_P7_Pos)) +#define PIO_REHLSR_P8_Pos _U_(8) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P8_Msk (_U_(0x1) << PIO_REHLSR_P8_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P8(value) (PIO_REHLSR_P8_Msk & ((value) << PIO_REHLSR_P8_Pos)) +#define PIO_REHLSR_P9_Pos _U_(9) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P9_Msk (_U_(0x1) << PIO_REHLSR_P9_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P9(value) (PIO_REHLSR_P9_Msk & ((value) << PIO_REHLSR_P9_Pos)) +#define PIO_REHLSR_P10_Pos _U_(10) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P10_Msk (_U_(0x1) << PIO_REHLSR_P10_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P10(value) (PIO_REHLSR_P10_Msk & ((value) << PIO_REHLSR_P10_Pos)) +#define PIO_REHLSR_P11_Pos _U_(11) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P11_Msk (_U_(0x1) << PIO_REHLSR_P11_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P11(value) (PIO_REHLSR_P11_Msk & ((value) << PIO_REHLSR_P11_Pos)) +#define PIO_REHLSR_P12_Pos _U_(12) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P12_Msk (_U_(0x1) << PIO_REHLSR_P12_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P12(value) (PIO_REHLSR_P12_Msk & ((value) << PIO_REHLSR_P12_Pos)) +#define PIO_REHLSR_P13_Pos _U_(13) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P13_Msk (_U_(0x1) << PIO_REHLSR_P13_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P13(value) (PIO_REHLSR_P13_Msk & ((value) << PIO_REHLSR_P13_Pos)) +#define PIO_REHLSR_P14_Pos _U_(14) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P14_Msk (_U_(0x1) << PIO_REHLSR_P14_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P14(value) (PIO_REHLSR_P14_Msk & ((value) << PIO_REHLSR_P14_Pos)) +#define PIO_REHLSR_P15_Pos _U_(15) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P15_Msk (_U_(0x1) << PIO_REHLSR_P15_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P15(value) (PIO_REHLSR_P15_Msk & ((value) << PIO_REHLSR_P15_Pos)) +#define PIO_REHLSR_P16_Pos _U_(16) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P16_Msk (_U_(0x1) << PIO_REHLSR_P16_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P16(value) (PIO_REHLSR_P16_Msk & ((value) << PIO_REHLSR_P16_Pos)) +#define PIO_REHLSR_P17_Pos _U_(17) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P17_Msk (_U_(0x1) << PIO_REHLSR_P17_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P17(value) (PIO_REHLSR_P17_Msk & ((value) << PIO_REHLSR_P17_Pos)) +#define PIO_REHLSR_P18_Pos _U_(18) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P18_Msk (_U_(0x1) << PIO_REHLSR_P18_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P18(value) (PIO_REHLSR_P18_Msk & ((value) << PIO_REHLSR_P18_Pos)) +#define PIO_REHLSR_P19_Pos _U_(19) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P19_Msk (_U_(0x1) << PIO_REHLSR_P19_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P19(value) (PIO_REHLSR_P19_Msk & ((value) << PIO_REHLSR_P19_Pos)) +#define PIO_REHLSR_P20_Pos _U_(20) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P20_Msk (_U_(0x1) << PIO_REHLSR_P20_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P20(value) (PIO_REHLSR_P20_Msk & ((value) << PIO_REHLSR_P20_Pos)) +#define PIO_REHLSR_P21_Pos _U_(21) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P21_Msk (_U_(0x1) << PIO_REHLSR_P21_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P21(value) (PIO_REHLSR_P21_Msk & ((value) << PIO_REHLSR_P21_Pos)) +#define PIO_REHLSR_P22_Pos _U_(22) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P22_Msk (_U_(0x1) << PIO_REHLSR_P22_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P22(value) (PIO_REHLSR_P22_Msk & ((value) << PIO_REHLSR_P22_Pos)) +#define PIO_REHLSR_P23_Pos _U_(23) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P23_Msk (_U_(0x1) << PIO_REHLSR_P23_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P23(value) (PIO_REHLSR_P23_Msk & ((value) << PIO_REHLSR_P23_Pos)) +#define PIO_REHLSR_P24_Pos _U_(24) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P24_Msk (_U_(0x1) << PIO_REHLSR_P24_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P24(value) (PIO_REHLSR_P24_Msk & ((value) << PIO_REHLSR_P24_Pos)) +#define PIO_REHLSR_P25_Pos _U_(25) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P25_Msk (_U_(0x1) << PIO_REHLSR_P25_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P25(value) (PIO_REHLSR_P25_Msk & ((value) << PIO_REHLSR_P25_Pos)) +#define PIO_REHLSR_P26_Pos _U_(26) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P26_Msk (_U_(0x1) << PIO_REHLSR_P26_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P26(value) (PIO_REHLSR_P26_Msk & ((value) << PIO_REHLSR_P26_Pos)) +#define PIO_REHLSR_P27_Pos _U_(27) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P27_Msk (_U_(0x1) << PIO_REHLSR_P27_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P27(value) (PIO_REHLSR_P27_Msk & ((value) << PIO_REHLSR_P27_Pos)) +#define PIO_REHLSR_P28_Pos _U_(28) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P28_Msk (_U_(0x1) << PIO_REHLSR_P28_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P28(value) (PIO_REHLSR_P28_Msk & ((value) << PIO_REHLSR_P28_Pos)) +#define PIO_REHLSR_P29_Pos _U_(29) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P29_Msk (_U_(0x1) << PIO_REHLSR_P29_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P29(value) (PIO_REHLSR_P29_Msk & ((value) << PIO_REHLSR_P29_Pos)) +#define PIO_REHLSR_P30_Pos _U_(30) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P30_Msk (_U_(0x1) << PIO_REHLSR_P30_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P30(value) (PIO_REHLSR_P30_Msk & ((value) << PIO_REHLSR_P30_Pos)) +#define PIO_REHLSR_P31_Pos _U_(31) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P31_Msk (_U_(0x1) << PIO_REHLSR_P31_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P31(value) (PIO_REHLSR_P31_Msk & ((value) << PIO_REHLSR_P31_Pos)) +#define PIO_REHLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_REHLSR) Register Mask */ + +#define PIO_REHLSR_P_Pos _U_(0) /**< (PIO_REHLSR Position) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_REHLSR_P_Pos) /**< (PIO_REHLSR Mask) P */ +#define PIO_REHLSR_P(value) (PIO_REHLSR_P_Msk & ((value) << PIO_REHLSR_P_Pos)) + +/* -------- PIO_FRLHSR : (PIO Offset: 0xD8) ( R/ 32) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0_Pos _U_(0) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P0_Msk (_U_(0x1) << PIO_FRLHSR_P0_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P0(value) (PIO_FRLHSR_P0_Msk & ((value) << PIO_FRLHSR_P0_Pos)) +#define PIO_FRLHSR_P1_Pos _U_(1) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P1_Msk (_U_(0x1) << PIO_FRLHSR_P1_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P1(value) (PIO_FRLHSR_P1_Msk & ((value) << PIO_FRLHSR_P1_Pos)) +#define PIO_FRLHSR_P2_Pos _U_(2) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P2_Msk (_U_(0x1) << PIO_FRLHSR_P2_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P2(value) (PIO_FRLHSR_P2_Msk & ((value) << PIO_FRLHSR_P2_Pos)) +#define PIO_FRLHSR_P3_Pos _U_(3) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P3_Msk (_U_(0x1) << PIO_FRLHSR_P3_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P3(value) (PIO_FRLHSR_P3_Msk & ((value) << PIO_FRLHSR_P3_Pos)) +#define PIO_FRLHSR_P4_Pos _U_(4) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P4_Msk (_U_(0x1) << PIO_FRLHSR_P4_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P4(value) (PIO_FRLHSR_P4_Msk & ((value) << PIO_FRLHSR_P4_Pos)) +#define PIO_FRLHSR_P5_Pos _U_(5) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P5_Msk (_U_(0x1) << PIO_FRLHSR_P5_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P5(value) (PIO_FRLHSR_P5_Msk & ((value) << PIO_FRLHSR_P5_Pos)) +#define PIO_FRLHSR_P6_Pos _U_(6) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P6_Msk (_U_(0x1) << PIO_FRLHSR_P6_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P6(value) (PIO_FRLHSR_P6_Msk & ((value) << PIO_FRLHSR_P6_Pos)) +#define PIO_FRLHSR_P7_Pos _U_(7) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P7_Msk (_U_(0x1) << PIO_FRLHSR_P7_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P7(value) (PIO_FRLHSR_P7_Msk & ((value) << PIO_FRLHSR_P7_Pos)) +#define PIO_FRLHSR_P8_Pos _U_(8) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P8_Msk (_U_(0x1) << PIO_FRLHSR_P8_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P8(value) (PIO_FRLHSR_P8_Msk & ((value) << PIO_FRLHSR_P8_Pos)) +#define PIO_FRLHSR_P9_Pos _U_(9) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P9_Msk (_U_(0x1) << PIO_FRLHSR_P9_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P9(value) (PIO_FRLHSR_P9_Msk & ((value) << PIO_FRLHSR_P9_Pos)) +#define PIO_FRLHSR_P10_Pos _U_(10) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P10_Msk (_U_(0x1) << PIO_FRLHSR_P10_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P10(value) (PIO_FRLHSR_P10_Msk & ((value) << PIO_FRLHSR_P10_Pos)) +#define PIO_FRLHSR_P11_Pos _U_(11) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P11_Msk (_U_(0x1) << PIO_FRLHSR_P11_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P11(value) (PIO_FRLHSR_P11_Msk & ((value) << PIO_FRLHSR_P11_Pos)) +#define PIO_FRLHSR_P12_Pos _U_(12) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P12_Msk (_U_(0x1) << PIO_FRLHSR_P12_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P12(value) (PIO_FRLHSR_P12_Msk & ((value) << PIO_FRLHSR_P12_Pos)) +#define PIO_FRLHSR_P13_Pos _U_(13) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P13_Msk (_U_(0x1) << PIO_FRLHSR_P13_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P13(value) (PIO_FRLHSR_P13_Msk & ((value) << PIO_FRLHSR_P13_Pos)) +#define PIO_FRLHSR_P14_Pos _U_(14) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P14_Msk (_U_(0x1) << PIO_FRLHSR_P14_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P14(value) (PIO_FRLHSR_P14_Msk & ((value) << PIO_FRLHSR_P14_Pos)) +#define PIO_FRLHSR_P15_Pos _U_(15) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P15_Msk (_U_(0x1) << PIO_FRLHSR_P15_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P15(value) (PIO_FRLHSR_P15_Msk & ((value) << PIO_FRLHSR_P15_Pos)) +#define PIO_FRLHSR_P16_Pos _U_(16) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P16_Msk (_U_(0x1) << PIO_FRLHSR_P16_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P16(value) (PIO_FRLHSR_P16_Msk & ((value) << PIO_FRLHSR_P16_Pos)) +#define PIO_FRLHSR_P17_Pos _U_(17) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P17_Msk (_U_(0x1) << PIO_FRLHSR_P17_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P17(value) (PIO_FRLHSR_P17_Msk & ((value) << PIO_FRLHSR_P17_Pos)) +#define PIO_FRLHSR_P18_Pos _U_(18) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P18_Msk (_U_(0x1) << PIO_FRLHSR_P18_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P18(value) (PIO_FRLHSR_P18_Msk & ((value) << PIO_FRLHSR_P18_Pos)) +#define PIO_FRLHSR_P19_Pos _U_(19) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P19_Msk (_U_(0x1) << PIO_FRLHSR_P19_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P19(value) (PIO_FRLHSR_P19_Msk & ((value) << PIO_FRLHSR_P19_Pos)) +#define PIO_FRLHSR_P20_Pos _U_(20) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P20_Msk (_U_(0x1) << PIO_FRLHSR_P20_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P20(value) (PIO_FRLHSR_P20_Msk & ((value) << PIO_FRLHSR_P20_Pos)) +#define PIO_FRLHSR_P21_Pos _U_(21) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P21_Msk (_U_(0x1) << PIO_FRLHSR_P21_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P21(value) (PIO_FRLHSR_P21_Msk & ((value) << PIO_FRLHSR_P21_Pos)) +#define PIO_FRLHSR_P22_Pos _U_(22) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P22_Msk (_U_(0x1) << PIO_FRLHSR_P22_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P22(value) (PIO_FRLHSR_P22_Msk & ((value) << PIO_FRLHSR_P22_Pos)) +#define PIO_FRLHSR_P23_Pos _U_(23) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P23_Msk (_U_(0x1) << PIO_FRLHSR_P23_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P23(value) (PIO_FRLHSR_P23_Msk & ((value) << PIO_FRLHSR_P23_Pos)) +#define PIO_FRLHSR_P24_Pos _U_(24) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P24_Msk (_U_(0x1) << PIO_FRLHSR_P24_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P24(value) (PIO_FRLHSR_P24_Msk & ((value) << PIO_FRLHSR_P24_Pos)) +#define PIO_FRLHSR_P25_Pos _U_(25) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P25_Msk (_U_(0x1) << PIO_FRLHSR_P25_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P25(value) (PIO_FRLHSR_P25_Msk & ((value) << PIO_FRLHSR_P25_Pos)) +#define PIO_FRLHSR_P26_Pos _U_(26) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P26_Msk (_U_(0x1) << PIO_FRLHSR_P26_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P26(value) (PIO_FRLHSR_P26_Msk & ((value) << PIO_FRLHSR_P26_Pos)) +#define PIO_FRLHSR_P27_Pos _U_(27) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P27_Msk (_U_(0x1) << PIO_FRLHSR_P27_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P27(value) (PIO_FRLHSR_P27_Msk & ((value) << PIO_FRLHSR_P27_Pos)) +#define PIO_FRLHSR_P28_Pos _U_(28) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P28_Msk (_U_(0x1) << PIO_FRLHSR_P28_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P28(value) (PIO_FRLHSR_P28_Msk & ((value) << PIO_FRLHSR_P28_Pos)) +#define PIO_FRLHSR_P29_Pos _U_(29) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P29_Msk (_U_(0x1) << PIO_FRLHSR_P29_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P29(value) (PIO_FRLHSR_P29_Msk & ((value) << PIO_FRLHSR_P29_Pos)) +#define PIO_FRLHSR_P30_Pos _U_(30) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P30_Msk (_U_(0x1) << PIO_FRLHSR_P30_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P30(value) (PIO_FRLHSR_P30_Msk & ((value) << PIO_FRLHSR_P30_Pos)) +#define PIO_FRLHSR_P31_Pos _U_(31) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P31_Msk (_U_(0x1) << PIO_FRLHSR_P31_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P31(value) (PIO_FRLHSR_P31_Msk & ((value) << PIO_FRLHSR_P31_Pos)) +#define PIO_FRLHSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FRLHSR) Register Mask */ + +#define PIO_FRLHSR_P_Pos _U_(0) /**< (PIO_FRLHSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FRLHSR_P_Pos) /**< (PIO_FRLHSR Mask) P */ +#define PIO_FRLHSR_P(value) (PIO_FRLHSR_P_Msk & ((value) << PIO_FRLHSR_P_Pos)) + +/* -------- PIO_LOCKSR : (PIO Offset: 0xE0) ( R/ 32) Lock Status -------- */ +#define PIO_LOCKSR_P0_Pos _U_(0) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P0_Msk (_U_(0x1) << PIO_LOCKSR_P0_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P0(value) (PIO_LOCKSR_P0_Msk & ((value) << PIO_LOCKSR_P0_Pos)) +#define PIO_LOCKSR_P1_Pos _U_(1) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P1_Msk (_U_(0x1) << PIO_LOCKSR_P1_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P1(value) (PIO_LOCKSR_P1_Msk & ((value) << PIO_LOCKSR_P1_Pos)) +#define PIO_LOCKSR_P2_Pos _U_(2) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P2_Msk (_U_(0x1) << PIO_LOCKSR_P2_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P2(value) (PIO_LOCKSR_P2_Msk & ((value) << PIO_LOCKSR_P2_Pos)) +#define PIO_LOCKSR_P3_Pos _U_(3) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P3_Msk (_U_(0x1) << PIO_LOCKSR_P3_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P3(value) (PIO_LOCKSR_P3_Msk & ((value) << PIO_LOCKSR_P3_Pos)) +#define PIO_LOCKSR_P4_Pos _U_(4) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P4_Msk (_U_(0x1) << PIO_LOCKSR_P4_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P4(value) (PIO_LOCKSR_P4_Msk & ((value) << PIO_LOCKSR_P4_Pos)) +#define PIO_LOCKSR_P5_Pos _U_(5) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P5_Msk (_U_(0x1) << PIO_LOCKSR_P5_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P5(value) (PIO_LOCKSR_P5_Msk & ((value) << PIO_LOCKSR_P5_Pos)) +#define PIO_LOCKSR_P6_Pos _U_(6) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P6_Msk (_U_(0x1) << PIO_LOCKSR_P6_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P6(value) (PIO_LOCKSR_P6_Msk & ((value) << PIO_LOCKSR_P6_Pos)) +#define PIO_LOCKSR_P7_Pos _U_(7) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P7_Msk (_U_(0x1) << PIO_LOCKSR_P7_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P7(value) (PIO_LOCKSR_P7_Msk & ((value) << PIO_LOCKSR_P7_Pos)) +#define PIO_LOCKSR_P8_Pos _U_(8) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P8_Msk (_U_(0x1) << PIO_LOCKSR_P8_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P8(value) (PIO_LOCKSR_P8_Msk & ((value) << PIO_LOCKSR_P8_Pos)) +#define PIO_LOCKSR_P9_Pos _U_(9) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P9_Msk (_U_(0x1) << PIO_LOCKSR_P9_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P9(value) (PIO_LOCKSR_P9_Msk & ((value) << PIO_LOCKSR_P9_Pos)) +#define PIO_LOCKSR_P10_Pos _U_(10) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P10_Msk (_U_(0x1) << PIO_LOCKSR_P10_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P10(value) (PIO_LOCKSR_P10_Msk & ((value) << PIO_LOCKSR_P10_Pos)) +#define PIO_LOCKSR_P11_Pos _U_(11) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P11_Msk (_U_(0x1) << PIO_LOCKSR_P11_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P11(value) (PIO_LOCKSR_P11_Msk & ((value) << PIO_LOCKSR_P11_Pos)) +#define PIO_LOCKSR_P12_Pos _U_(12) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P12_Msk (_U_(0x1) << PIO_LOCKSR_P12_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P12(value) (PIO_LOCKSR_P12_Msk & ((value) << PIO_LOCKSR_P12_Pos)) +#define PIO_LOCKSR_P13_Pos _U_(13) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P13_Msk (_U_(0x1) << PIO_LOCKSR_P13_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P13(value) (PIO_LOCKSR_P13_Msk & ((value) << PIO_LOCKSR_P13_Pos)) +#define PIO_LOCKSR_P14_Pos _U_(14) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P14_Msk (_U_(0x1) << PIO_LOCKSR_P14_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P14(value) (PIO_LOCKSR_P14_Msk & ((value) << PIO_LOCKSR_P14_Pos)) +#define PIO_LOCKSR_P15_Pos _U_(15) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P15_Msk (_U_(0x1) << PIO_LOCKSR_P15_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P15(value) (PIO_LOCKSR_P15_Msk & ((value) << PIO_LOCKSR_P15_Pos)) +#define PIO_LOCKSR_P16_Pos _U_(16) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P16_Msk (_U_(0x1) << PIO_LOCKSR_P16_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P16(value) (PIO_LOCKSR_P16_Msk & ((value) << PIO_LOCKSR_P16_Pos)) +#define PIO_LOCKSR_P17_Pos _U_(17) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P17_Msk (_U_(0x1) << PIO_LOCKSR_P17_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P17(value) (PIO_LOCKSR_P17_Msk & ((value) << PIO_LOCKSR_P17_Pos)) +#define PIO_LOCKSR_P18_Pos _U_(18) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P18_Msk (_U_(0x1) << PIO_LOCKSR_P18_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P18(value) (PIO_LOCKSR_P18_Msk & ((value) << PIO_LOCKSR_P18_Pos)) +#define PIO_LOCKSR_P19_Pos _U_(19) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P19_Msk (_U_(0x1) << PIO_LOCKSR_P19_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P19(value) (PIO_LOCKSR_P19_Msk & ((value) << PIO_LOCKSR_P19_Pos)) +#define PIO_LOCKSR_P20_Pos _U_(20) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P20_Msk (_U_(0x1) << PIO_LOCKSR_P20_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P20(value) (PIO_LOCKSR_P20_Msk & ((value) << PIO_LOCKSR_P20_Pos)) +#define PIO_LOCKSR_P21_Pos _U_(21) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P21_Msk (_U_(0x1) << PIO_LOCKSR_P21_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P21(value) (PIO_LOCKSR_P21_Msk & ((value) << PIO_LOCKSR_P21_Pos)) +#define PIO_LOCKSR_P22_Pos _U_(22) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P22_Msk (_U_(0x1) << PIO_LOCKSR_P22_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P22(value) (PIO_LOCKSR_P22_Msk & ((value) << PIO_LOCKSR_P22_Pos)) +#define PIO_LOCKSR_P23_Pos _U_(23) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P23_Msk (_U_(0x1) << PIO_LOCKSR_P23_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P23(value) (PIO_LOCKSR_P23_Msk & ((value) << PIO_LOCKSR_P23_Pos)) +#define PIO_LOCKSR_P24_Pos _U_(24) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P24_Msk (_U_(0x1) << PIO_LOCKSR_P24_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P24(value) (PIO_LOCKSR_P24_Msk & ((value) << PIO_LOCKSR_P24_Pos)) +#define PIO_LOCKSR_P25_Pos _U_(25) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P25_Msk (_U_(0x1) << PIO_LOCKSR_P25_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P25(value) (PIO_LOCKSR_P25_Msk & ((value) << PIO_LOCKSR_P25_Pos)) +#define PIO_LOCKSR_P26_Pos _U_(26) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P26_Msk (_U_(0x1) << PIO_LOCKSR_P26_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P26(value) (PIO_LOCKSR_P26_Msk & ((value) << PIO_LOCKSR_P26_Pos)) +#define PIO_LOCKSR_P27_Pos _U_(27) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P27_Msk (_U_(0x1) << PIO_LOCKSR_P27_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P27(value) (PIO_LOCKSR_P27_Msk & ((value) << PIO_LOCKSR_P27_Pos)) +#define PIO_LOCKSR_P28_Pos _U_(28) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P28_Msk (_U_(0x1) << PIO_LOCKSR_P28_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P28(value) (PIO_LOCKSR_P28_Msk & ((value) << PIO_LOCKSR_P28_Pos)) +#define PIO_LOCKSR_P29_Pos _U_(29) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P29_Msk (_U_(0x1) << PIO_LOCKSR_P29_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P29(value) (PIO_LOCKSR_P29_Msk & ((value) << PIO_LOCKSR_P29_Pos)) +#define PIO_LOCKSR_P30_Pos _U_(30) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P30_Msk (_U_(0x1) << PIO_LOCKSR_P30_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P30(value) (PIO_LOCKSR_P30_Msk & ((value) << PIO_LOCKSR_P30_Pos)) +#define PIO_LOCKSR_P31_Pos _U_(31) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P31_Msk (_U_(0x1) << PIO_LOCKSR_P31_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P31(value) (PIO_LOCKSR_P31_Msk & ((value) << PIO_LOCKSR_P31_Pos)) +#define PIO_LOCKSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LOCKSR) Register Mask */ + +#define PIO_LOCKSR_P_Pos _U_(0) /**< (PIO_LOCKSR Position) Lock Status */ +#define PIO_LOCKSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LOCKSR_P_Pos) /**< (PIO_LOCKSR Mask) P */ +#define PIO_LOCKSR_P(value) (PIO_LOCKSR_P_Msk & ((value) << PIO_LOCKSR_P_Pos)) + +/* -------- PIO_WPMR : (PIO Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN_Pos _U_(0) /**< (PIO_WPMR) Write Protection Enable Position */ +#define PIO_WPMR_WPEN_Msk (_U_(0x1) << PIO_WPMR_WPEN_Pos) /**< (PIO_WPMR) Write Protection Enable Mask */ +#define PIO_WPMR_WPEN(value) (PIO_WPMR_WPEN_Msk & ((value) << PIO_WPMR_WPEN_Pos)) +#define PIO_WPMR_WPKEY_Pos _U_(8) /**< (PIO_WPMR) Write Protection Key Position */ +#define PIO_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Write Protection Key Mask */ +#define PIO_WPMR_WPKEY(value) (PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)) +#define PIO_WPMR_WPKEY_PASSWD_Val _U_(0x50494F) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define PIO_WPMR_WPKEY_PASSWD (PIO_WPMR_WPKEY_PASSWD_Val << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define PIO_WPMR_Msk _U_(0xFFFFFF01) /**< (PIO_WPMR) Register Mask */ + + +/* -------- PIO_WPSR : (PIO Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS_Pos _U_(0) /**< (PIO_WPSR) Write Protection Violation Status Position */ +#define PIO_WPSR_WPVS_Msk (_U_(0x1) << PIO_WPSR_WPVS_Pos) /**< (PIO_WPSR) Write Protection Violation Status Mask */ +#define PIO_WPSR_WPVS(value) (PIO_WPSR_WPVS_Msk & ((value) << PIO_WPSR_WPVS_Pos)) +#define PIO_WPSR_WPVSRC_Pos _U_(8) /**< (PIO_WPSR) Write Protection Violation Source Position */ +#define PIO_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PIO_WPSR_WPVSRC_Pos) /**< (PIO_WPSR) Write Protection Violation Source Mask */ +#define PIO_WPSR_WPVSRC(value) (PIO_WPSR_WPVSRC_Msk & ((value) << PIO_WPSR_WPVSRC_Pos)) +#define PIO_WPSR_Msk _U_(0x00FFFF01) /**< (PIO_WPSR) Register Mask */ + + +/* -------- PIO_SCHMITT : (PIO Offset: 0x100) (R/W 32) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0_Pos _U_(0) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT0_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT0_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT0(value) (PIO_SCHMITT_SCHMITT0_Msk & ((value) << PIO_SCHMITT_SCHMITT0_Pos)) +#define PIO_SCHMITT_SCHMITT1_Pos _U_(1) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT1_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT1_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT1(value) (PIO_SCHMITT_SCHMITT1_Msk & ((value) << PIO_SCHMITT_SCHMITT1_Pos)) +#define PIO_SCHMITT_SCHMITT2_Pos _U_(2) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT2_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT2_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT2(value) (PIO_SCHMITT_SCHMITT2_Msk & ((value) << PIO_SCHMITT_SCHMITT2_Pos)) +#define PIO_SCHMITT_SCHMITT3_Pos _U_(3) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT3_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT3_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT3(value) (PIO_SCHMITT_SCHMITT3_Msk & ((value) << PIO_SCHMITT_SCHMITT3_Pos)) +#define PIO_SCHMITT_SCHMITT4_Pos _U_(4) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT4_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT4_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT4(value) (PIO_SCHMITT_SCHMITT4_Msk & ((value) << PIO_SCHMITT_SCHMITT4_Pos)) +#define PIO_SCHMITT_SCHMITT5_Pos _U_(5) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT5_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT5_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT5(value) (PIO_SCHMITT_SCHMITT5_Msk & ((value) << PIO_SCHMITT_SCHMITT5_Pos)) +#define PIO_SCHMITT_SCHMITT6_Pos _U_(6) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT6_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT6_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT6(value) (PIO_SCHMITT_SCHMITT6_Msk & ((value) << PIO_SCHMITT_SCHMITT6_Pos)) +#define PIO_SCHMITT_SCHMITT7_Pos _U_(7) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT7_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT7_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT7(value) (PIO_SCHMITT_SCHMITT7_Msk & ((value) << PIO_SCHMITT_SCHMITT7_Pos)) +#define PIO_SCHMITT_SCHMITT8_Pos _U_(8) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT8_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT8_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT8(value) (PIO_SCHMITT_SCHMITT8_Msk & ((value) << PIO_SCHMITT_SCHMITT8_Pos)) +#define PIO_SCHMITT_SCHMITT9_Pos _U_(9) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT9_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT9_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT9(value) (PIO_SCHMITT_SCHMITT9_Msk & ((value) << PIO_SCHMITT_SCHMITT9_Pos)) +#define PIO_SCHMITT_SCHMITT10_Pos _U_(10) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT10_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT10_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT10(value) (PIO_SCHMITT_SCHMITT10_Msk & ((value) << PIO_SCHMITT_SCHMITT10_Pos)) +#define PIO_SCHMITT_SCHMITT11_Pos _U_(11) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT11_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT11_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT11(value) (PIO_SCHMITT_SCHMITT11_Msk & ((value) << PIO_SCHMITT_SCHMITT11_Pos)) +#define PIO_SCHMITT_SCHMITT12_Pos _U_(12) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT12_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT12_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT12(value) (PIO_SCHMITT_SCHMITT12_Msk & ((value) << PIO_SCHMITT_SCHMITT12_Pos)) +#define PIO_SCHMITT_SCHMITT13_Pos _U_(13) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT13_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT13_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT13(value) (PIO_SCHMITT_SCHMITT13_Msk & ((value) << PIO_SCHMITT_SCHMITT13_Pos)) +#define PIO_SCHMITT_SCHMITT14_Pos _U_(14) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT14_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT14_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT14(value) (PIO_SCHMITT_SCHMITT14_Msk & ((value) << PIO_SCHMITT_SCHMITT14_Pos)) +#define PIO_SCHMITT_SCHMITT15_Pos _U_(15) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT15_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT15_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT15(value) (PIO_SCHMITT_SCHMITT15_Msk & ((value) << PIO_SCHMITT_SCHMITT15_Pos)) +#define PIO_SCHMITT_SCHMITT16_Pos _U_(16) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT16_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT16_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT16(value) (PIO_SCHMITT_SCHMITT16_Msk & ((value) << PIO_SCHMITT_SCHMITT16_Pos)) +#define PIO_SCHMITT_SCHMITT17_Pos _U_(17) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT17_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT17_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT17(value) (PIO_SCHMITT_SCHMITT17_Msk & ((value) << PIO_SCHMITT_SCHMITT17_Pos)) +#define PIO_SCHMITT_SCHMITT18_Pos _U_(18) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT18_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT18_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT18(value) (PIO_SCHMITT_SCHMITT18_Msk & ((value) << PIO_SCHMITT_SCHMITT18_Pos)) +#define PIO_SCHMITT_SCHMITT19_Pos _U_(19) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT19_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT19_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT19(value) (PIO_SCHMITT_SCHMITT19_Msk & ((value) << PIO_SCHMITT_SCHMITT19_Pos)) +#define PIO_SCHMITT_SCHMITT20_Pos _U_(20) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT20_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT20_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT20(value) (PIO_SCHMITT_SCHMITT20_Msk & ((value) << PIO_SCHMITT_SCHMITT20_Pos)) +#define PIO_SCHMITT_SCHMITT21_Pos _U_(21) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT21_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT21_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT21(value) (PIO_SCHMITT_SCHMITT21_Msk & ((value) << PIO_SCHMITT_SCHMITT21_Pos)) +#define PIO_SCHMITT_SCHMITT22_Pos _U_(22) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT22_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT22_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT22(value) (PIO_SCHMITT_SCHMITT22_Msk & ((value) << PIO_SCHMITT_SCHMITT22_Pos)) +#define PIO_SCHMITT_SCHMITT23_Pos _U_(23) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT23_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT23_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT23(value) (PIO_SCHMITT_SCHMITT23_Msk & ((value) << PIO_SCHMITT_SCHMITT23_Pos)) +#define PIO_SCHMITT_SCHMITT24_Pos _U_(24) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT24_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT24_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT24(value) (PIO_SCHMITT_SCHMITT24_Msk & ((value) << PIO_SCHMITT_SCHMITT24_Pos)) +#define PIO_SCHMITT_SCHMITT25_Pos _U_(25) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT25_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT25_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT25(value) (PIO_SCHMITT_SCHMITT25_Msk & ((value) << PIO_SCHMITT_SCHMITT25_Pos)) +#define PIO_SCHMITT_SCHMITT26_Pos _U_(26) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT26_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT26_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT26(value) (PIO_SCHMITT_SCHMITT26_Msk & ((value) << PIO_SCHMITT_SCHMITT26_Pos)) +#define PIO_SCHMITT_SCHMITT27_Pos _U_(27) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT27_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT27_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT27(value) (PIO_SCHMITT_SCHMITT27_Msk & ((value) << PIO_SCHMITT_SCHMITT27_Pos)) +#define PIO_SCHMITT_SCHMITT28_Pos _U_(28) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT28_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT28_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT28(value) (PIO_SCHMITT_SCHMITT28_Msk & ((value) << PIO_SCHMITT_SCHMITT28_Pos)) +#define PIO_SCHMITT_SCHMITT29_Pos _U_(29) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT29_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT29_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT29(value) (PIO_SCHMITT_SCHMITT29_Msk & ((value) << PIO_SCHMITT_SCHMITT29_Pos)) +#define PIO_SCHMITT_SCHMITT30_Pos _U_(30) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT30_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT30_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT30(value) (PIO_SCHMITT_SCHMITT30_Msk & ((value) << PIO_SCHMITT_SCHMITT30_Pos)) +#define PIO_SCHMITT_SCHMITT31_Pos _U_(31) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT31_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT31_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT31(value) (PIO_SCHMITT_SCHMITT31_Msk & ((value) << PIO_SCHMITT_SCHMITT31_Pos)) +#define PIO_SCHMITT_Msk _U_(0xFFFFFFFF) /**< (PIO_SCHMITT) Register Mask */ + +#define PIO_SCHMITT_SCHMITT_Pos _U_(0) /**< (PIO_SCHMITT Position) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT_Msk (_U_(0xFFFFFFFF) << PIO_SCHMITT_SCHMITT_Pos) /**< (PIO_SCHMITT Mask) SCHMITT */ +#define PIO_SCHMITT_SCHMITT(value) (PIO_SCHMITT_SCHMITT_Msk & ((value) << PIO_SCHMITT_SCHMITT_Pos)) + +/* -------- PIO_DRIVER : (PIO Offset: 0x118) (R/W 32) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0_Pos _U_(0) /**< (PIO_DRIVER) Drive of PIO Line 0 Position */ +#define PIO_DRIVER_LINE0_Msk (_U_(0x1) << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Drive of PIO Line 0 Mask */ +#define PIO_DRIVER_LINE0(value) (PIO_DRIVER_LINE0_Msk & ((value) << PIO_DRIVER_LINE0_Pos)) +#define PIO_DRIVER_LINE0_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (PIO_DRIVER_LINE0_LOW_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (PIO_DRIVER_LINE0_HIGH_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE1_Pos _U_(1) /**< (PIO_DRIVER) Drive of PIO Line 1 Position */ +#define PIO_DRIVER_LINE1_Msk (_U_(0x1) << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Drive of PIO Line 1 Mask */ +#define PIO_DRIVER_LINE1(value) (PIO_DRIVER_LINE1_Msk & ((value) << PIO_DRIVER_LINE1_Pos)) +#define PIO_DRIVER_LINE1_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (PIO_DRIVER_LINE1_LOW_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (PIO_DRIVER_LINE1_HIGH_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE2_Pos _U_(2) /**< (PIO_DRIVER) Drive of PIO Line 2 Position */ +#define PIO_DRIVER_LINE2_Msk (_U_(0x1) << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Drive of PIO Line 2 Mask */ +#define PIO_DRIVER_LINE2(value) (PIO_DRIVER_LINE2_Msk & ((value) << PIO_DRIVER_LINE2_Pos)) +#define PIO_DRIVER_LINE2_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (PIO_DRIVER_LINE2_LOW_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (PIO_DRIVER_LINE2_HIGH_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE3_Pos _U_(3) /**< (PIO_DRIVER) Drive of PIO Line 3 Position */ +#define PIO_DRIVER_LINE3_Msk (_U_(0x1) << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Drive of PIO Line 3 Mask */ +#define PIO_DRIVER_LINE3(value) (PIO_DRIVER_LINE3_Msk & ((value) << PIO_DRIVER_LINE3_Pos)) +#define PIO_DRIVER_LINE3_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (PIO_DRIVER_LINE3_LOW_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (PIO_DRIVER_LINE3_HIGH_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE4_Pos _U_(4) /**< (PIO_DRIVER) Drive of PIO Line 4 Position */ +#define PIO_DRIVER_LINE4_Msk (_U_(0x1) << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Drive of PIO Line 4 Mask */ +#define PIO_DRIVER_LINE4(value) (PIO_DRIVER_LINE4_Msk & ((value) << PIO_DRIVER_LINE4_Pos)) +#define PIO_DRIVER_LINE4_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (PIO_DRIVER_LINE4_LOW_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (PIO_DRIVER_LINE4_HIGH_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE5_Pos _U_(5) /**< (PIO_DRIVER) Drive of PIO Line 5 Position */ +#define PIO_DRIVER_LINE5_Msk (_U_(0x1) << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Drive of PIO Line 5 Mask */ +#define PIO_DRIVER_LINE5(value) (PIO_DRIVER_LINE5_Msk & ((value) << PIO_DRIVER_LINE5_Pos)) +#define PIO_DRIVER_LINE5_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (PIO_DRIVER_LINE5_LOW_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (PIO_DRIVER_LINE5_HIGH_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE6_Pos _U_(6) /**< (PIO_DRIVER) Drive of PIO Line 6 Position */ +#define PIO_DRIVER_LINE6_Msk (_U_(0x1) << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Drive of PIO Line 6 Mask */ +#define PIO_DRIVER_LINE6(value) (PIO_DRIVER_LINE6_Msk & ((value) << PIO_DRIVER_LINE6_Pos)) +#define PIO_DRIVER_LINE6_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (PIO_DRIVER_LINE6_LOW_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (PIO_DRIVER_LINE6_HIGH_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE7_Pos _U_(7) /**< (PIO_DRIVER) Drive of PIO Line 7 Position */ +#define PIO_DRIVER_LINE7_Msk (_U_(0x1) << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Drive of PIO Line 7 Mask */ +#define PIO_DRIVER_LINE7(value) (PIO_DRIVER_LINE7_Msk & ((value) << PIO_DRIVER_LINE7_Pos)) +#define PIO_DRIVER_LINE7_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (PIO_DRIVER_LINE7_LOW_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (PIO_DRIVER_LINE7_HIGH_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE8_Pos _U_(8) /**< (PIO_DRIVER) Drive of PIO Line 8 Position */ +#define PIO_DRIVER_LINE8_Msk (_U_(0x1) << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Drive of PIO Line 8 Mask */ +#define PIO_DRIVER_LINE8(value) (PIO_DRIVER_LINE8_Msk & ((value) << PIO_DRIVER_LINE8_Pos)) +#define PIO_DRIVER_LINE8_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (PIO_DRIVER_LINE8_LOW_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (PIO_DRIVER_LINE8_HIGH_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE9_Pos _U_(9) /**< (PIO_DRIVER) Drive of PIO Line 9 Position */ +#define PIO_DRIVER_LINE9_Msk (_U_(0x1) << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Drive of PIO Line 9 Mask */ +#define PIO_DRIVER_LINE9(value) (PIO_DRIVER_LINE9_Msk & ((value) << PIO_DRIVER_LINE9_Pos)) +#define PIO_DRIVER_LINE9_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (PIO_DRIVER_LINE9_LOW_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (PIO_DRIVER_LINE9_HIGH_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE10_Pos _U_(10) /**< (PIO_DRIVER) Drive of PIO Line 10 Position */ +#define PIO_DRIVER_LINE10_Msk (_U_(0x1) << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Drive of PIO Line 10 Mask */ +#define PIO_DRIVER_LINE10(value) (PIO_DRIVER_LINE10_Msk & ((value) << PIO_DRIVER_LINE10_Pos)) +#define PIO_DRIVER_LINE10_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (PIO_DRIVER_LINE10_LOW_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (PIO_DRIVER_LINE10_HIGH_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE11_Pos _U_(11) /**< (PIO_DRIVER) Drive of PIO Line 11 Position */ +#define PIO_DRIVER_LINE11_Msk (_U_(0x1) << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Drive of PIO Line 11 Mask */ +#define PIO_DRIVER_LINE11(value) (PIO_DRIVER_LINE11_Msk & ((value) << PIO_DRIVER_LINE11_Pos)) +#define PIO_DRIVER_LINE11_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (PIO_DRIVER_LINE11_LOW_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (PIO_DRIVER_LINE11_HIGH_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE12_Pos _U_(12) /**< (PIO_DRIVER) Drive of PIO Line 12 Position */ +#define PIO_DRIVER_LINE12_Msk (_U_(0x1) << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Drive of PIO Line 12 Mask */ +#define PIO_DRIVER_LINE12(value) (PIO_DRIVER_LINE12_Msk & ((value) << PIO_DRIVER_LINE12_Pos)) +#define PIO_DRIVER_LINE12_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (PIO_DRIVER_LINE12_LOW_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (PIO_DRIVER_LINE12_HIGH_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE13_Pos _U_(13) /**< (PIO_DRIVER) Drive of PIO Line 13 Position */ +#define PIO_DRIVER_LINE13_Msk (_U_(0x1) << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Drive of PIO Line 13 Mask */ +#define PIO_DRIVER_LINE13(value) (PIO_DRIVER_LINE13_Msk & ((value) << PIO_DRIVER_LINE13_Pos)) +#define PIO_DRIVER_LINE13_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (PIO_DRIVER_LINE13_LOW_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (PIO_DRIVER_LINE13_HIGH_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE14_Pos _U_(14) /**< (PIO_DRIVER) Drive of PIO Line 14 Position */ +#define PIO_DRIVER_LINE14_Msk (_U_(0x1) << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Drive of PIO Line 14 Mask */ +#define PIO_DRIVER_LINE14(value) (PIO_DRIVER_LINE14_Msk & ((value) << PIO_DRIVER_LINE14_Pos)) +#define PIO_DRIVER_LINE14_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (PIO_DRIVER_LINE14_LOW_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (PIO_DRIVER_LINE14_HIGH_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE15_Pos _U_(15) /**< (PIO_DRIVER) Drive of PIO Line 15 Position */ +#define PIO_DRIVER_LINE15_Msk (_U_(0x1) << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Drive of PIO Line 15 Mask */ +#define PIO_DRIVER_LINE15(value) (PIO_DRIVER_LINE15_Msk & ((value) << PIO_DRIVER_LINE15_Pos)) +#define PIO_DRIVER_LINE15_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (PIO_DRIVER_LINE15_LOW_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (PIO_DRIVER_LINE15_HIGH_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE16_Pos _U_(16) /**< (PIO_DRIVER) Drive of PIO Line 16 Position */ +#define PIO_DRIVER_LINE16_Msk (_U_(0x1) << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Drive of PIO Line 16 Mask */ +#define PIO_DRIVER_LINE16(value) (PIO_DRIVER_LINE16_Msk & ((value) << PIO_DRIVER_LINE16_Pos)) +#define PIO_DRIVER_LINE16_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (PIO_DRIVER_LINE16_LOW_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (PIO_DRIVER_LINE16_HIGH_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE17_Pos _U_(17) /**< (PIO_DRIVER) Drive of PIO Line 17 Position */ +#define PIO_DRIVER_LINE17_Msk (_U_(0x1) << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Drive of PIO Line 17 Mask */ +#define PIO_DRIVER_LINE17(value) (PIO_DRIVER_LINE17_Msk & ((value) << PIO_DRIVER_LINE17_Pos)) +#define PIO_DRIVER_LINE17_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (PIO_DRIVER_LINE17_LOW_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (PIO_DRIVER_LINE17_HIGH_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE18_Pos _U_(18) /**< (PIO_DRIVER) Drive of PIO Line 18 Position */ +#define PIO_DRIVER_LINE18_Msk (_U_(0x1) << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Drive of PIO Line 18 Mask */ +#define PIO_DRIVER_LINE18(value) (PIO_DRIVER_LINE18_Msk & ((value) << PIO_DRIVER_LINE18_Pos)) +#define PIO_DRIVER_LINE18_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (PIO_DRIVER_LINE18_LOW_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (PIO_DRIVER_LINE18_HIGH_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE19_Pos _U_(19) /**< (PIO_DRIVER) Drive of PIO Line 19 Position */ +#define PIO_DRIVER_LINE19_Msk (_U_(0x1) << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Drive of PIO Line 19 Mask */ +#define PIO_DRIVER_LINE19(value) (PIO_DRIVER_LINE19_Msk & ((value) << PIO_DRIVER_LINE19_Pos)) +#define PIO_DRIVER_LINE19_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (PIO_DRIVER_LINE19_LOW_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (PIO_DRIVER_LINE19_HIGH_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE20_Pos _U_(20) /**< (PIO_DRIVER) Drive of PIO Line 20 Position */ +#define PIO_DRIVER_LINE20_Msk (_U_(0x1) << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Drive of PIO Line 20 Mask */ +#define PIO_DRIVER_LINE20(value) (PIO_DRIVER_LINE20_Msk & ((value) << PIO_DRIVER_LINE20_Pos)) +#define PIO_DRIVER_LINE20_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (PIO_DRIVER_LINE20_LOW_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (PIO_DRIVER_LINE20_HIGH_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE21_Pos _U_(21) /**< (PIO_DRIVER) Drive of PIO Line 21 Position */ +#define PIO_DRIVER_LINE21_Msk (_U_(0x1) << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Drive of PIO Line 21 Mask */ +#define PIO_DRIVER_LINE21(value) (PIO_DRIVER_LINE21_Msk & ((value) << PIO_DRIVER_LINE21_Pos)) +#define PIO_DRIVER_LINE21_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (PIO_DRIVER_LINE21_LOW_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (PIO_DRIVER_LINE21_HIGH_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE22_Pos _U_(22) /**< (PIO_DRIVER) Drive of PIO Line 22 Position */ +#define PIO_DRIVER_LINE22_Msk (_U_(0x1) << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Drive of PIO Line 22 Mask */ +#define PIO_DRIVER_LINE22(value) (PIO_DRIVER_LINE22_Msk & ((value) << PIO_DRIVER_LINE22_Pos)) +#define PIO_DRIVER_LINE22_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (PIO_DRIVER_LINE22_LOW_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (PIO_DRIVER_LINE22_HIGH_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE23_Pos _U_(23) /**< (PIO_DRIVER) Drive of PIO Line 23 Position */ +#define PIO_DRIVER_LINE23_Msk (_U_(0x1) << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Drive of PIO Line 23 Mask */ +#define PIO_DRIVER_LINE23(value) (PIO_DRIVER_LINE23_Msk & ((value) << PIO_DRIVER_LINE23_Pos)) +#define PIO_DRIVER_LINE23_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (PIO_DRIVER_LINE23_LOW_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (PIO_DRIVER_LINE23_HIGH_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE24_Pos _U_(24) /**< (PIO_DRIVER) Drive of PIO Line 24 Position */ +#define PIO_DRIVER_LINE24_Msk (_U_(0x1) << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Drive of PIO Line 24 Mask */ +#define PIO_DRIVER_LINE24(value) (PIO_DRIVER_LINE24_Msk & ((value) << PIO_DRIVER_LINE24_Pos)) +#define PIO_DRIVER_LINE24_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (PIO_DRIVER_LINE24_LOW_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (PIO_DRIVER_LINE24_HIGH_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE25_Pos _U_(25) /**< (PIO_DRIVER) Drive of PIO Line 25 Position */ +#define PIO_DRIVER_LINE25_Msk (_U_(0x1) << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Drive of PIO Line 25 Mask */ +#define PIO_DRIVER_LINE25(value) (PIO_DRIVER_LINE25_Msk & ((value) << PIO_DRIVER_LINE25_Pos)) +#define PIO_DRIVER_LINE25_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (PIO_DRIVER_LINE25_LOW_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (PIO_DRIVER_LINE25_HIGH_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE26_Pos _U_(26) /**< (PIO_DRIVER) Drive of PIO Line 26 Position */ +#define PIO_DRIVER_LINE26_Msk (_U_(0x1) << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Drive of PIO Line 26 Mask */ +#define PIO_DRIVER_LINE26(value) (PIO_DRIVER_LINE26_Msk & ((value) << PIO_DRIVER_LINE26_Pos)) +#define PIO_DRIVER_LINE26_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (PIO_DRIVER_LINE26_LOW_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (PIO_DRIVER_LINE26_HIGH_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE27_Pos _U_(27) /**< (PIO_DRIVER) Drive of PIO Line 27 Position */ +#define PIO_DRIVER_LINE27_Msk (_U_(0x1) << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Drive of PIO Line 27 Mask */ +#define PIO_DRIVER_LINE27(value) (PIO_DRIVER_LINE27_Msk & ((value) << PIO_DRIVER_LINE27_Pos)) +#define PIO_DRIVER_LINE27_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (PIO_DRIVER_LINE27_LOW_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (PIO_DRIVER_LINE27_HIGH_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE28_Pos _U_(28) /**< (PIO_DRIVER) Drive of PIO Line 28 Position */ +#define PIO_DRIVER_LINE28_Msk (_U_(0x1) << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Drive of PIO Line 28 Mask */ +#define PIO_DRIVER_LINE28(value) (PIO_DRIVER_LINE28_Msk & ((value) << PIO_DRIVER_LINE28_Pos)) +#define PIO_DRIVER_LINE28_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (PIO_DRIVER_LINE28_LOW_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (PIO_DRIVER_LINE28_HIGH_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE29_Pos _U_(29) /**< (PIO_DRIVER) Drive of PIO Line 29 Position */ +#define PIO_DRIVER_LINE29_Msk (_U_(0x1) << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Drive of PIO Line 29 Mask */ +#define PIO_DRIVER_LINE29(value) (PIO_DRIVER_LINE29_Msk & ((value) << PIO_DRIVER_LINE29_Pos)) +#define PIO_DRIVER_LINE29_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (PIO_DRIVER_LINE29_LOW_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (PIO_DRIVER_LINE29_HIGH_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE30_Pos _U_(30) /**< (PIO_DRIVER) Drive of PIO Line 30 Position */ +#define PIO_DRIVER_LINE30_Msk (_U_(0x1) << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Drive of PIO Line 30 Mask */ +#define PIO_DRIVER_LINE30(value) (PIO_DRIVER_LINE30_Msk & ((value) << PIO_DRIVER_LINE30_Pos)) +#define PIO_DRIVER_LINE30_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (PIO_DRIVER_LINE30_LOW_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (PIO_DRIVER_LINE30_HIGH_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE31_Pos _U_(31) /**< (PIO_DRIVER) Drive of PIO Line 31 Position */ +#define PIO_DRIVER_LINE31_Msk (_U_(0x1) << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Drive of PIO Line 31 Mask */ +#define PIO_DRIVER_LINE31(value) (PIO_DRIVER_LINE31_Msk & ((value) << PIO_DRIVER_LINE31_Pos)) +#define PIO_DRIVER_LINE31_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (PIO_DRIVER_LINE31_LOW_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (PIO_DRIVER_LINE31_HIGH_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_Msk _U_(0xFFFFFFFF) /**< (PIO_DRIVER) Register Mask */ + +#define PIO_DRIVER_LINE_Pos _U_(0) /**< (PIO_DRIVER Position) Drive of PIO Line 3x */ +#define PIO_DRIVER_LINE_Msk (_U_(0xFFFFFFFF) << PIO_DRIVER_LINE_Pos) /**< (PIO_DRIVER Mask) LINE */ +#define PIO_DRIVER_LINE(value) (PIO_DRIVER_LINE_Msk & ((value) << PIO_DRIVER_LINE_Pos)) + +/* -------- PIO_PCMR : (PIO Offset: 0x150) (R/W 32) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN_Pos _U_(0) /**< (PIO_PCMR) Parallel Capture Mode Enable Position */ +#define PIO_PCMR_PCEN_Msk (_U_(0x1) << PIO_PCMR_PCEN_Pos) /**< (PIO_PCMR) Parallel Capture Mode Enable Mask */ +#define PIO_PCMR_PCEN(value) (PIO_PCMR_PCEN_Msk & ((value) << PIO_PCMR_PCEN_Pos)) +#define PIO_PCMR_DSIZE_Pos _U_(4) /**< (PIO_PCMR) Parallel Capture Mode Data Size Position */ +#define PIO_PCMR_DSIZE_Msk (_U_(0x3) << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) Parallel Capture Mode Data Size Mask */ +#define PIO_PCMR_DSIZE(value) (PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)) +#define PIO_PCMR_DSIZE_BYTE_Val _U_(0x0) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD_Val _U_(0x1) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD_Val _U_(0x2) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_DSIZE_BYTE (PIO_PCMR_DSIZE_BYTE_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) Position */ +#define PIO_PCMR_DSIZE_HALFWORD (PIO_PCMR_DSIZE_HALFWORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) Position */ +#define PIO_PCMR_DSIZE_WORD (PIO_PCMR_DSIZE_WORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) Position */ +#define PIO_PCMR_ALWYS_Pos _U_(9) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Position */ +#define PIO_PCMR_ALWYS_Msk (_U_(0x1) << PIO_PCMR_ALWYS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Mask */ +#define PIO_PCMR_ALWYS(value) (PIO_PCMR_ALWYS_Msk & ((value) << PIO_PCMR_ALWYS_Pos)) +#define PIO_PCMR_HALFS_Pos _U_(10) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Position */ +#define PIO_PCMR_HALFS_Msk (_U_(0x1) << PIO_PCMR_HALFS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Mask */ +#define PIO_PCMR_HALFS(value) (PIO_PCMR_HALFS_Msk & ((value) << PIO_PCMR_HALFS_Pos)) +#define PIO_PCMR_FRSTS_Pos _U_(11) /**< (PIO_PCMR) Parallel Capture Mode First Sample Position */ +#define PIO_PCMR_FRSTS_Msk (_U_(0x1) << PIO_PCMR_FRSTS_Pos) /**< (PIO_PCMR) Parallel Capture Mode First Sample Mask */ +#define PIO_PCMR_FRSTS(value) (PIO_PCMR_FRSTS_Msk & ((value) << PIO_PCMR_FRSTS_Pos)) +#define PIO_PCMR_Msk _U_(0x00000E31) /**< (PIO_PCMR) Register Mask */ + + +/* -------- PIO_PCIER : (PIO Offset: 0x154) ( /W 32) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY_Pos _U_(0) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Position */ +#define PIO_PCIER_DRDY_Msk (_U_(0x1) << PIO_PCIER_DRDY_Pos) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Mask */ +#define PIO_PCIER_DRDY(value) (PIO_PCIER_DRDY_Msk & ((value) << PIO_PCIER_DRDY_Pos)) +#define PIO_PCIER_OVRE_Pos _U_(1) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Position */ +#define PIO_PCIER_OVRE_Msk (_U_(0x1) << PIO_PCIER_OVRE_Pos) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Mask */ +#define PIO_PCIER_OVRE(value) (PIO_PCIER_OVRE_Msk & ((value) << PIO_PCIER_OVRE_Pos)) +#define PIO_PCIER_ENDRX_Pos _U_(2) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Position */ +#define PIO_PCIER_ENDRX_Msk (_U_(0x1) << PIO_PCIER_ENDRX_Pos) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Mask */ +#define PIO_PCIER_ENDRX(value) (PIO_PCIER_ENDRX_Msk & ((value) << PIO_PCIER_ENDRX_Pos)) +#define PIO_PCIER_RXBUFF_Pos _U_(3) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Position */ +#define PIO_PCIER_RXBUFF_Msk (_U_(0x1) << PIO_PCIER_RXBUFF_Pos) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Mask */ +#define PIO_PCIER_RXBUFF(value) (PIO_PCIER_RXBUFF_Msk & ((value) << PIO_PCIER_RXBUFF_Pos)) +#define PIO_PCIER_Msk _U_(0x0000000F) /**< (PIO_PCIER) Register Mask */ + + +/* -------- PIO_PCIDR : (PIO Offset: 0x158) ( /W 32) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY_Pos _U_(0) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Position */ +#define PIO_PCIDR_DRDY_Msk (_U_(0x1) << PIO_PCIDR_DRDY_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Mask */ +#define PIO_PCIDR_DRDY(value) (PIO_PCIDR_DRDY_Msk & ((value) << PIO_PCIDR_DRDY_Pos)) +#define PIO_PCIDR_OVRE_Pos _U_(1) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Position */ +#define PIO_PCIDR_OVRE_Msk (_U_(0x1) << PIO_PCIDR_OVRE_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Mask */ +#define PIO_PCIDR_OVRE(value) (PIO_PCIDR_OVRE_Msk & ((value) << PIO_PCIDR_OVRE_Pos)) +#define PIO_PCIDR_ENDRX_Pos _U_(2) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Position */ +#define PIO_PCIDR_ENDRX_Msk (_U_(0x1) << PIO_PCIDR_ENDRX_Pos) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Mask */ +#define PIO_PCIDR_ENDRX(value) (PIO_PCIDR_ENDRX_Msk & ((value) << PIO_PCIDR_ENDRX_Pos)) +#define PIO_PCIDR_RXBUFF_Pos _U_(3) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Position */ +#define PIO_PCIDR_RXBUFF_Msk (_U_(0x1) << PIO_PCIDR_RXBUFF_Pos) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Mask */ +#define PIO_PCIDR_RXBUFF(value) (PIO_PCIDR_RXBUFF_Msk & ((value) << PIO_PCIDR_RXBUFF_Pos)) +#define PIO_PCIDR_Msk _U_(0x0000000F) /**< (PIO_PCIDR) Register Mask */ + + +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) ( R/ 32) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY_Pos _U_(0) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Position */ +#define PIO_PCIMR_DRDY_Msk (_U_(0x1) << PIO_PCIMR_DRDY_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Mask */ +#define PIO_PCIMR_DRDY(value) (PIO_PCIMR_DRDY_Msk & ((value) << PIO_PCIMR_DRDY_Pos)) +#define PIO_PCIMR_OVRE_Pos _U_(1) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Position */ +#define PIO_PCIMR_OVRE_Msk (_U_(0x1) << PIO_PCIMR_OVRE_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Mask */ +#define PIO_PCIMR_OVRE(value) (PIO_PCIMR_OVRE_Msk & ((value) << PIO_PCIMR_OVRE_Pos)) +#define PIO_PCIMR_ENDRX_Pos _U_(2) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Position */ +#define PIO_PCIMR_ENDRX_Msk (_U_(0x1) << PIO_PCIMR_ENDRX_Pos) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Mask */ +#define PIO_PCIMR_ENDRX(value) (PIO_PCIMR_ENDRX_Msk & ((value) << PIO_PCIMR_ENDRX_Pos)) +#define PIO_PCIMR_RXBUFF_Pos _U_(3) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Position */ +#define PIO_PCIMR_RXBUFF_Msk (_U_(0x1) << PIO_PCIMR_RXBUFF_Pos) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Mask */ +#define PIO_PCIMR_RXBUFF(value) (PIO_PCIMR_RXBUFF_Msk & ((value) << PIO_PCIMR_RXBUFF_Pos)) +#define PIO_PCIMR_Msk _U_(0x0000000F) /**< (PIO_PCIMR) Register Mask */ + + +/* -------- PIO_PCISR : (PIO Offset: 0x160) ( R/ 32) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY_Pos _U_(0) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Position */ +#define PIO_PCISR_DRDY_Msk (_U_(0x1) << PIO_PCISR_DRDY_Pos) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Mask */ +#define PIO_PCISR_DRDY(value) (PIO_PCISR_DRDY_Msk & ((value) << PIO_PCISR_DRDY_Pos)) +#define PIO_PCISR_OVRE_Pos _U_(1) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Position */ +#define PIO_PCISR_OVRE_Msk (_U_(0x1) << PIO_PCISR_OVRE_Pos) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Mask */ +#define PIO_PCISR_OVRE(value) (PIO_PCISR_OVRE_Msk & ((value) << PIO_PCISR_OVRE_Pos)) +#define PIO_PCISR_Msk _U_(0x00000003) /**< (PIO_PCISR) Register Mask */ + + +/* -------- PIO_PCRHR : (PIO Offset: 0x164) ( R/ 32) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos _U_(0) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Position */ +#define PIO_PCRHR_RDATA_Msk (_U_(0xFFFFFFFF) << PIO_PCRHR_RDATA_Pos) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Mask */ +#define PIO_PCRHR_RDATA(value) (PIO_PCRHR_RDATA_Msk & ((value) << PIO_PCRHR_RDATA_Pos)) +#define PIO_PCRHR_Msk _U_(0xFFFFFFFF) /**< (PIO_PCRHR) Register Mask */ + + +/** \brief PIO register offsets definitions */ +#define PIO_PER_REG_OFST (0x00) /**< (PIO_PER) PIO Enable Register Offset */ +#define PIO_PDR_REG_OFST (0x04) /**< (PIO_PDR) PIO Disable Register Offset */ +#define PIO_PSR_REG_OFST (0x08) /**< (PIO_PSR) PIO Status Register Offset */ +#define PIO_OER_REG_OFST (0x10) /**< (PIO_OER) Output Enable Register Offset */ +#define PIO_ODR_REG_OFST (0x14) /**< (PIO_ODR) Output Disable Register Offset */ +#define PIO_OSR_REG_OFST (0x18) /**< (PIO_OSR) Output Status Register Offset */ +#define PIO_IFER_REG_OFST (0x20) /**< (PIO_IFER) Glitch Input Filter Enable Register Offset */ +#define PIO_IFDR_REG_OFST (0x24) /**< (PIO_IFDR) Glitch Input Filter Disable Register Offset */ +#define PIO_IFSR_REG_OFST (0x28) /**< (PIO_IFSR) Glitch Input Filter Status Register Offset */ +#define PIO_SODR_REG_OFST (0x30) /**< (PIO_SODR) Set Output Data Register Offset */ +#define PIO_CODR_REG_OFST (0x34) /**< (PIO_CODR) Clear Output Data Register Offset */ +#define PIO_ODSR_REG_OFST (0x38) /**< (PIO_ODSR) Output Data Status Register Offset */ +#define PIO_PDSR_REG_OFST (0x3C) /**< (PIO_PDSR) Pin Data Status Register Offset */ +#define PIO_IER_REG_OFST (0x40) /**< (PIO_IER) Interrupt Enable Register Offset */ +#define PIO_IDR_REG_OFST (0x44) /**< (PIO_IDR) Interrupt Disable Register Offset */ +#define PIO_IMR_REG_OFST (0x48) /**< (PIO_IMR) Interrupt Mask Register Offset */ +#define PIO_ISR_REG_OFST (0x4C) /**< (PIO_ISR) Interrupt Status Register Offset */ +#define PIO_MDER_REG_OFST (0x50) /**< (PIO_MDER) Multi-driver Enable Register Offset */ +#define PIO_MDDR_REG_OFST (0x54) /**< (PIO_MDDR) Multi-driver Disable Register Offset */ +#define PIO_MDSR_REG_OFST (0x58) /**< (PIO_MDSR) Multi-driver Status Register Offset */ +#define PIO_PUDR_REG_OFST (0x60) /**< (PIO_PUDR) Pull-up Disable Register Offset */ +#define PIO_PUER_REG_OFST (0x64) /**< (PIO_PUER) Pull-up Enable Register Offset */ +#define PIO_PUSR_REG_OFST (0x68) /**< (PIO_PUSR) Pad Pull-up Status Register Offset */ +#define PIO_ABCDSR_REG_OFST (0x70) /**< (PIO_ABCDSR) Peripheral ABCD Select Register 0 Offset */ +#define PIO_IFSCDR_REG_OFST (0x80) /**< (PIO_IFSCDR) Input Filter Slow Clock Disable Register Offset */ +#define PIO_IFSCER_REG_OFST (0x84) /**< (PIO_IFSCER) Input Filter Slow Clock Enable Register Offset */ +#define PIO_IFSCSR_REG_OFST (0x88) /**< (PIO_IFSCSR) Input Filter Slow Clock Status Register Offset */ +#define PIO_SCDR_REG_OFST (0x8C) /**< (PIO_SCDR) Slow Clock Divider Debouncing Register Offset */ +#define PIO_PPDDR_REG_OFST (0x90) /**< (PIO_PPDDR) Pad Pull-down Disable Register Offset */ +#define PIO_PPDER_REG_OFST (0x94) /**< (PIO_PPDER) Pad Pull-down Enable Register Offset */ +#define PIO_PPDSR_REG_OFST (0x98) /**< (PIO_PPDSR) Pad Pull-down Status Register Offset */ +#define PIO_OWER_REG_OFST (0xA0) /**< (PIO_OWER) Output Write Enable Offset */ +#define PIO_OWDR_REG_OFST (0xA4) /**< (PIO_OWDR) Output Write Disable Offset */ +#define PIO_OWSR_REG_OFST (0xA8) /**< (PIO_OWSR) Output Write Status Register Offset */ +#define PIO_AIMER_REG_OFST (0xB0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Register Offset */ +#define PIO_AIMDR_REG_OFST (0xB4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Register Offset */ +#define PIO_AIMMR_REG_OFST (0xB8) /**< (PIO_AIMMR) Additional Interrupt Modes Mask Register Offset */ +#define PIO_ESR_REG_OFST (0xC0) /**< (PIO_ESR) Edge Select Register Offset */ +#define PIO_LSR_REG_OFST (0xC4) /**< (PIO_LSR) Level Select Register Offset */ +#define PIO_ELSR_REG_OFST (0xC8) /**< (PIO_ELSR) Edge/Level Status Register Offset */ +#define PIO_FELLSR_REG_OFST (0xD0) /**< (PIO_FELLSR) Falling Edge/Low-Level Select Register Offset */ +#define PIO_REHLSR_REG_OFST (0xD4) /**< (PIO_REHLSR) Rising Edge/High-Level Select Register Offset */ +#define PIO_FRLHSR_REG_OFST (0xD8) /**< (PIO_FRLHSR) Fall/Rise - Low/High Status Register Offset */ +#define PIO_LOCKSR_REG_OFST (0xE0) /**< (PIO_LOCKSR) Lock Status Offset */ +#define PIO_WPMR_REG_OFST (0xE4) /**< (PIO_WPMR) Write Protection Mode Register Offset */ +#define PIO_WPSR_REG_OFST (0xE8) /**< (PIO_WPSR) Write Protection Status Register Offset */ +#define PIO_SCHMITT_REG_OFST (0x100) /**< (PIO_SCHMITT) Schmitt Trigger Register Offset */ +#define PIO_DRIVER_REG_OFST (0x118) /**< (PIO_DRIVER) I/O Drive Register Offset */ +#define PIO_PCMR_REG_OFST (0x150) /**< (PIO_PCMR) Parallel Capture Mode Register Offset */ +#define PIO_PCIER_REG_OFST (0x154) /**< (PIO_PCIER) Parallel Capture Interrupt Enable Register Offset */ +#define PIO_PCIDR_REG_OFST (0x158) /**< (PIO_PCIDR) Parallel Capture Interrupt Disable Register Offset */ +#define PIO_PCIMR_REG_OFST (0x15C) /**< (PIO_PCIMR) Parallel Capture Interrupt Mask Register Offset */ +#define PIO_PCISR_REG_OFST (0x160) /**< (PIO_PCISR) Parallel Capture Interrupt Status Register Offset */ +#define PIO_PCRHR_REG_OFST (0x164) /**< (PIO_PCRHR) Parallel Capture Reception Holding Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PIO register API structure */ +typedef struct +{ + __O uint32_t PIO_PER; /**< Offset: 0x00 ( /W 32) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< Offset: 0x04 ( /W 32) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< Offset: 0x08 (R/ 32) PIO Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t PIO_OER; /**< Offset: 0x10 ( /W 32) Output Enable Register */ + __O uint32_t PIO_ODR; /**< Offset: 0x14 ( /W 32) Output Disable Register */ + __I uint32_t PIO_OSR; /**< Offset: 0x18 (R/ 32) Output Status Register */ + __I uint8_t Reserved2[0x04]; + __O uint32_t PIO_IFER; /**< Offset: 0x20 ( /W 32) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< Offset: 0x24 ( /W 32) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< Offset: 0x28 (R/ 32) Glitch Input Filter Status Register */ + __I uint8_t Reserved3[0x04]; + __O uint32_t PIO_SODR; /**< Offset: 0x30 ( /W 32) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< Offset: 0x34 ( /W 32) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< Offset: 0x38 (R/W 32) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< Offset: 0x3C (R/ 32) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< Offset: 0x40 ( /W 32) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< Offset: 0x44 ( /W 32) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< Offset: 0x48 (R/ 32) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< Offset: 0x4C (R/ 32) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< Offset: 0x50 ( /W 32) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< Offset: 0x54 ( /W 32) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< Offset: 0x58 (R/ 32) Multi-driver Status Register */ + __I uint8_t Reserved4[0x04]; + __O uint32_t PIO_PUDR; /**< Offset: 0x60 ( /W 32) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< Offset: 0x64 ( /W 32) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< Offset: 0x68 (R/ 32) Pad Pull-up Status Register */ + __I uint8_t Reserved5[0x04]; + __IO uint32_t PIO_ABCDSR[2]; /**< Offset: 0x70 (R/W 32) Peripheral ABCD Select Register 0 */ + __I uint8_t Reserved6[0x08]; + __O uint32_t PIO_IFSCDR; /**< Offset: 0x80 ( /W 32) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< Offset: 0x84 ( /W 32) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< Offset: 0x88 (R/ 32) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< Offset: 0x8C (R/W 32) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< Offset: 0x90 ( /W 32) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< Offset: 0x94 ( /W 32) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< Offset: 0x98 (R/ 32) Pad Pull-down Status Register */ + __I uint8_t Reserved7[0x04]; + __O uint32_t PIO_OWER; /**< Offset: 0xA0 ( /W 32) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< Offset: 0xA4 ( /W 32) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< Offset: 0xA8 (R/ 32) Output Write Status Register */ + __I uint8_t Reserved8[0x04]; + __O uint32_t PIO_AIMER; /**< Offset: 0xB0 ( /W 32) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< Offset: 0xB4 ( /W 32) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< Offset: 0xB8 (R/ 32) Additional Interrupt Modes Mask Register */ + __I uint8_t Reserved9[0x04]; + __O uint32_t PIO_ESR; /**< Offset: 0xC0 ( /W 32) Edge Select Register */ + __O uint32_t PIO_LSR; /**< Offset: 0xC4 ( /W 32) Level Select Register */ + __I uint32_t PIO_ELSR; /**< Offset: 0xC8 (R/ 32) Edge/Level Status Register */ + __I uint8_t Reserved10[0x04]; + __O uint32_t PIO_FELLSR; /**< Offset: 0xD0 ( /W 32) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< Offset: 0xD4 ( /W 32) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< Offset: 0xD8 (R/ 32) Fall/Rise - Low/High Status Register */ + __I uint8_t Reserved11[0x04]; + __I uint32_t PIO_LOCKSR; /**< Offset: 0xE0 (R/ 32) Lock Status */ + __IO uint32_t PIO_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved12[0x14]; + __IO uint32_t PIO_SCHMITT; /**< Offset: 0x100 (R/W 32) Schmitt Trigger Register */ + __I uint8_t Reserved13[0x14]; + __IO uint32_t PIO_DRIVER; /**< Offset: 0x118 (R/W 32) I/O Drive Register */ + __I uint8_t Reserved14[0x34]; + __IO uint32_t PIO_PCMR; /**< Offset: 0x150 (R/W 32) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< Offset: 0x154 ( /W 32) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< Offset: 0x158 ( /W 32) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< Offset: 0x15C (R/ 32) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< Offset: 0x160 (R/ 32) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< Offset: 0x164 (R/ 32) Parallel Capture Reception Holding Register */ +} pio_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PIO_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/pmc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/pmc.h new file mode 100644 index 00000000..1b087cb2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/pmc.h @@ -0,0 +1,1983 @@ +/** + * \brief Component description for PMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_PMC_COMPONENT_H_ +#define _SAME70_PMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PMC */ +/* ************************************************************************** */ + +/* -------- PMC_SCER : (PMC Offset: 0x00) ( /W 32) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK_Pos _U_(5) /**< (PMC_SCER) Enable USB FS Clock Position */ +#define PMC_SCER_USBCLK_Msk (_U_(0x1) << PMC_SCER_USBCLK_Pos) /**< (PMC_SCER) Enable USB FS Clock Mask */ +#define PMC_SCER_USBCLK(value) (PMC_SCER_USBCLK_Msk & ((value) << PMC_SCER_USBCLK_Pos)) +#define PMC_SCER_PCK0_Pos _U_(8) /**< (PMC_SCER) Programmable Clock 0 Output Enable Position */ +#define PMC_SCER_PCK0_Msk (_U_(0x1) << PMC_SCER_PCK0_Pos) /**< (PMC_SCER) Programmable Clock 0 Output Enable Mask */ +#define PMC_SCER_PCK0(value) (PMC_SCER_PCK0_Msk & ((value) << PMC_SCER_PCK0_Pos)) +#define PMC_SCER_PCK1_Pos _U_(9) /**< (PMC_SCER) Programmable Clock 1 Output Enable Position */ +#define PMC_SCER_PCK1_Msk (_U_(0x1) << PMC_SCER_PCK1_Pos) /**< (PMC_SCER) Programmable Clock 1 Output Enable Mask */ +#define PMC_SCER_PCK1(value) (PMC_SCER_PCK1_Msk & ((value) << PMC_SCER_PCK1_Pos)) +#define PMC_SCER_PCK2_Pos _U_(10) /**< (PMC_SCER) Programmable Clock 2 Output Enable Position */ +#define PMC_SCER_PCK2_Msk (_U_(0x1) << PMC_SCER_PCK2_Pos) /**< (PMC_SCER) Programmable Clock 2 Output Enable Mask */ +#define PMC_SCER_PCK2(value) (PMC_SCER_PCK2_Msk & ((value) << PMC_SCER_PCK2_Pos)) +#define PMC_SCER_PCK3_Pos _U_(11) /**< (PMC_SCER) Programmable Clock 3 Output Enable Position */ +#define PMC_SCER_PCK3_Msk (_U_(0x1) << PMC_SCER_PCK3_Pos) /**< (PMC_SCER) Programmable Clock 3 Output Enable Mask */ +#define PMC_SCER_PCK3(value) (PMC_SCER_PCK3_Msk & ((value) << PMC_SCER_PCK3_Pos)) +#define PMC_SCER_PCK4_Pos _U_(12) /**< (PMC_SCER) Programmable Clock 4 Output Enable Position */ +#define PMC_SCER_PCK4_Msk (_U_(0x1) << PMC_SCER_PCK4_Pos) /**< (PMC_SCER) Programmable Clock 4 Output Enable Mask */ +#define PMC_SCER_PCK4(value) (PMC_SCER_PCK4_Msk & ((value) << PMC_SCER_PCK4_Pos)) +#define PMC_SCER_PCK5_Pos _U_(13) /**< (PMC_SCER) Programmable Clock 5 Output Enable Position */ +#define PMC_SCER_PCK5_Msk (_U_(0x1) << PMC_SCER_PCK5_Pos) /**< (PMC_SCER) Programmable Clock 5 Output Enable Mask */ +#define PMC_SCER_PCK5(value) (PMC_SCER_PCK5_Msk & ((value) << PMC_SCER_PCK5_Pos)) +#define PMC_SCER_PCK6_Pos _U_(14) /**< (PMC_SCER) Programmable Clock 6 Output Enable Position */ +#define PMC_SCER_PCK6_Msk (_U_(0x1) << PMC_SCER_PCK6_Pos) /**< (PMC_SCER) Programmable Clock 6 Output Enable Mask */ +#define PMC_SCER_PCK6(value) (PMC_SCER_PCK6_Msk & ((value) << PMC_SCER_PCK6_Pos)) +#define PMC_SCER_Msk _U_(0x00007F20) /**< (PMC_SCER) Register Mask */ + +#define PMC_SCER_PCK_Pos _U_(8) /**< (PMC_SCER Position) Programmable Clock 6 Output Enable */ +#define PMC_SCER_PCK_Msk (_U_(0x7F) << PMC_SCER_PCK_Pos) /**< (PMC_SCER Mask) PCK */ +#define PMC_SCER_PCK(value) (PMC_SCER_PCK_Msk & ((value) << PMC_SCER_PCK_Pos)) + +/* -------- PMC_SCDR : (PMC Offset: 0x04) ( /W 32) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK_Pos _U_(5) /**< (PMC_SCDR) Disable USB FS Clock Position */ +#define PMC_SCDR_USBCLK_Msk (_U_(0x1) << PMC_SCDR_USBCLK_Pos) /**< (PMC_SCDR) Disable USB FS Clock Mask */ +#define PMC_SCDR_USBCLK(value) (PMC_SCDR_USBCLK_Msk & ((value) << PMC_SCDR_USBCLK_Pos)) +#define PMC_SCDR_PCK0_Pos _U_(8) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Position */ +#define PMC_SCDR_PCK0_Msk (_U_(0x1) << PMC_SCDR_PCK0_Pos) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Mask */ +#define PMC_SCDR_PCK0(value) (PMC_SCDR_PCK0_Msk & ((value) << PMC_SCDR_PCK0_Pos)) +#define PMC_SCDR_PCK1_Pos _U_(9) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Position */ +#define PMC_SCDR_PCK1_Msk (_U_(0x1) << PMC_SCDR_PCK1_Pos) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Mask */ +#define PMC_SCDR_PCK1(value) (PMC_SCDR_PCK1_Msk & ((value) << PMC_SCDR_PCK1_Pos)) +#define PMC_SCDR_PCK2_Pos _U_(10) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Position */ +#define PMC_SCDR_PCK2_Msk (_U_(0x1) << PMC_SCDR_PCK2_Pos) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Mask */ +#define PMC_SCDR_PCK2(value) (PMC_SCDR_PCK2_Msk & ((value) << PMC_SCDR_PCK2_Pos)) +#define PMC_SCDR_PCK3_Pos _U_(11) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Position */ +#define PMC_SCDR_PCK3_Msk (_U_(0x1) << PMC_SCDR_PCK3_Pos) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Mask */ +#define PMC_SCDR_PCK3(value) (PMC_SCDR_PCK3_Msk & ((value) << PMC_SCDR_PCK3_Pos)) +#define PMC_SCDR_PCK4_Pos _U_(12) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Position */ +#define PMC_SCDR_PCK4_Msk (_U_(0x1) << PMC_SCDR_PCK4_Pos) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Mask */ +#define PMC_SCDR_PCK4(value) (PMC_SCDR_PCK4_Msk & ((value) << PMC_SCDR_PCK4_Pos)) +#define PMC_SCDR_PCK5_Pos _U_(13) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Position */ +#define PMC_SCDR_PCK5_Msk (_U_(0x1) << PMC_SCDR_PCK5_Pos) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Mask */ +#define PMC_SCDR_PCK5(value) (PMC_SCDR_PCK5_Msk & ((value) << PMC_SCDR_PCK5_Pos)) +#define PMC_SCDR_PCK6_Pos _U_(14) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Position */ +#define PMC_SCDR_PCK6_Msk (_U_(0x1) << PMC_SCDR_PCK6_Pos) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Mask */ +#define PMC_SCDR_PCK6(value) (PMC_SCDR_PCK6_Msk & ((value) << PMC_SCDR_PCK6_Pos)) +#define PMC_SCDR_Msk _U_(0x00007F20) /**< (PMC_SCDR) Register Mask */ + +#define PMC_SCDR_PCK_Pos _U_(8) /**< (PMC_SCDR Position) Programmable Clock 6 Output Disable */ +#define PMC_SCDR_PCK_Msk (_U_(0x7F) << PMC_SCDR_PCK_Pos) /**< (PMC_SCDR Mask) PCK */ +#define PMC_SCDR_PCK(value) (PMC_SCDR_PCK_Msk & ((value) << PMC_SCDR_PCK_Pos)) + +/* -------- PMC_SCSR : (PMC Offset: 0x08) ( R/ 32) System Clock Status Register -------- */ +#define PMC_SCSR_HCLKS_Pos _U_(0) /**< (PMC_SCSR) HCLK Status Position */ +#define PMC_SCSR_HCLKS_Msk (_U_(0x1) << PMC_SCSR_HCLKS_Pos) /**< (PMC_SCSR) HCLK Status Mask */ +#define PMC_SCSR_HCLKS(value) (PMC_SCSR_HCLKS_Msk & ((value) << PMC_SCSR_HCLKS_Pos)) +#define PMC_SCSR_USBCLK_Pos _U_(5) /**< (PMC_SCSR) USB FS Clock Status Position */ +#define PMC_SCSR_USBCLK_Msk (_U_(0x1) << PMC_SCSR_USBCLK_Pos) /**< (PMC_SCSR) USB FS Clock Status Mask */ +#define PMC_SCSR_USBCLK(value) (PMC_SCSR_USBCLK_Msk & ((value) << PMC_SCSR_USBCLK_Pos)) +#define PMC_SCSR_PCK0_Pos _U_(8) /**< (PMC_SCSR) Programmable Clock 0 Output Status Position */ +#define PMC_SCSR_PCK0_Msk (_U_(0x1) << PMC_SCSR_PCK0_Pos) /**< (PMC_SCSR) Programmable Clock 0 Output Status Mask */ +#define PMC_SCSR_PCK0(value) (PMC_SCSR_PCK0_Msk & ((value) << PMC_SCSR_PCK0_Pos)) +#define PMC_SCSR_PCK1_Pos _U_(9) /**< (PMC_SCSR) Programmable Clock 1 Output Status Position */ +#define PMC_SCSR_PCK1_Msk (_U_(0x1) << PMC_SCSR_PCK1_Pos) /**< (PMC_SCSR) Programmable Clock 1 Output Status Mask */ +#define PMC_SCSR_PCK1(value) (PMC_SCSR_PCK1_Msk & ((value) << PMC_SCSR_PCK1_Pos)) +#define PMC_SCSR_PCK2_Pos _U_(10) /**< (PMC_SCSR) Programmable Clock 2 Output Status Position */ +#define PMC_SCSR_PCK2_Msk (_U_(0x1) << PMC_SCSR_PCK2_Pos) /**< (PMC_SCSR) Programmable Clock 2 Output Status Mask */ +#define PMC_SCSR_PCK2(value) (PMC_SCSR_PCK2_Msk & ((value) << PMC_SCSR_PCK2_Pos)) +#define PMC_SCSR_PCK3_Pos _U_(11) /**< (PMC_SCSR) Programmable Clock 3 Output Status Position */ +#define PMC_SCSR_PCK3_Msk (_U_(0x1) << PMC_SCSR_PCK3_Pos) /**< (PMC_SCSR) Programmable Clock 3 Output Status Mask */ +#define PMC_SCSR_PCK3(value) (PMC_SCSR_PCK3_Msk & ((value) << PMC_SCSR_PCK3_Pos)) +#define PMC_SCSR_PCK4_Pos _U_(12) /**< (PMC_SCSR) Programmable Clock 4 Output Status Position */ +#define PMC_SCSR_PCK4_Msk (_U_(0x1) << PMC_SCSR_PCK4_Pos) /**< (PMC_SCSR) Programmable Clock 4 Output Status Mask */ +#define PMC_SCSR_PCK4(value) (PMC_SCSR_PCK4_Msk & ((value) << PMC_SCSR_PCK4_Pos)) +#define PMC_SCSR_PCK5_Pos _U_(13) /**< (PMC_SCSR) Programmable Clock 5 Output Status Position */ +#define PMC_SCSR_PCK5_Msk (_U_(0x1) << PMC_SCSR_PCK5_Pos) /**< (PMC_SCSR) Programmable Clock 5 Output Status Mask */ +#define PMC_SCSR_PCK5(value) (PMC_SCSR_PCK5_Msk & ((value) << PMC_SCSR_PCK5_Pos)) +#define PMC_SCSR_PCK6_Pos _U_(14) /**< (PMC_SCSR) Programmable Clock 6 Output Status Position */ +#define PMC_SCSR_PCK6_Msk (_U_(0x1) << PMC_SCSR_PCK6_Pos) /**< (PMC_SCSR) Programmable Clock 6 Output Status Mask */ +#define PMC_SCSR_PCK6(value) (PMC_SCSR_PCK6_Msk & ((value) << PMC_SCSR_PCK6_Pos)) +#define PMC_SCSR_Msk _U_(0x00007F21) /**< (PMC_SCSR) Register Mask */ + +#define PMC_SCSR_PCK_Pos _U_(8) /**< (PMC_SCSR Position) Programmable Clock 6 Output Status */ +#define PMC_SCSR_PCK_Msk (_U_(0x7F) << PMC_SCSR_PCK_Pos) /**< (PMC_SCSR Mask) PCK */ +#define PMC_SCSR_PCK(value) (PMC_SCSR_PCK_Msk & ((value) << PMC_SCSR_PCK_Pos)) + +/* -------- PMC_PCER0 : (PMC Offset: 0x10) ( /W 32) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7_Pos _U_(7) /**< (PMC_PCER0) Peripheral Clock 7 Enable Position */ +#define PMC_PCER0_PID7_Msk (_U_(0x1) << PMC_PCER0_PID7_Pos) /**< (PMC_PCER0) Peripheral Clock 7 Enable Mask */ +#define PMC_PCER0_PID7(value) (PMC_PCER0_PID7_Msk & ((value) << PMC_PCER0_PID7_Pos)) +#define PMC_PCER0_PID8_Pos _U_(8) /**< (PMC_PCER0) Peripheral Clock 8 Enable Position */ +#define PMC_PCER0_PID8_Msk (_U_(0x1) << PMC_PCER0_PID8_Pos) /**< (PMC_PCER0) Peripheral Clock 8 Enable Mask */ +#define PMC_PCER0_PID8(value) (PMC_PCER0_PID8_Msk & ((value) << PMC_PCER0_PID8_Pos)) +#define PMC_PCER0_PID9_Pos _U_(9) /**< (PMC_PCER0) Peripheral Clock 9 Enable Position */ +#define PMC_PCER0_PID9_Msk (_U_(0x1) << PMC_PCER0_PID9_Pos) /**< (PMC_PCER0) Peripheral Clock 9 Enable Mask */ +#define PMC_PCER0_PID9(value) (PMC_PCER0_PID9_Msk & ((value) << PMC_PCER0_PID9_Pos)) +#define PMC_PCER0_PID10_Pos _U_(10) /**< (PMC_PCER0) Peripheral Clock 10 Enable Position */ +#define PMC_PCER0_PID10_Msk (_U_(0x1) << PMC_PCER0_PID10_Pos) /**< (PMC_PCER0) Peripheral Clock 10 Enable Mask */ +#define PMC_PCER0_PID10(value) (PMC_PCER0_PID10_Msk & ((value) << PMC_PCER0_PID10_Pos)) +#define PMC_PCER0_PID11_Pos _U_(11) /**< (PMC_PCER0) Peripheral Clock 11 Enable Position */ +#define PMC_PCER0_PID11_Msk (_U_(0x1) << PMC_PCER0_PID11_Pos) /**< (PMC_PCER0) Peripheral Clock 11 Enable Mask */ +#define PMC_PCER0_PID11(value) (PMC_PCER0_PID11_Msk & ((value) << PMC_PCER0_PID11_Pos)) +#define PMC_PCER0_PID12_Pos _U_(12) /**< (PMC_PCER0) Peripheral Clock 12 Enable Position */ +#define PMC_PCER0_PID12_Msk (_U_(0x1) << PMC_PCER0_PID12_Pos) /**< (PMC_PCER0) Peripheral Clock 12 Enable Mask */ +#define PMC_PCER0_PID12(value) (PMC_PCER0_PID12_Msk & ((value) << PMC_PCER0_PID12_Pos)) +#define PMC_PCER0_PID13_Pos _U_(13) /**< (PMC_PCER0) Peripheral Clock 13 Enable Position */ +#define PMC_PCER0_PID13_Msk (_U_(0x1) << PMC_PCER0_PID13_Pos) /**< (PMC_PCER0) Peripheral Clock 13 Enable Mask */ +#define PMC_PCER0_PID13(value) (PMC_PCER0_PID13_Msk & ((value) << PMC_PCER0_PID13_Pos)) +#define PMC_PCER0_PID14_Pos _U_(14) /**< (PMC_PCER0) Peripheral Clock 14 Enable Position */ +#define PMC_PCER0_PID14_Msk (_U_(0x1) << PMC_PCER0_PID14_Pos) /**< (PMC_PCER0) Peripheral Clock 14 Enable Mask */ +#define PMC_PCER0_PID14(value) (PMC_PCER0_PID14_Msk & ((value) << PMC_PCER0_PID14_Pos)) +#define PMC_PCER0_PID15_Pos _U_(15) /**< (PMC_PCER0) Peripheral Clock 15 Enable Position */ +#define PMC_PCER0_PID15_Msk (_U_(0x1) << PMC_PCER0_PID15_Pos) /**< (PMC_PCER0) Peripheral Clock 15 Enable Mask */ +#define PMC_PCER0_PID15(value) (PMC_PCER0_PID15_Msk & ((value) << PMC_PCER0_PID15_Pos)) +#define PMC_PCER0_PID16_Pos _U_(16) /**< (PMC_PCER0) Peripheral Clock 16 Enable Position */ +#define PMC_PCER0_PID16_Msk (_U_(0x1) << PMC_PCER0_PID16_Pos) /**< (PMC_PCER0) Peripheral Clock 16 Enable Mask */ +#define PMC_PCER0_PID16(value) (PMC_PCER0_PID16_Msk & ((value) << PMC_PCER0_PID16_Pos)) +#define PMC_PCER0_PID17_Pos _U_(17) /**< (PMC_PCER0) Peripheral Clock 17 Enable Position */ +#define PMC_PCER0_PID17_Msk (_U_(0x1) << PMC_PCER0_PID17_Pos) /**< (PMC_PCER0) Peripheral Clock 17 Enable Mask */ +#define PMC_PCER0_PID17(value) (PMC_PCER0_PID17_Msk & ((value) << PMC_PCER0_PID17_Pos)) +#define PMC_PCER0_PID18_Pos _U_(18) /**< (PMC_PCER0) Peripheral Clock 18 Enable Position */ +#define PMC_PCER0_PID18_Msk (_U_(0x1) << PMC_PCER0_PID18_Pos) /**< (PMC_PCER0) Peripheral Clock 18 Enable Mask */ +#define PMC_PCER0_PID18(value) (PMC_PCER0_PID18_Msk & ((value) << PMC_PCER0_PID18_Pos)) +#define PMC_PCER0_PID19_Pos _U_(19) /**< (PMC_PCER0) Peripheral Clock 19 Enable Position */ +#define PMC_PCER0_PID19_Msk (_U_(0x1) << PMC_PCER0_PID19_Pos) /**< (PMC_PCER0) Peripheral Clock 19 Enable Mask */ +#define PMC_PCER0_PID19(value) (PMC_PCER0_PID19_Msk & ((value) << PMC_PCER0_PID19_Pos)) +#define PMC_PCER0_PID20_Pos _U_(20) /**< (PMC_PCER0) Peripheral Clock 20 Enable Position */ +#define PMC_PCER0_PID20_Msk (_U_(0x1) << PMC_PCER0_PID20_Pos) /**< (PMC_PCER0) Peripheral Clock 20 Enable Mask */ +#define PMC_PCER0_PID20(value) (PMC_PCER0_PID20_Msk & ((value) << PMC_PCER0_PID20_Pos)) +#define PMC_PCER0_PID21_Pos _U_(21) /**< (PMC_PCER0) Peripheral Clock 21 Enable Position */ +#define PMC_PCER0_PID21_Msk (_U_(0x1) << PMC_PCER0_PID21_Pos) /**< (PMC_PCER0) Peripheral Clock 21 Enable Mask */ +#define PMC_PCER0_PID21(value) (PMC_PCER0_PID21_Msk & ((value) << PMC_PCER0_PID21_Pos)) +#define PMC_PCER0_PID22_Pos _U_(22) /**< (PMC_PCER0) Peripheral Clock 22 Enable Position */ +#define PMC_PCER0_PID22_Msk (_U_(0x1) << PMC_PCER0_PID22_Pos) /**< (PMC_PCER0) Peripheral Clock 22 Enable Mask */ +#define PMC_PCER0_PID22(value) (PMC_PCER0_PID22_Msk & ((value) << PMC_PCER0_PID22_Pos)) +#define PMC_PCER0_PID23_Pos _U_(23) /**< (PMC_PCER0) Peripheral Clock 23 Enable Position */ +#define PMC_PCER0_PID23_Msk (_U_(0x1) << PMC_PCER0_PID23_Pos) /**< (PMC_PCER0) Peripheral Clock 23 Enable Mask */ +#define PMC_PCER0_PID23(value) (PMC_PCER0_PID23_Msk & ((value) << PMC_PCER0_PID23_Pos)) +#define PMC_PCER0_PID24_Pos _U_(24) /**< (PMC_PCER0) Peripheral Clock 24 Enable Position */ +#define PMC_PCER0_PID24_Msk (_U_(0x1) << PMC_PCER0_PID24_Pos) /**< (PMC_PCER0) Peripheral Clock 24 Enable Mask */ +#define PMC_PCER0_PID24(value) (PMC_PCER0_PID24_Msk & ((value) << PMC_PCER0_PID24_Pos)) +#define PMC_PCER0_PID25_Pos _U_(25) /**< (PMC_PCER0) Peripheral Clock 25 Enable Position */ +#define PMC_PCER0_PID25_Msk (_U_(0x1) << PMC_PCER0_PID25_Pos) /**< (PMC_PCER0) Peripheral Clock 25 Enable Mask */ +#define PMC_PCER0_PID25(value) (PMC_PCER0_PID25_Msk & ((value) << PMC_PCER0_PID25_Pos)) +#define PMC_PCER0_PID26_Pos _U_(26) /**< (PMC_PCER0) Peripheral Clock 26 Enable Position */ +#define PMC_PCER0_PID26_Msk (_U_(0x1) << PMC_PCER0_PID26_Pos) /**< (PMC_PCER0) Peripheral Clock 26 Enable Mask */ +#define PMC_PCER0_PID26(value) (PMC_PCER0_PID26_Msk & ((value) << PMC_PCER0_PID26_Pos)) +#define PMC_PCER0_PID27_Pos _U_(27) /**< (PMC_PCER0) Peripheral Clock 27 Enable Position */ +#define PMC_PCER0_PID27_Msk (_U_(0x1) << PMC_PCER0_PID27_Pos) /**< (PMC_PCER0) Peripheral Clock 27 Enable Mask */ +#define PMC_PCER0_PID27(value) (PMC_PCER0_PID27_Msk & ((value) << PMC_PCER0_PID27_Pos)) +#define PMC_PCER0_PID28_Pos _U_(28) /**< (PMC_PCER0) Peripheral Clock 28 Enable Position */ +#define PMC_PCER0_PID28_Msk (_U_(0x1) << PMC_PCER0_PID28_Pos) /**< (PMC_PCER0) Peripheral Clock 28 Enable Mask */ +#define PMC_PCER0_PID28(value) (PMC_PCER0_PID28_Msk & ((value) << PMC_PCER0_PID28_Pos)) +#define PMC_PCER0_PID29_Pos _U_(29) /**< (PMC_PCER0) Peripheral Clock 29 Enable Position */ +#define PMC_PCER0_PID29_Msk (_U_(0x1) << PMC_PCER0_PID29_Pos) /**< (PMC_PCER0) Peripheral Clock 29 Enable Mask */ +#define PMC_PCER0_PID29(value) (PMC_PCER0_PID29_Msk & ((value) << PMC_PCER0_PID29_Pos)) +#define PMC_PCER0_PID30_Pos _U_(30) /**< (PMC_PCER0) Peripheral Clock 30 Enable Position */ +#define PMC_PCER0_PID30_Msk (_U_(0x1) << PMC_PCER0_PID30_Pos) /**< (PMC_PCER0) Peripheral Clock 30 Enable Mask */ +#define PMC_PCER0_PID30(value) (PMC_PCER0_PID30_Msk & ((value) << PMC_PCER0_PID30_Pos)) +#define PMC_PCER0_PID31_Pos _U_(31) /**< (PMC_PCER0) Peripheral Clock 31 Enable Position */ +#define PMC_PCER0_PID31_Msk (_U_(0x1) << PMC_PCER0_PID31_Pos) /**< (PMC_PCER0) Peripheral Clock 31 Enable Mask */ +#define PMC_PCER0_PID31(value) (PMC_PCER0_PID31_Msk & ((value) << PMC_PCER0_PID31_Pos)) +#define PMC_PCER0_Msk _U_(0xFFFFFF80) /**< (PMC_PCER0) Register Mask */ + +#define PMC_PCER0_PID_Pos _U_(7) /**< (PMC_PCER0 Position) Peripheral Clock 3x Enable */ +#define PMC_PCER0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER0_PID_Pos) /**< (PMC_PCER0 Mask) PID */ +#define PMC_PCER0_PID(value) (PMC_PCER0_PID_Msk & ((value) << PMC_PCER0_PID_Pos)) + +/* -------- PMC_PCDR0 : (PMC Offset: 0x14) ( /W 32) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7_Pos _U_(7) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Position */ +#define PMC_PCDR0_PID7_Msk (_U_(0x1) << PMC_PCDR0_PID7_Pos) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Mask */ +#define PMC_PCDR0_PID7(value) (PMC_PCDR0_PID7_Msk & ((value) << PMC_PCDR0_PID7_Pos)) +#define PMC_PCDR0_PID8_Pos _U_(8) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Position */ +#define PMC_PCDR0_PID8_Msk (_U_(0x1) << PMC_PCDR0_PID8_Pos) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Mask */ +#define PMC_PCDR0_PID8(value) (PMC_PCDR0_PID8_Msk & ((value) << PMC_PCDR0_PID8_Pos)) +#define PMC_PCDR0_PID9_Pos _U_(9) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Position */ +#define PMC_PCDR0_PID9_Msk (_U_(0x1) << PMC_PCDR0_PID9_Pos) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Mask */ +#define PMC_PCDR0_PID9(value) (PMC_PCDR0_PID9_Msk & ((value) << PMC_PCDR0_PID9_Pos)) +#define PMC_PCDR0_PID10_Pos _U_(10) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Position */ +#define PMC_PCDR0_PID10_Msk (_U_(0x1) << PMC_PCDR0_PID10_Pos) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Mask */ +#define PMC_PCDR0_PID10(value) (PMC_PCDR0_PID10_Msk & ((value) << PMC_PCDR0_PID10_Pos)) +#define PMC_PCDR0_PID11_Pos _U_(11) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Position */ +#define PMC_PCDR0_PID11_Msk (_U_(0x1) << PMC_PCDR0_PID11_Pos) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Mask */ +#define PMC_PCDR0_PID11(value) (PMC_PCDR0_PID11_Msk & ((value) << PMC_PCDR0_PID11_Pos)) +#define PMC_PCDR0_PID12_Pos _U_(12) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Position */ +#define PMC_PCDR0_PID12_Msk (_U_(0x1) << PMC_PCDR0_PID12_Pos) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Mask */ +#define PMC_PCDR0_PID12(value) (PMC_PCDR0_PID12_Msk & ((value) << PMC_PCDR0_PID12_Pos)) +#define PMC_PCDR0_PID13_Pos _U_(13) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Position */ +#define PMC_PCDR0_PID13_Msk (_U_(0x1) << PMC_PCDR0_PID13_Pos) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Mask */ +#define PMC_PCDR0_PID13(value) (PMC_PCDR0_PID13_Msk & ((value) << PMC_PCDR0_PID13_Pos)) +#define PMC_PCDR0_PID14_Pos _U_(14) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Position */ +#define PMC_PCDR0_PID14_Msk (_U_(0x1) << PMC_PCDR0_PID14_Pos) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Mask */ +#define PMC_PCDR0_PID14(value) (PMC_PCDR0_PID14_Msk & ((value) << PMC_PCDR0_PID14_Pos)) +#define PMC_PCDR0_PID15_Pos _U_(15) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Position */ +#define PMC_PCDR0_PID15_Msk (_U_(0x1) << PMC_PCDR0_PID15_Pos) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Mask */ +#define PMC_PCDR0_PID15(value) (PMC_PCDR0_PID15_Msk & ((value) << PMC_PCDR0_PID15_Pos)) +#define PMC_PCDR0_PID16_Pos _U_(16) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Position */ +#define PMC_PCDR0_PID16_Msk (_U_(0x1) << PMC_PCDR0_PID16_Pos) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Mask */ +#define PMC_PCDR0_PID16(value) (PMC_PCDR0_PID16_Msk & ((value) << PMC_PCDR0_PID16_Pos)) +#define PMC_PCDR0_PID17_Pos _U_(17) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Position */ +#define PMC_PCDR0_PID17_Msk (_U_(0x1) << PMC_PCDR0_PID17_Pos) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Mask */ +#define PMC_PCDR0_PID17(value) (PMC_PCDR0_PID17_Msk & ((value) << PMC_PCDR0_PID17_Pos)) +#define PMC_PCDR0_PID18_Pos _U_(18) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Position */ +#define PMC_PCDR0_PID18_Msk (_U_(0x1) << PMC_PCDR0_PID18_Pos) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Mask */ +#define PMC_PCDR0_PID18(value) (PMC_PCDR0_PID18_Msk & ((value) << PMC_PCDR0_PID18_Pos)) +#define PMC_PCDR0_PID19_Pos _U_(19) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Position */ +#define PMC_PCDR0_PID19_Msk (_U_(0x1) << PMC_PCDR0_PID19_Pos) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Mask */ +#define PMC_PCDR0_PID19(value) (PMC_PCDR0_PID19_Msk & ((value) << PMC_PCDR0_PID19_Pos)) +#define PMC_PCDR0_PID20_Pos _U_(20) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Position */ +#define PMC_PCDR0_PID20_Msk (_U_(0x1) << PMC_PCDR0_PID20_Pos) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Mask */ +#define PMC_PCDR0_PID20(value) (PMC_PCDR0_PID20_Msk & ((value) << PMC_PCDR0_PID20_Pos)) +#define PMC_PCDR0_PID21_Pos _U_(21) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Position */ +#define PMC_PCDR0_PID21_Msk (_U_(0x1) << PMC_PCDR0_PID21_Pos) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Mask */ +#define PMC_PCDR0_PID21(value) (PMC_PCDR0_PID21_Msk & ((value) << PMC_PCDR0_PID21_Pos)) +#define PMC_PCDR0_PID22_Pos _U_(22) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Position */ +#define PMC_PCDR0_PID22_Msk (_U_(0x1) << PMC_PCDR0_PID22_Pos) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Mask */ +#define PMC_PCDR0_PID22(value) (PMC_PCDR0_PID22_Msk & ((value) << PMC_PCDR0_PID22_Pos)) +#define PMC_PCDR0_PID23_Pos _U_(23) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Position */ +#define PMC_PCDR0_PID23_Msk (_U_(0x1) << PMC_PCDR0_PID23_Pos) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Mask */ +#define PMC_PCDR0_PID23(value) (PMC_PCDR0_PID23_Msk & ((value) << PMC_PCDR0_PID23_Pos)) +#define PMC_PCDR0_PID24_Pos _U_(24) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Position */ +#define PMC_PCDR0_PID24_Msk (_U_(0x1) << PMC_PCDR0_PID24_Pos) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Mask */ +#define PMC_PCDR0_PID24(value) (PMC_PCDR0_PID24_Msk & ((value) << PMC_PCDR0_PID24_Pos)) +#define PMC_PCDR0_PID25_Pos _U_(25) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Position */ +#define PMC_PCDR0_PID25_Msk (_U_(0x1) << PMC_PCDR0_PID25_Pos) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Mask */ +#define PMC_PCDR0_PID25(value) (PMC_PCDR0_PID25_Msk & ((value) << PMC_PCDR0_PID25_Pos)) +#define PMC_PCDR0_PID26_Pos _U_(26) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Position */ +#define PMC_PCDR0_PID26_Msk (_U_(0x1) << PMC_PCDR0_PID26_Pos) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Mask */ +#define PMC_PCDR0_PID26(value) (PMC_PCDR0_PID26_Msk & ((value) << PMC_PCDR0_PID26_Pos)) +#define PMC_PCDR0_PID27_Pos _U_(27) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Position */ +#define PMC_PCDR0_PID27_Msk (_U_(0x1) << PMC_PCDR0_PID27_Pos) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Mask */ +#define PMC_PCDR0_PID27(value) (PMC_PCDR0_PID27_Msk & ((value) << PMC_PCDR0_PID27_Pos)) +#define PMC_PCDR0_PID28_Pos _U_(28) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Position */ +#define PMC_PCDR0_PID28_Msk (_U_(0x1) << PMC_PCDR0_PID28_Pos) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Mask */ +#define PMC_PCDR0_PID28(value) (PMC_PCDR0_PID28_Msk & ((value) << PMC_PCDR0_PID28_Pos)) +#define PMC_PCDR0_PID29_Pos _U_(29) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Position */ +#define PMC_PCDR0_PID29_Msk (_U_(0x1) << PMC_PCDR0_PID29_Pos) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Mask */ +#define PMC_PCDR0_PID29(value) (PMC_PCDR0_PID29_Msk & ((value) << PMC_PCDR0_PID29_Pos)) +#define PMC_PCDR0_PID30_Pos _U_(30) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Position */ +#define PMC_PCDR0_PID30_Msk (_U_(0x1) << PMC_PCDR0_PID30_Pos) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Mask */ +#define PMC_PCDR0_PID30(value) (PMC_PCDR0_PID30_Msk & ((value) << PMC_PCDR0_PID30_Pos)) +#define PMC_PCDR0_PID31_Pos _U_(31) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Position */ +#define PMC_PCDR0_PID31_Msk (_U_(0x1) << PMC_PCDR0_PID31_Pos) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Mask */ +#define PMC_PCDR0_PID31(value) (PMC_PCDR0_PID31_Msk & ((value) << PMC_PCDR0_PID31_Pos)) +#define PMC_PCDR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCDR0) Register Mask */ + +#define PMC_PCDR0_PID_Pos _U_(7) /**< (PMC_PCDR0 Position) Peripheral Clock 3x Disable */ +#define PMC_PCDR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR0_PID_Pos) /**< (PMC_PCDR0 Mask) PID */ +#define PMC_PCDR0_PID(value) (PMC_PCDR0_PID_Msk & ((value) << PMC_PCDR0_PID_Pos)) + +/* -------- PMC_PCSR0 : (PMC Offset: 0x18) ( R/ 32) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7_Pos _U_(7) /**< (PMC_PCSR0) Peripheral Clock 7 Status Position */ +#define PMC_PCSR0_PID7_Msk (_U_(0x1) << PMC_PCSR0_PID7_Pos) /**< (PMC_PCSR0) Peripheral Clock 7 Status Mask */ +#define PMC_PCSR0_PID7(value) (PMC_PCSR0_PID7_Msk & ((value) << PMC_PCSR0_PID7_Pos)) +#define PMC_PCSR0_PID8_Pos _U_(8) /**< (PMC_PCSR0) Peripheral Clock 8 Status Position */ +#define PMC_PCSR0_PID8_Msk (_U_(0x1) << PMC_PCSR0_PID8_Pos) /**< (PMC_PCSR0) Peripheral Clock 8 Status Mask */ +#define PMC_PCSR0_PID8(value) (PMC_PCSR0_PID8_Msk & ((value) << PMC_PCSR0_PID8_Pos)) +#define PMC_PCSR0_PID9_Pos _U_(9) /**< (PMC_PCSR0) Peripheral Clock 9 Status Position */ +#define PMC_PCSR0_PID9_Msk (_U_(0x1) << PMC_PCSR0_PID9_Pos) /**< (PMC_PCSR0) Peripheral Clock 9 Status Mask */ +#define PMC_PCSR0_PID9(value) (PMC_PCSR0_PID9_Msk & ((value) << PMC_PCSR0_PID9_Pos)) +#define PMC_PCSR0_PID10_Pos _U_(10) /**< (PMC_PCSR0) Peripheral Clock 10 Status Position */ +#define PMC_PCSR0_PID10_Msk (_U_(0x1) << PMC_PCSR0_PID10_Pos) /**< (PMC_PCSR0) Peripheral Clock 10 Status Mask */ +#define PMC_PCSR0_PID10(value) (PMC_PCSR0_PID10_Msk & ((value) << PMC_PCSR0_PID10_Pos)) +#define PMC_PCSR0_PID11_Pos _U_(11) /**< (PMC_PCSR0) Peripheral Clock 11 Status Position */ +#define PMC_PCSR0_PID11_Msk (_U_(0x1) << PMC_PCSR0_PID11_Pos) /**< (PMC_PCSR0) Peripheral Clock 11 Status Mask */ +#define PMC_PCSR0_PID11(value) (PMC_PCSR0_PID11_Msk & ((value) << PMC_PCSR0_PID11_Pos)) +#define PMC_PCSR0_PID12_Pos _U_(12) /**< (PMC_PCSR0) Peripheral Clock 12 Status Position */ +#define PMC_PCSR0_PID12_Msk (_U_(0x1) << PMC_PCSR0_PID12_Pos) /**< (PMC_PCSR0) Peripheral Clock 12 Status Mask */ +#define PMC_PCSR0_PID12(value) (PMC_PCSR0_PID12_Msk & ((value) << PMC_PCSR0_PID12_Pos)) +#define PMC_PCSR0_PID13_Pos _U_(13) /**< (PMC_PCSR0) Peripheral Clock 13 Status Position */ +#define PMC_PCSR0_PID13_Msk (_U_(0x1) << PMC_PCSR0_PID13_Pos) /**< (PMC_PCSR0) Peripheral Clock 13 Status Mask */ +#define PMC_PCSR0_PID13(value) (PMC_PCSR0_PID13_Msk & ((value) << PMC_PCSR0_PID13_Pos)) +#define PMC_PCSR0_PID14_Pos _U_(14) /**< (PMC_PCSR0) Peripheral Clock 14 Status Position */ +#define PMC_PCSR0_PID14_Msk (_U_(0x1) << PMC_PCSR0_PID14_Pos) /**< (PMC_PCSR0) Peripheral Clock 14 Status Mask */ +#define PMC_PCSR0_PID14(value) (PMC_PCSR0_PID14_Msk & ((value) << PMC_PCSR0_PID14_Pos)) +#define PMC_PCSR0_PID15_Pos _U_(15) /**< (PMC_PCSR0) Peripheral Clock 15 Status Position */ +#define PMC_PCSR0_PID15_Msk (_U_(0x1) << PMC_PCSR0_PID15_Pos) /**< (PMC_PCSR0) Peripheral Clock 15 Status Mask */ +#define PMC_PCSR0_PID15(value) (PMC_PCSR0_PID15_Msk & ((value) << PMC_PCSR0_PID15_Pos)) +#define PMC_PCSR0_PID16_Pos _U_(16) /**< (PMC_PCSR0) Peripheral Clock 16 Status Position */ +#define PMC_PCSR0_PID16_Msk (_U_(0x1) << PMC_PCSR0_PID16_Pos) /**< (PMC_PCSR0) Peripheral Clock 16 Status Mask */ +#define PMC_PCSR0_PID16(value) (PMC_PCSR0_PID16_Msk & ((value) << PMC_PCSR0_PID16_Pos)) +#define PMC_PCSR0_PID17_Pos _U_(17) /**< (PMC_PCSR0) Peripheral Clock 17 Status Position */ +#define PMC_PCSR0_PID17_Msk (_U_(0x1) << PMC_PCSR0_PID17_Pos) /**< (PMC_PCSR0) Peripheral Clock 17 Status Mask */ +#define PMC_PCSR0_PID17(value) (PMC_PCSR0_PID17_Msk & ((value) << PMC_PCSR0_PID17_Pos)) +#define PMC_PCSR0_PID18_Pos _U_(18) /**< (PMC_PCSR0) Peripheral Clock 18 Status Position */ +#define PMC_PCSR0_PID18_Msk (_U_(0x1) << PMC_PCSR0_PID18_Pos) /**< (PMC_PCSR0) Peripheral Clock 18 Status Mask */ +#define PMC_PCSR0_PID18(value) (PMC_PCSR0_PID18_Msk & ((value) << PMC_PCSR0_PID18_Pos)) +#define PMC_PCSR0_PID19_Pos _U_(19) /**< (PMC_PCSR0) Peripheral Clock 19 Status Position */ +#define PMC_PCSR0_PID19_Msk (_U_(0x1) << PMC_PCSR0_PID19_Pos) /**< (PMC_PCSR0) Peripheral Clock 19 Status Mask */ +#define PMC_PCSR0_PID19(value) (PMC_PCSR0_PID19_Msk & ((value) << PMC_PCSR0_PID19_Pos)) +#define PMC_PCSR0_PID20_Pos _U_(20) /**< (PMC_PCSR0) Peripheral Clock 20 Status Position */ +#define PMC_PCSR0_PID20_Msk (_U_(0x1) << PMC_PCSR0_PID20_Pos) /**< (PMC_PCSR0) Peripheral Clock 20 Status Mask */ +#define PMC_PCSR0_PID20(value) (PMC_PCSR0_PID20_Msk & ((value) << PMC_PCSR0_PID20_Pos)) +#define PMC_PCSR0_PID21_Pos _U_(21) /**< (PMC_PCSR0) Peripheral Clock 21 Status Position */ +#define PMC_PCSR0_PID21_Msk (_U_(0x1) << PMC_PCSR0_PID21_Pos) /**< (PMC_PCSR0) Peripheral Clock 21 Status Mask */ +#define PMC_PCSR0_PID21(value) (PMC_PCSR0_PID21_Msk & ((value) << PMC_PCSR0_PID21_Pos)) +#define PMC_PCSR0_PID22_Pos _U_(22) /**< (PMC_PCSR0) Peripheral Clock 22 Status Position */ +#define PMC_PCSR0_PID22_Msk (_U_(0x1) << PMC_PCSR0_PID22_Pos) /**< (PMC_PCSR0) Peripheral Clock 22 Status Mask */ +#define PMC_PCSR0_PID22(value) (PMC_PCSR0_PID22_Msk & ((value) << PMC_PCSR0_PID22_Pos)) +#define PMC_PCSR0_PID23_Pos _U_(23) /**< (PMC_PCSR0) Peripheral Clock 23 Status Position */ +#define PMC_PCSR0_PID23_Msk (_U_(0x1) << PMC_PCSR0_PID23_Pos) /**< (PMC_PCSR0) Peripheral Clock 23 Status Mask */ +#define PMC_PCSR0_PID23(value) (PMC_PCSR0_PID23_Msk & ((value) << PMC_PCSR0_PID23_Pos)) +#define PMC_PCSR0_PID24_Pos _U_(24) /**< (PMC_PCSR0) Peripheral Clock 24 Status Position */ +#define PMC_PCSR0_PID24_Msk (_U_(0x1) << PMC_PCSR0_PID24_Pos) /**< (PMC_PCSR0) Peripheral Clock 24 Status Mask */ +#define PMC_PCSR0_PID24(value) (PMC_PCSR0_PID24_Msk & ((value) << PMC_PCSR0_PID24_Pos)) +#define PMC_PCSR0_PID25_Pos _U_(25) /**< (PMC_PCSR0) Peripheral Clock 25 Status Position */ +#define PMC_PCSR0_PID25_Msk (_U_(0x1) << PMC_PCSR0_PID25_Pos) /**< (PMC_PCSR0) Peripheral Clock 25 Status Mask */ +#define PMC_PCSR0_PID25(value) (PMC_PCSR0_PID25_Msk & ((value) << PMC_PCSR0_PID25_Pos)) +#define PMC_PCSR0_PID26_Pos _U_(26) /**< (PMC_PCSR0) Peripheral Clock 26 Status Position */ +#define PMC_PCSR0_PID26_Msk (_U_(0x1) << PMC_PCSR0_PID26_Pos) /**< (PMC_PCSR0) Peripheral Clock 26 Status Mask */ +#define PMC_PCSR0_PID26(value) (PMC_PCSR0_PID26_Msk & ((value) << PMC_PCSR0_PID26_Pos)) +#define PMC_PCSR0_PID27_Pos _U_(27) /**< (PMC_PCSR0) Peripheral Clock 27 Status Position */ +#define PMC_PCSR0_PID27_Msk (_U_(0x1) << PMC_PCSR0_PID27_Pos) /**< (PMC_PCSR0) Peripheral Clock 27 Status Mask */ +#define PMC_PCSR0_PID27(value) (PMC_PCSR0_PID27_Msk & ((value) << PMC_PCSR0_PID27_Pos)) +#define PMC_PCSR0_PID28_Pos _U_(28) /**< (PMC_PCSR0) Peripheral Clock 28 Status Position */ +#define PMC_PCSR0_PID28_Msk (_U_(0x1) << PMC_PCSR0_PID28_Pos) /**< (PMC_PCSR0) Peripheral Clock 28 Status Mask */ +#define PMC_PCSR0_PID28(value) (PMC_PCSR0_PID28_Msk & ((value) << PMC_PCSR0_PID28_Pos)) +#define PMC_PCSR0_PID29_Pos _U_(29) /**< (PMC_PCSR0) Peripheral Clock 29 Status Position */ +#define PMC_PCSR0_PID29_Msk (_U_(0x1) << PMC_PCSR0_PID29_Pos) /**< (PMC_PCSR0) Peripheral Clock 29 Status Mask */ +#define PMC_PCSR0_PID29(value) (PMC_PCSR0_PID29_Msk & ((value) << PMC_PCSR0_PID29_Pos)) +#define PMC_PCSR0_PID30_Pos _U_(30) /**< (PMC_PCSR0) Peripheral Clock 30 Status Position */ +#define PMC_PCSR0_PID30_Msk (_U_(0x1) << PMC_PCSR0_PID30_Pos) /**< (PMC_PCSR0) Peripheral Clock 30 Status Mask */ +#define PMC_PCSR0_PID30(value) (PMC_PCSR0_PID30_Msk & ((value) << PMC_PCSR0_PID30_Pos)) +#define PMC_PCSR0_PID31_Pos _U_(31) /**< (PMC_PCSR0) Peripheral Clock 31 Status Position */ +#define PMC_PCSR0_PID31_Msk (_U_(0x1) << PMC_PCSR0_PID31_Pos) /**< (PMC_PCSR0) Peripheral Clock 31 Status Mask */ +#define PMC_PCSR0_PID31(value) (PMC_PCSR0_PID31_Msk & ((value) << PMC_PCSR0_PID31_Pos)) +#define PMC_PCSR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCSR0) Register Mask */ + +#define PMC_PCSR0_PID_Pos _U_(7) /**< (PMC_PCSR0 Position) Peripheral Clock 3x Status */ +#define PMC_PCSR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR0_PID_Pos) /**< (PMC_PCSR0 Mask) PID */ +#define PMC_PCSR0_PID(value) (PMC_PCSR0_PID_Msk & ((value) << PMC_PCSR0_PID_Pos)) + +/* -------- CKGR_UCKR : (PMC Offset: 0x1C) (R/W 32) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN_Pos _U_(16) /**< (CKGR_UCKR) UTMI PLL Enable Position */ +#define CKGR_UCKR_UPLLEN_Msk (_U_(0x1) << CKGR_UCKR_UPLLEN_Pos) /**< (CKGR_UCKR) UTMI PLL Enable Mask */ +#define CKGR_UCKR_UPLLEN(value) (CKGR_UCKR_UPLLEN_Msk & ((value) << CKGR_UCKR_UPLLEN_Pos)) +#define CKGR_UCKR_UPLLCOUNT_Pos _U_(20) /**< (CKGR_UCKR) UTMI PLL Start-up Time Position */ +#define CKGR_UCKR_UPLLCOUNT_Msk (_U_(0xF) << CKGR_UCKR_UPLLCOUNT_Pos) /**< (CKGR_UCKR) UTMI PLL Start-up Time Mask */ +#define CKGR_UCKR_UPLLCOUNT(value) (CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)) +#define CKGR_UCKR_Msk _U_(0x00F10000) /**< (CKGR_UCKR) Register Mask */ + + +/* -------- CKGR_MOR : (PMC Offset: 0x20) (R/W 32) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN_Pos _U_(0) /**< (CKGR_MOR) Main Crystal Oscillator Enable Position */ +#define CKGR_MOR_MOSCXTEN_Msk (_U_(0x1) << CKGR_MOR_MOSCXTEN_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Enable Mask */ +#define CKGR_MOR_MOSCXTEN(value) (CKGR_MOR_MOSCXTEN_Msk & ((value) << CKGR_MOR_MOSCXTEN_Pos)) +#define CKGR_MOR_MOSCXTBY_Pos _U_(1) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Position */ +#define CKGR_MOR_MOSCXTBY_Msk (_U_(0x1) << CKGR_MOR_MOSCXTBY_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Mask */ +#define CKGR_MOR_MOSCXTBY(value) (CKGR_MOR_MOSCXTBY_Msk & ((value) << CKGR_MOR_MOSCXTBY_Pos)) +#define CKGR_MOR_WAITMODE_Pos _U_(2) /**< (CKGR_MOR) Wait Mode Command (Write-only) Position */ +#define CKGR_MOR_WAITMODE_Msk (_U_(0x1) << CKGR_MOR_WAITMODE_Pos) /**< (CKGR_MOR) Wait Mode Command (Write-only) Mask */ +#define CKGR_MOR_WAITMODE(value) (CKGR_MOR_WAITMODE_Msk & ((value) << CKGR_MOR_WAITMODE_Pos)) +#define CKGR_MOR_MOSCRCEN_Pos _U_(3) /**< (CKGR_MOR) Main RC Oscillator Enable Position */ +#define CKGR_MOR_MOSCRCEN_Msk (_U_(0x1) << CKGR_MOR_MOSCRCEN_Pos) /**< (CKGR_MOR) Main RC Oscillator Enable Mask */ +#define CKGR_MOR_MOSCRCEN(value) (CKGR_MOR_MOSCRCEN_Msk & ((value) << CKGR_MOR_MOSCRCEN_Pos)) +#define CKGR_MOR_MOSCRCF_Pos _U_(4) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Position */ +#define CKGR_MOR_MOSCRCF_Msk (_U_(0x7) << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Mask */ +#define CKGR_MOR_MOSCRCF(value) (CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)) +#define CKGR_MOR_MOSCRCF_4_MHz_Val _U_(0x0) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz */ +#define CKGR_MOR_MOSCRCF_8_MHz_Val _U_(0x1) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz_Val _U_(0x2) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCRCF_4_MHz (CKGR_MOR_MOSCRCF_4_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz Position */ +#define CKGR_MOR_MOSCRCF_8_MHz (CKGR_MOR_MOSCRCF_8_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz Position */ +#define CKGR_MOR_MOSCRCF_12_MHz (CKGR_MOR_MOSCRCF_12_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz Position */ +#define CKGR_MOR_MOSCXTST_Pos _U_(8) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Position */ +#define CKGR_MOR_MOSCXTST_Msk (_U_(0xFF) << CKGR_MOR_MOSCXTST_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Mask */ +#define CKGR_MOR_MOSCXTST(value) (CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)) +#define CKGR_MOR_KEY_Pos _U_(16) /**< (CKGR_MOR) Write Access Password Position */ +#define CKGR_MOR_KEY_Msk (_U_(0xFF) << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Write Access Password Mask */ +#define CKGR_MOR_KEY(value) (CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)) +#define CKGR_MOR_KEY_PASSWD_Val _U_(0x37) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_KEY_PASSWD (CKGR_MOR_KEY_PASSWD_Val << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define CKGR_MOR_MOSCSEL_Pos _U_(24) /**< (CKGR_MOR) Main Clock Oscillator Selection Position */ +#define CKGR_MOR_MOSCSEL_Msk (_U_(0x1) << CKGR_MOR_MOSCSEL_Pos) /**< (CKGR_MOR) Main Clock Oscillator Selection Mask */ +#define CKGR_MOR_MOSCSEL(value) (CKGR_MOR_MOSCSEL_Msk & ((value) << CKGR_MOR_MOSCSEL_Pos)) +#define CKGR_MOR_CFDEN_Pos _U_(25) /**< (CKGR_MOR) Clock Failure Detector Enable Position */ +#define CKGR_MOR_CFDEN_Msk (_U_(0x1) << CKGR_MOR_CFDEN_Pos) /**< (CKGR_MOR) Clock Failure Detector Enable Mask */ +#define CKGR_MOR_CFDEN(value) (CKGR_MOR_CFDEN_Msk & ((value) << CKGR_MOR_CFDEN_Pos)) +#define CKGR_MOR_XT32KFME_Pos _U_(26) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Position */ +#define CKGR_MOR_XT32KFME_Msk (_U_(0x1) << CKGR_MOR_XT32KFME_Pos) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Mask */ +#define CKGR_MOR_XT32KFME(value) (CKGR_MOR_XT32KFME_Msk & ((value) << CKGR_MOR_XT32KFME_Pos)) +#define CKGR_MOR_Msk _U_(0x07FFFF7F) /**< (CKGR_MOR) Register Mask */ + + +/* -------- CKGR_MCFR : (PMC Offset: 0x24) (R/W 32) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos _U_(0) /**< (CKGR_MCFR) Main Clock Frequency Position */ +#define CKGR_MCFR_MAINF_Msk (_U_(0xFFFF) << CKGR_MCFR_MAINF_Pos) /**< (CKGR_MCFR) Main Clock Frequency Mask */ +#define CKGR_MCFR_MAINF(value) (CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)) +#define CKGR_MCFR_MAINFRDY_Pos _U_(16) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Position */ +#define CKGR_MCFR_MAINFRDY_Msk (_U_(0x1) << CKGR_MCFR_MAINFRDY_Pos) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Mask */ +#define CKGR_MCFR_MAINFRDY(value) (CKGR_MCFR_MAINFRDY_Msk & ((value) << CKGR_MCFR_MAINFRDY_Pos)) +#define CKGR_MCFR_RCMEAS_Pos _U_(20) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Position */ +#define CKGR_MCFR_RCMEAS_Msk (_U_(0x1) << CKGR_MCFR_RCMEAS_Pos) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Mask */ +#define CKGR_MCFR_RCMEAS(value) (CKGR_MCFR_RCMEAS_Msk & ((value) << CKGR_MCFR_RCMEAS_Pos)) +#define CKGR_MCFR_CCSS_Pos _U_(24) /**< (CKGR_MCFR) Counter Clock Source Selection Position */ +#define CKGR_MCFR_CCSS_Msk (_U_(0x1) << CKGR_MCFR_CCSS_Pos) /**< (CKGR_MCFR) Counter Clock Source Selection Mask */ +#define CKGR_MCFR_CCSS(value) (CKGR_MCFR_CCSS_Msk & ((value) << CKGR_MCFR_CCSS_Pos)) +#define CKGR_MCFR_Msk _U_(0x0111FFFF) /**< (CKGR_MCFR) Register Mask */ + + +/* -------- CKGR_PLLAR : (PMC Offset: 0x28) (R/W 32) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos _U_(0) /**< (CKGR_PLLAR) PLLA Front End Divider Position */ +#define CKGR_PLLAR_DIVA_Msk (_U_(0xFF) << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) PLLA Front End Divider Mask */ +#define CKGR_PLLAR_DIVA(value) (CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)) +#define CKGR_PLLAR_DIVA_0_Val _U_(0x0) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS_Val _U_(0x1) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_DIVA_0 (CKGR_PLLAR_DIVA_0_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. Position */ +#define CKGR_PLLAR_DIVA_BYPASS (CKGR_PLLAR_DIVA_BYPASS_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. Position */ +#define CKGR_PLLAR_PLLACOUNT_Pos _U_(8) /**< (CKGR_PLLAR) PLLA Counter Position */ +#define CKGR_PLLAR_PLLACOUNT_Msk (_U_(0x3F) << CKGR_PLLAR_PLLACOUNT_Pos) /**< (CKGR_PLLAR) PLLA Counter Mask */ +#define CKGR_PLLAR_PLLACOUNT(value) (CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)) +#define CKGR_PLLAR_MULA_Pos _U_(16) /**< (CKGR_PLLAR) PLLA Multiplier Position */ +#define CKGR_PLLAR_MULA_Msk (_U_(0x7FF) << CKGR_PLLAR_MULA_Pos) /**< (CKGR_PLLAR) PLLA Multiplier Mask */ +#define CKGR_PLLAR_MULA(value) (CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)) +#define CKGR_PLLAR_ONE_Pos _U_(29) /**< (CKGR_PLLAR) Must Be Set to 1 Position */ +#define CKGR_PLLAR_ONE_Msk (_U_(0x1) << CKGR_PLLAR_ONE_Pos) /**< (CKGR_PLLAR) Must Be Set to 1 Mask */ +#define CKGR_PLLAR_ONE(value) (CKGR_PLLAR_ONE_Msk & ((value) << CKGR_PLLAR_ONE_Pos)) +#define CKGR_PLLAR_Msk _U_(0x27FF3FFF) /**< (CKGR_PLLAR) Register Mask */ + + +/* -------- PMC_MCKR : (PMC Offset: 0x30) (R/W 32) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos _U_(0) /**< (PMC_MCKR) Master Clock Source Selection Position */ +#define PMC_MCKR_CSS_Msk (_U_(0x3) << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Master Clock Source Selection Mask */ +#define PMC_MCKR_CSS(value) (PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)) +#define PMC_MCKR_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_CSS_SLOW_CLK (PMC_MCKR_CSS_SLOW_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Slow Clock is selected Position */ +#define PMC_MCKR_CSS_MAIN_CLK (PMC_MCKR_CSS_MAIN_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Main Clock is selected Position */ +#define PMC_MCKR_CSS_PLLA_CLK (PMC_MCKR_CSS_PLLA_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) PLLA Clock is selected Position */ +#define PMC_MCKR_CSS_UPLL_CLK (PMC_MCKR_CSS_UPLL_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Divided UPLL Clock is selected Position */ +#define PMC_MCKR_PRES_Pos _U_(4) /**< (PMC_MCKR) Processor Clock Prescaler Position */ +#define PMC_MCKR_PRES_Msk (_U_(0x7) << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Processor Clock Prescaler Mask */ +#define PMC_MCKR_PRES(value) (PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)) +#define PMC_MCKR_PRES_CLK_1_Val _U_(0x0) /**< (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2_Val _U_(0x1) /**< (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4_Val _U_(0x2) /**< (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8_Val _U_(0x3) /**< (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16_Val _U_(0x4) /**< (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32_Val _U_(0x5) /**< (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64_Val _U_(0x6) /**< (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3_Val _U_(0x7) /**< (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PRES_CLK_1 (PMC_MCKR_PRES_CLK_1_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock Position */ +#define PMC_MCKR_PRES_CLK_2 (PMC_MCKR_PRES_CLK_2_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 2 Position */ +#define PMC_MCKR_PRES_CLK_4 (PMC_MCKR_PRES_CLK_4_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 4 Position */ +#define PMC_MCKR_PRES_CLK_8 (PMC_MCKR_PRES_CLK_8_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 8 Position */ +#define PMC_MCKR_PRES_CLK_16 (PMC_MCKR_PRES_CLK_16_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 16 Position */ +#define PMC_MCKR_PRES_CLK_32 (PMC_MCKR_PRES_CLK_32_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 32 Position */ +#define PMC_MCKR_PRES_CLK_64 (PMC_MCKR_PRES_CLK_64_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 64 Position */ +#define PMC_MCKR_PRES_CLK_3 (PMC_MCKR_PRES_CLK_3_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 3 Position */ +#define PMC_MCKR_MDIV_Pos _U_(8) /**< (PMC_MCKR) Master Clock Division Position */ +#define PMC_MCKR_MDIV_Msk (_U_(0x3) << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock Division Mask */ +#define PMC_MCKR_MDIV(value) (PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)) +#define PMC_MCKR_MDIV_EQ_PCK_Val _U_(0x0) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2_Val _U_(0x1) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4_Val _U_(0x2) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3_Val _U_(0x3) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_MDIV_EQ_PCK (PMC_MCKR_MDIV_EQ_PCK_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. Position */ +#define PMC_MCKR_MDIV_PCK_DIV2 (PMC_MCKR_MDIV_PCK_DIV2_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. Position */ +#define PMC_MCKR_MDIV_PCK_DIV4 (PMC_MCKR_MDIV_PCK_DIV4_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. Position */ +#define PMC_MCKR_MDIV_PCK_DIV3 (PMC_MCKR_MDIV_PCK_DIV3_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. Position */ +#define PMC_MCKR_UPLLDIV2_Pos _U_(13) /**< (PMC_MCKR) UPLL Divider by 2 Position */ +#define PMC_MCKR_UPLLDIV2_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV2_Pos) /**< (PMC_MCKR) UPLL Divider by 2 Mask */ +#define PMC_MCKR_UPLLDIV2(value) (PMC_MCKR_UPLLDIV2_Msk & ((value) << PMC_MCKR_UPLLDIV2_Pos)) +#define PMC_MCKR_Msk _U_(0x00002373) /**< (PMC_MCKR) Register Mask */ + +#define PMC_MCKR_UPLLDIV_Pos _U_(13) /**< (PMC_MCKR Position) UPLL Divider by 2 */ +#define PMC_MCKR_UPLLDIV_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV_Pos) /**< (PMC_MCKR Mask) UPLLDIV */ +#define PMC_MCKR_UPLLDIV(value) (PMC_MCKR_UPLLDIV_Msk & ((value) << PMC_MCKR_UPLLDIV_Pos)) + +/* -------- PMC_USB : (PMC Offset: 0x38) (R/W 32) USB Clock Register -------- */ +#define PMC_USB_USBS_Pos _U_(0) /**< (PMC_USB) USB Input Clock Selection Position */ +#define PMC_USB_USBS_Msk (_U_(0x1) << PMC_USB_USBS_Pos) /**< (PMC_USB) USB Input Clock Selection Mask */ +#define PMC_USB_USBS(value) (PMC_USB_USBS_Msk & ((value) << PMC_USB_USBS_Pos)) +#define PMC_USB_USBDIV_Pos _U_(8) /**< (PMC_USB) Divider for USB_48M Position */ +#define PMC_USB_USBDIV_Msk (_U_(0xF) << PMC_USB_USBDIV_Pos) /**< (PMC_USB) Divider for USB_48M Mask */ +#define PMC_USB_USBDIV(value) (PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)) +#define PMC_USB_Msk _U_(0x00000F01) /**< (PMC_USB) Register Mask */ + + +/* -------- PMC_PCK : (PMC Offset: 0x40) (R/W 32) Programmable Clock Register -------- */ +#define PMC_PCK_CSS_Pos _U_(0) /**< (PMC_PCK) Programmable Clock Source Selection Position */ +#define PMC_PCK_CSS_Msk (_U_(0x7) << PMC_PCK_CSS_Pos) /**< (PMC_PCK) Programmable Clock Source Selection Mask */ +#define PMC_PCK_CSS(value) (PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)) +#define PMC_PCK_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCK) SLCK is selected */ +#define PMC_PCK_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCK) MAINCK is selected */ +#define PMC_PCK_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCK) PLLACK is selected */ +#define PMC_PCK_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCK) UPLLCKDIV is selected */ +#define PMC_PCK_CSS_MCK_Val _U_(0x4) /**< (PMC_PCK) MCK is selected */ +#define PMC_PCK_CSS_SLOW_CLK (PMC_PCK_CSS_SLOW_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) SLCK is selected Position */ +#define PMC_PCK_CSS_MAIN_CLK (PMC_PCK_CSS_MAIN_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MAINCK is selected Position */ +#define PMC_PCK_CSS_PLLA_CLK (PMC_PCK_CSS_PLLA_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) PLLACK is selected Position */ +#define PMC_PCK_CSS_UPLL_CLK (PMC_PCK_CSS_UPLL_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) UPLLCKDIV is selected Position */ +#define PMC_PCK_CSS_MCK (PMC_PCK_CSS_MCK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MCK is selected Position */ +#define PMC_PCK_PRES_Pos _U_(4) /**< (PMC_PCK) Programmable Clock Prescaler Position */ +#define PMC_PCK_PRES_Msk (_U_(0xFF) << PMC_PCK_PRES_Pos) /**< (PMC_PCK) Programmable Clock Prescaler Mask */ +#define PMC_PCK_PRES(value) (PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)) +#define PMC_PCK_Msk _U_(0x00000FF7) /**< (PMC_PCK) Register Mask */ + + +/* -------- PMC_IER : (PMC Offset: 0x60) ( /W 32) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS_Pos _U_(0) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCXTS_Msk (_U_(0x1) << PMC_IER_MOSCXTS_Pos) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCXTS(value) (PMC_IER_MOSCXTS_Msk & ((value) << PMC_IER_MOSCXTS_Pos)) +#define PMC_IER_LOCKA_Pos _U_(1) /**< (PMC_IER) PLLA Lock Interrupt Enable Position */ +#define PMC_IER_LOCKA_Msk (_U_(0x1) << PMC_IER_LOCKA_Pos) /**< (PMC_IER) PLLA Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKA(value) (PMC_IER_LOCKA_Msk & ((value) << PMC_IER_LOCKA_Pos)) +#define PMC_IER_MCKRDY_Pos _U_(3) /**< (PMC_IER) Master Clock Ready Interrupt Enable Position */ +#define PMC_IER_MCKRDY_Msk (_U_(0x1) << PMC_IER_MCKRDY_Pos) /**< (PMC_IER) Master Clock Ready Interrupt Enable Mask */ +#define PMC_IER_MCKRDY(value) (PMC_IER_MCKRDY_Msk & ((value) << PMC_IER_MCKRDY_Pos)) +#define PMC_IER_LOCKU_Pos _U_(6) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Position */ +#define PMC_IER_LOCKU_Msk (_U_(0x1) << PMC_IER_LOCKU_Pos) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKU(value) (PMC_IER_LOCKU_Msk & ((value) << PMC_IER_LOCKU_Pos)) +#define PMC_IER_PCKRDY0_Pos _U_(8) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Position */ +#define PMC_IER_PCKRDY0_Msk (_U_(0x1) << PMC_IER_PCKRDY0_Pos) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY0(value) (PMC_IER_PCKRDY0_Msk & ((value) << PMC_IER_PCKRDY0_Pos)) +#define PMC_IER_PCKRDY1_Pos _U_(9) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Position */ +#define PMC_IER_PCKRDY1_Msk (_U_(0x1) << PMC_IER_PCKRDY1_Pos) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY1(value) (PMC_IER_PCKRDY1_Msk & ((value) << PMC_IER_PCKRDY1_Pos)) +#define PMC_IER_PCKRDY2_Pos _U_(10) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Position */ +#define PMC_IER_PCKRDY2_Msk (_U_(0x1) << PMC_IER_PCKRDY2_Pos) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY2(value) (PMC_IER_PCKRDY2_Msk & ((value) << PMC_IER_PCKRDY2_Pos)) +#define PMC_IER_PCKRDY3_Pos _U_(11) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Position */ +#define PMC_IER_PCKRDY3_Msk (_U_(0x1) << PMC_IER_PCKRDY3_Pos) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY3(value) (PMC_IER_PCKRDY3_Msk & ((value) << PMC_IER_PCKRDY3_Pos)) +#define PMC_IER_PCKRDY4_Pos _U_(12) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Position */ +#define PMC_IER_PCKRDY4_Msk (_U_(0x1) << PMC_IER_PCKRDY4_Pos) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY4(value) (PMC_IER_PCKRDY4_Msk & ((value) << PMC_IER_PCKRDY4_Pos)) +#define PMC_IER_PCKRDY5_Pos _U_(13) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Position */ +#define PMC_IER_PCKRDY5_Msk (_U_(0x1) << PMC_IER_PCKRDY5_Pos) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY5(value) (PMC_IER_PCKRDY5_Msk & ((value) << PMC_IER_PCKRDY5_Pos)) +#define PMC_IER_PCKRDY6_Pos _U_(14) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Position */ +#define PMC_IER_PCKRDY6_Msk (_U_(0x1) << PMC_IER_PCKRDY6_Pos) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY6(value) (PMC_IER_PCKRDY6_Msk & ((value) << PMC_IER_PCKRDY6_Pos)) +#define PMC_IER_MOSCSELS_Pos _U_(16) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Position */ +#define PMC_IER_MOSCSELS_Msk (_U_(0x1) << PMC_IER_MOSCSELS_Pos) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Mask */ +#define PMC_IER_MOSCSELS(value) (PMC_IER_MOSCSELS_Msk & ((value) << PMC_IER_MOSCSELS_Pos)) +#define PMC_IER_MOSCRCS_Pos _U_(17) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCRCS_Msk (_U_(0x1) << PMC_IER_MOSCRCS_Pos) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCRCS(value) (PMC_IER_MOSCRCS_Msk & ((value) << PMC_IER_MOSCRCS_Pos)) +#define PMC_IER_CFDEV_Pos _U_(18) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Position */ +#define PMC_IER_CFDEV_Msk (_U_(0x1) << PMC_IER_CFDEV_Pos) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Mask */ +#define PMC_IER_CFDEV(value) (PMC_IER_CFDEV_Msk & ((value) << PMC_IER_CFDEV_Pos)) +#define PMC_IER_XT32KERR_Pos _U_(21) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Position */ +#define PMC_IER_XT32KERR_Msk (_U_(0x1) << PMC_IER_XT32KERR_Pos) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Mask */ +#define PMC_IER_XT32KERR(value) (PMC_IER_XT32KERR_Msk & ((value) << PMC_IER_XT32KERR_Pos)) +#define PMC_IER_Msk _U_(0x00277F4B) /**< (PMC_IER) Register Mask */ + +#define PMC_IER_PCKRDY_Pos _U_(8) /**< (PMC_IER Position) Programmable Clock Ready x Interrupt Enable */ +#define PMC_IER_PCKRDY_Msk (_U_(0x7F) << PMC_IER_PCKRDY_Pos) /**< (PMC_IER Mask) PCKRDY */ +#define PMC_IER_PCKRDY(value) (PMC_IER_PCKRDY_Msk & ((value) << PMC_IER_PCKRDY_Pos)) + +/* -------- PMC_IDR : (PMC Offset: 0x64) ( /W 32) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS_Pos _U_(0) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Position */ +#define PMC_IDR_MOSCXTS_Msk (_U_(0x1) << PMC_IDR_MOSCXTS_Pos) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCXTS(value) (PMC_IDR_MOSCXTS_Msk & ((value) << PMC_IDR_MOSCXTS_Pos)) +#define PMC_IDR_LOCKA_Pos _U_(1) /**< (PMC_IDR) PLLA Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKA_Msk (_U_(0x1) << PMC_IDR_LOCKA_Pos) /**< (PMC_IDR) PLLA Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKA(value) (PMC_IDR_LOCKA_Msk & ((value) << PMC_IDR_LOCKA_Pos)) +#define PMC_IDR_MCKRDY_Pos _U_(3) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Position */ +#define PMC_IDR_MCKRDY_Msk (_U_(0x1) << PMC_IDR_MCKRDY_Pos) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Mask */ +#define PMC_IDR_MCKRDY(value) (PMC_IDR_MCKRDY_Msk & ((value) << PMC_IDR_MCKRDY_Pos)) +#define PMC_IDR_LOCKU_Pos _U_(6) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKU_Msk (_U_(0x1) << PMC_IDR_LOCKU_Pos) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKU(value) (PMC_IDR_LOCKU_Msk & ((value) << PMC_IDR_LOCKU_Pos)) +#define PMC_IDR_PCKRDY0_Pos _U_(8) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY0_Msk (_U_(0x1) << PMC_IDR_PCKRDY0_Pos) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY0(value) (PMC_IDR_PCKRDY0_Msk & ((value) << PMC_IDR_PCKRDY0_Pos)) +#define PMC_IDR_PCKRDY1_Pos _U_(9) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY1_Msk (_U_(0x1) << PMC_IDR_PCKRDY1_Pos) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY1(value) (PMC_IDR_PCKRDY1_Msk & ((value) << PMC_IDR_PCKRDY1_Pos)) +#define PMC_IDR_PCKRDY2_Pos _U_(10) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY2_Msk (_U_(0x1) << PMC_IDR_PCKRDY2_Pos) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY2(value) (PMC_IDR_PCKRDY2_Msk & ((value) << PMC_IDR_PCKRDY2_Pos)) +#define PMC_IDR_PCKRDY3_Pos _U_(11) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY3_Msk (_U_(0x1) << PMC_IDR_PCKRDY3_Pos) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY3(value) (PMC_IDR_PCKRDY3_Msk & ((value) << PMC_IDR_PCKRDY3_Pos)) +#define PMC_IDR_PCKRDY4_Pos _U_(12) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY4_Msk (_U_(0x1) << PMC_IDR_PCKRDY4_Pos) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY4(value) (PMC_IDR_PCKRDY4_Msk & ((value) << PMC_IDR_PCKRDY4_Pos)) +#define PMC_IDR_PCKRDY5_Pos _U_(13) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY5_Msk (_U_(0x1) << PMC_IDR_PCKRDY5_Pos) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY5(value) (PMC_IDR_PCKRDY5_Msk & ((value) << PMC_IDR_PCKRDY5_Pos)) +#define PMC_IDR_PCKRDY6_Pos _U_(14) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY6_Msk (_U_(0x1) << PMC_IDR_PCKRDY6_Pos) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY6(value) (PMC_IDR_PCKRDY6_Msk & ((value) << PMC_IDR_PCKRDY6_Pos)) +#define PMC_IDR_MOSCSELS_Pos _U_(16) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Position */ +#define PMC_IDR_MOSCSELS_Msk (_U_(0x1) << PMC_IDR_MOSCSELS_Pos) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCSELS(value) (PMC_IDR_MOSCSELS_Msk & ((value) << PMC_IDR_MOSCSELS_Pos)) +#define PMC_IDR_MOSCRCS_Pos _U_(17) /**< (PMC_IDR) Main RC Status Interrupt Disable Position */ +#define PMC_IDR_MOSCRCS_Msk (_U_(0x1) << PMC_IDR_MOSCRCS_Pos) /**< (PMC_IDR) Main RC Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCRCS(value) (PMC_IDR_MOSCRCS_Msk & ((value) << PMC_IDR_MOSCRCS_Pos)) +#define PMC_IDR_CFDEV_Pos _U_(18) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Position */ +#define PMC_IDR_CFDEV_Msk (_U_(0x1) << PMC_IDR_CFDEV_Pos) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Mask */ +#define PMC_IDR_CFDEV(value) (PMC_IDR_CFDEV_Msk & ((value) << PMC_IDR_CFDEV_Pos)) +#define PMC_IDR_XT32KERR_Pos _U_(21) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Position */ +#define PMC_IDR_XT32KERR_Msk (_U_(0x1) << PMC_IDR_XT32KERR_Pos) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Mask */ +#define PMC_IDR_XT32KERR(value) (PMC_IDR_XT32KERR_Msk & ((value) << PMC_IDR_XT32KERR_Pos)) +#define PMC_IDR_Msk _U_(0x00277F4B) /**< (PMC_IDR) Register Mask */ + +#define PMC_IDR_PCKRDY_Pos _U_(8) /**< (PMC_IDR Position) Programmable Clock Ready x Interrupt Disable */ +#define PMC_IDR_PCKRDY_Msk (_U_(0x7F) << PMC_IDR_PCKRDY_Pos) /**< (PMC_IDR Mask) PCKRDY */ +#define PMC_IDR_PCKRDY(value) (PMC_IDR_PCKRDY_Msk & ((value) << PMC_IDR_PCKRDY_Pos)) + +/* -------- PMC_SR : (PMC Offset: 0x68) ( R/ 32) Status Register -------- */ +#define PMC_SR_MOSCXTS_Pos _U_(0) /**< (PMC_SR) Main Crystal Oscillator Status Position */ +#define PMC_SR_MOSCXTS_Msk (_U_(0x1) << PMC_SR_MOSCXTS_Pos) /**< (PMC_SR) Main Crystal Oscillator Status Mask */ +#define PMC_SR_MOSCXTS(value) (PMC_SR_MOSCXTS_Msk & ((value) << PMC_SR_MOSCXTS_Pos)) +#define PMC_SR_LOCKA_Pos _U_(1) /**< (PMC_SR) PLLA Lock Status Position */ +#define PMC_SR_LOCKA_Msk (_U_(0x1) << PMC_SR_LOCKA_Pos) /**< (PMC_SR) PLLA Lock Status Mask */ +#define PMC_SR_LOCKA(value) (PMC_SR_LOCKA_Msk & ((value) << PMC_SR_LOCKA_Pos)) +#define PMC_SR_MCKRDY_Pos _U_(3) /**< (PMC_SR) Master Clock Status Position */ +#define PMC_SR_MCKRDY_Msk (_U_(0x1) << PMC_SR_MCKRDY_Pos) /**< (PMC_SR) Master Clock Status Mask */ +#define PMC_SR_MCKRDY(value) (PMC_SR_MCKRDY_Msk & ((value) << PMC_SR_MCKRDY_Pos)) +#define PMC_SR_LOCKU_Pos _U_(6) /**< (PMC_SR) UTMI PLL Lock Status Position */ +#define PMC_SR_LOCKU_Msk (_U_(0x1) << PMC_SR_LOCKU_Pos) /**< (PMC_SR) UTMI PLL Lock Status Mask */ +#define PMC_SR_LOCKU(value) (PMC_SR_LOCKU_Msk & ((value) << PMC_SR_LOCKU_Pos)) +#define PMC_SR_OSCSELS_Pos _U_(7) /**< (PMC_SR) Slow Clock Source Oscillator Selection Position */ +#define PMC_SR_OSCSELS_Msk (_U_(0x1) << PMC_SR_OSCSELS_Pos) /**< (PMC_SR) Slow Clock Source Oscillator Selection Mask */ +#define PMC_SR_OSCSELS(value) (PMC_SR_OSCSELS_Msk & ((value) << PMC_SR_OSCSELS_Pos)) +#define PMC_SR_PCKRDY0_Pos _U_(8) /**< (PMC_SR) Programmable Clock Ready 0 Status Position */ +#define PMC_SR_PCKRDY0_Msk (_U_(0x1) << PMC_SR_PCKRDY0_Pos) /**< (PMC_SR) Programmable Clock Ready 0 Status Mask */ +#define PMC_SR_PCKRDY0(value) (PMC_SR_PCKRDY0_Msk & ((value) << PMC_SR_PCKRDY0_Pos)) +#define PMC_SR_PCKRDY1_Pos _U_(9) /**< (PMC_SR) Programmable Clock Ready 1 Status Position */ +#define PMC_SR_PCKRDY1_Msk (_U_(0x1) << PMC_SR_PCKRDY1_Pos) /**< (PMC_SR) Programmable Clock Ready 1 Status Mask */ +#define PMC_SR_PCKRDY1(value) (PMC_SR_PCKRDY1_Msk & ((value) << PMC_SR_PCKRDY1_Pos)) +#define PMC_SR_PCKRDY2_Pos _U_(10) /**< (PMC_SR) Programmable Clock Ready 2 Status Position */ +#define PMC_SR_PCKRDY2_Msk (_U_(0x1) << PMC_SR_PCKRDY2_Pos) /**< (PMC_SR) Programmable Clock Ready 2 Status Mask */ +#define PMC_SR_PCKRDY2(value) (PMC_SR_PCKRDY2_Msk & ((value) << PMC_SR_PCKRDY2_Pos)) +#define PMC_SR_PCKRDY3_Pos _U_(11) /**< (PMC_SR) Programmable Clock Ready 3 Status Position */ +#define PMC_SR_PCKRDY3_Msk (_U_(0x1) << PMC_SR_PCKRDY3_Pos) /**< (PMC_SR) Programmable Clock Ready 3 Status Mask */ +#define PMC_SR_PCKRDY3(value) (PMC_SR_PCKRDY3_Msk & ((value) << PMC_SR_PCKRDY3_Pos)) +#define PMC_SR_PCKRDY4_Pos _U_(12) /**< (PMC_SR) Programmable Clock Ready 4 Status Position */ +#define PMC_SR_PCKRDY4_Msk (_U_(0x1) << PMC_SR_PCKRDY4_Pos) /**< (PMC_SR) Programmable Clock Ready 4 Status Mask */ +#define PMC_SR_PCKRDY4(value) (PMC_SR_PCKRDY4_Msk & ((value) << PMC_SR_PCKRDY4_Pos)) +#define PMC_SR_PCKRDY5_Pos _U_(13) /**< (PMC_SR) Programmable Clock Ready 5 Status Position */ +#define PMC_SR_PCKRDY5_Msk (_U_(0x1) << PMC_SR_PCKRDY5_Pos) /**< (PMC_SR) Programmable Clock Ready 5 Status Mask */ +#define PMC_SR_PCKRDY5(value) (PMC_SR_PCKRDY5_Msk & ((value) << PMC_SR_PCKRDY5_Pos)) +#define PMC_SR_PCKRDY6_Pos _U_(14) /**< (PMC_SR) Programmable Clock Ready 6 Status Position */ +#define PMC_SR_PCKRDY6_Msk (_U_(0x1) << PMC_SR_PCKRDY6_Pos) /**< (PMC_SR) Programmable Clock Ready 6 Status Mask */ +#define PMC_SR_PCKRDY6(value) (PMC_SR_PCKRDY6_Msk & ((value) << PMC_SR_PCKRDY6_Pos)) +#define PMC_SR_MOSCSELS_Pos _U_(16) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Position */ +#define PMC_SR_MOSCSELS_Msk (_U_(0x1) << PMC_SR_MOSCSELS_Pos) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Mask */ +#define PMC_SR_MOSCSELS(value) (PMC_SR_MOSCSELS_Msk & ((value) << PMC_SR_MOSCSELS_Pos)) +#define PMC_SR_MOSCRCS_Pos _U_(17) /**< (PMC_SR) Main RC Oscillator Status Position */ +#define PMC_SR_MOSCRCS_Msk (_U_(0x1) << PMC_SR_MOSCRCS_Pos) /**< (PMC_SR) Main RC Oscillator Status Mask */ +#define PMC_SR_MOSCRCS(value) (PMC_SR_MOSCRCS_Msk & ((value) << PMC_SR_MOSCRCS_Pos)) +#define PMC_SR_CFDEV_Pos _U_(18) /**< (PMC_SR) Clock Failure Detector Event Position */ +#define PMC_SR_CFDEV_Msk (_U_(0x1) << PMC_SR_CFDEV_Pos) /**< (PMC_SR) Clock Failure Detector Event Mask */ +#define PMC_SR_CFDEV(value) (PMC_SR_CFDEV_Msk & ((value) << PMC_SR_CFDEV_Pos)) +#define PMC_SR_CFDS_Pos _U_(19) /**< (PMC_SR) Clock Failure Detector Status Position */ +#define PMC_SR_CFDS_Msk (_U_(0x1) << PMC_SR_CFDS_Pos) /**< (PMC_SR) Clock Failure Detector Status Mask */ +#define PMC_SR_CFDS(value) (PMC_SR_CFDS_Msk & ((value) << PMC_SR_CFDS_Pos)) +#define PMC_SR_FOS_Pos _U_(20) /**< (PMC_SR) Clock Failure Detector Fault Output Status Position */ +#define PMC_SR_FOS_Msk (_U_(0x1) << PMC_SR_FOS_Pos) /**< (PMC_SR) Clock Failure Detector Fault Output Status Mask */ +#define PMC_SR_FOS(value) (PMC_SR_FOS_Msk & ((value) << PMC_SR_FOS_Pos)) +#define PMC_SR_XT32KERR_Pos _U_(21) /**< (PMC_SR) Slow Crystal Oscillator Error Position */ +#define PMC_SR_XT32KERR_Msk (_U_(0x1) << PMC_SR_XT32KERR_Pos) /**< (PMC_SR) Slow Crystal Oscillator Error Mask */ +#define PMC_SR_XT32KERR(value) (PMC_SR_XT32KERR_Msk & ((value) << PMC_SR_XT32KERR_Pos)) +#define PMC_SR_Msk _U_(0x003F7FCB) /**< (PMC_SR) Register Mask */ + +#define PMC_SR_PCKRDY_Pos _U_(8) /**< (PMC_SR Position) Programmable Clock Ready x Status */ +#define PMC_SR_PCKRDY_Msk (_U_(0x7F) << PMC_SR_PCKRDY_Pos) /**< (PMC_SR Mask) PCKRDY */ +#define PMC_SR_PCKRDY(value) (PMC_SR_PCKRDY_Msk & ((value) << PMC_SR_PCKRDY_Pos)) + +/* -------- PMC_IMR : (PMC Offset: 0x6C) ( R/ 32) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS_Pos _U_(0) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Position */ +#define PMC_IMR_MOSCXTS_Msk (_U_(0x1) << PMC_IMR_MOSCXTS_Pos) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCXTS(value) (PMC_IMR_MOSCXTS_Msk & ((value) << PMC_IMR_MOSCXTS_Pos)) +#define PMC_IMR_LOCKA_Pos _U_(1) /**< (PMC_IMR) PLLA Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKA_Msk (_U_(0x1) << PMC_IMR_LOCKA_Pos) /**< (PMC_IMR) PLLA Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKA(value) (PMC_IMR_LOCKA_Msk & ((value) << PMC_IMR_LOCKA_Pos)) +#define PMC_IMR_MCKRDY_Pos _U_(3) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Position */ +#define PMC_IMR_MCKRDY_Msk (_U_(0x1) << PMC_IMR_MCKRDY_Pos) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Mask */ +#define PMC_IMR_MCKRDY(value) (PMC_IMR_MCKRDY_Msk & ((value) << PMC_IMR_MCKRDY_Pos)) +#define PMC_IMR_LOCKU_Pos _U_(6) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKU_Msk (_U_(0x1) << PMC_IMR_LOCKU_Pos) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKU(value) (PMC_IMR_LOCKU_Msk & ((value) << PMC_IMR_LOCKU_Pos)) +#define PMC_IMR_PCKRDY0_Pos _U_(8) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY0_Msk (_U_(0x1) << PMC_IMR_PCKRDY0_Pos) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY0(value) (PMC_IMR_PCKRDY0_Msk & ((value) << PMC_IMR_PCKRDY0_Pos)) +#define PMC_IMR_PCKRDY1_Pos _U_(9) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY1_Msk (_U_(0x1) << PMC_IMR_PCKRDY1_Pos) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY1(value) (PMC_IMR_PCKRDY1_Msk & ((value) << PMC_IMR_PCKRDY1_Pos)) +#define PMC_IMR_PCKRDY2_Pos _U_(10) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY2_Msk (_U_(0x1) << PMC_IMR_PCKRDY2_Pos) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY2(value) (PMC_IMR_PCKRDY2_Msk & ((value) << PMC_IMR_PCKRDY2_Pos)) +#define PMC_IMR_PCKRDY3_Pos _U_(11) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY3_Msk (_U_(0x1) << PMC_IMR_PCKRDY3_Pos) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY3(value) (PMC_IMR_PCKRDY3_Msk & ((value) << PMC_IMR_PCKRDY3_Pos)) +#define PMC_IMR_PCKRDY4_Pos _U_(12) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY4_Msk (_U_(0x1) << PMC_IMR_PCKRDY4_Pos) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY4(value) (PMC_IMR_PCKRDY4_Msk & ((value) << PMC_IMR_PCKRDY4_Pos)) +#define PMC_IMR_PCKRDY5_Pos _U_(13) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY5_Msk (_U_(0x1) << PMC_IMR_PCKRDY5_Pos) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY5(value) (PMC_IMR_PCKRDY5_Msk & ((value) << PMC_IMR_PCKRDY5_Pos)) +#define PMC_IMR_PCKRDY6_Pos _U_(14) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY6_Msk (_U_(0x1) << PMC_IMR_PCKRDY6_Pos) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY6(value) (PMC_IMR_PCKRDY6_Msk & ((value) << PMC_IMR_PCKRDY6_Pos)) +#define PMC_IMR_MOSCSELS_Pos _U_(16) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Position */ +#define PMC_IMR_MOSCSELS_Msk (_U_(0x1) << PMC_IMR_MOSCSELS_Pos) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCSELS(value) (PMC_IMR_MOSCSELS_Msk & ((value) << PMC_IMR_MOSCSELS_Pos)) +#define PMC_IMR_MOSCRCS_Pos _U_(17) /**< (PMC_IMR) Main RC Status Interrupt Mask Position */ +#define PMC_IMR_MOSCRCS_Msk (_U_(0x1) << PMC_IMR_MOSCRCS_Pos) /**< (PMC_IMR) Main RC Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCRCS(value) (PMC_IMR_MOSCRCS_Msk & ((value) << PMC_IMR_MOSCRCS_Pos)) +#define PMC_IMR_CFDEV_Pos _U_(18) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Position */ +#define PMC_IMR_CFDEV_Msk (_U_(0x1) << PMC_IMR_CFDEV_Pos) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Mask */ +#define PMC_IMR_CFDEV(value) (PMC_IMR_CFDEV_Msk & ((value) << PMC_IMR_CFDEV_Pos)) +#define PMC_IMR_XT32KERR_Pos _U_(21) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Position */ +#define PMC_IMR_XT32KERR_Msk (_U_(0x1) << PMC_IMR_XT32KERR_Pos) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Mask */ +#define PMC_IMR_XT32KERR(value) (PMC_IMR_XT32KERR_Msk & ((value) << PMC_IMR_XT32KERR_Pos)) +#define PMC_IMR_Msk _U_(0x00277F4B) /**< (PMC_IMR) Register Mask */ + +#define PMC_IMR_PCKRDY_Pos _U_(8) /**< (PMC_IMR Position) Programmable Clock Ready x Interrupt Mask */ +#define PMC_IMR_PCKRDY_Msk (_U_(0x7F) << PMC_IMR_PCKRDY_Pos) /**< (PMC_IMR Mask) PCKRDY */ +#define PMC_IMR_PCKRDY(value) (PMC_IMR_PCKRDY_Msk & ((value) << PMC_IMR_PCKRDY_Pos)) + +/* -------- PMC_FSMR : (PMC Offset: 0x70) (R/W 32) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0_Pos _U_(0) /**< (PMC_FSMR) Fast Startup Input Enable 0 Position */ +#define PMC_FSMR_FSTT0_Msk (_U_(0x1) << PMC_FSMR_FSTT0_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 0 Mask */ +#define PMC_FSMR_FSTT0(value) (PMC_FSMR_FSTT0_Msk & ((value) << PMC_FSMR_FSTT0_Pos)) +#define PMC_FSMR_FSTT1_Pos _U_(1) /**< (PMC_FSMR) Fast Startup Input Enable 1 Position */ +#define PMC_FSMR_FSTT1_Msk (_U_(0x1) << PMC_FSMR_FSTT1_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 1 Mask */ +#define PMC_FSMR_FSTT1(value) (PMC_FSMR_FSTT1_Msk & ((value) << PMC_FSMR_FSTT1_Pos)) +#define PMC_FSMR_FSTT2_Pos _U_(2) /**< (PMC_FSMR) Fast Startup Input Enable 2 Position */ +#define PMC_FSMR_FSTT2_Msk (_U_(0x1) << PMC_FSMR_FSTT2_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 2 Mask */ +#define PMC_FSMR_FSTT2(value) (PMC_FSMR_FSTT2_Msk & ((value) << PMC_FSMR_FSTT2_Pos)) +#define PMC_FSMR_FSTT3_Pos _U_(3) /**< (PMC_FSMR) Fast Startup Input Enable 3 Position */ +#define PMC_FSMR_FSTT3_Msk (_U_(0x1) << PMC_FSMR_FSTT3_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 3 Mask */ +#define PMC_FSMR_FSTT3(value) (PMC_FSMR_FSTT3_Msk & ((value) << PMC_FSMR_FSTT3_Pos)) +#define PMC_FSMR_FSTT4_Pos _U_(4) /**< (PMC_FSMR) Fast Startup Input Enable 4 Position */ +#define PMC_FSMR_FSTT4_Msk (_U_(0x1) << PMC_FSMR_FSTT4_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 4 Mask */ +#define PMC_FSMR_FSTT4(value) (PMC_FSMR_FSTT4_Msk & ((value) << PMC_FSMR_FSTT4_Pos)) +#define PMC_FSMR_FSTT5_Pos _U_(5) /**< (PMC_FSMR) Fast Startup Input Enable 5 Position */ +#define PMC_FSMR_FSTT5_Msk (_U_(0x1) << PMC_FSMR_FSTT5_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 5 Mask */ +#define PMC_FSMR_FSTT5(value) (PMC_FSMR_FSTT5_Msk & ((value) << PMC_FSMR_FSTT5_Pos)) +#define PMC_FSMR_FSTT6_Pos _U_(6) /**< (PMC_FSMR) Fast Startup Input Enable 6 Position */ +#define PMC_FSMR_FSTT6_Msk (_U_(0x1) << PMC_FSMR_FSTT6_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 6 Mask */ +#define PMC_FSMR_FSTT6(value) (PMC_FSMR_FSTT6_Msk & ((value) << PMC_FSMR_FSTT6_Pos)) +#define PMC_FSMR_FSTT7_Pos _U_(7) /**< (PMC_FSMR) Fast Startup Input Enable 7 Position */ +#define PMC_FSMR_FSTT7_Msk (_U_(0x1) << PMC_FSMR_FSTT7_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 7 Mask */ +#define PMC_FSMR_FSTT7(value) (PMC_FSMR_FSTT7_Msk & ((value) << PMC_FSMR_FSTT7_Pos)) +#define PMC_FSMR_FSTT8_Pos _U_(8) /**< (PMC_FSMR) Fast Startup Input Enable 8 Position */ +#define PMC_FSMR_FSTT8_Msk (_U_(0x1) << PMC_FSMR_FSTT8_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 8 Mask */ +#define PMC_FSMR_FSTT8(value) (PMC_FSMR_FSTT8_Msk & ((value) << PMC_FSMR_FSTT8_Pos)) +#define PMC_FSMR_FSTT9_Pos _U_(9) /**< (PMC_FSMR) Fast Startup Input Enable 9 Position */ +#define PMC_FSMR_FSTT9_Msk (_U_(0x1) << PMC_FSMR_FSTT9_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 9 Mask */ +#define PMC_FSMR_FSTT9(value) (PMC_FSMR_FSTT9_Msk & ((value) << PMC_FSMR_FSTT9_Pos)) +#define PMC_FSMR_FSTT10_Pos _U_(10) /**< (PMC_FSMR) Fast Startup Input Enable 10 Position */ +#define PMC_FSMR_FSTT10_Msk (_U_(0x1) << PMC_FSMR_FSTT10_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 10 Mask */ +#define PMC_FSMR_FSTT10(value) (PMC_FSMR_FSTT10_Msk & ((value) << PMC_FSMR_FSTT10_Pos)) +#define PMC_FSMR_FSTT11_Pos _U_(11) /**< (PMC_FSMR) Fast Startup Input Enable 11 Position */ +#define PMC_FSMR_FSTT11_Msk (_U_(0x1) << PMC_FSMR_FSTT11_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 11 Mask */ +#define PMC_FSMR_FSTT11(value) (PMC_FSMR_FSTT11_Msk & ((value) << PMC_FSMR_FSTT11_Pos)) +#define PMC_FSMR_FSTT12_Pos _U_(12) /**< (PMC_FSMR) Fast Startup Input Enable 12 Position */ +#define PMC_FSMR_FSTT12_Msk (_U_(0x1) << PMC_FSMR_FSTT12_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 12 Mask */ +#define PMC_FSMR_FSTT12(value) (PMC_FSMR_FSTT12_Msk & ((value) << PMC_FSMR_FSTT12_Pos)) +#define PMC_FSMR_FSTT13_Pos _U_(13) /**< (PMC_FSMR) Fast Startup Input Enable 13 Position */ +#define PMC_FSMR_FSTT13_Msk (_U_(0x1) << PMC_FSMR_FSTT13_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 13 Mask */ +#define PMC_FSMR_FSTT13(value) (PMC_FSMR_FSTT13_Msk & ((value) << PMC_FSMR_FSTT13_Pos)) +#define PMC_FSMR_FSTT14_Pos _U_(14) /**< (PMC_FSMR) Fast Startup Input Enable 14 Position */ +#define PMC_FSMR_FSTT14_Msk (_U_(0x1) << PMC_FSMR_FSTT14_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 14 Mask */ +#define PMC_FSMR_FSTT14(value) (PMC_FSMR_FSTT14_Msk & ((value) << PMC_FSMR_FSTT14_Pos)) +#define PMC_FSMR_FSTT15_Pos _U_(15) /**< (PMC_FSMR) Fast Startup Input Enable 15 Position */ +#define PMC_FSMR_FSTT15_Msk (_U_(0x1) << PMC_FSMR_FSTT15_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 15 Mask */ +#define PMC_FSMR_FSTT15(value) (PMC_FSMR_FSTT15_Msk & ((value) << PMC_FSMR_FSTT15_Pos)) +#define PMC_FSMR_RTTAL_Pos _U_(16) /**< (PMC_FSMR) RTT Alarm Enable Position */ +#define PMC_FSMR_RTTAL_Msk (_U_(0x1) << PMC_FSMR_RTTAL_Pos) /**< (PMC_FSMR) RTT Alarm Enable Mask */ +#define PMC_FSMR_RTTAL(value) (PMC_FSMR_RTTAL_Msk & ((value) << PMC_FSMR_RTTAL_Pos)) +#define PMC_FSMR_RTCAL_Pos _U_(17) /**< (PMC_FSMR) RTC Alarm Enable Position */ +#define PMC_FSMR_RTCAL_Msk (_U_(0x1) << PMC_FSMR_RTCAL_Pos) /**< (PMC_FSMR) RTC Alarm Enable Mask */ +#define PMC_FSMR_RTCAL(value) (PMC_FSMR_RTCAL_Msk & ((value) << PMC_FSMR_RTCAL_Pos)) +#define PMC_FSMR_USBAL_Pos _U_(18) /**< (PMC_FSMR) USB Alarm Enable Position */ +#define PMC_FSMR_USBAL_Msk (_U_(0x1) << PMC_FSMR_USBAL_Pos) /**< (PMC_FSMR) USB Alarm Enable Mask */ +#define PMC_FSMR_USBAL(value) (PMC_FSMR_USBAL_Msk & ((value) << PMC_FSMR_USBAL_Pos)) +#define PMC_FSMR_LPM_Pos _U_(20) /**< (PMC_FSMR) Low-power Mode Position */ +#define PMC_FSMR_LPM_Msk (_U_(0x1) << PMC_FSMR_LPM_Pos) /**< (PMC_FSMR) Low-power Mode Mask */ +#define PMC_FSMR_LPM(value) (PMC_FSMR_LPM_Msk & ((value) << PMC_FSMR_LPM_Pos)) +#define PMC_FSMR_FLPM_Pos _U_(21) /**< (PMC_FSMR) Flash Low-power Mode Position */ +#define PMC_FSMR_FLPM_Msk (_U_(0x3) << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash Low-power Mode Mask */ +#define PMC_FSMR_FLPM(value) (PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)) +#define PMC_FSMR_FLPM_FLASH_STANDBY_Val _U_(0x0) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val _U_(0x1) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE_Val _U_(0x2) /**< (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FLPM_FLASH_STANDBY (PMC_FSMR_FLPM_FLASH_STANDBY_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_IDLE (PMC_FSMR_FLPM_FLASH_IDLE_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Idle mode Position */ +#define PMC_FSMR_FFLPM_Pos _U_(23) /**< (PMC_FSMR) Force Flash Low-power Mode Position */ +#define PMC_FSMR_FFLPM_Msk (_U_(0x1) << PMC_FSMR_FFLPM_Pos) /**< (PMC_FSMR) Force Flash Low-power Mode Mask */ +#define PMC_FSMR_FFLPM(value) (PMC_FSMR_FFLPM_Msk & ((value) << PMC_FSMR_FFLPM_Pos)) +#define PMC_FSMR_Msk _U_(0x00F7FFFF) /**< (PMC_FSMR) Register Mask */ + +#define PMC_FSMR_FSTT_Pos _U_(0) /**< (PMC_FSMR Position) Fast Startup Input Enable x */ +#define PMC_FSMR_FSTT_Msk (_U_(0xFFFF) << PMC_FSMR_FSTT_Pos) /**< (PMC_FSMR Mask) FSTT */ +#define PMC_FSMR_FSTT(value) (PMC_FSMR_FSTT_Msk & ((value) << PMC_FSMR_FSTT_Pos)) + +/* -------- PMC_FSPR : (PMC Offset: 0x74) (R/W 32) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0_Pos _U_(0) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Position */ +#define PMC_FSPR_FSTP0_Msk (_U_(0x1) << PMC_FSPR_FSTP0_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Mask */ +#define PMC_FSPR_FSTP0(value) (PMC_FSPR_FSTP0_Msk & ((value) << PMC_FSPR_FSTP0_Pos)) +#define PMC_FSPR_FSTP1_Pos _U_(1) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Position */ +#define PMC_FSPR_FSTP1_Msk (_U_(0x1) << PMC_FSPR_FSTP1_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Mask */ +#define PMC_FSPR_FSTP1(value) (PMC_FSPR_FSTP1_Msk & ((value) << PMC_FSPR_FSTP1_Pos)) +#define PMC_FSPR_FSTP2_Pos _U_(2) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Position */ +#define PMC_FSPR_FSTP2_Msk (_U_(0x1) << PMC_FSPR_FSTP2_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Mask */ +#define PMC_FSPR_FSTP2(value) (PMC_FSPR_FSTP2_Msk & ((value) << PMC_FSPR_FSTP2_Pos)) +#define PMC_FSPR_FSTP3_Pos _U_(3) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Position */ +#define PMC_FSPR_FSTP3_Msk (_U_(0x1) << PMC_FSPR_FSTP3_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Mask */ +#define PMC_FSPR_FSTP3(value) (PMC_FSPR_FSTP3_Msk & ((value) << PMC_FSPR_FSTP3_Pos)) +#define PMC_FSPR_FSTP4_Pos _U_(4) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Position */ +#define PMC_FSPR_FSTP4_Msk (_U_(0x1) << PMC_FSPR_FSTP4_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Mask */ +#define PMC_FSPR_FSTP4(value) (PMC_FSPR_FSTP4_Msk & ((value) << PMC_FSPR_FSTP4_Pos)) +#define PMC_FSPR_FSTP5_Pos _U_(5) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Position */ +#define PMC_FSPR_FSTP5_Msk (_U_(0x1) << PMC_FSPR_FSTP5_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Mask */ +#define PMC_FSPR_FSTP5(value) (PMC_FSPR_FSTP5_Msk & ((value) << PMC_FSPR_FSTP5_Pos)) +#define PMC_FSPR_FSTP6_Pos _U_(6) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Position */ +#define PMC_FSPR_FSTP6_Msk (_U_(0x1) << PMC_FSPR_FSTP6_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Mask */ +#define PMC_FSPR_FSTP6(value) (PMC_FSPR_FSTP6_Msk & ((value) << PMC_FSPR_FSTP6_Pos)) +#define PMC_FSPR_FSTP7_Pos _U_(7) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Position */ +#define PMC_FSPR_FSTP7_Msk (_U_(0x1) << PMC_FSPR_FSTP7_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Mask */ +#define PMC_FSPR_FSTP7(value) (PMC_FSPR_FSTP7_Msk & ((value) << PMC_FSPR_FSTP7_Pos)) +#define PMC_FSPR_FSTP8_Pos _U_(8) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Position */ +#define PMC_FSPR_FSTP8_Msk (_U_(0x1) << PMC_FSPR_FSTP8_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Mask */ +#define PMC_FSPR_FSTP8(value) (PMC_FSPR_FSTP8_Msk & ((value) << PMC_FSPR_FSTP8_Pos)) +#define PMC_FSPR_FSTP9_Pos _U_(9) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Position */ +#define PMC_FSPR_FSTP9_Msk (_U_(0x1) << PMC_FSPR_FSTP9_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Mask */ +#define PMC_FSPR_FSTP9(value) (PMC_FSPR_FSTP9_Msk & ((value) << PMC_FSPR_FSTP9_Pos)) +#define PMC_FSPR_FSTP10_Pos _U_(10) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Position */ +#define PMC_FSPR_FSTP10_Msk (_U_(0x1) << PMC_FSPR_FSTP10_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Mask */ +#define PMC_FSPR_FSTP10(value) (PMC_FSPR_FSTP10_Msk & ((value) << PMC_FSPR_FSTP10_Pos)) +#define PMC_FSPR_FSTP11_Pos _U_(11) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Position */ +#define PMC_FSPR_FSTP11_Msk (_U_(0x1) << PMC_FSPR_FSTP11_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Mask */ +#define PMC_FSPR_FSTP11(value) (PMC_FSPR_FSTP11_Msk & ((value) << PMC_FSPR_FSTP11_Pos)) +#define PMC_FSPR_FSTP12_Pos _U_(12) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Position */ +#define PMC_FSPR_FSTP12_Msk (_U_(0x1) << PMC_FSPR_FSTP12_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Mask */ +#define PMC_FSPR_FSTP12(value) (PMC_FSPR_FSTP12_Msk & ((value) << PMC_FSPR_FSTP12_Pos)) +#define PMC_FSPR_FSTP13_Pos _U_(13) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Position */ +#define PMC_FSPR_FSTP13_Msk (_U_(0x1) << PMC_FSPR_FSTP13_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Mask */ +#define PMC_FSPR_FSTP13(value) (PMC_FSPR_FSTP13_Msk & ((value) << PMC_FSPR_FSTP13_Pos)) +#define PMC_FSPR_FSTP14_Pos _U_(14) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Position */ +#define PMC_FSPR_FSTP14_Msk (_U_(0x1) << PMC_FSPR_FSTP14_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Mask */ +#define PMC_FSPR_FSTP14(value) (PMC_FSPR_FSTP14_Msk & ((value) << PMC_FSPR_FSTP14_Pos)) +#define PMC_FSPR_FSTP15_Pos _U_(15) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Position */ +#define PMC_FSPR_FSTP15_Msk (_U_(0x1) << PMC_FSPR_FSTP15_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Mask */ +#define PMC_FSPR_FSTP15(value) (PMC_FSPR_FSTP15_Msk & ((value) << PMC_FSPR_FSTP15_Pos)) +#define PMC_FSPR_Msk _U_(0x0000FFFF) /**< (PMC_FSPR) Register Mask */ + +#define PMC_FSPR_FSTP_Pos _U_(0) /**< (PMC_FSPR Position) Fast Startup Input Polarity x5 */ +#define PMC_FSPR_FSTP_Msk (_U_(0xFFFF) << PMC_FSPR_FSTP_Pos) /**< (PMC_FSPR Mask) FSTP */ +#define PMC_FSPR_FSTP(value) (PMC_FSPR_FSTP_Msk & ((value) << PMC_FSPR_FSTP_Pos)) + +/* -------- PMC_FOCR : (PMC Offset: 0x78) ( /W 32) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR_Pos _U_(0) /**< (PMC_FOCR) Fault Output Clear Position */ +#define PMC_FOCR_FOCLR_Msk (_U_(0x1) << PMC_FOCR_FOCLR_Pos) /**< (PMC_FOCR) Fault Output Clear Mask */ +#define PMC_FOCR_FOCLR(value) (PMC_FOCR_FOCLR_Msk & ((value) << PMC_FOCR_FOCLR_Pos)) +#define PMC_FOCR_Msk _U_(0x00000001) /**< (PMC_FOCR) Register Mask */ + + +/* -------- PMC_WPMR : (PMC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN_Pos _U_(0) /**< (PMC_WPMR) Write Protection Enable Position */ +#define PMC_WPMR_WPEN_Msk (_U_(0x1) << PMC_WPMR_WPEN_Pos) /**< (PMC_WPMR) Write Protection Enable Mask */ +#define PMC_WPMR_WPEN(value) (PMC_WPMR_WPEN_Msk & ((value) << PMC_WPMR_WPEN_Pos)) +#define PMC_WPMR_WPKEY_Pos _U_(8) /**< (PMC_WPMR) Write Protection Key Position */ +#define PMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Write Protection Key Mask */ +#define PMC_WPMR_WPKEY(value) (PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)) +#define PMC_WPMR_WPKEY_PASSWD_Val _U_(0x504D43) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define PMC_WPMR_WPKEY_PASSWD (PMC_WPMR_WPKEY_PASSWD_Val << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define PMC_WPMR_Msk _U_(0xFFFFFF01) /**< (PMC_WPMR) Register Mask */ + + +/* -------- PMC_WPSR : (PMC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS_Pos _U_(0) /**< (PMC_WPSR) Write Protection Violation Status Position */ +#define PMC_WPSR_WPVS_Msk (_U_(0x1) << PMC_WPSR_WPVS_Pos) /**< (PMC_WPSR) Write Protection Violation Status Mask */ +#define PMC_WPSR_WPVS(value) (PMC_WPSR_WPVS_Msk & ((value) << PMC_WPSR_WPVS_Pos)) +#define PMC_WPSR_WPVSRC_Pos _U_(8) /**< (PMC_WPSR) Write Protection Violation Source Position */ +#define PMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PMC_WPSR_WPVSRC_Pos) /**< (PMC_WPSR) Write Protection Violation Source Mask */ +#define PMC_WPSR_WPVSRC(value) (PMC_WPSR_WPVSRC_Msk & ((value) << PMC_WPSR_WPVSRC_Pos)) +#define PMC_WPSR_Msk _U_(0x00FFFF01) /**< (PMC_WPSR) Register Mask */ + + +/* -------- PMC_PCER1 : (PMC Offset: 0x100) ( /W 32) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32_Pos _U_(0) /**< (PMC_PCER1) Peripheral Clock 32 Enable Position */ +#define PMC_PCER1_PID32_Msk (_U_(0x1) << PMC_PCER1_PID32_Pos) /**< (PMC_PCER1) Peripheral Clock 32 Enable Mask */ +#define PMC_PCER1_PID32(value) (PMC_PCER1_PID32_Msk & ((value) << PMC_PCER1_PID32_Pos)) +#define PMC_PCER1_PID33_Pos _U_(1) /**< (PMC_PCER1) Peripheral Clock 33 Enable Position */ +#define PMC_PCER1_PID33_Msk (_U_(0x1) << PMC_PCER1_PID33_Pos) /**< (PMC_PCER1) Peripheral Clock 33 Enable Mask */ +#define PMC_PCER1_PID33(value) (PMC_PCER1_PID33_Msk & ((value) << PMC_PCER1_PID33_Pos)) +#define PMC_PCER1_PID34_Pos _U_(2) /**< (PMC_PCER1) Peripheral Clock 34 Enable Position */ +#define PMC_PCER1_PID34_Msk (_U_(0x1) << PMC_PCER1_PID34_Pos) /**< (PMC_PCER1) Peripheral Clock 34 Enable Mask */ +#define PMC_PCER1_PID34(value) (PMC_PCER1_PID34_Msk & ((value) << PMC_PCER1_PID34_Pos)) +#define PMC_PCER1_PID35_Pos _U_(3) /**< (PMC_PCER1) Peripheral Clock 35 Enable Position */ +#define PMC_PCER1_PID35_Msk (_U_(0x1) << PMC_PCER1_PID35_Pos) /**< (PMC_PCER1) Peripheral Clock 35 Enable Mask */ +#define PMC_PCER1_PID35(value) (PMC_PCER1_PID35_Msk & ((value) << PMC_PCER1_PID35_Pos)) +#define PMC_PCER1_PID37_Pos _U_(5) /**< (PMC_PCER1) Peripheral Clock 37 Enable Position */ +#define PMC_PCER1_PID37_Msk (_U_(0x1) << PMC_PCER1_PID37_Pos) /**< (PMC_PCER1) Peripheral Clock 37 Enable Mask */ +#define PMC_PCER1_PID37(value) (PMC_PCER1_PID37_Msk & ((value) << PMC_PCER1_PID37_Pos)) +#define PMC_PCER1_PID39_Pos _U_(7) /**< (PMC_PCER1) Peripheral Clock 39 Enable Position */ +#define PMC_PCER1_PID39_Msk (_U_(0x1) << PMC_PCER1_PID39_Pos) /**< (PMC_PCER1) Peripheral Clock 39 Enable Mask */ +#define PMC_PCER1_PID39(value) (PMC_PCER1_PID39_Msk & ((value) << PMC_PCER1_PID39_Pos)) +#define PMC_PCER1_PID40_Pos _U_(8) /**< (PMC_PCER1) Peripheral Clock 40 Enable Position */ +#define PMC_PCER1_PID40_Msk (_U_(0x1) << PMC_PCER1_PID40_Pos) /**< (PMC_PCER1) Peripheral Clock 40 Enable Mask */ +#define PMC_PCER1_PID40(value) (PMC_PCER1_PID40_Msk & ((value) << PMC_PCER1_PID40_Pos)) +#define PMC_PCER1_PID41_Pos _U_(9) /**< (PMC_PCER1) Peripheral Clock 41 Enable Position */ +#define PMC_PCER1_PID41_Msk (_U_(0x1) << PMC_PCER1_PID41_Pos) /**< (PMC_PCER1) Peripheral Clock 41 Enable Mask */ +#define PMC_PCER1_PID41(value) (PMC_PCER1_PID41_Msk & ((value) << PMC_PCER1_PID41_Pos)) +#define PMC_PCER1_PID42_Pos _U_(10) /**< (PMC_PCER1) Peripheral Clock 42 Enable Position */ +#define PMC_PCER1_PID42_Msk (_U_(0x1) << PMC_PCER1_PID42_Pos) /**< (PMC_PCER1) Peripheral Clock 42 Enable Mask */ +#define PMC_PCER1_PID42(value) (PMC_PCER1_PID42_Msk & ((value) << PMC_PCER1_PID42_Pos)) +#define PMC_PCER1_PID43_Pos _U_(11) /**< (PMC_PCER1) Peripheral Clock 43 Enable Position */ +#define PMC_PCER1_PID43_Msk (_U_(0x1) << PMC_PCER1_PID43_Pos) /**< (PMC_PCER1) Peripheral Clock 43 Enable Mask */ +#define PMC_PCER1_PID43(value) (PMC_PCER1_PID43_Msk & ((value) << PMC_PCER1_PID43_Pos)) +#define PMC_PCER1_PID44_Pos _U_(12) /**< (PMC_PCER1) Peripheral Clock 44 Enable Position */ +#define PMC_PCER1_PID44_Msk (_U_(0x1) << PMC_PCER1_PID44_Pos) /**< (PMC_PCER1) Peripheral Clock 44 Enable Mask */ +#define PMC_PCER1_PID44(value) (PMC_PCER1_PID44_Msk & ((value) << PMC_PCER1_PID44_Pos)) +#define PMC_PCER1_PID45_Pos _U_(13) /**< (PMC_PCER1) Peripheral Clock 45 Enable Position */ +#define PMC_PCER1_PID45_Msk (_U_(0x1) << PMC_PCER1_PID45_Pos) /**< (PMC_PCER1) Peripheral Clock 45 Enable Mask */ +#define PMC_PCER1_PID45(value) (PMC_PCER1_PID45_Msk & ((value) << PMC_PCER1_PID45_Pos)) +#define PMC_PCER1_PID46_Pos _U_(14) /**< (PMC_PCER1) Peripheral Clock 46 Enable Position */ +#define PMC_PCER1_PID46_Msk (_U_(0x1) << PMC_PCER1_PID46_Pos) /**< (PMC_PCER1) Peripheral Clock 46 Enable Mask */ +#define PMC_PCER1_PID46(value) (PMC_PCER1_PID46_Msk & ((value) << PMC_PCER1_PID46_Pos)) +#define PMC_PCER1_PID47_Pos _U_(15) /**< (PMC_PCER1) Peripheral Clock 47 Enable Position */ +#define PMC_PCER1_PID47_Msk (_U_(0x1) << PMC_PCER1_PID47_Pos) /**< (PMC_PCER1) Peripheral Clock 47 Enable Mask */ +#define PMC_PCER1_PID47(value) (PMC_PCER1_PID47_Msk & ((value) << PMC_PCER1_PID47_Pos)) +#define PMC_PCER1_PID48_Pos _U_(16) /**< (PMC_PCER1) Peripheral Clock 48 Enable Position */ +#define PMC_PCER1_PID48_Msk (_U_(0x1) << PMC_PCER1_PID48_Pos) /**< (PMC_PCER1) Peripheral Clock 48 Enable Mask */ +#define PMC_PCER1_PID48(value) (PMC_PCER1_PID48_Msk & ((value) << PMC_PCER1_PID48_Pos)) +#define PMC_PCER1_PID49_Pos _U_(17) /**< (PMC_PCER1) Peripheral Clock 49 Enable Position */ +#define PMC_PCER1_PID49_Msk (_U_(0x1) << PMC_PCER1_PID49_Pos) /**< (PMC_PCER1) Peripheral Clock 49 Enable Mask */ +#define PMC_PCER1_PID49(value) (PMC_PCER1_PID49_Msk & ((value) << PMC_PCER1_PID49_Pos)) +#define PMC_PCER1_PID50_Pos _U_(18) /**< (PMC_PCER1) Peripheral Clock 50 Enable Position */ +#define PMC_PCER1_PID50_Msk (_U_(0x1) << PMC_PCER1_PID50_Pos) /**< (PMC_PCER1) Peripheral Clock 50 Enable Mask */ +#define PMC_PCER1_PID50(value) (PMC_PCER1_PID50_Msk & ((value) << PMC_PCER1_PID50_Pos)) +#define PMC_PCER1_PID51_Pos _U_(19) /**< (PMC_PCER1) Peripheral Clock 51 Enable Position */ +#define PMC_PCER1_PID51_Msk (_U_(0x1) << PMC_PCER1_PID51_Pos) /**< (PMC_PCER1) Peripheral Clock 51 Enable Mask */ +#define PMC_PCER1_PID51(value) (PMC_PCER1_PID51_Msk & ((value) << PMC_PCER1_PID51_Pos)) +#define PMC_PCER1_PID52_Pos _U_(20) /**< (PMC_PCER1) Peripheral Clock 52 Enable Position */ +#define PMC_PCER1_PID52_Msk (_U_(0x1) << PMC_PCER1_PID52_Pos) /**< (PMC_PCER1) Peripheral Clock 52 Enable Mask */ +#define PMC_PCER1_PID52(value) (PMC_PCER1_PID52_Msk & ((value) << PMC_PCER1_PID52_Pos)) +#define PMC_PCER1_PID53_Pos _U_(21) /**< (PMC_PCER1) Peripheral Clock 53 Enable Position */ +#define PMC_PCER1_PID53_Msk (_U_(0x1) << PMC_PCER1_PID53_Pos) /**< (PMC_PCER1) Peripheral Clock 53 Enable Mask */ +#define PMC_PCER1_PID53(value) (PMC_PCER1_PID53_Msk & ((value) << PMC_PCER1_PID53_Pos)) +#define PMC_PCER1_PID56_Pos _U_(24) /**< (PMC_PCER1) Peripheral Clock 56 Enable Position */ +#define PMC_PCER1_PID56_Msk (_U_(0x1) << PMC_PCER1_PID56_Pos) /**< (PMC_PCER1) Peripheral Clock 56 Enable Mask */ +#define PMC_PCER1_PID56(value) (PMC_PCER1_PID56_Msk & ((value) << PMC_PCER1_PID56_Pos)) +#define PMC_PCER1_PID57_Pos _U_(25) /**< (PMC_PCER1) Peripheral Clock 57 Enable Position */ +#define PMC_PCER1_PID57_Msk (_U_(0x1) << PMC_PCER1_PID57_Pos) /**< (PMC_PCER1) Peripheral Clock 57 Enable Mask */ +#define PMC_PCER1_PID57(value) (PMC_PCER1_PID57_Msk & ((value) << PMC_PCER1_PID57_Pos)) +#define PMC_PCER1_PID58_Pos _U_(26) /**< (PMC_PCER1) Peripheral Clock 58 Enable Position */ +#define PMC_PCER1_PID58_Msk (_U_(0x1) << PMC_PCER1_PID58_Pos) /**< (PMC_PCER1) Peripheral Clock 58 Enable Mask */ +#define PMC_PCER1_PID58(value) (PMC_PCER1_PID58_Msk & ((value) << PMC_PCER1_PID58_Pos)) +#define PMC_PCER1_PID59_Pos _U_(27) /**< (PMC_PCER1) Peripheral Clock 59 Enable Position */ +#define PMC_PCER1_PID59_Msk (_U_(0x1) << PMC_PCER1_PID59_Pos) /**< (PMC_PCER1) Peripheral Clock 59 Enable Mask */ +#define PMC_PCER1_PID59(value) (PMC_PCER1_PID59_Msk & ((value) << PMC_PCER1_PID59_Pos)) +#define PMC_PCER1_PID60_Pos _U_(28) /**< (PMC_PCER1) Peripheral Clock 60 Enable Position */ +#define PMC_PCER1_PID60_Msk (_U_(0x1) << PMC_PCER1_PID60_Pos) /**< (PMC_PCER1) Peripheral Clock 60 Enable Mask */ +#define PMC_PCER1_PID60(value) (PMC_PCER1_PID60_Msk & ((value) << PMC_PCER1_PID60_Pos)) +#define PMC_PCER1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCER1) Register Mask */ + +#define PMC_PCER1_PID_Pos _U_(0) /**< (PMC_PCER1 Position) Peripheral Clock 6x Enable */ +#define PMC_PCER1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER1_PID_Pos) /**< (PMC_PCER1 Mask) PID */ +#define PMC_PCER1_PID(value) (PMC_PCER1_PID_Msk & ((value) << PMC_PCER1_PID_Pos)) + +/* -------- PMC_PCDR1 : (PMC Offset: 0x104) ( /W 32) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32_Pos _U_(0) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Position */ +#define PMC_PCDR1_PID32_Msk (_U_(0x1) << PMC_PCDR1_PID32_Pos) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Mask */ +#define PMC_PCDR1_PID32(value) (PMC_PCDR1_PID32_Msk & ((value) << PMC_PCDR1_PID32_Pos)) +#define PMC_PCDR1_PID33_Pos _U_(1) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Position */ +#define PMC_PCDR1_PID33_Msk (_U_(0x1) << PMC_PCDR1_PID33_Pos) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Mask */ +#define PMC_PCDR1_PID33(value) (PMC_PCDR1_PID33_Msk & ((value) << PMC_PCDR1_PID33_Pos)) +#define PMC_PCDR1_PID34_Pos _U_(2) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Position */ +#define PMC_PCDR1_PID34_Msk (_U_(0x1) << PMC_PCDR1_PID34_Pos) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Mask */ +#define PMC_PCDR1_PID34(value) (PMC_PCDR1_PID34_Msk & ((value) << PMC_PCDR1_PID34_Pos)) +#define PMC_PCDR1_PID35_Pos _U_(3) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Position */ +#define PMC_PCDR1_PID35_Msk (_U_(0x1) << PMC_PCDR1_PID35_Pos) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Mask */ +#define PMC_PCDR1_PID35(value) (PMC_PCDR1_PID35_Msk & ((value) << PMC_PCDR1_PID35_Pos)) +#define PMC_PCDR1_PID37_Pos _U_(5) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Position */ +#define PMC_PCDR1_PID37_Msk (_U_(0x1) << PMC_PCDR1_PID37_Pos) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Mask */ +#define PMC_PCDR1_PID37(value) (PMC_PCDR1_PID37_Msk & ((value) << PMC_PCDR1_PID37_Pos)) +#define PMC_PCDR1_PID39_Pos _U_(7) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Position */ +#define PMC_PCDR1_PID39_Msk (_U_(0x1) << PMC_PCDR1_PID39_Pos) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Mask */ +#define PMC_PCDR1_PID39(value) (PMC_PCDR1_PID39_Msk & ((value) << PMC_PCDR1_PID39_Pos)) +#define PMC_PCDR1_PID40_Pos _U_(8) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Position */ +#define PMC_PCDR1_PID40_Msk (_U_(0x1) << PMC_PCDR1_PID40_Pos) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Mask */ +#define PMC_PCDR1_PID40(value) (PMC_PCDR1_PID40_Msk & ((value) << PMC_PCDR1_PID40_Pos)) +#define PMC_PCDR1_PID41_Pos _U_(9) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Position */ +#define PMC_PCDR1_PID41_Msk (_U_(0x1) << PMC_PCDR1_PID41_Pos) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Mask */ +#define PMC_PCDR1_PID41(value) (PMC_PCDR1_PID41_Msk & ((value) << PMC_PCDR1_PID41_Pos)) +#define PMC_PCDR1_PID42_Pos _U_(10) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Position */ +#define PMC_PCDR1_PID42_Msk (_U_(0x1) << PMC_PCDR1_PID42_Pos) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Mask */ +#define PMC_PCDR1_PID42(value) (PMC_PCDR1_PID42_Msk & ((value) << PMC_PCDR1_PID42_Pos)) +#define PMC_PCDR1_PID43_Pos _U_(11) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Position */ +#define PMC_PCDR1_PID43_Msk (_U_(0x1) << PMC_PCDR1_PID43_Pos) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Mask */ +#define PMC_PCDR1_PID43(value) (PMC_PCDR1_PID43_Msk & ((value) << PMC_PCDR1_PID43_Pos)) +#define PMC_PCDR1_PID44_Pos _U_(12) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Position */ +#define PMC_PCDR1_PID44_Msk (_U_(0x1) << PMC_PCDR1_PID44_Pos) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Mask */ +#define PMC_PCDR1_PID44(value) (PMC_PCDR1_PID44_Msk & ((value) << PMC_PCDR1_PID44_Pos)) +#define PMC_PCDR1_PID45_Pos _U_(13) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Position */ +#define PMC_PCDR1_PID45_Msk (_U_(0x1) << PMC_PCDR1_PID45_Pos) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Mask */ +#define PMC_PCDR1_PID45(value) (PMC_PCDR1_PID45_Msk & ((value) << PMC_PCDR1_PID45_Pos)) +#define PMC_PCDR1_PID46_Pos _U_(14) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Position */ +#define PMC_PCDR1_PID46_Msk (_U_(0x1) << PMC_PCDR1_PID46_Pos) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Mask */ +#define PMC_PCDR1_PID46(value) (PMC_PCDR1_PID46_Msk & ((value) << PMC_PCDR1_PID46_Pos)) +#define PMC_PCDR1_PID47_Pos _U_(15) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Position */ +#define PMC_PCDR1_PID47_Msk (_U_(0x1) << PMC_PCDR1_PID47_Pos) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Mask */ +#define PMC_PCDR1_PID47(value) (PMC_PCDR1_PID47_Msk & ((value) << PMC_PCDR1_PID47_Pos)) +#define PMC_PCDR1_PID48_Pos _U_(16) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Position */ +#define PMC_PCDR1_PID48_Msk (_U_(0x1) << PMC_PCDR1_PID48_Pos) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Mask */ +#define PMC_PCDR1_PID48(value) (PMC_PCDR1_PID48_Msk & ((value) << PMC_PCDR1_PID48_Pos)) +#define PMC_PCDR1_PID49_Pos _U_(17) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Position */ +#define PMC_PCDR1_PID49_Msk (_U_(0x1) << PMC_PCDR1_PID49_Pos) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Mask */ +#define PMC_PCDR1_PID49(value) (PMC_PCDR1_PID49_Msk & ((value) << PMC_PCDR1_PID49_Pos)) +#define PMC_PCDR1_PID50_Pos _U_(18) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Position */ +#define PMC_PCDR1_PID50_Msk (_U_(0x1) << PMC_PCDR1_PID50_Pos) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Mask */ +#define PMC_PCDR1_PID50(value) (PMC_PCDR1_PID50_Msk & ((value) << PMC_PCDR1_PID50_Pos)) +#define PMC_PCDR1_PID51_Pos _U_(19) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Position */ +#define PMC_PCDR1_PID51_Msk (_U_(0x1) << PMC_PCDR1_PID51_Pos) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Mask */ +#define PMC_PCDR1_PID51(value) (PMC_PCDR1_PID51_Msk & ((value) << PMC_PCDR1_PID51_Pos)) +#define PMC_PCDR1_PID52_Pos _U_(20) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Position */ +#define PMC_PCDR1_PID52_Msk (_U_(0x1) << PMC_PCDR1_PID52_Pos) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Mask */ +#define PMC_PCDR1_PID52(value) (PMC_PCDR1_PID52_Msk & ((value) << PMC_PCDR1_PID52_Pos)) +#define PMC_PCDR1_PID53_Pos _U_(21) /**< (PMC_PCDR1) Peripheral Clock 53 Disable Position */ +#define PMC_PCDR1_PID53_Msk (_U_(0x1) << PMC_PCDR1_PID53_Pos) /**< (PMC_PCDR1) Peripheral Clock 53 Disable Mask */ +#define PMC_PCDR1_PID53(value) (PMC_PCDR1_PID53_Msk & ((value) << PMC_PCDR1_PID53_Pos)) +#define PMC_PCDR1_PID56_Pos _U_(24) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Position */ +#define PMC_PCDR1_PID56_Msk (_U_(0x1) << PMC_PCDR1_PID56_Pos) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Mask */ +#define PMC_PCDR1_PID56(value) (PMC_PCDR1_PID56_Msk & ((value) << PMC_PCDR1_PID56_Pos)) +#define PMC_PCDR1_PID57_Pos _U_(25) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Position */ +#define PMC_PCDR1_PID57_Msk (_U_(0x1) << PMC_PCDR1_PID57_Pos) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Mask */ +#define PMC_PCDR1_PID57(value) (PMC_PCDR1_PID57_Msk & ((value) << PMC_PCDR1_PID57_Pos)) +#define PMC_PCDR1_PID58_Pos _U_(26) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Position */ +#define PMC_PCDR1_PID58_Msk (_U_(0x1) << PMC_PCDR1_PID58_Pos) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Mask */ +#define PMC_PCDR1_PID58(value) (PMC_PCDR1_PID58_Msk & ((value) << PMC_PCDR1_PID58_Pos)) +#define PMC_PCDR1_PID59_Pos _U_(27) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Position */ +#define PMC_PCDR1_PID59_Msk (_U_(0x1) << PMC_PCDR1_PID59_Pos) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Mask */ +#define PMC_PCDR1_PID59(value) (PMC_PCDR1_PID59_Msk & ((value) << PMC_PCDR1_PID59_Pos)) +#define PMC_PCDR1_PID60_Pos _U_(28) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Position */ +#define PMC_PCDR1_PID60_Msk (_U_(0x1) << PMC_PCDR1_PID60_Pos) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Mask */ +#define PMC_PCDR1_PID60(value) (PMC_PCDR1_PID60_Msk & ((value) << PMC_PCDR1_PID60_Pos)) +#define PMC_PCDR1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCDR1) Register Mask */ + +#define PMC_PCDR1_PID_Pos _U_(0) /**< (PMC_PCDR1 Position) Peripheral Clock 6x Disable */ +#define PMC_PCDR1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR1_PID_Pos) /**< (PMC_PCDR1 Mask) PID */ +#define PMC_PCDR1_PID(value) (PMC_PCDR1_PID_Msk & ((value) << PMC_PCDR1_PID_Pos)) + +/* -------- PMC_PCSR1 : (PMC Offset: 0x108) ( R/ 32) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32_Pos _U_(0) /**< (PMC_PCSR1) Peripheral Clock 32 Status Position */ +#define PMC_PCSR1_PID32_Msk (_U_(0x1) << PMC_PCSR1_PID32_Pos) /**< (PMC_PCSR1) Peripheral Clock 32 Status Mask */ +#define PMC_PCSR1_PID32(value) (PMC_PCSR1_PID32_Msk & ((value) << PMC_PCSR1_PID32_Pos)) +#define PMC_PCSR1_PID33_Pos _U_(1) /**< (PMC_PCSR1) Peripheral Clock 33 Status Position */ +#define PMC_PCSR1_PID33_Msk (_U_(0x1) << PMC_PCSR1_PID33_Pos) /**< (PMC_PCSR1) Peripheral Clock 33 Status Mask */ +#define PMC_PCSR1_PID33(value) (PMC_PCSR1_PID33_Msk & ((value) << PMC_PCSR1_PID33_Pos)) +#define PMC_PCSR1_PID34_Pos _U_(2) /**< (PMC_PCSR1) Peripheral Clock 34 Status Position */ +#define PMC_PCSR1_PID34_Msk (_U_(0x1) << PMC_PCSR1_PID34_Pos) /**< (PMC_PCSR1) Peripheral Clock 34 Status Mask */ +#define PMC_PCSR1_PID34(value) (PMC_PCSR1_PID34_Msk & ((value) << PMC_PCSR1_PID34_Pos)) +#define PMC_PCSR1_PID35_Pos _U_(3) /**< (PMC_PCSR1) Peripheral Clock 35 Status Position */ +#define PMC_PCSR1_PID35_Msk (_U_(0x1) << PMC_PCSR1_PID35_Pos) /**< (PMC_PCSR1) Peripheral Clock 35 Status Mask */ +#define PMC_PCSR1_PID35(value) (PMC_PCSR1_PID35_Msk & ((value) << PMC_PCSR1_PID35_Pos)) +#define PMC_PCSR1_PID37_Pos _U_(5) /**< (PMC_PCSR1) Peripheral Clock 37 Status Position */ +#define PMC_PCSR1_PID37_Msk (_U_(0x1) << PMC_PCSR1_PID37_Pos) /**< (PMC_PCSR1) Peripheral Clock 37 Status Mask */ +#define PMC_PCSR1_PID37(value) (PMC_PCSR1_PID37_Msk & ((value) << PMC_PCSR1_PID37_Pos)) +#define PMC_PCSR1_PID39_Pos _U_(7) /**< (PMC_PCSR1) Peripheral Clock 39 Status Position */ +#define PMC_PCSR1_PID39_Msk (_U_(0x1) << PMC_PCSR1_PID39_Pos) /**< (PMC_PCSR1) Peripheral Clock 39 Status Mask */ +#define PMC_PCSR1_PID39(value) (PMC_PCSR1_PID39_Msk & ((value) << PMC_PCSR1_PID39_Pos)) +#define PMC_PCSR1_PID40_Pos _U_(8) /**< (PMC_PCSR1) Peripheral Clock 40 Status Position */ +#define PMC_PCSR1_PID40_Msk (_U_(0x1) << PMC_PCSR1_PID40_Pos) /**< (PMC_PCSR1) Peripheral Clock 40 Status Mask */ +#define PMC_PCSR1_PID40(value) (PMC_PCSR1_PID40_Msk & ((value) << PMC_PCSR1_PID40_Pos)) +#define PMC_PCSR1_PID41_Pos _U_(9) /**< (PMC_PCSR1) Peripheral Clock 41 Status Position */ +#define PMC_PCSR1_PID41_Msk (_U_(0x1) << PMC_PCSR1_PID41_Pos) /**< (PMC_PCSR1) Peripheral Clock 41 Status Mask */ +#define PMC_PCSR1_PID41(value) (PMC_PCSR1_PID41_Msk & ((value) << PMC_PCSR1_PID41_Pos)) +#define PMC_PCSR1_PID42_Pos _U_(10) /**< (PMC_PCSR1) Peripheral Clock 42 Status Position */ +#define PMC_PCSR1_PID42_Msk (_U_(0x1) << PMC_PCSR1_PID42_Pos) /**< (PMC_PCSR1) Peripheral Clock 42 Status Mask */ +#define PMC_PCSR1_PID42(value) (PMC_PCSR1_PID42_Msk & ((value) << PMC_PCSR1_PID42_Pos)) +#define PMC_PCSR1_PID43_Pos _U_(11) /**< (PMC_PCSR1) Peripheral Clock 43 Status Position */ +#define PMC_PCSR1_PID43_Msk (_U_(0x1) << PMC_PCSR1_PID43_Pos) /**< (PMC_PCSR1) Peripheral Clock 43 Status Mask */ +#define PMC_PCSR1_PID43(value) (PMC_PCSR1_PID43_Msk & ((value) << PMC_PCSR1_PID43_Pos)) +#define PMC_PCSR1_PID44_Pos _U_(12) /**< (PMC_PCSR1) Peripheral Clock 44 Status Position */ +#define PMC_PCSR1_PID44_Msk (_U_(0x1) << PMC_PCSR1_PID44_Pos) /**< (PMC_PCSR1) Peripheral Clock 44 Status Mask */ +#define PMC_PCSR1_PID44(value) (PMC_PCSR1_PID44_Msk & ((value) << PMC_PCSR1_PID44_Pos)) +#define PMC_PCSR1_PID45_Pos _U_(13) /**< (PMC_PCSR1) Peripheral Clock 45 Status Position */ +#define PMC_PCSR1_PID45_Msk (_U_(0x1) << PMC_PCSR1_PID45_Pos) /**< (PMC_PCSR1) Peripheral Clock 45 Status Mask */ +#define PMC_PCSR1_PID45(value) (PMC_PCSR1_PID45_Msk & ((value) << PMC_PCSR1_PID45_Pos)) +#define PMC_PCSR1_PID46_Pos _U_(14) /**< (PMC_PCSR1) Peripheral Clock 46 Status Position */ +#define PMC_PCSR1_PID46_Msk (_U_(0x1) << PMC_PCSR1_PID46_Pos) /**< (PMC_PCSR1) Peripheral Clock 46 Status Mask */ +#define PMC_PCSR1_PID46(value) (PMC_PCSR1_PID46_Msk & ((value) << PMC_PCSR1_PID46_Pos)) +#define PMC_PCSR1_PID47_Pos _U_(15) /**< (PMC_PCSR1) Peripheral Clock 47 Status Position */ +#define PMC_PCSR1_PID47_Msk (_U_(0x1) << PMC_PCSR1_PID47_Pos) /**< (PMC_PCSR1) Peripheral Clock 47 Status Mask */ +#define PMC_PCSR1_PID47(value) (PMC_PCSR1_PID47_Msk & ((value) << PMC_PCSR1_PID47_Pos)) +#define PMC_PCSR1_PID48_Pos _U_(16) /**< (PMC_PCSR1) Peripheral Clock 48 Status Position */ +#define PMC_PCSR1_PID48_Msk (_U_(0x1) << PMC_PCSR1_PID48_Pos) /**< (PMC_PCSR1) Peripheral Clock 48 Status Mask */ +#define PMC_PCSR1_PID48(value) (PMC_PCSR1_PID48_Msk & ((value) << PMC_PCSR1_PID48_Pos)) +#define PMC_PCSR1_PID49_Pos _U_(17) /**< (PMC_PCSR1) Peripheral Clock 49 Status Position */ +#define PMC_PCSR1_PID49_Msk (_U_(0x1) << PMC_PCSR1_PID49_Pos) /**< (PMC_PCSR1) Peripheral Clock 49 Status Mask */ +#define PMC_PCSR1_PID49(value) (PMC_PCSR1_PID49_Msk & ((value) << PMC_PCSR1_PID49_Pos)) +#define PMC_PCSR1_PID50_Pos _U_(18) /**< (PMC_PCSR1) Peripheral Clock 50 Status Position */ +#define PMC_PCSR1_PID50_Msk (_U_(0x1) << PMC_PCSR1_PID50_Pos) /**< (PMC_PCSR1) Peripheral Clock 50 Status Mask */ +#define PMC_PCSR1_PID50(value) (PMC_PCSR1_PID50_Msk & ((value) << PMC_PCSR1_PID50_Pos)) +#define PMC_PCSR1_PID51_Pos _U_(19) /**< (PMC_PCSR1) Peripheral Clock 51 Status Position */ +#define PMC_PCSR1_PID51_Msk (_U_(0x1) << PMC_PCSR1_PID51_Pos) /**< (PMC_PCSR1) Peripheral Clock 51 Status Mask */ +#define PMC_PCSR1_PID51(value) (PMC_PCSR1_PID51_Msk & ((value) << PMC_PCSR1_PID51_Pos)) +#define PMC_PCSR1_PID52_Pos _U_(20) /**< (PMC_PCSR1) Peripheral Clock 52 Status Position */ +#define PMC_PCSR1_PID52_Msk (_U_(0x1) << PMC_PCSR1_PID52_Pos) /**< (PMC_PCSR1) Peripheral Clock 52 Status Mask */ +#define PMC_PCSR1_PID52(value) (PMC_PCSR1_PID52_Msk & ((value) << PMC_PCSR1_PID52_Pos)) +#define PMC_PCSR1_PID53_Pos _U_(21) /**< (PMC_PCSR1) Peripheral Clock 53 Status Position */ +#define PMC_PCSR1_PID53_Msk (_U_(0x1) << PMC_PCSR1_PID53_Pos) /**< (PMC_PCSR1) Peripheral Clock 53 Status Mask */ +#define PMC_PCSR1_PID53(value) (PMC_PCSR1_PID53_Msk & ((value) << PMC_PCSR1_PID53_Pos)) +#define PMC_PCSR1_PID56_Pos _U_(24) /**< (PMC_PCSR1) Peripheral Clock 56 Status Position */ +#define PMC_PCSR1_PID56_Msk (_U_(0x1) << PMC_PCSR1_PID56_Pos) /**< (PMC_PCSR1) Peripheral Clock 56 Status Mask */ +#define PMC_PCSR1_PID56(value) (PMC_PCSR1_PID56_Msk & ((value) << PMC_PCSR1_PID56_Pos)) +#define PMC_PCSR1_PID57_Pos _U_(25) /**< (PMC_PCSR1) Peripheral Clock 57 Status Position */ +#define PMC_PCSR1_PID57_Msk (_U_(0x1) << PMC_PCSR1_PID57_Pos) /**< (PMC_PCSR1) Peripheral Clock 57 Status Mask */ +#define PMC_PCSR1_PID57(value) (PMC_PCSR1_PID57_Msk & ((value) << PMC_PCSR1_PID57_Pos)) +#define PMC_PCSR1_PID58_Pos _U_(26) /**< (PMC_PCSR1) Peripheral Clock 58 Status Position */ +#define PMC_PCSR1_PID58_Msk (_U_(0x1) << PMC_PCSR1_PID58_Pos) /**< (PMC_PCSR1) Peripheral Clock 58 Status Mask */ +#define PMC_PCSR1_PID58(value) (PMC_PCSR1_PID58_Msk & ((value) << PMC_PCSR1_PID58_Pos)) +#define PMC_PCSR1_PID59_Pos _U_(27) /**< (PMC_PCSR1) Peripheral Clock 59 Status Position */ +#define PMC_PCSR1_PID59_Msk (_U_(0x1) << PMC_PCSR1_PID59_Pos) /**< (PMC_PCSR1) Peripheral Clock 59 Status Mask */ +#define PMC_PCSR1_PID59(value) (PMC_PCSR1_PID59_Msk & ((value) << PMC_PCSR1_PID59_Pos)) +#define PMC_PCSR1_PID60_Pos _U_(28) /**< (PMC_PCSR1) Peripheral Clock 60 Status Position */ +#define PMC_PCSR1_PID60_Msk (_U_(0x1) << PMC_PCSR1_PID60_Pos) /**< (PMC_PCSR1) Peripheral Clock 60 Status Mask */ +#define PMC_PCSR1_PID60(value) (PMC_PCSR1_PID60_Msk & ((value) << PMC_PCSR1_PID60_Pos)) +#define PMC_PCSR1_Msk _U_(0x1F3FFFAF) /**< (PMC_PCSR1) Register Mask */ + +#define PMC_PCSR1_PID_Pos _U_(0) /**< (PMC_PCSR1 Position) Peripheral Clock 6x Status */ +#define PMC_PCSR1_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR1_PID_Pos) /**< (PMC_PCSR1 Mask) PID */ +#define PMC_PCSR1_PID(value) (PMC_PCSR1_PID_Msk & ((value) << PMC_PCSR1_PID_Pos)) + +/* -------- PMC_PCR : (PMC Offset: 0x10C) (R/W 32) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos _U_(0) /**< (PMC_PCR) Peripheral ID Position */ +#define PMC_PCR_PID_Msk (_U_(0x7F) << PMC_PCR_PID_Pos) /**< (PMC_PCR) Peripheral ID Mask */ +#define PMC_PCR_PID(value) (PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)) +#define PMC_PCR_GCLKCSS_Pos _U_(8) /**< (PMC_PCR) Generic Clock Source Selection Position */ +#define PMC_PCR_GCLKCSS_Msk (_U_(0x7) << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Generic Clock Source Selection Mask */ +#define PMC_PCR_GCLKCSS(value) (PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)) +#define PMC_PCR_GCLKCSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCR) Slow clock is selected */ +#define PMC_PCR_GCLKCSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCR) Main clock is selected */ +#define PMC_PCR_GCLKCSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCR) PLLACK is selected */ +#define PMC_PCR_GCLKCSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCR) UPLL Clock is selected */ +#define PMC_PCR_GCLKCSS_MCK_CLK_Val _U_(0x4) /**< (PMC_PCR) Master Clock is selected */ +#define PMC_PCR_GCLKCSS_SLOW_CLK (PMC_PCR_GCLKCSS_SLOW_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Slow clock is selected Position */ +#define PMC_PCR_GCLKCSS_MAIN_CLK (PMC_PCR_GCLKCSS_MAIN_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Main clock is selected Position */ +#define PMC_PCR_GCLKCSS_PLLA_CLK (PMC_PCR_GCLKCSS_PLLA_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) PLLACK is selected Position */ +#define PMC_PCR_GCLKCSS_UPLL_CLK (PMC_PCR_GCLKCSS_UPLL_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) UPLL Clock is selected Position */ +#define PMC_PCR_GCLKCSS_MCK_CLK (PMC_PCR_GCLKCSS_MCK_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Master Clock is selected Position */ +#define PMC_PCR_CMD_Pos _U_(12) /**< (PMC_PCR) Command Position */ +#define PMC_PCR_CMD_Msk (_U_(0x1) << PMC_PCR_CMD_Pos) /**< (PMC_PCR) Command Mask */ +#define PMC_PCR_CMD(value) (PMC_PCR_CMD_Msk & ((value) << PMC_PCR_CMD_Pos)) +#define PMC_PCR_GCLKDIV_Pos _U_(20) /**< (PMC_PCR) Generic Clock Division Ratio Position */ +#define PMC_PCR_GCLKDIV_Msk (_U_(0xFF) << PMC_PCR_GCLKDIV_Pos) /**< (PMC_PCR) Generic Clock Division Ratio Mask */ +#define PMC_PCR_GCLKDIV(value) (PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)) +#define PMC_PCR_EN_Pos _U_(28) /**< (PMC_PCR) Enable Position */ +#define PMC_PCR_EN_Msk (_U_(0x1) << PMC_PCR_EN_Pos) /**< (PMC_PCR) Enable Mask */ +#define PMC_PCR_EN(value) (PMC_PCR_EN_Msk & ((value) << PMC_PCR_EN_Pos)) +#define PMC_PCR_GCLKEN_Pos _U_(29) /**< (PMC_PCR) Generic Clock Enable Position */ +#define PMC_PCR_GCLKEN_Msk (_U_(0x1) << PMC_PCR_GCLKEN_Pos) /**< (PMC_PCR) Generic Clock Enable Mask */ +#define PMC_PCR_GCLKEN(value) (PMC_PCR_GCLKEN_Msk & ((value) << PMC_PCR_GCLKEN_Pos)) +#define PMC_PCR_Msk _U_(0x3FF0177F) /**< (PMC_PCR) Register Mask */ + + +/* -------- PMC_OCR : (PMC Offset: 0x110) (R/W 32) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos _U_(0) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_CAL4_Msk (_U_(0x7F) << PMC_OCR_CAL4_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)) +#define PMC_OCR_SEL4_Pos _U_(7) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_SEL4_Msk (_U_(0x1) << PMC_OCR_SEL4_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_SEL4(value) (PMC_OCR_SEL4_Msk & ((value) << PMC_OCR_SEL4_Pos)) +#define PMC_OCR_CAL8_Pos _U_(8) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_CAL8_Msk (_U_(0x7F) << PMC_OCR_CAL8_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_CAL8(value) (PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)) +#define PMC_OCR_SEL8_Pos _U_(15) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_SEL8_Msk (_U_(0x1) << PMC_OCR_SEL8_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_SEL8(value) (PMC_OCR_SEL8_Msk & ((value) << PMC_OCR_SEL8_Pos)) +#define PMC_OCR_CAL12_Pos _U_(16) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_CAL12_Msk (_U_(0x7F) << PMC_OCR_CAL12_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_CAL12(value) (PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)) +#define PMC_OCR_SEL12_Pos _U_(23) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_SEL12_Msk (_U_(0x1) << PMC_OCR_SEL12_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_SEL12(value) (PMC_OCR_SEL12_Msk & ((value) << PMC_OCR_SEL12_Pos)) +#define PMC_OCR_Msk _U_(0x00FFFFFF) /**< (PMC_OCR) Register Mask */ + + +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) ( /W 32) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7_Pos _U_(7) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID7_Pos) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID7(value) (PMC_SLPWK_ER0_PID7_Msk & ((value) << PMC_SLPWK_ER0_PID7_Pos)) +#define PMC_SLPWK_ER0_PID8_Pos _U_(8) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID8_Pos) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID8(value) (PMC_SLPWK_ER0_PID8_Msk & ((value) << PMC_SLPWK_ER0_PID8_Pos)) +#define PMC_SLPWK_ER0_PID9_Pos _U_(9) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID9_Pos) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID9(value) (PMC_SLPWK_ER0_PID9_Msk & ((value) << PMC_SLPWK_ER0_PID9_Pos)) +#define PMC_SLPWK_ER0_PID10_Pos _U_(10) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID10_Pos) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID10(value) (PMC_SLPWK_ER0_PID10_Msk & ((value) << PMC_SLPWK_ER0_PID10_Pos)) +#define PMC_SLPWK_ER0_PID11_Pos _U_(11) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID11_Pos) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID11(value) (PMC_SLPWK_ER0_PID11_Msk & ((value) << PMC_SLPWK_ER0_PID11_Pos)) +#define PMC_SLPWK_ER0_PID12_Pos _U_(12) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID12_Pos) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID12(value) (PMC_SLPWK_ER0_PID12_Msk & ((value) << PMC_SLPWK_ER0_PID12_Pos)) +#define PMC_SLPWK_ER0_PID13_Pos _U_(13) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID13_Pos) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID13(value) (PMC_SLPWK_ER0_PID13_Msk & ((value) << PMC_SLPWK_ER0_PID13_Pos)) +#define PMC_SLPWK_ER0_PID14_Pos _U_(14) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID14_Pos) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID14(value) (PMC_SLPWK_ER0_PID14_Msk & ((value) << PMC_SLPWK_ER0_PID14_Pos)) +#define PMC_SLPWK_ER0_PID15_Pos _U_(15) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID15_Pos) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID15(value) (PMC_SLPWK_ER0_PID15_Msk & ((value) << PMC_SLPWK_ER0_PID15_Pos)) +#define PMC_SLPWK_ER0_PID16_Pos _U_(16) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID16_Pos) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID16(value) (PMC_SLPWK_ER0_PID16_Msk & ((value) << PMC_SLPWK_ER0_PID16_Pos)) +#define PMC_SLPWK_ER0_PID17_Pos _U_(17) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID17_Pos) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID17(value) (PMC_SLPWK_ER0_PID17_Msk & ((value) << PMC_SLPWK_ER0_PID17_Pos)) +#define PMC_SLPWK_ER0_PID18_Pos _U_(18) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID18_Pos) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID18(value) (PMC_SLPWK_ER0_PID18_Msk & ((value) << PMC_SLPWK_ER0_PID18_Pos)) +#define PMC_SLPWK_ER0_PID19_Pos _U_(19) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID19_Pos) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID19(value) (PMC_SLPWK_ER0_PID19_Msk & ((value) << PMC_SLPWK_ER0_PID19_Pos)) +#define PMC_SLPWK_ER0_PID20_Pos _U_(20) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID20_Pos) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID20(value) (PMC_SLPWK_ER0_PID20_Msk & ((value) << PMC_SLPWK_ER0_PID20_Pos)) +#define PMC_SLPWK_ER0_PID21_Pos _U_(21) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID21_Pos) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID21(value) (PMC_SLPWK_ER0_PID21_Msk & ((value) << PMC_SLPWK_ER0_PID21_Pos)) +#define PMC_SLPWK_ER0_PID22_Pos _U_(22) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID22_Pos) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID22(value) (PMC_SLPWK_ER0_PID22_Msk & ((value) << PMC_SLPWK_ER0_PID22_Pos)) +#define PMC_SLPWK_ER0_PID23_Pos _U_(23) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID23_Pos) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID23(value) (PMC_SLPWK_ER0_PID23_Msk & ((value) << PMC_SLPWK_ER0_PID23_Pos)) +#define PMC_SLPWK_ER0_PID24_Pos _U_(24) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID24_Pos) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID24(value) (PMC_SLPWK_ER0_PID24_Msk & ((value) << PMC_SLPWK_ER0_PID24_Pos)) +#define PMC_SLPWK_ER0_PID25_Pos _U_(25) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID25_Pos) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID25(value) (PMC_SLPWK_ER0_PID25_Msk & ((value) << PMC_SLPWK_ER0_PID25_Pos)) +#define PMC_SLPWK_ER0_PID26_Pos _U_(26) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID26_Pos) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID26(value) (PMC_SLPWK_ER0_PID26_Msk & ((value) << PMC_SLPWK_ER0_PID26_Pos)) +#define PMC_SLPWK_ER0_PID27_Pos _U_(27) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID27_Pos) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID27(value) (PMC_SLPWK_ER0_PID27_Msk & ((value) << PMC_SLPWK_ER0_PID27_Pos)) +#define PMC_SLPWK_ER0_PID28_Pos _U_(28) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID28_Pos) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID28(value) (PMC_SLPWK_ER0_PID28_Msk & ((value) << PMC_SLPWK_ER0_PID28_Pos)) +#define PMC_SLPWK_ER0_PID29_Pos _U_(29) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID29_Pos) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID29(value) (PMC_SLPWK_ER0_PID29_Msk & ((value) << PMC_SLPWK_ER0_PID29_Pos)) +#define PMC_SLPWK_ER0_PID30_Pos _U_(30) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID30_Pos) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID30(value) (PMC_SLPWK_ER0_PID30_Msk & ((value) << PMC_SLPWK_ER0_PID30_Pos)) +#define PMC_SLPWK_ER0_PID31_Pos _U_(31) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID31_Pos) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID31(value) (PMC_SLPWK_ER0_PID31_Msk & ((value) << PMC_SLPWK_ER0_PID31_Pos)) +#define PMC_SLPWK_ER0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ER0) Register Mask */ + +#define PMC_SLPWK_ER0_PID_Pos _U_(7) /**< (PMC_SLPWK_ER0 Position) Peripheral 3x SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER0_PID_Pos) /**< (PMC_SLPWK_ER0 Mask) PID */ +#define PMC_SLPWK_ER0_PID(value) (PMC_SLPWK_ER0_PID_Msk & ((value) << PMC_SLPWK_ER0_PID_Pos)) + +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) ( /W 32) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID7_Pos) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID7(value) (PMC_SLPWK_DR0_PID7_Msk & ((value) << PMC_SLPWK_DR0_PID7_Pos)) +#define PMC_SLPWK_DR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID8_Pos) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID8(value) (PMC_SLPWK_DR0_PID8_Msk & ((value) << PMC_SLPWK_DR0_PID8_Pos)) +#define PMC_SLPWK_DR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID9_Pos) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID9(value) (PMC_SLPWK_DR0_PID9_Msk & ((value) << PMC_SLPWK_DR0_PID9_Pos)) +#define PMC_SLPWK_DR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID10_Pos) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID10(value) (PMC_SLPWK_DR0_PID10_Msk & ((value) << PMC_SLPWK_DR0_PID10_Pos)) +#define PMC_SLPWK_DR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID11_Pos) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID11(value) (PMC_SLPWK_DR0_PID11_Msk & ((value) << PMC_SLPWK_DR0_PID11_Pos)) +#define PMC_SLPWK_DR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID12_Pos) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID12(value) (PMC_SLPWK_DR0_PID12_Msk & ((value) << PMC_SLPWK_DR0_PID12_Pos)) +#define PMC_SLPWK_DR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID13_Pos) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID13(value) (PMC_SLPWK_DR0_PID13_Msk & ((value) << PMC_SLPWK_DR0_PID13_Pos)) +#define PMC_SLPWK_DR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID14_Pos) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID14(value) (PMC_SLPWK_DR0_PID14_Msk & ((value) << PMC_SLPWK_DR0_PID14_Pos)) +#define PMC_SLPWK_DR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID15_Pos) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID15(value) (PMC_SLPWK_DR0_PID15_Msk & ((value) << PMC_SLPWK_DR0_PID15_Pos)) +#define PMC_SLPWK_DR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID16_Pos) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID16(value) (PMC_SLPWK_DR0_PID16_Msk & ((value) << PMC_SLPWK_DR0_PID16_Pos)) +#define PMC_SLPWK_DR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID17_Pos) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID17(value) (PMC_SLPWK_DR0_PID17_Msk & ((value) << PMC_SLPWK_DR0_PID17_Pos)) +#define PMC_SLPWK_DR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID18_Pos) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID18(value) (PMC_SLPWK_DR0_PID18_Msk & ((value) << PMC_SLPWK_DR0_PID18_Pos)) +#define PMC_SLPWK_DR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID19_Pos) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID19(value) (PMC_SLPWK_DR0_PID19_Msk & ((value) << PMC_SLPWK_DR0_PID19_Pos)) +#define PMC_SLPWK_DR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID20_Pos) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID20(value) (PMC_SLPWK_DR0_PID20_Msk & ((value) << PMC_SLPWK_DR0_PID20_Pos)) +#define PMC_SLPWK_DR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID21_Pos) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID21(value) (PMC_SLPWK_DR0_PID21_Msk & ((value) << PMC_SLPWK_DR0_PID21_Pos)) +#define PMC_SLPWK_DR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID22_Pos) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID22(value) (PMC_SLPWK_DR0_PID22_Msk & ((value) << PMC_SLPWK_DR0_PID22_Pos)) +#define PMC_SLPWK_DR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID23_Pos) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID23(value) (PMC_SLPWK_DR0_PID23_Msk & ((value) << PMC_SLPWK_DR0_PID23_Pos)) +#define PMC_SLPWK_DR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID24_Pos) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID24(value) (PMC_SLPWK_DR0_PID24_Msk & ((value) << PMC_SLPWK_DR0_PID24_Pos)) +#define PMC_SLPWK_DR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID25_Pos) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID25(value) (PMC_SLPWK_DR0_PID25_Msk & ((value) << PMC_SLPWK_DR0_PID25_Pos)) +#define PMC_SLPWK_DR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID26_Pos) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID26(value) (PMC_SLPWK_DR0_PID26_Msk & ((value) << PMC_SLPWK_DR0_PID26_Pos)) +#define PMC_SLPWK_DR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID27_Pos) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID27(value) (PMC_SLPWK_DR0_PID27_Msk & ((value) << PMC_SLPWK_DR0_PID27_Pos)) +#define PMC_SLPWK_DR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID28_Pos) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID28(value) (PMC_SLPWK_DR0_PID28_Msk & ((value) << PMC_SLPWK_DR0_PID28_Pos)) +#define PMC_SLPWK_DR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID29_Pos) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID29(value) (PMC_SLPWK_DR0_PID29_Msk & ((value) << PMC_SLPWK_DR0_PID29_Pos)) +#define PMC_SLPWK_DR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID30_Pos) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID30(value) (PMC_SLPWK_DR0_PID30_Msk & ((value) << PMC_SLPWK_DR0_PID30_Pos)) +#define PMC_SLPWK_DR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID31_Pos) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID31(value) (PMC_SLPWK_DR0_PID31_Msk & ((value) << PMC_SLPWK_DR0_PID31_Pos)) +#define PMC_SLPWK_DR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_DR0) Register Mask */ + +#define PMC_SLPWK_DR0_PID_Pos _U_(7) /**< (PMC_SLPWK_DR0 Position) Peripheral 3x SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR0_PID_Pos) /**< (PMC_SLPWK_DR0 Mask) PID */ +#define PMC_SLPWK_DR0_PID(value) (PMC_SLPWK_DR0_PID_Msk & ((value) << PMC_SLPWK_DR0_PID_Pos)) + +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11C) ( R/ 32) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID7_Pos) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID7(value) (PMC_SLPWK_SR0_PID7_Msk & ((value) << PMC_SLPWK_SR0_PID7_Pos)) +#define PMC_SLPWK_SR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID8_Pos) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID8(value) (PMC_SLPWK_SR0_PID8_Msk & ((value) << PMC_SLPWK_SR0_PID8_Pos)) +#define PMC_SLPWK_SR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID9_Pos) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID9(value) (PMC_SLPWK_SR0_PID9_Msk & ((value) << PMC_SLPWK_SR0_PID9_Pos)) +#define PMC_SLPWK_SR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID10_Pos) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID10(value) (PMC_SLPWK_SR0_PID10_Msk & ((value) << PMC_SLPWK_SR0_PID10_Pos)) +#define PMC_SLPWK_SR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID11_Pos) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID11(value) (PMC_SLPWK_SR0_PID11_Msk & ((value) << PMC_SLPWK_SR0_PID11_Pos)) +#define PMC_SLPWK_SR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID12_Pos) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID12(value) (PMC_SLPWK_SR0_PID12_Msk & ((value) << PMC_SLPWK_SR0_PID12_Pos)) +#define PMC_SLPWK_SR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID13_Pos) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID13(value) (PMC_SLPWK_SR0_PID13_Msk & ((value) << PMC_SLPWK_SR0_PID13_Pos)) +#define PMC_SLPWK_SR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID14_Pos) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID14(value) (PMC_SLPWK_SR0_PID14_Msk & ((value) << PMC_SLPWK_SR0_PID14_Pos)) +#define PMC_SLPWK_SR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID15_Pos) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID15(value) (PMC_SLPWK_SR0_PID15_Msk & ((value) << PMC_SLPWK_SR0_PID15_Pos)) +#define PMC_SLPWK_SR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID16_Pos) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID16(value) (PMC_SLPWK_SR0_PID16_Msk & ((value) << PMC_SLPWK_SR0_PID16_Pos)) +#define PMC_SLPWK_SR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID17_Pos) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID17(value) (PMC_SLPWK_SR0_PID17_Msk & ((value) << PMC_SLPWK_SR0_PID17_Pos)) +#define PMC_SLPWK_SR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID18_Pos) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID18(value) (PMC_SLPWK_SR0_PID18_Msk & ((value) << PMC_SLPWK_SR0_PID18_Pos)) +#define PMC_SLPWK_SR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID19_Pos) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID19(value) (PMC_SLPWK_SR0_PID19_Msk & ((value) << PMC_SLPWK_SR0_PID19_Pos)) +#define PMC_SLPWK_SR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID20_Pos) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID20(value) (PMC_SLPWK_SR0_PID20_Msk & ((value) << PMC_SLPWK_SR0_PID20_Pos)) +#define PMC_SLPWK_SR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID21_Pos) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID21(value) (PMC_SLPWK_SR0_PID21_Msk & ((value) << PMC_SLPWK_SR0_PID21_Pos)) +#define PMC_SLPWK_SR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID22_Pos) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID22(value) (PMC_SLPWK_SR0_PID22_Msk & ((value) << PMC_SLPWK_SR0_PID22_Pos)) +#define PMC_SLPWK_SR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID23_Pos) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID23(value) (PMC_SLPWK_SR0_PID23_Msk & ((value) << PMC_SLPWK_SR0_PID23_Pos)) +#define PMC_SLPWK_SR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID24_Pos) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID24(value) (PMC_SLPWK_SR0_PID24_Msk & ((value) << PMC_SLPWK_SR0_PID24_Pos)) +#define PMC_SLPWK_SR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID25_Pos) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID25(value) (PMC_SLPWK_SR0_PID25_Msk & ((value) << PMC_SLPWK_SR0_PID25_Pos)) +#define PMC_SLPWK_SR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID26_Pos) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID26(value) (PMC_SLPWK_SR0_PID26_Msk & ((value) << PMC_SLPWK_SR0_PID26_Pos)) +#define PMC_SLPWK_SR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID27_Pos) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID27(value) (PMC_SLPWK_SR0_PID27_Msk & ((value) << PMC_SLPWK_SR0_PID27_Pos)) +#define PMC_SLPWK_SR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID28_Pos) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID28(value) (PMC_SLPWK_SR0_PID28_Msk & ((value) << PMC_SLPWK_SR0_PID28_Pos)) +#define PMC_SLPWK_SR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID29_Pos) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID29(value) (PMC_SLPWK_SR0_PID29_Msk & ((value) << PMC_SLPWK_SR0_PID29_Pos)) +#define PMC_SLPWK_SR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID30_Pos) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID30(value) (PMC_SLPWK_SR0_PID30_Msk & ((value) << PMC_SLPWK_SR0_PID30_Pos)) +#define PMC_SLPWK_SR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID31_Pos) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID31(value) (PMC_SLPWK_SR0_PID31_Msk & ((value) << PMC_SLPWK_SR0_PID31_Pos)) +#define PMC_SLPWK_SR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_SR0) Register Mask */ + +#define PMC_SLPWK_SR0_PID_Pos _U_(7) /**< (PMC_SLPWK_SR0 Position) Peripheral 3x SleepWalking Status */ +#define PMC_SLPWK_SR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR0_PID_Pos) /**< (PMC_SLPWK_SR0 Mask) PID */ +#define PMC_SLPWK_SR0_PID(value) (PMC_SLPWK_SR0_PID_Msk & ((value) << PMC_SLPWK_SR0_PID_Pos)) + +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) ( R/ 32) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID7_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID7(value) (PMC_SLPWK_ASR0_PID7_Msk & ((value) << PMC_SLPWK_ASR0_PID7_Pos)) +#define PMC_SLPWK_ASR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID8_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID8(value) (PMC_SLPWK_ASR0_PID8_Msk & ((value) << PMC_SLPWK_ASR0_PID8_Pos)) +#define PMC_SLPWK_ASR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID9_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID9(value) (PMC_SLPWK_ASR0_PID9_Msk & ((value) << PMC_SLPWK_ASR0_PID9_Pos)) +#define PMC_SLPWK_ASR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID10_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID10(value) (PMC_SLPWK_ASR0_PID10_Msk & ((value) << PMC_SLPWK_ASR0_PID10_Pos)) +#define PMC_SLPWK_ASR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID11_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID11(value) (PMC_SLPWK_ASR0_PID11_Msk & ((value) << PMC_SLPWK_ASR0_PID11_Pos)) +#define PMC_SLPWK_ASR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID12_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID12(value) (PMC_SLPWK_ASR0_PID12_Msk & ((value) << PMC_SLPWK_ASR0_PID12_Pos)) +#define PMC_SLPWK_ASR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID13_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID13(value) (PMC_SLPWK_ASR0_PID13_Msk & ((value) << PMC_SLPWK_ASR0_PID13_Pos)) +#define PMC_SLPWK_ASR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID14_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID14(value) (PMC_SLPWK_ASR0_PID14_Msk & ((value) << PMC_SLPWK_ASR0_PID14_Pos)) +#define PMC_SLPWK_ASR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID15_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID15(value) (PMC_SLPWK_ASR0_PID15_Msk & ((value) << PMC_SLPWK_ASR0_PID15_Pos)) +#define PMC_SLPWK_ASR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID16_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID16(value) (PMC_SLPWK_ASR0_PID16_Msk & ((value) << PMC_SLPWK_ASR0_PID16_Pos)) +#define PMC_SLPWK_ASR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID17_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID17(value) (PMC_SLPWK_ASR0_PID17_Msk & ((value) << PMC_SLPWK_ASR0_PID17_Pos)) +#define PMC_SLPWK_ASR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID18_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID18(value) (PMC_SLPWK_ASR0_PID18_Msk & ((value) << PMC_SLPWK_ASR0_PID18_Pos)) +#define PMC_SLPWK_ASR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID19_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID19(value) (PMC_SLPWK_ASR0_PID19_Msk & ((value) << PMC_SLPWK_ASR0_PID19_Pos)) +#define PMC_SLPWK_ASR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID20_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID20(value) (PMC_SLPWK_ASR0_PID20_Msk & ((value) << PMC_SLPWK_ASR0_PID20_Pos)) +#define PMC_SLPWK_ASR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID21_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID21(value) (PMC_SLPWK_ASR0_PID21_Msk & ((value) << PMC_SLPWK_ASR0_PID21_Pos)) +#define PMC_SLPWK_ASR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID22_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID22(value) (PMC_SLPWK_ASR0_PID22_Msk & ((value) << PMC_SLPWK_ASR0_PID22_Pos)) +#define PMC_SLPWK_ASR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID23_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID23(value) (PMC_SLPWK_ASR0_PID23_Msk & ((value) << PMC_SLPWK_ASR0_PID23_Pos)) +#define PMC_SLPWK_ASR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID24_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID24(value) (PMC_SLPWK_ASR0_PID24_Msk & ((value) << PMC_SLPWK_ASR0_PID24_Pos)) +#define PMC_SLPWK_ASR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID25_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID25(value) (PMC_SLPWK_ASR0_PID25_Msk & ((value) << PMC_SLPWK_ASR0_PID25_Pos)) +#define PMC_SLPWK_ASR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID26_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID26(value) (PMC_SLPWK_ASR0_PID26_Msk & ((value) << PMC_SLPWK_ASR0_PID26_Pos)) +#define PMC_SLPWK_ASR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID27_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID27(value) (PMC_SLPWK_ASR0_PID27_Msk & ((value) << PMC_SLPWK_ASR0_PID27_Pos)) +#define PMC_SLPWK_ASR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID28_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID28(value) (PMC_SLPWK_ASR0_PID28_Msk & ((value) << PMC_SLPWK_ASR0_PID28_Pos)) +#define PMC_SLPWK_ASR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID29_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID29(value) (PMC_SLPWK_ASR0_PID29_Msk & ((value) << PMC_SLPWK_ASR0_PID29_Pos)) +#define PMC_SLPWK_ASR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID30_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID30(value) (PMC_SLPWK_ASR0_PID30_Msk & ((value) << PMC_SLPWK_ASR0_PID30_Pos)) +#define PMC_SLPWK_ASR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID31_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID31(value) (PMC_SLPWK_ASR0_PID31_Msk & ((value) << PMC_SLPWK_ASR0_PID31_Pos)) +#define PMC_SLPWK_ASR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ASR0) Register Mask */ + +#define PMC_SLPWK_ASR0_PID_Pos _U_(7) /**< (PMC_SLPWK_ASR0 Position) Peripheral 3x Activity Status */ +#define PMC_SLPWK_ASR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR0_PID_Pos) /**< (PMC_SLPWK_ASR0 Mask) PID */ +#define PMC_SLPWK_ASR0_PID(value) (PMC_SLPWK_ASR0_PID_Msk & ((value) << PMC_SLPWK_ASR0_PID_Pos)) + +/* -------- PMC_PMMR : (PMC Offset: 0x130) (R/W 32) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos _U_(0) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Position */ +#define PMC_PMMR_PLLA_MMAX_Msk (_U_(0x7FF) << PMC_PMMR_PLLA_MMAX_Pos) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Mask */ +#define PMC_PMMR_PLLA_MMAX(value) (PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)) +#define PMC_PMMR_Msk _U_(0x000007FF) /**< (PMC_PMMR) Register Mask */ + + +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x134) ( /W 32) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32_Pos _U_(0) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID32_Pos) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID32(value) (PMC_SLPWK_ER1_PID32_Msk & ((value) << PMC_SLPWK_ER1_PID32_Pos)) +#define PMC_SLPWK_ER1_PID33_Pos _U_(1) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID33_Pos) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID33(value) (PMC_SLPWK_ER1_PID33_Msk & ((value) << PMC_SLPWK_ER1_PID33_Pos)) +#define PMC_SLPWK_ER1_PID34_Pos _U_(2) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID34_Pos) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID34(value) (PMC_SLPWK_ER1_PID34_Msk & ((value) << PMC_SLPWK_ER1_PID34_Pos)) +#define PMC_SLPWK_ER1_PID35_Pos _U_(3) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID35_Pos) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID35(value) (PMC_SLPWK_ER1_PID35_Msk & ((value) << PMC_SLPWK_ER1_PID35_Pos)) +#define PMC_SLPWK_ER1_PID37_Pos _U_(5) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID37_Pos) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID37(value) (PMC_SLPWK_ER1_PID37_Msk & ((value) << PMC_SLPWK_ER1_PID37_Pos)) +#define PMC_SLPWK_ER1_PID39_Pos _U_(7) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID39_Pos) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID39(value) (PMC_SLPWK_ER1_PID39_Msk & ((value) << PMC_SLPWK_ER1_PID39_Pos)) +#define PMC_SLPWK_ER1_PID40_Pos _U_(8) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID40_Pos) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID40(value) (PMC_SLPWK_ER1_PID40_Msk & ((value) << PMC_SLPWK_ER1_PID40_Pos)) +#define PMC_SLPWK_ER1_PID41_Pos _U_(9) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID41_Pos) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID41(value) (PMC_SLPWK_ER1_PID41_Msk & ((value) << PMC_SLPWK_ER1_PID41_Pos)) +#define PMC_SLPWK_ER1_PID42_Pos _U_(10) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID42_Pos) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID42(value) (PMC_SLPWK_ER1_PID42_Msk & ((value) << PMC_SLPWK_ER1_PID42_Pos)) +#define PMC_SLPWK_ER1_PID43_Pos _U_(11) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID43_Pos) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID43(value) (PMC_SLPWK_ER1_PID43_Msk & ((value) << PMC_SLPWK_ER1_PID43_Pos)) +#define PMC_SLPWK_ER1_PID44_Pos _U_(12) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID44_Pos) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID44(value) (PMC_SLPWK_ER1_PID44_Msk & ((value) << PMC_SLPWK_ER1_PID44_Pos)) +#define PMC_SLPWK_ER1_PID45_Pos _U_(13) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID45_Pos) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID45(value) (PMC_SLPWK_ER1_PID45_Msk & ((value) << PMC_SLPWK_ER1_PID45_Pos)) +#define PMC_SLPWK_ER1_PID46_Pos _U_(14) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID46_Pos) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID46(value) (PMC_SLPWK_ER1_PID46_Msk & ((value) << PMC_SLPWK_ER1_PID46_Pos)) +#define PMC_SLPWK_ER1_PID47_Pos _U_(15) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID47_Pos) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID47(value) (PMC_SLPWK_ER1_PID47_Msk & ((value) << PMC_SLPWK_ER1_PID47_Pos)) +#define PMC_SLPWK_ER1_PID48_Pos _U_(16) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID48_Pos) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID48(value) (PMC_SLPWK_ER1_PID48_Msk & ((value) << PMC_SLPWK_ER1_PID48_Pos)) +#define PMC_SLPWK_ER1_PID49_Pos _U_(17) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID49_Pos) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID49(value) (PMC_SLPWK_ER1_PID49_Msk & ((value) << PMC_SLPWK_ER1_PID49_Pos)) +#define PMC_SLPWK_ER1_PID50_Pos _U_(18) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID50_Pos) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID50(value) (PMC_SLPWK_ER1_PID50_Msk & ((value) << PMC_SLPWK_ER1_PID50_Pos)) +#define PMC_SLPWK_ER1_PID51_Pos _U_(19) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID51_Pos) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID51(value) (PMC_SLPWK_ER1_PID51_Msk & ((value) << PMC_SLPWK_ER1_PID51_Pos)) +#define PMC_SLPWK_ER1_PID52_Pos _U_(20) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID52_Pos) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID52(value) (PMC_SLPWK_ER1_PID52_Msk & ((value) << PMC_SLPWK_ER1_PID52_Pos)) +#define PMC_SLPWK_ER1_PID53_Pos _U_(21) /**< (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID53_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID53_Pos) /**< (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID53(value) (PMC_SLPWK_ER1_PID53_Msk & ((value) << PMC_SLPWK_ER1_PID53_Pos)) +#define PMC_SLPWK_ER1_PID56_Pos _U_(24) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID56_Pos) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID56(value) (PMC_SLPWK_ER1_PID56_Msk & ((value) << PMC_SLPWK_ER1_PID56_Pos)) +#define PMC_SLPWK_ER1_PID57_Pos _U_(25) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID57_Pos) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID57(value) (PMC_SLPWK_ER1_PID57_Msk & ((value) << PMC_SLPWK_ER1_PID57_Pos)) +#define PMC_SLPWK_ER1_PID58_Pos _U_(26) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID58_Pos) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID58(value) (PMC_SLPWK_ER1_PID58_Msk & ((value) << PMC_SLPWK_ER1_PID58_Pos)) +#define PMC_SLPWK_ER1_PID59_Pos _U_(27) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID59_Pos) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID59(value) (PMC_SLPWK_ER1_PID59_Msk & ((value) << PMC_SLPWK_ER1_PID59_Pos)) +#define PMC_SLPWK_ER1_PID60_Pos _U_(28) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID60_Pos) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID60(value) (PMC_SLPWK_ER1_PID60_Msk & ((value) << PMC_SLPWK_ER1_PID60_Pos)) +#define PMC_SLPWK_ER1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_ER1) Register Mask */ + +#define PMC_SLPWK_ER1_PID_Pos _U_(0) /**< (PMC_SLPWK_ER1 Position) Peripheral 6x SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER1_PID_Pos) /**< (PMC_SLPWK_ER1 Mask) PID */ +#define PMC_SLPWK_ER1_PID(value) (PMC_SLPWK_ER1_PID_Msk & ((value) << PMC_SLPWK_ER1_PID_Pos)) + +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x138) ( /W 32) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID32_Pos) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID32(value) (PMC_SLPWK_DR1_PID32_Msk & ((value) << PMC_SLPWK_DR1_PID32_Pos)) +#define PMC_SLPWK_DR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID33_Pos) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID33(value) (PMC_SLPWK_DR1_PID33_Msk & ((value) << PMC_SLPWK_DR1_PID33_Pos)) +#define PMC_SLPWK_DR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID34_Pos) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID34(value) (PMC_SLPWK_DR1_PID34_Msk & ((value) << PMC_SLPWK_DR1_PID34_Pos)) +#define PMC_SLPWK_DR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID35_Pos) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID35(value) (PMC_SLPWK_DR1_PID35_Msk & ((value) << PMC_SLPWK_DR1_PID35_Pos)) +#define PMC_SLPWK_DR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID37_Pos) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID37(value) (PMC_SLPWK_DR1_PID37_Msk & ((value) << PMC_SLPWK_DR1_PID37_Pos)) +#define PMC_SLPWK_DR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID39_Pos) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID39(value) (PMC_SLPWK_DR1_PID39_Msk & ((value) << PMC_SLPWK_DR1_PID39_Pos)) +#define PMC_SLPWK_DR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID40_Pos) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID40(value) (PMC_SLPWK_DR1_PID40_Msk & ((value) << PMC_SLPWK_DR1_PID40_Pos)) +#define PMC_SLPWK_DR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID41_Pos) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID41(value) (PMC_SLPWK_DR1_PID41_Msk & ((value) << PMC_SLPWK_DR1_PID41_Pos)) +#define PMC_SLPWK_DR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID42_Pos) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID42(value) (PMC_SLPWK_DR1_PID42_Msk & ((value) << PMC_SLPWK_DR1_PID42_Pos)) +#define PMC_SLPWK_DR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID43_Pos) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID43(value) (PMC_SLPWK_DR1_PID43_Msk & ((value) << PMC_SLPWK_DR1_PID43_Pos)) +#define PMC_SLPWK_DR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID44_Pos) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID44(value) (PMC_SLPWK_DR1_PID44_Msk & ((value) << PMC_SLPWK_DR1_PID44_Pos)) +#define PMC_SLPWK_DR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID45_Pos) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID45(value) (PMC_SLPWK_DR1_PID45_Msk & ((value) << PMC_SLPWK_DR1_PID45_Pos)) +#define PMC_SLPWK_DR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID46_Pos) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID46(value) (PMC_SLPWK_DR1_PID46_Msk & ((value) << PMC_SLPWK_DR1_PID46_Pos)) +#define PMC_SLPWK_DR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID47_Pos) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID47(value) (PMC_SLPWK_DR1_PID47_Msk & ((value) << PMC_SLPWK_DR1_PID47_Pos)) +#define PMC_SLPWK_DR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID48_Pos) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID48(value) (PMC_SLPWK_DR1_PID48_Msk & ((value) << PMC_SLPWK_DR1_PID48_Pos)) +#define PMC_SLPWK_DR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID49_Pos) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID49(value) (PMC_SLPWK_DR1_PID49_Msk & ((value) << PMC_SLPWK_DR1_PID49_Pos)) +#define PMC_SLPWK_DR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID50_Pos) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID50(value) (PMC_SLPWK_DR1_PID50_Msk & ((value) << PMC_SLPWK_DR1_PID50_Pos)) +#define PMC_SLPWK_DR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID51_Pos) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID51(value) (PMC_SLPWK_DR1_PID51_Msk & ((value) << PMC_SLPWK_DR1_PID51_Pos)) +#define PMC_SLPWK_DR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID52_Pos) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID52(value) (PMC_SLPWK_DR1_PID52_Msk & ((value) << PMC_SLPWK_DR1_PID52_Pos)) +#define PMC_SLPWK_DR1_PID53_Pos _U_(21) /**< (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID53_Pos) /**< (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID53(value) (PMC_SLPWK_DR1_PID53_Msk & ((value) << PMC_SLPWK_DR1_PID53_Pos)) +#define PMC_SLPWK_DR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID56_Pos) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID56(value) (PMC_SLPWK_DR1_PID56_Msk & ((value) << PMC_SLPWK_DR1_PID56_Pos)) +#define PMC_SLPWK_DR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID57_Pos) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID57(value) (PMC_SLPWK_DR1_PID57_Msk & ((value) << PMC_SLPWK_DR1_PID57_Pos)) +#define PMC_SLPWK_DR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID58_Pos) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID58(value) (PMC_SLPWK_DR1_PID58_Msk & ((value) << PMC_SLPWK_DR1_PID58_Pos)) +#define PMC_SLPWK_DR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID59_Pos) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID59(value) (PMC_SLPWK_DR1_PID59_Msk & ((value) << PMC_SLPWK_DR1_PID59_Pos)) +#define PMC_SLPWK_DR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID60_Pos) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID60(value) (PMC_SLPWK_DR1_PID60_Msk & ((value) << PMC_SLPWK_DR1_PID60_Pos)) +#define PMC_SLPWK_DR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_DR1) Register Mask */ + +#define PMC_SLPWK_DR1_PID_Pos _U_(0) /**< (PMC_SLPWK_DR1 Position) Peripheral 6x SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR1_PID_Pos) /**< (PMC_SLPWK_DR1 Mask) PID */ +#define PMC_SLPWK_DR1_PID(value) (PMC_SLPWK_DR1_PID_Msk & ((value) << PMC_SLPWK_DR1_PID_Pos)) + +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x13C) ( R/ 32) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID32_Pos) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID32(value) (PMC_SLPWK_SR1_PID32_Msk & ((value) << PMC_SLPWK_SR1_PID32_Pos)) +#define PMC_SLPWK_SR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID33_Pos) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID33(value) (PMC_SLPWK_SR1_PID33_Msk & ((value) << PMC_SLPWK_SR1_PID33_Pos)) +#define PMC_SLPWK_SR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID34_Pos) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID34(value) (PMC_SLPWK_SR1_PID34_Msk & ((value) << PMC_SLPWK_SR1_PID34_Pos)) +#define PMC_SLPWK_SR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID35_Pos) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID35(value) (PMC_SLPWK_SR1_PID35_Msk & ((value) << PMC_SLPWK_SR1_PID35_Pos)) +#define PMC_SLPWK_SR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID37_Pos) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID37(value) (PMC_SLPWK_SR1_PID37_Msk & ((value) << PMC_SLPWK_SR1_PID37_Pos)) +#define PMC_SLPWK_SR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID39_Pos) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID39(value) (PMC_SLPWK_SR1_PID39_Msk & ((value) << PMC_SLPWK_SR1_PID39_Pos)) +#define PMC_SLPWK_SR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID40_Pos) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID40(value) (PMC_SLPWK_SR1_PID40_Msk & ((value) << PMC_SLPWK_SR1_PID40_Pos)) +#define PMC_SLPWK_SR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID41_Pos) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID41(value) (PMC_SLPWK_SR1_PID41_Msk & ((value) << PMC_SLPWK_SR1_PID41_Pos)) +#define PMC_SLPWK_SR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID42_Pos) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID42(value) (PMC_SLPWK_SR1_PID42_Msk & ((value) << PMC_SLPWK_SR1_PID42_Pos)) +#define PMC_SLPWK_SR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID43_Pos) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID43(value) (PMC_SLPWK_SR1_PID43_Msk & ((value) << PMC_SLPWK_SR1_PID43_Pos)) +#define PMC_SLPWK_SR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID44_Pos) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID44(value) (PMC_SLPWK_SR1_PID44_Msk & ((value) << PMC_SLPWK_SR1_PID44_Pos)) +#define PMC_SLPWK_SR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID45_Pos) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID45(value) (PMC_SLPWK_SR1_PID45_Msk & ((value) << PMC_SLPWK_SR1_PID45_Pos)) +#define PMC_SLPWK_SR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID46_Pos) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID46(value) (PMC_SLPWK_SR1_PID46_Msk & ((value) << PMC_SLPWK_SR1_PID46_Pos)) +#define PMC_SLPWK_SR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID47_Pos) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID47(value) (PMC_SLPWK_SR1_PID47_Msk & ((value) << PMC_SLPWK_SR1_PID47_Pos)) +#define PMC_SLPWK_SR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID48_Pos) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID48(value) (PMC_SLPWK_SR1_PID48_Msk & ((value) << PMC_SLPWK_SR1_PID48_Pos)) +#define PMC_SLPWK_SR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID49_Pos) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID49(value) (PMC_SLPWK_SR1_PID49_Msk & ((value) << PMC_SLPWK_SR1_PID49_Pos)) +#define PMC_SLPWK_SR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID50_Pos) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID50(value) (PMC_SLPWK_SR1_PID50_Msk & ((value) << PMC_SLPWK_SR1_PID50_Pos)) +#define PMC_SLPWK_SR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID51_Pos) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID51(value) (PMC_SLPWK_SR1_PID51_Msk & ((value) << PMC_SLPWK_SR1_PID51_Pos)) +#define PMC_SLPWK_SR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID52_Pos) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID52(value) (PMC_SLPWK_SR1_PID52_Msk & ((value) << PMC_SLPWK_SR1_PID52_Pos)) +#define PMC_SLPWK_SR1_PID53_Pos _U_(21) /**< (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID53_Pos) /**< (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID53(value) (PMC_SLPWK_SR1_PID53_Msk & ((value) << PMC_SLPWK_SR1_PID53_Pos)) +#define PMC_SLPWK_SR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID56_Pos) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID56(value) (PMC_SLPWK_SR1_PID56_Msk & ((value) << PMC_SLPWK_SR1_PID56_Pos)) +#define PMC_SLPWK_SR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID57_Pos) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID57(value) (PMC_SLPWK_SR1_PID57_Msk & ((value) << PMC_SLPWK_SR1_PID57_Pos)) +#define PMC_SLPWK_SR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID58_Pos) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID58(value) (PMC_SLPWK_SR1_PID58_Msk & ((value) << PMC_SLPWK_SR1_PID58_Pos)) +#define PMC_SLPWK_SR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID59_Pos) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID59(value) (PMC_SLPWK_SR1_PID59_Msk & ((value) << PMC_SLPWK_SR1_PID59_Pos)) +#define PMC_SLPWK_SR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID60_Pos) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID60(value) (PMC_SLPWK_SR1_PID60_Msk & ((value) << PMC_SLPWK_SR1_PID60_Pos)) +#define PMC_SLPWK_SR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_SR1) Register Mask */ + +#define PMC_SLPWK_SR1_PID_Pos _U_(0) /**< (PMC_SLPWK_SR1 Position) Peripheral 6x SleepWalking Status */ +#define PMC_SLPWK_SR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR1_PID_Pos) /**< (PMC_SLPWK_SR1 Mask) PID */ +#define PMC_SLPWK_SR1_PID(value) (PMC_SLPWK_SR1_PID_Msk & ((value) << PMC_SLPWK_SR1_PID_Pos)) + +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x140) ( R/ 32) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID32_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID32(value) (PMC_SLPWK_ASR1_PID32_Msk & ((value) << PMC_SLPWK_ASR1_PID32_Pos)) +#define PMC_SLPWK_ASR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID33_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID33(value) (PMC_SLPWK_ASR1_PID33_Msk & ((value) << PMC_SLPWK_ASR1_PID33_Pos)) +#define PMC_SLPWK_ASR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID34_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID34(value) (PMC_SLPWK_ASR1_PID34_Msk & ((value) << PMC_SLPWK_ASR1_PID34_Pos)) +#define PMC_SLPWK_ASR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID35_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID35(value) (PMC_SLPWK_ASR1_PID35_Msk & ((value) << PMC_SLPWK_ASR1_PID35_Pos)) +#define PMC_SLPWK_ASR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID37_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID37(value) (PMC_SLPWK_ASR1_PID37_Msk & ((value) << PMC_SLPWK_ASR1_PID37_Pos)) +#define PMC_SLPWK_ASR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID39_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID39(value) (PMC_SLPWK_ASR1_PID39_Msk & ((value) << PMC_SLPWK_ASR1_PID39_Pos)) +#define PMC_SLPWK_ASR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID40_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID40(value) (PMC_SLPWK_ASR1_PID40_Msk & ((value) << PMC_SLPWK_ASR1_PID40_Pos)) +#define PMC_SLPWK_ASR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID41_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID41(value) (PMC_SLPWK_ASR1_PID41_Msk & ((value) << PMC_SLPWK_ASR1_PID41_Pos)) +#define PMC_SLPWK_ASR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID42_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID42(value) (PMC_SLPWK_ASR1_PID42_Msk & ((value) << PMC_SLPWK_ASR1_PID42_Pos)) +#define PMC_SLPWK_ASR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID43_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID43(value) (PMC_SLPWK_ASR1_PID43_Msk & ((value) << PMC_SLPWK_ASR1_PID43_Pos)) +#define PMC_SLPWK_ASR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID44_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID44(value) (PMC_SLPWK_ASR1_PID44_Msk & ((value) << PMC_SLPWK_ASR1_PID44_Pos)) +#define PMC_SLPWK_ASR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID45_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID45(value) (PMC_SLPWK_ASR1_PID45_Msk & ((value) << PMC_SLPWK_ASR1_PID45_Pos)) +#define PMC_SLPWK_ASR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID46_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID46(value) (PMC_SLPWK_ASR1_PID46_Msk & ((value) << PMC_SLPWK_ASR1_PID46_Pos)) +#define PMC_SLPWK_ASR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID47_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID47(value) (PMC_SLPWK_ASR1_PID47_Msk & ((value) << PMC_SLPWK_ASR1_PID47_Pos)) +#define PMC_SLPWK_ASR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID48_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID48(value) (PMC_SLPWK_ASR1_PID48_Msk & ((value) << PMC_SLPWK_ASR1_PID48_Pos)) +#define PMC_SLPWK_ASR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID49_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID49(value) (PMC_SLPWK_ASR1_PID49_Msk & ((value) << PMC_SLPWK_ASR1_PID49_Pos)) +#define PMC_SLPWK_ASR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID50_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID50(value) (PMC_SLPWK_ASR1_PID50_Msk & ((value) << PMC_SLPWK_ASR1_PID50_Pos)) +#define PMC_SLPWK_ASR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID51_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID51(value) (PMC_SLPWK_ASR1_PID51_Msk & ((value) << PMC_SLPWK_ASR1_PID51_Pos)) +#define PMC_SLPWK_ASR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID52_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID52(value) (PMC_SLPWK_ASR1_PID52_Msk & ((value) << PMC_SLPWK_ASR1_PID52_Pos)) +#define PMC_SLPWK_ASR1_PID53_Pos _U_(21) /**< (PMC_SLPWK_ASR1) Peripheral 53 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID53_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID53_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 53 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID53(value) (PMC_SLPWK_ASR1_PID53_Msk & ((value) << PMC_SLPWK_ASR1_PID53_Pos)) +#define PMC_SLPWK_ASR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID56_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID56(value) (PMC_SLPWK_ASR1_PID56_Msk & ((value) << PMC_SLPWK_ASR1_PID56_Pos)) +#define PMC_SLPWK_ASR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID57_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID57(value) (PMC_SLPWK_ASR1_PID57_Msk & ((value) << PMC_SLPWK_ASR1_PID57_Pos)) +#define PMC_SLPWK_ASR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID58_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID58(value) (PMC_SLPWK_ASR1_PID58_Msk & ((value) << PMC_SLPWK_ASR1_PID58_Pos)) +#define PMC_SLPWK_ASR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID59_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID59(value) (PMC_SLPWK_ASR1_PID59_Msk & ((value) << PMC_SLPWK_ASR1_PID59_Pos)) +#define PMC_SLPWK_ASR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID60_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID60(value) (PMC_SLPWK_ASR1_PID60_Msk & ((value) << PMC_SLPWK_ASR1_PID60_Pos)) +#define PMC_SLPWK_ASR1_Msk _U_(0x1F3FFFAF) /**< (PMC_SLPWK_ASR1) Register Mask */ + +#define PMC_SLPWK_ASR1_PID_Pos _U_(0) /**< (PMC_SLPWK_ASR1 Position) Peripheral 6x Activity Status */ +#define PMC_SLPWK_ASR1_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR1_PID_Pos) /**< (PMC_SLPWK_ASR1 Mask) PID */ +#define PMC_SLPWK_ASR1_PID(value) (PMC_SLPWK_ASR1_PID_Msk & ((value) << PMC_SLPWK_ASR1_PID_Pos)) + +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x144) ( R/ 32) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP_Pos _U_(0) /**< (PMC_SLPWK_AIPR) Activity In Progress Position */ +#define PMC_SLPWK_AIPR_AIP_Msk (_U_(0x1) << PMC_SLPWK_AIPR_AIP_Pos) /**< (PMC_SLPWK_AIPR) Activity In Progress Mask */ +#define PMC_SLPWK_AIPR_AIP(value) (PMC_SLPWK_AIPR_AIP_Msk & ((value) << PMC_SLPWK_AIPR_AIP_Pos)) +#define PMC_SLPWK_AIPR_Msk _U_(0x00000001) /**< (PMC_SLPWK_AIPR) Register Mask */ + + +/** \brief PMC register offsets definitions */ +#define PMC_SCER_REG_OFST (0x00) /**< (PMC_SCER) System Clock Enable Register Offset */ +#define PMC_SCDR_REG_OFST (0x04) /**< (PMC_SCDR) System Clock Disable Register Offset */ +#define PMC_SCSR_REG_OFST (0x08) /**< (PMC_SCSR) System Clock Status Register Offset */ +#define PMC_PCER0_REG_OFST (0x10) /**< (PMC_PCER0) Peripheral Clock Enable Register 0 Offset */ +#define PMC_PCDR0_REG_OFST (0x14) /**< (PMC_PCDR0) Peripheral Clock Disable Register 0 Offset */ +#define PMC_PCSR0_REG_OFST (0x18) /**< (PMC_PCSR0) Peripheral Clock Status Register 0 Offset */ +#define CKGR_UCKR_REG_OFST (0x1C) /**< (CKGR_UCKR) UTMI Clock Register Offset */ +#define CKGR_MOR_REG_OFST (0x20) /**< (CKGR_MOR) Main Oscillator Register Offset */ +#define CKGR_MCFR_REG_OFST (0x24) /**< (CKGR_MCFR) Main Clock Frequency Register Offset */ +#define CKGR_PLLAR_REG_OFST (0x28) /**< (CKGR_PLLAR) PLLA Register Offset */ +#define PMC_MCKR_REG_OFST (0x30) /**< (PMC_MCKR) Master Clock Register Offset */ +#define PMC_USB_REG_OFST (0x38) /**< (PMC_USB) USB Clock Register Offset */ +#define PMC_PCK_REG_OFST (0x40) /**< (PMC_PCK) Programmable Clock Register Offset */ +#define PMC_IER_REG_OFST (0x60) /**< (PMC_IER) Interrupt Enable Register Offset */ +#define PMC_IDR_REG_OFST (0x64) /**< (PMC_IDR) Interrupt Disable Register Offset */ +#define PMC_SR_REG_OFST (0x68) /**< (PMC_SR) Status Register Offset */ +#define PMC_IMR_REG_OFST (0x6C) /**< (PMC_IMR) Interrupt Mask Register Offset */ +#define PMC_FSMR_REG_OFST (0x70) /**< (PMC_FSMR) Fast Startup Mode Register Offset */ +#define PMC_FSPR_REG_OFST (0x74) /**< (PMC_FSPR) Fast Startup Polarity Register Offset */ +#define PMC_FOCR_REG_OFST (0x78) /**< (PMC_FOCR) Fault Output Clear Register Offset */ +#define PMC_WPMR_REG_OFST (0xE4) /**< (PMC_WPMR) Write Protection Mode Register Offset */ +#define PMC_WPSR_REG_OFST (0xE8) /**< (PMC_WPSR) Write Protection Status Register Offset */ +#define PMC_PCER1_REG_OFST (0x100) /**< (PMC_PCER1) Peripheral Clock Enable Register 1 Offset */ +#define PMC_PCDR1_REG_OFST (0x104) /**< (PMC_PCDR1) Peripheral Clock Disable Register 1 Offset */ +#define PMC_PCSR1_REG_OFST (0x108) /**< (PMC_PCSR1) Peripheral Clock Status Register 1 Offset */ +#define PMC_PCR_REG_OFST (0x10C) /**< (PMC_PCR) Peripheral Control Register Offset */ +#define PMC_OCR_REG_OFST (0x110) /**< (PMC_OCR) Oscillator Calibration Register Offset */ +#define PMC_SLPWK_ER0_REG_OFST (0x114) /**< (PMC_SLPWK_ER0) SleepWalking Enable Register 0 Offset */ +#define PMC_SLPWK_DR0_REG_OFST (0x118) /**< (PMC_SLPWK_DR0) SleepWalking Disable Register 0 Offset */ +#define PMC_SLPWK_SR0_REG_OFST (0x11C) /**< (PMC_SLPWK_SR0) SleepWalking Status Register 0 Offset */ +#define PMC_SLPWK_ASR0_REG_OFST (0x120) /**< (PMC_SLPWK_ASR0) SleepWalking Activity Status Register 0 Offset */ +#define PMC_PMMR_REG_OFST (0x130) /**< (PMC_PMMR) PLL Maximum Multiplier Value Register Offset */ +#define PMC_SLPWK_ER1_REG_OFST (0x134) /**< (PMC_SLPWK_ER1) SleepWalking Enable Register 1 Offset */ +#define PMC_SLPWK_DR1_REG_OFST (0x138) /**< (PMC_SLPWK_DR1) SleepWalking Disable Register 1 Offset */ +#define PMC_SLPWK_SR1_REG_OFST (0x13C) /**< (PMC_SLPWK_SR1) SleepWalking Status Register 1 Offset */ +#define PMC_SLPWK_ASR1_REG_OFST (0x140) /**< (PMC_SLPWK_ASR1) SleepWalking Activity Status Register 1 Offset */ +#define PMC_SLPWK_AIPR_REG_OFST (0x144) /**< (PMC_SLPWK_AIPR) SleepWalking Activity In Progress Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PMC register API structure */ +typedef struct +{ + __O uint32_t PMC_SCER; /**< Offset: 0x00 ( /W 32) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< Offset: 0x04 ( /W 32) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< Offset: 0x08 (R/ 32) System Clock Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t PMC_PCER0; /**< Offset: 0x10 ( /W 32) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< Offset: 0x14 ( /W 32) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< Offset: 0x18 (R/ 32) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< Offset: 0x1C (R/W 32) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< Offset: 0x20 (R/W 32) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< Offset: 0x24 (R/W 32) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< Offset: 0x28 (R/W 32) PLLA Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t PMC_MCKR; /**< Offset: 0x30 (R/W 32) Master Clock Register */ + __I uint8_t Reserved3[0x04]; + __IO uint32_t PMC_USB; /**< Offset: 0x38 (R/W 32) USB Clock Register */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t PMC_PCK[8]; /**< Offset: 0x40 (R/W 32) Programmable Clock Register */ + __O uint32_t PMC_IER; /**< Offset: 0x60 ( /W 32) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< Offset: 0x64 ( /W 32) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< Offset: 0x68 (R/ 32) Status Register */ + __I uint32_t PMC_IMR; /**< Offset: 0x6C (R/ 32) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< Offset: 0x70 (R/W 32) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< Offset: 0x74 (R/W 32) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< Offset: 0x78 ( /W 32) Fault Output Clear Register */ + __I uint8_t Reserved5[0x68]; + __IO uint32_t PMC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved6[0x14]; + __O uint32_t PMC_PCER1; /**< Offset: 0x100 ( /W 32) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< Offset: 0x104 ( /W 32) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< Offset: 0x108 (R/ 32) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< Offset: 0x10C (R/W 32) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< Offset: 0x110 (R/W 32) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< Offset: 0x114 ( /W 32) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< Offset: 0x118 ( /W 32) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< Offset: 0x11C (R/ 32) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< Offset: 0x120 (R/ 32) SleepWalking Activity Status Register 0 */ + __I uint8_t Reserved7[0x0C]; + __IO uint32_t PMC_PMMR; /**< Offset: 0x130 (R/W 32) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< Offset: 0x134 ( /W 32) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< Offset: 0x138 ( /W 32) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< Offset: 0x13C (R/ 32) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< Offset: 0x140 (R/ 32) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< Offset: 0x144 (R/ 32) SleepWalking Activity In Progress Register */ +} pmc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/pwm.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/pwm.h new file mode 100644 index 00000000..360cc2d1 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/pwm.h @@ -0,0 +1,1563 @@ +/** + * \brief Component description for PWM + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_PWM_COMPONENT_H_ +#define _SAME70_PWM_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWM */ +/* ************************************************************************** */ + +/* -------- PWM_CMR : (PWM Offset: 0x00) (R/W 32) PWM Channel Mode Register (ch_num = 0) -------- */ +#define PWM_CMR_CPRE_Pos _U_(0) /**< (PWM_CMR) Channel Pre-scaler Position */ +#define PWM_CMR_CPRE_Msk (_U_(0xF) << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Channel Pre-scaler Mask */ +#define PWM_CMR_CPRE(value) (PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)) +#define PWM_CMR_CPRE_MCK_Val _U_(0x0) /**< (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2_Val _U_(0x1) /**< (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4_Val _U_(0x2) /**< (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8_Val _U_(0x3) /**< (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16_Val _U_(0x4) /**< (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32_Val _U_(0x5) /**< (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64_Val _U_(0x6) /**< (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128_Val _U_(0x7) /**< (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256_Val _U_(0x8) /**< (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512_Val _U_(0x9) /**< (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024_Val _U_(0xA) /**< (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA_Val _U_(0xB) /**< (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB_Val _U_(0xC) /**< (PWM_CMR) Clock B */ +#define PWM_CMR_CPRE_MCK (PWM_CMR_CPRE_MCK_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock Position */ +#define PWM_CMR_CPRE_MCK_DIV_2 (PWM_CMR_CPRE_MCK_DIV_2_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/2 Position */ +#define PWM_CMR_CPRE_MCK_DIV_4 (PWM_CMR_CPRE_MCK_DIV_4_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/4 Position */ +#define PWM_CMR_CPRE_MCK_DIV_8 (PWM_CMR_CPRE_MCK_DIV_8_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/8 Position */ +#define PWM_CMR_CPRE_MCK_DIV_16 (PWM_CMR_CPRE_MCK_DIV_16_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/16 Position */ +#define PWM_CMR_CPRE_MCK_DIV_32 (PWM_CMR_CPRE_MCK_DIV_32_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/32 Position */ +#define PWM_CMR_CPRE_MCK_DIV_64 (PWM_CMR_CPRE_MCK_DIV_64_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/64 Position */ +#define PWM_CMR_CPRE_MCK_DIV_128 (PWM_CMR_CPRE_MCK_DIV_128_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/128 Position */ +#define PWM_CMR_CPRE_MCK_DIV_256 (PWM_CMR_CPRE_MCK_DIV_256_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/256 Position */ +#define PWM_CMR_CPRE_MCK_DIV_512 (PWM_CMR_CPRE_MCK_DIV_512_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/512 Position */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (PWM_CMR_CPRE_MCK_DIV_1024_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/1024 Position */ +#define PWM_CMR_CPRE_CLKA (PWM_CMR_CPRE_CLKA_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock A Position */ +#define PWM_CMR_CPRE_CLKB (PWM_CMR_CPRE_CLKB_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock B Position */ +#define PWM_CMR_CALG_Pos _U_(8) /**< (PWM_CMR) Channel Alignment Position */ +#define PWM_CMR_CALG_Msk (_U_(0x1) << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Channel Alignment Mask */ +#define PWM_CMR_CALG(value) (PWM_CMR_CALG_Msk & ((value) << PWM_CMR_CALG_Pos)) +#define PWM_CMR_CPOL_Pos _U_(9) /**< (PWM_CMR) Channel Polarity Position */ +#define PWM_CMR_CPOL_Msk (_U_(0x1) << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Channel Polarity Mask */ +#define PWM_CMR_CPOL(value) (PWM_CMR_CPOL_Msk & ((value) << PWM_CMR_CPOL_Pos)) +#define PWM_CMR_CES_Pos _U_(10) /**< (PWM_CMR) Counter Event Selection Position */ +#define PWM_CMR_CES_Msk (_U_(0x1) << PWM_CMR_CES_Pos) /**< (PWM_CMR) Counter Event Selection Mask */ +#define PWM_CMR_CES(value) (PWM_CMR_CES_Msk & ((value) << PWM_CMR_CES_Pos)) +#define PWM_CMR_UPDS_Pos _U_(11) /**< (PWM_CMR) Update Selection Position */ +#define PWM_CMR_UPDS_Msk (_U_(0x1) << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) Update Selection Mask */ +#define PWM_CMR_UPDS(value) (PWM_CMR_UPDS_Msk & ((value) << PWM_CMR_UPDS_Pos)) +#define PWM_CMR_DPOLI_Pos _U_(12) /**< (PWM_CMR) Disabled Polarity Inverted Position */ +#define PWM_CMR_DPOLI_Msk (_U_(0x1) << PWM_CMR_DPOLI_Pos) /**< (PWM_CMR) Disabled Polarity Inverted Mask */ +#define PWM_CMR_DPOLI(value) (PWM_CMR_DPOLI_Msk & ((value) << PWM_CMR_DPOLI_Pos)) +#define PWM_CMR_TCTS_Pos _U_(13) /**< (PWM_CMR) Timer Counter Trigger Selection Position */ +#define PWM_CMR_TCTS_Msk (_U_(0x1) << PWM_CMR_TCTS_Pos) /**< (PWM_CMR) Timer Counter Trigger Selection Mask */ +#define PWM_CMR_TCTS(value) (PWM_CMR_TCTS_Msk & ((value) << PWM_CMR_TCTS_Pos)) +#define PWM_CMR_DTE_Pos _U_(16) /**< (PWM_CMR) Dead-Time Generator Enable Position */ +#define PWM_CMR_DTE_Msk (_U_(0x1) << PWM_CMR_DTE_Pos) /**< (PWM_CMR) Dead-Time Generator Enable Mask */ +#define PWM_CMR_DTE(value) (PWM_CMR_DTE_Msk & ((value) << PWM_CMR_DTE_Pos)) +#define PWM_CMR_DTHI_Pos _U_(17) /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Position */ +#define PWM_CMR_DTHI_Msk (_U_(0x1) << PWM_CMR_DTHI_Pos) /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Mask */ +#define PWM_CMR_DTHI(value) (PWM_CMR_DTHI_Msk & ((value) << PWM_CMR_DTHI_Pos)) +#define PWM_CMR_DTLI_Pos _U_(18) /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Position */ +#define PWM_CMR_DTLI_Msk (_U_(0x1) << PWM_CMR_DTLI_Pos) /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Mask */ +#define PWM_CMR_DTLI(value) (PWM_CMR_DTLI_Msk & ((value) << PWM_CMR_DTLI_Pos)) +#define PWM_CMR_PPM_Pos _U_(19) /**< (PWM_CMR) Push-Pull Mode Position */ +#define PWM_CMR_PPM_Msk (_U_(0x1) << PWM_CMR_PPM_Pos) /**< (PWM_CMR) Push-Pull Mode Mask */ +#define PWM_CMR_PPM(value) (PWM_CMR_PPM_Msk & ((value) << PWM_CMR_PPM_Pos)) +#define PWM_CMR_Msk _U_(0x000F3F0F) /**< (PWM_CMR) Register Mask */ + + +/* -------- PWM_CDTY : (PWM Offset: 0x04) (R/W 32) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ +#define PWM_CDTY_CDTY_Pos _U_(0) /**< (PWM_CDTY) Channel Duty-Cycle Position */ +#define PWM_CDTY_CDTY_Msk (_U_(0xFFFFFF) << PWM_CDTY_CDTY_Pos) /**< (PWM_CDTY) Channel Duty-Cycle Mask */ +#define PWM_CDTY_CDTY(value) (PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)) +#define PWM_CDTY_Msk _U_(0x00FFFFFF) /**< (PWM_CDTY) Register Mask */ + + +/* -------- PWM_CDTYUPD : (PWM Offset: 0x08) ( /W 32) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos _U_(0) /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Position */ +#define PWM_CDTYUPD_CDTYUPD_Msk (_U_(0xFFFFFF) << PWM_CDTYUPD_CDTYUPD_Pos) /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Mask */ +#define PWM_CDTYUPD_CDTYUPD(value) (PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)) +#define PWM_CDTYUPD_Msk _U_(0x00FFFFFF) /**< (PWM_CDTYUPD) Register Mask */ + + +/* -------- PWM_CPRD : (PWM Offset: 0x0C) (R/W 32) PWM Channel Period Register (ch_num = 0) -------- */ +#define PWM_CPRD_CPRD_Pos _U_(0) /**< (PWM_CPRD) Channel Period Position */ +#define PWM_CPRD_CPRD_Msk (_U_(0xFFFFFF) << PWM_CPRD_CPRD_Pos) /**< (PWM_CPRD) Channel Period Mask */ +#define PWM_CPRD_CPRD(value) (PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)) +#define PWM_CPRD_Msk _U_(0x00FFFFFF) /**< (PWM_CPRD) Register Mask */ + + +/* -------- PWM_CPRDUPD : (PWM Offset: 0x10) ( /W 32) PWM Channel Period Update Register (ch_num = 0) -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos _U_(0) /**< (PWM_CPRDUPD) Channel Period Update Position */ +#define PWM_CPRDUPD_CPRDUPD_Msk (_U_(0xFFFFFF) << PWM_CPRDUPD_CPRDUPD_Pos) /**< (PWM_CPRDUPD) Channel Period Update Mask */ +#define PWM_CPRDUPD_CPRDUPD(value) (PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)) +#define PWM_CPRDUPD_Msk _U_(0x00FFFFFF) /**< (PWM_CPRDUPD) Register Mask */ + + +/* -------- PWM_CCNT : (PWM Offset: 0x14) ( R/ 32) PWM Channel Counter Register (ch_num = 0) -------- */ +#define PWM_CCNT_CNT_Pos _U_(0) /**< (PWM_CCNT) Channel Counter Register Position */ +#define PWM_CCNT_CNT_Msk (_U_(0xFFFFFF) << PWM_CCNT_CNT_Pos) /**< (PWM_CCNT) Channel Counter Register Mask */ +#define PWM_CCNT_CNT(value) (PWM_CCNT_CNT_Msk & ((value) << PWM_CCNT_CNT_Pos)) +#define PWM_CCNT_Msk _U_(0x00FFFFFF) /**< (PWM_CCNT) Register Mask */ + + +/* -------- PWM_DT : (PWM Offset: 0x18) (R/W 32) PWM Channel Dead Time Register (ch_num = 0) -------- */ +#define PWM_DT_DTH_Pos _U_(0) /**< (PWM_DT) Dead-Time Value for PWMHx Output Position */ +#define PWM_DT_DTH_Msk (_U_(0xFFFF) << PWM_DT_DTH_Pos) /**< (PWM_DT) Dead-Time Value for PWMHx Output Mask */ +#define PWM_DT_DTH(value) (PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)) +#define PWM_DT_DTL_Pos _U_(16) /**< (PWM_DT) Dead-Time Value for PWMLx Output Position */ +#define PWM_DT_DTL_Msk (_U_(0xFFFF) << PWM_DT_DTL_Pos) /**< (PWM_DT) Dead-Time Value for PWMLx Output Mask */ +#define PWM_DT_DTL(value) (PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)) +#define PWM_DT_Msk _U_(0xFFFFFFFF) /**< (PWM_DT) Register Mask */ + + +/* -------- PWM_DTUPD : (PWM Offset: 0x1C) ( /W 32) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ +#define PWM_DTUPD_DTHUPD_Pos _U_(0) /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Position */ +#define PWM_DTUPD_DTHUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTHUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Mask */ +#define PWM_DTUPD_DTHUPD(value) (PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)) +#define PWM_DTUPD_DTLUPD_Pos _U_(16) /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Position */ +#define PWM_DTUPD_DTLUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTLUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Mask */ +#define PWM_DTUPD_DTLUPD(value) (PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)) +#define PWM_DTUPD_Msk _U_(0xFFFFFFFF) /**< (PWM_DTUPD) Register Mask */ + + +/* -------- PWM_CMPV : (PWM Offset: 0x00) (R/W 32) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos _U_(0) /**< (PWM_CMPV) Comparison x Value Position */ +#define PWM_CMPV_CV_Msk (_U_(0xFFFFFF) << PWM_CMPV_CV_Pos) /**< (PWM_CMPV) Comparison x Value Mask */ +#define PWM_CMPV_CV(value) (PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)) +#define PWM_CMPV_CVM_Pos _U_(24) /**< (PWM_CMPV) Comparison x Value Mode Position */ +#define PWM_CMPV_CVM_Msk (_U_(0x1) << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Comparison x Value Mode Mask */ +#define PWM_CMPV_CVM(value) (PWM_CMPV_CVM_Msk & ((value) << PWM_CMPV_CVM_Pos)) +#define PWM_CMPV_Msk _U_(0x01FFFFFF) /**< (PWM_CMPV) Register Mask */ + + +/* -------- PWM_CMPVUPD : (PWM Offset: 0x04) ( /W 32) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos _U_(0) /**< (PWM_CMPVUPD) Comparison x Value Update Position */ +#define PWM_CMPVUPD_CVUPD_Msk (_U_(0xFFFFFF) << PWM_CMPVUPD_CVUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Update Mask */ +#define PWM_CMPVUPD_CVUPD(value) (PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)) +#define PWM_CMPVUPD_CVMUPD_Pos _U_(24) /**< (PWM_CMPVUPD) Comparison x Value Mode Update Position */ +#define PWM_CMPVUPD_CVMUPD_Msk (_U_(0x1) << PWM_CMPVUPD_CVMUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Mode Update Mask */ +#define PWM_CMPVUPD_CVMUPD(value) (PWM_CMPVUPD_CVMUPD_Msk & ((value) << PWM_CMPVUPD_CVMUPD_Pos)) +#define PWM_CMPVUPD_Msk _U_(0x01FFFFFF) /**< (PWM_CMPVUPD) Register Mask */ + + +/* -------- PWM_CMPM : (PWM Offset: 0x08) (R/W 32) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN_Pos _U_(0) /**< (PWM_CMPM) Comparison x Enable Position */ +#define PWM_CMPM_CEN_Msk (_U_(0x1) << PWM_CMPM_CEN_Pos) /**< (PWM_CMPM) Comparison x Enable Mask */ +#define PWM_CMPM_CEN(value) (PWM_CMPM_CEN_Msk & ((value) << PWM_CMPM_CEN_Pos)) +#define PWM_CMPM_CTR_Pos _U_(4) /**< (PWM_CMPM) Comparison x Trigger Position */ +#define PWM_CMPM_CTR_Msk (_U_(0xF) << PWM_CMPM_CTR_Pos) /**< (PWM_CMPM) Comparison x Trigger Mask */ +#define PWM_CMPM_CTR(value) (PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)) +#define PWM_CMPM_CPR_Pos _U_(8) /**< (PWM_CMPM) Comparison x Period Position */ +#define PWM_CMPM_CPR_Msk (_U_(0xF) << PWM_CMPM_CPR_Pos) /**< (PWM_CMPM) Comparison x Period Mask */ +#define PWM_CMPM_CPR(value) (PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)) +#define PWM_CMPM_CPRCNT_Pos _U_(12) /**< (PWM_CMPM) Comparison x Period Counter Position */ +#define PWM_CMPM_CPRCNT_Msk (_U_(0xF) << PWM_CMPM_CPRCNT_Pos) /**< (PWM_CMPM) Comparison x Period Counter Mask */ +#define PWM_CMPM_CPRCNT(value) (PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)) +#define PWM_CMPM_CUPR_Pos _U_(16) /**< (PWM_CMPM) Comparison x Update Period Position */ +#define PWM_CMPM_CUPR_Msk (_U_(0xF) << PWM_CMPM_CUPR_Pos) /**< (PWM_CMPM) Comparison x Update Period Mask */ +#define PWM_CMPM_CUPR(value) (PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)) +#define PWM_CMPM_CUPRCNT_Pos _U_(20) /**< (PWM_CMPM) Comparison x Update Period Counter Position */ +#define PWM_CMPM_CUPRCNT_Msk (_U_(0xF) << PWM_CMPM_CUPRCNT_Pos) /**< (PWM_CMPM) Comparison x Update Period Counter Mask */ +#define PWM_CMPM_CUPRCNT(value) (PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)) +#define PWM_CMPM_Msk _U_(0x00FFFFF1) /**< (PWM_CMPM) Register Mask */ + + +/* -------- PWM_CMPMUPD : (PWM Offset: 0x0C) ( /W 32) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD_Pos _U_(0) /**< (PWM_CMPMUPD) Comparison x Enable Update Position */ +#define PWM_CMPMUPD_CENUPD_Msk (_U_(0x1) << PWM_CMPMUPD_CENUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Enable Update Mask */ +#define PWM_CMPMUPD_CENUPD(value) (PWM_CMPMUPD_CENUPD_Msk & ((value) << PWM_CMPMUPD_CENUPD_Pos)) +#define PWM_CMPMUPD_CTRUPD_Pos _U_(4) /**< (PWM_CMPMUPD) Comparison x Trigger Update Position */ +#define PWM_CMPMUPD_CTRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CTRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Trigger Update Mask */ +#define PWM_CMPMUPD_CTRUPD(value) (PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)) +#define PWM_CMPMUPD_CPRUPD_Pos _U_(8) /**< (PWM_CMPMUPD) Comparison x Period Update Position */ +#define PWM_CMPMUPD_CPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Period Update Mask */ +#define PWM_CMPMUPD_CPRUPD(value) (PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)) +#define PWM_CMPMUPD_CUPRUPD_Pos _U_(16) /**< (PWM_CMPMUPD) Comparison x Update Period Update Position */ +#define PWM_CMPMUPD_CUPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CUPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Update Period Update Mask */ +#define PWM_CMPMUPD_CUPRUPD(value) (PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)) +#define PWM_CMPMUPD_Msk _U_(0x000F0FF1) /**< (PWM_CMPMUPD) Register Mask */ + + +/* -------- PWM_CLK : (PWM Offset: 0x00) (R/W 32) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos _U_(0) /**< (PWM_CLK) CLKA Divide Factor Position */ +#define PWM_CLK_DIVA_Msk (_U_(0xFF) << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA Divide Factor Mask */ +#define PWM_CLK_DIVA(value) (PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)) +#define PWM_CLK_DIVA_CLKA_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA_Val _U_(0x1) /**< (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_DIVA_CLKA_POFF (PWM_CLK_DIVA_CLKA_POFF_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is turned off Position */ +#define PWM_CLK_DIVA_PREA (PWM_CLK_DIVA_PREA_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is clock selected by PREA Position */ +#define PWM_CLK_PREA_Pos _U_(8) /**< (PWM_CLK) CLKA Source Clock Selection Position */ +#define PWM_CLK_PREA_Msk (_U_(0xF) << PWM_CLK_PREA_Pos) /**< (PWM_CLK) CLKA Source Clock Selection Mask */ +#define PWM_CLK_PREA(value) (PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)) +#define PWM_CLK_PREA_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREA_CLK (PWM_CLK_PREA_CLK_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREA_CLK_DIV2 (PWM_CLK_PREA_CLK_DIV2_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREA_CLK_DIV4 (PWM_CLK_PREA_CLK_DIV4_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREA_CLK_DIV8 (PWM_CLK_PREA_CLK_DIV8_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREA_CLK_DIV16 (PWM_CLK_PREA_CLK_DIV16_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREA_CLK_DIV32 (PWM_CLK_PREA_CLK_DIV32_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREA_CLK_DIV64 (PWM_CLK_PREA_CLK_DIV64_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREA_CLK_DIV128 (PWM_CLK_PREA_CLK_DIV128_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREA_CLK_DIV256 (PWM_CLK_PREA_CLK_DIV256_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREA_CLK_DIV512 (PWM_CLK_PREA_CLK_DIV512_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREA_CLK_DIV1024 (PWM_CLK_PREA_CLK_DIV1024_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_DIVB_Pos _U_(16) /**< (PWM_CLK) CLKB Divide Factor Position */ +#define PWM_CLK_DIVB_Msk (_U_(0xFF) << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB Divide Factor Mask */ +#define PWM_CLK_DIVB(value) (PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)) +#define PWM_CLK_DIVB_CLKB_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB_Val _U_(0x1) /**< (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_DIVB_CLKB_POFF (PWM_CLK_DIVB_CLKB_POFF_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is turned off Position */ +#define PWM_CLK_DIVB_PREB (PWM_CLK_DIVB_PREB_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is clock selected by PREB Position */ +#define PWM_CLK_PREB_Pos _U_(24) /**< (PWM_CLK) CLKB Source Clock Selection Position */ +#define PWM_CLK_PREB_Msk (_U_(0xF) << PWM_CLK_PREB_Pos) /**< (PWM_CLK) CLKB Source Clock Selection Mask */ +#define PWM_CLK_PREB(value) (PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)) +#define PWM_CLK_PREB_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREB_CLK (PWM_CLK_PREB_CLK_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREB_CLK_DIV2 (PWM_CLK_PREB_CLK_DIV2_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREB_CLK_DIV4 (PWM_CLK_PREB_CLK_DIV4_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREB_CLK_DIV8 (PWM_CLK_PREB_CLK_DIV8_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREB_CLK_DIV16 (PWM_CLK_PREB_CLK_DIV16_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREB_CLK_DIV32 (PWM_CLK_PREB_CLK_DIV32_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREB_CLK_DIV64 (PWM_CLK_PREB_CLK_DIV64_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREB_CLK_DIV128 (PWM_CLK_PREB_CLK_DIV128_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREB_CLK_DIV256 (PWM_CLK_PREB_CLK_DIV256_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREB_CLK_DIV512 (PWM_CLK_PREB_CLK_DIV512_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREB_CLK_DIV1024 (PWM_CLK_PREB_CLK_DIV1024_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_Msk _U_(0x0FFF0FFF) /**< (PWM_CLK) Register Mask */ + + +/* -------- PWM_ENA : (PWM Offset: 0x04) ( /W 32) PWM Enable Register -------- */ +#define PWM_ENA_CHID0_Pos _U_(0) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID0_Msk (_U_(0x1) << PWM_ENA_CHID0_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID0(value) (PWM_ENA_CHID0_Msk & ((value) << PWM_ENA_CHID0_Pos)) +#define PWM_ENA_CHID1_Pos _U_(1) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID1_Msk (_U_(0x1) << PWM_ENA_CHID1_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID1(value) (PWM_ENA_CHID1_Msk & ((value) << PWM_ENA_CHID1_Pos)) +#define PWM_ENA_CHID2_Pos _U_(2) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID2_Msk (_U_(0x1) << PWM_ENA_CHID2_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID2(value) (PWM_ENA_CHID2_Msk & ((value) << PWM_ENA_CHID2_Pos)) +#define PWM_ENA_CHID3_Pos _U_(3) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID3_Msk (_U_(0x1) << PWM_ENA_CHID3_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID3(value) (PWM_ENA_CHID3_Msk & ((value) << PWM_ENA_CHID3_Pos)) +#define PWM_ENA_Msk _U_(0x0000000F) /**< (PWM_ENA) Register Mask */ + +#define PWM_ENA_CHID_Pos _U_(0) /**< (PWM_ENA Position) Channel ID */ +#define PWM_ENA_CHID_Msk (_U_(0xF) << PWM_ENA_CHID_Pos) /**< (PWM_ENA Mask) CHID */ +#define PWM_ENA_CHID(value) (PWM_ENA_CHID_Msk & ((value) << PWM_ENA_CHID_Pos)) + +/* -------- PWM_DIS : (PWM Offset: 0x08) ( /W 32) PWM Disable Register -------- */ +#define PWM_DIS_CHID0_Pos _U_(0) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID0_Msk (_U_(0x1) << PWM_DIS_CHID0_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID0(value) (PWM_DIS_CHID0_Msk & ((value) << PWM_DIS_CHID0_Pos)) +#define PWM_DIS_CHID1_Pos _U_(1) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID1_Msk (_U_(0x1) << PWM_DIS_CHID1_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID1(value) (PWM_DIS_CHID1_Msk & ((value) << PWM_DIS_CHID1_Pos)) +#define PWM_DIS_CHID2_Pos _U_(2) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID2_Msk (_U_(0x1) << PWM_DIS_CHID2_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID2(value) (PWM_DIS_CHID2_Msk & ((value) << PWM_DIS_CHID2_Pos)) +#define PWM_DIS_CHID3_Pos _U_(3) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID3_Msk (_U_(0x1) << PWM_DIS_CHID3_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID3(value) (PWM_DIS_CHID3_Msk & ((value) << PWM_DIS_CHID3_Pos)) +#define PWM_DIS_Msk _U_(0x0000000F) /**< (PWM_DIS) Register Mask */ + +#define PWM_DIS_CHID_Pos _U_(0) /**< (PWM_DIS Position) Channel ID */ +#define PWM_DIS_CHID_Msk (_U_(0xF) << PWM_DIS_CHID_Pos) /**< (PWM_DIS Mask) CHID */ +#define PWM_DIS_CHID(value) (PWM_DIS_CHID_Msk & ((value) << PWM_DIS_CHID_Pos)) + +/* -------- PWM_SR : (PWM Offset: 0x0C) ( R/ 32) PWM Status Register -------- */ +#define PWM_SR_CHID0_Pos _U_(0) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID0_Msk (_U_(0x1) << PWM_SR_CHID0_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID0(value) (PWM_SR_CHID0_Msk & ((value) << PWM_SR_CHID0_Pos)) +#define PWM_SR_CHID1_Pos _U_(1) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID1_Msk (_U_(0x1) << PWM_SR_CHID1_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID1(value) (PWM_SR_CHID1_Msk & ((value) << PWM_SR_CHID1_Pos)) +#define PWM_SR_CHID2_Pos _U_(2) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID2_Msk (_U_(0x1) << PWM_SR_CHID2_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID2(value) (PWM_SR_CHID2_Msk & ((value) << PWM_SR_CHID2_Pos)) +#define PWM_SR_CHID3_Pos _U_(3) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID3_Msk (_U_(0x1) << PWM_SR_CHID3_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID3(value) (PWM_SR_CHID3_Msk & ((value) << PWM_SR_CHID3_Pos)) +#define PWM_SR_Msk _U_(0x0000000F) /**< (PWM_SR) Register Mask */ + +#define PWM_SR_CHID_Pos _U_(0) /**< (PWM_SR Position) Channel ID */ +#define PWM_SR_CHID_Msk (_U_(0xF) << PWM_SR_CHID_Pos) /**< (PWM_SR Mask) CHID */ +#define PWM_SR_CHID(value) (PWM_SR_CHID_Msk & ((value) << PWM_SR_CHID_Pos)) + +/* -------- PWM_IER1 : (PWM Offset: 0x10) ( /W 32) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0_Pos _U_(0) /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_CHID0_Msk (_U_(0x1) << PWM_IER1_CHID0_Pos) /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_CHID0(value) (PWM_IER1_CHID0_Msk & ((value) << PWM_IER1_CHID0_Pos)) +#define PWM_IER1_CHID1_Pos _U_(1) /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_CHID1_Msk (_U_(0x1) << PWM_IER1_CHID1_Pos) /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_CHID1(value) (PWM_IER1_CHID1_Msk & ((value) << PWM_IER1_CHID1_Pos)) +#define PWM_IER1_CHID2_Pos _U_(2) /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_CHID2_Msk (_U_(0x1) << PWM_IER1_CHID2_Pos) /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_CHID2(value) (PWM_IER1_CHID2_Msk & ((value) << PWM_IER1_CHID2_Pos)) +#define PWM_IER1_CHID3_Pos _U_(3) /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_CHID3_Msk (_U_(0x1) << PWM_IER1_CHID3_Pos) /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_CHID3(value) (PWM_IER1_CHID3_Msk & ((value) << PWM_IER1_CHID3_Pos)) +#define PWM_IER1_FCHID0_Pos _U_(16) /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_FCHID0_Msk (_U_(0x1) << PWM_IER1_FCHID0_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_FCHID0(value) (PWM_IER1_FCHID0_Msk & ((value) << PWM_IER1_FCHID0_Pos)) +#define PWM_IER1_FCHID1_Pos _U_(17) /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_FCHID1_Msk (_U_(0x1) << PWM_IER1_FCHID1_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_FCHID1(value) (PWM_IER1_FCHID1_Msk & ((value) << PWM_IER1_FCHID1_Pos)) +#define PWM_IER1_FCHID2_Pos _U_(18) /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_FCHID2_Msk (_U_(0x1) << PWM_IER1_FCHID2_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_FCHID2(value) (PWM_IER1_FCHID2_Msk & ((value) << PWM_IER1_FCHID2_Pos)) +#define PWM_IER1_FCHID3_Pos _U_(19) /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_FCHID3_Msk (_U_(0x1) << PWM_IER1_FCHID3_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_FCHID3(value) (PWM_IER1_FCHID3_Msk & ((value) << PWM_IER1_FCHID3_Pos)) +#define PWM_IER1_Msk _U_(0x000F000F) /**< (PWM_IER1) Register Mask */ + +#define PWM_IER1_CHID_Pos _U_(0) /**< (PWM_IER1 Position) Counter Event on Channel x Interrupt Enable */ +#define PWM_IER1_CHID_Msk (_U_(0xF) << PWM_IER1_CHID_Pos) /**< (PWM_IER1 Mask) CHID */ +#define PWM_IER1_CHID(value) (PWM_IER1_CHID_Msk & ((value) << PWM_IER1_CHID_Pos)) +#define PWM_IER1_FCHID_Pos _U_(16) /**< (PWM_IER1 Position) Fault Protection Trigger on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID_Msk (_U_(0xF) << PWM_IER1_FCHID_Pos) /**< (PWM_IER1 Mask) FCHID */ +#define PWM_IER1_FCHID(value) (PWM_IER1_FCHID_Msk & ((value) << PWM_IER1_FCHID_Pos)) + +/* -------- PWM_IDR1 : (PWM Offset: 0x14) ( /W 32) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0_Pos _U_(0) /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_CHID0_Msk (_U_(0x1) << PWM_IDR1_CHID0_Pos) /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_CHID0(value) (PWM_IDR1_CHID0_Msk & ((value) << PWM_IDR1_CHID0_Pos)) +#define PWM_IDR1_CHID1_Pos _U_(1) /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_CHID1_Msk (_U_(0x1) << PWM_IDR1_CHID1_Pos) /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_CHID1(value) (PWM_IDR1_CHID1_Msk & ((value) << PWM_IDR1_CHID1_Pos)) +#define PWM_IDR1_CHID2_Pos _U_(2) /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_CHID2_Msk (_U_(0x1) << PWM_IDR1_CHID2_Pos) /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_CHID2(value) (PWM_IDR1_CHID2_Msk & ((value) << PWM_IDR1_CHID2_Pos)) +#define PWM_IDR1_CHID3_Pos _U_(3) /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_CHID3_Msk (_U_(0x1) << PWM_IDR1_CHID3_Pos) /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_CHID3(value) (PWM_IDR1_CHID3_Msk & ((value) << PWM_IDR1_CHID3_Pos)) +#define PWM_IDR1_FCHID0_Pos _U_(16) /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_FCHID0_Msk (_U_(0x1) << PWM_IDR1_FCHID0_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID0(value) (PWM_IDR1_FCHID0_Msk & ((value) << PWM_IDR1_FCHID0_Pos)) +#define PWM_IDR1_FCHID1_Pos _U_(17) /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_FCHID1_Msk (_U_(0x1) << PWM_IDR1_FCHID1_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID1(value) (PWM_IDR1_FCHID1_Msk & ((value) << PWM_IDR1_FCHID1_Pos)) +#define PWM_IDR1_FCHID2_Pos _U_(18) /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_FCHID2_Msk (_U_(0x1) << PWM_IDR1_FCHID2_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID2(value) (PWM_IDR1_FCHID2_Msk & ((value) << PWM_IDR1_FCHID2_Pos)) +#define PWM_IDR1_FCHID3_Pos _U_(19) /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_FCHID3_Msk (_U_(0x1) << PWM_IDR1_FCHID3_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID3(value) (PWM_IDR1_FCHID3_Msk & ((value) << PWM_IDR1_FCHID3_Pos)) +#define PWM_IDR1_Msk _U_(0x000F000F) /**< (PWM_IDR1) Register Mask */ + +#define PWM_IDR1_CHID_Pos _U_(0) /**< (PWM_IDR1 Position) Counter Event on Channel x Interrupt Disable */ +#define PWM_IDR1_CHID_Msk (_U_(0xF) << PWM_IDR1_CHID_Pos) /**< (PWM_IDR1 Mask) CHID */ +#define PWM_IDR1_CHID(value) (PWM_IDR1_CHID_Msk & ((value) << PWM_IDR1_CHID_Pos)) +#define PWM_IDR1_FCHID_Pos _U_(16) /**< (PWM_IDR1 Position) Fault Protection Trigger on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID_Msk (_U_(0xF) << PWM_IDR1_FCHID_Pos) /**< (PWM_IDR1 Mask) FCHID */ +#define PWM_IDR1_FCHID(value) (PWM_IDR1_FCHID_Msk & ((value) << PWM_IDR1_FCHID_Pos)) + +/* -------- PWM_IMR1 : (PWM Offset: 0x18) ( R/ 32) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0_Pos _U_(0) /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_CHID0_Msk (_U_(0x1) << PWM_IMR1_CHID0_Pos) /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_CHID0(value) (PWM_IMR1_CHID0_Msk & ((value) << PWM_IMR1_CHID0_Pos)) +#define PWM_IMR1_CHID1_Pos _U_(1) /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_CHID1_Msk (_U_(0x1) << PWM_IMR1_CHID1_Pos) /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_CHID1(value) (PWM_IMR1_CHID1_Msk & ((value) << PWM_IMR1_CHID1_Pos)) +#define PWM_IMR1_CHID2_Pos _U_(2) /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_CHID2_Msk (_U_(0x1) << PWM_IMR1_CHID2_Pos) /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_CHID2(value) (PWM_IMR1_CHID2_Msk & ((value) << PWM_IMR1_CHID2_Pos)) +#define PWM_IMR1_CHID3_Pos _U_(3) /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_CHID3_Msk (_U_(0x1) << PWM_IMR1_CHID3_Pos) /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_CHID3(value) (PWM_IMR1_CHID3_Msk & ((value) << PWM_IMR1_CHID3_Pos)) +#define PWM_IMR1_FCHID0_Pos _U_(16) /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_FCHID0_Msk (_U_(0x1) << PWM_IMR1_FCHID0_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID0(value) (PWM_IMR1_FCHID0_Msk & ((value) << PWM_IMR1_FCHID0_Pos)) +#define PWM_IMR1_FCHID1_Pos _U_(17) /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_FCHID1_Msk (_U_(0x1) << PWM_IMR1_FCHID1_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID1(value) (PWM_IMR1_FCHID1_Msk & ((value) << PWM_IMR1_FCHID1_Pos)) +#define PWM_IMR1_FCHID2_Pos _U_(18) /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_FCHID2_Msk (_U_(0x1) << PWM_IMR1_FCHID2_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID2(value) (PWM_IMR1_FCHID2_Msk & ((value) << PWM_IMR1_FCHID2_Pos)) +#define PWM_IMR1_FCHID3_Pos _U_(19) /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_FCHID3_Msk (_U_(0x1) << PWM_IMR1_FCHID3_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID3(value) (PWM_IMR1_FCHID3_Msk & ((value) << PWM_IMR1_FCHID3_Pos)) +#define PWM_IMR1_Msk _U_(0x000F000F) /**< (PWM_IMR1) Register Mask */ + +#define PWM_IMR1_CHID_Pos _U_(0) /**< (PWM_IMR1 Position) Counter Event on Channel x Interrupt Mask */ +#define PWM_IMR1_CHID_Msk (_U_(0xF) << PWM_IMR1_CHID_Pos) /**< (PWM_IMR1 Mask) CHID */ +#define PWM_IMR1_CHID(value) (PWM_IMR1_CHID_Msk & ((value) << PWM_IMR1_CHID_Pos)) +#define PWM_IMR1_FCHID_Pos _U_(16) /**< (PWM_IMR1 Position) Fault Protection Trigger on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID_Msk (_U_(0xF) << PWM_IMR1_FCHID_Pos) /**< (PWM_IMR1 Mask) FCHID */ +#define PWM_IMR1_FCHID(value) (PWM_IMR1_FCHID_Msk & ((value) << PWM_IMR1_FCHID_Pos)) + +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) ( R/ 32) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0_Pos _U_(0) /**< (PWM_ISR1) Counter Event on Channel 0 Position */ +#define PWM_ISR1_CHID0_Msk (_U_(0x1) << PWM_ISR1_CHID0_Pos) /**< (PWM_ISR1) Counter Event on Channel 0 Mask */ +#define PWM_ISR1_CHID0(value) (PWM_ISR1_CHID0_Msk & ((value) << PWM_ISR1_CHID0_Pos)) +#define PWM_ISR1_CHID1_Pos _U_(1) /**< (PWM_ISR1) Counter Event on Channel 1 Position */ +#define PWM_ISR1_CHID1_Msk (_U_(0x1) << PWM_ISR1_CHID1_Pos) /**< (PWM_ISR1) Counter Event on Channel 1 Mask */ +#define PWM_ISR1_CHID1(value) (PWM_ISR1_CHID1_Msk & ((value) << PWM_ISR1_CHID1_Pos)) +#define PWM_ISR1_CHID2_Pos _U_(2) /**< (PWM_ISR1) Counter Event on Channel 2 Position */ +#define PWM_ISR1_CHID2_Msk (_U_(0x1) << PWM_ISR1_CHID2_Pos) /**< (PWM_ISR1) Counter Event on Channel 2 Mask */ +#define PWM_ISR1_CHID2(value) (PWM_ISR1_CHID2_Msk & ((value) << PWM_ISR1_CHID2_Pos)) +#define PWM_ISR1_CHID3_Pos _U_(3) /**< (PWM_ISR1) Counter Event on Channel 3 Position */ +#define PWM_ISR1_CHID3_Msk (_U_(0x1) << PWM_ISR1_CHID3_Pos) /**< (PWM_ISR1) Counter Event on Channel 3 Mask */ +#define PWM_ISR1_CHID3(value) (PWM_ISR1_CHID3_Msk & ((value) << PWM_ISR1_CHID3_Pos)) +#define PWM_ISR1_FCHID0_Pos _U_(16) /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Position */ +#define PWM_ISR1_FCHID0_Msk (_U_(0x1) << PWM_ISR1_FCHID0_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Mask */ +#define PWM_ISR1_FCHID0(value) (PWM_ISR1_FCHID0_Msk & ((value) << PWM_ISR1_FCHID0_Pos)) +#define PWM_ISR1_FCHID1_Pos _U_(17) /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Position */ +#define PWM_ISR1_FCHID1_Msk (_U_(0x1) << PWM_ISR1_FCHID1_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Mask */ +#define PWM_ISR1_FCHID1(value) (PWM_ISR1_FCHID1_Msk & ((value) << PWM_ISR1_FCHID1_Pos)) +#define PWM_ISR1_FCHID2_Pos _U_(18) /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Position */ +#define PWM_ISR1_FCHID2_Msk (_U_(0x1) << PWM_ISR1_FCHID2_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Mask */ +#define PWM_ISR1_FCHID2(value) (PWM_ISR1_FCHID2_Msk & ((value) << PWM_ISR1_FCHID2_Pos)) +#define PWM_ISR1_FCHID3_Pos _U_(19) /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Position */ +#define PWM_ISR1_FCHID3_Msk (_U_(0x1) << PWM_ISR1_FCHID3_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Mask */ +#define PWM_ISR1_FCHID3(value) (PWM_ISR1_FCHID3_Msk & ((value) << PWM_ISR1_FCHID3_Pos)) +#define PWM_ISR1_Msk _U_(0x000F000F) /**< (PWM_ISR1) Register Mask */ + +#define PWM_ISR1_CHID_Pos _U_(0) /**< (PWM_ISR1 Position) Counter Event on Channel x */ +#define PWM_ISR1_CHID_Msk (_U_(0xF) << PWM_ISR1_CHID_Pos) /**< (PWM_ISR1 Mask) CHID */ +#define PWM_ISR1_CHID(value) (PWM_ISR1_CHID_Msk & ((value) << PWM_ISR1_CHID_Pos)) +#define PWM_ISR1_FCHID_Pos _U_(16) /**< (PWM_ISR1 Position) Fault Protection Trigger on Channel 3 */ +#define PWM_ISR1_FCHID_Msk (_U_(0xF) << PWM_ISR1_FCHID_Pos) /**< (PWM_ISR1 Mask) FCHID */ +#define PWM_ISR1_FCHID(value) (PWM_ISR1_FCHID_Msk & ((value) << PWM_ISR1_FCHID_Pos)) + +/* -------- PWM_SCM : (PWM Offset: 0x20) (R/W 32) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0_Pos _U_(0) /**< (PWM_SCM) Synchronous Channel 0 Position */ +#define PWM_SCM_SYNC0_Msk (_U_(0x1) << PWM_SCM_SYNC0_Pos) /**< (PWM_SCM) Synchronous Channel 0 Mask */ +#define PWM_SCM_SYNC0(value) (PWM_SCM_SYNC0_Msk & ((value) << PWM_SCM_SYNC0_Pos)) +#define PWM_SCM_SYNC1_Pos _U_(1) /**< (PWM_SCM) Synchronous Channel 1 Position */ +#define PWM_SCM_SYNC1_Msk (_U_(0x1) << PWM_SCM_SYNC1_Pos) /**< (PWM_SCM) Synchronous Channel 1 Mask */ +#define PWM_SCM_SYNC1(value) (PWM_SCM_SYNC1_Msk & ((value) << PWM_SCM_SYNC1_Pos)) +#define PWM_SCM_SYNC2_Pos _U_(2) /**< (PWM_SCM) Synchronous Channel 2 Position */ +#define PWM_SCM_SYNC2_Msk (_U_(0x1) << PWM_SCM_SYNC2_Pos) /**< (PWM_SCM) Synchronous Channel 2 Mask */ +#define PWM_SCM_SYNC2(value) (PWM_SCM_SYNC2_Msk & ((value) << PWM_SCM_SYNC2_Pos)) +#define PWM_SCM_SYNC3_Pos _U_(3) /**< (PWM_SCM) Synchronous Channel 3 Position */ +#define PWM_SCM_SYNC3_Msk (_U_(0x1) << PWM_SCM_SYNC3_Pos) /**< (PWM_SCM) Synchronous Channel 3 Mask */ +#define PWM_SCM_SYNC3(value) (PWM_SCM_SYNC3_Msk & ((value) << PWM_SCM_SYNC3_Pos)) +#define PWM_SCM_UPDM_Pos _U_(16) /**< (PWM_SCM) Synchronous Channels Update Mode Position */ +#define PWM_SCM_UPDM_Msk (_U_(0x3) << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Synchronous Channels Update Mode Mask */ +#define PWM_SCM_UPDM(value) (PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)) +#define PWM_SCM_UPDM_MODE0_Val _U_(0x0) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1_Val _U_(0x1) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2_Val _U_(0x2) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE0 (PWM_SCM_UPDM_MODE0_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE1 (PWM_SCM_UPDM_MODE1_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE2 (PWM_SCM_UPDM_MODE2_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels Position */ +#define PWM_SCM_PTRM_Pos _U_(20) /**< (PWM_SCM) DMA Controller Transfer Request Mode Position */ +#define PWM_SCM_PTRM_Msk (_U_(0x1) << PWM_SCM_PTRM_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Mode Mask */ +#define PWM_SCM_PTRM(value) (PWM_SCM_PTRM_Msk & ((value) << PWM_SCM_PTRM_Pos)) +#define PWM_SCM_PTRCS_Pos _U_(21) /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Position */ +#define PWM_SCM_PTRCS_Msk (_U_(0x7) << PWM_SCM_PTRCS_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Mask */ +#define PWM_SCM_PTRCS(value) (PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)) +#define PWM_SCM_Msk _U_(0x00F3000F) /**< (PWM_SCM) Register Mask */ + +#define PWM_SCM_SYNC_Pos _U_(0) /**< (PWM_SCM Position) Synchronous Channel x */ +#define PWM_SCM_SYNC_Msk (_U_(0xF) << PWM_SCM_SYNC_Pos) /**< (PWM_SCM Mask) SYNC */ +#define PWM_SCM_SYNC(value) (PWM_SCM_SYNC_Msk & ((value) << PWM_SCM_SYNC_Pos)) + +/* -------- PWM_DMAR : (PWM Offset: 0x24) ( /W 32) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos _U_(0) /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Position */ +#define PWM_DMAR_DMADUTY_Msk (_U_(0xFFFFFF) << PWM_DMAR_DMADUTY_Pos) /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Mask */ +#define PWM_DMAR_DMADUTY(value) (PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)) +#define PWM_DMAR_Msk _U_(0x00FFFFFF) /**< (PWM_DMAR) Register Mask */ + + +/* -------- PWM_SCUC : (PWM Offset: 0x28) (R/W 32) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK_Pos _U_(0) /**< (PWM_SCUC) Synchronous Channels Update Unlock Position */ +#define PWM_SCUC_UPDULOCK_Msk (_U_(0x1) << PWM_SCUC_UPDULOCK_Pos) /**< (PWM_SCUC) Synchronous Channels Update Unlock Mask */ +#define PWM_SCUC_UPDULOCK(value) (PWM_SCUC_UPDULOCK_Msk & ((value) << PWM_SCUC_UPDULOCK_Pos)) +#define PWM_SCUC_Msk _U_(0x00000001) /**< (PWM_SCUC) Register Mask */ + + +/* -------- PWM_SCUP : (PWM Offset: 0x2C) (R/W 32) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos _U_(0) /**< (PWM_SCUP) Update Period Position */ +#define PWM_SCUP_UPR_Msk (_U_(0xF) << PWM_SCUP_UPR_Pos) /**< (PWM_SCUP) Update Period Mask */ +#define PWM_SCUP_UPR(value) (PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)) +#define PWM_SCUP_UPRCNT_Pos _U_(4) /**< (PWM_SCUP) Update Period Counter Position */ +#define PWM_SCUP_UPRCNT_Msk (_U_(0xF) << PWM_SCUP_UPRCNT_Pos) /**< (PWM_SCUP) Update Period Counter Mask */ +#define PWM_SCUP_UPRCNT(value) (PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)) +#define PWM_SCUP_Msk _U_(0x000000FF) /**< (PWM_SCUP) Register Mask */ + + +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) ( /W 32) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos _U_(0) /**< (PWM_SCUPUPD) Update Period Update Position */ +#define PWM_SCUPUPD_UPRUPD_Msk (_U_(0xF) << PWM_SCUPUPD_UPRUPD_Pos) /**< (PWM_SCUPUPD) Update Period Update Mask */ +#define PWM_SCUPUPD_UPRUPD(value) (PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)) +#define PWM_SCUPUPD_Msk _U_(0x0000000F) /**< (PWM_SCUPUPD) Register Mask */ + + +/* -------- PWM_IER2 : (PWM Offset: 0x34) ( /W 32) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY_Pos _U_(0) /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Position */ +#define PWM_IER2_WRDY_Msk (_U_(0x1) << PWM_IER2_WRDY_Pos) /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Mask */ +#define PWM_IER2_WRDY(value) (PWM_IER2_WRDY_Msk & ((value) << PWM_IER2_WRDY_Pos)) +#define PWM_IER2_UNRE_Pos _U_(3) /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Position */ +#define PWM_IER2_UNRE_Msk (_U_(0x1) << PWM_IER2_UNRE_Pos) /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Mask */ +#define PWM_IER2_UNRE(value) (PWM_IER2_UNRE_Msk & ((value) << PWM_IER2_UNRE_Pos)) +#define PWM_IER2_CMPM0_Pos _U_(8) /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM0_Msk (_U_(0x1) << PWM_IER2_CMPM0_Pos) /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM0(value) (PWM_IER2_CMPM0_Msk & ((value) << PWM_IER2_CMPM0_Pos)) +#define PWM_IER2_CMPM1_Pos _U_(9) /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM1_Msk (_U_(0x1) << PWM_IER2_CMPM1_Pos) /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM1(value) (PWM_IER2_CMPM1_Msk & ((value) << PWM_IER2_CMPM1_Pos)) +#define PWM_IER2_CMPM2_Pos _U_(10) /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM2_Msk (_U_(0x1) << PWM_IER2_CMPM2_Pos) /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM2(value) (PWM_IER2_CMPM2_Msk & ((value) << PWM_IER2_CMPM2_Pos)) +#define PWM_IER2_CMPM3_Pos _U_(11) /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM3_Msk (_U_(0x1) << PWM_IER2_CMPM3_Pos) /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM3(value) (PWM_IER2_CMPM3_Msk & ((value) << PWM_IER2_CMPM3_Pos)) +#define PWM_IER2_CMPM4_Pos _U_(12) /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM4_Msk (_U_(0x1) << PWM_IER2_CMPM4_Pos) /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM4(value) (PWM_IER2_CMPM4_Msk & ((value) << PWM_IER2_CMPM4_Pos)) +#define PWM_IER2_CMPM5_Pos _U_(13) /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM5_Msk (_U_(0x1) << PWM_IER2_CMPM5_Pos) /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM5(value) (PWM_IER2_CMPM5_Msk & ((value) << PWM_IER2_CMPM5_Pos)) +#define PWM_IER2_CMPM6_Pos _U_(14) /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM6_Msk (_U_(0x1) << PWM_IER2_CMPM6_Pos) /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM6(value) (PWM_IER2_CMPM6_Msk & ((value) << PWM_IER2_CMPM6_Pos)) +#define PWM_IER2_CMPM7_Pos _U_(15) /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM7_Msk (_U_(0x1) << PWM_IER2_CMPM7_Pos) /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM7(value) (PWM_IER2_CMPM7_Msk & ((value) << PWM_IER2_CMPM7_Pos)) +#define PWM_IER2_CMPU0_Pos _U_(16) /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU0_Msk (_U_(0x1) << PWM_IER2_CMPU0_Pos) /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU0(value) (PWM_IER2_CMPU0_Msk & ((value) << PWM_IER2_CMPU0_Pos)) +#define PWM_IER2_CMPU1_Pos _U_(17) /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU1_Msk (_U_(0x1) << PWM_IER2_CMPU1_Pos) /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU1(value) (PWM_IER2_CMPU1_Msk & ((value) << PWM_IER2_CMPU1_Pos)) +#define PWM_IER2_CMPU2_Pos _U_(18) /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU2_Msk (_U_(0x1) << PWM_IER2_CMPU2_Pos) /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU2(value) (PWM_IER2_CMPU2_Msk & ((value) << PWM_IER2_CMPU2_Pos)) +#define PWM_IER2_CMPU3_Pos _U_(19) /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU3_Msk (_U_(0x1) << PWM_IER2_CMPU3_Pos) /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU3(value) (PWM_IER2_CMPU3_Msk & ((value) << PWM_IER2_CMPU3_Pos)) +#define PWM_IER2_CMPU4_Pos _U_(20) /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU4_Msk (_U_(0x1) << PWM_IER2_CMPU4_Pos) /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU4(value) (PWM_IER2_CMPU4_Msk & ((value) << PWM_IER2_CMPU4_Pos)) +#define PWM_IER2_CMPU5_Pos _U_(21) /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU5_Msk (_U_(0x1) << PWM_IER2_CMPU5_Pos) /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU5(value) (PWM_IER2_CMPU5_Msk & ((value) << PWM_IER2_CMPU5_Pos)) +#define PWM_IER2_CMPU6_Pos _U_(22) /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU6_Msk (_U_(0x1) << PWM_IER2_CMPU6_Pos) /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU6(value) (PWM_IER2_CMPU6_Msk & ((value) << PWM_IER2_CMPU6_Pos)) +#define PWM_IER2_CMPU7_Pos _U_(23) /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU7_Msk (_U_(0x1) << PWM_IER2_CMPU7_Pos) /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU7(value) (PWM_IER2_CMPU7_Msk & ((value) << PWM_IER2_CMPU7_Pos)) +#define PWM_IER2_Msk _U_(0x00FFFF09) /**< (PWM_IER2) Register Mask */ + +#define PWM_IER2_CMPM_Pos _U_(8) /**< (PWM_IER2 Position) Comparison x Match Interrupt Enable */ +#define PWM_IER2_CMPM_Msk (_U_(0xFF) << PWM_IER2_CMPM_Pos) /**< (PWM_IER2 Mask) CMPM */ +#define PWM_IER2_CMPM(value) (PWM_IER2_CMPM_Msk & ((value) << PWM_IER2_CMPM_Pos)) +#define PWM_IER2_CMPU_Pos _U_(16) /**< (PWM_IER2 Position) Comparison 7 Update Interrupt Enable */ +#define PWM_IER2_CMPU_Msk (_U_(0xFF) << PWM_IER2_CMPU_Pos) /**< (PWM_IER2 Mask) CMPU */ +#define PWM_IER2_CMPU(value) (PWM_IER2_CMPU_Msk & ((value) << PWM_IER2_CMPU_Pos)) + +/* -------- PWM_IDR2 : (PWM Offset: 0x38) ( /W 32) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY_Pos _U_(0) /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Position */ +#define PWM_IDR2_WRDY_Msk (_U_(0x1) << PWM_IDR2_WRDY_Pos) /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Mask */ +#define PWM_IDR2_WRDY(value) (PWM_IDR2_WRDY_Msk & ((value) << PWM_IDR2_WRDY_Pos)) +#define PWM_IDR2_UNRE_Pos _U_(3) /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Position */ +#define PWM_IDR2_UNRE_Msk (_U_(0x1) << PWM_IDR2_UNRE_Pos) /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Mask */ +#define PWM_IDR2_UNRE(value) (PWM_IDR2_UNRE_Msk & ((value) << PWM_IDR2_UNRE_Pos)) +#define PWM_IDR2_CMPM0_Pos _U_(8) /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM0_Msk (_U_(0x1) << PWM_IDR2_CMPM0_Pos) /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM0(value) (PWM_IDR2_CMPM0_Msk & ((value) << PWM_IDR2_CMPM0_Pos)) +#define PWM_IDR2_CMPM1_Pos _U_(9) /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM1_Msk (_U_(0x1) << PWM_IDR2_CMPM1_Pos) /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM1(value) (PWM_IDR2_CMPM1_Msk & ((value) << PWM_IDR2_CMPM1_Pos)) +#define PWM_IDR2_CMPM2_Pos _U_(10) /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM2_Msk (_U_(0x1) << PWM_IDR2_CMPM2_Pos) /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM2(value) (PWM_IDR2_CMPM2_Msk & ((value) << PWM_IDR2_CMPM2_Pos)) +#define PWM_IDR2_CMPM3_Pos _U_(11) /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM3_Msk (_U_(0x1) << PWM_IDR2_CMPM3_Pos) /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM3(value) (PWM_IDR2_CMPM3_Msk & ((value) << PWM_IDR2_CMPM3_Pos)) +#define PWM_IDR2_CMPM4_Pos _U_(12) /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM4_Msk (_U_(0x1) << PWM_IDR2_CMPM4_Pos) /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM4(value) (PWM_IDR2_CMPM4_Msk & ((value) << PWM_IDR2_CMPM4_Pos)) +#define PWM_IDR2_CMPM5_Pos _U_(13) /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM5_Msk (_U_(0x1) << PWM_IDR2_CMPM5_Pos) /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM5(value) (PWM_IDR2_CMPM5_Msk & ((value) << PWM_IDR2_CMPM5_Pos)) +#define PWM_IDR2_CMPM6_Pos _U_(14) /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM6_Msk (_U_(0x1) << PWM_IDR2_CMPM6_Pos) /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM6(value) (PWM_IDR2_CMPM6_Msk & ((value) << PWM_IDR2_CMPM6_Pos)) +#define PWM_IDR2_CMPM7_Pos _U_(15) /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM7_Msk (_U_(0x1) << PWM_IDR2_CMPM7_Pos) /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM7(value) (PWM_IDR2_CMPM7_Msk & ((value) << PWM_IDR2_CMPM7_Pos)) +#define PWM_IDR2_CMPU0_Pos _U_(16) /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU0_Msk (_U_(0x1) << PWM_IDR2_CMPU0_Pos) /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU0(value) (PWM_IDR2_CMPU0_Msk & ((value) << PWM_IDR2_CMPU0_Pos)) +#define PWM_IDR2_CMPU1_Pos _U_(17) /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU1_Msk (_U_(0x1) << PWM_IDR2_CMPU1_Pos) /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU1(value) (PWM_IDR2_CMPU1_Msk & ((value) << PWM_IDR2_CMPU1_Pos)) +#define PWM_IDR2_CMPU2_Pos _U_(18) /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU2_Msk (_U_(0x1) << PWM_IDR2_CMPU2_Pos) /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU2(value) (PWM_IDR2_CMPU2_Msk & ((value) << PWM_IDR2_CMPU2_Pos)) +#define PWM_IDR2_CMPU3_Pos _U_(19) /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU3_Msk (_U_(0x1) << PWM_IDR2_CMPU3_Pos) /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU3(value) (PWM_IDR2_CMPU3_Msk & ((value) << PWM_IDR2_CMPU3_Pos)) +#define PWM_IDR2_CMPU4_Pos _U_(20) /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU4_Msk (_U_(0x1) << PWM_IDR2_CMPU4_Pos) /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU4(value) (PWM_IDR2_CMPU4_Msk & ((value) << PWM_IDR2_CMPU4_Pos)) +#define PWM_IDR2_CMPU5_Pos _U_(21) /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU5_Msk (_U_(0x1) << PWM_IDR2_CMPU5_Pos) /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU5(value) (PWM_IDR2_CMPU5_Msk & ((value) << PWM_IDR2_CMPU5_Pos)) +#define PWM_IDR2_CMPU6_Pos _U_(22) /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU6_Msk (_U_(0x1) << PWM_IDR2_CMPU6_Pos) /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU6(value) (PWM_IDR2_CMPU6_Msk & ((value) << PWM_IDR2_CMPU6_Pos)) +#define PWM_IDR2_CMPU7_Pos _U_(23) /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU7_Msk (_U_(0x1) << PWM_IDR2_CMPU7_Pos) /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU7(value) (PWM_IDR2_CMPU7_Msk & ((value) << PWM_IDR2_CMPU7_Pos)) +#define PWM_IDR2_Msk _U_(0x00FFFF09) /**< (PWM_IDR2) Register Mask */ + +#define PWM_IDR2_CMPM_Pos _U_(8) /**< (PWM_IDR2 Position) Comparison x Match Interrupt Disable */ +#define PWM_IDR2_CMPM_Msk (_U_(0xFF) << PWM_IDR2_CMPM_Pos) /**< (PWM_IDR2 Mask) CMPM */ +#define PWM_IDR2_CMPM(value) (PWM_IDR2_CMPM_Msk & ((value) << PWM_IDR2_CMPM_Pos)) +#define PWM_IDR2_CMPU_Pos _U_(16) /**< (PWM_IDR2 Position) Comparison 7 Update Interrupt Disable */ +#define PWM_IDR2_CMPU_Msk (_U_(0xFF) << PWM_IDR2_CMPU_Pos) /**< (PWM_IDR2 Mask) CMPU */ +#define PWM_IDR2_CMPU(value) (PWM_IDR2_CMPU_Msk & ((value) << PWM_IDR2_CMPU_Pos)) + +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) ( R/ 32) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY_Pos _U_(0) /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Position */ +#define PWM_IMR2_WRDY_Msk (_U_(0x1) << PWM_IMR2_WRDY_Pos) /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Mask */ +#define PWM_IMR2_WRDY(value) (PWM_IMR2_WRDY_Msk & ((value) << PWM_IMR2_WRDY_Pos)) +#define PWM_IMR2_UNRE_Pos _U_(3) /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Position */ +#define PWM_IMR2_UNRE_Msk (_U_(0x1) << PWM_IMR2_UNRE_Pos) /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Mask */ +#define PWM_IMR2_UNRE(value) (PWM_IMR2_UNRE_Msk & ((value) << PWM_IMR2_UNRE_Pos)) +#define PWM_IMR2_CMPM0_Pos _U_(8) /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM0_Msk (_U_(0x1) << PWM_IMR2_CMPM0_Pos) /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM0(value) (PWM_IMR2_CMPM0_Msk & ((value) << PWM_IMR2_CMPM0_Pos)) +#define PWM_IMR2_CMPM1_Pos _U_(9) /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM1_Msk (_U_(0x1) << PWM_IMR2_CMPM1_Pos) /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM1(value) (PWM_IMR2_CMPM1_Msk & ((value) << PWM_IMR2_CMPM1_Pos)) +#define PWM_IMR2_CMPM2_Pos _U_(10) /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM2_Msk (_U_(0x1) << PWM_IMR2_CMPM2_Pos) /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM2(value) (PWM_IMR2_CMPM2_Msk & ((value) << PWM_IMR2_CMPM2_Pos)) +#define PWM_IMR2_CMPM3_Pos _U_(11) /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM3_Msk (_U_(0x1) << PWM_IMR2_CMPM3_Pos) /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM3(value) (PWM_IMR2_CMPM3_Msk & ((value) << PWM_IMR2_CMPM3_Pos)) +#define PWM_IMR2_CMPM4_Pos _U_(12) /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM4_Msk (_U_(0x1) << PWM_IMR2_CMPM4_Pos) /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM4(value) (PWM_IMR2_CMPM4_Msk & ((value) << PWM_IMR2_CMPM4_Pos)) +#define PWM_IMR2_CMPM5_Pos _U_(13) /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM5_Msk (_U_(0x1) << PWM_IMR2_CMPM5_Pos) /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM5(value) (PWM_IMR2_CMPM5_Msk & ((value) << PWM_IMR2_CMPM5_Pos)) +#define PWM_IMR2_CMPM6_Pos _U_(14) /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM6_Msk (_U_(0x1) << PWM_IMR2_CMPM6_Pos) /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM6(value) (PWM_IMR2_CMPM6_Msk & ((value) << PWM_IMR2_CMPM6_Pos)) +#define PWM_IMR2_CMPM7_Pos _U_(15) /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM7_Msk (_U_(0x1) << PWM_IMR2_CMPM7_Pos) /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM7(value) (PWM_IMR2_CMPM7_Msk & ((value) << PWM_IMR2_CMPM7_Pos)) +#define PWM_IMR2_CMPU0_Pos _U_(16) /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU0_Msk (_U_(0x1) << PWM_IMR2_CMPU0_Pos) /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU0(value) (PWM_IMR2_CMPU0_Msk & ((value) << PWM_IMR2_CMPU0_Pos)) +#define PWM_IMR2_CMPU1_Pos _U_(17) /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU1_Msk (_U_(0x1) << PWM_IMR2_CMPU1_Pos) /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU1(value) (PWM_IMR2_CMPU1_Msk & ((value) << PWM_IMR2_CMPU1_Pos)) +#define PWM_IMR2_CMPU2_Pos _U_(18) /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU2_Msk (_U_(0x1) << PWM_IMR2_CMPU2_Pos) /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU2(value) (PWM_IMR2_CMPU2_Msk & ((value) << PWM_IMR2_CMPU2_Pos)) +#define PWM_IMR2_CMPU3_Pos _U_(19) /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU3_Msk (_U_(0x1) << PWM_IMR2_CMPU3_Pos) /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU3(value) (PWM_IMR2_CMPU3_Msk & ((value) << PWM_IMR2_CMPU3_Pos)) +#define PWM_IMR2_CMPU4_Pos _U_(20) /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU4_Msk (_U_(0x1) << PWM_IMR2_CMPU4_Pos) /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU4(value) (PWM_IMR2_CMPU4_Msk & ((value) << PWM_IMR2_CMPU4_Pos)) +#define PWM_IMR2_CMPU5_Pos _U_(21) /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU5_Msk (_U_(0x1) << PWM_IMR2_CMPU5_Pos) /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU5(value) (PWM_IMR2_CMPU5_Msk & ((value) << PWM_IMR2_CMPU5_Pos)) +#define PWM_IMR2_CMPU6_Pos _U_(22) /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU6_Msk (_U_(0x1) << PWM_IMR2_CMPU6_Pos) /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU6(value) (PWM_IMR2_CMPU6_Msk & ((value) << PWM_IMR2_CMPU6_Pos)) +#define PWM_IMR2_CMPU7_Pos _U_(23) /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU7_Msk (_U_(0x1) << PWM_IMR2_CMPU7_Pos) /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU7(value) (PWM_IMR2_CMPU7_Msk & ((value) << PWM_IMR2_CMPU7_Pos)) +#define PWM_IMR2_Msk _U_(0x00FFFF09) /**< (PWM_IMR2) Register Mask */ + +#define PWM_IMR2_CMPM_Pos _U_(8) /**< (PWM_IMR2 Position) Comparison x Match Interrupt Mask */ +#define PWM_IMR2_CMPM_Msk (_U_(0xFF) << PWM_IMR2_CMPM_Pos) /**< (PWM_IMR2 Mask) CMPM */ +#define PWM_IMR2_CMPM(value) (PWM_IMR2_CMPM_Msk & ((value) << PWM_IMR2_CMPM_Pos)) +#define PWM_IMR2_CMPU_Pos _U_(16) /**< (PWM_IMR2 Position) Comparison 7 Update Interrupt Mask */ +#define PWM_IMR2_CMPU_Msk (_U_(0xFF) << PWM_IMR2_CMPU_Pos) /**< (PWM_IMR2 Mask) CMPU */ +#define PWM_IMR2_CMPU(value) (PWM_IMR2_CMPU_Msk & ((value) << PWM_IMR2_CMPU_Pos)) + +/* -------- PWM_ISR2 : (PWM Offset: 0x40) ( R/ 32) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY_Pos _U_(0) /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Position */ +#define PWM_ISR2_WRDY_Msk (_U_(0x1) << PWM_ISR2_WRDY_Pos) /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Mask */ +#define PWM_ISR2_WRDY(value) (PWM_ISR2_WRDY_Msk & ((value) << PWM_ISR2_WRDY_Pos)) +#define PWM_ISR2_UNRE_Pos _U_(3) /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Position */ +#define PWM_ISR2_UNRE_Msk (_U_(0x1) << PWM_ISR2_UNRE_Pos) /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Mask */ +#define PWM_ISR2_UNRE(value) (PWM_ISR2_UNRE_Msk & ((value) << PWM_ISR2_UNRE_Pos)) +#define PWM_ISR2_CMPM0_Pos _U_(8) /**< (PWM_ISR2) Comparison 0 Match Position */ +#define PWM_ISR2_CMPM0_Msk (_U_(0x1) << PWM_ISR2_CMPM0_Pos) /**< (PWM_ISR2) Comparison 0 Match Mask */ +#define PWM_ISR2_CMPM0(value) (PWM_ISR2_CMPM0_Msk & ((value) << PWM_ISR2_CMPM0_Pos)) +#define PWM_ISR2_CMPM1_Pos _U_(9) /**< (PWM_ISR2) Comparison 1 Match Position */ +#define PWM_ISR2_CMPM1_Msk (_U_(0x1) << PWM_ISR2_CMPM1_Pos) /**< (PWM_ISR2) Comparison 1 Match Mask */ +#define PWM_ISR2_CMPM1(value) (PWM_ISR2_CMPM1_Msk & ((value) << PWM_ISR2_CMPM1_Pos)) +#define PWM_ISR2_CMPM2_Pos _U_(10) /**< (PWM_ISR2) Comparison 2 Match Position */ +#define PWM_ISR2_CMPM2_Msk (_U_(0x1) << PWM_ISR2_CMPM2_Pos) /**< (PWM_ISR2) Comparison 2 Match Mask */ +#define PWM_ISR2_CMPM2(value) (PWM_ISR2_CMPM2_Msk & ((value) << PWM_ISR2_CMPM2_Pos)) +#define PWM_ISR2_CMPM3_Pos _U_(11) /**< (PWM_ISR2) Comparison 3 Match Position */ +#define PWM_ISR2_CMPM3_Msk (_U_(0x1) << PWM_ISR2_CMPM3_Pos) /**< (PWM_ISR2) Comparison 3 Match Mask */ +#define PWM_ISR2_CMPM3(value) (PWM_ISR2_CMPM3_Msk & ((value) << PWM_ISR2_CMPM3_Pos)) +#define PWM_ISR2_CMPM4_Pos _U_(12) /**< (PWM_ISR2) Comparison 4 Match Position */ +#define PWM_ISR2_CMPM4_Msk (_U_(0x1) << PWM_ISR2_CMPM4_Pos) /**< (PWM_ISR2) Comparison 4 Match Mask */ +#define PWM_ISR2_CMPM4(value) (PWM_ISR2_CMPM4_Msk & ((value) << PWM_ISR2_CMPM4_Pos)) +#define PWM_ISR2_CMPM5_Pos _U_(13) /**< (PWM_ISR2) Comparison 5 Match Position */ +#define PWM_ISR2_CMPM5_Msk (_U_(0x1) << PWM_ISR2_CMPM5_Pos) /**< (PWM_ISR2) Comparison 5 Match Mask */ +#define PWM_ISR2_CMPM5(value) (PWM_ISR2_CMPM5_Msk & ((value) << PWM_ISR2_CMPM5_Pos)) +#define PWM_ISR2_CMPM6_Pos _U_(14) /**< (PWM_ISR2) Comparison 6 Match Position */ +#define PWM_ISR2_CMPM6_Msk (_U_(0x1) << PWM_ISR2_CMPM6_Pos) /**< (PWM_ISR2) Comparison 6 Match Mask */ +#define PWM_ISR2_CMPM6(value) (PWM_ISR2_CMPM6_Msk & ((value) << PWM_ISR2_CMPM6_Pos)) +#define PWM_ISR2_CMPM7_Pos _U_(15) /**< (PWM_ISR2) Comparison 7 Match Position */ +#define PWM_ISR2_CMPM7_Msk (_U_(0x1) << PWM_ISR2_CMPM7_Pos) /**< (PWM_ISR2) Comparison 7 Match Mask */ +#define PWM_ISR2_CMPM7(value) (PWM_ISR2_CMPM7_Msk & ((value) << PWM_ISR2_CMPM7_Pos)) +#define PWM_ISR2_CMPU0_Pos _U_(16) /**< (PWM_ISR2) Comparison 0 Update Position */ +#define PWM_ISR2_CMPU0_Msk (_U_(0x1) << PWM_ISR2_CMPU0_Pos) /**< (PWM_ISR2) Comparison 0 Update Mask */ +#define PWM_ISR2_CMPU0(value) (PWM_ISR2_CMPU0_Msk & ((value) << PWM_ISR2_CMPU0_Pos)) +#define PWM_ISR2_CMPU1_Pos _U_(17) /**< (PWM_ISR2) Comparison 1 Update Position */ +#define PWM_ISR2_CMPU1_Msk (_U_(0x1) << PWM_ISR2_CMPU1_Pos) /**< (PWM_ISR2) Comparison 1 Update Mask */ +#define PWM_ISR2_CMPU1(value) (PWM_ISR2_CMPU1_Msk & ((value) << PWM_ISR2_CMPU1_Pos)) +#define PWM_ISR2_CMPU2_Pos _U_(18) /**< (PWM_ISR2) Comparison 2 Update Position */ +#define PWM_ISR2_CMPU2_Msk (_U_(0x1) << PWM_ISR2_CMPU2_Pos) /**< (PWM_ISR2) Comparison 2 Update Mask */ +#define PWM_ISR2_CMPU2(value) (PWM_ISR2_CMPU2_Msk & ((value) << PWM_ISR2_CMPU2_Pos)) +#define PWM_ISR2_CMPU3_Pos _U_(19) /**< (PWM_ISR2) Comparison 3 Update Position */ +#define PWM_ISR2_CMPU3_Msk (_U_(0x1) << PWM_ISR2_CMPU3_Pos) /**< (PWM_ISR2) Comparison 3 Update Mask */ +#define PWM_ISR2_CMPU3(value) (PWM_ISR2_CMPU3_Msk & ((value) << PWM_ISR2_CMPU3_Pos)) +#define PWM_ISR2_CMPU4_Pos _U_(20) /**< (PWM_ISR2) Comparison 4 Update Position */ +#define PWM_ISR2_CMPU4_Msk (_U_(0x1) << PWM_ISR2_CMPU4_Pos) /**< (PWM_ISR2) Comparison 4 Update Mask */ +#define PWM_ISR2_CMPU4(value) (PWM_ISR2_CMPU4_Msk & ((value) << PWM_ISR2_CMPU4_Pos)) +#define PWM_ISR2_CMPU5_Pos _U_(21) /**< (PWM_ISR2) Comparison 5 Update Position */ +#define PWM_ISR2_CMPU5_Msk (_U_(0x1) << PWM_ISR2_CMPU5_Pos) /**< (PWM_ISR2) Comparison 5 Update Mask */ +#define PWM_ISR2_CMPU5(value) (PWM_ISR2_CMPU5_Msk & ((value) << PWM_ISR2_CMPU5_Pos)) +#define PWM_ISR2_CMPU6_Pos _U_(22) /**< (PWM_ISR2) Comparison 6 Update Position */ +#define PWM_ISR2_CMPU6_Msk (_U_(0x1) << PWM_ISR2_CMPU6_Pos) /**< (PWM_ISR2) Comparison 6 Update Mask */ +#define PWM_ISR2_CMPU6(value) (PWM_ISR2_CMPU6_Msk & ((value) << PWM_ISR2_CMPU6_Pos)) +#define PWM_ISR2_CMPU7_Pos _U_(23) /**< (PWM_ISR2) Comparison 7 Update Position */ +#define PWM_ISR2_CMPU7_Msk (_U_(0x1) << PWM_ISR2_CMPU7_Pos) /**< (PWM_ISR2) Comparison 7 Update Mask */ +#define PWM_ISR2_CMPU7(value) (PWM_ISR2_CMPU7_Msk & ((value) << PWM_ISR2_CMPU7_Pos)) +#define PWM_ISR2_Msk _U_(0x00FFFF09) /**< (PWM_ISR2) Register Mask */ + +#define PWM_ISR2_CMPM_Pos _U_(8) /**< (PWM_ISR2 Position) Comparison x Match */ +#define PWM_ISR2_CMPM_Msk (_U_(0xFF) << PWM_ISR2_CMPM_Pos) /**< (PWM_ISR2 Mask) CMPM */ +#define PWM_ISR2_CMPM(value) (PWM_ISR2_CMPM_Msk & ((value) << PWM_ISR2_CMPM_Pos)) +#define PWM_ISR2_CMPU_Pos _U_(16) /**< (PWM_ISR2 Position) Comparison 7 Update */ +#define PWM_ISR2_CMPU_Msk (_U_(0xFF) << PWM_ISR2_CMPU_Pos) /**< (PWM_ISR2 Mask) CMPU */ +#define PWM_ISR2_CMPU(value) (PWM_ISR2_CMPU_Msk & ((value) << PWM_ISR2_CMPU_Pos)) + +/* -------- PWM_OOV : (PWM Offset: 0x44) (R/W 32) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0_Pos _U_(0) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Position */ +#define PWM_OOV_OOVH0_Msk (_U_(0x1) << PWM_OOV_OOVH0_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Mask */ +#define PWM_OOV_OOVH0(value) (PWM_OOV_OOVH0_Msk & ((value) << PWM_OOV_OOVH0_Pos)) +#define PWM_OOV_OOVH1_Pos _U_(1) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Position */ +#define PWM_OOV_OOVH1_Msk (_U_(0x1) << PWM_OOV_OOVH1_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Mask */ +#define PWM_OOV_OOVH1(value) (PWM_OOV_OOVH1_Msk & ((value) << PWM_OOV_OOVH1_Pos)) +#define PWM_OOV_OOVH2_Pos _U_(2) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Position */ +#define PWM_OOV_OOVH2_Msk (_U_(0x1) << PWM_OOV_OOVH2_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Mask */ +#define PWM_OOV_OOVH2(value) (PWM_OOV_OOVH2_Msk & ((value) << PWM_OOV_OOVH2_Pos)) +#define PWM_OOV_OOVH3_Pos _U_(3) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Position */ +#define PWM_OOV_OOVH3_Msk (_U_(0x1) << PWM_OOV_OOVH3_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Mask */ +#define PWM_OOV_OOVH3(value) (PWM_OOV_OOVH3_Msk & ((value) << PWM_OOV_OOVH3_Pos)) +#define PWM_OOV_OOVL0_Pos _U_(16) /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Position */ +#define PWM_OOV_OOVL0_Msk (_U_(0x1) << PWM_OOV_OOVL0_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Mask */ +#define PWM_OOV_OOVL0(value) (PWM_OOV_OOVL0_Msk & ((value) << PWM_OOV_OOVL0_Pos)) +#define PWM_OOV_OOVL1_Pos _U_(17) /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Position */ +#define PWM_OOV_OOVL1_Msk (_U_(0x1) << PWM_OOV_OOVL1_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Mask */ +#define PWM_OOV_OOVL1(value) (PWM_OOV_OOVL1_Msk & ((value) << PWM_OOV_OOVL1_Pos)) +#define PWM_OOV_OOVL2_Pos _U_(18) /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Position */ +#define PWM_OOV_OOVL2_Msk (_U_(0x1) << PWM_OOV_OOVL2_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Mask */ +#define PWM_OOV_OOVL2(value) (PWM_OOV_OOVL2_Msk & ((value) << PWM_OOV_OOVL2_Pos)) +#define PWM_OOV_OOVL3_Pos _U_(19) /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Position */ +#define PWM_OOV_OOVL3_Msk (_U_(0x1) << PWM_OOV_OOVL3_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Mask */ +#define PWM_OOV_OOVL3(value) (PWM_OOV_OOVL3_Msk & ((value) << PWM_OOV_OOVL3_Pos)) +#define PWM_OOV_Msk _U_(0x000F000F) /**< (PWM_OOV) Register Mask */ + +#define PWM_OOV_OOVH_Pos _U_(0) /**< (PWM_OOV Position) Output Override Value for PWMH output of the channel x */ +#define PWM_OOV_OOVH_Msk (_U_(0xF) << PWM_OOV_OOVH_Pos) /**< (PWM_OOV Mask) OOVH */ +#define PWM_OOV_OOVH(value) (PWM_OOV_OOVH_Msk & ((value) << PWM_OOV_OOVH_Pos)) +#define PWM_OOV_OOVL_Pos _U_(16) /**< (PWM_OOV Position) Output Override Value for PWML output of the channel 3 */ +#define PWM_OOV_OOVL_Msk (_U_(0xF) << PWM_OOV_OOVL_Pos) /**< (PWM_OOV Mask) OOVL */ +#define PWM_OOV_OOVL(value) (PWM_OOV_OOVL_Msk & ((value) << PWM_OOV_OOVL_Pos)) + +/* -------- PWM_OS : (PWM Offset: 0x48) (R/W 32) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0_Pos _U_(0) /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Position */ +#define PWM_OS_OSH0_Msk (_U_(0x1) << PWM_OS_OSH0_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Mask */ +#define PWM_OS_OSH0(value) (PWM_OS_OSH0_Msk & ((value) << PWM_OS_OSH0_Pos)) +#define PWM_OS_OSH1_Pos _U_(1) /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Position */ +#define PWM_OS_OSH1_Msk (_U_(0x1) << PWM_OS_OSH1_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Mask */ +#define PWM_OS_OSH1(value) (PWM_OS_OSH1_Msk & ((value) << PWM_OS_OSH1_Pos)) +#define PWM_OS_OSH2_Pos _U_(2) /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Position */ +#define PWM_OS_OSH2_Msk (_U_(0x1) << PWM_OS_OSH2_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Mask */ +#define PWM_OS_OSH2(value) (PWM_OS_OSH2_Msk & ((value) << PWM_OS_OSH2_Pos)) +#define PWM_OS_OSH3_Pos _U_(3) /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Position */ +#define PWM_OS_OSH3_Msk (_U_(0x1) << PWM_OS_OSH3_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Mask */ +#define PWM_OS_OSH3(value) (PWM_OS_OSH3_Msk & ((value) << PWM_OS_OSH3_Pos)) +#define PWM_OS_OSL0_Pos _U_(16) /**< (PWM_OS) Output Selection for PWML output of the channel 0 Position */ +#define PWM_OS_OSL0_Msk (_U_(0x1) << PWM_OS_OSL0_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 0 Mask */ +#define PWM_OS_OSL0(value) (PWM_OS_OSL0_Msk & ((value) << PWM_OS_OSL0_Pos)) +#define PWM_OS_OSL1_Pos _U_(17) /**< (PWM_OS) Output Selection for PWML output of the channel 1 Position */ +#define PWM_OS_OSL1_Msk (_U_(0x1) << PWM_OS_OSL1_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 1 Mask */ +#define PWM_OS_OSL1(value) (PWM_OS_OSL1_Msk & ((value) << PWM_OS_OSL1_Pos)) +#define PWM_OS_OSL2_Pos _U_(18) /**< (PWM_OS) Output Selection for PWML output of the channel 2 Position */ +#define PWM_OS_OSL2_Msk (_U_(0x1) << PWM_OS_OSL2_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 2 Mask */ +#define PWM_OS_OSL2(value) (PWM_OS_OSL2_Msk & ((value) << PWM_OS_OSL2_Pos)) +#define PWM_OS_OSL3_Pos _U_(19) /**< (PWM_OS) Output Selection for PWML output of the channel 3 Position */ +#define PWM_OS_OSL3_Msk (_U_(0x1) << PWM_OS_OSL3_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 3 Mask */ +#define PWM_OS_OSL3(value) (PWM_OS_OSL3_Msk & ((value) << PWM_OS_OSL3_Pos)) +#define PWM_OS_Msk _U_(0x000F000F) /**< (PWM_OS) Register Mask */ + +#define PWM_OS_OSH_Pos _U_(0) /**< (PWM_OS Position) Output Selection for PWMH output of the channel x */ +#define PWM_OS_OSH_Msk (_U_(0xF) << PWM_OS_OSH_Pos) /**< (PWM_OS Mask) OSH */ +#define PWM_OS_OSH(value) (PWM_OS_OSH_Msk & ((value) << PWM_OS_OSH_Pos)) +#define PWM_OS_OSL_Pos _U_(16) /**< (PWM_OS Position) Output Selection for PWML output of the channel 3 */ +#define PWM_OS_OSL_Msk (_U_(0xF) << PWM_OS_OSL_Pos) /**< (PWM_OS Mask) OSL */ +#define PWM_OS_OSL(value) (PWM_OS_OSL_Msk & ((value) << PWM_OS_OSL_Pos)) + +/* -------- PWM_OSS : (PWM Offset: 0x4C) ( /W 32) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0_Pos _U_(0) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSS_OSSH0_Msk (_U_(0x1) << PWM_OSS_OSSH0_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSS_OSSH0(value) (PWM_OSS_OSSH0_Msk & ((value) << PWM_OSS_OSSH0_Pos)) +#define PWM_OSS_OSSH1_Pos _U_(1) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSS_OSSH1_Msk (_U_(0x1) << PWM_OSS_OSSH1_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSS_OSSH1(value) (PWM_OSS_OSSH1_Msk & ((value) << PWM_OSS_OSSH1_Pos)) +#define PWM_OSS_OSSH2_Pos _U_(2) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSS_OSSH2_Msk (_U_(0x1) << PWM_OSS_OSSH2_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSS_OSSH2(value) (PWM_OSS_OSSH2_Msk & ((value) << PWM_OSS_OSSH2_Pos)) +#define PWM_OSS_OSSH3_Pos _U_(3) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSS_OSSH3_Msk (_U_(0x1) << PWM_OSS_OSSH3_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSS_OSSH3(value) (PWM_OSS_OSSH3_Msk & ((value) << PWM_OSS_OSSH3_Pos)) +#define PWM_OSS_OSSL0_Pos _U_(16) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSS_OSSL0_Msk (_U_(0x1) << PWM_OSS_OSSL0_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSS_OSSL0(value) (PWM_OSS_OSSL0_Msk & ((value) << PWM_OSS_OSSL0_Pos)) +#define PWM_OSS_OSSL1_Pos _U_(17) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSS_OSSL1_Msk (_U_(0x1) << PWM_OSS_OSSL1_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSS_OSSL1(value) (PWM_OSS_OSSL1_Msk & ((value) << PWM_OSS_OSSL1_Pos)) +#define PWM_OSS_OSSL2_Pos _U_(18) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSS_OSSL2_Msk (_U_(0x1) << PWM_OSS_OSSL2_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSS_OSSL2(value) (PWM_OSS_OSSL2_Msk & ((value) << PWM_OSS_OSSL2_Pos)) +#define PWM_OSS_OSSL3_Pos _U_(19) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSS_OSSL3_Msk (_U_(0x1) << PWM_OSS_OSSL3_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSS_OSSL3(value) (PWM_OSS_OSSL3_Msk & ((value) << PWM_OSS_OSSL3_Pos)) +#define PWM_OSS_Msk _U_(0x000F000F) /**< (PWM_OSS) Register Mask */ + +#define PWM_OSS_OSSH_Pos _U_(0) /**< (PWM_OSS Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSS_OSSH_Msk (_U_(0xF) << PWM_OSS_OSSH_Pos) /**< (PWM_OSS Mask) OSSH */ +#define PWM_OSS_OSSH(value) (PWM_OSS_OSSH_Msk & ((value) << PWM_OSS_OSSH_Pos)) +#define PWM_OSS_OSSL_Pos _U_(16) /**< (PWM_OSS Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSS_OSSL_Msk (_U_(0xF) << PWM_OSS_OSSL_Pos) /**< (PWM_OSS Mask) OSSL */ +#define PWM_OSS_OSSL(value) (PWM_OSS_OSSL_Msk & ((value) << PWM_OSS_OSSL_Pos)) + +/* -------- PWM_OSC : (PWM Offset: 0x50) ( /W 32) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0_Pos _U_(0) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSC_OSCH0_Msk (_U_(0x1) << PWM_OSC_OSCH0_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSC_OSCH0(value) (PWM_OSC_OSCH0_Msk & ((value) << PWM_OSC_OSCH0_Pos)) +#define PWM_OSC_OSCH1_Pos _U_(1) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSC_OSCH1_Msk (_U_(0x1) << PWM_OSC_OSCH1_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSC_OSCH1(value) (PWM_OSC_OSCH1_Msk & ((value) << PWM_OSC_OSCH1_Pos)) +#define PWM_OSC_OSCH2_Pos _U_(2) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSC_OSCH2_Msk (_U_(0x1) << PWM_OSC_OSCH2_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSC_OSCH2(value) (PWM_OSC_OSCH2_Msk & ((value) << PWM_OSC_OSCH2_Pos)) +#define PWM_OSC_OSCH3_Pos _U_(3) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSC_OSCH3_Msk (_U_(0x1) << PWM_OSC_OSCH3_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSC_OSCH3(value) (PWM_OSC_OSCH3_Msk & ((value) << PWM_OSC_OSCH3_Pos)) +#define PWM_OSC_OSCL0_Pos _U_(16) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSC_OSCL0_Msk (_U_(0x1) << PWM_OSC_OSCL0_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSC_OSCL0(value) (PWM_OSC_OSCL0_Msk & ((value) << PWM_OSC_OSCL0_Pos)) +#define PWM_OSC_OSCL1_Pos _U_(17) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSC_OSCL1_Msk (_U_(0x1) << PWM_OSC_OSCL1_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSC_OSCL1(value) (PWM_OSC_OSCL1_Msk & ((value) << PWM_OSC_OSCL1_Pos)) +#define PWM_OSC_OSCL2_Pos _U_(18) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSC_OSCL2_Msk (_U_(0x1) << PWM_OSC_OSCL2_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSC_OSCL2(value) (PWM_OSC_OSCL2_Msk & ((value) << PWM_OSC_OSCL2_Pos)) +#define PWM_OSC_OSCL3_Pos _U_(19) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSC_OSCL3_Msk (_U_(0x1) << PWM_OSC_OSCL3_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSC_OSCL3(value) (PWM_OSC_OSCL3_Msk & ((value) << PWM_OSC_OSCL3_Pos)) +#define PWM_OSC_Msk _U_(0x000F000F) /**< (PWM_OSC) Register Mask */ + +#define PWM_OSC_OSCH_Pos _U_(0) /**< (PWM_OSC Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSC_OSCH_Msk (_U_(0xF) << PWM_OSC_OSCH_Pos) /**< (PWM_OSC Mask) OSCH */ +#define PWM_OSC_OSCH(value) (PWM_OSC_OSCH_Msk & ((value) << PWM_OSC_OSCH_Pos)) +#define PWM_OSC_OSCL_Pos _U_(16) /**< (PWM_OSC Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSC_OSCL_Msk (_U_(0xF) << PWM_OSC_OSCL_Pos) /**< (PWM_OSC Mask) OSCL */ +#define PWM_OSC_OSCL(value) (PWM_OSC_OSCL_Msk & ((value) << PWM_OSC_OSCL_Pos)) + +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) ( /W 32) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0_Pos _U_(0) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPH0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPH0(value) (PWM_OSSUPD_OSSUPH0_Msk & ((value) << PWM_OSSUPD_OSSUPH0_Pos)) +#define PWM_OSSUPD_OSSUPH1_Pos _U_(1) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPH1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPH1(value) (PWM_OSSUPD_OSSUPH1_Msk & ((value) << PWM_OSSUPD_OSSUPH1_Pos)) +#define PWM_OSSUPD_OSSUPH2_Pos _U_(2) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPH2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPH2(value) (PWM_OSSUPD_OSSUPH2_Msk & ((value) << PWM_OSSUPD_OSSUPH2_Pos)) +#define PWM_OSSUPD_OSSUPH3_Pos _U_(3) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPH3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPH3(value) (PWM_OSSUPD_OSSUPH3_Msk & ((value) << PWM_OSSUPD_OSSUPH3_Pos)) +#define PWM_OSSUPD_OSSUPL0_Pos _U_(16) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPL0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPL0(value) (PWM_OSSUPD_OSSUPL0_Msk & ((value) << PWM_OSSUPD_OSSUPL0_Pos)) +#define PWM_OSSUPD_OSSUPL1_Pos _U_(17) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPL1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPL1(value) (PWM_OSSUPD_OSSUPL1_Msk & ((value) << PWM_OSSUPD_OSSUPL1_Pos)) +#define PWM_OSSUPD_OSSUPL2_Pos _U_(18) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPL2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPL2(value) (PWM_OSSUPD_OSSUPL2_Msk & ((value) << PWM_OSSUPD_OSSUPL2_Pos)) +#define PWM_OSSUPD_OSSUPL3_Pos _U_(19) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPL3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPL3(value) (PWM_OSSUPD_OSSUPL3_Msk & ((value) << PWM_OSSUPD_OSSUPL3_Pos)) +#define PWM_OSSUPD_Msk _U_(0x000F000F) /**< (PWM_OSSUPD) Register Mask */ + +#define PWM_OSSUPD_OSSUPH_Pos _U_(0) /**< (PWM_OSSUPD Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSSUPD_OSSUPH_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPH_Pos) /**< (PWM_OSSUPD Mask) OSSUPH */ +#define PWM_OSSUPD_OSSUPH(value) (PWM_OSSUPD_OSSUPH_Msk & ((value) << PWM_OSSUPD_OSSUPH_Pos)) +#define PWM_OSSUPD_OSSUPL_Pos _U_(16) /**< (PWM_OSSUPD Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPL_Pos) /**< (PWM_OSSUPD Mask) OSSUPL */ +#define PWM_OSSUPD_OSSUPL(value) (PWM_OSSUPD_OSSUPL_Msk & ((value) << PWM_OSSUPD_OSSUPL_Pos)) + +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) ( /W 32) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0_Pos _U_(0) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPH0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPH0(value) (PWM_OSCUPD_OSCUPH0_Msk & ((value) << PWM_OSCUPD_OSCUPH0_Pos)) +#define PWM_OSCUPD_OSCUPH1_Pos _U_(1) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPH1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPH1(value) (PWM_OSCUPD_OSCUPH1_Msk & ((value) << PWM_OSCUPD_OSCUPH1_Pos)) +#define PWM_OSCUPD_OSCUPH2_Pos _U_(2) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPH2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPH2(value) (PWM_OSCUPD_OSCUPH2_Msk & ((value) << PWM_OSCUPD_OSCUPH2_Pos)) +#define PWM_OSCUPD_OSCUPH3_Pos _U_(3) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPH3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPH3(value) (PWM_OSCUPD_OSCUPH3_Msk & ((value) << PWM_OSCUPD_OSCUPH3_Pos)) +#define PWM_OSCUPD_OSCUPL0_Pos _U_(16) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPL0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPL0(value) (PWM_OSCUPD_OSCUPL0_Msk & ((value) << PWM_OSCUPD_OSCUPL0_Pos)) +#define PWM_OSCUPD_OSCUPL1_Pos _U_(17) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPL1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPL1(value) (PWM_OSCUPD_OSCUPL1_Msk & ((value) << PWM_OSCUPD_OSCUPL1_Pos)) +#define PWM_OSCUPD_OSCUPL2_Pos _U_(18) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPL2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPL2(value) (PWM_OSCUPD_OSCUPL2_Msk & ((value) << PWM_OSCUPD_OSCUPL2_Pos)) +#define PWM_OSCUPD_OSCUPL3_Pos _U_(19) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPL3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPL3(value) (PWM_OSCUPD_OSCUPL3_Msk & ((value) << PWM_OSCUPD_OSCUPL3_Pos)) +#define PWM_OSCUPD_Msk _U_(0x000F000F) /**< (PWM_OSCUPD) Register Mask */ + +#define PWM_OSCUPD_OSCUPH_Pos _U_(0) /**< (PWM_OSCUPD Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSCUPD_OSCUPH_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPH_Pos) /**< (PWM_OSCUPD Mask) OSCUPH */ +#define PWM_OSCUPD_OSCUPH(value) (PWM_OSCUPD_OSCUPH_Msk & ((value) << PWM_OSCUPD_OSCUPH_Pos)) +#define PWM_OSCUPD_OSCUPL_Pos _U_(16) /**< (PWM_OSCUPD Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPL_Pos) /**< (PWM_OSCUPD Mask) OSCUPL */ +#define PWM_OSCUPD_OSCUPL(value) (PWM_OSCUPD_OSCUPL_Msk & ((value) << PWM_OSCUPD_OSCUPL_Pos)) + +/* -------- PWM_FMR : (PWM Offset: 0x5C) (R/W 32) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos _U_(0) /**< (PWM_FMR) Fault Polarity Position */ +#define PWM_FMR_FPOL_Msk (_U_(0xFF) << PWM_FMR_FPOL_Pos) /**< (PWM_FMR) Fault Polarity Mask */ +#define PWM_FMR_FPOL(value) (PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)) +#define PWM_FMR_FMOD_Pos _U_(8) /**< (PWM_FMR) Fault Activation Mode Position */ +#define PWM_FMR_FMOD_Msk (_U_(0xFF) << PWM_FMR_FMOD_Pos) /**< (PWM_FMR) Fault Activation Mode Mask */ +#define PWM_FMR_FMOD(value) (PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)) +#define PWM_FMR_FFIL_Pos _U_(16) /**< (PWM_FMR) Fault Filtering Position */ +#define PWM_FMR_FFIL_Msk (_U_(0xFF) << PWM_FMR_FFIL_Pos) /**< (PWM_FMR) Fault Filtering Mask */ +#define PWM_FMR_FFIL(value) (PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)) +#define PWM_FMR_Msk _U_(0x00FFFFFF) /**< (PWM_FMR) Register Mask */ + + +/* -------- PWM_FSR : (PWM Offset: 0x60) ( R/ 32) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos _U_(0) /**< (PWM_FSR) Fault Input Value Position */ +#define PWM_FSR_FIV_Msk (_U_(0xFF) << PWM_FSR_FIV_Pos) /**< (PWM_FSR) Fault Input Value Mask */ +#define PWM_FSR_FIV(value) (PWM_FSR_FIV_Msk & ((value) << PWM_FSR_FIV_Pos)) +#define PWM_FSR_FS_Pos _U_(8) /**< (PWM_FSR) Fault Status Position */ +#define PWM_FSR_FS_Msk (_U_(0xFF) << PWM_FSR_FS_Pos) /**< (PWM_FSR) Fault Status Mask */ +#define PWM_FSR_FS(value) (PWM_FSR_FS_Msk & ((value) << PWM_FSR_FS_Pos)) +#define PWM_FSR_Msk _U_(0x0000FFFF) /**< (PWM_FSR) Register Mask */ + + +/* -------- PWM_FCR : (PWM Offset: 0x64) ( /W 32) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos _U_(0) /**< (PWM_FCR) Fault Clear Position */ +#define PWM_FCR_FCLR_Msk (_U_(0xFF) << PWM_FCR_FCLR_Pos) /**< (PWM_FCR) Fault Clear Mask */ +#define PWM_FCR_FCLR(value) (PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)) +#define PWM_FCR_Msk _U_(0x000000FF) /**< (PWM_FCR) Register Mask */ + + +/* -------- PWM_FPV1 : (PWM Offset: 0x68) (R/W 32) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0_Pos _U_(0) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Position */ +#define PWM_FPV1_FPVH0_Msk (_U_(0x1) << PWM_FPV1_FPVH0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Mask */ +#define PWM_FPV1_FPVH0(value) (PWM_FPV1_FPVH0_Msk & ((value) << PWM_FPV1_FPVH0_Pos)) +#define PWM_FPV1_FPVH1_Pos _U_(1) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Position */ +#define PWM_FPV1_FPVH1_Msk (_U_(0x1) << PWM_FPV1_FPVH1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Mask */ +#define PWM_FPV1_FPVH1(value) (PWM_FPV1_FPVH1_Msk & ((value) << PWM_FPV1_FPVH1_Pos)) +#define PWM_FPV1_FPVH2_Pos _U_(2) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Position */ +#define PWM_FPV1_FPVH2_Msk (_U_(0x1) << PWM_FPV1_FPVH2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Mask */ +#define PWM_FPV1_FPVH2(value) (PWM_FPV1_FPVH2_Msk & ((value) << PWM_FPV1_FPVH2_Pos)) +#define PWM_FPV1_FPVH3_Pos _U_(3) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Position */ +#define PWM_FPV1_FPVH3_Msk (_U_(0x1) << PWM_FPV1_FPVH3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Mask */ +#define PWM_FPV1_FPVH3(value) (PWM_FPV1_FPVH3_Msk & ((value) << PWM_FPV1_FPVH3_Pos)) +#define PWM_FPV1_FPVL0_Pos _U_(16) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Position */ +#define PWM_FPV1_FPVL0_Msk (_U_(0x1) << PWM_FPV1_FPVL0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Mask */ +#define PWM_FPV1_FPVL0(value) (PWM_FPV1_FPVL0_Msk & ((value) << PWM_FPV1_FPVL0_Pos)) +#define PWM_FPV1_FPVL1_Pos _U_(17) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Position */ +#define PWM_FPV1_FPVL1_Msk (_U_(0x1) << PWM_FPV1_FPVL1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Mask */ +#define PWM_FPV1_FPVL1(value) (PWM_FPV1_FPVL1_Msk & ((value) << PWM_FPV1_FPVL1_Pos)) +#define PWM_FPV1_FPVL2_Pos _U_(18) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Position */ +#define PWM_FPV1_FPVL2_Msk (_U_(0x1) << PWM_FPV1_FPVL2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Mask */ +#define PWM_FPV1_FPVL2(value) (PWM_FPV1_FPVL2_Msk & ((value) << PWM_FPV1_FPVL2_Pos)) +#define PWM_FPV1_FPVL3_Pos _U_(19) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Position */ +#define PWM_FPV1_FPVL3_Msk (_U_(0x1) << PWM_FPV1_FPVL3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Mask */ +#define PWM_FPV1_FPVL3(value) (PWM_FPV1_FPVL3_Msk & ((value) << PWM_FPV1_FPVL3_Pos)) +#define PWM_FPV1_Msk _U_(0x000F000F) /**< (PWM_FPV1) Register Mask */ + +#define PWM_FPV1_FPVH_Pos _U_(0) /**< (PWM_FPV1 Position) Fault Protection Value for PWMH output on channel x */ +#define PWM_FPV1_FPVH_Msk (_U_(0xF) << PWM_FPV1_FPVH_Pos) /**< (PWM_FPV1 Mask) FPVH */ +#define PWM_FPV1_FPVH(value) (PWM_FPV1_FPVH_Msk & ((value) << PWM_FPV1_FPVH_Pos)) +#define PWM_FPV1_FPVL_Pos _U_(16) /**< (PWM_FPV1 Position) Fault Protection Value for PWML output on channel 3 */ +#define PWM_FPV1_FPVL_Msk (_U_(0xF) << PWM_FPV1_FPVL_Pos) /**< (PWM_FPV1 Mask) FPVL */ +#define PWM_FPV1_FPVL(value) (PWM_FPV1_FPVL_Msk & ((value) << PWM_FPV1_FPVL_Pos)) + +/* -------- PWM_FPE : (PWM Offset: 0x6C) (R/W 32) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos _U_(0) /**< (PWM_FPE) Fault Protection Enable for channel 0 Position */ +#define PWM_FPE_FPE0_Msk (_U_(0xFF) << PWM_FPE_FPE0_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 0 Mask */ +#define PWM_FPE_FPE0(value) (PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)) +#define PWM_FPE_FPE1_Pos _U_(8) /**< (PWM_FPE) Fault Protection Enable for channel 1 Position */ +#define PWM_FPE_FPE1_Msk (_U_(0xFF) << PWM_FPE_FPE1_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 1 Mask */ +#define PWM_FPE_FPE1(value) (PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)) +#define PWM_FPE_FPE2_Pos _U_(16) /**< (PWM_FPE) Fault Protection Enable for channel 2 Position */ +#define PWM_FPE_FPE2_Msk (_U_(0xFF) << PWM_FPE_FPE2_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 2 Mask */ +#define PWM_FPE_FPE2(value) (PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)) +#define PWM_FPE_FPE3_Pos _U_(24) /**< (PWM_FPE) Fault Protection Enable for channel 3 Position */ +#define PWM_FPE_FPE3_Msk (_U_(0xFF) << PWM_FPE_FPE3_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 3 Mask */ +#define PWM_FPE_FPE3(value) (PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)) +#define PWM_FPE_Msk _U_(0xFFFFFFFF) /**< (PWM_FPE) Register Mask */ + + +/* -------- PWM_ELMR : (PWM Offset: 0x7C) (R/W 32) PWM Event Line 0 Mode Register 0 -------- */ +#define PWM_ELMR_CSEL0_Pos _U_(0) /**< (PWM_ELMR) Comparison 0 Selection Position */ +#define PWM_ELMR_CSEL0_Msk (_U_(0x1) << PWM_ELMR_CSEL0_Pos) /**< (PWM_ELMR) Comparison 0 Selection Mask */ +#define PWM_ELMR_CSEL0(value) (PWM_ELMR_CSEL0_Msk & ((value) << PWM_ELMR_CSEL0_Pos)) +#define PWM_ELMR_CSEL1_Pos _U_(1) /**< (PWM_ELMR) Comparison 1 Selection Position */ +#define PWM_ELMR_CSEL1_Msk (_U_(0x1) << PWM_ELMR_CSEL1_Pos) /**< (PWM_ELMR) Comparison 1 Selection Mask */ +#define PWM_ELMR_CSEL1(value) (PWM_ELMR_CSEL1_Msk & ((value) << PWM_ELMR_CSEL1_Pos)) +#define PWM_ELMR_CSEL2_Pos _U_(2) /**< (PWM_ELMR) Comparison 2 Selection Position */ +#define PWM_ELMR_CSEL2_Msk (_U_(0x1) << PWM_ELMR_CSEL2_Pos) /**< (PWM_ELMR) Comparison 2 Selection Mask */ +#define PWM_ELMR_CSEL2(value) (PWM_ELMR_CSEL2_Msk & ((value) << PWM_ELMR_CSEL2_Pos)) +#define PWM_ELMR_CSEL3_Pos _U_(3) /**< (PWM_ELMR) Comparison 3 Selection Position */ +#define PWM_ELMR_CSEL3_Msk (_U_(0x1) << PWM_ELMR_CSEL3_Pos) /**< (PWM_ELMR) Comparison 3 Selection Mask */ +#define PWM_ELMR_CSEL3(value) (PWM_ELMR_CSEL3_Msk & ((value) << PWM_ELMR_CSEL3_Pos)) +#define PWM_ELMR_CSEL4_Pos _U_(4) /**< (PWM_ELMR) Comparison 4 Selection Position */ +#define PWM_ELMR_CSEL4_Msk (_U_(0x1) << PWM_ELMR_CSEL4_Pos) /**< (PWM_ELMR) Comparison 4 Selection Mask */ +#define PWM_ELMR_CSEL4(value) (PWM_ELMR_CSEL4_Msk & ((value) << PWM_ELMR_CSEL4_Pos)) +#define PWM_ELMR_CSEL5_Pos _U_(5) /**< (PWM_ELMR) Comparison 5 Selection Position */ +#define PWM_ELMR_CSEL5_Msk (_U_(0x1) << PWM_ELMR_CSEL5_Pos) /**< (PWM_ELMR) Comparison 5 Selection Mask */ +#define PWM_ELMR_CSEL5(value) (PWM_ELMR_CSEL5_Msk & ((value) << PWM_ELMR_CSEL5_Pos)) +#define PWM_ELMR_CSEL6_Pos _U_(6) /**< (PWM_ELMR) Comparison 6 Selection Position */ +#define PWM_ELMR_CSEL6_Msk (_U_(0x1) << PWM_ELMR_CSEL6_Pos) /**< (PWM_ELMR) Comparison 6 Selection Mask */ +#define PWM_ELMR_CSEL6(value) (PWM_ELMR_CSEL6_Msk & ((value) << PWM_ELMR_CSEL6_Pos)) +#define PWM_ELMR_CSEL7_Pos _U_(7) /**< (PWM_ELMR) Comparison 7 Selection Position */ +#define PWM_ELMR_CSEL7_Msk (_U_(0x1) << PWM_ELMR_CSEL7_Pos) /**< (PWM_ELMR) Comparison 7 Selection Mask */ +#define PWM_ELMR_CSEL7(value) (PWM_ELMR_CSEL7_Msk & ((value) << PWM_ELMR_CSEL7_Pos)) +#define PWM_ELMR_Msk _U_(0x000000FF) /**< (PWM_ELMR) Register Mask */ + +#define PWM_ELMR_CSEL_Pos _U_(0) /**< (PWM_ELMR Position) Comparison 7 Selection */ +#define PWM_ELMR_CSEL_Msk (_U_(0xFF) << PWM_ELMR_CSEL_Pos) /**< (PWM_ELMR Mask) CSEL */ +#define PWM_ELMR_CSEL(value) (PWM_ELMR_CSEL_Msk & ((value) << PWM_ELMR_CSEL_Pos)) + +/* -------- PWM_SSPR : (PWM Offset: 0xA0) (R/W 32) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos _U_(0) /**< (PWM_SSPR) Spread Spectrum Limit Value Position */ +#define PWM_SSPR_SPRD_Msk (_U_(0xFFFFFF) << PWM_SSPR_SPRD_Pos) /**< (PWM_SSPR) Spread Spectrum Limit Value Mask */ +#define PWM_SSPR_SPRD(value) (PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)) +#define PWM_SSPR_SPRDM_Pos _U_(24) /**< (PWM_SSPR) Spread Spectrum Counter Mode Position */ +#define PWM_SSPR_SPRDM_Msk (_U_(0x1) << PWM_SSPR_SPRDM_Pos) /**< (PWM_SSPR) Spread Spectrum Counter Mode Mask */ +#define PWM_SSPR_SPRDM(value) (PWM_SSPR_SPRDM_Msk & ((value) << PWM_SSPR_SPRDM_Pos)) +#define PWM_SSPR_Msk _U_(0x01FFFFFF) /**< (PWM_SSPR) Register Mask */ + + +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) ( /W 32) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos _U_(0) /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Position */ +#define PWM_SSPUP_SPRDUP_Msk (_U_(0xFFFFFF) << PWM_SSPUP_SPRDUP_Pos) /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Mask */ +#define PWM_SSPUP_SPRDUP(value) (PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)) +#define PWM_SSPUP_Msk _U_(0x00FFFFFF) /**< (PWM_SSPUP) Register Mask */ + + +/* -------- PWM_SMMR : (PWM Offset: 0xB0) (R/W 32) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0_Pos _U_(0) /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN0_Msk (_U_(0x1) << PWM_SMMR_GCEN0_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN0(value) (PWM_SMMR_GCEN0_Msk & ((value) << PWM_SMMR_GCEN0_Pos)) +#define PWM_SMMR_GCEN1_Pos _U_(1) /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN1_Msk (_U_(0x1) << PWM_SMMR_GCEN1_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN1(value) (PWM_SMMR_GCEN1_Msk & ((value) << PWM_SMMR_GCEN1_Pos)) +#define PWM_SMMR_DOWN0_Pos _U_(16) /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN0_Msk (_U_(0x1) << PWM_SMMR_DOWN0_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN0(value) (PWM_SMMR_DOWN0_Msk & ((value) << PWM_SMMR_DOWN0_Pos)) +#define PWM_SMMR_DOWN1_Pos _U_(17) /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN1_Msk (_U_(0x1) << PWM_SMMR_DOWN1_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN1(value) (PWM_SMMR_DOWN1_Msk & ((value) << PWM_SMMR_DOWN1_Pos)) +#define PWM_SMMR_Msk _U_(0x00030003) /**< (PWM_SMMR) Register Mask */ + +#define PWM_SMMR_GCEN_Pos _U_(0) /**< (PWM_SMMR Position) Gray Count ENable */ +#define PWM_SMMR_GCEN_Msk (_U_(0x3) << PWM_SMMR_GCEN_Pos) /**< (PWM_SMMR Mask) GCEN */ +#define PWM_SMMR_GCEN(value) (PWM_SMMR_GCEN_Msk & ((value) << PWM_SMMR_GCEN_Pos)) +#define PWM_SMMR_DOWN_Pos _U_(16) /**< (PWM_SMMR Position) DOWN Count */ +#define PWM_SMMR_DOWN_Msk (_U_(0x3) << PWM_SMMR_DOWN_Pos) /**< (PWM_SMMR Mask) DOWN */ +#define PWM_SMMR_DOWN(value) (PWM_SMMR_DOWN_Msk & ((value) << PWM_SMMR_DOWN_Pos)) + +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) (R/W 32) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0_Pos _U_(0) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Position */ +#define PWM_FPV2_FPZH0_Msk (_U_(0x1) << PWM_FPV2_FPZH0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Mask */ +#define PWM_FPV2_FPZH0(value) (PWM_FPV2_FPZH0_Msk & ((value) << PWM_FPV2_FPZH0_Pos)) +#define PWM_FPV2_FPZH1_Pos _U_(1) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Position */ +#define PWM_FPV2_FPZH1_Msk (_U_(0x1) << PWM_FPV2_FPZH1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Mask */ +#define PWM_FPV2_FPZH1(value) (PWM_FPV2_FPZH1_Msk & ((value) << PWM_FPV2_FPZH1_Pos)) +#define PWM_FPV2_FPZH2_Pos _U_(2) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Position */ +#define PWM_FPV2_FPZH2_Msk (_U_(0x1) << PWM_FPV2_FPZH2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Mask */ +#define PWM_FPV2_FPZH2(value) (PWM_FPV2_FPZH2_Msk & ((value) << PWM_FPV2_FPZH2_Pos)) +#define PWM_FPV2_FPZH3_Pos _U_(3) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Position */ +#define PWM_FPV2_FPZH3_Msk (_U_(0x1) << PWM_FPV2_FPZH3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Mask */ +#define PWM_FPV2_FPZH3(value) (PWM_FPV2_FPZH3_Msk & ((value) << PWM_FPV2_FPZH3_Pos)) +#define PWM_FPV2_FPZL0_Pos _U_(16) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Position */ +#define PWM_FPV2_FPZL0_Msk (_U_(0x1) << PWM_FPV2_FPZL0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Mask */ +#define PWM_FPV2_FPZL0(value) (PWM_FPV2_FPZL0_Msk & ((value) << PWM_FPV2_FPZL0_Pos)) +#define PWM_FPV2_FPZL1_Pos _U_(17) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Position */ +#define PWM_FPV2_FPZL1_Msk (_U_(0x1) << PWM_FPV2_FPZL1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Mask */ +#define PWM_FPV2_FPZL1(value) (PWM_FPV2_FPZL1_Msk & ((value) << PWM_FPV2_FPZL1_Pos)) +#define PWM_FPV2_FPZL2_Pos _U_(18) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Position */ +#define PWM_FPV2_FPZL2_Msk (_U_(0x1) << PWM_FPV2_FPZL2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Mask */ +#define PWM_FPV2_FPZL2(value) (PWM_FPV2_FPZL2_Msk & ((value) << PWM_FPV2_FPZL2_Pos)) +#define PWM_FPV2_FPZL3_Pos _U_(19) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Position */ +#define PWM_FPV2_FPZL3_Msk (_U_(0x1) << PWM_FPV2_FPZL3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Mask */ +#define PWM_FPV2_FPZL3(value) (PWM_FPV2_FPZL3_Msk & ((value) << PWM_FPV2_FPZL3_Pos)) +#define PWM_FPV2_Msk _U_(0x000F000F) /**< (PWM_FPV2) Register Mask */ + +#define PWM_FPV2_FPZH_Pos _U_(0) /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWMH output on channel x */ +#define PWM_FPV2_FPZH_Msk (_U_(0xF) << PWM_FPV2_FPZH_Pos) /**< (PWM_FPV2 Mask) FPZH */ +#define PWM_FPV2_FPZH(value) (PWM_FPV2_FPZH_Msk & ((value) << PWM_FPV2_FPZH_Pos)) +#define PWM_FPV2_FPZL_Pos _U_(16) /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWML output on channel 3 */ +#define PWM_FPV2_FPZL_Msk (_U_(0xF) << PWM_FPV2_FPZL_Pos) /**< (PWM_FPV2 Mask) FPZL */ +#define PWM_FPV2_FPZL(value) (PWM_FPV2_FPZL_Msk & ((value) << PWM_FPV2_FPZL_Pos)) + +/* -------- PWM_WPCR : (PWM Offset: 0xE4) ( /W 32) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos _U_(0) /**< (PWM_WPCR) Write Protection Command Position */ +#define PWM_WPCR_WPCMD_Msk (_U_(0x3) << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Write Protection Command Mask */ +#define PWM_WPCR_WPCMD(value) (PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val _U_(0x0) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val _U_(0x1) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val _U_(0x2) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. Position */ +#define PWM_WPCR_WPRG0_Pos _U_(2) /**< (PWM_WPCR) Write Protection Register Group 0 Position */ +#define PWM_WPCR_WPRG0_Msk (_U_(0x1) << PWM_WPCR_WPRG0_Pos) /**< (PWM_WPCR) Write Protection Register Group 0 Mask */ +#define PWM_WPCR_WPRG0(value) (PWM_WPCR_WPRG0_Msk & ((value) << PWM_WPCR_WPRG0_Pos)) +#define PWM_WPCR_WPRG1_Pos _U_(3) /**< (PWM_WPCR) Write Protection Register Group 1 Position */ +#define PWM_WPCR_WPRG1_Msk (_U_(0x1) << PWM_WPCR_WPRG1_Pos) /**< (PWM_WPCR) Write Protection Register Group 1 Mask */ +#define PWM_WPCR_WPRG1(value) (PWM_WPCR_WPRG1_Msk & ((value) << PWM_WPCR_WPRG1_Pos)) +#define PWM_WPCR_WPRG2_Pos _U_(4) /**< (PWM_WPCR) Write Protection Register Group 2 Position */ +#define PWM_WPCR_WPRG2_Msk (_U_(0x1) << PWM_WPCR_WPRG2_Pos) /**< (PWM_WPCR) Write Protection Register Group 2 Mask */ +#define PWM_WPCR_WPRG2(value) (PWM_WPCR_WPRG2_Msk & ((value) << PWM_WPCR_WPRG2_Pos)) +#define PWM_WPCR_WPRG3_Pos _U_(5) /**< (PWM_WPCR) Write Protection Register Group 3 Position */ +#define PWM_WPCR_WPRG3_Msk (_U_(0x1) << PWM_WPCR_WPRG3_Pos) /**< (PWM_WPCR) Write Protection Register Group 3 Mask */ +#define PWM_WPCR_WPRG3(value) (PWM_WPCR_WPRG3_Msk & ((value) << PWM_WPCR_WPRG3_Pos)) +#define PWM_WPCR_WPRG4_Pos _U_(6) /**< (PWM_WPCR) Write Protection Register Group 4 Position */ +#define PWM_WPCR_WPRG4_Msk (_U_(0x1) << PWM_WPCR_WPRG4_Pos) /**< (PWM_WPCR) Write Protection Register Group 4 Mask */ +#define PWM_WPCR_WPRG4(value) (PWM_WPCR_WPRG4_Msk & ((value) << PWM_WPCR_WPRG4_Pos)) +#define PWM_WPCR_WPRG5_Pos _U_(7) /**< (PWM_WPCR) Write Protection Register Group 5 Position */ +#define PWM_WPCR_WPRG5_Msk (_U_(0x1) << PWM_WPCR_WPRG5_Pos) /**< (PWM_WPCR) Write Protection Register Group 5 Mask */ +#define PWM_WPCR_WPRG5(value) (PWM_WPCR_WPRG5_Msk & ((value) << PWM_WPCR_WPRG5_Pos)) +#define PWM_WPCR_WPKEY_Pos _U_(8) /**< (PWM_WPCR) Write Protection Key Position */ +#define PWM_WPCR_WPKEY_Msk (_U_(0xFFFFFF) << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Write Protection Key Mask */ +#define PWM_WPCR_WPKEY(value) (PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)) +#define PWM_WPCR_WPKEY_PASSWD_Val _U_(0x50574D) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +#define PWM_WPCR_WPKEY_PASSWD (PWM_WPCR_WPKEY_PASSWD_Val << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 Position */ +#define PWM_WPCR_Msk _U_(0xFFFFFFFF) /**< (PWM_WPCR) Register Mask */ + +#define PWM_WPCR_WPRG_Pos _U_(2) /**< (PWM_WPCR Position) Write Protection Register Group x */ +#define PWM_WPCR_WPRG_Msk (_U_(0x3F) << PWM_WPCR_WPRG_Pos) /**< (PWM_WPCR Mask) WPRG */ +#define PWM_WPCR_WPRG(value) (PWM_WPCR_WPRG_Msk & ((value) << PWM_WPCR_WPRG_Pos)) + +/* -------- PWM_WPSR : (PWM Offset: 0xE8) ( R/ 32) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0_Pos _U_(0) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS0_Msk (_U_(0x1) << PWM_WPSR_WPSWS0_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS0(value) (PWM_WPSR_WPSWS0_Msk & ((value) << PWM_WPSR_WPSWS0_Pos)) +#define PWM_WPSR_WPSWS1_Pos _U_(1) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS1_Msk (_U_(0x1) << PWM_WPSR_WPSWS1_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS1(value) (PWM_WPSR_WPSWS1_Msk & ((value) << PWM_WPSR_WPSWS1_Pos)) +#define PWM_WPSR_WPSWS2_Pos _U_(2) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS2_Msk (_U_(0x1) << PWM_WPSR_WPSWS2_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS2(value) (PWM_WPSR_WPSWS2_Msk & ((value) << PWM_WPSR_WPSWS2_Pos)) +#define PWM_WPSR_WPSWS3_Pos _U_(3) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS3_Msk (_U_(0x1) << PWM_WPSR_WPSWS3_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS3(value) (PWM_WPSR_WPSWS3_Msk & ((value) << PWM_WPSR_WPSWS3_Pos)) +#define PWM_WPSR_WPSWS4_Pos _U_(4) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS4_Msk (_U_(0x1) << PWM_WPSR_WPSWS4_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS4(value) (PWM_WPSR_WPSWS4_Msk & ((value) << PWM_WPSR_WPSWS4_Pos)) +#define PWM_WPSR_WPSWS5_Pos _U_(5) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS5_Msk (_U_(0x1) << PWM_WPSR_WPSWS5_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS5(value) (PWM_WPSR_WPSWS5_Msk & ((value) << PWM_WPSR_WPSWS5_Pos)) +#define PWM_WPSR_WPVS_Pos _U_(7) /**< (PWM_WPSR) Write Protect Violation Status Position */ +#define PWM_WPSR_WPVS_Msk (_U_(0x1) << PWM_WPSR_WPVS_Pos) /**< (PWM_WPSR) Write Protect Violation Status Mask */ +#define PWM_WPSR_WPVS(value) (PWM_WPSR_WPVS_Msk & ((value) << PWM_WPSR_WPVS_Pos)) +#define PWM_WPSR_WPHWS0_Pos _U_(8) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS0_Msk (_U_(0x1) << PWM_WPSR_WPHWS0_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS0(value) (PWM_WPSR_WPHWS0_Msk & ((value) << PWM_WPSR_WPHWS0_Pos)) +#define PWM_WPSR_WPHWS1_Pos _U_(9) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS1_Msk (_U_(0x1) << PWM_WPSR_WPHWS1_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS1(value) (PWM_WPSR_WPHWS1_Msk & ((value) << PWM_WPSR_WPHWS1_Pos)) +#define PWM_WPSR_WPHWS2_Pos _U_(10) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS2_Msk (_U_(0x1) << PWM_WPSR_WPHWS2_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS2(value) (PWM_WPSR_WPHWS2_Msk & ((value) << PWM_WPSR_WPHWS2_Pos)) +#define PWM_WPSR_WPHWS3_Pos _U_(11) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS3_Msk (_U_(0x1) << PWM_WPSR_WPHWS3_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS3(value) (PWM_WPSR_WPHWS3_Msk & ((value) << PWM_WPSR_WPHWS3_Pos)) +#define PWM_WPSR_WPHWS4_Pos _U_(12) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS4_Msk (_U_(0x1) << PWM_WPSR_WPHWS4_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS4(value) (PWM_WPSR_WPHWS4_Msk & ((value) << PWM_WPSR_WPHWS4_Pos)) +#define PWM_WPSR_WPHWS5_Pos _U_(13) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS5_Msk (_U_(0x1) << PWM_WPSR_WPHWS5_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS5(value) (PWM_WPSR_WPHWS5_Msk & ((value) << PWM_WPSR_WPHWS5_Pos)) +#define PWM_WPSR_WPVSRC_Pos _U_(16) /**< (PWM_WPSR) Write Protect Violation Source Position */ +#define PWM_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PWM_WPSR_WPVSRC_Pos) /**< (PWM_WPSR) Write Protect Violation Source Mask */ +#define PWM_WPSR_WPVSRC(value) (PWM_WPSR_WPVSRC_Msk & ((value) << PWM_WPSR_WPVSRC_Pos)) +#define PWM_WPSR_Msk _U_(0xFFFF3FBF) /**< (PWM_WPSR) Register Mask */ + +#define PWM_WPSR_WPSWS_Pos _U_(0) /**< (PWM_WPSR Position) Write Protect SW Status */ +#define PWM_WPSR_WPSWS_Msk (_U_(0x3F) << PWM_WPSR_WPSWS_Pos) /**< (PWM_WPSR Mask) WPSWS */ +#define PWM_WPSR_WPSWS(value) (PWM_WPSR_WPSWS_Msk & ((value) << PWM_WPSR_WPSWS_Pos)) +#define PWM_WPSR_WPHWS_Pos _U_(8) /**< (PWM_WPSR Position) Write Protect HW Status */ +#define PWM_WPSR_WPHWS_Msk (_U_(0x3F) << PWM_WPSR_WPHWS_Pos) /**< (PWM_WPSR Mask) WPHWS */ +#define PWM_WPSR_WPHWS(value) (PWM_WPSR_WPHWS_Msk & ((value) << PWM_WPSR_WPHWS_Pos)) + +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) ( /W 32) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD0) Channel Polarity Update Position */ +#define PWM_CMUPD0_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Update Mask */ +#define PWM_CMUPD0_CPOLUP(value) (PWM_CMUPD0_CPOLUP_Msk & ((value) << PWM_CMUPD0_CPOLUP_Pos)) +#define PWM_CMUPD0_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD0) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD0_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLINVUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD0_CPOLINVUP(value) (PWM_CMUPD0_CPOLINVUP_Msk & ((value) << PWM_CMUPD0_CPOLINVUP_Pos)) +#define PWM_CMUPD0_Msk _U_(0x00002200) /**< (PWM_CMUPD0) Register Mask */ + + +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) ( /W 32) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD1) Channel Polarity Update Position */ +#define PWM_CMUPD1_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Update Mask */ +#define PWM_CMUPD1_CPOLUP(value) (PWM_CMUPD1_CPOLUP_Msk & ((value) << PWM_CMUPD1_CPOLUP_Pos)) +#define PWM_CMUPD1_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD1) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD1_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLINVUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD1_CPOLINVUP(value) (PWM_CMUPD1_CPOLINVUP_Msk & ((value) << PWM_CMUPD1_CPOLINVUP_Pos)) +#define PWM_CMUPD1_Msk _U_(0x00002200) /**< (PWM_CMUPD1) Register Mask */ + + +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) (R/W 32) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos _U_(0) /**< (PWM_ETRG1) Maximum Counter value Position */ +#define PWM_ETRG1_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG1_MAXCNT_Pos) /**< (PWM_ETRG1) Maximum Counter value Mask */ +#define PWM_ETRG1_MAXCNT(value) (PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)) +#define PWM_ETRG1_TRGMODE_Pos _U_(24) /**< (PWM_ETRG1) External Trigger Mode Position */ +#define PWM_ETRG1_TRGMODE_Msk (_U_(0x3) << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External Trigger Mode Mask */ +#define PWM_ETRG1_TRGMODE(value) (PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)) +#define PWM_ETRG1_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGMODE_OFF (PWM_ETRG1_TRGMODE_OFF_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External trigger is not enabled. Position */ +#define PWM_ETRG1_TRGMODE_MODE1 (PWM_ETRG1_TRGMODE_MODE1_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Reset Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE2 (PWM_ETRG1_TRGMODE_MODE2_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Start Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE3 (PWM_ETRG1_TRGMODE_MODE3_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG1_TRGEDGE_Pos _U_(28) /**< (PWM_ETRG1) Edge Selection Position */ +#define PWM_ETRG1_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) Edge Selection Mask */ +#define PWM_ETRG1_TRGEDGE(value) (PWM_ETRG1_TRGEDGE_Msk & ((value) << PWM_ETRG1_TRGEDGE_Pos)) +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (PWM_ETRG1_TRGEDGE_RISING_ONE_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG1_TRGFILT_Pos _U_(29) /**< (PWM_ETRG1) Filtered input Position */ +#define PWM_ETRG1_TRGFILT_Msk (_U_(0x1) << PWM_ETRG1_TRGFILT_Pos) /**< (PWM_ETRG1) Filtered input Mask */ +#define PWM_ETRG1_TRGFILT(value) (PWM_ETRG1_TRGFILT_Msk & ((value) << PWM_ETRG1_TRGFILT_Pos)) +#define PWM_ETRG1_TRGSRC_Pos _U_(30) /**< (PWM_ETRG1) Trigger Source Position */ +#define PWM_ETRG1_TRGSRC_Msk (_U_(0x1) << PWM_ETRG1_TRGSRC_Pos) /**< (PWM_ETRG1) Trigger Source Mask */ +#define PWM_ETRG1_TRGSRC(value) (PWM_ETRG1_TRGSRC_Msk & ((value) << PWM_ETRG1_TRGSRC_Pos)) +#define PWM_ETRG1_RFEN_Pos _U_(31) /**< (PWM_ETRG1) Recoverable Fault Enable Position */ +#define PWM_ETRG1_RFEN_Msk (_U_(0x1) << PWM_ETRG1_RFEN_Pos) /**< (PWM_ETRG1) Recoverable Fault Enable Mask */ +#define PWM_ETRG1_RFEN(value) (PWM_ETRG1_RFEN_Msk & ((value) << PWM_ETRG1_RFEN_Pos)) +#define PWM_ETRG1_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG1) Register Mask */ + + +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos _U_(0) /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR1_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR1_LEBDELAY_Pos) /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR1_LEBDELAY(value) (PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)) +#define PWM_LEBR1_PWMLFEN_Pos _U_(16) /**< (PWM_LEBR1) PWML Falling Edge Enable Position */ +#define PWM_LEBR1_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMLFEN_Pos) /**< (PWM_LEBR1) PWML Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMLFEN(value) (PWM_LEBR1_PWMLFEN_Msk & ((value) << PWM_LEBR1_PWMLFEN_Pos)) +#define PWM_LEBR1_PWMLREN_Pos _U_(17) /**< (PWM_LEBR1) PWML Rising Edge Enable Position */ +#define PWM_LEBR1_PWMLREN_Msk (_U_(0x1) << PWM_LEBR1_PWMLREN_Pos) /**< (PWM_LEBR1) PWML Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMLREN(value) (PWM_LEBR1_PWMLREN_Msk & ((value) << PWM_LEBR1_PWMLREN_Pos)) +#define PWM_LEBR1_PWMHFEN_Pos _U_(18) /**< (PWM_LEBR1) PWMH Falling Edge Enable Position */ +#define PWM_LEBR1_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMHFEN_Pos) /**< (PWM_LEBR1) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMHFEN(value) (PWM_LEBR1_PWMHFEN_Msk & ((value) << PWM_LEBR1_PWMHFEN_Pos)) +#define PWM_LEBR1_PWMHREN_Pos _U_(19) /**< (PWM_LEBR1) PWMH Rising Edge Enable Position */ +#define PWM_LEBR1_PWMHREN_Msk (_U_(0x1) << PWM_LEBR1_PWMHREN_Pos) /**< (PWM_LEBR1) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMHREN(value) (PWM_LEBR1_PWMHREN_Msk & ((value) << PWM_LEBR1_PWMHREN_Pos)) +#define PWM_LEBR1_Msk _U_(0x000F007F) /**< (PWM_LEBR1) Register Mask */ + + +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) ( /W 32) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD2) Channel Polarity Update Position */ +#define PWM_CMUPD2_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Update Mask */ +#define PWM_CMUPD2_CPOLUP(value) (PWM_CMUPD2_CPOLUP_Msk & ((value) << PWM_CMUPD2_CPOLUP_Pos)) +#define PWM_CMUPD2_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD2) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD2_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLINVUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD2_CPOLINVUP(value) (PWM_CMUPD2_CPOLINVUP_Msk & ((value) << PWM_CMUPD2_CPOLINVUP_Pos)) +#define PWM_CMUPD2_Msk _U_(0x00002200) /**< (PWM_CMUPD2) Register Mask */ + + +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) (R/W 32) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos _U_(0) /**< (PWM_ETRG2) Maximum Counter value Position */ +#define PWM_ETRG2_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG2_MAXCNT_Pos) /**< (PWM_ETRG2) Maximum Counter value Mask */ +#define PWM_ETRG2_MAXCNT(value) (PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)) +#define PWM_ETRG2_TRGMODE_Pos _U_(24) /**< (PWM_ETRG2) External Trigger Mode Position */ +#define PWM_ETRG2_TRGMODE_Msk (_U_(0x3) << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External Trigger Mode Mask */ +#define PWM_ETRG2_TRGMODE(value) (PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)) +#define PWM_ETRG2_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGMODE_OFF (PWM_ETRG2_TRGMODE_OFF_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External trigger is not enabled. Position */ +#define PWM_ETRG2_TRGMODE_MODE1 (PWM_ETRG2_TRGMODE_MODE1_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Reset Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE2 (PWM_ETRG2_TRGMODE_MODE2_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Start Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE3 (PWM_ETRG2_TRGMODE_MODE3_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG2_TRGEDGE_Pos _U_(28) /**< (PWM_ETRG2) Edge Selection Position */ +#define PWM_ETRG2_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) Edge Selection Mask */ +#define PWM_ETRG2_TRGEDGE(value) (PWM_ETRG2_TRGEDGE_Msk & ((value) << PWM_ETRG2_TRGEDGE_Pos)) +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (PWM_ETRG2_TRGEDGE_RISING_ONE_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG2_TRGFILT_Pos _U_(29) /**< (PWM_ETRG2) Filtered input Position */ +#define PWM_ETRG2_TRGFILT_Msk (_U_(0x1) << PWM_ETRG2_TRGFILT_Pos) /**< (PWM_ETRG2) Filtered input Mask */ +#define PWM_ETRG2_TRGFILT(value) (PWM_ETRG2_TRGFILT_Msk & ((value) << PWM_ETRG2_TRGFILT_Pos)) +#define PWM_ETRG2_TRGSRC_Pos _U_(30) /**< (PWM_ETRG2) Trigger Source Position */ +#define PWM_ETRG2_TRGSRC_Msk (_U_(0x1) << PWM_ETRG2_TRGSRC_Pos) /**< (PWM_ETRG2) Trigger Source Mask */ +#define PWM_ETRG2_TRGSRC(value) (PWM_ETRG2_TRGSRC_Msk & ((value) << PWM_ETRG2_TRGSRC_Pos)) +#define PWM_ETRG2_RFEN_Pos _U_(31) /**< (PWM_ETRG2) Recoverable Fault Enable Position */ +#define PWM_ETRG2_RFEN_Msk (_U_(0x1) << PWM_ETRG2_RFEN_Pos) /**< (PWM_ETRG2) Recoverable Fault Enable Mask */ +#define PWM_ETRG2_RFEN(value) (PWM_ETRG2_RFEN_Msk & ((value) << PWM_ETRG2_RFEN_Pos)) +#define PWM_ETRG2_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG2) Register Mask */ + + +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos _U_(0) /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR2_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR2_LEBDELAY_Pos) /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR2_LEBDELAY(value) (PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)) +#define PWM_LEBR2_PWMLFEN_Pos _U_(16) /**< (PWM_LEBR2) PWML Falling Edge Enable Position */ +#define PWM_LEBR2_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMLFEN_Pos) /**< (PWM_LEBR2) PWML Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMLFEN(value) (PWM_LEBR2_PWMLFEN_Msk & ((value) << PWM_LEBR2_PWMLFEN_Pos)) +#define PWM_LEBR2_PWMLREN_Pos _U_(17) /**< (PWM_LEBR2) PWML Rising Edge Enable Position */ +#define PWM_LEBR2_PWMLREN_Msk (_U_(0x1) << PWM_LEBR2_PWMLREN_Pos) /**< (PWM_LEBR2) PWML Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMLREN(value) (PWM_LEBR2_PWMLREN_Msk & ((value) << PWM_LEBR2_PWMLREN_Pos)) +#define PWM_LEBR2_PWMHFEN_Pos _U_(18) /**< (PWM_LEBR2) PWMH Falling Edge Enable Position */ +#define PWM_LEBR2_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMHFEN_Pos) /**< (PWM_LEBR2) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMHFEN(value) (PWM_LEBR2_PWMHFEN_Msk & ((value) << PWM_LEBR2_PWMHFEN_Pos)) +#define PWM_LEBR2_PWMHREN_Pos _U_(19) /**< (PWM_LEBR2) PWMH Rising Edge Enable Position */ +#define PWM_LEBR2_PWMHREN_Msk (_U_(0x1) << PWM_LEBR2_PWMHREN_Pos) /**< (PWM_LEBR2) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMHREN(value) (PWM_LEBR2_PWMHREN_Msk & ((value) << PWM_LEBR2_PWMHREN_Pos)) +#define PWM_LEBR2_Msk _U_(0x000F007F) /**< (PWM_LEBR2) Register Mask */ + + +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) ( /W 32) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD3) Channel Polarity Update Position */ +#define PWM_CMUPD3_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Update Mask */ +#define PWM_CMUPD3_CPOLUP(value) (PWM_CMUPD3_CPOLUP_Msk & ((value) << PWM_CMUPD3_CPOLUP_Pos)) +#define PWM_CMUPD3_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD3) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD3_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLINVUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD3_CPOLINVUP(value) (PWM_CMUPD3_CPOLINVUP_Msk & ((value) << PWM_CMUPD3_CPOLINVUP_Pos)) +#define PWM_CMUPD3_Msk _U_(0x00002200) /**< (PWM_CMUPD3) Register Mask */ + + +/** \brief PWM register offsets definitions */ +#define PWM_CMR_REG_OFST (0x00) /**< (PWM_CMR) PWM Channel Mode Register (ch_num = 0) Offset */ +#define PWM_CDTY_REG_OFST (0x04) /**< (PWM_CDTY) PWM Channel Duty Cycle Register (ch_num = 0) Offset */ +#define PWM_CDTYUPD_REG_OFST (0x08) /**< (PWM_CDTYUPD) PWM Channel Duty Cycle Update Register (ch_num = 0) Offset */ +#define PWM_CPRD_REG_OFST (0x0C) /**< (PWM_CPRD) PWM Channel Period Register (ch_num = 0) Offset */ +#define PWM_CPRDUPD_REG_OFST (0x10) /**< (PWM_CPRDUPD) PWM Channel Period Update Register (ch_num = 0) Offset */ +#define PWM_CCNT_REG_OFST (0x14) /**< (PWM_CCNT) PWM Channel Counter Register (ch_num = 0) Offset */ +#define PWM_DT_REG_OFST (0x18) /**< (PWM_DT) PWM Channel Dead Time Register (ch_num = 0) Offset */ +#define PWM_DTUPD_REG_OFST (0x1C) /**< (PWM_DTUPD) PWM Channel Dead Time Update Register (ch_num = 0) Offset */ +#define PWM_CMPV_REG_OFST (0x00) /**< (PWM_CMPV) PWM Comparison 0 Value Register Offset */ +#define PWM_CMPVUPD_REG_OFST (0x04) /**< (PWM_CMPVUPD) PWM Comparison 0 Value Update Register Offset */ +#define PWM_CMPM_REG_OFST (0x08) /**< (PWM_CMPM) PWM Comparison 0 Mode Register Offset */ +#define PWM_CMPMUPD_REG_OFST (0x0C) /**< (PWM_CMPMUPD) PWM Comparison 0 Mode Update Register Offset */ +#define PWM_CLK_REG_OFST (0x00) /**< (PWM_CLK) PWM Clock Register Offset */ +#define PWM_ENA_REG_OFST (0x04) /**< (PWM_ENA) PWM Enable Register Offset */ +#define PWM_DIS_REG_OFST (0x08) /**< (PWM_DIS) PWM Disable Register Offset */ +#define PWM_SR_REG_OFST (0x0C) /**< (PWM_SR) PWM Status Register Offset */ +#define PWM_IER1_REG_OFST (0x10) /**< (PWM_IER1) PWM Interrupt Enable Register 1 Offset */ +#define PWM_IDR1_REG_OFST (0x14) /**< (PWM_IDR1) PWM Interrupt Disable Register 1 Offset */ +#define PWM_IMR1_REG_OFST (0x18) /**< (PWM_IMR1) PWM Interrupt Mask Register 1 Offset */ +#define PWM_ISR1_REG_OFST (0x1C) /**< (PWM_ISR1) PWM Interrupt Status Register 1 Offset */ +#define PWM_SCM_REG_OFST (0x20) /**< (PWM_SCM) PWM Sync Channels Mode Register Offset */ +#define PWM_DMAR_REG_OFST (0x24) /**< (PWM_DMAR) PWM DMA Register Offset */ +#define PWM_SCUC_REG_OFST (0x28) /**< (PWM_SCUC) PWM Sync Channels Update Control Register Offset */ +#define PWM_SCUP_REG_OFST (0x2C) /**< (PWM_SCUP) PWM Sync Channels Update Period Register Offset */ +#define PWM_SCUPUPD_REG_OFST (0x30) /**< (PWM_SCUPUPD) PWM Sync Channels Update Period Update Register Offset */ +#define PWM_IER2_REG_OFST (0x34) /**< (PWM_IER2) PWM Interrupt Enable Register 2 Offset */ +#define PWM_IDR2_REG_OFST (0x38) /**< (PWM_IDR2) PWM Interrupt Disable Register 2 Offset */ +#define PWM_IMR2_REG_OFST (0x3C) /**< (PWM_IMR2) PWM Interrupt Mask Register 2 Offset */ +#define PWM_ISR2_REG_OFST (0x40) /**< (PWM_ISR2) PWM Interrupt Status Register 2 Offset */ +#define PWM_OOV_REG_OFST (0x44) /**< (PWM_OOV) PWM Output Override Value Register Offset */ +#define PWM_OS_REG_OFST (0x48) /**< (PWM_OS) PWM Output Selection Register Offset */ +#define PWM_OSS_REG_OFST (0x4C) /**< (PWM_OSS) PWM Output Selection Set Register Offset */ +#define PWM_OSC_REG_OFST (0x50) /**< (PWM_OSC) PWM Output Selection Clear Register Offset */ +#define PWM_OSSUPD_REG_OFST (0x54) /**< (PWM_OSSUPD) PWM Output Selection Set Update Register Offset */ +#define PWM_OSCUPD_REG_OFST (0x58) /**< (PWM_OSCUPD) PWM Output Selection Clear Update Register Offset */ +#define PWM_FMR_REG_OFST (0x5C) /**< (PWM_FMR) PWM Fault Mode Register Offset */ +#define PWM_FSR_REG_OFST (0x60) /**< (PWM_FSR) PWM Fault Status Register Offset */ +#define PWM_FCR_REG_OFST (0x64) /**< (PWM_FCR) PWM Fault Clear Register Offset */ +#define PWM_FPV1_REG_OFST (0x68) /**< (PWM_FPV1) PWM Fault Protection Value Register 1 Offset */ +#define PWM_FPE_REG_OFST (0x6C) /**< (PWM_FPE) PWM Fault Protection Enable Register Offset */ +#define PWM_ELMR_REG_OFST (0x7C) /**< (PWM_ELMR) PWM Event Line 0 Mode Register 0 Offset */ +#define PWM_SSPR_REG_OFST (0xA0) /**< (PWM_SSPR) PWM Spread Spectrum Register Offset */ +#define PWM_SSPUP_REG_OFST (0xA4) /**< (PWM_SSPUP) PWM Spread Spectrum Update Register Offset */ +#define PWM_SMMR_REG_OFST (0xB0) /**< (PWM_SMMR) PWM Stepper Motor Mode Register Offset */ +#define PWM_FPV2_REG_OFST (0xC0) /**< (PWM_FPV2) PWM Fault Protection Value 2 Register Offset */ +#define PWM_WPCR_REG_OFST (0xE4) /**< (PWM_WPCR) PWM Write Protection Control Register Offset */ +#define PWM_WPSR_REG_OFST (0xE8) /**< (PWM_WPSR) PWM Write Protection Status Register Offset */ +#define PWM_CMUPD0_REG_OFST (0x400) /**< (PWM_CMUPD0) PWM Channel Mode Update Register (ch_num = 0) Offset */ +#define PWM_CMUPD1_REG_OFST (0x420) /**< (PWM_CMUPD1) PWM Channel Mode Update Register (ch_num = 1) Offset */ +#define PWM_ETRG1_REG_OFST (0x42C) /**< (PWM_ETRG1) PWM External Trigger Register (trg_num = 1) Offset */ +#define PWM_LEBR1_REG_OFST (0x430) /**< (PWM_LEBR1) PWM Leading-Edge Blanking Register (trg_num = 1) Offset */ +#define PWM_CMUPD2_REG_OFST (0x440) /**< (PWM_CMUPD2) PWM Channel Mode Update Register (ch_num = 2) Offset */ +#define PWM_ETRG2_REG_OFST (0x44C) /**< (PWM_ETRG2) PWM External Trigger Register (trg_num = 2) Offset */ +#define PWM_LEBR2_REG_OFST (0x450) /**< (PWM_LEBR2) PWM Leading-Edge Blanking Register (trg_num = 2) Offset */ +#define PWM_CMUPD3_REG_OFST (0x460) /**< (PWM_CMUPD3) PWM Channel Mode Update Register (ch_num = 3) Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PWM_CH_NUM register API structure */ +typedef struct +{ + __IO uint32_t PWM_CMR; /**< Offset: 0x00 (R/W 32) PWM Channel Mode Register (ch_num = 0) */ + __IO uint32_t PWM_CDTY; /**< Offset: 0x04 (R/W 32) PWM Channel Duty Cycle Register (ch_num = 0) */ + __O uint32_t PWM_CDTYUPD; /**< Offset: 0x08 ( /W 32) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + __IO uint32_t PWM_CPRD; /**< Offset: 0x0C (R/W 32) PWM Channel Period Register (ch_num = 0) */ + __O uint32_t PWM_CPRDUPD; /**< Offset: 0x10 ( /W 32) PWM Channel Period Update Register (ch_num = 0) */ + __I uint32_t PWM_CCNT; /**< Offset: 0x14 (R/ 32) PWM Channel Counter Register (ch_num = 0) */ + __IO uint32_t PWM_DT; /**< Offset: 0x18 (R/W 32) PWM Channel Dead Time Register (ch_num = 0) */ + __O uint32_t PWM_DTUPD; /**< Offset: 0x1C ( /W 32) PWM Channel Dead Time Update Register (ch_num = 0) */ +} pwm_ch_num_registers_t; + +/** \brief PWM_CMP register API structure */ +typedef struct +{ + __IO uint32_t PWM_CMPV; /**< Offset: 0x00 (R/W 32) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< Offset: 0x04 ( /W 32) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< Offset: 0x08 (R/W 32) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< Offset: 0x0C ( /W 32) PWM Comparison 0 Mode Update Register */ +} pwm_cmp_registers_t; + +#define PWM_CMP_NUMBER _U_(8) + +#define PWM_CH_NUM_NUMBER _U_(4) + +/** \brief PWM register API structure */ +typedef struct +{ + __IO uint32_t PWM_CLK; /**< Offset: 0x00 (R/W 32) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< Offset: 0x04 ( /W 32) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< Offset: 0x08 ( /W 32) PWM Disable Register */ + __I uint32_t PWM_SR; /**< Offset: 0x0C (R/ 32) PWM Status Register */ + __O uint32_t PWM_IER1; /**< Offset: 0x10 ( /W 32) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< Offset: 0x14 ( /W 32) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< Offset: 0x18 (R/ 32) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< Offset: 0x1C (R/ 32) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< Offset: 0x20 (R/W 32) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< Offset: 0x24 ( /W 32) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< Offset: 0x28 (R/W 32) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< Offset: 0x2C (R/W 32) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< Offset: 0x30 ( /W 32) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< Offset: 0x34 ( /W 32) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< Offset: 0x38 ( /W 32) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< Offset: 0x3C (R/ 32) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< Offset: 0x40 (R/ 32) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< Offset: 0x44 (R/W 32) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< Offset: 0x48 (R/W 32) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< Offset: 0x4C ( /W 32) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< Offset: 0x50 ( /W 32) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< Offset: 0x54 ( /W 32) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< Offset: 0x58 ( /W 32) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< Offset: 0x5C (R/W 32) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< Offset: 0x60 (R/ 32) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< Offset: 0x64 ( /W 32) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< Offset: 0x68 (R/W 32) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< Offset: 0x6C (R/W 32) PWM Fault Protection Enable Register */ + __I uint8_t Reserved1[0x0C]; + __IO uint32_t PWM_ELMR[2]; /**< Offset: 0x7C (R/W 32) PWM Event Line 0 Mode Register 0 */ + __I uint8_t Reserved2[0x1C]; + __IO uint32_t PWM_SSPR; /**< Offset: 0xA0 (R/W 32) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< Offset: 0xA4 ( /W 32) PWM Spread Spectrum Update Register */ + __I uint8_t Reserved3[0x08]; + __IO uint32_t PWM_SMMR; /**< Offset: 0xB0 (R/W 32) PWM Stepper Motor Mode Register */ + __I uint8_t Reserved4[0x0C]; + __IO uint32_t PWM_FPV2; /**< Offset: 0xC0 (R/W 32) PWM Fault Protection Value 2 Register */ + __I uint8_t Reserved5[0x20]; + __O uint32_t PWM_WPCR; /**< Offset: 0xE4 ( /W 32) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< Offset: 0xE8 (R/ 32) PWM Write Protection Status Register */ + __I uint8_t Reserved6[0x44]; + pwm_cmp_registers_t PWM_CMP[PWM_CMP_NUMBER]; /**< Offset: 0x130 PWM Comparison 0 Value Register */ + __I uint8_t Reserved7[0x50]; + pwm_ch_num_registers_t PWM_CH_NUM[PWM_CH_NUM_NUMBER]; /**< Offset: 0x200 PWM Channel Mode Register (ch_num = 0) */ + __I uint8_t Reserved8[0x180]; + __O uint32_t PWM_CMUPD0; /**< Offset: 0x400 ( /W 32) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint8_t Reserved9[0x1C]; + __O uint32_t PWM_CMUPD1; /**< Offset: 0x420 ( /W 32) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint8_t Reserved10[0x08]; + __IO uint32_t PWM_ETRG1; /**< Offset: 0x42C (R/W 32) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< Offset: 0x430 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint8_t Reserved11[0x0C]; + __O uint32_t PWM_CMUPD2; /**< Offset: 0x440 ( /W 32) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint8_t Reserved12[0x08]; + __IO uint32_t PWM_ETRG2; /**< Offset: 0x44C (R/W 32) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< Offset: 0x450 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint8_t Reserved13[0x0C]; + __O uint32_t PWM_CMUPD3; /**< Offset: 0x460 ( /W 32) PWM Channel Mode Update Register (ch_num = 3) */ +} pwm_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PWM_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/qspi.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/qspi.h new file mode 100644 index 00000000..be6992d2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/qspi.h @@ -0,0 +1,404 @@ +/** + * \brief Component description for QSPI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_QSPI_COMPONENT_H_ +#define _SAME70_QSPI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR QSPI */ +/* ************************************************************************** */ + +/* -------- QSPI_CR : (QSPI Offset: 0x00) ( /W 32) Control Register -------- */ +#define QSPI_CR_QSPIEN_Pos _U_(0) /**< (QSPI_CR) QSPI Enable Position */ +#define QSPI_CR_QSPIEN_Msk (_U_(0x1) << QSPI_CR_QSPIEN_Pos) /**< (QSPI_CR) QSPI Enable Mask */ +#define QSPI_CR_QSPIEN(value) (QSPI_CR_QSPIEN_Msk & ((value) << QSPI_CR_QSPIEN_Pos)) +#define QSPI_CR_QSPIDIS_Pos _U_(1) /**< (QSPI_CR) QSPI Disable Position */ +#define QSPI_CR_QSPIDIS_Msk (_U_(0x1) << QSPI_CR_QSPIDIS_Pos) /**< (QSPI_CR) QSPI Disable Mask */ +#define QSPI_CR_QSPIDIS(value) (QSPI_CR_QSPIDIS_Msk & ((value) << QSPI_CR_QSPIDIS_Pos)) +#define QSPI_CR_SWRST_Pos _U_(7) /**< (QSPI_CR) QSPI Software Reset Position */ +#define QSPI_CR_SWRST_Msk (_U_(0x1) << QSPI_CR_SWRST_Pos) /**< (QSPI_CR) QSPI Software Reset Mask */ +#define QSPI_CR_SWRST(value) (QSPI_CR_SWRST_Msk & ((value) << QSPI_CR_SWRST_Pos)) +#define QSPI_CR_LASTXFER_Pos _U_(24) /**< (QSPI_CR) Last Transfer Position */ +#define QSPI_CR_LASTXFER_Msk (_U_(0x1) << QSPI_CR_LASTXFER_Pos) /**< (QSPI_CR) Last Transfer Mask */ +#define QSPI_CR_LASTXFER(value) (QSPI_CR_LASTXFER_Msk & ((value) << QSPI_CR_LASTXFER_Pos)) +#define QSPI_CR_Msk _U_(0x01000083) /**< (QSPI_CR) Register Mask */ + + +/* -------- QSPI_MR : (QSPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define QSPI_MR_SMM_Pos _U_(0) /**< (QSPI_MR) Serial Memory Mode Position */ +#define QSPI_MR_SMM_Msk (_U_(0x1) << QSPI_MR_SMM_Pos) /**< (QSPI_MR) Serial Memory Mode Mask */ +#define QSPI_MR_SMM(value) (QSPI_MR_SMM_Msk & ((value) << QSPI_MR_SMM_Pos)) +#define QSPI_MR_SMM_SPI_Val _U_(0x0) /**< (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY_Val _U_(0x1) /**< (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_SMM_SPI (QSPI_MR_SMM_SPI_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in SPI mode. Position */ +#define QSPI_MR_SMM_MEMORY (QSPI_MR_SMM_MEMORY_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in Serial Memory mode. Position */ +#define QSPI_MR_LLB_Pos _U_(1) /**< (QSPI_MR) Local Loopback Enable Position */ +#define QSPI_MR_LLB_Msk (_U_(0x1) << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local Loopback Enable Mask */ +#define QSPI_MR_LLB(value) (QSPI_MR_LLB_Msk & ((value) << QSPI_MR_LLB_Pos)) +#define QSPI_MR_LLB_DISABLED_Val _U_(0x0) /**< (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED_Val _U_(0x1) /**< (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_LLB_DISABLED (QSPI_MR_LLB_DISABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path disabled. Position */ +#define QSPI_MR_LLB_ENABLED (QSPI_MR_LLB_ENABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path enabled. Position */ +#define QSPI_MR_WDRBT_Pos _U_(2) /**< (QSPI_MR) Wait Data Read Before Transfer Position */ +#define QSPI_MR_WDRBT_Msk (_U_(0x1) << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) Wait Data Read Before Transfer Mask */ +#define QSPI_MR_WDRBT(value) (QSPI_MR_WDRBT_Msk & ((value) << QSPI_MR_WDRBT_Pos)) +#define QSPI_MR_WDRBT_DISABLED_Val _U_(0x0) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED_Val _U_(0x1) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_WDRBT_DISABLED (QSPI_MR_WDRBT_DISABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. Position */ +#define QSPI_MR_WDRBT_ENABLED (QSPI_MR_WDRBT_ENABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. Position */ +#define QSPI_MR_CSMODE_Pos _U_(4) /**< (QSPI_MR) Chip Select Mode Position */ +#define QSPI_MR_CSMODE_Msk (_U_(0x3) << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) Chip Select Mode Mask */ +#define QSPI_MR_CSMODE(value) (QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)) +#define QSPI_MR_CSMODE_NOT_RELOADED_Val _U_(0x0) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_CSMODE_NOT_RELOADED (QSPI_MR_CSMODE_NOT_RELOADED_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. Position */ +#define QSPI_MR_CSMODE_LASTXFER (QSPI_MR_CSMODE_LASTXFER_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. Position */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (QSPI_MR_CSMODE_SYSTEMATICALLY_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. Position */ +#define QSPI_MR_NBBITS_Pos _U_(8) /**< (QSPI_MR) Number Of Bits Per Transfer Position */ +#define QSPI_MR_NBBITS_Msk (_U_(0xF) << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) Number Of Bits Per Transfer Mask */ +#define QSPI_MR_NBBITS(value) (QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)) +#define QSPI_MR_NBBITS_8_BIT_Val _U_(0x0) /**< (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT_Val _U_(0x8) /**< (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_NBBITS_8_BIT (QSPI_MR_NBBITS_8_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 8 bits for transfer Position */ +#define QSPI_MR_NBBITS_16_BIT (QSPI_MR_NBBITS_16_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 16 bits for transfer Position */ +#define QSPI_MR_DLYBCT_Pos _U_(16) /**< (QSPI_MR) Delay Between Consecutive Transfers Position */ +#define QSPI_MR_DLYBCT_Msk (_U_(0xFF) << QSPI_MR_DLYBCT_Pos) /**< (QSPI_MR) Delay Between Consecutive Transfers Mask */ +#define QSPI_MR_DLYBCT(value) (QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)) +#define QSPI_MR_DLYCS_Pos _U_(24) /**< (QSPI_MR) Minimum Inactive QCS Delay Position */ +#define QSPI_MR_DLYCS_Msk (_U_(0xFF) << QSPI_MR_DLYCS_Pos) /**< (QSPI_MR) Minimum Inactive QCS Delay Mask */ +#define QSPI_MR_DLYCS(value) (QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)) +#define QSPI_MR_Msk _U_(0xFFFF0F37) /**< (QSPI_MR) Register Mask */ + + +/* -------- QSPI_RDR : (QSPI Offset: 0x08) ( R/ 32) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos _U_(0) /**< (QSPI_RDR) Receive Data Position */ +#define QSPI_RDR_RD_Msk (_U_(0xFFFF) << QSPI_RDR_RD_Pos) /**< (QSPI_RDR) Receive Data Mask */ +#define QSPI_RDR_RD(value) (QSPI_RDR_RD_Msk & ((value) << QSPI_RDR_RD_Pos)) +#define QSPI_RDR_Msk _U_(0x0000FFFF) /**< (QSPI_RDR) Register Mask */ + + +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) ( /W 32) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos _U_(0) /**< (QSPI_TDR) Transmit Data Position */ +#define QSPI_TDR_TD_Msk (_U_(0xFFFF) << QSPI_TDR_TD_Pos) /**< (QSPI_TDR) Transmit Data Mask */ +#define QSPI_TDR_TD(value) (QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)) +#define QSPI_TDR_Msk _U_(0x0000FFFF) /**< (QSPI_TDR) Register Mask */ + + +/* -------- QSPI_SR : (QSPI Offset: 0x10) ( R/ 32) Status Register -------- */ +#define QSPI_SR_RDRF_Pos _U_(0) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define QSPI_SR_RDRF_Msk (_U_(0x1) << QSPI_SR_RDRF_Pos) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define QSPI_SR_RDRF(value) (QSPI_SR_RDRF_Msk & ((value) << QSPI_SR_RDRF_Pos)) +#define QSPI_SR_TDRE_Pos _U_(1) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TDRE_Msk (_U_(0x1) << QSPI_SR_TDRE_Pos) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TDRE(value) (QSPI_SR_TDRE_Msk & ((value) << QSPI_SR_TDRE_Pos)) +#define QSPI_SR_TXEMPTY_Pos _U_(2) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TXEMPTY_Msk (_U_(0x1) << QSPI_SR_TXEMPTY_Pos) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TXEMPTY(value) (QSPI_SR_TXEMPTY_Msk & ((value) << QSPI_SR_TXEMPTY_Pos)) +#define QSPI_SR_OVRES_Pos _U_(3) /**< (QSPI_SR) Overrun Error Status (cleared on read) Position */ +#define QSPI_SR_OVRES_Msk (_U_(0x1) << QSPI_SR_OVRES_Pos) /**< (QSPI_SR) Overrun Error Status (cleared on read) Mask */ +#define QSPI_SR_OVRES(value) (QSPI_SR_OVRES_Msk & ((value) << QSPI_SR_OVRES_Pos)) +#define QSPI_SR_CSR_Pos _U_(8) /**< (QSPI_SR) Chip Select Rise (cleared on read) Position */ +#define QSPI_SR_CSR_Msk (_U_(0x1) << QSPI_SR_CSR_Pos) /**< (QSPI_SR) Chip Select Rise (cleared on read) Mask */ +#define QSPI_SR_CSR(value) (QSPI_SR_CSR_Msk & ((value) << QSPI_SR_CSR_Pos)) +#define QSPI_SR_CSS_Pos _U_(9) /**< (QSPI_SR) Chip Select Status Position */ +#define QSPI_SR_CSS_Msk (_U_(0x1) << QSPI_SR_CSS_Pos) /**< (QSPI_SR) Chip Select Status Mask */ +#define QSPI_SR_CSS(value) (QSPI_SR_CSS_Msk & ((value) << QSPI_SR_CSS_Pos)) +#define QSPI_SR_INSTRE_Pos _U_(10) /**< (QSPI_SR) Instruction End Status (cleared on read) Position */ +#define QSPI_SR_INSTRE_Msk (_U_(0x1) << QSPI_SR_INSTRE_Pos) /**< (QSPI_SR) Instruction End Status (cleared on read) Mask */ +#define QSPI_SR_INSTRE(value) (QSPI_SR_INSTRE_Msk & ((value) << QSPI_SR_INSTRE_Pos)) +#define QSPI_SR_QSPIENS_Pos _U_(24) /**< (QSPI_SR) QSPI Enable Status Position */ +#define QSPI_SR_QSPIENS_Msk (_U_(0x1) << QSPI_SR_QSPIENS_Pos) /**< (QSPI_SR) QSPI Enable Status Mask */ +#define QSPI_SR_QSPIENS(value) (QSPI_SR_QSPIENS_Msk & ((value) << QSPI_SR_QSPIENS_Pos)) +#define QSPI_SR_Msk _U_(0x0100070F) /**< (QSPI_SR) Register Mask */ + + +/* -------- QSPI_IER : (QSPI Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF_Pos _U_(0) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define QSPI_IER_RDRF_Msk (_U_(0x1) << QSPI_IER_RDRF_Pos) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define QSPI_IER_RDRF(value) (QSPI_IER_RDRF_Msk & ((value) << QSPI_IER_RDRF_Pos)) +#define QSPI_IER_TDRE_Pos _U_(1) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Position */ +#define QSPI_IER_TDRE_Msk (_U_(0x1) << QSPI_IER_TDRE_Pos) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Mask */ +#define QSPI_IER_TDRE(value) (QSPI_IER_TDRE_Msk & ((value) << QSPI_IER_TDRE_Pos)) +#define QSPI_IER_TXEMPTY_Pos _U_(2) /**< (QSPI_IER) Transmission Registers Empty Enable Position */ +#define QSPI_IER_TXEMPTY_Msk (_U_(0x1) << QSPI_IER_TXEMPTY_Pos) /**< (QSPI_IER) Transmission Registers Empty Enable Mask */ +#define QSPI_IER_TXEMPTY(value) (QSPI_IER_TXEMPTY_Msk & ((value) << QSPI_IER_TXEMPTY_Pos)) +#define QSPI_IER_OVRES_Pos _U_(3) /**< (QSPI_IER) Overrun Error Interrupt Enable Position */ +#define QSPI_IER_OVRES_Msk (_U_(0x1) << QSPI_IER_OVRES_Pos) /**< (QSPI_IER) Overrun Error Interrupt Enable Mask */ +#define QSPI_IER_OVRES(value) (QSPI_IER_OVRES_Msk & ((value) << QSPI_IER_OVRES_Pos)) +#define QSPI_IER_CSR_Pos _U_(8) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Position */ +#define QSPI_IER_CSR_Msk (_U_(0x1) << QSPI_IER_CSR_Pos) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Mask */ +#define QSPI_IER_CSR(value) (QSPI_IER_CSR_Msk & ((value) << QSPI_IER_CSR_Pos)) +#define QSPI_IER_CSS_Pos _U_(9) /**< (QSPI_IER) Chip Select Status Interrupt Enable Position */ +#define QSPI_IER_CSS_Msk (_U_(0x1) << QSPI_IER_CSS_Pos) /**< (QSPI_IER) Chip Select Status Interrupt Enable Mask */ +#define QSPI_IER_CSS(value) (QSPI_IER_CSS_Msk & ((value) << QSPI_IER_CSS_Pos)) +#define QSPI_IER_INSTRE_Pos _U_(10) /**< (QSPI_IER) Instruction End Interrupt Enable Position */ +#define QSPI_IER_INSTRE_Msk (_U_(0x1) << QSPI_IER_INSTRE_Pos) /**< (QSPI_IER) Instruction End Interrupt Enable Mask */ +#define QSPI_IER_INSTRE(value) (QSPI_IER_INSTRE_Msk & ((value) << QSPI_IER_INSTRE_Pos)) +#define QSPI_IER_Msk _U_(0x0000070F) /**< (QSPI_IER) Register Mask */ + + +/* -------- QSPI_IDR : (QSPI Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF_Pos _U_(0) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define QSPI_IDR_RDRF_Msk (_U_(0x1) << QSPI_IDR_RDRF_Pos) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define QSPI_IDR_RDRF(value) (QSPI_IDR_RDRF_Msk & ((value) << QSPI_IDR_RDRF_Pos)) +#define QSPI_IDR_TDRE_Pos _U_(1) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Position */ +#define QSPI_IDR_TDRE_Msk (_U_(0x1) << QSPI_IDR_TDRE_Pos) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Mask */ +#define QSPI_IDR_TDRE(value) (QSPI_IDR_TDRE_Msk & ((value) << QSPI_IDR_TDRE_Pos)) +#define QSPI_IDR_TXEMPTY_Pos _U_(2) /**< (QSPI_IDR) Transmission Registers Empty Disable Position */ +#define QSPI_IDR_TXEMPTY_Msk (_U_(0x1) << QSPI_IDR_TXEMPTY_Pos) /**< (QSPI_IDR) Transmission Registers Empty Disable Mask */ +#define QSPI_IDR_TXEMPTY(value) (QSPI_IDR_TXEMPTY_Msk & ((value) << QSPI_IDR_TXEMPTY_Pos)) +#define QSPI_IDR_OVRES_Pos _U_(3) /**< (QSPI_IDR) Overrun Error Interrupt Disable Position */ +#define QSPI_IDR_OVRES_Msk (_U_(0x1) << QSPI_IDR_OVRES_Pos) /**< (QSPI_IDR) Overrun Error Interrupt Disable Mask */ +#define QSPI_IDR_OVRES(value) (QSPI_IDR_OVRES_Msk & ((value) << QSPI_IDR_OVRES_Pos)) +#define QSPI_IDR_CSR_Pos _U_(8) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Position */ +#define QSPI_IDR_CSR_Msk (_U_(0x1) << QSPI_IDR_CSR_Pos) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Mask */ +#define QSPI_IDR_CSR(value) (QSPI_IDR_CSR_Msk & ((value) << QSPI_IDR_CSR_Pos)) +#define QSPI_IDR_CSS_Pos _U_(9) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Position */ +#define QSPI_IDR_CSS_Msk (_U_(0x1) << QSPI_IDR_CSS_Pos) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Mask */ +#define QSPI_IDR_CSS(value) (QSPI_IDR_CSS_Msk & ((value) << QSPI_IDR_CSS_Pos)) +#define QSPI_IDR_INSTRE_Pos _U_(10) /**< (QSPI_IDR) Instruction End Interrupt Disable Position */ +#define QSPI_IDR_INSTRE_Msk (_U_(0x1) << QSPI_IDR_INSTRE_Pos) /**< (QSPI_IDR) Instruction End Interrupt Disable Mask */ +#define QSPI_IDR_INSTRE(value) (QSPI_IDR_INSTRE_Msk & ((value) << QSPI_IDR_INSTRE_Pos)) +#define QSPI_IDR_Msk _U_(0x0000070F) /**< (QSPI_IDR) Register Mask */ + + +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) ( R/ 32) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF_Pos _U_(0) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define QSPI_IMR_RDRF_Msk (_U_(0x1) << QSPI_IMR_RDRF_Pos) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define QSPI_IMR_RDRF(value) (QSPI_IMR_RDRF_Msk & ((value) << QSPI_IMR_RDRF_Pos)) +#define QSPI_IMR_TDRE_Pos _U_(1) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Position */ +#define QSPI_IMR_TDRE_Msk (_U_(0x1) << QSPI_IMR_TDRE_Pos) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Mask */ +#define QSPI_IMR_TDRE(value) (QSPI_IMR_TDRE_Msk & ((value) << QSPI_IMR_TDRE_Pos)) +#define QSPI_IMR_TXEMPTY_Pos _U_(2) /**< (QSPI_IMR) Transmission Registers Empty Mask Position */ +#define QSPI_IMR_TXEMPTY_Msk (_U_(0x1) << QSPI_IMR_TXEMPTY_Pos) /**< (QSPI_IMR) Transmission Registers Empty Mask Mask */ +#define QSPI_IMR_TXEMPTY(value) (QSPI_IMR_TXEMPTY_Msk & ((value) << QSPI_IMR_TXEMPTY_Pos)) +#define QSPI_IMR_OVRES_Pos _U_(3) /**< (QSPI_IMR) Overrun Error Interrupt Mask Position */ +#define QSPI_IMR_OVRES_Msk (_U_(0x1) << QSPI_IMR_OVRES_Pos) /**< (QSPI_IMR) Overrun Error Interrupt Mask Mask */ +#define QSPI_IMR_OVRES(value) (QSPI_IMR_OVRES_Msk & ((value) << QSPI_IMR_OVRES_Pos)) +#define QSPI_IMR_CSR_Pos _U_(8) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Position */ +#define QSPI_IMR_CSR_Msk (_U_(0x1) << QSPI_IMR_CSR_Pos) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Mask */ +#define QSPI_IMR_CSR(value) (QSPI_IMR_CSR_Msk & ((value) << QSPI_IMR_CSR_Pos)) +#define QSPI_IMR_CSS_Pos _U_(9) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Position */ +#define QSPI_IMR_CSS_Msk (_U_(0x1) << QSPI_IMR_CSS_Pos) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Mask */ +#define QSPI_IMR_CSS(value) (QSPI_IMR_CSS_Msk & ((value) << QSPI_IMR_CSS_Pos)) +#define QSPI_IMR_INSTRE_Pos _U_(10) /**< (QSPI_IMR) Instruction End Interrupt Mask Position */ +#define QSPI_IMR_INSTRE_Msk (_U_(0x1) << QSPI_IMR_INSTRE_Pos) /**< (QSPI_IMR) Instruction End Interrupt Mask Mask */ +#define QSPI_IMR_INSTRE(value) (QSPI_IMR_INSTRE_Msk & ((value) << QSPI_IMR_INSTRE_Pos)) +#define QSPI_IMR_Msk _U_(0x0000070F) /**< (QSPI_IMR) Register Mask */ + + +/* -------- QSPI_SCR : (QSPI Offset: 0x20) (R/W 32) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL_Pos _U_(0) /**< (QSPI_SCR) Clock Polarity Position */ +#define QSPI_SCR_CPOL_Msk (_U_(0x1) << QSPI_SCR_CPOL_Pos) /**< (QSPI_SCR) Clock Polarity Mask */ +#define QSPI_SCR_CPOL(value) (QSPI_SCR_CPOL_Msk & ((value) << QSPI_SCR_CPOL_Pos)) +#define QSPI_SCR_CPHA_Pos _U_(1) /**< (QSPI_SCR) Clock Phase Position */ +#define QSPI_SCR_CPHA_Msk (_U_(0x1) << QSPI_SCR_CPHA_Pos) /**< (QSPI_SCR) Clock Phase Mask */ +#define QSPI_SCR_CPHA(value) (QSPI_SCR_CPHA_Msk & ((value) << QSPI_SCR_CPHA_Pos)) +#define QSPI_SCR_SCBR_Pos _U_(8) /**< (QSPI_SCR) Serial Clock Baud Rate Position */ +#define QSPI_SCR_SCBR_Msk (_U_(0xFF) << QSPI_SCR_SCBR_Pos) /**< (QSPI_SCR) Serial Clock Baud Rate Mask */ +#define QSPI_SCR_SCBR(value) (QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)) +#define QSPI_SCR_DLYBS_Pos _U_(16) /**< (QSPI_SCR) Delay Before QSCK Position */ +#define QSPI_SCR_DLYBS_Msk (_U_(0xFF) << QSPI_SCR_DLYBS_Pos) /**< (QSPI_SCR) Delay Before QSCK Mask */ +#define QSPI_SCR_DLYBS(value) (QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)) +#define QSPI_SCR_Msk _U_(0x00FFFF03) /**< (QSPI_SCR) Register Mask */ + + +/* -------- QSPI_IAR : (QSPI Offset: 0x30) (R/W 32) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos _U_(0) /**< (QSPI_IAR) Address Position */ +#define QSPI_IAR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_IAR_ADDR_Pos) /**< (QSPI_IAR) Address Mask */ +#define QSPI_IAR_ADDR(value) (QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)) +#define QSPI_IAR_Msk _U_(0xFFFFFFFF) /**< (QSPI_IAR) Register Mask */ + + +/* -------- QSPI_ICR : (QSPI Offset: 0x34) (R/W 32) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos _U_(0) /**< (QSPI_ICR) Instruction Code Position */ +#define QSPI_ICR_INST_Msk (_U_(0xFF) << QSPI_ICR_INST_Pos) /**< (QSPI_ICR) Instruction Code Mask */ +#define QSPI_ICR_INST(value) (QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)) +#define QSPI_ICR_OPT_Pos _U_(16) /**< (QSPI_ICR) Option Code Position */ +#define QSPI_ICR_OPT_Msk (_U_(0xFF) << QSPI_ICR_OPT_Pos) /**< (QSPI_ICR) Option Code Mask */ +#define QSPI_ICR_OPT(value) (QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)) +#define QSPI_ICR_Msk _U_(0x00FF00FF) /**< (QSPI_ICR) Register Mask */ + + +/* -------- QSPI_IFR : (QSPI Offset: 0x38) (R/W 32) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos _U_(0) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Position */ +#define QSPI_IFR_WIDTH_Msk (_U_(0x7) << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Mask */ +#define QSPI_IFR_WIDTH(value) (QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (QSPI_IFR_WIDTH_DUAL_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (QSPI_IFR_WIDTH_QUAD_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_IO (QSPI_IFR_WIDTH_DUAL_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_IO (QSPI_IFR_WIDTH_QUAD_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_CMD (QSPI_IFR_WIDTH_DUAL_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_CMD (QSPI_IFR_WIDTH_QUAD_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_INSTEN_Pos _U_(4) /**< (QSPI_IFR) Instruction Enable Position */ +#define QSPI_IFR_INSTEN_Msk (_U_(0x1) << QSPI_IFR_INSTEN_Pos) /**< (QSPI_IFR) Instruction Enable Mask */ +#define QSPI_IFR_INSTEN(value) (QSPI_IFR_INSTEN_Msk & ((value) << QSPI_IFR_INSTEN_Pos)) +#define QSPI_IFR_ADDREN_Pos _U_(5) /**< (QSPI_IFR) Address Enable Position */ +#define QSPI_IFR_ADDREN_Msk (_U_(0x1) << QSPI_IFR_ADDREN_Pos) /**< (QSPI_IFR) Address Enable Mask */ +#define QSPI_IFR_ADDREN(value) (QSPI_IFR_ADDREN_Msk & ((value) << QSPI_IFR_ADDREN_Pos)) +#define QSPI_IFR_OPTEN_Pos _U_(6) /**< (QSPI_IFR) Option Enable Position */ +#define QSPI_IFR_OPTEN_Msk (_U_(0x1) << QSPI_IFR_OPTEN_Pos) /**< (QSPI_IFR) Option Enable Mask */ +#define QSPI_IFR_OPTEN(value) (QSPI_IFR_OPTEN_Msk & ((value) << QSPI_IFR_OPTEN_Pos)) +#define QSPI_IFR_DATAEN_Pos _U_(7) /**< (QSPI_IFR) Data Enable Position */ +#define QSPI_IFR_DATAEN_Msk (_U_(0x1) << QSPI_IFR_DATAEN_Pos) /**< (QSPI_IFR) Data Enable Mask */ +#define QSPI_IFR_DATAEN(value) (QSPI_IFR_DATAEN_Msk & ((value) << QSPI_IFR_DATAEN_Pos)) +#define QSPI_IFR_OPTL_Pos _U_(8) /**< (QSPI_IFR) Option Code Length Position */ +#define QSPI_IFR_OPTL_Msk (_U_(0x3) << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) Option Code Length Mask */ +#define QSPI_IFR_OPTL(value) (QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)) +#define QSPI_IFR_OPTL_OPTION_1BIT_Val _U_(0x0) /**< (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT_Val _U_(0x1) /**< (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT_Val _U_(0x2) /**< (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT_Val _U_(0x3) /**< (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_OPTL_OPTION_1BIT (QSPI_IFR_OPTL_OPTION_1BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 1 bit long. Position */ +#define QSPI_IFR_OPTL_OPTION_2BIT (QSPI_IFR_OPTL_OPTION_2BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 2 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_4BIT (QSPI_IFR_OPTL_OPTION_4BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 4 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_8BIT (QSPI_IFR_OPTL_OPTION_8BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 8 bits long. Position */ +#define QSPI_IFR_ADDRL_Pos _U_(10) /**< (QSPI_IFR) Address Length Position */ +#define QSPI_IFR_ADDRL_Msk (_U_(0x1) << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) Address Length Mask */ +#define QSPI_IFR_ADDRL(value) (QSPI_IFR_ADDRL_Msk & ((value) << QSPI_IFR_ADDRL_Pos)) +#define QSPI_IFR_ADDRL_24_BIT_Val _U_(0x0) /**< (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT_Val _U_(0x1) /**< (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_ADDRL_24_BIT (QSPI_IFR_ADDRL_24_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 24 bits long. Position */ +#define QSPI_IFR_ADDRL_32_BIT (QSPI_IFR_ADDRL_32_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 32 bits long. Position */ +#define QSPI_IFR_TFRTYP_Pos _U_(12) /**< (QSPI_IFR) Data Transfer Type Position */ +#define QSPI_IFR_TFRTYP_Msk (_U_(0x3) << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Data Transfer Type Mask */ +#define QSPI_IFR_TFRTYP(value) (QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)) +#define QSPI_IFR_TFRTYP_TRSFR_READ_Val _U_(0x0) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val _U_(0x1) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_Val _U_(0x2) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val _U_(0x3) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ (QSPI_IFR_TFRTYP_TRSFR_READ_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (QSPI_IFR_TFRTYP_TRSFR_WRITE_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */ +#define QSPI_IFR_CRM_Pos _U_(14) /**< (QSPI_IFR) Continuous Read Mode Position */ +#define QSPI_IFR_CRM_Msk (_U_(0x1) << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) Continuous Read Mode Mask */ +#define QSPI_IFR_CRM(value) (QSPI_IFR_CRM_Msk & ((value) << QSPI_IFR_CRM_Pos)) +#define QSPI_IFR_CRM_DISABLED_Val _U_(0x0) /**< (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED_Val _U_(0x1) /**< (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_CRM_DISABLED (QSPI_IFR_CRM_DISABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is disabled. Position */ +#define QSPI_IFR_CRM_ENABLED (QSPI_IFR_CRM_ENABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is enabled. Position */ +#define QSPI_IFR_NBDUM_Pos _U_(16) /**< (QSPI_IFR) Number Of Dummy Cycles Position */ +#define QSPI_IFR_NBDUM_Msk (_U_(0x1F) << QSPI_IFR_NBDUM_Pos) /**< (QSPI_IFR) Number Of Dummy Cycles Mask */ +#define QSPI_IFR_NBDUM(value) (QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)) +#define QSPI_IFR_Msk _U_(0x001F77F7) /**< (QSPI_IFR) Register Mask */ + + +/* -------- QSPI_SMR : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN_Pos _U_(0) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Position */ +#define QSPI_SMR_SCREN_Msk (_U_(0x1) << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Mask */ +#define QSPI_SMR_SCREN(value) (QSPI_SMR_SCREN_Msk & ((value) << QSPI_SMR_SCREN_Pos)) +#define QSPI_SMR_SCREN_DISABLED_Val _U_(0x0) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED_Val _U_(0x1) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_SCREN_DISABLED (QSPI_SMR_SCREN_DISABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. Position */ +#define QSPI_SMR_SCREN_ENABLED (QSPI_SMR_SCREN_ENABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. Position */ +#define QSPI_SMR_RVDIS_Pos _U_(1) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Position */ +#define QSPI_SMR_RVDIS_Msk (_U_(0x1) << QSPI_SMR_RVDIS_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Mask */ +#define QSPI_SMR_RVDIS(value) (QSPI_SMR_RVDIS_Msk & ((value) << QSPI_SMR_RVDIS_Pos)) +#define QSPI_SMR_Msk _U_(0x00000003) /**< (QSPI_SMR) Register Mask */ + + +/* -------- QSPI_SKR : (QSPI Offset: 0x44) ( /W 32) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos _U_(0) /**< (QSPI_SKR) Scrambling User Key Position */ +#define QSPI_SKR_USRK_Msk (_U_(0xFFFFFFFF) << QSPI_SKR_USRK_Pos) /**< (QSPI_SKR) Scrambling User Key Mask */ +#define QSPI_SKR_USRK(value) (QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)) +#define QSPI_SKR_Msk _U_(0xFFFFFFFF) /**< (QSPI_SKR) Register Mask */ + + +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN_Pos _U_(0) /**< (QSPI_WPMR) Write Protection Enable Position */ +#define QSPI_WPMR_WPEN_Msk (_U_(0x1) << QSPI_WPMR_WPEN_Pos) /**< (QSPI_WPMR) Write Protection Enable Mask */ +#define QSPI_WPMR_WPEN(value) (QSPI_WPMR_WPEN_Msk & ((value) << QSPI_WPMR_WPEN_Pos)) +#define QSPI_WPMR_WPKEY_Pos _U_(8) /**< (QSPI_WPMR) Write Protection Key Position */ +#define QSPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Write Protection Key Mask */ +#define QSPI_WPMR_WPKEY(value) (QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)) +#define QSPI_WPMR_WPKEY_PASSWD_Val _U_(0x515350) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define QSPI_WPMR_WPKEY_PASSWD (QSPI_WPMR_WPKEY_PASSWD_Val << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define QSPI_WPMR_Msk _U_(0xFFFFFF01) /**< (QSPI_WPMR) Register Mask */ + + +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS_Pos _U_(0) /**< (QSPI_WPSR) Write Protection Violation Status Position */ +#define QSPI_WPSR_WPVS_Msk (_U_(0x1) << QSPI_WPSR_WPVS_Pos) /**< (QSPI_WPSR) Write Protection Violation Status Mask */ +#define QSPI_WPSR_WPVS(value) (QSPI_WPSR_WPVS_Msk & ((value) << QSPI_WPSR_WPVS_Pos)) +#define QSPI_WPSR_WPVSRC_Pos _U_(8) /**< (QSPI_WPSR) Write Protection Violation Source Position */ +#define QSPI_WPSR_WPVSRC_Msk (_U_(0xFF) << QSPI_WPSR_WPVSRC_Pos) /**< (QSPI_WPSR) Write Protection Violation Source Mask */ +#define QSPI_WPSR_WPVSRC(value) (QSPI_WPSR_WPVSRC_Msk & ((value) << QSPI_WPSR_WPVSRC_Pos)) +#define QSPI_WPSR_Msk _U_(0x0000FF01) /**< (QSPI_WPSR) Register Mask */ + + +/** \brief QSPI register offsets definitions */ +#define QSPI_CR_REG_OFST (0x00) /**< (QSPI_CR) Control Register Offset */ +#define QSPI_MR_REG_OFST (0x04) /**< (QSPI_MR) Mode Register Offset */ +#define QSPI_RDR_REG_OFST (0x08) /**< (QSPI_RDR) Receive Data Register Offset */ +#define QSPI_TDR_REG_OFST (0x0C) /**< (QSPI_TDR) Transmit Data Register Offset */ +#define QSPI_SR_REG_OFST (0x10) /**< (QSPI_SR) Status Register Offset */ +#define QSPI_IER_REG_OFST (0x14) /**< (QSPI_IER) Interrupt Enable Register Offset */ +#define QSPI_IDR_REG_OFST (0x18) /**< (QSPI_IDR) Interrupt Disable Register Offset */ +#define QSPI_IMR_REG_OFST (0x1C) /**< (QSPI_IMR) Interrupt Mask Register Offset */ +#define QSPI_SCR_REG_OFST (0x20) /**< (QSPI_SCR) Serial Clock Register Offset */ +#define QSPI_IAR_REG_OFST (0x30) /**< (QSPI_IAR) Instruction Address Register Offset */ +#define QSPI_ICR_REG_OFST (0x34) /**< (QSPI_ICR) Instruction Code Register Offset */ +#define QSPI_IFR_REG_OFST (0x38) /**< (QSPI_IFR) Instruction Frame Register Offset */ +#define QSPI_SMR_REG_OFST (0x40) /**< (QSPI_SMR) Scrambling Mode Register Offset */ +#define QSPI_SKR_REG_OFST (0x44) /**< (QSPI_SKR) Scrambling Key Register Offset */ +#define QSPI_WPMR_REG_OFST (0xE4) /**< (QSPI_WPMR) Write Protection Mode Register Offset */ +#define QSPI_WPSR_REG_OFST (0xE8) /**< (QSPI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief QSPI register API structure */ +typedef struct +{ + __O uint32_t QSPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t QSPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t QSPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O uint32_t QSPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< Offset: 0x20 (R/W 32) Serial Clock Register */ + __I uint8_t Reserved1[0x0C]; + __IO uint32_t QSPI_IAR; /**< Offset: 0x30 (R/W 32) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< Offset: 0x34 (R/W 32) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< Offset: 0x38 (R/W 32) Instruction Frame Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t QSPI_SMR; /**< Offset: 0x40 (R/W 32) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< Offset: 0x44 ( /W 32) Scrambling Key Register */ + __I uint8_t Reserved3[0x9C]; + __IO uint32_t QSPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} qspi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_QSPI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/rstc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/rstc.h new file mode 100644 index 00000000..33e67e83 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/rstc.h @@ -0,0 +1,106 @@ +/** + * \brief Component description for RSTC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_RSTC_COMPONENT_H_ +#define _SAME70_RSTC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RSTC */ +/* ************************************************************************** */ + +/* -------- RSTC_CR : (RSTC Offset: 0x00) ( /W 32) Control Register -------- */ +#define RSTC_CR_PROCRST_Pos _U_(0) /**< (RSTC_CR) Processor Reset Position */ +#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */ +#define RSTC_CR_PROCRST(value) (RSTC_CR_PROCRST_Msk & ((value) << RSTC_CR_PROCRST_Pos)) +#define RSTC_CR_EXTRST_Pos _U_(3) /**< (RSTC_CR) External Reset Position */ +#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */ +#define RSTC_CR_EXTRST(value) (RSTC_CR_EXTRST_Msk & ((value) << RSTC_CR_EXTRST_Pos)) +#define RSTC_CR_KEY_Pos _U_(24) /**< (RSTC_CR) System Reset Key Position */ +#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */ +#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)) +#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */ +#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */ + + +/* -------- RSTC_SR : (RSTC Offset: 0x04) ( R/ 32) Status Register -------- */ +#define RSTC_SR_URSTS_Pos _U_(0) /**< (RSTC_SR) User Reset Status Position */ +#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */ +#define RSTC_SR_URSTS(value) (RSTC_SR_URSTS_Msk & ((value) << RSTC_SR_URSTS_Pos)) +#define RSTC_SR_RSTTYP_Pos _U_(8) /**< (RSTC_SR) Reset Type Position */ +#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */ +#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos)) +#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */ +#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */ +#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */ +#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */ +#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */ +#define RSTC_SR_NRSTL_Pos _U_(16) /**< (RSTC_SR) NRST Pin Level Position */ +#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */ +#define RSTC_SR_NRSTL(value) (RSTC_SR_NRSTL_Msk & ((value) << RSTC_SR_NRSTL_Pos)) +#define RSTC_SR_SRCMP_Pos _U_(17) /**< (RSTC_SR) Software Reset Command in Progress Position */ +#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */ +#define RSTC_SR_SRCMP(value) (RSTC_SR_SRCMP_Msk & ((value) << RSTC_SR_SRCMP_Pos)) +#define RSTC_SR_Msk _U_(0x00030701) /**< (RSTC_SR) Register Mask */ + + +/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */ +#define RSTC_MR_URSTEN_Pos _U_(0) /**< (RSTC_MR) User Reset Enable Position */ +#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */ +#define RSTC_MR_URSTEN(value) (RSTC_MR_URSTEN_Msk & ((value) << RSTC_MR_URSTEN_Pos)) +#define RSTC_MR_URSTIEN_Pos _U_(4) /**< (RSTC_MR) User Reset Interrupt Enable Position */ +#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */ +#define RSTC_MR_URSTIEN(value) (RSTC_MR_URSTIEN_Msk & ((value) << RSTC_MR_URSTIEN_Pos)) +#define RSTC_MR_ERSTL_Pos _U_(8) /**< (RSTC_MR) External Reset Length Position */ +#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */ +#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)) +#define RSTC_MR_KEY_Pos _U_(24) /**< (RSTC_MR) Write Access Password Position */ +#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */ +#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)) +#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */ + + +/** \brief RSTC register offsets definitions */ +#define RSTC_CR_REG_OFST (0x00) /**< (RSTC_CR) Control Register Offset */ +#define RSTC_SR_REG_OFST (0x04) /**< (RSTC_SR) Status Register Offset */ +#define RSTC_MR_REG_OFST (0x08) /**< (RSTC_MR) Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RSTC register API structure */ +typedef struct +{ + __O uint32_t RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I uint32_t RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */ + __IO uint32_t RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */ +} rstc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RSTC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/rswdt.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/rswdt.h new file mode 100644 index 00000000..2e6a847c --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/rswdt.h @@ -0,0 +1,91 @@ +/** + * \brief Component description for RSWDT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_RSWDT_COMPONENT_H_ +#define _SAME70_RSWDT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RSWDT */ +/* ************************************************************************** */ + +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) ( /W 32) Control Register -------- */ +#define RSWDT_CR_WDRSTT_Pos _U_(0) /**< (RSWDT_CR) Watchdog Restart Position */ +#define RSWDT_CR_WDRSTT_Msk (_U_(0x1) << RSWDT_CR_WDRSTT_Pos) /**< (RSWDT_CR) Watchdog Restart Mask */ +#define RSWDT_CR_WDRSTT(value) (RSWDT_CR_WDRSTT_Msk & ((value) << RSWDT_CR_WDRSTT_Pos)) +#define RSWDT_CR_KEY_Pos _U_(24) /**< (RSWDT_CR) Password Position */ +#define RSWDT_CR_KEY_Msk (_U_(0xFF) << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Password Mask */ +#define RSWDT_CR_KEY(value) (RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)) +#define RSWDT_CR_KEY_PASSWD_Val _U_(0xC4) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +#define RSWDT_CR_KEY_PASSWD (RSWDT_CR_KEY_PASSWD_Val << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSWDT_CR_Msk _U_(0xFF000001) /**< (RSWDT_CR) Register Mask */ + + +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos _U_(0) /**< (RSWDT_MR) Watchdog Counter Value Position */ +#define RSWDT_MR_WDV_Msk (_U_(0xFFF) << RSWDT_MR_WDV_Pos) /**< (RSWDT_MR) Watchdog Counter Value Mask */ +#define RSWDT_MR_WDV(value) (RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)) +#define RSWDT_MR_WDFIEN_Pos _U_(12) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Position */ +#define RSWDT_MR_WDFIEN_Msk (_U_(0x1) << RSWDT_MR_WDFIEN_Pos) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define RSWDT_MR_WDFIEN(value) (RSWDT_MR_WDFIEN_Msk & ((value) << RSWDT_MR_WDFIEN_Pos)) +#define RSWDT_MR_WDRSTEN_Pos _U_(13) /**< (RSWDT_MR) Watchdog Reset Enable Position */ +#define RSWDT_MR_WDRSTEN_Msk (_U_(0x1) << RSWDT_MR_WDRSTEN_Pos) /**< (RSWDT_MR) Watchdog Reset Enable Mask */ +#define RSWDT_MR_WDRSTEN(value) (RSWDT_MR_WDRSTEN_Msk & ((value) << RSWDT_MR_WDRSTEN_Pos)) +#define RSWDT_MR_WDDIS_Pos _U_(15) /**< (RSWDT_MR) Watchdog Disable Position */ +#define RSWDT_MR_WDDIS_Msk (_U_(0x1) << RSWDT_MR_WDDIS_Pos) /**< (RSWDT_MR) Watchdog Disable Mask */ +#define RSWDT_MR_WDDIS(value) (RSWDT_MR_WDDIS_Msk & ((value) << RSWDT_MR_WDDIS_Pos)) +#define RSWDT_MR_ALLONES_Pos _U_(16) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Position */ +#define RSWDT_MR_ALLONES_Msk (_U_(0xFFF) << RSWDT_MR_ALLONES_Pos) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Mask */ +#define RSWDT_MR_ALLONES(value) (RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)) +#define RSWDT_MR_WDDBGHLT_Pos _U_(28) /**< (RSWDT_MR) Watchdog Debug Halt Position */ +#define RSWDT_MR_WDDBGHLT_Msk (_U_(0x1) << RSWDT_MR_WDDBGHLT_Pos) /**< (RSWDT_MR) Watchdog Debug Halt Mask */ +#define RSWDT_MR_WDDBGHLT(value) (RSWDT_MR_WDDBGHLT_Msk & ((value) << RSWDT_MR_WDDBGHLT_Pos)) +#define RSWDT_MR_WDIDLEHLT_Pos _U_(29) /**< (RSWDT_MR) Watchdog Idle Halt Position */ +#define RSWDT_MR_WDIDLEHLT_Msk (_U_(0x1) << RSWDT_MR_WDIDLEHLT_Pos) /**< (RSWDT_MR) Watchdog Idle Halt Mask */ +#define RSWDT_MR_WDIDLEHLT(value) (RSWDT_MR_WDIDLEHLT_Msk & ((value) << RSWDT_MR_WDIDLEHLT_Pos)) +#define RSWDT_MR_Msk _U_(0x3FFFBFFF) /**< (RSWDT_MR) Register Mask */ + + +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) ( R/ 32) Status Register -------- */ +#define RSWDT_SR_WDUNF_Pos _U_(0) /**< (RSWDT_SR) Watchdog Underflow Position */ +#define RSWDT_SR_WDUNF_Msk (_U_(0x1) << RSWDT_SR_WDUNF_Pos) /**< (RSWDT_SR) Watchdog Underflow Mask */ +#define RSWDT_SR_WDUNF(value) (RSWDT_SR_WDUNF_Msk & ((value) << RSWDT_SR_WDUNF_Pos)) +#define RSWDT_SR_Msk _U_(0x00000001) /**< (RSWDT_SR) Register Mask */ + + +/** \brief RSWDT register offsets definitions */ +#define RSWDT_CR_REG_OFST (0x00) /**< (RSWDT_CR) Control Register Offset */ +#define RSWDT_MR_REG_OFST (0x04) /**< (RSWDT_MR) Mode Register Offset */ +#define RSWDT_SR_REG_OFST (0x08) /**< (RSWDT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RSWDT register API structure */ +typedef struct +{ + __O uint32_t RSWDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t RSWDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t RSWDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} rswdt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RSWDT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/rtc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/rtc.h new file mode 100644 index 00000000..0ea04c72 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/rtc.h @@ -0,0 +1,408 @@ +/** + * \brief Component description for RTC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_RTC_COMPONENT_H_ +#define _SAME70_RTC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RTC */ +/* ************************************************************************** */ + +/* -------- RTC_CR : (RTC Offset: 0x00) (R/W 32) Control Register -------- */ +#define RTC_CR_UPDTIM_Pos _U_(0) /**< (RTC_CR) Update Request Time Register Position */ +#define RTC_CR_UPDTIM_Msk (_U_(0x1) << RTC_CR_UPDTIM_Pos) /**< (RTC_CR) Update Request Time Register Mask */ +#define RTC_CR_UPDTIM(value) (RTC_CR_UPDTIM_Msk & ((value) << RTC_CR_UPDTIM_Pos)) +#define RTC_CR_UPDCAL_Pos _U_(1) /**< (RTC_CR) Update Request Calendar Register Position */ +#define RTC_CR_UPDCAL_Msk (_U_(0x1) << RTC_CR_UPDCAL_Pos) /**< (RTC_CR) Update Request Calendar Register Mask */ +#define RTC_CR_UPDCAL(value) (RTC_CR_UPDCAL_Msk & ((value) << RTC_CR_UPDCAL_Pos)) +#define RTC_CR_TIMEVSEL_Pos _U_(8) /**< (RTC_CR) Time Event Selection Position */ +#define RTC_CR_TIMEVSEL_Msk (_U_(0x3) << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Time Event Selection Mask */ +#define RTC_CR_TIMEVSEL(value) (RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)) +#define RTC_CR_TIMEVSEL_MINUTE_Val _U_(0x0) /**< (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR_Val _U_(0x1) /**< (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT_Val _U_(0x2) /**< (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON_Val _U_(0x3) /**< (RTC_CR) Every day at noon */ +#define RTC_CR_TIMEVSEL_MINUTE (RTC_CR_TIMEVSEL_MINUTE_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Minute change Position */ +#define RTC_CR_TIMEVSEL_HOUR (RTC_CR_TIMEVSEL_HOUR_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Hour change Position */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (RTC_CR_TIMEVSEL_MIDNIGHT_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at midnight Position */ +#define RTC_CR_TIMEVSEL_NOON (RTC_CR_TIMEVSEL_NOON_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at noon Position */ +#define RTC_CR_CALEVSEL_Pos _U_(16) /**< (RTC_CR) Calendar Event Selection Position */ +#define RTC_CR_CALEVSEL_Msk (_U_(0x3) << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Calendar Event Selection Mask */ +#define RTC_CR_CALEVSEL(value) (RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)) +#define RTC_CR_CALEVSEL_WEEK_Val _U_(0x0) /**< (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH_Val _U_(0x1) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR_Val _U_(0x2) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) */ +#define RTC_CR_CALEVSEL_WEEK (RTC_CR_CALEVSEL_WEEK_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Week change (every Monday at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_MONTH (RTC_CR_CALEVSEL_MONTH_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_YEAR (RTC_CR_CALEVSEL_YEAR_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) Position */ +#define RTC_CR_Msk _U_(0x00030303) /**< (RTC_CR) Register Mask */ + + +/* -------- RTC_MR : (RTC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define RTC_MR_HRMOD_Pos _U_(0) /**< (RTC_MR) 12-/24-hour Mode Position */ +#define RTC_MR_HRMOD_Msk (_U_(0x1) << RTC_MR_HRMOD_Pos) /**< (RTC_MR) 12-/24-hour Mode Mask */ +#define RTC_MR_HRMOD(value) (RTC_MR_HRMOD_Msk & ((value) << RTC_MR_HRMOD_Pos)) +#define RTC_MR_PERSIAN_Pos _U_(1) /**< (RTC_MR) PERSIAN Calendar Position */ +#define RTC_MR_PERSIAN_Msk (_U_(0x1) << RTC_MR_PERSIAN_Pos) /**< (RTC_MR) PERSIAN Calendar Mask */ +#define RTC_MR_PERSIAN(value) (RTC_MR_PERSIAN_Msk & ((value) << RTC_MR_PERSIAN_Pos)) +#define RTC_MR_NEGPPM_Pos _U_(4) /**< (RTC_MR) NEGative PPM Correction Position */ +#define RTC_MR_NEGPPM_Msk (_U_(0x1) << RTC_MR_NEGPPM_Pos) /**< (RTC_MR) NEGative PPM Correction Mask */ +#define RTC_MR_NEGPPM(value) (RTC_MR_NEGPPM_Msk & ((value) << RTC_MR_NEGPPM_Pos)) +#define RTC_MR_CORRECTION_Pos _U_(8) /**< (RTC_MR) Slow Clock Correction Position */ +#define RTC_MR_CORRECTION_Msk (_U_(0x7F) << RTC_MR_CORRECTION_Pos) /**< (RTC_MR) Slow Clock Correction Mask */ +#define RTC_MR_CORRECTION(value) (RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)) +#define RTC_MR_HIGHPPM_Pos _U_(15) /**< (RTC_MR) HIGH PPM Correction Position */ +#define RTC_MR_HIGHPPM_Msk (_U_(0x1) << RTC_MR_HIGHPPM_Pos) /**< (RTC_MR) HIGH PPM Correction Mask */ +#define RTC_MR_HIGHPPM(value) (RTC_MR_HIGHPPM_Msk & ((value) << RTC_MR_HIGHPPM_Pos)) +#define RTC_MR_OUT0_Pos _U_(16) /**< (RTC_MR) RTCOUT0 OutputSource Selection Position */ +#define RTC_MR_OUT0_Msk (_U_(0x7) << RTC_MR_OUT0_Pos) /**< (RTC_MR) RTCOUT0 OutputSource Selection Mask */ +#define RTC_MR_OUT0(value) (RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)) +#define RTC_MR_OUT0_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT0_NO_WAVE (RTC_MR_OUT0_NO_WAVE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT0_FREQ1HZ (RTC_MR_OUT0_FREQ1HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ32HZ (RTC_MR_OUT0_FREQ32HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ64HZ (RTC_MR_OUT0_FREQ64HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ512HZ (RTC_MR_OUT0_FREQ512HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT0_ALARM_TOGGLE (RTC_MR_OUT0_ALARM_TOGGLE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT0_ALARM_FLAG (RTC_MR_OUT0_ALARM_FLAG_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT0_PROG_PULSE (RTC_MR_OUT0_PROG_PULSE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_OUT1_Pos _U_(20) /**< (RTC_MR) RTCOUT1 Output Source Selection Position */ +#define RTC_MR_OUT1_Msk (_U_(0x7) << RTC_MR_OUT1_Pos) /**< (RTC_MR) RTCOUT1 Output Source Selection Mask */ +#define RTC_MR_OUT1(value) (RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)) +#define RTC_MR_OUT1_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_NO_WAVE (RTC_MR_OUT1_NO_WAVE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT1_FREQ1HZ (RTC_MR_OUT1_FREQ1HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ32HZ (RTC_MR_OUT1_FREQ32HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ64HZ (RTC_MR_OUT1_FREQ64HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ512HZ (RTC_MR_OUT1_FREQ512HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT1_ALARM_TOGGLE (RTC_MR_OUT1_ALARM_TOGGLE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT1_ALARM_FLAG (RTC_MR_OUT1_ALARM_FLAG_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT1_PROG_PULSE (RTC_MR_OUT1_PROG_PULSE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_THIGH_Pos _U_(24) /**< (RTC_MR) High Duration of the Output Pulse Position */ +#define RTC_MR_THIGH_Msk (_U_(0x7) << RTC_MR_THIGH_Pos) /**< (RTC_MR) High Duration of the Output Pulse Mask */ +#define RTC_MR_THIGH(value) (RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)) +#define RTC_MR_THIGH_H_31MS_Val _U_(0x0) /**< (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS_Val _U_(0x1) /**< (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS_Val _U_(0x2) /**< (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US_Val _U_(0x3) /**< (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US_Val _U_(0x4) /**< (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US_Val _U_(0x5) /**< (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US_Val _U_(0x6) /**< (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US_Val _U_(0x7) /**< (RTC_MR) 15.2 us */ +#define RTC_MR_THIGH_H_31MS (RTC_MR_THIGH_H_31MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 31.2 ms Position */ +#define RTC_MR_THIGH_H_16MS (RTC_MR_THIGH_H_16MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.6 ms Position */ +#define RTC_MR_THIGH_H_4MS (RTC_MR_THIGH_H_4MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 3.91 ms Position */ +#define RTC_MR_THIGH_H_976US (RTC_MR_THIGH_H_976US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 976 us Position */ +#define RTC_MR_THIGH_H_488US (RTC_MR_THIGH_H_488US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 488 us Position */ +#define RTC_MR_THIGH_H_122US (RTC_MR_THIGH_H_122US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 122 us Position */ +#define RTC_MR_THIGH_H_30US (RTC_MR_THIGH_H_30US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 30.5 us Position */ +#define RTC_MR_THIGH_H_15US (RTC_MR_THIGH_H_15US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.2 us Position */ +#define RTC_MR_TPERIOD_Pos _U_(28) /**< (RTC_MR) Period of the Output Pulse Position */ +#define RTC_MR_TPERIOD_Msk (_U_(0x3) << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) Period of the Output Pulse Mask */ +#define RTC_MR_TPERIOD(value) (RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)) +#define RTC_MR_TPERIOD_P_1S_Val _U_(0x0) /**< (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS_Val _U_(0x1) /**< (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS_Val _U_(0x2) /**< (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS_Val _U_(0x3) /**< (RTC_MR) 125 ms */ +#define RTC_MR_TPERIOD_P_1S (RTC_MR_TPERIOD_P_1S_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 1 second Position */ +#define RTC_MR_TPERIOD_P_500MS (RTC_MR_TPERIOD_P_500MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 500 ms Position */ +#define RTC_MR_TPERIOD_P_250MS (RTC_MR_TPERIOD_P_250MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 250 ms Position */ +#define RTC_MR_TPERIOD_P_125MS (RTC_MR_TPERIOD_P_125MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 125 ms Position */ +#define RTC_MR_Msk _U_(0x3777FF13) /**< (RTC_MR) Register Mask */ + + +/* -------- RTC_TIMR : (RTC Offset: 0x08) (R/W 32) Time Register -------- */ +#define RTC_TIMR_SEC_Pos _U_(0) /**< (RTC_TIMR) Current Second Position */ +#define RTC_TIMR_SEC_Msk (_U_(0x7F) << RTC_TIMR_SEC_Pos) /**< (RTC_TIMR) Current Second Mask */ +#define RTC_TIMR_SEC(value) (RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)) +#define RTC_TIMR_MIN_Pos _U_(8) /**< (RTC_TIMR) Current Minute Position */ +#define RTC_TIMR_MIN_Msk (_U_(0x7F) << RTC_TIMR_MIN_Pos) /**< (RTC_TIMR) Current Minute Mask */ +#define RTC_TIMR_MIN(value) (RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)) +#define RTC_TIMR_HOUR_Pos _U_(16) /**< (RTC_TIMR) Current Hour Position */ +#define RTC_TIMR_HOUR_Msk (_U_(0x3F) << RTC_TIMR_HOUR_Pos) /**< (RTC_TIMR) Current Hour Mask */ +#define RTC_TIMR_HOUR(value) (RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)) +#define RTC_TIMR_AMPM_Pos _U_(22) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Position */ +#define RTC_TIMR_AMPM_Msk (_U_(0x1) << RTC_TIMR_AMPM_Pos) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Mask */ +#define RTC_TIMR_AMPM(value) (RTC_TIMR_AMPM_Msk & ((value) << RTC_TIMR_AMPM_Pos)) +#define RTC_TIMR_Msk _U_(0x007F7F7F) /**< (RTC_TIMR) Register Mask */ + + +/* -------- RTC_CALR : (RTC Offset: 0x0C) (R/W 32) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos _U_(0) /**< (RTC_CALR) Current Century Position */ +#define RTC_CALR_CENT_Msk (_U_(0x7F) << RTC_CALR_CENT_Pos) /**< (RTC_CALR) Current Century Mask */ +#define RTC_CALR_CENT(value) (RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)) +#define RTC_CALR_YEAR_Pos _U_(8) /**< (RTC_CALR) Current Year Position */ +#define RTC_CALR_YEAR_Msk (_U_(0xFF) << RTC_CALR_YEAR_Pos) /**< (RTC_CALR) Current Year Mask */ +#define RTC_CALR_YEAR(value) (RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)) +#define RTC_CALR_MONTH_Pos _U_(16) /**< (RTC_CALR) Current Month Position */ +#define RTC_CALR_MONTH_Msk (_U_(0x1F) << RTC_CALR_MONTH_Pos) /**< (RTC_CALR) Current Month Mask */ +#define RTC_CALR_MONTH(value) (RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)) +#define RTC_CALR_DAY_Pos _U_(21) /**< (RTC_CALR) Current Day in Current Week Position */ +#define RTC_CALR_DAY_Msk (_U_(0x7) << RTC_CALR_DAY_Pos) /**< (RTC_CALR) Current Day in Current Week Mask */ +#define RTC_CALR_DAY(value) (RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)) +#define RTC_CALR_DATE_Pos _U_(24) /**< (RTC_CALR) Current Day in Current Month Position */ +#define RTC_CALR_DATE_Msk (_U_(0x3F) << RTC_CALR_DATE_Pos) /**< (RTC_CALR) Current Day in Current Month Mask */ +#define RTC_CALR_DATE(value) (RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)) +#define RTC_CALR_Msk _U_(0x3FFFFF7F) /**< (RTC_CALR) Register Mask */ + + +/* -------- RTC_TIMALR : (RTC Offset: 0x10) (R/W 32) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos _U_(0) /**< (RTC_TIMALR) Second Alarm Position */ +#define RTC_TIMALR_SEC_Msk (_U_(0x7F) << RTC_TIMALR_SEC_Pos) /**< (RTC_TIMALR) Second Alarm Mask */ +#define RTC_TIMALR_SEC(value) (RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)) +#define RTC_TIMALR_SECEN_Pos _U_(7) /**< (RTC_TIMALR) Second Alarm Enable Position */ +#define RTC_TIMALR_SECEN_Msk (_U_(0x1) << RTC_TIMALR_SECEN_Pos) /**< (RTC_TIMALR) Second Alarm Enable Mask */ +#define RTC_TIMALR_SECEN(value) (RTC_TIMALR_SECEN_Msk & ((value) << RTC_TIMALR_SECEN_Pos)) +#define RTC_TIMALR_MIN_Pos _U_(8) /**< (RTC_TIMALR) Minute Alarm Position */ +#define RTC_TIMALR_MIN_Msk (_U_(0x7F) << RTC_TIMALR_MIN_Pos) /**< (RTC_TIMALR) Minute Alarm Mask */ +#define RTC_TIMALR_MIN(value) (RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)) +#define RTC_TIMALR_MINEN_Pos _U_(15) /**< (RTC_TIMALR) Minute Alarm Enable Position */ +#define RTC_TIMALR_MINEN_Msk (_U_(0x1) << RTC_TIMALR_MINEN_Pos) /**< (RTC_TIMALR) Minute Alarm Enable Mask */ +#define RTC_TIMALR_MINEN(value) (RTC_TIMALR_MINEN_Msk & ((value) << RTC_TIMALR_MINEN_Pos)) +#define RTC_TIMALR_HOUR_Pos _U_(16) /**< (RTC_TIMALR) Hour Alarm Position */ +#define RTC_TIMALR_HOUR_Msk (_U_(0x3F) << RTC_TIMALR_HOUR_Pos) /**< (RTC_TIMALR) Hour Alarm Mask */ +#define RTC_TIMALR_HOUR(value) (RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)) +#define RTC_TIMALR_AMPM_Pos _U_(22) /**< (RTC_TIMALR) AM/PM Indicator Position */ +#define RTC_TIMALR_AMPM_Msk (_U_(0x1) << RTC_TIMALR_AMPM_Pos) /**< (RTC_TIMALR) AM/PM Indicator Mask */ +#define RTC_TIMALR_AMPM(value) (RTC_TIMALR_AMPM_Msk & ((value) << RTC_TIMALR_AMPM_Pos)) +#define RTC_TIMALR_HOUREN_Pos _U_(23) /**< (RTC_TIMALR) Hour Alarm Enable Position */ +#define RTC_TIMALR_HOUREN_Msk (_U_(0x1) << RTC_TIMALR_HOUREN_Pos) /**< (RTC_TIMALR) Hour Alarm Enable Mask */ +#define RTC_TIMALR_HOUREN(value) (RTC_TIMALR_HOUREN_Msk & ((value) << RTC_TIMALR_HOUREN_Pos)) +#define RTC_TIMALR_Msk _U_(0x00FFFFFF) /**< (RTC_TIMALR) Register Mask */ + + +/* -------- RTC_CALALR : (RTC Offset: 0x14) (R/W 32) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos _U_(16) /**< (RTC_CALALR) Month Alarm Position */ +#define RTC_CALALR_MONTH_Msk (_U_(0x1F) << RTC_CALALR_MONTH_Pos) /**< (RTC_CALALR) Month Alarm Mask */ +#define RTC_CALALR_MONTH(value) (RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)) +#define RTC_CALALR_MTHEN_Pos _U_(23) /**< (RTC_CALALR) Month Alarm Enable Position */ +#define RTC_CALALR_MTHEN_Msk (_U_(0x1) << RTC_CALALR_MTHEN_Pos) /**< (RTC_CALALR) Month Alarm Enable Mask */ +#define RTC_CALALR_MTHEN(value) (RTC_CALALR_MTHEN_Msk & ((value) << RTC_CALALR_MTHEN_Pos)) +#define RTC_CALALR_DATE_Pos _U_(24) /**< (RTC_CALALR) Date Alarm Position */ +#define RTC_CALALR_DATE_Msk (_U_(0x3F) << RTC_CALALR_DATE_Pos) /**< (RTC_CALALR) Date Alarm Mask */ +#define RTC_CALALR_DATE(value) (RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)) +#define RTC_CALALR_DATEEN_Pos _U_(31) /**< (RTC_CALALR) Date Alarm Enable Position */ +#define RTC_CALALR_DATEEN_Msk (_U_(0x1) << RTC_CALALR_DATEEN_Pos) /**< (RTC_CALALR) Date Alarm Enable Mask */ +#define RTC_CALALR_DATEEN(value) (RTC_CALALR_DATEEN_Msk & ((value) << RTC_CALALR_DATEEN_Pos)) +#define RTC_CALALR_Msk _U_(0xBF9F0000) /**< (RTC_CALALR) Register Mask */ + + +/* -------- RTC_SR : (RTC Offset: 0x18) ( R/ 32) Status Register -------- */ +#define RTC_SR_ACKUPD_Pos _U_(0) /**< (RTC_SR) Acknowledge for Update Position */ +#define RTC_SR_ACKUPD_Msk (_U_(0x1) << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Acknowledge for Update Mask */ +#define RTC_SR_ACKUPD(value) (RTC_SR_ACKUPD_Msk & ((value) << RTC_SR_ACKUPD_Pos)) +#define RTC_SR_ACKUPD_FREERUN_Val _U_(0x0) /**< (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE_Val _U_(0x1) /**< (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ACKUPD_FREERUN (RTC_SR_ACKUPD_FREERUN_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers cannot be updated. Position */ +#define RTC_SR_ACKUPD_UPDATE (RTC_SR_ACKUPD_UPDATE_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers can be updated. Position */ +#define RTC_SR_ALARM_Pos _U_(1) /**< (RTC_SR) Alarm Flag Position */ +#define RTC_SR_ALARM_Msk (_U_(0x1) << RTC_SR_ALARM_Pos) /**< (RTC_SR) Alarm Flag Mask */ +#define RTC_SR_ALARM(value) (RTC_SR_ALARM_Msk & ((value) << RTC_SR_ALARM_Pos)) +#define RTC_SR_ALARM_NO_ALARMEVENT_Val _U_(0x0) /**< (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT_Val _U_(0x1) /**< (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_ALARM_NO_ALARMEVENT (RTC_SR_ALARM_NO_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) No alarm matching condition occurred. Position */ +#define RTC_SR_ALARM_ALARMEVENT (RTC_SR_ALARM_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) An alarm matching condition has occurred. Position */ +#define RTC_SR_SEC_Pos _U_(2) /**< (RTC_SR) Second Event Position */ +#define RTC_SR_SEC_Msk (_U_(0x1) << RTC_SR_SEC_Pos) /**< (RTC_SR) Second Event Mask */ +#define RTC_SR_SEC(value) (RTC_SR_SEC_Msk & ((value) << RTC_SR_SEC_Pos)) +#define RTC_SR_SEC_NO_SECEVENT_Val _U_(0x0) /**< (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT_Val _U_(0x1) /**< (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_SEC_NO_SECEVENT (RTC_SR_SEC_NO_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) No second event has occurred since the last clear. Position */ +#define RTC_SR_SEC_SECEVENT (RTC_SR_SEC_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) At least one second event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_Pos _U_(3) /**< (RTC_SR) Time Event Position */ +#define RTC_SR_TIMEV_Msk (_U_(0x1) << RTC_SR_TIMEV_Pos) /**< (RTC_SR) Time Event Mask */ +#define RTC_SR_TIMEV(value) (RTC_SR_TIMEV_Msk & ((value) << RTC_SR_TIMEV_Pos)) +#define RTC_SR_TIMEV_NO_TIMEVENT_Val _U_(0x0) /**< (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT_Val _U_(0x1) /**< (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_NO_TIMEVENT (RTC_SR_TIMEV_NO_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) No time event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_TIMEVENT (RTC_SR_TIMEV_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) At least one time event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_Pos _U_(4) /**< (RTC_SR) Calendar Event Position */ +#define RTC_SR_CALEV_Msk (_U_(0x1) << RTC_SR_CALEV_Pos) /**< (RTC_SR) Calendar Event Mask */ +#define RTC_SR_CALEV(value) (RTC_SR_CALEV_Msk & ((value) << RTC_SR_CALEV_Pos)) +#define RTC_SR_CALEV_NO_CALEVENT_Val _U_(0x0) /**< (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT_Val _U_(0x1) /**< (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_NO_CALEVENT (RTC_SR_CALEV_NO_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) No calendar event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_CALEVENT (RTC_SR_CALEV_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) At least one calendar event has occurred since the last clear. Position */ +#define RTC_SR_TDERR_Pos _U_(5) /**< (RTC_SR) Time and/or Date Free Running Error Position */ +#define RTC_SR_TDERR_Msk (_U_(0x1) << RTC_SR_TDERR_Pos) /**< (RTC_SR) Time and/or Date Free Running Error Mask */ +#define RTC_SR_TDERR(value) (RTC_SR_TDERR_Msk & ((value) << RTC_SR_TDERR_Pos)) +#define RTC_SR_TDERR_CORRECT_Val _U_(0x0) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE_Val _U_(0x1) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +#define RTC_SR_TDERR_CORRECT (RTC_SR_TDERR_CORRECT_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). Position */ +#define RTC_SR_TDERR_ERR_TIMEDATE (RTC_SR_TDERR_ERR_TIMEDATE_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. Position */ +#define RTC_SR_Msk _U_(0x0000003F) /**< (RTC_SR) Register Mask */ + + +/* -------- RTC_SCCR : (RTC Offset: 0x1C) ( /W 32) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR_Pos _U_(0) /**< (RTC_SCCR) Acknowledge Clear Position */ +#define RTC_SCCR_ACKCLR_Msk (_U_(0x1) << RTC_SCCR_ACKCLR_Pos) /**< (RTC_SCCR) Acknowledge Clear Mask */ +#define RTC_SCCR_ACKCLR(value) (RTC_SCCR_ACKCLR_Msk & ((value) << RTC_SCCR_ACKCLR_Pos)) +#define RTC_SCCR_ALRCLR_Pos _U_(1) /**< (RTC_SCCR) Alarm Clear Position */ +#define RTC_SCCR_ALRCLR_Msk (_U_(0x1) << RTC_SCCR_ALRCLR_Pos) /**< (RTC_SCCR) Alarm Clear Mask */ +#define RTC_SCCR_ALRCLR(value) (RTC_SCCR_ALRCLR_Msk & ((value) << RTC_SCCR_ALRCLR_Pos)) +#define RTC_SCCR_SECCLR_Pos _U_(2) /**< (RTC_SCCR) Second Clear Position */ +#define RTC_SCCR_SECCLR_Msk (_U_(0x1) << RTC_SCCR_SECCLR_Pos) /**< (RTC_SCCR) Second Clear Mask */ +#define RTC_SCCR_SECCLR(value) (RTC_SCCR_SECCLR_Msk & ((value) << RTC_SCCR_SECCLR_Pos)) +#define RTC_SCCR_TIMCLR_Pos _U_(3) /**< (RTC_SCCR) Time Clear Position */ +#define RTC_SCCR_TIMCLR_Msk (_U_(0x1) << RTC_SCCR_TIMCLR_Pos) /**< (RTC_SCCR) Time Clear Mask */ +#define RTC_SCCR_TIMCLR(value) (RTC_SCCR_TIMCLR_Msk & ((value) << RTC_SCCR_TIMCLR_Pos)) +#define RTC_SCCR_CALCLR_Pos _U_(4) /**< (RTC_SCCR) Calendar Clear Position */ +#define RTC_SCCR_CALCLR_Msk (_U_(0x1) << RTC_SCCR_CALCLR_Pos) /**< (RTC_SCCR) Calendar Clear Mask */ +#define RTC_SCCR_CALCLR(value) (RTC_SCCR_CALCLR_Msk & ((value) << RTC_SCCR_CALCLR_Pos)) +#define RTC_SCCR_TDERRCLR_Pos _U_(5) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Position */ +#define RTC_SCCR_TDERRCLR_Msk (_U_(0x1) << RTC_SCCR_TDERRCLR_Pos) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Mask */ +#define RTC_SCCR_TDERRCLR(value) (RTC_SCCR_TDERRCLR_Msk & ((value) << RTC_SCCR_TDERRCLR_Pos)) +#define RTC_SCCR_Msk _U_(0x0000003F) /**< (RTC_SCCR) Register Mask */ + + +/* -------- RTC_IER : (RTC Offset: 0x20) ( /W 32) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN_Pos _U_(0) /**< (RTC_IER) Acknowledge Update Interrupt Enable Position */ +#define RTC_IER_ACKEN_Msk (_U_(0x1) << RTC_IER_ACKEN_Pos) /**< (RTC_IER) Acknowledge Update Interrupt Enable Mask */ +#define RTC_IER_ACKEN(value) (RTC_IER_ACKEN_Msk & ((value) << RTC_IER_ACKEN_Pos)) +#define RTC_IER_ALREN_Pos _U_(1) /**< (RTC_IER) Alarm Interrupt Enable Position */ +#define RTC_IER_ALREN_Msk (_U_(0x1) << RTC_IER_ALREN_Pos) /**< (RTC_IER) Alarm Interrupt Enable Mask */ +#define RTC_IER_ALREN(value) (RTC_IER_ALREN_Msk & ((value) << RTC_IER_ALREN_Pos)) +#define RTC_IER_SECEN_Pos _U_(2) /**< (RTC_IER) Second Event Interrupt Enable Position */ +#define RTC_IER_SECEN_Msk (_U_(0x1) << RTC_IER_SECEN_Pos) /**< (RTC_IER) Second Event Interrupt Enable Mask */ +#define RTC_IER_SECEN(value) (RTC_IER_SECEN_Msk & ((value) << RTC_IER_SECEN_Pos)) +#define RTC_IER_TIMEN_Pos _U_(3) /**< (RTC_IER) Time Event Interrupt Enable Position */ +#define RTC_IER_TIMEN_Msk (_U_(0x1) << RTC_IER_TIMEN_Pos) /**< (RTC_IER) Time Event Interrupt Enable Mask */ +#define RTC_IER_TIMEN(value) (RTC_IER_TIMEN_Msk & ((value) << RTC_IER_TIMEN_Pos)) +#define RTC_IER_CALEN_Pos _U_(4) /**< (RTC_IER) Calendar Event Interrupt Enable Position */ +#define RTC_IER_CALEN_Msk (_U_(0x1) << RTC_IER_CALEN_Pos) /**< (RTC_IER) Calendar Event Interrupt Enable Mask */ +#define RTC_IER_CALEN(value) (RTC_IER_CALEN_Msk & ((value) << RTC_IER_CALEN_Pos)) +#define RTC_IER_TDERREN_Pos _U_(5) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Position */ +#define RTC_IER_TDERREN_Msk (_U_(0x1) << RTC_IER_TDERREN_Pos) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Mask */ +#define RTC_IER_TDERREN(value) (RTC_IER_TDERREN_Msk & ((value) << RTC_IER_TDERREN_Pos)) +#define RTC_IER_Msk _U_(0x0000003F) /**< (RTC_IER) Register Mask */ + + +/* -------- RTC_IDR : (RTC Offset: 0x24) ( /W 32) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS_Pos _U_(0) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Position */ +#define RTC_IDR_ACKDIS_Msk (_U_(0x1) << RTC_IDR_ACKDIS_Pos) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Mask */ +#define RTC_IDR_ACKDIS(value) (RTC_IDR_ACKDIS_Msk & ((value) << RTC_IDR_ACKDIS_Pos)) +#define RTC_IDR_ALRDIS_Pos _U_(1) /**< (RTC_IDR) Alarm Interrupt Disable Position */ +#define RTC_IDR_ALRDIS_Msk (_U_(0x1) << RTC_IDR_ALRDIS_Pos) /**< (RTC_IDR) Alarm Interrupt Disable Mask */ +#define RTC_IDR_ALRDIS(value) (RTC_IDR_ALRDIS_Msk & ((value) << RTC_IDR_ALRDIS_Pos)) +#define RTC_IDR_SECDIS_Pos _U_(2) /**< (RTC_IDR) Second Event Interrupt Disable Position */ +#define RTC_IDR_SECDIS_Msk (_U_(0x1) << RTC_IDR_SECDIS_Pos) /**< (RTC_IDR) Second Event Interrupt Disable Mask */ +#define RTC_IDR_SECDIS(value) (RTC_IDR_SECDIS_Msk & ((value) << RTC_IDR_SECDIS_Pos)) +#define RTC_IDR_TIMDIS_Pos _U_(3) /**< (RTC_IDR) Time Event Interrupt Disable Position */ +#define RTC_IDR_TIMDIS_Msk (_U_(0x1) << RTC_IDR_TIMDIS_Pos) /**< (RTC_IDR) Time Event Interrupt Disable Mask */ +#define RTC_IDR_TIMDIS(value) (RTC_IDR_TIMDIS_Msk & ((value) << RTC_IDR_TIMDIS_Pos)) +#define RTC_IDR_CALDIS_Pos _U_(4) /**< (RTC_IDR) Calendar Event Interrupt Disable Position */ +#define RTC_IDR_CALDIS_Msk (_U_(0x1) << RTC_IDR_CALDIS_Pos) /**< (RTC_IDR) Calendar Event Interrupt Disable Mask */ +#define RTC_IDR_CALDIS(value) (RTC_IDR_CALDIS_Msk & ((value) << RTC_IDR_CALDIS_Pos)) +#define RTC_IDR_TDERRDIS_Pos _U_(5) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Position */ +#define RTC_IDR_TDERRDIS_Msk (_U_(0x1) << RTC_IDR_TDERRDIS_Pos) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Mask */ +#define RTC_IDR_TDERRDIS(value) (RTC_IDR_TDERRDIS_Msk & ((value) << RTC_IDR_TDERRDIS_Pos)) +#define RTC_IDR_Msk _U_(0x0000003F) /**< (RTC_IDR) Register Mask */ + + +/* -------- RTC_IMR : (RTC Offset: 0x28) ( R/ 32) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK_Pos _U_(0) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Position */ +#define RTC_IMR_ACK_Msk (_U_(0x1) << RTC_IMR_ACK_Pos) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Mask */ +#define RTC_IMR_ACK(value) (RTC_IMR_ACK_Msk & ((value) << RTC_IMR_ACK_Pos)) +#define RTC_IMR_ALR_Pos _U_(1) /**< (RTC_IMR) Alarm Interrupt Mask Position */ +#define RTC_IMR_ALR_Msk (_U_(0x1) << RTC_IMR_ALR_Pos) /**< (RTC_IMR) Alarm Interrupt Mask Mask */ +#define RTC_IMR_ALR(value) (RTC_IMR_ALR_Msk & ((value) << RTC_IMR_ALR_Pos)) +#define RTC_IMR_SEC_Pos _U_(2) /**< (RTC_IMR) Second Event Interrupt Mask Position */ +#define RTC_IMR_SEC_Msk (_U_(0x1) << RTC_IMR_SEC_Pos) /**< (RTC_IMR) Second Event Interrupt Mask Mask */ +#define RTC_IMR_SEC(value) (RTC_IMR_SEC_Msk & ((value) << RTC_IMR_SEC_Pos)) +#define RTC_IMR_TIM_Pos _U_(3) /**< (RTC_IMR) Time Event Interrupt Mask Position */ +#define RTC_IMR_TIM_Msk (_U_(0x1) << RTC_IMR_TIM_Pos) /**< (RTC_IMR) Time Event Interrupt Mask Mask */ +#define RTC_IMR_TIM(value) (RTC_IMR_TIM_Msk & ((value) << RTC_IMR_TIM_Pos)) +#define RTC_IMR_CAL_Pos _U_(4) /**< (RTC_IMR) Calendar Event Interrupt Mask Position */ +#define RTC_IMR_CAL_Msk (_U_(0x1) << RTC_IMR_CAL_Pos) /**< (RTC_IMR) Calendar Event Interrupt Mask Mask */ +#define RTC_IMR_CAL(value) (RTC_IMR_CAL_Msk & ((value) << RTC_IMR_CAL_Pos)) +#define RTC_IMR_TDERR_Pos _U_(5) /**< (RTC_IMR) Time and/or Date Error Mask Position */ +#define RTC_IMR_TDERR_Msk (_U_(0x1) << RTC_IMR_TDERR_Pos) /**< (RTC_IMR) Time and/or Date Error Mask Mask */ +#define RTC_IMR_TDERR(value) (RTC_IMR_TDERR_Msk & ((value) << RTC_IMR_TDERR_Pos)) +#define RTC_IMR_Msk _U_(0x0000003F) /**< (RTC_IMR) Register Mask */ + + +/* -------- RTC_VER : (RTC Offset: 0x2C) ( R/ 32) Valid Entry Register -------- */ +#define RTC_VER_NVTIM_Pos _U_(0) /**< (RTC_VER) Non-valid Time Position */ +#define RTC_VER_NVTIM_Msk (_U_(0x1) << RTC_VER_NVTIM_Pos) /**< (RTC_VER) Non-valid Time Mask */ +#define RTC_VER_NVTIM(value) (RTC_VER_NVTIM_Msk & ((value) << RTC_VER_NVTIM_Pos)) +#define RTC_VER_NVCAL_Pos _U_(1) /**< (RTC_VER) Non-valid Calendar Position */ +#define RTC_VER_NVCAL_Msk (_U_(0x1) << RTC_VER_NVCAL_Pos) /**< (RTC_VER) Non-valid Calendar Mask */ +#define RTC_VER_NVCAL(value) (RTC_VER_NVCAL_Msk & ((value) << RTC_VER_NVCAL_Pos)) +#define RTC_VER_NVTIMALR_Pos _U_(2) /**< (RTC_VER) Non-valid Time Alarm Position */ +#define RTC_VER_NVTIMALR_Msk (_U_(0x1) << RTC_VER_NVTIMALR_Pos) /**< (RTC_VER) Non-valid Time Alarm Mask */ +#define RTC_VER_NVTIMALR(value) (RTC_VER_NVTIMALR_Msk & ((value) << RTC_VER_NVTIMALR_Pos)) +#define RTC_VER_NVCALALR_Pos _U_(3) /**< (RTC_VER) Non-valid Calendar Alarm Position */ +#define RTC_VER_NVCALALR_Msk (_U_(0x1) << RTC_VER_NVCALALR_Pos) /**< (RTC_VER) Non-valid Calendar Alarm Mask */ +#define RTC_VER_NVCALALR(value) (RTC_VER_NVCALALR_Msk & ((value) << RTC_VER_NVCALALR_Pos)) +#define RTC_VER_Msk _U_(0x0000000F) /**< (RTC_VER) Register Mask */ + + +/** \brief RTC register offsets definitions */ +#define RTC_CR_REG_OFST (0x00) /**< (RTC_CR) Control Register Offset */ +#define RTC_MR_REG_OFST (0x04) /**< (RTC_MR) Mode Register Offset */ +#define RTC_TIMR_REG_OFST (0x08) /**< (RTC_TIMR) Time Register Offset */ +#define RTC_CALR_REG_OFST (0x0C) /**< (RTC_CALR) Calendar Register Offset */ +#define RTC_TIMALR_REG_OFST (0x10) /**< (RTC_TIMALR) Time Alarm Register Offset */ +#define RTC_CALALR_REG_OFST (0x14) /**< (RTC_CALALR) Calendar Alarm Register Offset */ +#define RTC_SR_REG_OFST (0x18) /**< (RTC_SR) Status Register Offset */ +#define RTC_SCCR_REG_OFST (0x1C) /**< (RTC_SCCR) Status Clear Command Register Offset */ +#define RTC_IER_REG_OFST (0x20) /**< (RTC_IER) Interrupt Enable Register Offset */ +#define RTC_IDR_REG_OFST (0x24) /**< (RTC_IDR) Interrupt Disable Register Offset */ +#define RTC_IMR_REG_OFST (0x28) /**< (RTC_IMR) Interrupt Mask Register Offset */ +#define RTC_VER_REG_OFST (0x2C) /**< (RTC_VER) Valid Entry Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RTC register API structure */ +typedef struct +{ + __IO uint32_t RTC_CR; /**< Offset: 0x00 (R/W 32) Control Register */ + __IO uint32_t RTC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t RTC_TIMR; /**< Offset: 0x08 (R/W 32) Time Register */ + __IO uint32_t RTC_CALR; /**< Offset: 0x0C (R/W 32) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< Offset: 0x10 (R/W 32) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< Offset: 0x14 (R/W 32) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< Offset: 0x18 (R/ 32) Status Register */ + __O uint32_t RTC_SCCR; /**< Offset: 0x1C ( /W 32) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< Offset: 0x20 ( /W 32) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< Offset: 0x24 ( /W 32) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< Offset: 0x28 (R/ 32) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< Offset: 0x2C (R/ 32) Valid Entry Register */ +} rtc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RTC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/rtt.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/rtt.h new file mode 100644 index 00000000..fffcfa45 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/rtt.h @@ -0,0 +1,95 @@ +/** + * \brief Component description for RTT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_RTT_COMPONENT_H_ +#define _SAME70_RTT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RTT */ +/* ************************************************************************** */ + +/* -------- RTT_MR : (RTT Offset: 0x00) (R/W 32) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos _U_(0) /**< (RTT_MR) Real-time Timer Prescaler Value Position */ +#define RTT_MR_RTPRES_Msk (_U_(0xFFFF) << RTT_MR_RTPRES_Pos) /**< (RTT_MR) Real-time Timer Prescaler Value Mask */ +#define RTT_MR_RTPRES(value) (RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)) +#define RTT_MR_ALMIEN_Pos _U_(16) /**< (RTT_MR) Alarm Interrupt Enable Position */ +#define RTT_MR_ALMIEN_Msk (_U_(0x1) << RTT_MR_ALMIEN_Pos) /**< (RTT_MR) Alarm Interrupt Enable Mask */ +#define RTT_MR_ALMIEN(value) (RTT_MR_ALMIEN_Msk & ((value) << RTT_MR_ALMIEN_Pos)) +#define RTT_MR_RTTINCIEN_Pos _U_(17) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Position */ +#define RTT_MR_RTTINCIEN_Msk (_U_(0x1) << RTT_MR_RTTINCIEN_Pos) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Mask */ +#define RTT_MR_RTTINCIEN(value) (RTT_MR_RTTINCIEN_Msk & ((value) << RTT_MR_RTTINCIEN_Pos)) +#define RTT_MR_RTTRST_Pos _U_(18) /**< (RTT_MR) Real-time Timer Restart Position */ +#define RTT_MR_RTTRST_Msk (_U_(0x1) << RTT_MR_RTTRST_Pos) /**< (RTT_MR) Real-time Timer Restart Mask */ +#define RTT_MR_RTTRST(value) (RTT_MR_RTTRST_Msk & ((value) << RTT_MR_RTTRST_Pos)) +#define RTT_MR_RTTDIS_Pos _U_(20) /**< (RTT_MR) Real-time Timer Disable Position */ +#define RTT_MR_RTTDIS_Msk (_U_(0x1) << RTT_MR_RTTDIS_Pos) /**< (RTT_MR) Real-time Timer Disable Mask */ +#define RTT_MR_RTTDIS(value) (RTT_MR_RTTDIS_Msk & ((value) << RTT_MR_RTTDIS_Pos)) +#define RTT_MR_RTC1HZ_Pos _U_(24) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Position */ +#define RTT_MR_RTC1HZ_Msk (_U_(0x1) << RTT_MR_RTC1HZ_Pos) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Mask */ +#define RTT_MR_RTC1HZ(value) (RTT_MR_RTC1HZ_Msk & ((value) << RTT_MR_RTC1HZ_Pos)) +#define RTT_MR_Msk _U_(0x0117FFFF) /**< (RTT_MR) Register Mask */ + + +/* -------- RTT_AR : (RTT Offset: 0x04) (R/W 32) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos _U_(0) /**< (RTT_AR) Alarm Value Position */ +#define RTT_AR_ALMV_Msk (_U_(0xFFFFFFFF) << RTT_AR_ALMV_Pos) /**< (RTT_AR) Alarm Value Mask */ +#define RTT_AR_ALMV(value) (RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)) +#define RTT_AR_Msk _U_(0xFFFFFFFF) /**< (RTT_AR) Register Mask */ + + +/* -------- RTT_VR : (RTT Offset: 0x08) ( R/ 32) Value Register -------- */ +#define RTT_VR_CRTV_Pos _U_(0) /**< (RTT_VR) Current Real-time Value Position */ +#define RTT_VR_CRTV_Msk (_U_(0xFFFFFFFF) << RTT_VR_CRTV_Pos) /**< (RTT_VR) Current Real-time Value Mask */ +#define RTT_VR_CRTV(value) (RTT_VR_CRTV_Msk & ((value) << RTT_VR_CRTV_Pos)) +#define RTT_VR_Msk _U_(0xFFFFFFFF) /**< (RTT_VR) Register Mask */ + + +/* -------- RTT_SR : (RTT Offset: 0x0C) ( R/ 32) Status Register -------- */ +#define RTT_SR_ALMS_Pos _U_(0) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Position */ +#define RTT_SR_ALMS_Msk (_U_(0x1) << RTT_SR_ALMS_Pos) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Mask */ +#define RTT_SR_ALMS(value) (RTT_SR_ALMS_Msk & ((value) << RTT_SR_ALMS_Pos)) +#define RTT_SR_RTTINC_Pos _U_(1) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Position */ +#define RTT_SR_RTTINC_Msk (_U_(0x1) << RTT_SR_RTTINC_Pos) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Mask */ +#define RTT_SR_RTTINC(value) (RTT_SR_RTTINC_Msk & ((value) << RTT_SR_RTTINC_Pos)) +#define RTT_SR_Msk _U_(0x00000003) /**< (RTT_SR) Register Mask */ + + +/** \brief RTT register offsets definitions */ +#define RTT_MR_REG_OFST (0x00) /**< (RTT_MR) Mode Register Offset */ +#define RTT_AR_REG_OFST (0x04) /**< (RTT_AR) Alarm Register Offset */ +#define RTT_VR_REG_OFST (0x08) /**< (RTT_VR) Value Register Offset */ +#define RTT_SR_REG_OFST (0x0C) /**< (RTT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RTT register API structure */ +typedef struct +{ + __IO uint32_t RTT_MR; /**< Offset: 0x00 (R/W 32) Mode Register */ + __IO uint32_t RTT_AR; /**< Offset: 0x04 (R/W 32) Alarm Register */ + __I uint32_t RTT_VR; /**< Offset: 0x08 (R/ 32) Value Register */ + __I uint32_t RTT_SR; /**< Offset: 0x0C (R/ 32) Status Register */ +} rtt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RTT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/sdramc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/sdramc.h new file mode 100644 index 00000000..67ab5e5b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/sdramc.h @@ -0,0 +1,264 @@ +/** + * \brief Component description for SDRAMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_SDRAMC_COMPONENT_H_ +#define _SAME70_SDRAMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SDRAMC */ +/* ************************************************************************** */ + +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) (R/W 32) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos _U_(0) /**< (SDRAMC_MR) SDRAMC Command Mode Position */ +#define SDRAMC_MR_MODE_Msk (_U_(0x7) << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) SDRAMC Command Mode Mask */ +#define SDRAMC_MR_MODE(value) (SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)) +#define SDRAMC_MR_MODE_NORMAL_Val _U_(0x0) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP_Val _U_(0x1) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val _U_(0x2) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG_Val _U_(0x3) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH_Val _U_(0x4) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val _U_(0x5) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN_Val _U_(0x6) /**< (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +#define SDRAMC_MR_MODE_NORMAL (SDRAMC_MR_MODE_NORMAL_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_NOP (SDRAMC_MR_MODE_NOP_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (SDRAMC_MR_MODE_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (SDRAMC_MR_MODE_AUTO_REFRESH_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. Position */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (SDRAMC_MR_MODE_DEEP_POWERDOWN_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. Position */ +#define SDRAMC_MR_Msk _U_(0x00000007) /**< (SDRAMC_MR) Register Mask */ + + +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) (R/W 32) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos _U_(0) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Position */ +#define SDRAMC_TR_COUNT_Msk (_U_(0xFFF) << SDRAMC_TR_COUNT_Pos) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Mask */ +#define SDRAMC_TR_COUNT(value) (SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)) +#define SDRAMC_TR_Msk _U_(0x00000FFF) /**< (SDRAMC_TR) Register Mask */ + + +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) (R/W 32) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos _U_(0) /**< (SDRAMC_CR) Number of Column Bits Position */ +#define SDRAMC_CR_NC_Msk (_U_(0x3) << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) Number of Column Bits Mask */ +#define SDRAMC_CR_NC(value) (SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)) +#define SDRAMC_CR_NC_COL8_Val _U_(0x0) /**< (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9_Val _U_(0x1) /**< (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10_Val _U_(0x2) /**< (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11_Val _U_(0x3) /**< (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NC_COL8 (SDRAMC_CR_NC_COL8_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 8 column bits Position */ +#define SDRAMC_CR_NC_COL9 (SDRAMC_CR_NC_COL9_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 9 column bits Position */ +#define SDRAMC_CR_NC_COL10 (SDRAMC_CR_NC_COL10_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 10 column bits Position */ +#define SDRAMC_CR_NC_COL11 (SDRAMC_CR_NC_COL11_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 11 column bits Position */ +#define SDRAMC_CR_NR_Pos _U_(2) /**< (SDRAMC_CR) Number of Row Bits Position */ +#define SDRAMC_CR_NR_Msk (_U_(0x3) << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) Number of Row Bits Mask */ +#define SDRAMC_CR_NR(value) (SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)) +#define SDRAMC_CR_NR_ROW11_Val _U_(0x0) /**< (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12_Val _U_(0x1) /**< (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13_Val _U_(0x2) /**< (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NR_ROW11 (SDRAMC_CR_NR_ROW11_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 11 row bits Position */ +#define SDRAMC_CR_NR_ROW12 (SDRAMC_CR_NR_ROW12_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 12 row bits Position */ +#define SDRAMC_CR_NR_ROW13 (SDRAMC_CR_NR_ROW13_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 13 row bits Position */ +#define SDRAMC_CR_NB_Pos _U_(4) /**< (SDRAMC_CR) Number of Banks Position */ +#define SDRAMC_CR_NB_Msk (_U_(0x1) << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) Number of Banks Mask */ +#define SDRAMC_CR_NB(value) (SDRAMC_CR_NB_Msk & ((value) << SDRAMC_CR_NB_Pos)) +#define SDRAMC_CR_NB_BANK2_Val _U_(0x0) /**< (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4_Val _U_(0x1) /**< (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_NB_BANK2 (SDRAMC_CR_NB_BANK2_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 2 banks Position */ +#define SDRAMC_CR_NB_BANK4 (SDRAMC_CR_NB_BANK4_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 4 banks Position */ +#define SDRAMC_CR_CAS_Pos _U_(5) /**< (SDRAMC_CR) CAS Latency Position */ +#define SDRAMC_CR_CAS_Msk (_U_(0x3) << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) CAS Latency Mask */ +#define SDRAMC_CR_CAS(value) (SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)) +#define SDRAMC_CR_CAS_LATENCY1_Val _U_(0x1) /**< (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2_Val _U_(0x2) /**< (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3_Val _U_(0x3) /**< (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY1 (SDRAMC_CR_CAS_LATENCY1_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 1 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY2 (SDRAMC_CR_CAS_LATENCY2_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 2 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY3 (SDRAMC_CR_CAS_LATENCY3_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 3 cycle CAS latency Position */ +#define SDRAMC_CR_DBW_Pos _U_(7) /**< (SDRAMC_CR) Data Bus Width Position */ +#define SDRAMC_CR_DBW_Msk (_U_(0x1) << SDRAMC_CR_DBW_Pos) /**< (SDRAMC_CR) Data Bus Width Mask */ +#define SDRAMC_CR_DBW(value) (SDRAMC_CR_DBW_Msk & ((value) << SDRAMC_CR_DBW_Pos)) +#define SDRAMC_CR_TWR_Pos _U_(8) /**< (SDRAMC_CR) Write Recovery Delay Position */ +#define SDRAMC_CR_TWR_Msk (_U_(0xF) << SDRAMC_CR_TWR_Pos) /**< (SDRAMC_CR) Write Recovery Delay Mask */ +#define SDRAMC_CR_TWR(value) (SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)) +#define SDRAMC_CR_TRC_TRFC_Pos _U_(12) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Position */ +#define SDRAMC_CR_TRC_TRFC_Msk (_U_(0xF) << SDRAMC_CR_TRC_TRFC_Pos) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Mask */ +#define SDRAMC_CR_TRC_TRFC(value) (SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)) +#define SDRAMC_CR_TRP_Pos _U_(16) /**< (SDRAMC_CR) Row Precharge Delay Position */ +#define SDRAMC_CR_TRP_Msk (_U_(0xF) << SDRAMC_CR_TRP_Pos) /**< (SDRAMC_CR) Row Precharge Delay Mask */ +#define SDRAMC_CR_TRP(value) (SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)) +#define SDRAMC_CR_TRCD_Pos _U_(20) /**< (SDRAMC_CR) Row to Column Delay Position */ +#define SDRAMC_CR_TRCD_Msk (_U_(0xF) << SDRAMC_CR_TRCD_Pos) /**< (SDRAMC_CR) Row to Column Delay Mask */ +#define SDRAMC_CR_TRCD(value) (SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)) +#define SDRAMC_CR_TRAS_Pos _U_(24) /**< (SDRAMC_CR) Active to Precharge Delay Position */ +#define SDRAMC_CR_TRAS_Msk (_U_(0xF) << SDRAMC_CR_TRAS_Pos) /**< (SDRAMC_CR) Active to Precharge Delay Mask */ +#define SDRAMC_CR_TRAS(value) (SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)) +#define SDRAMC_CR_TXSR_Pos _U_(28) /**< (SDRAMC_CR) Exit Self Refresh to Active Delay Position */ +#define SDRAMC_CR_TXSR_Msk (_U_(0xF) << SDRAMC_CR_TXSR_Pos) /**< (SDRAMC_CR) Exit Self Refresh to Active Delay Mask */ +#define SDRAMC_CR_TXSR(value) (SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)) +#define SDRAMC_CR_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_CR) Register Mask */ + + +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) (R/W 32) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos _U_(0) /**< (SDRAMC_LPR) Low-power Configuration Bits Position */ +#define SDRAMC_LPR_LPCB_Msk (_U_(0x3) << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low-power Configuration Bits Mask */ +#define SDRAMC_LPR_LPCB(value) (SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)) +#define SDRAMC_LPR_LPCB_DISABLED_Val _U_(0x0) /**< (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val _U_(0x3) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_LPCB_DISABLED (SDRAMC_LPR_LPCB_DISABLED_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. Position */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (SDRAMC_LPR_LPCB_SELF_REFRESH_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (SDRAMC_LPR_LPCB_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. Position */ +#define SDRAMC_LPR_PASR_Pos _U_(4) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_PASR_Msk (_U_(0x7) << SDRAMC_LPR_PASR_Pos) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_PASR(value) (SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)) +#define SDRAMC_LPR_TCSR_Pos _U_(8) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_TCSR_Msk (_U_(0x3) << SDRAMC_LPR_TCSR_Pos) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_TCSR(value) (SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)) +#define SDRAMC_LPR_DS_Pos _U_(10) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_DS_Msk (_U_(0x3) << SDRAMC_LPR_DS_Pos) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_DS(value) (SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)) +#define SDRAMC_LPR_TIMEOUT_Pos _U_(12) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Position */ +#define SDRAMC_LPR_TIMEOUT_Msk (_U_(0x3) << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Mask */ +#define SDRAMC_LPR_TIMEOUT(value) (SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val _U_(0x0) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_Msk _U_(0x00003F73) /**< (SDRAMC_LPR) Register Mask */ + + +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) ( /W 32) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES_Pos _U_(0) /**< (SDRAMC_IER) Refresh Error Status Position */ +#define SDRAMC_IER_RES_Msk (_U_(0x1) << SDRAMC_IER_RES_Pos) /**< (SDRAMC_IER) Refresh Error Status Mask */ +#define SDRAMC_IER_RES(value) (SDRAMC_IER_RES_Msk & ((value) << SDRAMC_IER_RES_Pos)) +#define SDRAMC_IER_Msk _U_(0x00000001) /**< (SDRAMC_IER) Register Mask */ + + +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) ( /W 32) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES_Pos _U_(0) /**< (SDRAMC_IDR) Refresh Error Status Position */ +#define SDRAMC_IDR_RES_Msk (_U_(0x1) << SDRAMC_IDR_RES_Pos) /**< (SDRAMC_IDR) Refresh Error Status Mask */ +#define SDRAMC_IDR_RES(value) (SDRAMC_IDR_RES_Msk & ((value) << SDRAMC_IDR_RES_Pos)) +#define SDRAMC_IDR_Msk _U_(0x00000001) /**< (SDRAMC_IDR) Register Mask */ + + +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) ( R/ 32) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES_Pos _U_(0) /**< (SDRAMC_IMR) Refresh Error Status Position */ +#define SDRAMC_IMR_RES_Msk (_U_(0x1) << SDRAMC_IMR_RES_Pos) /**< (SDRAMC_IMR) Refresh Error Status Mask */ +#define SDRAMC_IMR_RES(value) (SDRAMC_IMR_RES_Msk & ((value) << SDRAMC_IMR_RES_Pos)) +#define SDRAMC_IMR_Msk _U_(0x00000001) /**< (SDRAMC_IMR) Register Mask */ + + +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) ( R/ 32) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES_Pos _U_(0) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Position */ +#define SDRAMC_ISR_RES_Msk (_U_(0x1) << SDRAMC_ISR_RES_Pos) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Mask */ +#define SDRAMC_ISR_RES(value) (SDRAMC_ISR_RES_Msk & ((value) << SDRAMC_ISR_RES_Pos)) +#define SDRAMC_ISR_Msk _U_(0x00000001) /**< (SDRAMC_ISR) Register Mask */ + + +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) (R/W 32) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos _U_(0) /**< (SDRAMC_MDR) Memory Device Type Position */ +#define SDRAMC_MDR_MD_Msk (_U_(0x3) << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Memory Device Type Mask */ +#define SDRAMC_MDR_MD(value) (SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)) +#define SDRAMC_MDR_MD_SDRAM_Val _U_(0x0) /**< (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM_Val _U_(0x1) /**< (SDRAMC_MDR) Low-power SDRAM */ +#define SDRAMC_MDR_MD_SDRAM (SDRAMC_MDR_MD_SDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) SDRAM Position */ +#define SDRAMC_MDR_MD_LPSDRAM (SDRAMC_MDR_MD_LPSDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Low-power SDRAM Position */ +#define SDRAMC_MDR_Msk _U_(0x00000003) /**< (SDRAMC_MDR) Register Mask */ + + +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) (R/W 32) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos _U_(0) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Position */ +#define SDRAMC_CFR1_TMRD_Msk (_U_(0xF) << SDRAMC_CFR1_TMRD_Pos) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Mask */ +#define SDRAMC_CFR1_TMRD(value) (SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)) +#define SDRAMC_CFR1_UNAL_Pos _U_(8) /**< (SDRAMC_CFR1) Support Unaligned Access Position */ +#define SDRAMC_CFR1_UNAL_Msk (_U_(0x1) << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Support Unaligned Access Mask */ +#define SDRAMC_CFR1_UNAL(value) (SDRAMC_CFR1_UNAL_Msk & ((value) << SDRAMC_CFR1_UNAL_Pos)) +#define SDRAMC_CFR1_UNAL_UNSUPPORTED_Val _U_(0x0) /**< (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED_Val _U_(0x1) /**< (SDRAMC_CFR1) Unaligned access is supported. */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (SDRAMC_CFR1_UNAL_UNSUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is not supported. Position */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (SDRAMC_CFR1_UNAL_SUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is supported. Position */ +#define SDRAMC_CFR1_Msk _U_(0x0000010F) /**< (SDRAMC_CFR1) Register Mask */ + + +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) (R/W 32) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE_Pos _U_(0) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Position */ +#define SDRAMC_OCMS_SDR_SE_Msk (_U_(0x1) << SDRAMC_OCMS_SDR_SE_Pos) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Mask */ +#define SDRAMC_OCMS_SDR_SE(value) (SDRAMC_OCMS_SDR_SE_Msk & ((value) << SDRAMC_OCMS_SDR_SE_Pos)) +#define SDRAMC_OCMS_Msk _U_(0x00000001) /**< (SDRAMC_OCMS) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) ( /W 32) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos _U_(0) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SDRAMC_OCMS_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SDRAMC_OCMS_KEY1_KEY1(value) (SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)) +#define SDRAMC_OCMS_KEY1_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY1) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) ( /W 32) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos _U_(0) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SDRAMC_OCMS_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SDRAMC_OCMS_KEY2_KEY2(value) (SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)) +#define SDRAMC_OCMS_KEY2_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY2) Register Mask */ + + +/** \brief SDRAMC register offsets definitions */ +#define SDRAMC_MR_REG_OFST (0x00) /**< (SDRAMC_MR) SDRAMC Mode Register Offset */ +#define SDRAMC_TR_REG_OFST (0x04) /**< (SDRAMC_TR) SDRAMC Refresh Timer Register Offset */ +#define SDRAMC_CR_REG_OFST (0x08) /**< (SDRAMC_CR) SDRAMC Configuration Register Offset */ +#define SDRAMC_LPR_REG_OFST (0x10) /**< (SDRAMC_LPR) SDRAMC Low Power Register Offset */ +#define SDRAMC_IER_REG_OFST (0x14) /**< (SDRAMC_IER) SDRAMC Interrupt Enable Register Offset */ +#define SDRAMC_IDR_REG_OFST (0x18) /**< (SDRAMC_IDR) SDRAMC Interrupt Disable Register Offset */ +#define SDRAMC_IMR_REG_OFST (0x1C) /**< (SDRAMC_IMR) SDRAMC Interrupt Mask Register Offset */ +#define SDRAMC_ISR_REG_OFST (0x20) /**< (SDRAMC_ISR) SDRAMC Interrupt Status Register Offset */ +#define SDRAMC_MDR_REG_OFST (0x24) /**< (SDRAMC_MDR) SDRAMC Memory Device Register Offset */ +#define SDRAMC_CFR1_REG_OFST (0x28) /**< (SDRAMC_CFR1) SDRAMC Configuration Register 1 Offset */ +#define SDRAMC_OCMS_REG_OFST (0x2C) /**< (SDRAMC_OCMS) SDRAMC OCMS Register Offset */ +#define SDRAMC_OCMS_KEY1_REG_OFST (0x30) /**< (SDRAMC_OCMS_KEY1) SDRAMC OCMS KEY1 Register Offset */ +#define SDRAMC_OCMS_KEY2_REG_OFST (0x34) /**< (SDRAMC_OCMS_KEY2) SDRAMC OCMS KEY2 Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SDRAMC register API structure */ +typedef struct +{ + __IO uint32_t SDRAMC_MR; /**< Offset: 0x00 (R/W 32) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< Offset: 0x04 (R/W 32) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< Offset: 0x08 (R/W 32) SDRAMC Configuration Register */ + __I uint8_t Reserved1[0x04]; + __IO uint32_t SDRAMC_LPR; /**< Offset: 0x10 (R/W 32) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< Offset: 0x14 ( /W 32) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< Offset: 0x18 ( /W 32) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< Offset: 0x1C (R/ 32) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< Offset: 0x20 (R/ 32) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< Offset: 0x24 (R/W 32) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< Offset: 0x28 (R/W 32) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< Offset: 0x2C (R/W 32) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< Offset: 0x30 ( /W 32) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< Offset: 0x34 ( /W 32) SDRAMC OCMS KEY2 Register */ +} sdramc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SDRAMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/smc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/smc.h new file mode 100644 index 00000000..d8781b76 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/smc.h @@ -0,0 +1,219 @@ +/** + * \brief Component description for SMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_SMC_COMPONENT_H_ +#define _SAME70_SMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SMC */ +/* ************************************************************************** */ + +/* -------- SMC_SETUP : (SMC Offset: 0x00) (R/W 32) SMC Setup Register (CS_number = 0) -------- */ +#define SMC_SETUP_NWE_SETUP_Pos _U_(0) /**< (SMC_SETUP) NWE Setup Length Position */ +#define SMC_SETUP_NWE_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NWE_SETUP_Pos) /**< (SMC_SETUP) NWE Setup Length Mask */ +#define SMC_SETUP_NWE_SETUP(value) (SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)) +#define SMC_SETUP_NCS_WR_SETUP_Pos _U_(8) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Position */ +#define SMC_SETUP_NCS_WR_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_WR_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Mask */ +#define SMC_SETUP_NCS_WR_SETUP(value) (SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)) +#define SMC_SETUP_NRD_SETUP_Pos _U_(16) /**< (SMC_SETUP) NRD Setup Length Position */ +#define SMC_SETUP_NRD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NRD_SETUP_Pos) /**< (SMC_SETUP) NRD Setup Length Mask */ +#define SMC_SETUP_NRD_SETUP(value) (SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)) +#define SMC_SETUP_NCS_RD_SETUP_Pos _U_(24) /**< (SMC_SETUP) NCS Setup Length in READ Access Position */ +#define SMC_SETUP_NCS_RD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_RD_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in READ Access Mask */ +#define SMC_SETUP_NCS_RD_SETUP(value) (SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)) +#define SMC_SETUP_Msk _U_(0x3F3F3F3F) /**< (SMC_SETUP) Register Mask */ + + +/* -------- SMC_PULSE : (SMC Offset: 0x04) (R/W 32) SMC Pulse Register (CS_number = 0) -------- */ +#define SMC_PULSE_NWE_PULSE_Pos _U_(0) /**< (SMC_PULSE) NWE Pulse Length Position */ +#define SMC_PULSE_NWE_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NWE_PULSE_Pos) /**< (SMC_PULSE) NWE Pulse Length Mask */ +#define SMC_PULSE_NWE_PULSE(value) (SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)) +#define SMC_PULSE_NCS_WR_PULSE_Pos _U_(8) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Position */ +#define SMC_PULSE_NCS_WR_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_WR_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Mask */ +#define SMC_PULSE_NCS_WR_PULSE(value) (SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)) +#define SMC_PULSE_NRD_PULSE_Pos _U_(16) /**< (SMC_PULSE) NRD Pulse Length Position */ +#define SMC_PULSE_NRD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NRD_PULSE_Pos) /**< (SMC_PULSE) NRD Pulse Length Mask */ +#define SMC_PULSE_NRD_PULSE(value) (SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)) +#define SMC_PULSE_NCS_RD_PULSE_Pos _U_(24) /**< (SMC_PULSE) NCS Pulse Length in READ Access Position */ +#define SMC_PULSE_NCS_RD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_RD_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in READ Access Mask */ +#define SMC_PULSE_NCS_RD_PULSE(value) (SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)) +#define SMC_PULSE_Msk _U_(0x7F7F7F7F) /**< (SMC_PULSE) Register Mask */ + + +/* -------- SMC_CYCLE : (SMC Offset: 0x08) (R/W 32) SMC Cycle Register (CS_number = 0) -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos _U_(0) /**< (SMC_CYCLE) Total Write Cycle Length Position */ +#define SMC_CYCLE_NWE_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NWE_CYCLE_Pos) /**< (SMC_CYCLE) Total Write Cycle Length Mask */ +#define SMC_CYCLE_NWE_CYCLE(value) (SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)) +#define SMC_CYCLE_NRD_CYCLE_Pos _U_(16) /**< (SMC_CYCLE) Total Read Cycle Length Position */ +#define SMC_CYCLE_NRD_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NRD_CYCLE_Pos) /**< (SMC_CYCLE) Total Read Cycle Length Mask */ +#define SMC_CYCLE_NRD_CYCLE(value) (SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)) +#define SMC_CYCLE_Msk _U_(0x01FF01FF) /**< (SMC_CYCLE) Register Mask */ + + +/* -------- SMC_MODE : (SMC Offset: 0x0C) (R/W 32) SMC MODE Register (CS_number = 0) -------- */ +#define SMC_MODE_READ_MODE_Pos _U_(0) /**< (SMC_MODE) Read Mode Position */ +#define SMC_MODE_READ_MODE_Msk (_U_(0x1) << SMC_MODE_READ_MODE_Pos) /**< (SMC_MODE) Read Mode Mask */ +#define SMC_MODE_READ_MODE(value) (SMC_MODE_READ_MODE_Msk & ((value) << SMC_MODE_READ_MODE_Pos)) +#define SMC_MODE_WRITE_MODE_Pos _U_(1) /**< (SMC_MODE) Write Mode Position */ +#define SMC_MODE_WRITE_MODE_Msk (_U_(0x1) << SMC_MODE_WRITE_MODE_Pos) /**< (SMC_MODE) Write Mode Mask */ +#define SMC_MODE_WRITE_MODE(value) (SMC_MODE_WRITE_MODE_Msk & ((value) << SMC_MODE_WRITE_MODE_Pos)) +#define SMC_MODE_EXNW_MODE_Pos _U_(4) /**< (SMC_MODE) NWAIT Mode Position */ +#define SMC_MODE_EXNW_MODE_Msk (_U_(0x3) << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) NWAIT Mode Mask */ +#define SMC_MODE_EXNW_MODE(value) (SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)) +#define SMC_MODE_EXNW_MODE_DISABLED_Val _U_(0x0) /**< (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN_Val _U_(0x2) /**< (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY_Val _U_(0x3) /**< (SMC_MODE) Ready Mode */ +#define SMC_MODE_EXNW_MODE_DISABLED (SMC_MODE_EXNW_MODE_DISABLED_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Disabled Position */ +#define SMC_MODE_EXNW_MODE_FROZEN (SMC_MODE_EXNW_MODE_FROZEN_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Frozen Mode Position */ +#define SMC_MODE_EXNW_MODE_READY (SMC_MODE_EXNW_MODE_READY_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Ready Mode Position */ +#define SMC_MODE_BAT_Pos _U_(8) /**< (SMC_MODE) Byte Access Type Position */ +#define SMC_MODE_BAT_Msk (_U_(0x1) << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte Access Type Mask */ +#define SMC_MODE_BAT(value) (SMC_MODE_BAT_Msk & ((value) << SMC_MODE_BAT_Pos)) +#define SMC_MODE_BAT_BYTE_SELECT_Val _U_(0x0) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE_Val _U_(0x1) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_BAT_BYTE_SELECT (SMC_MODE_BAT_BYTE_SELECT_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. Position */ +#define SMC_MODE_BAT_BYTE_WRITE (SMC_MODE_BAT_BYTE_WRITE_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. Position */ +#define SMC_MODE_DBW_Pos _U_(12) /**< (SMC_MODE) Data Bus Width Position */ +#define SMC_MODE_DBW_Msk (_U_(0x1) << SMC_MODE_DBW_Pos) /**< (SMC_MODE) Data Bus Width Mask */ +#define SMC_MODE_DBW(value) (SMC_MODE_DBW_Msk & ((value) << SMC_MODE_DBW_Pos)) +#define SMC_MODE_DBW_8_BIT_Val _U_(0x0) /**< (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT_Val _U_(0x1) /**< (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_DBW_8_BIT (SMC_MODE_DBW_8_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 8-bit Data Bus Position */ +#define SMC_MODE_DBW_16_BIT (SMC_MODE_DBW_16_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 16-bit Data Bus Position */ +#define SMC_MODE_TDF_CYCLES_Pos _U_(16) /**< (SMC_MODE) Data Float Time Position */ +#define SMC_MODE_TDF_CYCLES_Msk (_U_(0xF) << SMC_MODE_TDF_CYCLES_Pos) /**< (SMC_MODE) Data Float Time Mask */ +#define SMC_MODE_TDF_CYCLES(value) (SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)) +#define SMC_MODE_TDF_MODE_Pos _U_(20) /**< (SMC_MODE) TDF Optimization Position */ +#define SMC_MODE_TDF_MODE_Msk (_U_(0x1) << SMC_MODE_TDF_MODE_Pos) /**< (SMC_MODE) TDF Optimization Mask */ +#define SMC_MODE_TDF_MODE(value) (SMC_MODE_TDF_MODE_Msk & ((value) << SMC_MODE_TDF_MODE_Pos)) +#define SMC_MODE_PMEN_Pos _U_(24) /**< (SMC_MODE) Page Mode Enabled Position */ +#define SMC_MODE_PMEN_Msk (_U_(0x1) << SMC_MODE_PMEN_Pos) /**< (SMC_MODE) Page Mode Enabled Mask */ +#define SMC_MODE_PMEN(value) (SMC_MODE_PMEN_Msk & ((value) << SMC_MODE_PMEN_Pos)) +#define SMC_MODE_PS_Pos _U_(28) /**< (SMC_MODE) Page Size Position */ +#define SMC_MODE_PS_Msk (_U_(0x3) << SMC_MODE_PS_Pos) /**< (SMC_MODE) Page Size Mask */ +#define SMC_MODE_PS(value) (SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)) +#define SMC_MODE_PS_4_BYTE_Val _U_(0x0) /**< (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE_Val _U_(0x1) /**< (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE_Val _U_(0x2) /**< (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE_Val _U_(0x3) /**< (SMC_MODE) 32-byte page */ +#define SMC_MODE_PS_4_BYTE (SMC_MODE_PS_4_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 4-byte page Position */ +#define SMC_MODE_PS_8_BYTE (SMC_MODE_PS_8_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 8-byte page Position */ +#define SMC_MODE_PS_16_BYTE (SMC_MODE_PS_16_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 16-byte page Position */ +#define SMC_MODE_PS_32_BYTE (SMC_MODE_PS_32_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 32-byte page Position */ +#define SMC_MODE_Msk _U_(0x311F1133) /**< (SMC_MODE) Register Mask */ + + +/* -------- SMC_OCMS : (SMC Offset: 0x80) (R/W 32) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE_Pos _U_(0) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Position */ +#define SMC_OCMS_SMSE_Msk (_U_(0x1) << SMC_OCMS_SMSE_Pos) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Mask */ +#define SMC_OCMS_SMSE(value) (SMC_OCMS_SMSE_Msk & ((value) << SMC_OCMS_SMSE_Pos)) +#define SMC_OCMS_CS0SE_Pos _U_(8) /**< (SMC_OCMS) Chip Select 0 Scrambling Enable Position */ +#define SMC_OCMS_CS0SE_Msk (_U_(0x1) << SMC_OCMS_CS0SE_Pos) /**< (SMC_OCMS) Chip Select 0 Scrambling Enable Mask */ +#define SMC_OCMS_CS0SE(value) (SMC_OCMS_CS0SE_Msk & ((value) << SMC_OCMS_CS0SE_Pos)) +#define SMC_OCMS_CS1SE_Pos _U_(9) /**< (SMC_OCMS) Chip Select 1 Scrambling Enable Position */ +#define SMC_OCMS_CS1SE_Msk (_U_(0x1) << SMC_OCMS_CS1SE_Pos) /**< (SMC_OCMS) Chip Select 1 Scrambling Enable Mask */ +#define SMC_OCMS_CS1SE(value) (SMC_OCMS_CS1SE_Msk & ((value) << SMC_OCMS_CS1SE_Pos)) +#define SMC_OCMS_CS2SE_Pos _U_(10) /**< (SMC_OCMS) Chip Select 2 Scrambling Enable Position */ +#define SMC_OCMS_CS2SE_Msk (_U_(0x1) << SMC_OCMS_CS2SE_Pos) /**< (SMC_OCMS) Chip Select 2 Scrambling Enable Mask */ +#define SMC_OCMS_CS2SE(value) (SMC_OCMS_CS2SE_Msk & ((value) << SMC_OCMS_CS2SE_Pos)) +#define SMC_OCMS_CS3SE_Pos _U_(11) /**< (SMC_OCMS) Chip Select 3 Scrambling Enable Position */ +#define SMC_OCMS_CS3SE_Msk (_U_(0x1) << SMC_OCMS_CS3SE_Pos) /**< (SMC_OCMS) Chip Select 3 Scrambling Enable Mask */ +#define SMC_OCMS_CS3SE(value) (SMC_OCMS_CS3SE_Msk & ((value) << SMC_OCMS_CS3SE_Pos)) +#define SMC_OCMS_Msk _U_(0x00000F01) /**< (SMC_OCMS) Register Mask */ + + +/* -------- SMC_KEY1 : (SMC Offset: 0x84) ( /W 32) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos _U_(0) /**< (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SMC_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SMC_KEY1_KEY1_Pos) /**< (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SMC_KEY1_KEY1(value) (SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)) +#define SMC_KEY1_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY1) Register Mask */ + + +/* -------- SMC_KEY2 : (SMC Offset: 0x88) ( /W 32) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos _U_(0) /**< (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SMC_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SMC_KEY2_KEY2_Pos) /**< (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SMC_KEY2_KEY2(value) (SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)) +#define SMC_KEY2_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY2) Register Mask */ + + +/* -------- SMC_WPMR : (SMC Offset: 0xE4) (R/W 32) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN_Pos _U_(0) /**< (SMC_WPMR) Write Protect Enable Position */ +#define SMC_WPMR_WPEN_Msk (_U_(0x1) << SMC_WPMR_WPEN_Pos) /**< (SMC_WPMR) Write Protect Enable Mask */ +#define SMC_WPMR_WPEN(value) (SMC_WPMR_WPEN_Msk & ((value) << SMC_WPMR_WPEN_Pos)) +#define SMC_WPMR_WPKEY_Pos _U_(8) /**< (SMC_WPMR) Write Protection Key Position */ +#define SMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Write Protection Key Mask */ +#define SMC_WPMR_WPKEY(value) (SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)) +#define SMC_WPMR_WPKEY_PASSWD_Val _U_(0x534D43) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define SMC_WPMR_WPKEY_PASSWD (SMC_WPMR_WPKEY_PASSWD_Val << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define SMC_WPMR_Msk _U_(0xFFFFFF01) /**< (SMC_WPMR) Register Mask */ + + +/* -------- SMC_WPSR : (SMC Offset: 0xE8) ( R/ 32) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS_Pos _U_(0) /**< (SMC_WPSR) Write Protection Violation Status Position */ +#define SMC_WPSR_WPVS_Msk (_U_(0x1) << SMC_WPSR_WPVS_Pos) /**< (SMC_WPSR) Write Protection Violation Status Mask */ +#define SMC_WPSR_WPVS(value) (SMC_WPSR_WPVS_Msk & ((value) << SMC_WPSR_WPVS_Pos)) +#define SMC_WPSR_WPVSRC_Pos _U_(8) /**< (SMC_WPSR) Write Protection Violation Source Position */ +#define SMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SMC_WPSR_WPVSRC_Pos) /**< (SMC_WPSR) Write Protection Violation Source Mask */ +#define SMC_WPSR_WPVSRC(value) (SMC_WPSR_WPVSRC_Msk & ((value) << SMC_WPSR_WPVSRC_Pos)) +#define SMC_WPSR_Msk _U_(0x00FFFF01) /**< (SMC_WPSR) Register Mask */ + + +/** \brief SMC register offsets definitions */ +#define SMC_SETUP_REG_OFST (0x00) /**< (SMC_SETUP) SMC Setup Register (CS_number = 0) Offset */ +#define SMC_PULSE_REG_OFST (0x04) /**< (SMC_PULSE) SMC Pulse Register (CS_number = 0) Offset */ +#define SMC_CYCLE_REG_OFST (0x08) /**< (SMC_CYCLE) SMC Cycle Register (CS_number = 0) Offset */ +#define SMC_MODE_REG_OFST (0x0C) /**< (SMC_MODE) SMC MODE Register (CS_number = 0) Offset */ +#define SMC_OCMS_REG_OFST (0x80) /**< (SMC_OCMS) SMC OCMS MODE Register Offset */ +#define SMC_KEY1_REG_OFST (0x84) /**< (SMC_KEY1) SMC OCMS KEY1 Register Offset */ +#define SMC_KEY2_REG_OFST (0x88) /**< (SMC_KEY2) SMC OCMS KEY2 Register Offset */ +#define SMC_WPMR_REG_OFST (0xE4) /**< (SMC_WPMR) SMC Write Protection Mode Register Offset */ +#define SMC_WPSR_REG_OFST (0xE8) /**< (SMC_WPSR) SMC Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SMC_CS_NUMBER register API structure */ +typedef struct +{ + __IO uint32_t SMC_SETUP; /**< Offset: 0x00 (R/W 32) SMC Setup Register (CS_number = 0) */ + __IO uint32_t SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */ + __IO uint32_t SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */ + __IO uint32_t SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC MODE Register (CS_number = 0) */ +} smc_cs_number_registers_t; + +#define SMC_CS_NUMBER_NUMBER _U_(4) + +/** \brief SMC register API structure */ +typedef struct +{ + smc_cs_number_registers_t SMC_CS_NUMBER[SMC_CS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ + __I uint8_t Reserved1[0x40]; + __IO uint32_t SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< Offset: 0x88 ( /W 32) SMC OCMS KEY2 Register */ + __I uint8_t Reserved2[0x58]; + __IO uint32_t SMC_WPMR; /**< Offset: 0xE4 (R/W 32) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< Offset: 0xE8 (R/ 32) SMC Write Protection Status Register */ +} smc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/spi.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/spi.h new file mode 100644 index 00000000..ffa69ab6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/spi.h @@ -0,0 +1,318 @@ +/** + * \brief Component description for SPI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_SPI_COMPONENT_H_ +#define _SAME70_SPI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SPI */ +/* ************************************************************************** */ + +/* -------- SPI_CR : (SPI Offset: 0x00) ( /W 32) Control Register -------- */ +#define SPI_CR_SPIEN_Pos _U_(0) /**< (SPI_CR) SPI Enable Position */ +#define SPI_CR_SPIEN_Msk (_U_(0x1) << SPI_CR_SPIEN_Pos) /**< (SPI_CR) SPI Enable Mask */ +#define SPI_CR_SPIEN(value) (SPI_CR_SPIEN_Msk & ((value) << SPI_CR_SPIEN_Pos)) +#define SPI_CR_SPIDIS_Pos _U_(1) /**< (SPI_CR) SPI Disable Position */ +#define SPI_CR_SPIDIS_Msk (_U_(0x1) << SPI_CR_SPIDIS_Pos) /**< (SPI_CR) SPI Disable Mask */ +#define SPI_CR_SPIDIS(value) (SPI_CR_SPIDIS_Msk & ((value) << SPI_CR_SPIDIS_Pos)) +#define SPI_CR_SWRST_Pos _U_(7) /**< (SPI_CR) SPI Software Reset Position */ +#define SPI_CR_SWRST_Msk (_U_(0x1) << SPI_CR_SWRST_Pos) /**< (SPI_CR) SPI Software Reset Mask */ +#define SPI_CR_SWRST(value) (SPI_CR_SWRST_Msk & ((value) << SPI_CR_SWRST_Pos)) +#define SPI_CR_REQCLR_Pos _U_(12) /**< (SPI_CR) Request to Clear the Comparison Trigger Position */ +#define SPI_CR_REQCLR_Msk (_U_(0x1) << SPI_CR_REQCLR_Pos) /**< (SPI_CR) Request to Clear the Comparison Trigger Mask */ +#define SPI_CR_REQCLR(value) (SPI_CR_REQCLR_Msk & ((value) << SPI_CR_REQCLR_Pos)) +#define SPI_CR_TXFCLR_Pos _U_(16) /**< (SPI_CR) Transmit FIFO Clear Position */ +#define SPI_CR_TXFCLR_Msk (_U_(0x1) << SPI_CR_TXFCLR_Pos) /**< (SPI_CR) Transmit FIFO Clear Mask */ +#define SPI_CR_TXFCLR(value) (SPI_CR_TXFCLR_Msk & ((value) << SPI_CR_TXFCLR_Pos)) +#define SPI_CR_RXFCLR_Pos _U_(17) /**< (SPI_CR) Receive FIFO Clear Position */ +#define SPI_CR_RXFCLR_Msk (_U_(0x1) << SPI_CR_RXFCLR_Pos) /**< (SPI_CR) Receive FIFO Clear Mask */ +#define SPI_CR_RXFCLR(value) (SPI_CR_RXFCLR_Msk & ((value) << SPI_CR_RXFCLR_Pos)) +#define SPI_CR_LASTXFER_Pos _U_(24) /**< (SPI_CR) Last Transfer Position */ +#define SPI_CR_LASTXFER_Msk (_U_(0x1) << SPI_CR_LASTXFER_Pos) /**< (SPI_CR) Last Transfer Mask */ +#define SPI_CR_LASTXFER(value) (SPI_CR_LASTXFER_Msk & ((value) << SPI_CR_LASTXFER_Pos)) +#define SPI_CR_FIFOEN_Pos _U_(30) /**< (SPI_CR) FIFO Enable Position */ +#define SPI_CR_FIFOEN_Msk (_U_(0x1) << SPI_CR_FIFOEN_Pos) /**< (SPI_CR) FIFO Enable Mask */ +#define SPI_CR_FIFOEN(value) (SPI_CR_FIFOEN_Msk & ((value) << SPI_CR_FIFOEN_Pos)) +#define SPI_CR_FIFODIS_Pos _U_(31) /**< (SPI_CR) FIFO Disable Position */ +#define SPI_CR_FIFODIS_Msk (_U_(0x1) << SPI_CR_FIFODIS_Pos) /**< (SPI_CR) FIFO Disable Mask */ +#define SPI_CR_FIFODIS(value) (SPI_CR_FIFODIS_Msk & ((value) << SPI_CR_FIFODIS_Pos)) +#define SPI_CR_Msk _U_(0xC1031083) /**< (SPI_CR) Register Mask */ + + +/* -------- SPI_MR : (SPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define SPI_MR_MSTR_Pos _U_(0) /**< (SPI_MR) Master/Slave Mode Position */ +#define SPI_MR_MSTR_Msk (_U_(0x1) << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master/Slave Mode Mask */ +#define SPI_MR_MSTR(value) (SPI_MR_MSTR_Msk & ((value) << SPI_MR_MSTR_Pos)) +#define SPI_MR_PS_Pos _U_(1) /**< (SPI_MR) Peripheral Select Position */ +#define SPI_MR_PS_Msk (_U_(0x1) << SPI_MR_PS_Pos) /**< (SPI_MR) Peripheral Select Mask */ +#define SPI_MR_PS(value) (SPI_MR_PS_Msk & ((value) << SPI_MR_PS_Pos)) +#define SPI_MR_PCSDEC_Pos _U_(2) /**< (SPI_MR) Chip Select Decode Position */ +#define SPI_MR_PCSDEC_Msk (_U_(0x1) << SPI_MR_PCSDEC_Pos) /**< (SPI_MR) Chip Select Decode Mask */ +#define SPI_MR_PCSDEC(value) (SPI_MR_PCSDEC_Msk & ((value) << SPI_MR_PCSDEC_Pos)) +#define SPI_MR_MODFDIS_Pos _U_(4) /**< (SPI_MR) Mode Fault Detection Position */ +#define SPI_MR_MODFDIS_Msk (_U_(0x1) << SPI_MR_MODFDIS_Pos) /**< (SPI_MR) Mode Fault Detection Mask */ +#define SPI_MR_MODFDIS(value) (SPI_MR_MODFDIS_Msk & ((value) << SPI_MR_MODFDIS_Pos)) +#define SPI_MR_WDRBT_Pos _U_(5) /**< (SPI_MR) Wait Data Read Before Transfer Position */ +#define SPI_MR_WDRBT_Msk (_U_(0x1) << SPI_MR_WDRBT_Pos) /**< (SPI_MR) Wait Data Read Before Transfer Mask */ +#define SPI_MR_WDRBT(value) (SPI_MR_WDRBT_Msk & ((value) << SPI_MR_WDRBT_Pos)) +#define SPI_MR_LLB_Pos _U_(7) /**< (SPI_MR) Local Loopback Enable Position */ +#define SPI_MR_LLB_Msk (_U_(0x1) << SPI_MR_LLB_Pos) /**< (SPI_MR) Local Loopback Enable Mask */ +#define SPI_MR_LLB(value) (SPI_MR_LLB_Msk & ((value) << SPI_MR_LLB_Pos)) +#define SPI_MR_PCS_Pos _U_(16) /**< (SPI_MR) Peripheral Chip Select Position */ +#define SPI_MR_PCS_Msk (_U_(0xF) << SPI_MR_PCS_Pos) /**< (SPI_MR) Peripheral Chip Select Mask */ +#define SPI_MR_PCS(value) (SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)) +#define SPI_MR_DLYBCS_Pos _U_(24) /**< (SPI_MR) Delay Between Chip Selects Position */ +#define SPI_MR_DLYBCS_Msk (_U_(0xFF) << SPI_MR_DLYBCS_Pos) /**< (SPI_MR) Delay Between Chip Selects Mask */ +#define SPI_MR_DLYBCS(value) (SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)) +#define SPI_MR_Msk _U_(0xFF0F00B7) /**< (SPI_MR) Register Mask */ + + +/* -------- SPI_RDR : (SPI Offset: 0x08) ( R/ 32) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos _U_(0) /**< (SPI_RDR) Receive Data Position */ +#define SPI_RDR_RD_Msk (_U_(0xFFFF) << SPI_RDR_RD_Pos) /**< (SPI_RDR) Receive Data Mask */ +#define SPI_RDR_RD(value) (SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos)) +#define SPI_RDR_PCS_Pos _U_(16) /**< (SPI_RDR) Peripheral Chip Select Position */ +#define SPI_RDR_PCS_Msk (_U_(0xF) << SPI_RDR_PCS_Pos) /**< (SPI_RDR) Peripheral Chip Select Mask */ +#define SPI_RDR_PCS(value) (SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos)) +#define SPI_RDR_Msk _U_(0x000FFFFF) /**< (SPI_RDR) Register Mask */ + + +/* -------- SPI_TDR : (SPI Offset: 0x0C) ( /W 32) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos _U_(0) /**< (SPI_TDR) Transmit Data Position */ +#define SPI_TDR_TD_Msk (_U_(0xFFFF) << SPI_TDR_TD_Pos) /**< (SPI_TDR) Transmit Data Mask */ +#define SPI_TDR_TD(value) (SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)) +#define SPI_TDR_PCS_Pos _U_(16) /**< (SPI_TDR) Peripheral Chip Select Position */ +#define SPI_TDR_PCS_Msk (_U_(0xF) << SPI_TDR_PCS_Pos) /**< (SPI_TDR) Peripheral Chip Select Mask */ +#define SPI_TDR_PCS(value) (SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)) +#define SPI_TDR_LASTXFER_Pos _U_(24) /**< (SPI_TDR) Last Transfer Position */ +#define SPI_TDR_LASTXFER_Msk (_U_(0x1) << SPI_TDR_LASTXFER_Pos) /**< (SPI_TDR) Last Transfer Mask */ +#define SPI_TDR_LASTXFER(value) (SPI_TDR_LASTXFER_Msk & ((value) << SPI_TDR_LASTXFER_Pos)) +#define SPI_TDR_Msk _U_(0x010FFFFF) /**< (SPI_TDR) Register Mask */ + + +/* -------- SPI_SR : (SPI Offset: 0x10) ( R/ 32) Status Register -------- */ +#define SPI_SR_RDRF_Pos _U_(0) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define SPI_SR_RDRF_Msk (_U_(0x1) << SPI_SR_RDRF_Pos) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define SPI_SR_RDRF(value) (SPI_SR_RDRF_Msk & ((value) << SPI_SR_RDRF_Pos)) +#define SPI_SR_TDRE_Pos _U_(1) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TDRE_Msk (_U_(0x1) << SPI_SR_TDRE_Pos) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TDRE(value) (SPI_SR_TDRE_Msk & ((value) << SPI_SR_TDRE_Pos)) +#define SPI_SR_MODF_Pos _U_(2) /**< (SPI_SR) Mode Fault Error (cleared on read) Position */ +#define SPI_SR_MODF_Msk (_U_(0x1) << SPI_SR_MODF_Pos) /**< (SPI_SR) Mode Fault Error (cleared on read) Mask */ +#define SPI_SR_MODF(value) (SPI_SR_MODF_Msk & ((value) << SPI_SR_MODF_Pos)) +#define SPI_SR_OVRES_Pos _U_(3) /**< (SPI_SR) Overrun Error Status (cleared on read) Position */ +#define SPI_SR_OVRES_Msk (_U_(0x1) << SPI_SR_OVRES_Pos) /**< (SPI_SR) Overrun Error Status (cleared on read) Mask */ +#define SPI_SR_OVRES(value) (SPI_SR_OVRES_Msk & ((value) << SPI_SR_OVRES_Pos)) +#define SPI_SR_NSSR_Pos _U_(8) /**< (SPI_SR) NSS Rising (cleared on read) Position */ +#define SPI_SR_NSSR_Msk (_U_(0x1) << SPI_SR_NSSR_Pos) /**< (SPI_SR) NSS Rising (cleared on read) Mask */ +#define SPI_SR_NSSR(value) (SPI_SR_NSSR_Msk & ((value) << SPI_SR_NSSR_Pos)) +#define SPI_SR_TXEMPTY_Pos _U_(9) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TXEMPTY_Msk (_U_(0x1) << SPI_SR_TXEMPTY_Pos) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TXEMPTY(value) (SPI_SR_TXEMPTY_Msk & ((value) << SPI_SR_TXEMPTY_Pos)) +#define SPI_SR_UNDES_Pos _U_(10) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Position */ +#define SPI_SR_UNDES_Msk (_U_(0x1) << SPI_SR_UNDES_Pos) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Mask */ +#define SPI_SR_UNDES(value) (SPI_SR_UNDES_Msk & ((value) << SPI_SR_UNDES_Pos)) +#define SPI_SR_SPIENS_Pos _U_(16) /**< (SPI_SR) SPI Enable Status Position */ +#define SPI_SR_SPIENS_Msk (_U_(0x1) << SPI_SR_SPIENS_Pos) /**< (SPI_SR) SPI Enable Status Mask */ +#define SPI_SR_SPIENS(value) (SPI_SR_SPIENS_Msk & ((value) << SPI_SR_SPIENS_Pos)) +#define SPI_SR_Msk _U_(0x0001070F) /**< (SPI_SR) Register Mask */ + + +/* -------- SPI_IER : (SPI Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF_Pos _U_(0) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define SPI_IER_RDRF_Msk (_U_(0x1) << SPI_IER_RDRF_Pos) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define SPI_IER_RDRF(value) (SPI_IER_RDRF_Msk & ((value) << SPI_IER_RDRF_Pos)) +#define SPI_IER_TDRE_Pos _U_(1) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Position */ +#define SPI_IER_TDRE_Msk (_U_(0x1) << SPI_IER_TDRE_Pos) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Mask */ +#define SPI_IER_TDRE(value) (SPI_IER_TDRE_Msk & ((value) << SPI_IER_TDRE_Pos)) +#define SPI_IER_MODF_Pos _U_(2) /**< (SPI_IER) Mode Fault Error Interrupt Enable Position */ +#define SPI_IER_MODF_Msk (_U_(0x1) << SPI_IER_MODF_Pos) /**< (SPI_IER) Mode Fault Error Interrupt Enable Mask */ +#define SPI_IER_MODF(value) (SPI_IER_MODF_Msk & ((value) << SPI_IER_MODF_Pos)) +#define SPI_IER_OVRES_Pos _U_(3) /**< (SPI_IER) Overrun Error Interrupt Enable Position */ +#define SPI_IER_OVRES_Msk (_U_(0x1) << SPI_IER_OVRES_Pos) /**< (SPI_IER) Overrun Error Interrupt Enable Mask */ +#define SPI_IER_OVRES(value) (SPI_IER_OVRES_Msk & ((value) << SPI_IER_OVRES_Pos)) +#define SPI_IER_NSSR_Pos _U_(8) /**< (SPI_IER) NSS Rising Interrupt Enable Position */ +#define SPI_IER_NSSR_Msk (_U_(0x1) << SPI_IER_NSSR_Pos) /**< (SPI_IER) NSS Rising Interrupt Enable Mask */ +#define SPI_IER_NSSR(value) (SPI_IER_NSSR_Msk & ((value) << SPI_IER_NSSR_Pos)) +#define SPI_IER_TXEMPTY_Pos _U_(9) /**< (SPI_IER) Transmission Registers Empty Enable Position */ +#define SPI_IER_TXEMPTY_Msk (_U_(0x1) << SPI_IER_TXEMPTY_Pos) /**< (SPI_IER) Transmission Registers Empty Enable Mask */ +#define SPI_IER_TXEMPTY(value) (SPI_IER_TXEMPTY_Msk & ((value) << SPI_IER_TXEMPTY_Pos)) +#define SPI_IER_UNDES_Pos _U_(10) /**< (SPI_IER) Underrun Error Interrupt Enable Position */ +#define SPI_IER_UNDES_Msk (_U_(0x1) << SPI_IER_UNDES_Pos) /**< (SPI_IER) Underrun Error Interrupt Enable Mask */ +#define SPI_IER_UNDES(value) (SPI_IER_UNDES_Msk & ((value) << SPI_IER_UNDES_Pos)) +#define SPI_IER_Msk _U_(0x0000070F) /**< (SPI_IER) Register Mask */ + + +/* -------- SPI_IDR : (SPI Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF_Pos _U_(0) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define SPI_IDR_RDRF_Msk (_U_(0x1) << SPI_IDR_RDRF_Pos) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define SPI_IDR_RDRF(value) (SPI_IDR_RDRF_Msk & ((value) << SPI_IDR_RDRF_Pos)) +#define SPI_IDR_TDRE_Pos _U_(1) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Position */ +#define SPI_IDR_TDRE_Msk (_U_(0x1) << SPI_IDR_TDRE_Pos) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Mask */ +#define SPI_IDR_TDRE(value) (SPI_IDR_TDRE_Msk & ((value) << SPI_IDR_TDRE_Pos)) +#define SPI_IDR_MODF_Pos _U_(2) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Position */ +#define SPI_IDR_MODF_Msk (_U_(0x1) << SPI_IDR_MODF_Pos) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Mask */ +#define SPI_IDR_MODF(value) (SPI_IDR_MODF_Msk & ((value) << SPI_IDR_MODF_Pos)) +#define SPI_IDR_OVRES_Pos _U_(3) /**< (SPI_IDR) Overrun Error Interrupt Disable Position */ +#define SPI_IDR_OVRES_Msk (_U_(0x1) << SPI_IDR_OVRES_Pos) /**< (SPI_IDR) Overrun Error Interrupt Disable Mask */ +#define SPI_IDR_OVRES(value) (SPI_IDR_OVRES_Msk & ((value) << SPI_IDR_OVRES_Pos)) +#define SPI_IDR_NSSR_Pos _U_(8) /**< (SPI_IDR) NSS Rising Interrupt Disable Position */ +#define SPI_IDR_NSSR_Msk (_U_(0x1) << SPI_IDR_NSSR_Pos) /**< (SPI_IDR) NSS Rising Interrupt Disable Mask */ +#define SPI_IDR_NSSR(value) (SPI_IDR_NSSR_Msk & ((value) << SPI_IDR_NSSR_Pos)) +#define SPI_IDR_TXEMPTY_Pos _U_(9) /**< (SPI_IDR) Transmission Registers Empty Disable Position */ +#define SPI_IDR_TXEMPTY_Msk (_U_(0x1) << SPI_IDR_TXEMPTY_Pos) /**< (SPI_IDR) Transmission Registers Empty Disable Mask */ +#define SPI_IDR_TXEMPTY(value) (SPI_IDR_TXEMPTY_Msk & ((value) << SPI_IDR_TXEMPTY_Pos)) +#define SPI_IDR_UNDES_Pos _U_(10) /**< (SPI_IDR) Underrun Error Interrupt Disable Position */ +#define SPI_IDR_UNDES_Msk (_U_(0x1) << SPI_IDR_UNDES_Pos) /**< (SPI_IDR) Underrun Error Interrupt Disable Mask */ +#define SPI_IDR_UNDES(value) (SPI_IDR_UNDES_Msk & ((value) << SPI_IDR_UNDES_Pos)) +#define SPI_IDR_Msk _U_(0x0000070F) /**< (SPI_IDR) Register Mask */ + + +/* -------- SPI_IMR : (SPI Offset: 0x1C) ( R/ 32) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF_Pos _U_(0) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define SPI_IMR_RDRF_Msk (_U_(0x1) << SPI_IMR_RDRF_Pos) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define SPI_IMR_RDRF(value) (SPI_IMR_RDRF_Msk & ((value) << SPI_IMR_RDRF_Pos)) +#define SPI_IMR_TDRE_Pos _U_(1) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Position */ +#define SPI_IMR_TDRE_Msk (_U_(0x1) << SPI_IMR_TDRE_Pos) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Mask */ +#define SPI_IMR_TDRE(value) (SPI_IMR_TDRE_Msk & ((value) << SPI_IMR_TDRE_Pos)) +#define SPI_IMR_MODF_Pos _U_(2) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Position */ +#define SPI_IMR_MODF_Msk (_U_(0x1) << SPI_IMR_MODF_Pos) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Mask */ +#define SPI_IMR_MODF(value) (SPI_IMR_MODF_Msk & ((value) << SPI_IMR_MODF_Pos)) +#define SPI_IMR_OVRES_Pos _U_(3) /**< (SPI_IMR) Overrun Error Interrupt Mask Position */ +#define SPI_IMR_OVRES_Msk (_U_(0x1) << SPI_IMR_OVRES_Pos) /**< (SPI_IMR) Overrun Error Interrupt Mask Mask */ +#define SPI_IMR_OVRES(value) (SPI_IMR_OVRES_Msk & ((value) << SPI_IMR_OVRES_Pos)) +#define SPI_IMR_NSSR_Pos _U_(8) /**< (SPI_IMR) NSS Rising Interrupt Mask Position */ +#define SPI_IMR_NSSR_Msk (_U_(0x1) << SPI_IMR_NSSR_Pos) /**< (SPI_IMR) NSS Rising Interrupt Mask Mask */ +#define SPI_IMR_NSSR(value) (SPI_IMR_NSSR_Msk & ((value) << SPI_IMR_NSSR_Pos)) +#define SPI_IMR_TXEMPTY_Pos _U_(9) /**< (SPI_IMR) Transmission Registers Empty Mask Position */ +#define SPI_IMR_TXEMPTY_Msk (_U_(0x1) << SPI_IMR_TXEMPTY_Pos) /**< (SPI_IMR) Transmission Registers Empty Mask Mask */ +#define SPI_IMR_TXEMPTY(value) (SPI_IMR_TXEMPTY_Msk & ((value) << SPI_IMR_TXEMPTY_Pos)) +#define SPI_IMR_UNDES_Pos _U_(10) /**< (SPI_IMR) Underrun Error Interrupt Mask Position */ +#define SPI_IMR_UNDES_Msk (_U_(0x1) << SPI_IMR_UNDES_Pos) /**< (SPI_IMR) Underrun Error Interrupt Mask Mask */ +#define SPI_IMR_UNDES(value) (SPI_IMR_UNDES_Msk & ((value) << SPI_IMR_UNDES_Pos)) +#define SPI_IMR_Msk _U_(0x0000070F) /**< (SPI_IMR) Register Mask */ + + +/* -------- SPI_CSR : (SPI Offset: 0x30) (R/W 32) Chip Select Register 0 -------- */ +#define SPI_CSR_CPOL_Pos _U_(0) /**< (SPI_CSR) Clock Polarity Position */ +#define SPI_CSR_CPOL_Msk (_U_(0x1) << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock Polarity Mask */ +#define SPI_CSR_CPOL(value) (SPI_CSR_CPOL_Msk & ((value) << SPI_CSR_CPOL_Pos)) +#define SPI_CSR_NCPHA_Pos _U_(1) /**< (SPI_CSR) Clock Phase Position */ +#define SPI_CSR_NCPHA_Msk (_U_(0x1) << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Clock Phase Mask */ +#define SPI_CSR_NCPHA(value) (SPI_CSR_NCPHA_Msk & ((value) << SPI_CSR_NCPHA_Pos)) +#define SPI_CSR_CSNAAT_Pos _U_(2) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Position */ +#define SPI_CSR_CSNAAT_Msk (_U_(0x1) << SPI_CSR_CSNAAT_Pos) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Mask */ +#define SPI_CSR_CSNAAT(value) (SPI_CSR_CSNAAT_Msk & ((value) << SPI_CSR_CSNAAT_Pos)) +#define SPI_CSR_CSAAT_Pos _U_(3) /**< (SPI_CSR) Chip Select Active After Transfer Position */ +#define SPI_CSR_CSAAT_Msk (_U_(0x1) << SPI_CSR_CSAAT_Pos) /**< (SPI_CSR) Chip Select Active After Transfer Mask */ +#define SPI_CSR_CSAAT(value) (SPI_CSR_CSAAT_Msk & ((value) << SPI_CSR_CSAAT_Pos)) +#define SPI_CSR_BITS_Pos _U_(4) /**< (SPI_CSR) Bits Per Transfer Position */ +#define SPI_CSR_BITS_Msk (_U_(0xF) << SPI_CSR_BITS_Pos) /**< (SPI_CSR) Bits Per Transfer Mask */ +#define SPI_CSR_BITS(value) (SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)) +#define SPI_CSR_BITS_8_BIT_Val _U_(0x0) /**< (SPI_CSR) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT_Val _U_(0x1) /**< (SPI_CSR) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT_Val _U_(0x2) /**< (SPI_CSR) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT_Val _U_(0x3) /**< (SPI_CSR) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT_Val _U_(0x4) /**< (SPI_CSR) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT_Val _U_(0x5) /**< (SPI_CSR) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT_Val _U_(0x6) /**< (SPI_CSR) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT_Val _U_(0x7) /**< (SPI_CSR) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT_Val _U_(0x8) /**< (SPI_CSR) 16 bits for transfer */ +#define SPI_CSR_BITS_8_BIT (SPI_CSR_BITS_8_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 8 bits for transfer Position */ +#define SPI_CSR_BITS_9_BIT (SPI_CSR_BITS_9_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 9 bits for transfer Position */ +#define SPI_CSR_BITS_10_BIT (SPI_CSR_BITS_10_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 10 bits for transfer Position */ +#define SPI_CSR_BITS_11_BIT (SPI_CSR_BITS_11_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 11 bits for transfer Position */ +#define SPI_CSR_BITS_12_BIT (SPI_CSR_BITS_12_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 12 bits for transfer Position */ +#define SPI_CSR_BITS_13_BIT (SPI_CSR_BITS_13_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 13 bits for transfer Position */ +#define SPI_CSR_BITS_14_BIT (SPI_CSR_BITS_14_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 14 bits for transfer Position */ +#define SPI_CSR_BITS_15_BIT (SPI_CSR_BITS_15_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 15 bits for transfer Position */ +#define SPI_CSR_BITS_16_BIT (SPI_CSR_BITS_16_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 16 bits for transfer Position */ +#define SPI_CSR_SCBR_Pos _U_(8) /**< (SPI_CSR) Serial Clock Bit Rate Position */ +#define SPI_CSR_SCBR_Msk (_U_(0xFF) << SPI_CSR_SCBR_Pos) /**< (SPI_CSR) Serial Clock Bit Rate Mask */ +#define SPI_CSR_SCBR(value) (SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)) +#define SPI_CSR_DLYBS_Pos _U_(16) /**< (SPI_CSR) Delay Before SPCK Position */ +#define SPI_CSR_DLYBS_Msk (_U_(0xFF) << SPI_CSR_DLYBS_Pos) /**< (SPI_CSR) Delay Before SPCK Mask */ +#define SPI_CSR_DLYBS(value) (SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)) +#define SPI_CSR_DLYBCT_Pos _U_(24) /**< (SPI_CSR) Delay Between Consecutive Transfers Position */ +#define SPI_CSR_DLYBCT_Msk (_U_(0xFF) << SPI_CSR_DLYBCT_Pos) /**< (SPI_CSR) Delay Between Consecutive Transfers Mask */ +#define SPI_CSR_DLYBCT(value) (SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)) +#define SPI_CSR_Msk _U_(0xFFFFFFFF) /**< (SPI_CSR) Register Mask */ + + +/* -------- SPI_WPMR : (SPI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN_Pos _U_(0) /**< (SPI_WPMR) Write Protection Enable Position */ +#define SPI_WPMR_WPEN_Msk (_U_(0x1) << SPI_WPMR_WPEN_Pos) /**< (SPI_WPMR) Write Protection Enable Mask */ +#define SPI_WPMR_WPEN(value) (SPI_WPMR_WPEN_Msk & ((value) << SPI_WPMR_WPEN_Pos)) +#define SPI_WPMR_WPKEY_Pos _U_(8) /**< (SPI_WPMR) Write Protection Key Position */ +#define SPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Write Protection Key Mask */ +#define SPI_WPMR_WPKEY(value) (SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)) +#define SPI_WPMR_WPKEY_PASSWD_Val _U_(0x535049) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SPI_WPMR_WPKEY_PASSWD (SPI_WPMR_WPKEY_PASSWD_Val << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SPI_WPMR_Msk _U_(0xFFFFFF01) /**< (SPI_WPMR) Register Mask */ + + +/* -------- SPI_WPSR : (SPI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS_Pos _U_(0) /**< (SPI_WPSR) Write Protection Violation Status Position */ +#define SPI_WPSR_WPVS_Msk (_U_(0x1) << SPI_WPSR_WPVS_Pos) /**< (SPI_WPSR) Write Protection Violation Status Mask */ +#define SPI_WPSR_WPVS(value) (SPI_WPSR_WPVS_Msk & ((value) << SPI_WPSR_WPVS_Pos)) +#define SPI_WPSR_WPVSRC_Pos _U_(8) /**< (SPI_WPSR) Write Protection Violation Source Position */ +#define SPI_WPSR_WPVSRC_Msk (_U_(0xFF) << SPI_WPSR_WPVSRC_Pos) /**< (SPI_WPSR) Write Protection Violation Source Mask */ +#define SPI_WPSR_WPVSRC(value) (SPI_WPSR_WPVSRC_Msk & ((value) << SPI_WPSR_WPVSRC_Pos)) +#define SPI_WPSR_Msk _U_(0x0000FF01) /**< (SPI_WPSR) Register Mask */ + + +/** \brief SPI register offsets definitions */ +#define SPI_CR_REG_OFST (0x00) /**< (SPI_CR) Control Register Offset */ +#define SPI_MR_REG_OFST (0x04) /**< (SPI_MR) Mode Register Offset */ +#define SPI_RDR_REG_OFST (0x08) /**< (SPI_RDR) Receive Data Register Offset */ +#define SPI_TDR_REG_OFST (0x0C) /**< (SPI_TDR) Transmit Data Register Offset */ +#define SPI_SR_REG_OFST (0x10) /**< (SPI_SR) Status Register Offset */ +#define SPI_IER_REG_OFST (0x14) /**< (SPI_IER) Interrupt Enable Register Offset */ +#define SPI_IDR_REG_OFST (0x18) /**< (SPI_IDR) Interrupt Disable Register Offset */ +#define SPI_IMR_REG_OFST (0x1C) /**< (SPI_IMR) Interrupt Mask Register Offset */ +#define SPI_CSR_REG_OFST (0x30) /**< (SPI_CSR) Chip Select Register 0 Offset */ +#define SPI_WPMR_REG_OFST (0xE4) /**< (SPI_WPMR) Write Protection Mode Register Offset */ +#define SPI_WPSR_REG_OFST (0xE8) /**< (SPI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SPI register API structure */ +typedef struct +{ + __O uint32_t SPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t SPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t SPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O uint32_t SPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I uint32_t SPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O uint32_t SPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved1[0x10]; + __IO uint32_t SPI_CSR[4]; /**< Offset: 0x30 (R/W 32) Chip Select Register 0 */ + __I uint8_t Reserved2[0xA4]; + __IO uint32_t SPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} spi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SPI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/ssc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/ssc.h new file mode 100644 index 00000000..7d5f1aaa --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/ssc.h @@ -0,0 +1,514 @@ +/** + * \brief Component description for SSC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_SSC_COMPONENT_H_ +#define _SAME70_SSC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SSC */ +/* ************************************************************************** */ + +/* -------- SSC_CR : (SSC Offset: 0x00) ( /W 32) Control Register -------- */ +#define SSC_CR_RXEN_Pos _U_(0) /**< (SSC_CR) Receive Enable Position */ +#define SSC_CR_RXEN_Msk (_U_(0x1) << SSC_CR_RXEN_Pos) /**< (SSC_CR) Receive Enable Mask */ +#define SSC_CR_RXEN(value) (SSC_CR_RXEN_Msk & ((value) << SSC_CR_RXEN_Pos)) +#define SSC_CR_RXDIS_Pos _U_(1) /**< (SSC_CR) Receive Disable Position */ +#define SSC_CR_RXDIS_Msk (_U_(0x1) << SSC_CR_RXDIS_Pos) /**< (SSC_CR) Receive Disable Mask */ +#define SSC_CR_RXDIS(value) (SSC_CR_RXDIS_Msk & ((value) << SSC_CR_RXDIS_Pos)) +#define SSC_CR_TXEN_Pos _U_(8) /**< (SSC_CR) Transmit Enable Position */ +#define SSC_CR_TXEN_Msk (_U_(0x1) << SSC_CR_TXEN_Pos) /**< (SSC_CR) Transmit Enable Mask */ +#define SSC_CR_TXEN(value) (SSC_CR_TXEN_Msk & ((value) << SSC_CR_TXEN_Pos)) +#define SSC_CR_TXDIS_Pos _U_(9) /**< (SSC_CR) Transmit Disable Position */ +#define SSC_CR_TXDIS_Msk (_U_(0x1) << SSC_CR_TXDIS_Pos) /**< (SSC_CR) Transmit Disable Mask */ +#define SSC_CR_TXDIS(value) (SSC_CR_TXDIS_Msk & ((value) << SSC_CR_TXDIS_Pos)) +#define SSC_CR_SWRST_Pos _U_(15) /**< (SSC_CR) Software Reset Position */ +#define SSC_CR_SWRST_Msk (_U_(0x1) << SSC_CR_SWRST_Pos) /**< (SSC_CR) Software Reset Mask */ +#define SSC_CR_SWRST(value) (SSC_CR_SWRST_Msk & ((value) << SSC_CR_SWRST_Pos)) +#define SSC_CR_Msk _U_(0x00008303) /**< (SSC_CR) Register Mask */ + + +/* -------- SSC_CMR : (SSC Offset: 0x04) (R/W 32) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos _U_(0) /**< (SSC_CMR) Clock Divider Position */ +#define SSC_CMR_DIV_Msk (_U_(0xFFF) << SSC_CMR_DIV_Pos) /**< (SSC_CMR) Clock Divider Mask */ +#define SSC_CMR_DIV(value) (SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)) +#define SSC_CMR_Msk _U_(0x00000FFF) /**< (SSC_CMR) Register Mask */ + + +/* -------- SSC_RCMR : (SSC Offset: 0x10) (R/W 32) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos _U_(0) /**< (SSC_RCMR) Receive Clock Selection Position */ +#define SSC_RCMR_CKS_Msk (_U_(0x3) << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Receive Clock Selection Mask */ +#define SSC_RCMR_CKS(value) (SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)) +#define SSC_RCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK_Val _U_(0x1) /**< (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK_Val _U_(0x2) /**< (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKS_MCK (SSC_RCMR_CKS_MCK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Divided Clock Position */ +#define SSC_RCMR_CKS_TK (SSC_RCMR_CKS_TK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) TK Clock signal Position */ +#define SSC_RCMR_CKS_RK (SSC_RCMR_CKS_RK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) RK pin Position */ +#define SSC_RCMR_CKO_Pos _U_(2) /**< (SSC_RCMR) Receive Clock Output Mode Selection Position */ +#define SSC_RCMR_CKO_Msk (_U_(0x7) << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock Output Mode Selection Mask */ +#define SSC_RCMR_CKO(value) (SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)) +#define SSC_RCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKO_NONE (SSC_RCMR_CKO_NONE_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) None, RK pin is an input Position */ +#define SSC_RCMR_CKO_CONTINUOUS (SSC_RCMR_CKO_CONTINUOUS_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output Position */ +#define SSC_RCMR_CKO_TRANSFER (SSC_RCMR_CKO_TRANSFER_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output Position */ +#define SSC_RCMR_CKI_Pos _U_(5) /**< (SSC_RCMR) Receive Clock Inversion Position */ +#define SSC_RCMR_CKI_Msk (_U_(0x1) << SSC_RCMR_CKI_Pos) /**< (SSC_RCMR) Receive Clock Inversion Mask */ +#define SSC_RCMR_CKI(value) (SSC_RCMR_CKI_Msk & ((value) << SSC_RCMR_CKI_Pos)) +#define SSC_RCMR_CKG_Pos _U_(6) /**< (SSC_RCMR) Receive Clock Gating Selection Position */ +#define SSC_RCMR_CKG_Msk (_U_(0x3) << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock Gating Selection Mask */ +#define SSC_RCMR_CKG(value) (SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)) +#define SSC_RCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW_Val _U_(0x1) /**< (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_CKG_CONTINUOUS (SSC_RCMR_CKG_CONTINUOUS_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) None Position */ +#define SSC_RCMR_CKG_EN_RF_LOW (SSC_RCMR_CKG_EN_RF_LOW_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF Low Position */ +#define SSC_RCMR_CKG_EN_RF_HIGH (SSC_RCMR_CKG_EN_RF_HIGH_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF High Position */ +#define SSC_RCMR_START_Pos _U_(8) /**< (SSC_RCMR) Receive Start Selection Position */ +#define SSC_RCMR_START_Msk (_U_(0xF) << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Receive Start Selection Mask */ +#define SSC_RCMR_START(value) (SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)) +#define SSC_RCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT_Val _U_(0x1) /**< (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW_Val _U_(0x2) /**< (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH_Val _U_(0x3) /**< (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING_Val _U_(0x4) /**< (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING_Val _U_(0x5) /**< (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL_Val _U_(0x6) /**< (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE_Val _U_(0x7) /**< (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0_Val _U_(0x8) /**< (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_START_CONTINUOUS (SSC_RCMR_START_CONTINUOUS_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Position */ +#define SSC_RCMR_START_TRANSMIT (SSC_RCMR_START_TRANSMIT_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Transmit start Position */ +#define SSC_RCMR_START_RF_LOW (SSC_RCMR_START_RF_LOW_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a low level on RF signal Position */ +#define SSC_RCMR_START_RF_HIGH (SSC_RCMR_START_RF_HIGH_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a high level on RF signal Position */ +#define SSC_RCMR_START_RF_FALLING (SSC_RCMR_START_RF_FALLING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a falling edge on RF signal Position */ +#define SSC_RCMR_START_RF_RISING (SSC_RCMR_START_RF_RISING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a rising edge on RF signal Position */ +#define SSC_RCMR_START_RF_LEVEL (SSC_RCMR_START_RF_LEVEL_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any level change on RF signal Position */ +#define SSC_RCMR_START_RF_EDGE (SSC_RCMR_START_RF_EDGE_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any edge on RF signal Position */ +#define SSC_RCMR_START_CMP_0 (SSC_RCMR_START_CMP_0_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Compare 0 Position */ +#define SSC_RCMR_STOP_Pos _U_(12) /**< (SSC_RCMR) Receive Stop Selection Position */ +#define SSC_RCMR_STOP_Msk (_U_(0x1) << SSC_RCMR_STOP_Pos) /**< (SSC_RCMR) Receive Stop Selection Mask */ +#define SSC_RCMR_STOP(value) (SSC_RCMR_STOP_Msk & ((value) << SSC_RCMR_STOP_Pos)) +#define SSC_RCMR_STTDLY_Pos _U_(16) /**< (SSC_RCMR) Receive Start Delay Position */ +#define SSC_RCMR_STTDLY_Msk (_U_(0xFF) << SSC_RCMR_STTDLY_Pos) /**< (SSC_RCMR) Receive Start Delay Mask */ +#define SSC_RCMR_STTDLY(value) (SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)) +#define SSC_RCMR_PERIOD_Pos _U_(24) /**< (SSC_RCMR) Receive Period Divider Selection Position */ +#define SSC_RCMR_PERIOD_Msk (_U_(0xFF) << SSC_RCMR_PERIOD_Pos) /**< (SSC_RCMR) Receive Period Divider Selection Mask */ +#define SSC_RCMR_PERIOD(value) (SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)) +#define SSC_RCMR_Msk _U_(0xFFFF1FFF) /**< (SSC_RCMR) Register Mask */ + + +/* -------- SSC_RFMR : (SSC Offset: 0x14) (R/W 32) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos _U_(0) /**< (SSC_RFMR) Data Length Position */ +#define SSC_RFMR_DATLEN_Msk (_U_(0x1F) << SSC_RFMR_DATLEN_Pos) /**< (SSC_RFMR) Data Length Mask */ +#define SSC_RFMR_DATLEN(value) (SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)) +#define SSC_RFMR_LOOP_Pos _U_(5) /**< (SSC_RFMR) Loop Mode Position */ +#define SSC_RFMR_LOOP_Msk (_U_(0x1) << SSC_RFMR_LOOP_Pos) /**< (SSC_RFMR) Loop Mode Mask */ +#define SSC_RFMR_LOOP(value) (SSC_RFMR_LOOP_Msk & ((value) << SSC_RFMR_LOOP_Pos)) +#define SSC_RFMR_MSBF_Pos _U_(7) /**< (SSC_RFMR) Most Significant Bit First Position */ +#define SSC_RFMR_MSBF_Msk (_U_(0x1) << SSC_RFMR_MSBF_Pos) /**< (SSC_RFMR) Most Significant Bit First Mask */ +#define SSC_RFMR_MSBF(value) (SSC_RFMR_MSBF_Msk & ((value) << SSC_RFMR_MSBF_Pos)) +#define SSC_RFMR_DATNB_Pos _U_(8) /**< (SSC_RFMR) Data Number per Frame Position */ +#define SSC_RFMR_DATNB_Msk (_U_(0xF) << SSC_RFMR_DATNB_Pos) /**< (SSC_RFMR) Data Number per Frame Mask */ +#define SSC_RFMR_DATNB(value) (SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)) +#define SSC_RFMR_FSLEN_Pos _U_(16) /**< (SSC_RFMR) Receive Frame Sync Length Position */ +#define SSC_RFMR_FSLEN_Msk (_U_(0xF) << SSC_RFMR_FSLEN_Pos) /**< (SSC_RFMR) Receive Frame Sync Length Mask */ +#define SSC_RFMR_FSLEN(value) (SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)) +#define SSC_RFMR_FSOS_Pos _U_(20) /**< (SSC_RFMR) Receive Frame Sync Output Selection Position */ +#define SSC_RFMR_FSOS_Msk (_U_(0x7) << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Receive Frame Sync Output Selection Mask */ +#define SSC_RFMR_FSOS(value) (SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)) +#define SSC_RFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_NONE (SSC_RFMR_FSOS_NONE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) None, RF pin is an input Position */ +#define SSC_RFMR_FSOS_NEGATIVE (SSC_RFMR_FSOS_NEGATIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Negative Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_POSITIVE (SSC_RFMR_FSOS_POSITIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Positive Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_LOW (SSC_RFMR_FSOS_LOW_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_HIGH (SSC_RFMR_FSOS_HIGH_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_TOGGLING (SSC_RFMR_FSOS_TOGGLING_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSEDGE_Pos _U_(24) /**< (SSC_RFMR) Frame Sync Edge Detection Position */ +#define SSC_RFMR_FSEDGE_Msk (_U_(0x1) << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Frame Sync Edge Detection Mask */ +#define SSC_RFMR_FSEDGE(value) (SSC_RFMR_FSEDGE_Msk & ((value) << SSC_RFMR_FSEDGE_Pos)) +#define SSC_RFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (SSC_RFMR_FSEDGE_POSITIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Positive Edge Detection Position */ +#define SSC_RFMR_FSEDGE_NEGATIVE (SSC_RFMR_FSEDGE_NEGATIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Negative Edge Detection Position */ +#define SSC_RFMR_FSLEN_EXT_Pos _U_(28) /**< (SSC_RFMR) FSLEN Field Extension Position */ +#define SSC_RFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_RFMR_FSLEN_EXT_Pos) /**< (SSC_RFMR) FSLEN Field Extension Mask */ +#define SSC_RFMR_FSLEN_EXT(value) (SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)) +#define SSC_RFMR_Msk _U_(0xF17F0FBF) /**< (SSC_RFMR) Register Mask */ + + +/* -------- SSC_TCMR : (SSC Offset: 0x18) (R/W 32) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos _U_(0) /**< (SSC_TCMR) Transmit Clock Selection Position */ +#define SSC_TCMR_CKS_Msk (_U_(0x3) << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Transmit Clock Selection Mask */ +#define SSC_TCMR_CKS(value) (SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)) +#define SSC_TCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK_Val _U_(0x1) /**< (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK_Val _U_(0x2) /**< (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKS_MCK (SSC_TCMR_CKS_MCK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Divided Clock Position */ +#define SSC_TCMR_CKS_RK (SSC_TCMR_CKS_RK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) RK Clock signal Position */ +#define SSC_TCMR_CKS_TK (SSC_TCMR_CKS_TK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) TK pin Position */ +#define SSC_TCMR_CKO_Pos _U_(2) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Position */ +#define SSC_TCMR_CKO_Msk (_U_(0x7) << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Mask */ +#define SSC_TCMR_CKO(value) (SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)) +#define SSC_TCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKO_NONE (SSC_TCMR_CKO_NONE_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) None, TK pin is an input Position */ +#define SSC_TCMR_CKO_CONTINUOUS (SSC_TCMR_CKO_CONTINUOUS_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output Position */ +#define SSC_TCMR_CKO_TRANSFER (SSC_TCMR_CKO_TRANSFER_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output Position */ +#define SSC_TCMR_CKI_Pos _U_(5) /**< (SSC_TCMR) Transmit Clock Inversion Position */ +#define SSC_TCMR_CKI_Msk (_U_(0x1) << SSC_TCMR_CKI_Pos) /**< (SSC_TCMR) Transmit Clock Inversion Mask */ +#define SSC_TCMR_CKI(value) (SSC_TCMR_CKI_Msk & ((value) << SSC_TCMR_CKI_Pos)) +#define SSC_TCMR_CKG_Pos _U_(6) /**< (SSC_TCMR) Transmit Clock Gating Selection Position */ +#define SSC_TCMR_CKG_Msk (_U_(0x3) << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock Gating Selection Mask */ +#define SSC_TCMR_CKG(value) (SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)) +#define SSC_TCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW_Val _U_(0x1) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_CKG_CONTINUOUS (SSC_TCMR_CKG_CONTINUOUS_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) None Position */ +#define SSC_TCMR_CKG_EN_TF_LOW (SSC_TCMR_CKG_EN_TF_LOW_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low Position */ +#define SSC_TCMR_CKG_EN_TF_HIGH (SSC_TCMR_CKG_EN_TF_HIGH_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF High Position */ +#define SSC_TCMR_START_Pos _U_(8) /**< (SSC_TCMR) Transmit Start Selection Position */ +#define SSC_TCMR_START_Msk (_U_(0xF) << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Transmit Start Selection Mask */ +#define SSC_TCMR_START(value) (SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)) +#define SSC_TCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE_Val _U_(0x1) /**< (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW_Val _U_(0x2) /**< (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH_Val _U_(0x3) /**< (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING_Val _U_(0x4) /**< (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING_Val _U_(0x5) /**< (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL_Val _U_(0x6) /**< (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE_Val _U_(0x7) /**< (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CONTINUOUS (SSC_TCMR_START_CONTINUOUS_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data Position */ +#define SSC_TCMR_START_RECEIVE (SSC_TCMR_START_RECEIVE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Receive start Position */ +#define SSC_TCMR_START_TF_LOW (SSC_TCMR_START_TF_LOW_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a low level on TF signal Position */ +#define SSC_TCMR_START_TF_HIGH (SSC_TCMR_START_TF_HIGH_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a high level on TF signal Position */ +#define SSC_TCMR_START_TF_FALLING (SSC_TCMR_START_TF_FALLING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a falling edge on TF signal Position */ +#define SSC_TCMR_START_TF_RISING (SSC_TCMR_START_TF_RISING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a rising edge on TF signal Position */ +#define SSC_TCMR_START_TF_LEVEL (SSC_TCMR_START_TF_LEVEL_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any level change on TF signal Position */ +#define SSC_TCMR_START_TF_EDGE (SSC_TCMR_START_TF_EDGE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any edge on TF signal Position */ +#define SSC_TCMR_STTDLY_Pos _U_(16) /**< (SSC_TCMR) Transmit Start Delay Position */ +#define SSC_TCMR_STTDLY_Msk (_U_(0xFF) << SSC_TCMR_STTDLY_Pos) /**< (SSC_TCMR) Transmit Start Delay Mask */ +#define SSC_TCMR_STTDLY(value) (SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)) +#define SSC_TCMR_PERIOD_Pos _U_(24) /**< (SSC_TCMR) Transmit Period Divider Selection Position */ +#define SSC_TCMR_PERIOD_Msk (_U_(0xFF) << SSC_TCMR_PERIOD_Pos) /**< (SSC_TCMR) Transmit Period Divider Selection Mask */ +#define SSC_TCMR_PERIOD(value) (SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)) +#define SSC_TCMR_Msk _U_(0xFFFF0FFF) /**< (SSC_TCMR) Register Mask */ + + +/* -------- SSC_TFMR : (SSC Offset: 0x1C) (R/W 32) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos _U_(0) /**< (SSC_TFMR) Data Length Position */ +#define SSC_TFMR_DATLEN_Msk (_U_(0x1F) << SSC_TFMR_DATLEN_Pos) /**< (SSC_TFMR) Data Length Mask */ +#define SSC_TFMR_DATLEN(value) (SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)) +#define SSC_TFMR_DATDEF_Pos _U_(5) /**< (SSC_TFMR) Data Default Value Position */ +#define SSC_TFMR_DATDEF_Msk (_U_(0x1) << SSC_TFMR_DATDEF_Pos) /**< (SSC_TFMR) Data Default Value Mask */ +#define SSC_TFMR_DATDEF(value) (SSC_TFMR_DATDEF_Msk & ((value) << SSC_TFMR_DATDEF_Pos)) +#define SSC_TFMR_MSBF_Pos _U_(7) /**< (SSC_TFMR) Most Significant Bit First Position */ +#define SSC_TFMR_MSBF_Msk (_U_(0x1) << SSC_TFMR_MSBF_Pos) /**< (SSC_TFMR) Most Significant Bit First Mask */ +#define SSC_TFMR_MSBF(value) (SSC_TFMR_MSBF_Msk & ((value) << SSC_TFMR_MSBF_Pos)) +#define SSC_TFMR_DATNB_Pos _U_(8) /**< (SSC_TFMR) Data Number per Frame Position */ +#define SSC_TFMR_DATNB_Msk (_U_(0xF) << SSC_TFMR_DATNB_Pos) /**< (SSC_TFMR) Data Number per Frame Mask */ +#define SSC_TFMR_DATNB(value) (SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)) +#define SSC_TFMR_FSLEN_Pos _U_(16) /**< (SSC_TFMR) Transmit Frame Sync Length Position */ +#define SSC_TFMR_FSLEN_Msk (_U_(0xF) << SSC_TFMR_FSLEN_Pos) /**< (SSC_TFMR) Transmit Frame Sync Length Mask */ +#define SSC_TFMR_FSLEN(value) (SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)) +#define SSC_TFMR_FSOS_Pos _U_(20) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Position */ +#define SSC_TFMR_FSOS_Msk (_U_(0x7) << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Mask */ +#define SSC_TFMR_FSOS(value) (SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)) +#define SSC_TFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSOS_NONE (SSC_TFMR_FSOS_NONE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) None, TF pin is an input Position */ +#define SSC_TFMR_FSOS_NEGATIVE (SSC_TFMR_FSOS_NEGATIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Negative Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_POSITIVE (SSC_TFMR_FSOS_POSITIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Positive Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_LOW (SSC_TFMR_FSOS_LOW_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven Low during data transfer Position */ +#define SSC_TFMR_FSOS_HIGH (SSC_TFMR_FSOS_HIGH_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven High during data transfer Position */ +#define SSC_TFMR_FSOS_TOGGLING (SSC_TFMR_FSOS_TOGGLING_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Toggling at each start of data transfer Position */ +#define SSC_TFMR_FSDEN_Pos _U_(23) /**< (SSC_TFMR) Frame Sync Data Enable Position */ +#define SSC_TFMR_FSDEN_Msk (_U_(0x1) << SSC_TFMR_FSDEN_Pos) /**< (SSC_TFMR) Frame Sync Data Enable Mask */ +#define SSC_TFMR_FSDEN(value) (SSC_TFMR_FSDEN_Msk & ((value) << SSC_TFMR_FSDEN_Pos)) +#define SSC_TFMR_FSEDGE_Pos _U_(24) /**< (SSC_TFMR) Frame Sync Edge Detection Position */ +#define SSC_TFMR_FSEDGE_Msk (_U_(0x1) << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Frame Sync Edge Detection Mask */ +#define SSC_TFMR_FSEDGE(value) (SSC_TFMR_FSEDGE_Msk & ((value) << SSC_TFMR_FSEDGE_Pos)) +#define SSC_TFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (SSC_TFMR_FSEDGE_POSITIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Positive Edge Detection Position */ +#define SSC_TFMR_FSEDGE_NEGATIVE (SSC_TFMR_FSEDGE_NEGATIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Negative Edge Detection Position */ +#define SSC_TFMR_FSLEN_EXT_Pos _U_(28) /**< (SSC_TFMR) FSLEN Field Extension Position */ +#define SSC_TFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_TFMR_FSLEN_EXT_Pos) /**< (SSC_TFMR) FSLEN Field Extension Mask */ +#define SSC_TFMR_FSLEN_EXT(value) (SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)) +#define SSC_TFMR_Msk _U_(0xF1FF0FBF) /**< (SSC_TFMR) Register Mask */ + + +/* -------- SSC_RHR : (SSC Offset: 0x20) ( R/ 32) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos _U_(0) /**< (SSC_RHR) Receive Data Position */ +#define SSC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << SSC_RHR_RDAT_Pos) /**< (SSC_RHR) Receive Data Mask */ +#define SSC_RHR_RDAT(value) (SSC_RHR_RDAT_Msk & ((value) << SSC_RHR_RDAT_Pos)) +#define SSC_RHR_Msk _U_(0xFFFFFFFF) /**< (SSC_RHR) Register Mask */ + + +/* -------- SSC_THR : (SSC Offset: 0x24) ( /W 32) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos _U_(0) /**< (SSC_THR) Transmit Data Position */ +#define SSC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << SSC_THR_TDAT_Pos) /**< (SSC_THR) Transmit Data Mask */ +#define SSC_THR_TDAT(value) (SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)) +#define SSC_THR_Msk _U_(0xFFFFFFFF) /**< (SSC_THR) Register Mask */ + + +/* -------- SSC_RSHR : (SSC Offset: 0x30) ( R/ 32) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos _U_(0) /**< (SSC_RSHR) Receive Synchronization Data Position */ +#define SSC_RSHR_RSDAT_Msk (_U_(0xFFFF) << SSC_RSHR_RSDAT_Pos) /**< (SSC_RSHR) Receive Synchronization Data Mask */ +#define SSC_RSHR_RSDAT(value) (SSC_RSHR_RSDAT_Msk & ((value) << SSC_RSHR_RSDAT_Pos)) +#define SSC_RSHR_Msk _U_(0x0000FFFF) /**< (SSC_RSHR) Register Mask */ + + +/* -------- SSC_TSHR : (SSC Offset: 0x34) (R/W 32) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos _U_(0) /**< (SSC_TSHR) Transmit Synchronization Data Position */ +#define SSC_TSHR_TSDAT_Msk (_U_(0xFFFF) << SSC_TSHR_TSDAT_Pos) /**< (SSC_TSHR) Transmit Synchronization Data Mask */ +#define SSC_TSHR_TSDAT(value) (SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)) +#define SSC_TSHR_Msk _U_(0x0000FFFF) /**< (SSC_TSHR) Register Mask */ + + +/* -------- SSC_RC0R : (SSC Offset: 0x38) (R/W 32) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos _U_(0) /**< (SSC_RC0R) Receive Compare Data 0 Position */ +#define SSC_RC0R_CP0_Msk (_U_(0xFFFF) << SSC_RC0R_CP0_Pos) /**< (SSC_RC0R) Receive Compare Data 0 Mask */ +#define SSC_RC0R_CP0(value) (SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)) +#define SSC_RC0R_Msk _U_(0x0000FFFF) /**< (SSC_RC0R) Register Mask */ + + +/* -------- SSC_RC1R : (SSC Offset: 0x3C) (R/W 32) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos _U_(0) /**< (SSC_RC1R) Receive Compare Data 1 Position */ +#define SSC_RC1R_CP1_Msk (_U_(0xFFFF) << SSC_RC1R_CP1_Pos) /**< (SSC_RC1R) Receive Compare Data 1 Mask */ +#define SSC_RC1R_CP1(value) (SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)) +#define SSC_RC1R_Msk _U_(0x0000FFFF) /**< (SSC_RC1R) Register Mask */ + + +/* -------- SSC_SR : (SSC Offset: 0x40) ( R/ 32) Status Register -------- */ +#define SSC_SR_TXRDY_Pos _U_(0) /**< (SSC_SR) Transmit Ready Position */ +#define SSC_SR_TXRDY_Msk (_U_(0x1) << SSC_SR_TXRDY_Pos) /**< (SSC_SR) Transmit Ready Mask */ +#define SSC_SR_TXRDY(value) (SSC_SR_TXRDY_Msk & ((value) << SSC_SR_TXRDY_Pos)) +#define SSC_SR_TXEMPTY_Pos _U_(1) /**< (SSC_SR) Transmit Empty Position */ +#define SSC_SR_TXEMPTY_Msk (_U_(0x1) << SSC_SR_TXEMPTY_Pos) /**< (SSC_SR) Transmit Empty Mask */ +#define SSC_SR_TXEMPTY(value) (SSC_SR_TXEMPTY_Msk & ((value) << SSC_SR_TXEMPTY_Pos)) +#define SSC_SR_RXRDY_Pos _U_(4) /**< (SSC_SR) Receive Ready Position */ +#define SSC_SR_RXRDY_Msk (_U_(0x1) << SSC_SR_RXRDY_Pos) /**< (SSC_SR) Receive Ready Mask */ +#define SSC_SR_RXRDY(value) (SSC_SR_RXRDY_Msk & ((value) << SSC_SR_RXRDY_Pos)) +#define SSC_SR_OVRUN_Pos _U_(5) /**< (SSC_SR) Receive Overrun Position */ +#define SSC_SR_OVRUN_Msk (_U_(0x1) << SSC_SR_OVRUN_Pos) /**< (SSC_SR) Receive Overrun Mask */ +#define SSC_SR_OVRUN(value) (SSC_SR_OVRUN_Msk & ((value) << SSC_SR_OVRUN_Pos)) +#define SSC_SR_CP0_Pos _U_(8) /**< (SSC_SR) Compare 0 Position */ +#define SSC_SR_CP0_Msk (_U_(0x1) << SSC_SR_CP0_Pos) /**< (SSC_SR) Compare 0 Mask */ +#define SSC_SR_CP0(value) (SSC_SR_CP0_Msk & ((value) << SSC_SR_CP0_Pos)) +#define SSC_SR_CP1_Pos _U_(9) /**< (SSC_SR) Compare 1 Position */ +#define SSC_SR_CP1_Msk (_U_(0x1) << SSC_SR_CP1_Pos) /**< (SSC_SR) Compare 1 Mask */ +#define SSC_SR_CP1(value) (SSC_SR_CP1_Msk & ((value) << SSC_SR_CP1_Pos)) +#define SSC_SR_TXSYN_Pos _U_(10) /**< (SSC_SR) Transmit Sync Position */ +#define SSC_SR_TXSYN_Msk (_U_(0x1) << SSC_SR_TXSYN_Pos) /**< (SSC_SR) Transmit Sync Mask */ +#define SSC_SR_TXSYN(value) (SSC_SR_TXSYN_Msk & ((value) << SSC_SR_TXSYN_Pos)) +#define SSC_SR_RXSYN_Pos _U_(11) /**< (SSC_SR) Receive Sync Position */ +#define SSC_SR_RXSYN_Msk (_U_(0x1) << SSC_SR_RXSYN_Pos) /**< (SSC_SR) Receive Sync Mask */ +#define SSC_SR_RXSYN(value) (SSC_SR_RXSYN_Msk & ((value) << SSC_SR_RXSYN_Pos)) +#define SSC_SR_TXEN_Pos _U_(16) /**< (SSC_SR) Transmit Enable Position */ +#define SSC_SR_TXEN_Msk (_U_(0x1) << SSC_SR_TXEN_Pos) /**< (SSC_SR) Transmit Enable Mask */ +#define SSC_SR_TXEN(value) (SSC_SR_TXEN_Msk & ((value) << SSC_SR_TXEN_Pos)) +#define SSC_SR_RXEN_Pos _U_(17) /**< (SSC_SR) Receive Enable Position */ +#define SSC_SR_RXEN_Msk (_U_(0x1) << SSC_SR_RXEN_Pos) /**< (SSC_SR) Receive Enable Mask */ +#define SSC_SR_RXEN(value) (SSC_SR_RXEN_Msk & ((value) << SSC_SR_RXEN_Pos)) +#define SSC_SR_Msk _U_(0x00030F33) /**< (SSC_SR) Register Mask */ + +#define SSC_SR_CP_Pos _U_(8) /**< (SSC_SR Position) Compare x */ +#define SSC_SR_CP_Msk (_U_(0x3) << SSC_SR_CP_Pos) /**< (SSC_SR Mask) CP */ +#define SSC_SR_CP(value) (SSC_SR_CP_Msk & ((value) << SSC_SR_CP_Pos)) + +/* -------- SSC_IER : (SSC Offset: 0x44) ( /W 32) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY_Pos _U_(0) /**< (SSC_IER) Transmit Ready Interrupt Enable Position */ +#define SSC_IER_TXRDY_Msk (_U_(0x1) << SSC_IER_TXRDY_Pos) /**< (SSC_IER) Transmit Ready Interrupt Enable Mask */ +#define SSC_IER_TXRDY(value) (SSC_IER_TXRDY_Msk & ((value) << SSC_IER_TXRDY_Pos)) +#define SSC_IER_TXEMPTY_Pos _U_(1) /**< (SSC_IER) Transmit Empty Interrupt Enable Position */ +#define SSC_IER_TXEMPTY_Msk (_U_(0x1) << SSC_IER_TXEMPTY_Pos) /**< (SSC_IER) Transmit Empty Interrupt Enable Mask */ +#define SSC_IER_TXEMPTY(value) (SSC_IER_TXEMPTY_Msk & ((value) << SSC_IER_TXEMPTY_Pos)) +#define SSC_IER_RXRDY_Pos _U_(4) /**< (SSC_IER) Receive Ready Interrupt Enable Position */ +#define SSC_IER_RXRDY_Msk (_U_(0x1) << SSC_IER_RXRDY_Pos) /**< (SSC_IER) Receive Ready Interrupt Enable Mask */ +#define SSC_IER_RXRDY(value) (SSC_IER_RXRDY_Msk & ((value) << SSC_IER_RXRDY_Pos)) +#define SSC_IER_OVRUN_Pos _U_(5) /**< (SSC_IER) Receive Overrun Interrupt Enable Position */ +#define SSC_IER_OVRUN_Msk (_U_(0x1) << SSC_IER_OVRUN_Pos) /**< (SSC_IER) Receive Overrun Interrupt Enable Mask */ +#define SSC_IER_OVRUN(value) (SSC_IER_OVRUN_Msk & ((value) << SSC_IER_OVRUN_Pos)) +#define SSC_IER_CP0_Pos _U_(8) /**< (SSC_IER) Compare 0 Interrupt Enable Position */ +#define SSC_IER_CP0_Msk (_U_(0x1) << SSC_IER_CP0_Pos) /**< (SSC_IER) Compare 0 Interrupt Enable Mask */ +#define SSC_IER_CP0(value) (SSC_IER_CP0_Msk & ((value) << SSC_IER_CP0_Pos)) +#define SSC_IER_CP1_Pos _U_(9) /**< (SSC_IER) Compare 1 Interrupt Enable Position */ +#define SSC_IER_CP1_Msk (_U_(0x1) << SSC_IER_CP1_Pos) /**< (SSC_IER) Compare 1 Interrupt Enable Mask */ +#define SSC_IER_CP1(value) (SSC_IER_CP1_Msk & ((value) << SSC_IER_CP1_Pos)) +#define SSC_IER_TXSYN_Pos _U_(10) /**< (SSC_IER) Tx Sync Interrupt Enable Position */ +#define SSC_IER_TXSYN_Msk (_U_(0x1) << SSC_IER_TXSYN_Pos) /**< (SSC_IER) Tx Sync Interrupt Enable Mask */ +#define SSC_IER_TXSYN(value) (SSC_IER_TXSYN_Msk & ((value) << SSC_IER_TXSYN_Pos)) +#define SSC_IER_RXSYN_Pos _U_(11) /**< (SSC_IER) Rx Sync Interrupt Enable Position */ +#define SSC_IER_RXSYN_Msk (_U_(0x1) << SSC_IER_RXSYN_Pos) /**< (SSC_IER) Rx Sync Interrupt Enable Mask */ +#define SSC_IER_RXSYN(value) (SSC_IER_RXSYN_Msk & ((value) << SSC_IER_RXSYN_Pos)) +#define SSC_IER_Msk _U_(0x00000F33) /**< (SSC_IER) Register Mask */ + +#define SSC_IER_CP_Pos _U_(8) /**< (SSC_IER Position) Compare x Interrupt Enable */ +#define SSC_IER_CP_Msk (_U_(0x3) << SSC_IER_CP_Pos) /**< (SSC_IER Mask) CP */ +#define SSC_IER_CP(value) (SSC_IER_CP_Msk & ((value) << SSC_IER_CP_Pos)) + +/* -------- SSC_IDR : (SSC Offset: 0x48) ( /W 32) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY_Pos _U_(0) /**< (SSC_IDR) Transmit Ready Interrupt Disable Position */ +#define SSC_IDR_TXRDY_Msk (_U_(0x1) << SSC_IDR_TXRDY_Pos) /**< (SSC_IDR) Transmit Ready Interrupt Disable Mask */ +#define SSC_IDR_TXRDY(value) (SSC_IDR_TXRDY_Msk & ((value) << SSC_IDR_TXRDY_Pos)) +#define SSC_IDR_TXEMPTY_Pos _U_(1) /**< (SSC_IDR) Transmit Empty Interrupt Disable Position */ +#define SSC_IDR_TXEMPTY_Msk (_U_(0x1) << SSC_IDR_TXEMPTY_Pos) /**< (SSC_IDR) Transmit Empty Interrupt Disable Mask */ +#define SSC_IDR_TXEMPTY(value) (SSC_IDR_TXEMPTY_Msk & ((value) << SSC_IDR_TXEMPTY_Pos)) +#define SSC_IDR_RXRDY_Pos _U_(4) /**< (SSC_IDR) Receive Ready Interrupt Disable Position */ +#define SSC_IDR_RXRDY_Msk (_U_(0x1) << SSC_IDR_RXRDY_Pos) /**< (SSC_IDR) Receive Ready Interrupt Disable Mask */ +#define SSC_IDR_RXRDY(value) (SSC_IDR_RXRDY_Msk & ((value) << SSC_IDR_RXRDY_Pos)) +#define SSC_IDR_OVRUN_Pos _U_(5) /**< (SSC_IDR) Receive Overrun Interrupt Disable Position */ +#define SSC_IDR_OVRUN_Msk (_U_(0x1) << SSC_IDR_OVRUN_Pos) /**< (SSC_IDR) Receive Overrun Interrupt Disable Mask */ +#define SSC_IDR_OVRUN(value) (SSC_IDR_OVRUN_Msk & ((value) << SSC_IDR_OVRUN_Pos)) +#define SSC_IDR_CP0_Pos _U_(8) /**< (SSC_IDR) Compare 0 Interrupt Disable Position */ +#define SSC_IDR_CP0_Msk (_U_(0x1) << SSC_IDR_CP0_Pos) /**< (SSC_IDR) Compare 0 Interrupt Disable Mask */ +#define SSC_IDR_CP0(value) (SSC_IDR_CP0_Msk & ((value) << SSC_IDR_CP0_Pos)) +#define SSC_IDR_CP1_Pos _U_(9) /**< (SSC_IDR) Compare 1 Interrupt Disable Position */ +#define SSC_IDR_CP1_Msk (_U_(0x1) << SSC_IDR_CP1_Pos) /**< (SSC_IDR) Compare 1 Interrupt Disable Mask */ +#define SSC_IDR_CP1(value) (SSC_IDR_CP1_Msk & ((value) << SSC_IDR_CP1_Pos)) +#define SSC_IDR_TXSYN_Pos _U_(10) /**< (SSC_IDR) Tx Sync Interrupt Enable Position */ +#define SSC_IDR_TXSYN_Msk (_U_(0x1) << SSC_IDR_TXSYN_Pos) /**< (SSC_IDR) Tx Sync Interrupt Enable Mask */ +#define SSC_IDR_TXSYN(value) (SSC_IDR_TXSYN_Msk & ((value) << SSC_IDR_TXSYN_Pos)) +#define SSC_IDR_RXSYN_Pos _U_(11) /**< (SSC_IDR) Rx Sync Interrupt Enable Position */ +#define SSC_IDR_RXSYN_Msk (_U_(0x1) << SSC_IDR_RXSYN_Pos) /**< (SSC_IDR) Rx Sync Interrupt Enable Mask */ +#define SSC_IDR_RXSYN(value) (SSC_IDR_RXSYN_Msk & ((value) << SSC_IDR_RXSYN_Pos)) +#define SSC_IDR_Msk _U_(0x00000F33) /**< (SSC_IDR) Register Mask */ + +#define SSC_IDR_CP_Pos _U_(8) /**< (SSC_IDR Position) Compare x Interrupt Disable */ +#define SSC_IDR_CP_Msk (_U_(0x3) << SSC_IDR_CP_Pos) /**< (SSC_IDR Mask) CP */ +#define SSC_IDR_CP(value) (SSC_IDR_CP_Msk & ((value) << SSC_IDR_CP_Pos)) + +/* -------- SSC_IMR : (SSC Offset: 0x4C) ( R/ 32) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY_Pos _U_(0) /**< (SSC_IMR) Transmit Ready Interrupt Mask Position */ +#define SSC_IMR_TXRDY_Msk (_U_(0x1) << SSC_IMR_TXRDY_Pos) /**< (SSC_IMR) Transmit Ready Interrupt Mask Mask */ +#define SSC_IMR_TXRDY(value) (SSC_IMR_TXRDY_Msk & ((value) << SSC_IMR_TXRDY_Pos)) +#define SSC_IMR_TXEMPTY_Pos _U_(1) /**< (SSC_IMR) Transmit Empty Interrupt Mask Position */ +#define SSC_IMR_TXEMPTY_Msk (_U_(0x1) << SSC_IMR_TXEMPTY_Pos) /**< (SSC_IMR) Transmit Empty Interrupt Mask Mask */ +#define SSC_IMR_TXEMPTY(value) (SSC_IMR_TXEMPTY_Msk & ((value) << SSC_IMR_TXEMPTY_Pos)) +#define SSC_IMR_RXRDY_Pos _U_(4) /**< (SSC_IMR) Receive Ready Interrupt Mask Position */ +#define SSC_IMR_RXRDY_Msk (_U_(0x1) << SSC_IMR_RXRDY_Pos) /**< (SSC_IMR) Receive Ready Interrupt Mask Mask */ +#define SSC_IMR_RXRDY(value) (SSC_IMR_RXRDY_Msk & ((value) << SSC_IMR_RXRDY_Pos)) +#define SSC_IMR_OVRUN_Pos _U_(5) /**< (SSC_IMR) Receive Overrun Interrupt Mask Position */ +#define SSC_IMR_OVRUN_Msk (_U_(0x1) << SSC_IMR_OVRUN_Pos) /**< (SSC_IMR) Receive Overrun Interrupt Mask Mask */ +#define SSC_IMR_OVRUN(value) (SSC_IMR_OVRUN_Msk & ((value) << SSC_IMR_OVRUN_Pos)) +#define SSC_IMR_CP0_Pos _U_(8) /**< (SSC_IMR) Compare 0 Interrupt Mask Position */ +#define SSC_IMR_CP0_Msk (_U_(0x1) << SSC_IMR_CP0_Pos) /**< (SSC_IMR) Compare 0 Interrupt Mask Mask */ +#define SSC_IMR_CP0(value) (SSC_IMR_CP0_Msk & ((value) << SSC_IMR_CP0_Pos)) +#define SSC_IMR_CP1_Pos _U_(9) /**< (SSC_IMR) Compare 1 Interrupt Mask Position */ +#define SSC_IMR_CP1_Msk (_U_(0x1) << SSC_IMR_CP1_Pos) /**< (SSC_IMR) Compare 1 Interrupt Mask Mask */ +#define SSC_IMR_CP1(value) (SSC_IMR_CP1_Msk & ((value) << SSC_IMR_CP1_Pos)) +#define SSC_IMR_TXSYN_Pos _U_(10) /**< (SSC_IMR) Tx Sync Interrupt Mask Position */ +#define SSC_IMR_TXSYN_Msk (_U_(0x1) << SSC_IMR_TXSYN_Pos) /**< (SSC_IMR) Tx Sync Interrupt Mask Mask */ +#define SSC_IMR_TXSYN(value) (SSC_IMR_TXSYN_Msk & ((value) << SSC_IMR_TXSYN_Pos)) +#define SSC_IMR_RXSYN_Pos _U_(11) /**< (SSC_IMR) Rx Sync Interrupt Mask Position */ +#define SSC_IMR_RXSYN_Msk (_U_(0x1) << SSC_IMR_RXSYN_Pos) /**< (SSC_IMR) Rx Sync Interrupt Mask Mask */ +#define SSC_IMR_RXSYN(value) (SSC_IMR_RXSYN_Msk & ((value) << SSC_IMR_RXSYN_Pos)) +#define SSC_IMR_Msk _U_(0x00000F33) /**< (SSC_IMR) Register Mask */ + +#define SSC_IMR_CP_Pos _U_(8) /**< (SSC_IMR Position) Compare x Interrupt Mask */ +#define SSC_IMR_CP_Msk (_U_(0x3) << SSC_IMR_CP_Pos) /**< (SSC_IMR Mask) CP */ +#define SSC_IMR_CP(value) (SSC_IMR_CP_Msk & ((value) << SSC_IMR_CP_Pos)) + +/* -------- SSC_WPMR : (SSC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN_Pos _U_(0) /**< (SSC_WPMR) Write Protection Enable Position */ +#define SSC_WPMR_WPEN_Msk (_U_(0x1) << SSC_WPMR_WPEN_Pos) /**< (SSC_WPMR) Write Protection Enable Mask */ +#define SSC_WPMR_WPEN(value) (SSC_WPMR_WPEN_Msk & ((value) << SSC_WPMR_WPEN_Pos)) +#define SSC_WPMR_WPKEY_Pos _U_(8) /**< (SSC_WPMR) Write Protection Key Position */ +#define SSC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Write Protection Key Mask */ +#define SSC_WPMR_WPKEY(value) (SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)) +#define SSC_WPMR_WPKEY_PASSWD_Val _U_(0x535343) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SSC_WPMR_WPKEY_PASSWD (SSC_WPMR_WPKEY_PASSWD_Val << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SSC_WPMR_Msk _U_(0xFFFFFF01) /**< (SSC_WPMR) Register Mask */ + + +/* -------- SSC_WPSR : (SSC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS_Pos _U_(0) /**< (SSC_WPSR) Write Protection Violation Status Position */ +#define SSC_WPSR_WPVS_Msk (_U_(0x1) << SSC_WPSR_WPVS_Pos) /**< (SSC_WPSR) Write Protection Violation Status Mask */ +#define SSC_WPSR_WPVS(value) (SSC_WPSR_WPVS_Msk & ((value) << SSC_WPSR_WPVS_Pos)) +#define SSC_WPSR_WPVSRC_Pos _U_(8) /**< (SSC_WPSR) Write Protect Violation Source Position */ +#define SSC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SSC_WPSR_WPVSRC_Pos) /**< (SSC_WPSR) Write Protect Violation Source Mask */ +#define SSC_WPSR_WPVSRC(value) (SSC_WPSR_WPVSRC_Msk & ((value) << SSC_WPSR_WPVSRC_Pos)) +#define SSC_WPSR_Msk _U_(0x00FFFF01) /**< (SSC_WPSR) Register Mask */ + + +/** \brief SSC register offsets definitions */ +#define SSC_CR_REG_OFST (0x00) /**< (SSC_CR) Control Register Offset */ +#define SSC_CMR_REG_OFST (0x04) /**< (SSC_CMR) Clock Mode Register Offset */ +#define SSC_RCMR_REG_OFST (0x10) /**< (SSC_RCMR) Receive Clock Mode Register Offset */ +#define SSC_RFMR_REG_OFST (0x14) /**< (SSC_RFMR) Receive Frame Mode Register Offset */ +#define SSC_TCMR_REG_OFST (0x18) /**< (SSC_TCMR) Transmit Clock Mode Register Offset */ +#define SSC_TFMR_REG_OFST (0x1C) /**< (SSC_TFMR) Transmit Frame Mode Register Offset */ +#define SSC_RHR_REG_OFST (0x20) /**< (SSC_RHR) Receive Holding Register Offset */ +#define SSC_THR_REG_OFST (0x24) /**< (SSC_THR) Transmit Holding Register Offset */ +#define SSC_RSHR_REG_OFST (0x30) /**< (SSC_RSHR) Receive Sync. Holding Register Offset */ +#define SSC_TSHR_REG_OFST (0x34) /**< (SSC_TSHR) Transmit Sync. Holding Register Offset */ +#define SSC_RC0R_REG_OFST (0x38) /**< (SSC_RC0R) Receive Compare 0 Register Offset */ +#define SSC_RC1R_REG_OFST (0x3C) /**< (SSC_RC1R) Receive Compare 1 Register Offset */ +#define SSC_SR_REG_OFST (0x40) /**< (SSC_SR) Status Register Offset */ +#define SSC_IER_REG_OFST (0x44) /**< (SSC_IER) Interrupt Enable Register Offset */ +#define SSC_IDR_REG_OFST (0x48) /**< (SSC_IDR) Interrupt Disable Register Offset */ +#define SSC_IMR_REG_OFST (0x4C) /**< (SSC_IMR) Interrupt Mask Register Offset */ +#define SSC_WPMR_REG_OFST (0xE4) /**< (SSC_WPMR) Write Protection Mode Register Offset */ +#define SSC_WPSR_REG_OFST (0xE8) /**< (SSC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SSC register API structure */ +typedef struct +{ + __O uint32_t SSC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t SSC_CMR; /**< Offset: 0x04 (R/W 32) Clock Mode Register */ + __I uint8_t Reserved1[0x08]; + __IO uint32_t SSC_RCMR; /**< Offset: 0x10 (R/W 32) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< Offset: 0x14 (R/W 32) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< Offset: 0x18 (R/W 32) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< Offset: 0x1C (R/W 32) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< Offset: 0x20 (R/ 32) Receive Holding Register */ + __O uint32_t SSC_THR; /**< Offset: 0x24 ( /W 32) Transmit Holding Register */ + __I uint8_t Reserved2[0x08]; + __I uint32_t SSC_RSHR; /**< Offset: 0x30 (R/ 32) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< Offset: 0x34 (R/W 32) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< Offset: 0x38 (R/W 32) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< Offset: 0x3C (R/W 32) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O uint32_t SSC_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved3[0x94]; + __IO uint32_t SSC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} ssc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SSC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/supc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/supc.h new file mode 100644 index 00000000..4e63f213 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/supc.h @@ -0,0 +1,610 @@ +/** + * \brief Component description for SUPC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_SUPC_COMPONENT_H_ +#define _SAME70_SUPC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SUPC */ +/* ************************************************************************** */ + +/* -------- SUPC_CR : (SUPC Offset: 0x00) ( /W 32) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF_Pos _U_(2) /**< (SUPC_CR) Voltage Regulator Off Position */ +#define SUPC_CR_VROFF_Msk (_U_(0x1) << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) Voltage Regulator Off Mask */ +#define SUPC_CR_VROFF(value) (SUPC_CR_VROFF_Msk & ((value) << SUPC_CR_VROFF_Pos)) +#define SUPC_CR_VROFF_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_VROFF_NO_EFFECT (SUPC_CR_VROFF_NO_EFFECT_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_VROFF_STOP_VREG (SUPC_CR_VROFF_STOP_VREG_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Position */ +#define SUPC_CR_XTALSEL_Pos _U_(3) /**< (SUPC_CR) Crystal Oscillator Select Position */ +#define SUPC_CR_XTALSEL_Msk (_U_(0x1) << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) Crystal Oscillator Select Mask */ +#define SUPC_CR_XTALSEL(value) (SUPC_CR_XTALSEL_Msk & ((value) << SUPC_CR_XTALSEL_Pos)) +#define SUPC_CR_XTALSEL_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_XTALSEL_NO_EFFECT (SUPC_CR_XTALSEL_NO_EFFECT_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (SUPC_CR_XTALSEL_CRYSTAL_SEL_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Position */ +#define SUPC_CR_KEY_Pos _U_(24) /**< (SUPC_CR) Password Position */ +#define SUPC_CR_KEY_Msk (_U_(0xFF) << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Password Mask */ +#define SUPC_CR_KEY(value) (SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)) +#define SUPC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. */ +#define SUPC_CR_KEY_PASSWD (SUPC_CR_KEY_PASSWD_Val << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_CR_Msk _U_(0xFF00000C) /**< (SUPC_CR) Register Mask */ + + +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) (R/W 32) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos _U_(0) /**< (SUPC_SMMR) Supply Monitor Threshold Position */ +#define SUPC_SMMR_SMTH_Msk (_U_(0xF) << SUPC_SMMR_SMTH_Pos) /**< (SUPC_SMMR) Supply Monitor Threshold Mask */ +#define SUPC_SMMR_SMTH(value) (SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)) +#define SUPC_SMMR_SMSMPL_Pos _U_(8) /**< (SUPC_SMMR) Supply Monitor Sampling Period Position */ +#define SUPC_SMMR_SMSMPL_Msk (_U_(0x7) << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor Sampling Period Mask */ +#define SUPC_SMMR_SMSMPL(value) (SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)) +#define SUPC_SMMR_SMSMPL_SMD_Val _U_(0x0) /**< (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM_Val _U_(0x1) /**< (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK_Val _U_(0x2) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK_Val _U_(0x3) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK_Val _U_(0x4) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMSMPL_SMD (SUPC_SMMR_SMSMPL_SMD_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor disabled Position */ +#define SUPC_SMMR_SMSMPL_CSM (SUPC_SMMR_SMSMPL_CSM_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Continuous Supply Monitor Position */ +#define SUPC_SMMR_SMSMPL_32SLCK (SUPC_SMMR_SMSMPL_32SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_256SLCK (SUPC_SMMR_SMSMPL_256SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_2048SLCK (SUPC_SMMR_SMSMPL_2048SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods Position */ +#define SUPC_SMMR_SMRSTEN_Pos _U_(12) /**< (SUPC_SMMR) Supply Monitor Reset Enable Position */ +#define SUPC_SMMR_SMRSTEN_Msk (_U_(0x1) << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) Supply Monitor Reset Enable Mask */ +#define SUPC_SMMR_SMRSTEN(value) (SUPC_SMMR_SMRSTEN_Msk & ((value) << SUPC_SMMR_SMRSTEN_Pos)) +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMRSTEN_ENABLE (SUPC_SMMR_SMRSTEN_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_Pos _U_(13) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Position */ +#define SUPC_SMMR_SMIEN_Msk (_U_(0x1) << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Mask */ +#define SUPC_SMMR_SMIEN(value) (SUPC_SMMR_SMIEN_Msk & ((value) << SUPC_SMMR_SMIEN_Pos)) +#define SUPC_SMMR_SMIEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (SUPC_SMMR_SMIEN_NOT_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_ENABLE (SUPC_SMMR_SMIEN_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_Msk _U_(0x0000370F) /**< (SUPC_SMMR) Register Mask */ + + +/* -------- SUPC_MR : (SUPC Offset: 0x08) (R/W 32) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN_Pos _U_(12) /**< (SUPC_MR) Brownout Detector Reset Enable Position */ +#define SUPC_MR_BODRSTEN_Msk (_U_(0x1) << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) Brownout Detector Reset Enable Mask */ +#define SUPC_MR_BODRSTEN(value) (SUPC_MR_BODRSTEN_Msk & ((value) << SUPC_MR_BODRSTEN_Pos)) +#define SUPC_MR_BODRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (SUPC_MR_BODRSTEN_NOT_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. Position */ +#define SUPC_MR_BODRSTEN_ENABLE (SUPC_MR_BODRSTEN_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Position */ +#define SUPC_MR_BODDIS_Pos _U_(13) /**< (SUPC_MR) Brownout Detector Disable Position */ +#define SUPC_MR_BODDIS_Msk (_U_(0x1) << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) Brownout Detector Disable Mask */ +#define SUPC_MR_BODDIS(value) (SUPC_MR_BODDIS_Msk & ((value) << SUPC_MR_BODDIS_Pos)) +#define SUPC_MR_BODDIS_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE_Val _U_(0x1) /**< (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_BODDIS_ENABLE (SUPC_MR_BODDIS_ENABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is enabled. Position */ +#define SUPC_MR_BODDIS_DISABLE (SUPC_MR_BODDIS_DISABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is disabled. Position */ +#define SUPC_MR_ONREG_Pos _U_(14) /**< (SUPC_MR) Voltage Regulator Enable Position */ +#define SUPC_MR_ONREG_Msk (_U_(0x1) << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Voltage Regulator Enable Mask */ +#define SUPC_MR_ONREG(value) (SUPC_MR_ONREG_Msk & ((value) << SUPC_MR_ONREG_Pos)) +#define SUPC_MR_ONREG_ONREG_UNUSED_Val _U_(0x0) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED_Val _U_(0x1) /**< (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_ONREG_ONREG_UNUSED (SUPC_MR_ONREG_ONREG_UNUSED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). Position */ +#define SUPC_MR_ONREG_ONREG_USED (SUPC_MR_ONREG_ONREG_USED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is used. Position */ +#define SUPC_MR_BKUPRETON_Pos _U_(17) /**< (SUPC_MR) SRAM On In Backup Mode Position */ +#define SUPC_MR_BKUPRETON_Msk (_U_(0x1) << SUPC_MR_BKUPRETON_Pos) /**< (SUPC_MR) SRAM On In Backup Mode Mask */ +#define SUPC_MR_BKUPRETON(value) (SUPC_MR_BKUPRETON_Msk & ((value) << SUPC_MR_BKUPRETON_Pos)) +#define SUPC_MR_OSCBYPASS_Pos _U_(20) /**< (SUPC_MR) Oscillator Bypass Position */ +#define SUPC_MR_OSCBYPASS_Msk (_U_(0x1) << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) Oscillator Bypass Mask */ +#define SUPC_MR_OSCBYPASS(value) (SUPC_MR_OSCBYPASS_Msk & ((value) << SUPC_MR_OSCBYPASS_Pos)) +#define SUPC_MR_OSCBYPASS_NO_EFFECT_Val _U_(0x0) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS_Val _U_(0x1) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (SUPC_MR_OSCBYPASS_NO_EFFECT_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). Position */ +#define SUPC_MR_OSCBYPASS_BYPASS (SUPC_MR_OSCBYPASS_BYPASS_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Position */ +#define SUPC_MR_KEY_Pos _U_(24) /**< (SUPC_MR) Password Key Position */ +#define SUPC_MR_KEY_Msk (_U_(0xFF) << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Password Key Mask */ +#define SUPC_MR_KEY(value) (SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)) +#define SUPC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. */ +#define SUPC_MR_KEY_PASSWD (SUPC_MR_KEY_PASSWD_Val << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_MR_Msk _U_(0xFF127000) /**< (SUPC_MR) Register Mask */ + + +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) (R/W 32) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN_Pos _U_(1) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Position */ +#define SUPC_WUMR_SMEN_Msk (_U_(0x1) << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Mask */ +#define SUPC_WUMR_SMEN(value) (SUPC_WUMR_SMEN_Msk & ((value) << SUPC_WUMR_SMEN_Pos)) +#define SUPC_WUMR_SMEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (SUPC_WUMR_SMEN_NOT_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. Position */ +#define SUPC_WUMR_SMEN_ENABLE (SUPC_WUMR_SMEN_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTTEN_Pos _U_(2) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Position */ +#define SUPC_WUMR_RTTEN_Msk (_U_(0x1) << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Mask */ +#define SUPC_WUMR_RTTEN(value) (SUPC_WUMR_RTTEN_Msk & ((value) << SUPC_WUMR_RTTEN_Pos)) +#define SUPC_WUMR_RTTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (SUPC_WUMR_RTTEN_NOT_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTTEN_ENABLE (SUPC_WUMR_RTTEN_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTCEN_Pos _U_(3) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Position */ +#define SUPC_WUMR_RTCEN_Msk (_U_(0x1) << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Mask */ +#define SUPC_WUMR_RTCEN(value) (SUPC_WUMR_RTCEN_Msk & ((value) << SUPC_WUMR_RTCEN_Pos)) +#define SUPC_WUMR_RTCEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (SUPC_WUMR_RTCEN_NOT_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTCEN_ENABLE (SUPC_WUMR_RTCEN_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_LPDBCEN0_Pos _U_(5) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Position */ +#define SUPC_WUMR_LPDBCEN0_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Mask */ +#define SUPC_WUMR_LPDBCEN0(value) (SUPC_WUMR_LPDBCEN0_Msk & ((value) << SUPC_WUMR_LPDBCEN0_Pos)) +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (SUPC_WUMR_LPDBCEN0_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCEN1_Pos _U_(6) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Position */ +#define SUPC_WUMR_LPDBCEN1_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Mask */ +#define SUPC_WUMR_LPDBCEN1(value) (SUPC_WUMR_LPDBCEN1_Msk & ((value) << SUPC_WUMR_LPDBCEN1_Pos)) +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (SUPC_WUMR_LPDBCEN1_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCCLR_Pos _U_(7) /**< (SUPC_WUMR) Low-power Debouncer Clear Position */ +#define SUPC_WUMR_LPDBCCLR_Msk (_U_(0x1) << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) Low-power Debouncer Clear Mask */ +#define SUPC_WUMR_LPDBCCLR(value) (SUPC_WUMR_LPDBCCLR_Msk & ((value) << SUPC_WUMR_LPDBCCLR_Pos)) +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (SUPC_WUMR_LPDBCCLR_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_WKUPDBC_Pos _U_(12) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Position */ +#define SUPC_WUMR_WKUPDBC_Msk (_U_(0x7) << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Mask */ +#define SUPC_WUMR_WKUPDBC(value) (SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE_Val _U_(0x0) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK_Val _U_(0x1) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK_Val _U_(0x2) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK_Val _U_(0x3) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK_Val _U_(0x4) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK_Val _U_(0x5) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (SUPC_WUMR_WKUPDBC_IMMEDIATE_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. Position */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (SUPC_WUMR_WKUPDBC_3_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (SUPC_WUMR_WKUPDBC_32_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (SUPC_WUMR_WKUPDBC_512_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (SUPC_WUMR_WKUPDBC_4096_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (SUPC_WUMR_WKUPDBC_32768_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods Position */ +#define SUPC_WUMR_LPDBC_Pos _U_(16) /**< (SUPC_WUMR) Low-power Debouncer Period Position */ +#define SUPC_WUMR_LPDBC_Msk (_U_(0x7) << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Low-power Debouncer Period Mask */ +#define SUPC_WUMR_LPDBC(value) (SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)) +#define SUPC_WUMR_LPDBC_DISABLE_Val _U_(0x0) /**< (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT_Val _U_(0x1) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT_Val _U_(0x2) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT_Val _U_(0x3) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT_Val _U_(0x4) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT_Val _U_(0x5) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT_Val _U_(0x6) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT_Val _U_(0x7) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_DISABLE (SUPC_WUMR_LPDBC_DISABLE_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Disable the low-power debouncers. Position */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (SUPC_WUMR_LPDBC_2_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (SUPC_WUMR_LPDBC_3_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (SUPC_WUMR_LPDBC_4_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (SUPC_WUMR_LPDBC_5_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (SUPC_WUMR_LPDBC_6_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (SUPC_WUMR_LPDBC_7_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (SUPC_WUMR_LPDBC_8_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods Position */ +#define SUPC_WUMR_Msk _U_(0x000770EE) /**< (SUPC_WUMR) Register Mask */ + +#define SUPC_WUMR_LPDBCEN_Pos _U_(5) /**< (SUPC_WUMR Position) Low-power Debouncer Enable WKUPx */ +#define SUPC_WUMR_LPDBCEN_Msk (_U_(0x3) << SUPC_WUMR_LPDBCEN_Pos) /**< (SUPC_WUMR Mask) LPDBCEN */ +#define SUPC_WUMR_LPDBCEN(value) (SUPC_WUMR_LPDBCEN_Msk & ((value) << SUPC_WUMR_LPDBCEN_Pos)) + +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) (R/W 32) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0_Pos _U_(0) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Position */ +#define SUPC_WUIR_WKUPEN0_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Mask */ +#define SUPC_WUIR_WKUPEN0(value) (SUPC_WUIR_WKUPEN0_Msk & ((value) << SUPC_WUIR_WKUPEN0_Pos)) +#define SUPC_WUIR_WKUPEN0_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN0_DISABLE (SUPC_WUIR_WKUPEN0_DISABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN0_ENABLE (SUPC_WUIR_WKUPEN0_ENABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN1_Pos _U_(1) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Position */ +#define SUPC_WUIR_WKUPEN1_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Mask */ +#define SUPC_WUIR_WKUPEN1(value) (SUPC_WUIR_WKUPEN1_Msk & ((value) << SUPC_WUIR_WKUPEN1_Pos)) +#define SUPC_WUIR_WKUPEN1_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1_DISABLE (SUPC_WUIR_WKUPEN1_DISABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN1_ENABLE (SUPC_WUIR_WKUPEN1_ENABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN2_Pos _U_(2) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Position */ +#define SUPC_WUIR_WKUPEN2_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Mask */ +#define SUPC_WUIR_WKUPEN2(value) (SUPC_WUIR_WKUPEN2_Msk & ((value) << SUPC_WUIR_WKUPEN2_Pos)) +#define SUPC_WUIR_WKUPEN2_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2_DISABLE (SUPC_WUIR_WKUPEN2_DISABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN2_ENABLE (SUPC_WUIR_WKUPEN2_ENABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN3_Pos _U_(3) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Position */ +#define SUPC_WUIR_WKUPEN3_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Mask */ +#define SUPC_WUIR_WKUPEN3(value) (SUPC_WUIR_WKUPEN3_Msk & ((value) << SUPC_WUIR_WKUPEN3_Pos)) +#define SUPC_WUIR_WKUPEN3_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3_DISABLE (SUPC_WUIR_WKUPEN3_DISABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN3_ENABLE (SUPC_WUIR_WKUPEN3_ENABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN4_Pos _U_(4) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Position */ +#define SUPC_WUIR_WKUPEN4_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Mask */ +#define SUPC_WUIR_WKUPEN4(value) (SUPC_WUIR_WKUPEN4_Msk & ((value) << SUPC_WUIR_WKUPEN4_Pos)) +#define SUPC_WUIR_WKUPEN4_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4_DISABLE (SUPC_WUIR_WKUPEN4_DISABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN4_ENABLE (SUPC_WUIR_WKUPEN4_ENABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN5_Pos _U_(5) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Position */ +#define SUPC_WUIR_WKUPEN5_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Mask */ +#define SUPC_WUIR_WKUPEN5(value) (SUPC_WUIR_WKUPEN5_Msk & ((value) << SUPC_WUIR_WKUPEN5_Pos)) +#define SUPC_WUIR_WKUPEN5_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5_DISABLE (SUPC_WUIR_WKUPEN5_DISABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN5_ENABLE (SUPC_WUIR_WKUPEN5_ENABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN6_Pos _U_(6) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Position */ +#define SUPC_WUIR_WKUPEN6_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Mask */ +#define SUPC_WUIR_WKUPEN6(value) (SUPC_WUIR_WKUPEN6_Msk & ((value) << SUPC_WUIR_WKUPEN6_Pos)) +#define SUPC_WUIR_WKUPEN6_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6_DISABLE (SUPC_WUIR_WKUPEN6_DISABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN6_ENABLE (SUPC_WUIR_WKUPEN6_ENABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN7_Pos _U_(7) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Position */ +#define SUPC_WUIR_WKUPEN7_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Mask */ +#define SUPC_WUIR_WKUPEN7(value) (SUPC_WUIR_WKUPEN7_Msk & ((value) << SUPC_WUIR_WKUPEN7_Pos)) +#define SUPC_WUIR_WKUPEN7_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7_DISABLE (SUPC_WUIR_WKUPEN7_DISABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN7_ENABLE (SUPC_WUIR_WKUPEN7_ENABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN8_Pos _U_(8) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Position */ +#define SUPC_WUIR_WKUPEN8_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Mask */ +#define SUPC_WUIR_WKUPEN8(value) (SUPC_WUIR_WKUPEN8_Msk & ((value) << SUPC_WUIR_WKUPEN8_Pos)) +#define SUPC_WUIR_WKUPEN8_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8_DISABLE (SUPC_WUIR_WKUPEN8_DISABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN8_ENABLE (SUPC_WUIR_WKUPEN8_ENABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN9_Pos _U_(9) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Position */ +#define SUPC_WUIR_WKUPEN9_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Mask */ +#define SUPC_WUIR_WKUPEN9(value) (SUPC_WUIR_WKUPEN9_Msk & ((value) << SUPC_WUIR_WKUPEN9_Pos)) +#define SUPC_WUIR_WKUPEN9_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9_DISABLE (SUPC_WUIR_WKUPEN9_DISABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN9_ENABLE (SUPC_WUIR_WKUPEN9_ENABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN10_Pos _U_(10) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Position */ +#define SUPC_WUIR_WKUPEN10_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Mask */ +#define SUPC_WUIR_WKUPEN10(value) (SUPC_WUIR_WKUPEN10_Msk & ((value) << SUPC_WUIR_WKUPEN10_Pos)) +#define SUPC_WUIR_WKUPEN10_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10_DISABLE (SUPC_WUIR_WKUPEN10_DISABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN10_ENABLE (SUPC_WUIR_WKUPEN10_ENABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN11_Pos _U_(11) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Position */ +#define SUPC_WUIR_WKUPEN11_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Mask */ +#define SUPC_WUIR_WKUPEN11(value) (SUPC_WUIR_WKUPEN11_Msk & ((value) << SUPC_WUIR_WKUPEN11_Pos)) +#define SUPC_WUIR_WKUPEN11_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11_DISABLE (SUPC_WUIR_WKUPEN11_DISABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN11_ENABLE (SUPC_WUIR_WKUPEN11_ENABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN12_Pos _U_(12) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Position */ +#define SUPC_WUIR_WKUPEN12_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Mask */ +#define SUPC_WUIR_WKUPEN12(value) (SUPC_WUIR_WKUPEN12_Msk & ((value) << SUPC_WUIR_WKUPEN12_Pos)) +#define SUPC_WUIR_WKUPEN12_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12_DISABLE (SUPC_WUIR_WKUPEN12_DISABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN12_ENABLE (SUPC_WUIR_WKUPEN12_ENABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN13_Pos _U_(13) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Position */ +#define SUPC_WUIR_WKUPEN13_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Mask */ +#define SUPC_WUIR_WKUPEN13(value) (SUPC_WUIR_WKUPEN13_Msk & ((value) << SUPC_WUIR_WKUPEN13_Pos)) +#define SUPC_WUIR_WKUPEN13_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13_DISABLE (SUPC_WUIR_WKUPEN13_DISABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN13_ENABLE (SUPC_WUIR_WKUPEN13_ENABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_Pos _U_(16) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Position */ +#define SUPC_WUIR_WKUPT0_Msk (_U_(0x1) << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Mask */ +#define SUPC_WUIR_WKUPT0(value) (SUPC_WUIR_WKUPT0_Msk & ((value) << SUPC_WUIR_WKUPT0_Pos)) +#define SUPC_WUIR_WKUPT0_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW (SUPC_WUIR_WKUPT0_LOW_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_HIGH (SUPC_WUIR_WKUPT0_HIGH_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_Pos _U_(17) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Position */ +#define SUPC_WUIR_WKUPT1_Msk (_U_(0x1) << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Mask */ +#define SUPC_WUIR_WKUPT1(value) (SUPC_WUIR_WKUPT1_Msk & ((value) << SUPC_WUIR_WKUPT1_Pos)) +#define SUPC_WUIR_WKUPT1_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW (SUPC_WUIR_WKUPT1_LOW_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_HIGH (SUPC_WUIR_WKUPT1_HIGH_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_Pos _U_(18) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Position */ +#define SUPC_WUIR_WKUPT2_Msk (_U_(0x1) << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Mask */ +#define SUPC_WUIR_WKUPT2(value) (SUPC_WUIR_WKUPT2_Msk & ((value) << SUPC_WUIR_WKUPT2_Pos)) +#define SUPC_WUIR_WKUPT2_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW (SUPC_WUIR_WKUPT2_LOW_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_HIGH (SUPC_WUIR_WKUPT2_HIGH_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_Pos _U_(19) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Position */ +#define SUPC_WUIR_WKUPT3_Msk (_U_(0x1) << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Mask */ +#define SUPC_WUIR_WKUPT3(value) (SUPC_WUIR_WKUPT3_Msk & ((value) << SUPC_WUIR_WKUPT3_Pos)) +#define SUPC_WUIR_WKUPT3_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW (SUPC_WUIR_WKUPT3_LOW_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_HIGH (SUPC_WUIR_WKUPT3_HIGH_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_Pos _U_(20) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Position */ +#define SUPC_WUIR_WKUPT4_Msk (_U_(0x1) << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Mask */ +#define SUPC_WUIR_WKUPT4(value) (SUPC_WUIR_WKUPT4_Msk & ((value) << SUPC_WUIR_WKUPT4_Pos)) +#define SUPC_WUIR_WKUPT4_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW (SUPC_WUIR_WKUPT4_LOW_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_HIGH (SUPC_WUIR_WKUPT4_HIGH_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_Pos _U_(21) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Position */ +#define SUPC_WUIR_WKUPT5_Msk (_U_(0x1) << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Mask */ +#define SUPC_WUIR_WKUPT5(value) (SUPC_WUIR_WKUPT5_Msk & ((value) << SUPC_WUIR_WKUPT5_Pos)) +#define SUPC_WUIR_WKUPT5_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW (SUPC_WUIR_WKUPT5_LOW_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_HIGH (SUPC_WUIR_WKUPT5_HIGH_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_Pos _U_(22) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Position */ +#define SUPC_WUIR_WKUPT6_Msk (_U_(0x1) << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Mask */ +#define SUPC_WUIR_WKUPT6(value) (SUPC_WUIR_WKUPT6_Msk & ((value) << SUPC_WUIR_WKUPT6_Pos)) +#define SUPC_WUIR_WKUPT6_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW (SUPC_WUIR_WKUPT6_LOW_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_HIGH (SUPC_WUIR_WKUPT6_HIGH_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_Pos _U_(23) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Position */ +#define SUPC_WUIR_WKUPT7_Msk (_U_(0x1) << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Mask */ +#define SUPC_WUIR_WKUPT7(value) (SUPC_WUIR_WKUPT7_Msk & ((value) << SUPC_WUIR_WKUPT7_Pos)) +#define SUPC_WUIR_WKUPT7_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW (SUPC_WUIR_WKUPT7_LOW_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_HIGH (SUPC_WUIR_WKUPT7_HIGH_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_Pos _U_(24) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Position */ +#define SUPC_WUIR_WKUPT8_Msk (_U_(0x1) << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Mask */ +#define SUPC_WUIR_WKUPT8(value) (SUPC_WUIR_WKUPT8_Msk & ((value) << SUPC_WUIR_WKUPT8_Pos)) +#define SUPC_WUIR_WKUPT8_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW (SUPC_WUIR_WKUPT8_LOW_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_HIGH (SUPC_WUIR_WKUPT8_HIGH_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_Pos _U_(25) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Position */ +#define SUPC_WUIR_WKUPT9_Msk (_U_(0x1) << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Mask */ +#define SUPC_WUIR_WKUPT9(value) (SUPC_WUIR_WKUPT9_Msk & ((value) << SUPC_WUIR_WKUPT9_Pos)) +#define SUPC_WUIR_WKUPT9_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW (SUPC_WUIR_WKUPT9_LOW_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_HIGH (SUPC_WUIR_WKUPT9_HIGH_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_Pos _U_(26) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Position */ +#define SUPC_WUIR_WKUPT10_Msk (_U_(0x1) << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Mask */ +#define SUPC_WUIR_WKUPT10(value) (SUPC_WUIR_WKUPT10_Msk & ((value) << SUPC_WUIR_WKUPT10_Pos)) +#define SUPC_WUIR_WKUPT10_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW (SUPC_WUIR_WKUPT10_LOW_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_HIGH (SUPC_WUIR_WKUPT10_HIGH_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_Pos _U_(27) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Position */ +#define SUPC_WUIR_WKUPT11_Msk (_U_(0x1) << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Mask */ +#define SUPC_WUIR_WKUPT11(value) (SUPC_WUIR_WKUPT11_Msk & ((value) << SUPC_WUIR_WKUPT11_Pos)) +#define SUPC_WUIR_WKUPT11_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW (SUPC_WUIR_WKUPT11_LOW_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_HIGH (SUPC_WUIR_WKUPT11_HIGH_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_Pos _U_(28) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Position */ +#define SUPC_WUIR_WKUPT12_Msk (_U_(0x1) << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Mask */ +#define SUPC_WUIR_WKUPT12(value) (SUPC_WUIR_WKUPT12_Msk & ((value) << SUPC_WUIR_WKUPT12_Pos)) +#define SUPC_WUIR_WKUPT12_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW (SUPC_WUIR_WKUPT12_LOW_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_HIGH (SUPC_WUIR_WKUPT12_HIGH_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_Pos _U_(29) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Position */ +#define SUPC_WUIR_WKUPT13_Msk (_U_(0x1) << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Mask */ +#define SUPC_WUIR_WKUPT13(value) (SUPC_WUIR_WKUPT13_Msk & ((value) << SUPC_WUIR_WKUPT13_Pos)) +#define SUPC_WUIR_WKUPT13_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW (SUPC_WUIR_WKUPT13_LOW_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_HIGH (SUPC_WUIR_WKUPT13_HIGH_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_Msk _U_(0x3FFF3FFF) /**< (SUPC_WUIR) Register Mask */ + +#define SUPC_WUIR_WKUPEN_Pos _U_(0) /**< (SUPC_WUIR Position) Wake-up Input Enable x to x */ +#define SUPC_WUIR_WKUPEN_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPEN_Pos) /**< (SUPC_WUIR Mask) WKUPEN */ +#define SUPC_WUIR_WKUPEN(value) (SUPC_WUIR_WKUPEN_Msk & ((value) << SUPC_WUIR_WKUPEN_Pos)) +#define SUPC_WUIR_WKUPT_Pos _U_(16) /**< (SUPC_WUIR Position) Wake-up Input Type x to x3 */ +#define SUPC_WUIR_WKUPT_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPT_Pos) /**< (SUPC_WUIR Mask) WKUPT */ +#define SUPC_WUIR_WKUPT(value) (SUPC_WUIR_WKUPT_Msk & ((value) << SUPC_WUIR_WKUPT_Pos)) + +/* -------- SUPC_SR : (SUPC Offset: 0x14) ( R/ 32) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS_Pos _U_(1) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Position */ +#define SUPC_SR_WKUPS_Msk (_U_(0x1) << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_WKUPS(value) (SUPC_SR_WKUPS_Msk & ((value) << SUPC_SR_WKUPS_Pos)) +#define SUPC_SR_WKUPS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_NO (SUPC_SR_WKUPS_NO_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPS_PRESENT (SUPC_SR_WKUPS_PRESENT_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_Pos _U_(2) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Position */ +#define SUPC_SR_SMWS_Msk (_U_(0x1) << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_SMWS(value) (SUPC_SR_SMWS_Msk & ((value) << SUPC_SR_SMWS_Pos)) +#define SUPC_SR_SMWS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_NO (SUPC_SR_SMWS_NO_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_PRESENT (SUPC_SR_SMWS_PRESENT_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_Pos _U_(3) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Position */ +#define SUPC_SR_BODRSTS_Msk (_U_(0x1) << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Mask */ +#define SUPC_SR_BODRSTS(value) (SUPC_SR_BODRSTS_Msk & ((value) << SUPC_SR_BODRSTS_Pos)) +#define SUPC_SR_BODRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_NO (SUPC_SR_BODRSTS_NO_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_PRESENT (SUPC_SR_BODRSTS_PRESENT_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_Pos _U_(4) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Position */ +#define SUPC_SR_SMRSTS_Msk (_U_(0x1) << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Mask */ +#define SUPC_SR_SMRSTS(value) (SUPC_SR_SMRSTS_Msk & ((value) << SUPC_SR_SMRSTS_Pos)) +#define SUPC_SR_SMRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_NO (SUPC_SR_SMRSTS_NO_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_PRESENT (SUPC_SR_SMRSTS_PRESENT_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMS_Pos _U_(5) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Position */ +#define SUPC_SR_SMS_Msk (_U_(0x1) << SUPC_SR_SMS_Pos) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Mask */ +#define SUPC_SR_SMS(value) (SUPC_SR_SMS_Msk & ((value) << SUPC_SR_SMS_Pos)) +#define SUPC_SR_SMS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_NO (SUPC_SR_SMS_NO_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMS_PRESENT (SUPC_SR_SMS_PRESENT_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMOS_Pos _U_(6) /**< (SUPC_SR) Supply Monitor Output Status Position */ +#define SUPC_SR_SMOS_Msk (_U_(0x1) << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) Supply Monitor Output Status Mask */ +#define SUPC_SR_SMOS(value) (SUPC_SR_SMOS_Msk & ((value) << SUPC_SR_SMOS_Pos)) +#define SUPC_SR_SMOS_HIGH_Val _U_(0x0) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW_Val _U_(0x1) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_HIGH (SUPC_SR_SMOS_HIGH_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. Position */ +#define SUPC_SR_SMOS_LOW (SUPC_SR_SMOS_LOW_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. Position */ +#define SUPC_SR_OSCSEL_Pos _U_(7) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Position */ +#define SUPC_SR_OSCSEL_Msk (_U_(0x1) << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Mask */ +#define SUPC_SR_OSCSEL(value) (SUPC_SR_OSCSEL_Msk & ((value) << SUPC_SR_OSCSEL_Pos)) +#define SUPC_SR_OSCSEL_RC_Val _U_(0x0) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST_Val _U_(0x1) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_OSCSEL_RC (SUPC_SR_OSCSEL_RC_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. Position */ +#define SUPC_SR_OSCSEL_CRYST (SUPC_SR_OSCSEL_CRYST_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. Position */ +#define SUPC_SR_LPDBCS0_Pos _U_(13) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Position */ +#define SUPC_SR_LPDBCS0_Msk (_U_(0x1) << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS0(value) (SUPC_SR_LPDBCS0_Msk & ((value) << SUPC_SR_LPDBCS0_Pos)) +#define SUPC_SR_LPDBCS0_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_NO (SUPC_SR_LPDBCS0_NO_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS0_PRESENT (SUPC_SR_LPDBCS0_PRESENT_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_Pos _U_(14) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Position */ +#define SUPC_SR_LPDBCS1_Msk (_U_(0x1) << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS1(value) (SUPC_SR_LPDBCS1_Msk & ((value) << SUPC_SR_LPDBCS1_Pos)) +#define SUPC_SR_LPDBCS1_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_NO (SUPC_SR_LPDBCS1_NO_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_PRESENT (SUPC_SR_LPDBCS1_PRESENT_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS0_Pos _U_(16) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS0_Msk (_U_(0x1) << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS0(value) (SUPC_SR_WKUPIS0_Msk & ((value) << SUPC_SR_WKUPIS0_Pos)) +#define SUPC_SR_WKUPIS0_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0_DIS (SUPC_SR_WKUPIS0_DIS_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS0_EN (SUPC_SR_WKUPIS0_EN_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS1_Pos _U_(17) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS1_Msk (_U_(0x1) << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS1(value) (SUPC_SR_WKUPIS1_Msk & ((value) << SUPC_SR_WKUPIS1_Pos)) +#define SUPC_SR_WKUPIS1_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1_DIS (SUPC_SR_WKUPIS1_DIS_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS1_EN (SUPC_SR_WKUPIS1_EN_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS2_Pos _U_(18) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS2_Msk (_U_(0x1) << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS2(value) (SUPC_SR_WKUPIS2_Msk & ((value) << SUPC_SR_WKUPIS2_Pos)) +#define SUPC_SR_WKUPIS2_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2_DIS (SUPC_SR_WKUPIS2_DIS_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS2_EN (SUPC_SR_WKUPIS2_EN_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS3_Pos _U_(19) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS3_Msk (_U_(0x1) << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS3(value) (SUPC_SR_WKUPIS3_Msk & ((value) << SUPC_SR_WKUPIS3_Pos)) +#define SUPC_SR_WKUPIS3_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3_DIS (SUPC_SR_WKUPIS3_DIS_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS3_EN (SUPC_SR_WKUPIS3_EN_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS4_Pos _U_(20) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS4_Msk (_U_(0x1) << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS4(value) (SUPC_SR_WKUPIS4_Msk & ((value) << SUPC_SR_WKUPIS4_Pos)) +#define SUPC_SR_WKUPIS4_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4_DIS (SUPC_SR_WKUPIS4_DIS_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS4_EN (SUPC_SR_WKUPIS4_EN_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS5_Pos _U_(21) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS5_Msk (_U_(0x1) << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS5(value) (SUPC_SR_WKUPIS5_Msk & ((value) << SUPC_SR_WKUPIS5_Pos)) +#define SUPC_SR_WKUPIS5_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5_DIS (SUPC_SR_WKUPIS5_DIS_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS5_EN (SUPC_SR_WKUPIS5_EN_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS6_Pos _U_(22) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS6_Msk (_U_(0x1) << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS6(value) (SUPC_SR_WKUPIS6_Msk & ((value) << SUPC_SR_WKUPIS6_Pos)) +#define SUPC_SR_WKUPIS6_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6_DIS (SUPC_SR_WKUPIS6_DIS_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS6_EN (SUPC_SR_WKUPIS6_EN_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS7_Pos _U_(23) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS7_Msk (_U_(0x1) << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS7(value) (SUPC_SR_WKUPIS7_Msk & ((value) << SUPC_SR_WKUPIS7_Pos)) +#define SUPC_SR_WKUPIS7_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7_DIS (SUPC_SR_WKUPIS7_DIS_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS7_EN (SUPC_SR_WKUPIS7_EN_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS8_Pos _U_(24) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS8_Msk (_U_(0x1) << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS8(value) (SUPC_SR_WKUPIS8_Msk & ((value) << SUPC_SR_WKUPIS8_Pos)) +#define SUPC_SR_WKUPIS8_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8_DIS (SUPC_SR_WKUPIS8_DIS_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS8_EN (SUPC_SR_WKUPIS8_EN_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS9_Pos _U_(25) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS9_Msk (_U_(0x1) << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS9(value) (SUPC_SR_WKUPIS9_Msk & ((value) << SUPC_SR_WKUPIS9_Pos)) +#define SUPC_SR_WKUPIS9_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9_DIS (SUPC_SR_WKUPIS9_DIS_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS9_EN (SUPC_SR_WKUPIS9_EN_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS10_Pos _U_(26) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS10_Msk (_U_(0x1) << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS10(value) (SUPC_SR_WKUPIS10_Msk & ((value) << SUPC_SR_WKUPIS10_Pos)) +#define SUPC_SR_WKUPIS10_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10_DIS (SUPC_SR_WKUPIS10_DIS_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS10_EN (SUPC_SR_WKUPIS10_EN_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS11_Pos _U_(27) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS11_Msk (_U_(0x1) << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS11(value) (SUPC_SR_WKUPIS11_Msk & ((value) << SUPC_SR_WKUPIS11_Pos)) +#define SUPC_SR_WKUPIS11_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11_DIS (SUPC_SR_WKUPIS11_DIS_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS11_EN (SUPC_SR_WKUPIS11_EN_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS12_Pos _U_(28) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS12_Msk (_U_(0x1) << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS12(value) (SUPC_SR_WKUPIS12_Msk & ((value) << SUPC_SR_WKUPIS12_Pos)) +#define SUPC_SR_WKUPIS12_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12_DIS (SUPC_SR_WKUPIS12_DIS_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS12_EN (SUPC_SR_WKUPIS12_EN_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS13_Pos _U_(29) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS13_Msk (_U_(0x1) << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS13(value) (SUPC_SR_WKUPIS13_Msk & ((value) << SUPC_SR_WKUPIS13_Pos)) +#define SUPC_SR_WKUPIS13_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13_DIS (SUPC_SR_WKUPIS13_DIS_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS13_EN (SUPC_SR_WKUPIS13_EN_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_Msk _U_(0x3FFF60FE) /**< (SUPC_SR) Register Mask */ + +#define SUPC_SR_LPDBCS_Pos _U_(13) /**< (SUPC_SR Position) Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */ +#define SUPC_SR_LPDBCS_Msk (_U_(0x3) << SUPC_SR_LPDBCS_Pos) /**< (SUPC_SR Mask) LPDBCS */ +#define SUPC_SR_LPDBCS(value) (SUPC_SR_LPDBCS_Msk & ((value) << SUPC_SR_LPDBCS_Pos)) +#define SUPC_SR_WKUPIS_Pos _U_(16) /**< (SUPC_SR Position) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS_Msk (_U_(0x3FFF) << SUPC_SR_WKUPIS_Pos) /**< (SUPC_SR Mask) WKUPIS */ +#define SUPC_SR_WKUPIS(value) (SUPC_SR_WKUPIS_Msk & ((value) << SUPC_SR_WKUPIS_Pos)) + +/** \brief SUPC register offsets definitions */ +#define SUPC_CR_REG_OFST (0x00) /**< (SUPC_CR) Supply Controller Control Register Offset */ +#define SUPC_SMMR_REG_OFST (0x04) /**< (SUPC_SMMR) Supply Controller Supply Monitor Mode Register Offset */ +#define SUPC_MR_REG_OFST (0x08) /**< (SUPC_MR) Supply Controller Mode Register Offset */ +#define SUPC_WUMR_REG_OFST (0x0C) /**< (SUPC_WUMR) Supply Controller Wake-up Mode Register Offset */ +#define SUPC_WUIR_REG_OFST (0x10) /**< (SUPC_WUIR) Supply Controller Wake-up Inputs Register Offset */ +#define SUPC_SR_REG_OFST (0x14) /**< (SUPC_SR) Supply Controller Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SUPC register API structure */ +typedef struct +{ + __O uint32_t SUPC_CR; /**< Offset: 0x00 ( /W 32) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< Offset: 0x04 (R/W 32) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< Offset: 0x08 (R/W 32) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< Offset: 0x0C (R/W 32) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< Offset: 0x10 (R/W 32) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< Offset: 0x14 (R/ 32) Supply Controller Status Register */ +} supc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SUPC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/tc.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/tc.h new file mode 100644 index 00000000..3b6d50e8 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/tc.h @@ -0,0 +1,542 @@ +/** + * \brief Component description for TC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_TC_COMPONENT_H_ +#define _SAME70_TC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TC */ +/* ************************************************************************** */ + +/* -------- TC_CCR : (TC Offset: 0x00) ( /W 32) Channel Control Register (channel = 0) -------- */ +#define TC_CCR_CLKEN_Pos _U_(0) /**< (TC_CCR) Counter Clock Enable Command Position */ +#define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */ +#define TC_CCR_CLKEN(value) (TC_CCR_CLKEN_Msk & ((value) << TC_CCR_CLKEN_Pos)) +#define TC_CCR_CLKDIS_Pos _U_(1) /**< (TC_CCR) Counter Clock Disable Command Position */ +#define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */ +#define TC_CCR_CLKDIS(value) (TC_CCR_CLKDIS_Msk & ((value) << TC_CCR_CLKDIS_Pos)) +#define TC_CCR_SWTRG_Pos _U_(2) /**< (TC_CCR) Software Trigger Command Position */ +#define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */ +#define TC_CCR_SWTRG(value) (TC_CCR_SWTRG_Msk & ((value) << TC_CCR_SWTRG_Pos)) +#define TC_CCR_Msk _U_(0x00000007) /**< (TC_CCR) Register Mask */ + + +/* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */ +#define TC_CMR_TCCLKS_Pos _U_(0) /**< (TC_CMR) Clock Selection Position */ +#define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */ +#define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) +#define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */ +#define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */ +#define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */ +#define TC_CMR_CLKI_Pos _U_(3) /**< (TC_CMR) Clock Invert Position */ +#define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */ +#define TC_CMR_CLKI(value) (TC_CMR_CLKI_Msk & ((value) << TC_CMR_CLKI_Pos)) +#define TC_CMR_BURST_Pos _U_(4) /**< (TC_CMR) Burst Signal Selection Position */ +#define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */ +#define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) +#define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ +#define TC_CMR_LDBSTOP_Pos _U_(6) /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ +#define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ +#define TC_CMR_LDBSTOP(value) (TC_CMR_LDBSTOP_Msk & ((value) << TC_CMR_LDBSTOP_Pos)) +#define TC_CMR_LDBDIS_Pos _U_(7) /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ +#define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ +#define TC_CMR_LDBDIS(value) (TC_CMR_LDBDIS_Msk & ((value) << TC_CMR_LDBDIS_Pos)) +#define TC_CMR_ETRGEDG_Pos _U_(8) /**< (TC_CMR) External Trigger Edge Selection Position */ +#define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ +#define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) +#define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */ +#define TC_CMR_ETRGEDG_NONE (TC_CMR_ETRGEDG_NONE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ +#define TC_CMR_ABETRG_Pos _U_(10) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ +#define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ +#define TC_CMR_ABETRG(value) (TC_CMR_ABETRG_Msk & ((value) << TC_CMR_ABETRG_Pos)) +#define TC_CMR_CPCTRG_Pos _U_(14) /**< (TC_CMR) RC Compare Trigger Enable Position */ +#define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ +#define TC_CMR_CPCTRG(value) (TC_CMR_CPCTRG_Msk & ((value) << TC_CMR_CPCTRG_Pos)) +#define TC_CMR_WAVE_Pos _U_(15) /**< (TC_CMR) Waveform Mode Position */ +#define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ +#define TC_CMR_WAVE(value) (TC_CMR_WAVE_Msk & ((value) << TC_CMR_WAVE_Pos)) +#define TC_CMR_LDRA_Pos _U_(16) /**< (TC_CMR) RA Loading Edge Selection Position */ +#define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ +#define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)) +#define TC_CMR_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */ +#define TC_CMR_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ +#define TC_CMR_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ +#define TC_CMR_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ +#define TC_CMR_LDRA_NONE (TC_CMR_LDRA_NONE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_LDRA_RISING (TC_CMR_LDRA_RISING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_LDRA_FALLING (TC_CMR_LDRA_FALLING_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_LDRA_EDGE (TC_CMR_LDRA_EDGE_Val << TC_CMR_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_LDRB_Pos _U_(18) /**< (TC_CMR) RB Loading Edge Selection Position */ +#define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ +#define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)) +#define TC_CMR_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */ +#define TC_CMR_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ +#define TC_CMR_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ +#define TC_CMR_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ +#define TC_CMR_LDRB_NONE (TC_CMR_LDRB_NONE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_LDRB_RISING (TC_CMR_LDRB_RISING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_LDRB_FALLING (TC_CMR_LDRB_FALLING_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_LDRB_EDGE (TC_CMR_LDRB_EDGE_Val << TC_CMR_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_SBSMPLR_Pos _U_(20) /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ +#define TC_CMR_SBSMPLR_Msk (_U_(0x7) << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ +#define TC_CMR_SBSMPLR(value) (TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)) +#define TC_CMR_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_SBSMPLR_ONE (TC_CMR_SBSMPLR_ONE_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ +#define TC_CMR_SBSMPLR_HALF (TC_CMR_SBSMPLR_HALF_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ +#define TC_CMR_SBSMPLR_FOURTH (TC_CMR_SBSMPLR_FOURTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ +#define TC_CMR_SBSMPLR_EIGHTH (TC_CMR_SBSMPLR_EIGHTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ +#define TC_CMR_SBSMPLR_SIXTEENTH (TC_CMR_SBSMPLR_SIXTEENTH_Val << TC_CMR_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ +#define TC_CMR_Msk _U_(0x007FC7FF) /**< (TC_CMR) Register Mask */ + + +/* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */ +#define TC_SMMR_GCEN_Pos _U_(0) /**< (TC_SMMR) Gray Count Enable Position */ +#define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */ +#define TC_SMMR_GCEN(value) (TC_SMMR_GCEN_Msk & ((value) << TC_SMMR_GCEN_Pos)) +#define TC_SMMR_DOWN_Pos _U_(1) /**< (TC_SMMR) Down Count Position */ +#define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */ +#define TC_SMMR_DOWN(value) (TC_SMMR_DOWN_Msk & ((value) << TC_SMMR_DOWN_Pos)) +#define TC_SMMR_Msk _U_(0x00000003) /**< (TC_SMMR) Register Mask */ + + +/* -------- TC_RAB : (TC Offset: 0x0C) ( R/ 32) Register AB (channel = 0) -------- */ +#define TC_RAB_RAB_Pos _U_(0) /**< (TC_RAB) Register A or Register B Position */ +#define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */ +#define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos)) +#define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */ + + +/* -------- TC_CV : (TC Offset: 0x10) ( R/ 32) Counter Value (channel = 0) -------- */ +#define TC_CV_CV_Pos _U_(0) /**< (TC_CV) Counter Value Position */ +#define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */ +#define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) +#define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */ + + +/* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */ +#define TC_RA_RA_Pos _U_(0) /**< (TC_RA) Register A Position */ +#define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */ +#define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) +#define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */ + + +/* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */ +#define TC_RB_RB_Pos _U_(0) /**< (TC_RB) Register B Position */ +#define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */ +#define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) +#define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */ + + +/* -------- TC_RC : (TC Offset: 0x1C) (R/W 32) Register C (channel = 0) -------- */ +#define TC_RC_RC_Pos _U_(0) /**< (TC_RC) Register C Position */ +#define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */ +#define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) +#define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */ + + +/* -------- TC_SR : (TC Offset: 0x20) ( R/ 32) Status Register (channel = 0) -------- */ +#define TC_SR_COVFS_Pos _U_(0) /**< (TC_SR) Counter Overflow Status (cleared on read) Position */ +#define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */ +#define TC_SR_COVFS(value) (TC_SR_COVFS_Msk & ((value) << TC_SR_COVFS_Pos)) +#define TC_SR_LOVRS_Pos _U_(1) /**< (TC_SR) Load Overrun Status (cleared on read) Position */ +#define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */ +#define TC_SR_LOVRS(value) (TC_SR_LOVRS_Msk & ((value) << TC_SR_LOVRS_Pos)) +#define TC_SR_CPAS_Pos _U_(2) /**< (TC_SR) RA Compare Status (cleared on read) Position */ +#define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */ +#define TC_SR_CPAS(value) (TC_SR_CPAS_Msk & ((value) << TC_SR_CPAS_Pos)) +#define TC_SR_CPBS_Pos _U_(3) /**< (TC_SR) RB Compare Status (cleared on read) Position */ +#define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */ +#define TC_SR_CPBS(value) (TC_SR_CPBS_Msk & ((value) << TC_SR_CPBS_Pos)) +#define TC_SR_CPCS_Pos _U_(4) /**< (TC_SR) RC Compare Status (cleared on read) Position */ +#define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */ +#define TC_SR_CPCS(value) (TC_SR_CPCS_Msk & ((value) << TC_SR_CPCS_Pos)) +#define TC_SR_LDRAS_Pos _U_(5) /**< (TC_SR) RA Loading Status (cleared on read) Position */ +#define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */ +#define TC_SR_LDRAS(value) (TC_SR_LDRAS_Msk & ((value) << TC_SR_LDRAS_Pos)) +#define TC_SR_LDRBS_Pos _U_(6) /**< (TC_SR) RB Loading Status (cleared on read) Position */ +#define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */ +#define TC_SR_LDRBS(value) (TC_SR_LDRBS_Msk & ((value) << TC_SR_LDRBS_Pos)) +#define TC_SR_ETRGS_Pos _U_(7) /**< (TC_SR) External Trigger Status (cleared on read) Position */ +#define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */ +#define TC_SR_ETRGS(value) (TC_SR_ETRGS_Msk & ((value) << TC_SR_ETRGS_Pos)) +#define TC_SR_CLKSTA_Pos _U_(16) /**< (TC_SR) Clock Enabling Status Position */ +#define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */ +#define TC_SR_CLKSTA(value) (TC_SR_CLKSTA_Msk & ((value) << TC_SR_CLKSTA_Pos)) +#define TC_SR_MTIOA_Pos _U_(17) /**< (TC_SR) TIOAx Mirror Position */ +#define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */ +#define TC_SR_MTIOA(value) (TC_SR_MTIOA_Msk & ((value) << TC_SR_MTIOA_Pos)) +#define TC_SR_MTIOB_Pos _U_(18) /**< (TC_SR) TIOBx Mirror Position */ +#define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */ +#define TC_SR_MTIOB(value) (TC_SR_MTIOB_Msk & ((value) << TC_SR_MTIOB_Pos)) +#define TC_SR_Msk _U_(0x000700FF) /**< (TC_SR) Register Mask */ + + +/* -------- TC_IER : (TC Offset: 0x24) ( /W 32) Interrupt Enable Register (channel = 0) -------- */ +#define TC_IER_COVFS_Pos _U_(0) /**< (TC_IER) Counter Overflow Position */ +#define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */ +#define TC_IER_COVFS(value) (TC_IER_COVFS_Msk & ((value) << TC_IER_COVFS_Pos)) +#define TC_IER_LOVRS_Pos _U_(1) /**< (TC_IER) Load Overrun Position */ +#define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */ +#define TC_IER_LOVRS(value) (TC_IER_LOVRS_Msk & ((value) << TC_IER_LOVRS_Pos)) +#define TC_IER_CPAS_Pos _U_(2) /**< (TC_IER) RA Compare Position */ +#define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */ +#define TC_IER_CPAS(value) (TC_IER_CPAS_Msk & ((value) << TC_IER_CPAS_Pos)) +#define TC_IER_CPBS_Pos _U_(3) /**< (TC_IER) RB Compare Position */ +#define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */ +#define TC_IER_CPBS(value) (TC_IER_CPBS_Msk & ((value) << TC_IER_CPBS_Pos)) +#define TC_IER_CPCS_Pos _U_(4) /**< (TC_IER) RC Compare Position */ +#define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */ +#define TC_IER_CPCS(value) (TC_IER_CPCS_Msk & ((value) << TC_IER_CPCS_Pos)) +#define TC_IER_LDRAS_Pos _U_(5) /**< (TC_IER) RA Loading Position */ +#define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */ +#define TC_IER_LDRAS(value) (TC_IER_LDRAS_Msk & ((value) << TC_IER_LDRAS_Pos)) +#define TC_IER_LDRBS_Pos _U_(6) /**< (TC_IER) RB Loading Position */ +#define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */ +#define TC_IER_LDRBS(value) (TC_IER_LDRBS_Msk & ((value) << TC_IER_LDRBS_Pos)) +#define TC_IER_ETRGS_Pos _U_(7) /**< (TC_IER) External Trigger Position */ +#define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */ +#define TC_IER_ETRGS(value) (TC_IER_ETRGS_Msk & ((value) << TC_IER_ETRGS_Pos)) +#define TC_IER_Msk _U_(0x000000FF) /**< (TC_IER) Register Mask */ + + +/* -------- TC_IDR : (TC Offset: 0x28) ( /W 32) Interrupt Disable Register (channel = 0) -------- */ +#define TC_IDR_COVFS_Pos _U_(0) /**< (TC_IDR) Counter Overflow Position */ +#define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */ +#define TC_IDR_COVFS(value) (TC_IDR_COVFS_Msk & ((value) << TC_IDR_COVFS_Pos)) +#define TC_IDR_LOVRS_Pos _U_(1) /**< (TC_IDR) Load Overrun Position */ +#define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */ +#define TC_IDR_LOVRS(value) (TC_IDR_LOVRS_Msk & ((value) << TC_IDR_LOVRS_Pos)) +#define TC_IDR_CPAS_Pos _U_(2) /**< (TC_IDR) RA Compare Position */ +#define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */ +#define TC_IDR_CPAS(value) (TC_IDR_CPAS_Msk & ((value) << TC_IDR_CPAS_Pos)) +#define TC_IDR_CPBS_Pos _U_(3) /**< (TC_IDR) RB Compare Position */ +#define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */ +#define TC_IDR_CPBS(value) (TC_IDR_CPBS_Msk & ((value) << TC_IDR_CPBS_Pos)) +#define TC_IDR_CPCS_Pos _U_(4) /**< (TC_IDR) RC Compare Position */ +#define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */ +#define TC_IDR_CPCS(value) (TC_IDR_CPCS_Msk & ((value) << TC_IDR_CPCS_Pos)) +#define TC_IDR_LDRAS_Pos _U_(5) /**< (TC_IDR) RA Loading Position */ +#define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */ +#define TC_IDR_LDRAS(value) (TC_IDR_LDRAS_Msk & ((value) << TC_IDR_LDRAS_Pos)) +#define TC_IDR_LDRBS_Pos _U_(6) /**< (TC_IDR) RB Loading Position */ +#define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */ +#define TC_IDR_LDRBS(value) (TC_IDR_LDRBS_Msk & ((value) << TC_IDR_LDRBS_Pos)) +#define TC_IDR_ETRGS_Pos _U_(7) /**< (TC_IDR) External Trigger Position */ +#define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */ +#define TC_IDR_ETRGS(value) (TC_IDR_ETRGS_Msk & ((value) << TC_IDR_ETRGS_Pos)) +#define TC_IDR_Msk _U_(0x000000FF) /**< (TC_IDR) Register Mask */ + + +/* -------- TC_IMR : (TC Offset: 0x2C) ( R/ 32) Interrupt Mask Register (channel = 0) -------- */ +#define TC_IMR_COVFS_Pos _U_(0) /**< (TC_IMR) Counter Overflow Position */ +#define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */ +#define TC_IMR_COVFS(value) (TC_IMR_COVFS_Msk & ((value) << TC_IMR_COVFS_Pos)) +#define TC_IMR_LOVRS_Pos _U_(1) /**< (TC_IMR) Load Overrun Position */ +#define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */ +#define TC_IMR_LOVRS(value) (TC_IMR_LOVRS_Msk & ((value) << TC_IMR_LOVRS_Pos)) +#define TC_IMR_CPAS_Pos _U_(2) /**< (TC_IMR) RA Compare Position */ +#define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */ +#define TC_IMR_CPAS(value) (TC_IMR_CPAS_Msk & ((value) << TC_IMR_CPAS_Pos)) +#define TC_IMR_CPBS_Pos _U_(3) /**< (TC_IMR) RB Compare Position */ +#define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */ +#define TC_IMR_CPBS(value) (TC_IMR_CPBS_Msk & ((value) << TC_IMR_CPBS_Pos)) +#define TC_IMR_CPCS_Pos _U_(4) /**< (TC_IMR) RC Compare Position */ +#define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */ +#define TC_IMR_CPCS(value) (TC_IMR_CPCS_Msk & ((value) << TC_IMR_CPCS_Pos)) +#define TC_IMR_LDRAS_Pos _U_(5) /**< (TC_IMR) RA Loading Position */ +#define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */ +#define TC_IMR_LDRAS(value) (TC_IMR_LDRAS_Msk & ((value) << TC_IMR_LDRAS_Pos)) +#define TC_IMR_LDRBS_Pos _U_(6) /**< (TC_IMR) RB Loading Position */ +#define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */ +#define TC_IMR_LDRBS(value) (TC_IMR_LDRBS_Msk & ((value) << TC_IMR_LDRBS_Pos)) +#define TC_IMR_ETRGS_Pos _U_(7) /**< (TC_IMR) External Trigger Position */ +#define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */ +#define TC_IMR_ETRGS(value) (TC_IMR_ETRGS_Msk & ((value) << TC_IMR_ETRGS_Pos)) +#define TC_IMR_Msk _U_(0x000000FF) /**< (TC_IMR) Register Mask */ + + +/* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */ +#define TC_EMR_TRIGSRCA_Pos _U_(0) /**< (TC_EMR) Trigger Source for Input A Position */ +#define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */ +#define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */ +#define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */ +#define TC_EMR_TRIGSRCB_Pos _U_(4) /**< (TC_EMR) Trigger Source for Input B Position */ +#define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */ +#define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */ +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */ +#define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */ +#define TC_EMR_NODIVCLK_Pos _U_(8) /**< (TC_EMR) No Divided Clock Position */ +#define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */ +#define TC_EMR_NODIVCLK(value) (TC_EMR_NODIVCLK_Msk & ((value) << TC_EMR_NODIVCLK_Pos)) +#define TC_EMR_Msk _U_(0x00000133) /**< (TC_EMR) Register Mask */ + + +/* -------- TC_BCR : (TC Offset: 0xC0) ( /W 32) Block Control Register -------- */ +#define TC_BCR_SYNC_Pos _U_(0) /**< (TC_BCR) Synchro Command Position */ +#define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */ +#define TC_BCR_SYNC(value) (TC_BCR_SYNC_Msk & ((value) << TC_BCR_SYNC_Pos)) +#define TC_BCR_Msk _U_(0x00000001) /**< (TC_BCR) Register Mask */ + + +/* -------- TC_BMR : (TC Offset: 0xC4) (R/W 32) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos _U_(0) /**< (TC_BMR) External Clock Signal 0 Selection Position */ +#define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */ +#define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) +#define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */ +#define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */ +#define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */ +#define TC_BMR_TC1XC1S_Pos _U_(2) /**< (TC_BMR) External Clock Signal 1 Selection Position */ +#define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */ +#define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) +#define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */ +#define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */ +#define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */ +#define TC_BMR_TC2XC2S_Pos _U_(4) /**< (TC_BMR) External Clock Signal 2 Selection Position */ +#define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */ +#define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) +#define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */ +#define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */ +#define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */ +#define TC_BMR_QDEN_Pos _U_(8) /**< (TC_BMR) Quadrature Decoder Enabled Position */ +#define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */ +#define TC_BMR_QDEN(value) (TC_BMR_QDEN_Msk & ((value) << TC_BMR_QDEN_Pos)) +#define TC_BMR_POSEN_Pos _U_(9) /**< (TC_BMR) Position Enabled Position */ +#define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */ +#define TC_BMR_POSEN(value) (TC_BMR_POSEN_Msk & ((value) << TC_BMR_POSEN_Pos)) +#define TC_BMR_SPEEDEN_Pos _U_(10) /**< (TC_BMR) Speed Enabled Position */ +#define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */ +#define TC_BMR_SPEEDEN(value) (TC_BMR_SPEEDEN_Msk & ((value) << TC_BMR_SPEEDEN_Pos)) +#define TC_BMR_QDTRANS_Pos _U_(11) /**< (TC_BMR) Quadrature Decoding Transparent Position */ +#define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */ +#define TC_BMR_QDTRANS(value) (TC_BMR_QDTRANS_Msk & ((value) << TC_BMR_QDTRANS_Pos)) +#define TC_BMR_EDGPHA_Pos _U_(12) /**< (TC_BMR) Edge on PHA Count Mode Position */ +#define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */ +#define TC_BMR_EDGPHA(value) (TC_BMR_EDGPHA_Msk & ((value) << TC_BMR_EDGPHA_Pos)) +#define TC_BMR_INVA_Pos _U_(13) /**< (TC_BMR) Inverted PHA Position */ +#define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */ +#define TC_BMR_INVA(value) (TC_BMR_INVA_Msk & ((value) << TC_BMR_INVA_Pos)) +#define TC_BMR_INVB_Pos _U_(14) /**< (TC_BMR) Inverted PHB Position */ +#define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */ +#define TC_BMR_INVB(value) (TC_BMR_INVB_Msk & ((value) << TC_BMR_INVB_Pos)) +#define TC_BMR_INVIDX_Pos _U_(15) /**< (TC_BMR) Inverted Index Position */ +#define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */ +#define TC_BMR_INVIDX(value) (TC_BMR_INVIDX_Msk & ((value) << TC_BMR_INVIDX_Pos)) +#define TC_BMR_SWAP_Pos _U_(16) /**< (TC_BMR) Swap PHA and PHB Position */ +#define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */ +#define TC_BMR_SWAP(value) (TC_BMR_SWAP_Msk & ((value) << TC_BMR_SWAP_Pos)) +#define TC_BMR_IDXPHB_Pos _U_(17) /**< (TC_BMR) Index Pin is PHB Pin Position */ +#define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */ +#define TC_BMR_IDXPHB(value) (TC_BMR_IDXPHB_Msk & ((value) << TC_BMR_IDXPHB_Pos)) +#define TC_BMR_MAXFILT_Pos _U_(20) /**< (TC_BMR) Maximum Filter Position */ +#define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */ +#define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)) +#define TC_BMR_Msk _U_(0x03F3FF3F) /**< (TC_BMR) Register Mask */ + + +/* -------- TC_QIER : (TC Offset: 0xC8) ( /W 32) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX_Pos _U_(0) /**< (TC_QIER) Index Position */ +#define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */ +#define TC_QIER_IDX(value) (TC_QIER_IDX_Msk & ((value) << TC_QIER_IDX_Pos)) +#define TC_QIER_DIRCHG_Pos _U_(1) /**< (TC_QIER) Direction Change Position */ +#define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */ +#define TC_QIER_DIRCHG(value) (TC_QIER_DIRCHG_Msk & ((value) << TC_QIER_DIRCHG_Pos)) +#define TC_QIER_QERR_Pos _U_(2) /**< (TC_QIER) Quadrature Error Position */ +#define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */ +#define TC_QIER_QERR(value) (TC_QIER_QERR_Msk & ((value) << TC_QIER_QERR_Pos)) +#define TC_QIER_Msk _U_(0x00000007) /**< (TC_QIER) Register Mask */ + + +/* -------- TC_QIDR : (TC Offset: 0xCC) ( /W 32) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX_Pos _U_(0) /**< (TC_QIDR) Index Position */ +#define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */ +#define TC_QIDR_IDX(value) (TC_QIDR_IDX_Msk & ((value) << TC_QIDR_IDX_Pos)) +#define TC_QIDR_DIRCHG_Pos _U_(1) /**< (TC_QIDR) Direction Change Position */ +#define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */ +#define TC_QIDR_DIRCHG(value) (TC_QIDR_DIRCHG_Msk & ((value) << TC_QIDR_DIRCHG_Pos)) +#define TC_QIDR_QERR_Pos _U_(2) /**< (TC_QIDR) Quadrature Error Position */ +#define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */ +#define TC_QIDR_QERR(value) (TC_QIDR_QERR_Msk & ((value) << TC_QIDR_QERR_Pos)) +#define TC_QIDR_Msk _U_(0x00000007) /**< (TC_QIDR) Register Mask */ + + +/* -------- TC_QIMR : (TC Offset: 0xD0) ( R/ 32) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX_Pos _U_(0) /**< (TC_QIMR) Index Position */ +#define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */ +#define TC_QIMR_IDX(value) (TC_QIMR_IDX_Msk & ((value) << TC_QIMR_IDX_Pos)) +#define TC_QIMR_DIRCHG_Pos _U_(1) /**< (TC_QIMR) Direction Change Position */ +#define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */ +#define TC_QIMR_DIRCHG(value) (TC_QIMR_DIRCHG_Msk & ((value) << TC_QIMR_DIRCHG_Pos)) +#define TC_QIMR_QERR_Pos _U_(2) /**< (TC_QIMR) Quadrature Error Position */ +#define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */ +#define TC_QIMR_QERR(value) (TC_QIMR_QERR_Msk & ((value) << TC_QIMR_QERR_Pos)) +#define TC_QIMR_Msk _U_(0x00000007) /**< (TC_QIMR) Register Mask */ + + +/* -------- TC_QISR : (TC Offset: 0xD4) ( R/ 32) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX_Pos _U_(0) /**< (TC_QISR) Index Position */ +#define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */ +#define TC_QISR_IDX(value) (TC_QISR_IDX_Msk & ((value) << TC_QISR_IDX_Pos)) +#define TC_QISR_DIRCHG_Pos _U_(1) /**< (TC_QISR) Direction Change Position */ +#define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */ +#define TC_QISR_DIRCHG(value) (TC_QISR_DIRCHG_Msk & ((value) << TC_QISR_DIRCHG_Pos)) +#define TC_QISR_QERR_Pos _U_(2) /**< (TC_QISR) Quadrature Error Position */ +#define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */ +#define TC_QISR_QERR(value) (TC_QISR_QERR_Msk & ((value) << TC_QISR_QERR_Pos)) +#define TC_QISR_DIR_Pos _U_(8) /**< (TC_QISR) Direction Position */ +#define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */ +#define TC_QISR_DIR(value) (TC_QISR_DIR_Msk & ((value) << TC_QISR_DIR_Pos)) +#define TC_QISR_Msk _U_(0x00000107) /**< (TC_QISR) Register Mask */ + + +/* -------- TC_FMR : (TC Offset: 0xD8) (R/W 32) Fault Mode Register -------- */ +#define TC_FMR_ENCF0_Pos _U_(0) /**< (TC_FMR) Enable Compare Fault Channel 0 Position */ +#define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */ +#define TC_FMR_ENCF0(value) (TC_FMR_ENCF0_Msk & ((value) << TC_FMR_ENCF0_Pos)) +#define TC_FMR_ENCF1_Pos _U_(1) /**< (TC_FMR) Enable Compare Fault Channel 1 Position */ +#define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */ +#define TC_FMR_ENCF1(value) (TC_FMR_ENCF1_Msk & ((value) << TC_FMR_ENCF1_Pos)) +#define TC_FMR_Msk _U_(0x00000003) /**< (TC_FMR) Register Mask */ + +#define TC_FMR_ENCF_Pos _U_(0) /**< (TC_FMR Position) Enable Compare Fault Channel x */ +#define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */ +#define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos)) + +/* -------- TC_WPMR : (TC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN_Pos _U_(0) /**< (TC_WPMR) Write Protection Enable Position */ +#define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */ +#define TC_WPMR_WPEN(value) (TC_WPMR_WPEN_Msk & ((value) << TC_WPMR_WPEN_Pos)) +#define TC_WPMR_WPKEY_Pos _U_(8) /**< (TC_WPMR) Write Protection Key Position */ +#define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */ +#define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) +#define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */ + + +/** \brief TC register offsets definitions */ +#define TC_CCR_REG_OFST (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */ +#define TC_CMR_REG_OFST (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */ +#define TC_SMMR_REG_OFST (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */ +#define TC_RAB_REG_OFST (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */ +#define TC_CV_REG_OFST (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */ +#define TC_RA_REG_OFST (0x14) /**< (TC_RA) Register A (channel = 0) Offset */ +#define TC_RB_REG_OFST (0x18) /**< (TC_RB) Register B (channel = 0) Offset */ +#define TC_RC_REG_OFST (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */ +#define TC_SR_REG_OFST (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */ +#define TC_IER_REG_OFST (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */ +#define TC_IDR_REG_OFST (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */ +#define TC_IMR_REG_OFST (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */ +#define TC_EMR_REG_OFST (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */ +#define TC_BCR_REG_OFST (0xC0) /**< (TC_BCR) Block Control Register Offset */ +#define TC_BMR_REG_OFST (0xC4) /**< (TC_BMR) Block Mode Register Offset */ +#define TC_QIER_REG_OFST (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */ +#define TC_QIDR_REG_OFST (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */ +#define TC_QIMR_REG_OFST (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */ +#define TC_QISR_REG_OFST (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */ +#define TC_FMR_REG_OFST (0xD8) /**< (TC_FMR) Fault Mode Register Offset */ +#define TC_WPMR_REG_OFST (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TC_CHANNEL register API structure */ +typedef struct +{ + __O uint32_t TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */ + __IO uint32_t TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */ + __IO uint32_t TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */ + __I uint32_t TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */ + __I uint32_t TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */ + __IO uint32_t TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */ + __IO uint32_t TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */ + __IO uint32_t TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */ + __I uint32_t TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */ + __O uint32_t TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */ + __O uint32_t TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */ + __I uint32_t TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */ + __IO uint32_t TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */ + __I uint8_t Reserved1[0x0C]; +} tc_channel_registers_t; + +#define TC_CHANNEL_NUMBER _U_(3) + +/** \brief TC register API structure */ +typedef struct +{ + tc_channel_registers_t TC_CHANNEL[TC_CHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ + __O uint32_t TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */ + __IO uint32_t TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */ + __O uint32_t TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */ + __I uint8_t Reserved1[0x08]; + __IO uint32_t TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} tc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/trng.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/trng.h new file mode 100644 index 00000000..263e0867 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/trng.h @@ -0,0 +1,102 @@ +/** + * \brief Component description for TRNG + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_TRNG_COMPONENT_H_ +#define _SAME70_TRNG_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TRNG */ +/* ************************************************************************** */ + +/* -------- TRNG_CR : (TRNG Offset: 0x00) ( /W 32) Control Register -------- */ +#define TRNG_CR_ENABLE_Pos _U_(0) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Position */ +#define TRNG_CR_ENABLE_Msk (_U_(0x1) << TRNG_CR_ENABLE_Pos) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Mask */ +#define TRNG_CR_ENABLE(value) (TRNG_CR_ENABLE_Msk & ((value) << TRNG_CR_ENABLE_Pos)) +#define TRNG_CR_KEY_Pos _U_(8) /**< (TRNG_CR) Security Key Position */ +#define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Security Key Mask */ +#define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)) +#define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */ +#define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */ +#define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */ + + +/* -------- TRNG_IER : (TRNG Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY_Pos _U_(0) /**< (TRNG_IER) Data Ready Interrupt Enable Position */ +#define TRNG_IER_DATRDY_Msk (_U_(0x1) << TRNG_IER_DATRDY_Pos) /**< (TRNG_IER) Data Ready Interrupt Enable Mask */ +#define TRNG_IER_DATRDY(value) (TRNG_IER_DATRDY_Msk & ((value) << TRNG_IER_DATRDY_Pos)) +#define TRNG_IER_Msk _U_(0x00000001) /**< (TRNG_IER) Register Mask */ + + +/* -------- TRNG_IDR : (TRNG Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY_Pos _U_(0) /**< (TRNG_IDR) Data Ready Interrupt Disable Position */ +#define TRNG_IDR_DATRDY_Msk (_U_(0x1) << TRNG_IDR_DATRDY_Pos) /**< (TRNG_IDR) Data Ready Interrupt Disable Mask */ +#define TRNG_IDR_DATRDY(value) (TRNG_IDR_DATRDY_Msk & ((value) << TRNG_IDR_DATRDY_Pos)) +#define TRNG_IDR_Msk _U_(0x00000001) /**< (TRNG_IDR) Register Mask */ + + +/* -------- TRNG_IMR : (TRNG Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY_Pos _U_(0) /**< (TRNG_IMR) Data Ready Interrupt Mask Position */ +#define TRNG_IMR_DATRDY_Msk (_U_(0x1) << TRNG_IMR_DATRDY_Pos) /**< (TRNG_IMR) Data Ready Interrupt Mask Mask */ +#define TRNG_IMR_DATRDY(value) (TRNG_IMR_DATRDY_Msk & ((value) << TRNG_IMR_DATRDY_Pos)) +#define TRNG_IMR_Msk _U_(0x00000001) /**< (TRNG_IMR) Register Mask */ + + +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY_Pos _U_(0) /**< (TRNG_ISR) Data Ready Position */ +#define TRNG_ISR_DATRDY_Msk (_U_(0x1) << TRNG_ISR_DATRDY_Pos) /**< (TRNG_ISR) Data Ready Mask */ +#define TRNG_ISR_DATRDY(value) (TRNG_ISR_DATRDY_Msk & ((value) << TRNG_ISR_DATRDY_Pos)) +#define TRNG_ISR_Msk _U_(0x00000001) /**< (TRNG_ISR) Register Mask */ + + +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) ( R/ 32) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos _U_(0) /**< (TRNG_ODATA) Output Data Position */ +#define TRNG_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << TRNG_ODATA_ODATA_Pos) /**< (TRNG_ODATA) Output Data Mask */ +#define TRNG_ODATA_ODATA(value) (TRNG_ODATA_ODATA_Msk & ((value) << TRNG_ODATA_ODATA_Pos)) +#define TRNG_ODATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_ODATA) Register Mask */ + + +/** \brief TRNG register offsets definitions */ +#define TRNG_CR_REG_OFST (0x00) /**< (TRNG_CR) Control Register Offset */ +#define TRNG_IER_REG_OFST (0x10) /**< (TRNG_IER) Interrupt Enable Register Offset */ +#define TRNG_IDR_REG_OFST (0x14) /**< (TRNG_IDR) Interrupt Disable Register Offset */ +#define TRNG_IMR_REG_OFST (0x18) /**< (TRNG_IMR) Interrupt Mask Register Offset */ +#define TRNG_ISR_REG_OFST (0x1C) /**< (TRNG_ISR) Interrupt Status Register Offset */ +#define TRNG_ODATA_REG_OFST (0x50) /**< (TRNG_ODATA) Output Data Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TRNG register API structure */ +typedef struct +{ + __O uint32_t TRNG_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t TRNG_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x30]; + __I uint32_t TRNG_ODATA; /**< Offset: 0x50 (R/ 32) Output Data Register */ +} trng_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TRNG_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/twihs.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/twihs.h new file mode 100644 index 00000000..410396ea --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/twihs.h @@ -0,0 +1,526 @@ +/** + * \brief Component description for TWIHS + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_TWIHS_COMPONENT_H_ +#define _SAME70_TWIHS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TWIHS */ +/* ************************************************************************** */ + +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) ( /W 32) Control Register -------- */ +#define TWIHS_CR_START_Pos _U_(0) /**< (TWIHS_CR) Send a START Condition Position */ +#define TWIHS_CR_START_Msk (_U_(0x1) << TWIHS_CR_START_Pos) /**< (TWIHS_CR) Send a START Condition Mask */ +#define TWIHS_CR_START(value) (TWIHS_CR_START_Msk & ((value) << TWIHS_CR_START_Pos)) +#define TWIHS_CR_STOP_Pos _U_(1) /**< (TWIHS_CR) Send a STOP Condition Position */ +#define TWIHS_CR_STOP_Msk (_U_(0x1) << TWIHS_CR_STOP_Pos) /**< (TWIHS_CR) Send a STOP Condition Mask */ +#define TWIHS_CR_STOP(value) (TWIHS_CR_STOP_Msk & ((value) << TWIHS_CR_STOP_Pos)) +#define TWIHS_CR_MSEN_Pos _U_(2) /**< (TWIHS_CR) TWIHS Master Mode Enabled Position */ +#define TWIHS_CR_MSEN_Msk (_U_(0x1) << TWIHS_CR_MSEN_Pos) /**< (TWIHS_CR) TWIHS Master Mode Enabled Mask */ +#define TWIHS_CR_MSEN(value) (TWIHS_CR_MSEN_Msk & ((value) << TWIHS_CR_MSEN_Pos)) +#define TWIHS_CR_MSDIS_Pos _U_(3) /**< (TWIHS_CR) TWIHS Master Mode Disabled Position */ +#define TWIHS_CR_MSDIS_Msk (_U_(0x1) << TWIHS_CR_MSDIS_Pos) /**< (TWIHS_CR) TWIHS Master Mode Disabled Mask */ +#define TWIHS_CR_MSDIS(value) (TWIHS_CR_MSDIS_Msk & ((value) << TWIHS_CR_MSDIS_Pos)) +#define TWIHS_CR_SVEN_Pos _U_(4) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Position */ +#define TWIHS_CR_SVEN_Msk (_U_(0x1) << TWIHS_CR_SVEN_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Mask */ +#define TWIHS_CR_SVEN(value) (TWIHS_CR_SVEN_Msk & ((value) << TWIHS_CR_SVEN_Pos)) +#define TWIHS_CR_SVDIS_Pos _U_(5) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Position */ +#define TWIHS_CR_SVDIS_Msk (_U_(0x1) << TWIHS_CR_SVDIS_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Mask */ +#define TWIHS_CR_SVDIS(value) (TWIHS_CR_SVDIS_Msk & ((value) << TWIHS_CR_SVDIS_Pos)) +#define TWIHS_CR_QUICK_Pos _U_(6) /**< (TWIHS_CR) SMBus Quick Command Position */ +#define TWIHS_CR_QUICK_Msk (_U_(0x1) << TWIHS_CR_QUICK_Pos) /**< (TWIHS_CR) SMBus Quick Command Mask */ +#define TWIHS_CR_QUICK(value) (TWIHS_CR_QUICK_Msk & ((value) << TWIHS_CR_QUICK_Pos)) +#define TWIHS_CR_SWRST_Pos _U_(7) /**< (TWIHS_CR) Software Reset Position */ +#define TWIHS_CR_SWRST_Msk (_U_(0x1) << TWIHS_CR_SWRST_Pos) /**< (TWIHS_CR) Software Reset Mask */ +#define TWIHS_CR_SWRST(value) (TWIHS_CR_SWRST_Msk & ((value) << TWIHS_CR_SWRST_Pos)) +#define TWIHS_CR_HSEN_Pos _U_(8) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Position */ +#define TWIHS_CR_HSEN_Msk (_U_(0x1) << TWIHS_CR_HSEN_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Mask */ +#define TWIHS_CR_HSEN(value) (TWIHS_CR_HSEN_Msk & ((value) << TWIHS_CR_HSEN_Pos)) +#define TWIHS_CR_HSDIS_Pos _U_(9) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Position */ +#define TWIHS_CR_HSDIS_Msk (_U_(0x1) << TWIHS_CR_HSDIS_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Mask */ +#define TWIHS_CR_HSDIS(value) (TWIHS_CR_HSDIS_Msk & ((value) << TWIHS_CR_HSDIS_Pos)) +#define TWIHS_CR_SMBEN_Pos _U_(10) /**< (TWIHS_CR) SMBus Mode Enabled Position */ +#define TWIHS_CR_SMBEN_Msk (_U_(0x1) << TWIHS_CR_SMBEN_Pos) /**< (TWIHS_CR) SMBus Mode Enabled Mask */ +#define TWIHS_CR_SMBEN(value) (TWIHS_CR_SMBEN_Msk & ((value) << TWIHS_CR_SMBEN_Pos)) +#define TWIHS_CR_SMBDIS_Pos _U_(11) /**< (TWIHS_CR) SMBus Mode Disabled Position */ +#define TWIHS_CR_SMBDIS_Msk (_U_(0x1) << TWIHS_CR_SMBDIS_Pos) /**< (TWIHS_CR) SMBus Mode Disabled Mask */ +#define TWIHS_CR_SMBDIS(value) (TWIHS_CR_SMBDIS_Msk & ((value) << TWIHS_CR_SMBDIS_Pos)) +#define TWIHS_CR_PECEN_Pos _U_(12) /**< (TWIHS_CR) Packet Error Checking Enable Position */ +#define TWIHS_CR_PECEN_Msk (_U_(0x1) << TWIHS_CR_PECEN_Pos) /**< (TWIHS_CR) Packet Error Checking Enable Mask */ +#define TWIHS_CR_PECEN(value) (TWIHS_CR_PECEN_Msk & ((value) << TWIHS_CR_PECEN_Pos)) +#define TWIHS_CR_PECDIS_Pos _U_(13) /**< (TWIHS_CR) Packet Error Checking Disable Position */ +#define TWIHS_CR_PECDIS_Msk (_U_(0x1) << TWIHS_CR_PECDIS_Pos) /**< (TWIHS_CR) Packet Error Checking Disable Mask */ +#define TWIHS_CR_PECDIS(value) (TWIHS_CR_PECDIS_Msk & ((value) << TWIHS_CR_PECDIS_Pos)) +#define TWIHS_CR_PECRQ_Pos _U_(14) /**< (TWIHS_CR) PEC Request Position */ +#define TWIHS_CR_PECRQ_Msk (_U_(0x1) << TWIHS_CR_PECRQ_Pos) /**< (TWIHS_CR) PEC Request Mask */ +#define TWIHS_CR_PECRQ(value) (TWIHS_CR_PECRQ_Msk & ((value) << TWIHS_CR_PECRQ_Pos)) +#define TWIHS_CR_CLEAR_Pos _U_(15) /**< (TWIHS_CR) Bus CLEAR Command Position */ +#define TWIHS_CR_CLEAR_Msk (_U_(0x1) << TWIHS_CR_CLEAR_Pos) /**< (TWIHS_CR) Bus CLEAR Command Mask */ +#define TWIHS_CR_CLEAR(value) (TWIHS_CR_CLEAR_Msk & ((value) << TWIHS_CR_CLEAR_Pos)) +#define TWIHS_CR_ACMEN_Pos _U_(16) /**< (TWIHS_CR) Alternative Command Mode Enable Position */ +#define TWIHS_CR_ACMEN_Msk (_U_(0x1) << TWIHS_CR_ACMEN_Pos) /**< (TWIHS_CR) Alternative Command Mode Enable Mask */ +#define TWIHS_CR_ACMEN(value) (TWIHS_CR_ACMEN_Msk & ((value) << TWIHS_CR_ACMEN_Pos)) +#define TWIHS_CR_ACMDIS_Pos _U_(17) /**< (TWIHS_CR) Alternative Command Mode Disable Position */ +#define TWIHS_CR_ACMDIS_Msk (_U_(0x1) << TWIHS_CR_ACMDIS_Pos) /**< (TWIHS_CR) Alternative Command Mode Disable Mask */ +#define TWIHS_CR_ACMDIS(value) (TWIHS_CR_ACMDIS_Msk & ((value) << TWIHS_CR_ACMDIS_Pos)) +#define TWIHS_CR_THRCLR_Pos _U_(24) /**< (TWIHS_CR) Transmit Holding Register Clear Position */ +#define TWIHS_CR_THRCLR_Msk (_U_(0x1) << TWIHS_CR_THRCLR_Pos) /**< (TWIHS_CR) Transmit Holding Register Clear Mask */ +#define TWIHS_CR_THRCLR(value) (TWIHS_CR_THRCLR_Msk & ((value) << TWIHS_CR_THRCLR_Pos)) +#define TWIHS_CR_LOCKCLR_Pos _U_(26) /**< (TWIHS_CR) Lock Clear Position */ +#define TWIHS_CR_LOCKCLR_Msk (_U_(0x1) << TWIHS_CR_LOCKCLR_Pos) /**< (TWIHS_CR) Lock Clear Mask */ +#define TWIHS_CR_LOCKCLR(value) (TWIHS_CR_LOCKCLR_Msk & ((value) << TWIHS_CR_LOCKCLR_Pos)) +#define TWIHS_CR_FIFOEN_Pos _U_(28) /**< (TWIHS_CR) FIFO Enable Position */ +#define TWIHS_CR_FIFOEN_Msk (_U_(0x1) << TWIHS_CR_FIFOEN_Pos) /**< (TWIHS_CR) FIFO Enable Mask */ +#define TWIHS_CR_FIFOEN(value) (TWIHS_CR_FIFOEN_Msk & ((value) << TWIHS_CR_FIFOEN_Pos)) +#define TWIHS_CR_FIFODIS_Pos _U_(29) /**< (TWIHS_CR) FIFO Disable Position */ +#define TWIHS_CR_FIFODIS_Msk (_U_(0x1) << TWIHS_CR_FIFODIS_Pos) /**< (TWIHS_CR) FIFO Disable Mask */ +#define TWIHS_CR_FIFODIS(value) (TWIHS_CR_FIFODIS_Msk & ((value) << TWIHS_CR_FIFODIS_Pos)) +#define TWIHS_CR_Msk _U_(0x3503FFFF) /**< (TWIHS_CR) Register Mask */ + + +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) (R/W 32) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos _U_(8) /**< (TWIHS_MMR) Internal Device Address Size Position */ +#define TWIHS_MMR_IADRSZ_Msk (_U_(0x3) << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Internal Device Address Size Mask */ +#define TWIHS_MMR_IADRSZ(value) (TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)) +#define TWIHS_MMR_IADRSZ_NONE_Val _U_(0x0) /**< (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE_Val _U_(0x1) /**< (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE_Val _U_(0x2) /**< (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE_Val _U_(0x3) /**< (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_IADRSZ_NONE (TWIHS_MMR_IADRSZ_NONE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) No internal device address Position */ +#define TWIHS_MMR_IADRSZ_1_BYTE (TWIHS_MMR_IADRSZ_1_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) One-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_2_BYTE (TWIHS_MMR_IADRSZ_2_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Two-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_3_BYTE (TWIHS_MMR_IADRSZ_3_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Three-byte internal device address Position */ +#define TWIHS_MMR_MREAD_Pos _U_(12) /**< (TWIHS_MMR) Master Read Direction Position */ +#define TWIHS_MMR_MREAD_Msk (_U_(0x1) << TWIHS_MMR_MREAD_Pos) /**< (TWIHS_MMR) Master Read Direction Mask */ +#define TWIHS_MMR_MREAD(value) (TWIHS_MMR_MREAD_Msk & ((value) << TWIHS_MMR_MREAD_Pos)) +#define TWIHS_MMR_DADR_Pos _U_(16) /**< (TWIHS_MMR) Device Address Position */ +#define TWIHS_MMR_DADR_Msk (_U_(0x7F) << TWIHS_MMR_DADR_Pos) /**< (TWIHS_MMR) Device Address Mask */ +#define TWIHS_MMR_DADR(value) (TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)) +#define TWIHS_MMR_Msk _U_(0x007F1300) /**< (TWIHS_MMR) Register Mask */ + + +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) (R/W 32) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN_Pos _U_(0) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Position */ +#define TWIHS_SMR_NACKEN_Msk (_U_(0x1) << TWIHS_SMR_NACKEN_Pos) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Mask */ +#define TWIHS_SMR_NACKEN(value) (TWIHS_SMR_NACKEN_Msk & ((value) << TWIHS_SMR_NACKEN_Pos)) +#define TWIHS_SMR_SMDA_Pos _U_(2) /**< (TWIHS_SMR) SMBus Default Address Position */ +#define TWIHS_SMR_SMDA_Msk (_U_(0x1) << TWIHS_SMR_SMDA_Pos) /**< (TWIHS_SMR) SMBus Default Address Mask */ +#define TWIHS_SMR_SMDA(value) (TWIHS_SMR_SMDA_Msk & ((value) << TWIHS_SMR_SMDA_Pos)) +#define TWIHS_SMR_SMHH_Pos _U_(3) /**< (TWIHS_SMR) SMBus Host Header Position */ +#define TWIHS_SMR_SMHH_Msk (_U_(0x1) << TWIHS_SMR_SMHH_Pos) /**< (TWIHS_SMR) SMBus Host Header Mask */ +#define TWIHS_SMR_SMHH(value) (TWIHS_SMR_SMHH_Msk & ((value) << TWIHS_SMR_SMHH_Pos)) +#define TWIHS_SMR_SCLWSDIS_Pos _U_(6) /**< (TWIHS_SMR) Clock Wait State Disable Position */ +#define TWIHS_SMR_SCLWSDIS_Msk (_U_(0x1) << TWIHS_SMR_SCLWSDIS_Pos) /**< (TWIHS_SMR) Clock Wait State Disable Mask */ +#define TWIHS_SMR_SCLWSDIS(value) (TWIHS_SMR_SCLWSDIS_Msk & ((value) << TWIHS_SMR_SCLWSDIS_Pos)) +#define TWIHS_SMR_MASK_Pos _U_(8) /**< (TWIHS_SMR) Slave Address Mask Position */ +#define TWIHS_SMR_MASK_Msk (_U_(0x7F) << TWIHS_SMR_MASK_Pos) /**< (TWIHS_SMR) Slave Address Mask Mask */ +#define TWIHS_SMR_MASK(value) (TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)) +#define TWIHS_SMR_SADR_Pos _U_(16) /**< (TWIHS_SMR) Slave Address Position */ +#define TWIHS_SMR_SADR_Msk (_U_(0x7F) << TWIHS_SMR_SADR_Pos) /**< (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_SADR(value) (TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)) +#define TWIHS_SMR_SADR1EN_Pos _U_(28) /**< (TWIHS_SMR) Slave Address 1 Enable Position */ +#define TWIHS_SMR_SADR1EN_Msk (_U_(0x1) << TWIHS_SMR_SADR1EN_Pos) /**< (TWIHS_SMR) Slave Address 1 Enable Mask */ +#define TWIHS_SMR_SADR1EN(value) (TWIHS_SMR_SADR1EN_Msk & ((value) << TWIHS_SMR_SADR1EN_Pos)) +#define TWIHS_SMR_SADR2EN_Pos _U_(29) /**< (TWIHS_SMR) Slave Address 2 Enable Position */ +#define TWIHS_SMR_SADR2EN_Msk (_U_(0x1) << TWIHS_SMR_SADR2EN_Pos) /**< (TWIHS_SMR) Slave Address 2 Enable Mask */ +#define TWIHS_SMR_SADR2EN(value) (TWIHS_SMR_SADR2EN_Msk & ((value) << TWIHS_SMR_SADR2EN_Pos)) +#define TWIHS_SMR_SADR3EN_Pos _U_(30) /**< (TWIHS_SMR) Slave Address 3 Enable Position */ +#define TWIHS_SMR_SADR3EN_Msk (_U_(0x1) << TWIHS_SMR_SADR3EN_Pos) /**< (TWIHS_SMR) Slave Address 3 Enable Mask */ +#define TWIHS_SMR_SADR3EN(value) (TWIHS_SMR_SADR3EN_Msk & ((value) << TWIHS_SMR_SADR3EN_Pos)) +#define TWIHS_SMR_DATAMEN_Pos _U_(31) /**< (TWIHS_SMR) Data Matching Enable Position */ +#define TWIHS_SMR_DATAMEN_Msk (_U_(0x1) << TWIHS_SMR_DATAMEN_Pos) /**< (TWIHS_SMR) Data Matching Enable Mask */ +#define TWIHS_SMR_DATAMEN(value) (TWIHS_SMR_DATAMEN_Msk & ((value) << TWIHS_SMR_DATAMEN_Pos)) +#define TWIHS_SMR_Msk _U_(0xF07F7F4D) /**< (TWIHS_SMR) Register Mask */ + + +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) (R/W 32) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos _U_(0) /**< (TWIHS_IADR) Internal Address Position */ +#define TWIHS_IADR_IADR_Msk (_U_(0xFFFFFF) << TWIHS_IADR_IADR_Pos) /**< (TWIHS_IADR) Internal Address Mask */ +#define TWIHS_IADR_IADR(value) (TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)) +#define TWIHS_IADR_Msk _U_(0x00FFFFFF) /**< (TWIHS_IADR) Register Mask */ + + +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) (R/W 32) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos _U_(0) /**< (TWIHS_CWGR) Clock Low Divider Position */ +#define TWIHS_CWGR_CLDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CLDIV_Pos) /**< (TWIHS_CWGR) Clock Low Divider Mask */ +#define TWIHS_CWGR_CLDIV(value) (TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)) +#define TWIHS_CWGR_CHDIV_Pos _U_(8) /**< (TWIHS_CWGR) Clock High Divider Position */ +#define TWIHS_CWGR_CHDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CHDIV_Pos) /**< (TWIHS_CWGR) Clock High Divider Mask */ +#define TWIHS_CWGR_CHDIV(value) (TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)) +#define TWIHS_CWGR_CKDIV_Pos _U_(16) /**< (TWIHS_CWGR) Clock Divider Position */ +#define TWIHS_CWGR_CKDIV_Msk (_U_(0x7) << TWIHS_CWGR_CKDIV_Pos) /**< (TWIHS_CWGR) Clock Divider Mask */ +#define TWIHS_CWGR_CKDIV(value) (TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)) +#define TWIHS_CWGR_HOLD_Pos _U_(24) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Position */ +#define TWIHS_CWGR_HOLD_Msk (_U_(0x3F) << TWIHS_CWGR_HOLD_Pos) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Mask */ +#define TWIHS_CWGR_HOLD(value) (TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)) +#define TWIHS_CWGR_Msk _U_(0x3F07FFFF) /**< (TWIHS_CWGR) Register Mask */ + + +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) ( R/ 32) Status Register -------- */ +#define TWIHS_SR_TXCOMP_Pos _U_(0) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXCOMP_Msk (_U_(0x1) << TWIHS_SR_TXCOMP_Pos) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXCOMP(value) (TWIHS_SR_TXCOMP_Msk & ((value) << TWIHS_SR_TXCOMP_Pos)) +#define TWIHS_SR_RXRDY_Pos _U_(1) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Position */ +#define TWIHS_SR_RXRDY_Msk (_U_(0x1) << TWIHS_SR_RXRDY_Pos) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Mask */ +#define TWIHS_SR_RXRDY(value) (TWIHS_SR_RXRDY_Msk & ((value) << TWIHS_SR_RXRDY_Pos)) +#define TWIHS_SR_TXRDY_Pos _U_(2) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXRDY_Msk (_U_(0x1) << TWIHS_SR_TXRDY_Pos) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXRDY(value) (TWIHS_SR_TXRDY_Msk & ((value) << TWIHS_SR_TXRDY_Pos)) +#define TWIHS_SR_SVREAD_Pos _U_(3) /**< (TWIHS_SR) Slave Read Position */ +#define TWIHS_SR_SVREAD_Msk (_U_(0x1) << TWIHS_SR_SVREAD_Pos) /**< (TWIHS_SR) Slave Read Mask */ +#define TWIHS_SR_SVREAD(value) (TWIHS_SR_SVREAD_Msk & ((value) << TWIHS_SR_SVREAD_Pos)) +#define TWIHS_SR_SVACC_Pos _U_(4) /**< (TWIHS_SR) Slave Access Position */ +#define TWIHS_SR_SVACC_Msk (_U_(0x1) << TWIHS_SR_SVACC_Pos) /**< (TWIHS_SR) Slave Access Mask */ +#define TWIHS_SR_SVACC(value) (TWIHS_SR_SVACC_Msk & ((value) << TWIHS_SR_SVACC_Pos)) +#define TWIHS_SR_GACC_Pos _U_(5) /**< (TWIHS_SR) General Call Access (cleared on read) Position */ +#define TWIHS_SR_GACC_Msk (_U_(0x1) << TWIHS_SR_GACC_Pos) /**< (TWIHS_SR) General Call Access (cleared on read) Mask */ +#define TWIHS_SR_GACC(value) (TWIHS_SR_GACC_Msk & ((value) << TWIHS_SR_GACC_Pos)) +#define TWIHS_SR_OVRE_Pos _U_(6) /**< (TWIHS_SR) Overrun Error (cleared on read) Position */ +#define TWIHS_SR_OVRE_Msk (_U_(0x1) << TWIHS_SR_OVRE_Pos) /**< (TWIHS_SR) Overrun Error (cleared on read) Mask */ +#define TWIHS_SR_OVRE(value) (TWIHS_SR_OVRE_Msk & ((value) << TWIHS_SR_OVRE_Pos)) +#define TWIHS_SR_UNRE_Pos _U_(7) /**< (TWIHS_SR) Underrun Error (cleared on read) Position */ +#define TWIHS_SR_UNRE_Msk (_U_(0x1) << TWIHS_SR_UNRE_Pos) /**< (TWIHS_SR) Underrun Error (cleared on read) Mask */ +#define TWIHS_SR_UNRE(value) (TWIHS_SR_UNRE_Msk & ((value) << TWIHS_SR_UNRE_Pos)) +#define TWIHS_SR_NACK_Pos _U_(8) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Position */ +#define TWIHS_SR_NACK_Msk (_U_(0x1) << TWIHS_SR_NACK_Pos) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Mask */ +#define TWIHS_SR_NACK(value) (TWIHS_SR_NACK_Msk & ((value) << TWIHS_SR_NACK_Pos)) +#define TWIHS_SR_ARBLST_Pos _U_(9) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Position */ +#define TWIHS_SR_ARBLST_Msk (_U_(0x1) << TWIHS_SR_ARBLST_Pos) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Mask */ +#define TWIHS_SR_ARBLST(value) (TWIHS_SR_ARBLST_Msk & ((value) << TWIHS_SR_ARBLST_Pos)) +#define TWIHS_SR_SCLWS_Pos _U_(10) /**< (TWIHS_SR) Clock Wait State Position */ +#define TWIHS_SR_SCLWS_Msk (_U_(0x1) << TWIHS_SR_SCLWS_Pos) /**< (TWIHS_SR) Clock Wait State Mask */ +#define TWIHS_SR_SCLWS(value) (TWIHS_SR_SCLWS_Msk & ((value) << TWIHS_SR_SCLWS_Pos)) +#define TWIHS_SR_EOSACC_Pos _U_(11) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Position */ +#define TWIHS_SR_EOSACC_Msk (_U_(0x1) << TWIHS_SR_EOSACC_Pos) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Mask */ +#define TWIHS_SR_EOSACC(value) (TWIHS_SR_EOSACC_Msk & ((value) << TWIHS_SR_EOSACC_Pos)) +#define TWIHS_SR_MCACK_Pos _U_(16) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Position */ +#define TWIHS_SR_MCACK_Msk (_U_(0x1) << TWIHS_SR_MCACK_Pos) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Mask */ +#define TWIHS_SR_MCACK(value) (TWIHS_SR_MCACK_Msk & ((value) << TWIHS_SR_MCACK_Pos)) +#define TWIHS_SR_TOUT_Pos _U_(18) /**< (TWIHS_SR) Timeout Error (cleared on read) Position */ +#define TWIHS_SR_TOUT_Msk (_U_(0x1) << TWIHS_SR_TOUT_Pos) /**< (TWIHS_SR) Timeout Error (cleared on read) Mask */ +#define TWIHS_SR_TOUT(value) (TWIHS_SR_TOUT_Msk & ((value) << TWIHS_SR_TOUT_Pos)) +#define TWIHS_SR_PECERR_Pos _U_(19) /**< (TWIHS_SR) PEC Error (cleared on read) Position */ +#define TWIHS_SR_PECERR_Msk (_U_(0x1) << TWIHS_SR_PECERR_Pos) /**< (TWIHS_SR) PEC Error (cleared on read) Mask */ +#define TWIHS_SR_PECERR(value) (TWIHS_SR_PECERR_Msk & ((value) << TWIHS_SR_PECERR_Pos)) +#define TWIHS_SR_SMBDAM_Pos _U_(20) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBDAM_Msk (_U_(0x1) << TWIHS_SR_SMBDAM_Pos) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBDAM(value) (TWIHS_SR_SMBDAM_Msk & ((value) << TWIHS_SR_SMBDAM_Pos)) +#define TWIHS_SR_SMBHHM_Pos _U_(21) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBHHM_Msk (_U_(0x1) << TWIHS_SR_SMBHHM_Pos) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBHHM(value) (TWIHS_SR_SMBHHM_Msk & ((value) << TWIHS_SR_SMBHHM_Pos)) +#define TWIHS_SR_SCL_Pos _U_(24) /**< (TWIHS_SR) SCL Line Value Position */ +#define TWIHS_SR_SCL_Msk (_U_(0x1) << TWIHS_SR_SCL_Pos) /**< (TWIHS_SR) SCL Line Value Mask */ +#define TWIHS_SR_SCL(value) (TWIHS_SR_SCL_Msk & ((value) << TWIHS_SR_SCL_Pos)) +#define TWIHS_SR_SDA_Pos _U_(25) /**< (TWIHS_SR) SDA Line Value Position */ +#define TWIHS_SR_SDA_Msk (_U_(0x1) << TWIHS_SR_SDA_Pos) /**< (TWIHS_SR) SDA Line Value Mask */ +#define TWIHS_SR_SDA(value) (TWIHS_SR_SDA_Msk & ((value) << TWIHS_SR_SDA_Pos)) +#define TWIHS_SR_Msk _U_(0x033D0FFF) /**< (TWIHS_SR) Register Mask */ + + +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP_Pos _U_(0) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Position */ +#define TWIHS_IER_TXCOMP_Msk (_U_(0x1) << TWIHS_IER_TXCOMP_Pos) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Mask */ +#define TWIHS_IER_TXCOMP(value) (TWIHS_IER_TXCOMP_Msk & ((value) << TWIHS_IER_TXCOMP_Pos)) +#define TWIHS_IER_RXRDY_Pos _U_(1) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_RXRDY_Msk (_U_(0x1) << TWIHS_IER_RXRDY_Pos) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_RXRDY(value) (TWIHS_IER_RXRDY_Msk & ((value) << TWIHS_IER_RXRDY_Pos)) +#define TWIHS_IER_TXRDY_Pos _U_(2) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_TXRDY_Msk (_U_(0x1) << TWIHS_IER_TXRDY_Pos) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_TXRDY(value) (TWIHS_IER_TXRDY_Msk & ((value) << TWIHS_IER_TXRDY_Pos)) +#define TWIHS_IER_SVACC_Pos _U_(4) /**< (TWIHS_IER) Slave Access Interrupt Enable Position */ +#define TWIHS_IER_SVACC_Msk (_U_(0x1) << TWIHS_IER_SVACC_Pos) /**< (TWIHS_IER) Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_SVACC(value) (TWIHS_IER_SVACC_Msk & ((value) << TWIHS_IER_SVACC_Pos)) +#define TWIHS_IER_GACC_Pos _U_(5) /**< (TWIHS_IER) General Call Access Interrupt Enable Position */ +#define TWIHS_IER_GACC_Msk (_U_(0x1) << TWIHS_IER_GACC_Pos) /**< (TWIHS_IER) General Call Access Interrupt Enable Mask */ +#define TWIHS_IER_GACC(value) (TWIHS_IER_GACC_Msk & ((value) << TWIHS_IER_GACC_Pos)) +#define TWIHS_IER_OVRE_Pos _U_(6) /**< (TWIHS_IER) Overrun Error Interrupt Enable Position */ +#define TWIHS_IER_OVRE_Msk (_U_(0x1) << TWIHS_IER_OVRE_Pos) /**< (TWIHS_IER) Overrun Error Interrupt Enable Mask */ +#define TWIHS_IER_OVRE(value) (TWIHS_IER_OVRE_Msk & ((value) << TWIHS_IER_OVRE_Pos)) +#define TWIHS_IER_UNRE_Pos _U_(7) /**< (TWIHS_IER) Underrun Error Interrupt Enable Position */ +#define TWIHS_IER_UNRE_Msk (_U_(0x1) << TWIHS_IER_UNRE_Pos) /**< (TWIHS_IER) Underrun Error Interrupt Enable Mask */ +#define TWIHS_IER_UNRE(value) (TWIHS_IER_UNRE_Msk & ((value) << TWIHS_IER_UNRE_Pos)) +#define TWIHS_IER_NACK_Pos _U_(8) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_NACK_Msk (_U_(0x1) << TWIHS_IER_NACK_Pos) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_NACK(value) (TWIHS_IER_NACK_Msk & ((value) << TWIHS_IER_NACK_Pos)) +#define TWIHS_IER_ARBLST_Pos _U_(9) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Position */ +#define TWIHS_IER_ARBLST_Msk (_U_(0x1) << TWIHS_IER_ARBLST_Pos) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Mask */ +#define TWIHS_IER_ARBLST(value) (TWIHS_IER_ARBLST_Msk & ((value) << TWIHS_IER_ARBLST_Pos)) +#define TWIHS_IER_SCL_WS_Pos _U_(10) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Position */ +#define TWIHS_IER_SCL_WS_Msk (_U_(0x1) << TWIHS_IER_SCL_WS_Pos) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Mask */ +#define TWIHS_IER_SCL_WS(value) (TWIHS_IER_SCL_WS_Msk & ((value) << TWIHS_IER_SCL_WS_Pos)) +#define TWIHS_IER_EOSACC_Pos _U_(11) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Position */ +#define TWIHS_IER_EOSACC_Msk (_U_(0x1) << TWIHS_IER_EOSACC_Pos) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_EOSACC(value) (TWIHS_IER_EOSACC_Msk & ((value) << TWIHS_IER_EOSACC_Pos)) +#define TWIHS_IER_MCACK_Pos _U_(16) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_MCACK_Msk (_U_(0x1) << TWIHS_IER_MCACK_Pos) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_MCACK(value) (TWIHS_IER_MCACK_Msk & ((value) << TWIHS_IER_MCACK_Pos)) +#define TWIHS_IER_TOUT_Pos _U_(18) /**< (TWIHS_IER) Timeout Error Interrupt Enable Position */ +#define TWIHS_IER_TOUT_Msk (_U_(0x1) << TWIHS_IER_TOUT_Pos) /**< (TWIHS_IER) Timeout Error Interrupt Enable Mask */ +#define TWIHS_IER_TOUT(value) (TWIHS_IER_TOUT_Msk & ((value) << TWIHS_IER_TOUT_Pos)) +#define TWIHS_IER_PECERR_Pos _U_(19) /**< (TWIHS_IER) PEC Error Interrupt Enable Position */ +#define TWIHS_IER_PECERR_Msk (_U_(0x1) << TWIHS_IER_PECERR_Pos) /**< (TWIHS_IER) PEC Error Interrupt Enable Mask */ +#define TWIHS_IER_PECERR(value) (TWIHS_IER_PECERR_Msk & ((value) << TWIHS_IER_PECERR_Pos)) +#define TWIHS_IER_SMBDAM_Pos _U_(20) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBDAM_Msk (_U_(0x1) << TWIHS_IER_SMBDAM_Pos) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBDAM(value) (TWIHS_IER_SMBDAM_Msk & ((value) << TWIHS_IER_SMBDAM_Pos)) +#define TWIHS_IER_SMBHHM_Pos _U_(21) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBHHM_Msk (_U_(0x1) << TWIHS_IER_SMBHHM_Pos) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBHHM(value) (TWIHS_IER_SMBHHM_Msk & ((value) << TWIHS_IER_SMBHHM_Pos)) +#define TWIHS_IER_Msk _U_(0x003D0FF7) /**< (TWIHS_IER) Register Mask */ + + +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP_Pos _U_(0) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Position */ +#define TWIHS_IDR_TXCOMP_Msk (_U_(0x1) << TWIHS_IDR_TXCOMP_Pos) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Mask */ +#define TWIHS_IDR_TXCOMP(value) (TWIHS_IDR_TXCOMP_Msk & ((value) << TWIHS_IDR_TXCOMP_Pos)) +#define TWIHS_IDR_RXRDY_Pos _U_(1) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_RXRDY_Msk (_U_(0x1) << TWIHS_IDR_RXRDY_Pos) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_RXRDY(value) (TWIHS_IDR_RXRDY_Msk & ((value) << TWIHS_IDR_RXRDY_Pos)) +#define TWIHS_IDR_TXRDY_Pos _U_(2) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_TXRDY_Msk (_U_(0x1) << TWIHS_IDR_TXRDY_Pos) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_TXRDY(value) (TWIHS_IDR_TXRDY_Msk & ((value) << TWIHS_IDR_TXRDY_Pos)) +#define TWIHS_IDR_SVACC_Pos _U_(4) /**< (TWIHS_IDR) Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_SVACC_Msk (_U_(0x1) << TWIHS_IDR_SVACC_Pos) /**< (TWIHS_IDR) Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_SVACC(value) (TWIHS_IDR_SVACC_Msk & ((value) << TWIHS_IDR_SVACC_Pos)) +#define TWIHS_IDR_GACC_Pos _U_(5) /**< (TWIHS_IDR) General Call Access Interrupt Disable Position */ +#define TWIHS_IDR_GACC_Msk (_U_(0x1) << TWIHS_IDR_GACC_Pos) /**< (TWIHS_IDR) General Call Access Interrupt Disable Mask */ +#define TWIHS_IDR_GACC(value) (TWIHS_IDR_GACC_Msk & ((value) << TWIHS_IDR_GACC_Pos)) +#define TWIHS_IDR_OVRE_Pos _U_(6) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Position */ +#define TWIHS_IDR_OVRE_Msk (_U_(0x1) << TWIHS_IDR_OVRE_Pos) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_OVRE(value) (TWIHS_IDR_OVRE_Msk & ((value) << TWIHS_IDR_OVRE_Pos)) +#define TWIHS_IDR_UNRE_Pos _U_(7) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Position */ +#define TWIHS_IDR_UNRE_Msk (_U_(0x1) << TWIHS_IDR_UNRE_Pos) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_UNRE(value) (TWIHS_IDR_UNRE_Msk & ((value) << TWIHS_IDR_UNRE_Pos)) +#define TWIHS_IDR_NACK_Pos _U_(8) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_NACK_Msk (_U_(0x1) << TWIHS_IDR_NACK_Pos) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_NACK(value) (TWIHS_IDR_NACK_Msk & ((value) << TWIHS_IDR_NACK_Pos)) +#define TWIHS_IDR_ARBLST_Pos _U_(9) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Position */ +#define TWIHS_IDR_ARBLST_Msk (_U_(0x1) << TWIHS_IDR_ARBLST_Pos) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Mask */ +#define TWIHS_IDR_ARBLST(value) (TWIHS_IDR_ARBLST_Msk & ((value) << TWIHS_IDR_ARBLST_Pos)) +#define TWIHS_IDR_SCL_WS_Pos _U_(10) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Position */ +#define TWIHS_IDR_SCL_WS_Msk (_U_(0x1) << TWIHS_IDR_SCL_WS_Pos) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Mask */ +#define TWIHS_IDR_SCL_WS(value) (TWIHS_IDR_SCL_WS_Msk & ((value) << TWIHS_IDR_SCL_WS_Pos)) +#define TWIHS_IDR_EOSACC_Pos _U_(11) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_EOSACC_Msk (_U_(0x1) << TWIHS_IDR_EOSACC_Pos) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_EOSACC(value) (TWIHS_IDR_EOSACC_Msk & ((value) << TWIHS_IDR_EOSACC_Pos)) +#define TWIHS_IDR_MCACK_Pos _U_(16) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_MCACK_Msk (_U_(0x1) << TWIHS_IDR_MCACK_Pos) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_MCACK(value) (TWIHS_IDR_MCACK_Msk & ((value) << TWIHS_IDR_MCACK_Pos)) +#define TWIHS_IDR_TOUT_Pos _U_(18) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Position */ +#define TWIHS_IDR_TOUT_Msk (_U_(0x1) << TWIHS_IDR_TOUT_Pos) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Mask */ +#define TWIHS_IDR_TOUT(value) (TWIHS_IDR_TOUT_Msk & ((value) << TWIHS_IDR_TOUT_Pos)) +#define TWIHS_IDR_PECERR_Pos _U_(19) /**< (TWIHS_IDR) PEC Error Interrupt Disable Position */ +#define TWIHS_IDR_PECERR_Msk (_U_(0x1) << TWIHS_IDR_PECERR_Pos) /**< (TWIHS_IDR) PEC Error Interrupt Disable Mask */ +#define TWIHS_IDR_PECERR(value) (TWIHS_IDR_PECERR_Msk & ((value) << TWIHS_IDR_PECERR_Pos)) +#define TWIHS_IDR_SMBDAM_Pos _U_(20) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBDAM_Msk (_U_(0x1) << TWIHS_IDR_SMBDAM_Pos) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBDAM(value) (TWIHS_IDR_SMBDAM_Msk & ((value) << TWIHS_IDR_SMBDAM_Pos)) +#define TWIHS_IDR_SMBHHM_Pos _U_(21) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBHHM_Msk (_U_(0x1) << TWIHS_IDR_SMBHHM_Pos) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBHHM(value) (TWIHS_IDR_SMBHHM_Msk & ((value) << TWIHS_IDR_SMBHHM_Pos)) +#define TWIHS_IDR_Msk _U_(0x003D0FF7) /**< (TWIHS_IDR) Register Mask */ + + +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP_Pos _U_(0) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Position */ +#define TWIHS_IMR_TXCOMP_Msk (_U_(0x1) << TWIHS_IMR_TXCOMP_Pos) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Mask */ +#define TWIHS_IMR_TXCOMP(value) (TWIHS_IMR_TXCOMP_Msk & ((value) << TWIHS_IMR_TXCOMP_Pos)) +#define TWIHS_IMR_RXRDY_Pos _U_(1) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_RXRDY_Msk (_U_(0x1) << TWIHS_IMR_RXRDY_Pos) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_RXRDY(value) (TWIHS_IMR_RXRDY_Msk & ((value) << TWIHS_IMR_RXRDY_Pos)) +#define TWIHS_IMR_TXRDY_Pos _U_(2) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_TXRDY_Msk (_U_(0x1) << TWIHS_IMR_TXRDY_Pos) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_TXRDY(value) (TWIHS_IMR_TXRDY_Msk & ((value) << TWIHS_IMR_TXRDY_Pos)) +#define TWIHS_IMR_SVACC_Pos _U_(4) /**< (TWIHS_IMR) Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_SVACC_Msk (_U_(0x1) << TWIHS_IMR_SVACC_Pos) /**< (TWIHS_IMR) Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_SVACC(value) (TWIHS_IMR_SVACC_Msk & ((value) << TWIHS_IMR_SVACC_Pos)) +#define TWIHS_IMR_GACC_Pos _U_(5) /**< (TWIHS_IMR) General Call Access Interrupt Mask Position */ +#define TWIHS_IMR_GACC_Msk (_U_(0x1) << TWIHS_IMR_GACC_Pos) /**< (TWIHS_IMR) General Call Access Interrupt Mask Mask */ +#define TWIHS_IMR_GACC(value) (TWIHS_IMR_GACC_Msk & ((value) << TWIHS_IMR_GACC_Pos)) +#define TWIHS_IMR_OVRE_Pos _U_(6) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Position */ +#define TWIHS_IMR_OVRE_Msk (_U_(0x1) << TWIHS_IMR_OVRE_Pos) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_OVRE(value) (TWIHS_IMR_OVRE_Msk & ((value) << TWIHS_IMR_OVRE_Pos)) +#define TWIHS_IMR_UNRE_Pos _U_(7) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Position */ +#define TWIHS_IMR_UNRE_Msk (_U_(0x1) << TWIHS_IMR_UNRE_Pos) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_UNRE(value) (TWIHS_IMR_UNRE_Msk & ((value) << TWIHS_IMR_UNRE_Pos)) +#define TWIHS_IMR_NACK_Pos _U_(8) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_NACK_Msk (_U_(0x1) << TWIHS_IMR_NACK_Pos) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_NACK(value) (TWIHS_IMR_NACK_Msk & ((value) << TWIHS_IMR_NACK_Pos)) +#define TWIHS_IMR_ARBLST_Pos _U_(9) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Position */ +#define TWIHS_IMR_ARBLST_Msk (_U_(0x1) << TWIHS_IMR_ARBLST_Pos) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Mask */ +#define TWIHS_IMR_ARBLST(value) (TWIHS_IMR_ARBLST_Msk & ((value) << TWIHS_IMR_ARBLST_Pos)) +#define TWIHS_IMR_SCL_WS_Pos _U_(10) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Position */ +#define TWIHS_IMR_SCL_WS_Msk (_U_(0x1) << TWIHS_IMR_SCL_WS_Pos) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Mask */ +#define TWIHS_IMR_SCL_WS(value) (TWIHS_IMR_SCL_WS_Msk & ((value) << TWIHS_IMR_SCL_WS_Pos)) +#define TWIHS_IMR_EOSACC_Pos _U_(11) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_EOSACC_Msk (_U_(0x1) << TWIHS_IMR_EOSACC_Pos) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_EOSACC(value) (TWIHS_IMR_EOSACC_Msk & ((value) << TWIHS_IMR_EOSACC_Pos)) +#define TWIHS_IMR_MCACK_Pos _U_(16) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_MCACK_Msk (_U_(0x1) << TWIHS_IMR_MCACK_Pos) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_MCACK(value) (TWIHS_IMR_MCACK_Msk & ((value) << TWIHS_IMR_MCACK_Pos)) +#define TWIHS_IMR_TOUT_Pos _U_(18) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Position */ +#define TWIHS_IMR_TOUT_Msk (_U_(0x1) << TWIHS_IMR_TOUT_Pos) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Mask */ +#define TWIHS_IMR_TOUT(value) (TWIHS_IMR_TOUT_Msk & ((value) << TWIHS_IMR_TOUT_Pos)) +#define TWIHS_IMR_PECERR_Pos _U_(19) /**< (TWIHS_IMR) PEC Error Interrupt Mask Position */ +#define TWIHS_IMR_PECERR_Msk (_U_(0x1) << TWIHS_IMR_PECERR_Pos) /**< (TWIHS_IMR) PEC Error Interrupt Mask Mask */ +#define TWIHS_IMR_PECERR(value) (TWIHS_IMR_PECERR_Msk & ((value) << TWIHS_IMR_PECERR_Pos)) +#define TWIHS_IMR_SMBDAM_Pos _U_(20) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBDAM_Msk (_U_(0x1) << TWIHS_IMR_SMBDAM_Pos) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBDAM(value) (TWIHS_IMR_SMBDAM_Msk & ((value) << TWIHS_IMR_SMBDAM_Pos)) +#define TWIHS_IMR_SMBHHM_Pos _U_(21) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBHHM_Msk (_U_(0x1) << TWIHS_IMR_SMBHHM_Pos) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBHHM(value) (TWIHS_IMR_SMBHHM_Msk & ((value) << TWIHS_IMR_SMBHHM_Pos)) +#define TWIHS_IMR_Msk _U_(0x003D0FF7) /**< (TWIHS_IMR) Register Mask */ + + +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) ( R/ 32) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos _U_(0) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Position */ +#define TWIHS_RHR_RXDATA_Msk (_U_(0xFF) << TWIHS_RHR_RXDATA_Pos) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Mask */ +#define TWIHS_RHR_RXDATA(value) (TWIHS_RHR_RXDATA_Msk & ((value) << TWIHS_RHR_RXDATA_Pos)) +#define TWIHS_RHR_Msk _U_(0x000000FF) /**< (TWIHS_RHR) Register Mask */ + + +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) ( /W 32) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos _U_(0) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Position */ +#define TWIHS_THR_TXDATA_Msk (_U_(0xFF) << TWIHS_THR_TXDATA_Pos) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Mask */ +#define TWIHS_THR_TXDATA(value) (TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)) +#define TWIHS_THR_Msk _U_(0x000000FF) /**< (TWIHS_THR) Register Mask */ + + +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) (R/W 32) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos _U_(0) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Position */ +#define TWIHS_SMBTR_PRESC_Msk (_U_(0xF) << TWIHS_SMBTR_PRESC_Pos) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Mask */ +#define TWIHS_SMBTR_PRESC(value) (TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)) +#define TWIHS_SMBTR_TLOWS_Pos _U_(8) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWS_Pos) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWS(value) (TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)) +#define TWIHS_SMBTR_TLOWM_Pos _U_(16) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWM_Pos) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWM(value) (TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)) +#define TWIHS_SMBTR_THMAX_Pos _U_(24) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Position */ +#define TWIHS_SMBTR_THMAX_Msk (_U_(0xFF) << TWIHS_SMBTR_THMAX_Pos) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Mask */ +#define TWIHS_SMBTR_THMAX(value) (TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)) +#define TWIHS_SMBTR_Msk _U_(0xFFFFFF0F) /**< (TWIHS_SMBTR) Register Mask */ + + +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) (R/W 32) Filter Register -------- */ +#define TWIHS_FILTR_FILT_Pos _U_(0) /**< (TWIHS_FILTR) RX Digital Filter Position */ +#define TWIHS_FILTR_FILT_Msk (_U_(0x1) << TWIHS_FILTR_FILT_Pos) /**< (TWIHS_FILTR) RX Digital Filter Mask */ +#define TWIHS_FILTR_FILT(value) (TWIHS_FILTR_FILT_Msk & ((value) << TWIHS_FILTR_FILT_Pos)) +#define TWIHS_FILTR_PADFEN_Pos _U_(1) /**< (TWIHS_FILTR) PAD Filter Enable Position */ +#define TWIHS_FILTR_PADFEN_Msk (_U_(0x1) << TWIHS_FILTR_PADFEN_Pos) /**< (TWIHS_FILTR) PAD Filter Enable Mask */ +#define TWIHS_FILTR_PADFEN(value) (TWIHS_FILTR_PADFEN_Msk & ((value) << TWIHS_FILTR_PADFEN_Pos)) +#define TWIHS_FILTR_PADFCFG_Pos _U_(2) /**< (TWIHS_FILTR) PAD Filter Config Position */ +#define TWIHS_FILTR_PADFCFG_Msk (_U_(0x1) << TWIHS_FILTR_PADFCFG_Pos) /**< (TWIHS_FILTR) PAD Filter Config Mask */ +#define TWIHS_FILTR_PADFCFG(value) (TWIHS_FILTR_PADFCFG_Msk & ((value) << TWIHS_FILTR_PADFCFG_Pos)) +#define TWIHS_FILTR_THRES_Pos _U_(8) /**< (TWIHS_FILTR) Digital Filter Threshold Position */ +#define TWIHS_FILTR_THRES_Msk (_U_(0x7) << TWIHS_FILTR_THRES_Pos) /**< (TWIHS_FILTR) Digital Filter Threshold Mask */ +#define TWIHS_FILTR_THRES(value) (TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)) +#define TWIHS_FILTR_Msk _U_(0x00000707) /**< (TWIHS_FILTR) Register Mask */ + + +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) (R/W 32) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos _U_(0) /**< (TWIHS_SWMR) Slave Address 1 Position */ +#define TWIHS_SWMR_SADR1_Msk (_U_(0x7F) << TWIHS_SWMR_SADR1_Pos) /**< (TWIHS_SWMR) Slave Address 1 Mask */ +#define TWIHS_SWMR_SADR1(value) (TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)) +#define TWIHS_SWMR_SADR2_Pos _U_(8) /**< (TWIHS_SWMR) Slave Address 2 Position */ +#define TWIHS_SWMR_SADR2_Msk (_U_(0x7F) << TWIHS_SWMR_SADR2_Pos) /**< (TWIHS_SWMR) Slave Address 2 Mask */ +#define TWIHS_SWMR_SADR2(value) (TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)) +#define TWIHS_SWMR_SADR3_Pos _U_(16) /**< (TWIHS_SWMR) Slave Address 3 Position */ +#define TWIHS_SWMR_SADR3_Msk (_U_(0x7F) << TWIHS_SWMR_SADR3_Pos) /**< (TWIHS_SWMR) Slave Address 3 Mask */ +#define TWIHS_SWMR_SADR3(value) (TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)) +#define TWIHS_SWMR_DATAM_Pos _U_(24) /**< (TWIHS_SWMR) Data Match Position */ +#define TWIHS_SWMR_DATAM_Msk (_U_(0xFF) << TWIHS_SWMR_DATAM_Pos) /**< (TWIHS_SWMR) Data Match Mask */ +#define TWIHS_SWMR_DATAM(value) (TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)) +#define TWIHS_SWMR_Msk _U_(0xFF7F7F7F) /**< (TWIHS_SWMR) Register Mask */ + + +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN_Pos _U_(0) /**< (TWIHS_WPMR) Write Protection Enable Position */ +#define TWIHS_WPMR_WPEN_Msk (_U_(0x1) << TWIHS_WPMR_WPEN_Pos) /**< (TWIHS_WPMR) Write Protection Enable Mask */ +#define TWIHS_WPMR_WPEN(value) (TWIHS_WPMR_WPEN_Msk & ((value) << TWIHS_WPMR_WPEN_Pos)) +#define TWIHS_WPMR_WPKEY_Pos _U_(8) /**< (TWIHS_WPMR) Write Protection Key Position */ +#define TWIHS_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Write Protection Key Mask */ +#define TWIHS_WPMR_WPKEY(value) (TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)) +#define TWIHS_WPMR_WPKEY_PASSWD_Val _U_(0x545749) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +#define TWIHS_WPMR_WPKEY_PASSWD (TWIHS_WPMR_WPKEY_PASSWD_Val << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 Position */ +#define TWIHS_WPMR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPMR) Register Mask */ + + +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS_Pos _U_(0) /**< (TWIHS_WPSR) Write Protection Violation Status Position */ +#define TWIHS_WPSR_WPVS_Msk (_U_(0x1) << TWIHS_WPSR_WPVS_Pos) /**< (TWIHS_WPSR) Write Protection Violation Status Mask */ +#define TWIHS_WPSR_WPVS(value) (TWIHS_WPSR_WPVS_Msk & ((value) << TWIHS_WPSR_WPVS_Pos)) +#define TWIHS_WPSR_WPVSRC_Pos _U_(8) /**< (TWIHS_WPSR) Write Protection Violation Source Position */ +#define TWIHS_WPSR_WPVSRC_Msk (_U_(0xFFFFFF) << TWIHS_WPSR_WPVSRC_Pos) /**< (TWIHS_WPSR) Write Protection Violation Source Mask */ +#define TWIHS_WPSR_WPVSRC(value) (TWIHS_WPSR_WPVSRC_Msk & ((value) << TWIHS_WPSR_WPVSRC_Pos)) +#define TWIHS_WPSR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPSR) Register Mask */ + + +/** \brief TWIHS register offsets definitions */ +#define TWIHS_CR_REG_OFST (0x00) /**< (TWIHS_CR) Control Register Offset */ +#define TWIHS_MMR_REG_OFST (0x04) /**< (TWIHS_MMR) Master Mode Register Offset */ +#define TWIHS_SMR_REG_OFST (0x08) /**< (TWIHS_SMR) Slave Mode Register Offset */ +#define TWIHS_IADR_REG_OFST (0x0C) /**< (TWIHS_IADR) Internal Address Register Offset */ +#define TWIHS_CWGR_REG_OFST (0x10) /**< (TWIHS_CWGR) Clock Waveform Generator Register Offset */ +#define TWIHS_SR_REG_OFST (0x20) /**< (TWIHS_SR) Status Register Offset */ +#define TWIHS_IER_REG_OFST (0x24) /**< (TWIHS_IER) Interrupt Enable Register Offset */ +#define TWIHS_IDR_REG_OFST (0x28) /**< (TWIHS_IDR) Interrupt Disable Register Offset */ +#define TWIHS_IMR_REG_OFST (0x2C) /**< (TWIHS_IMR) Interrupt Mask Register Offset */ +#define TWIHS_RHR_REG_OFST (0x30) /**< (TWIHS_RHR) Receive Holding Register Offset */ +#define TWIHS_THR_REG_OFST (0x34) /**< (TWIHS_THR) Transmit Holding Register Offset */ +#define TWIHS_SMBTR_REG_OFST (0x38) /**< (TWIHS_SMBTR) SMBus Timing Register Offset */ +#define TWIHS_FILTR_REG_OFST (0x44) /**< (TWIHS_FILTR) Filter Register Offset */ +#define TWIHS_SWMR_REG_OFST (0x4C) /**< (TWIHS_SWMR) SleepWalking Matching Register Offset */ +#define TWIHS_WPMR_REG_OFST (0xE4) /**< (TWIHS_WPMR) Write Protection Mode Register Offset */ +#define TWIHS_WPSR_REG_OFST (0xE8) /**< (TWIHS_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TWIHS register API structure */ +typedef struct +{ + __O uint32_t TWIHS_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t TWIHS_MMR; /**< Offset: 0x04 (R/W 32) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< Offset: 0x08 (R/W 32) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< Offset: 0x0C (R/W 32) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< Offset: 0x10 (R/W 32) Clock Waveform Generator Register */ + __I uint8_t Reserved1[0x0C]; + __I uint32_t TWIHS_SR; /**< Offset: 0x20 (R/ 32) Status Register */ + __O uint32_t TWIHS_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< Offset: 0x30 (R/ 32) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< Offset: 0x34 ( /W 32) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< Offset: 0x38 (R/W 32) SMBus Timing Register */ + __I uint8_t Reserved2[0x08]; + __IO uint32_t TWIHS_FILTR; /**< Offset: 0x44 (R/W 32) Filter Register */ + __I uint8_t Reserved3[0x04]; + __IO uint32_t TWIHS_SWMR; /**< Offset: 0x4C (R/W 32) SleepWalking Matching Register */ + __I uint8_t Reserved4[0x94]; + __IO uint32_t TWIHS_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} twihs_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TWIHS_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/uart.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/uart.h new file mode 100644 index 00000000..2b8bcd75 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/uart.h @@ -0,0 +1,287 @@ +/** + * \brief Component description for UART + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_UART_COMPONENT_H_ +#define _SAME70_UART_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR UART */ +/* ************************************************************************** */ + +/* -------- UART_CR : (UART Offset: 0x00) ( /W 32) Control Register -------- */ +#define UART_CR_RSTRX_Pos _U_(2) /**< (UART_CR) Reset Receiver Position */ +#define UART_CR_RSTRX_Msk (_U_(0x1) << UART_CR_RSTRX_Pos) /**< (UART_CR) Reset Receiver Mask */ +#define UART_CR_RSTRX(value) (UART_CR_RSTRX_Msk & ((value) << UART_CR_RSTRX_Pos)) +#define UART_CR_RSTTX_Pos _U_(3) /**< (UART_CR) Reset Transmitter Position */ +#define UART_CR_RSTTX_Msk (_U_(0x1) << UART_CR_RSTTX_Pos) /**< (UART_CR) Reset Transmitter Mask */ +#define UART_CR_RSTTX(value) (UART_CR_RSTTX_Msk & ((value) << UART_CR_RSTTX_Pos)) +#define UART_CR_RXEN_Pos _U_(4) /**< (UART_CR) Receiver Enable Position */ +#define UART_CR_RXEN_Msk (_U_(0x1) << UART_CR_RXEN_Pos) /**< (UART_CR) Receiver Enable Mask */ +#define UART_CR_RXEN(value) (UART_CR_RXEN_Msk & ((value) << UART_CR_RXEN_Pos)) +#define UART_CR_RXDIS_Pos _U_(5) /**< (UART_CR) Receiver Disable Position */ +#define UART_CR_RXDIS_Msk (_U_(0x1) << UART_CR_RXDIS_Pos) /**< (UART_CR) Receiver Disable Mask */ +#define UART_CR_RXDIS(value) (UART_CR_RXDIS_Msk & ((value) << UART_CR_RXDIS_Pos)) +#define UART_CR_TXEN_Pos _U_(6) /**< (UART_CR) Transmitter Enable Position */ +#define UART_CR_TXEN_Msk (_U_(0x1) << UART_CR_TXEN_Pos) /**< (UART_CR) Transmitter Enable Mask */ +#define UART_CR_TXEN(value) (UART_CR_TXEN_Msk & ((value) << UART_CR_TXEN_Pos)) +#define UART_CR_TXDIS_Pos _U_(7) /**< (UART_CR) Transmitter Disable Position */ +#define UART_CR_TXDIS_Msk (_U_(0x1) << UART_CR_TXDIS_Pos) /**< (UART_CR) Transmitter Disable Mask */ +#define UART_CR_TXDIS(value) (UART_CR_TXDIS_Msk & ((value) << UART_CR_TXDIS_Pos)) +#define UART_CR_RSTSTA_Pos _U_(8) /**< (UART_CR) Reset Status Position */ +#define UART_CR_RSTSTA_Msk (_U_(0x1) << UART_CR_RSTSTA_Pos) /**< (UART_CR) Reset Status Mask */ +#define UART_CR_RSTSTA(value) (UART_CR_RSTSTA_Msk & ((value) << UART_CR_RSTSTA_Pos)) +#define UART_CR_REQCLR_Pos _U_(12) /**< (UART_CR) Request Clear Position */ +#define UART_CR_REQCLR_Msk (_U_(0x1) << UART_CR_REQCLR_Pos) /**< (UART_CR) Request Clear Mask */ +#define UART_CR_REQCLR(value) (UART_CR_REQCLR_Msk & ((value) << UART_CR_REQCLR_Pos)) +#define UART_CR_Msk _U_(0x000011FC) /**< (UART_CR) Register Mask */ + + +/* -------- UART_MR : (UART Offset: 0x04) (R/W 32) Mode Register -------- */ +#define UART_MR_FILTER_Pos _U_(4) /**< (UART_MR) Receiver Digital Filter Position */ +#define UART_MR_FILTER_Msk (_U_(0x1) << UART_MR_FILTER_Pos) /**< (UART_MR) Receiver Digital Filter Mask */ +#define UART_MR_FILTER(value) (UART_MR_FILTER_Msk & ((value) << UART_MR_FILTER_Pos)) +#define UART_MR_FILTER_DISABLED_Val _U_(0x0) /**< (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED_Val _U_(0x1) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_FILTER_DISABLED (UART_MR_FILTER_DISABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART does not filter the receive line. Position */ +#define UART_MR_FILTER_ENABLED (UART_MR_FILTER_ENABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). Position */ +#define UART_MR_PAR_Pos _U_(9) /**< (UART_MR) Parity Type Position */ +#define UART_MR_PAR_Msk (_U_(0x7) << UART_MR_PAR_Pos) /**< (UART_MR) Parity Type Mask */ +#define UART_MR_PAR(value) (UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)) +#define UART_MR_PAR_EVEN_Val _U_(0x0) /**< (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD_Val _U_(0x1) /**< (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE_Val _U_(0x2) /**< (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK_Val _U_(0x3) /**< (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO_Val _U_(0x4) /**< (UART_MR) No parity */ +#define UART_MR_PAR_EVEN (UART_MR_PAR_EVEN_Val << UART_MR_PAR_Pos) /**< (UART_MR) Even Parity Position */ +#define UART_MR_PAR_ODD (UART_MR_PAR_ODD_Val << UART_MR_PAR_Pos) /**< (UART_MR) Odd Parity Position */ +#define UART_MR_PAR_SPACE (UART_MR_PAR_SPACE_Val << UART_MR_PAR_Pos) /**< (UART_MR) Space: parity forced to 0 Position */ +#define UART_MR_PAR_MARK (UART_MR_PAR_MARK_Val << UART_MR_PAR_Pos) /**< (UART_MR) Mark: parity forced to 1 Position */ +#define UART_MR_PAR_NO (UART_MR_PAR_NO_Val << UART_MR_PAR_Pos) /**< (UART_MR) No parity Position */ +#define UART_MR_BRSRCCK_Pos _U_(12) /**< (UART_MR) Baud Rate Source Clock Position */ +#define UART_MR_BRSRCCK_Msk (_U_(0x1) << UART_MR_BRSRCCK_Pos) /**< (UART_MR) Baud Rate Source Clock Mask */ +#define UART_MR_BRSRCCK(value) (UART_MR_BRSRCCK_Msk & ((value) << UART_MR_BRSRCCK_Pos)) +#define UART_MR_BRSRCCK_PERIPH_CLK_Val _U_(0x0) /**< (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK_Val _U_(0x1) /**< (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_BRSRCCK_PERIPH_CLK (UART_MR_BRSRCCK_PERIPH_CLK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by the peripheral clock Position */ +#define UART_MR_BRSRCCK_PMC_PCK (UART_MR_BRSRCCK_PMC_PCK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). Position */ +#define UART_MR_CHMODE_Pos _U_(14) /**< (UART_MR) Channel Mode Position */ +#define UART_MR_CHMODE_Msk (_U_(0x3) << UART_MR_CHMODE_Pos) /**< (UART_MR) Channel Mode Mask */ +#define UART_MR_CHMODE(value) (UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)) +#define UART_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (UART_MR) Remote loopback */ +#define UART_MR_CHMODE_NORMAL (UART_MR_CHMODE_NORMAL_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Normal mode Position */ +#define UART_MR_CHMODE_AUTOMATIC (UART_MR_CHMODE_AUTOMATIC_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Automatic echo Position */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (UART_MR_CHMODE_LOCAL_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Local loopback Position */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (UART_MR_CHMODE_REMOTE_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Remote loopback Position */ +#define UART_MR_Msk _U_(0x0000DE10) /**< (UART_MR) Register Mask */ + + +/* -------- UART_IER : (UART Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY_Pos _U_(0) /**< (UART_IER) Enable RXRDY Interrupt Position */ +#define UART_IER_RXRDY_Msk (_U_(0x1) << UART_IER_RXRDY_Pos) /**< (UART_IER) Enable RXRDY Interrupt Mask */ +#define UART_IER_RXRDY(value) (UART_IER_RXRDY_Msk & ((value) << UART_IER_RXRDY_Pos)) +#define UART_IER_TXRDY_Pos _U_(1) /**< (UART_IER) Enable TXRDY Interrupt Position */ +#define UART_IER_TXRDY_Msk (_U_(0x1) << UART_IER_TXRDY_Pos) /**< (UART_IER) Enable TXRDY Interrupt Mask */ +#define UART_IER_TXRDY(value) (UART_IER_TXRDY_Msk & ((value) << UART_IER_TXRDY_Pos)) +#define UART_IER_OVRE_Pos _U_(5) /**< (UART_IER) Enable Overrun Error Interrupt Position */ +#define UART_IER_OVRE_Msk (_U_(0x1) << UART_IER_OVRE_Pos) /**< (UART_IER) Enable Overrun Error Interrupt Mask */ +#define UART_IER_OVRE(value) (UART_IER_OVRE_Msk & ((value) << UART_IER_OVRE_Pos)) +#define UART_IER_FRAME_Pos _U_(6) /**< (UART_IER) Enable Framing Error Interrupt Position */ +#define UART_IER_FRAME_Msk (_U_(0x1) << UART_IER_FRAME_Pos) /**< (UART_IER) Enable Framing Error Interrupt Mask */ +#define UART_IER_FRAME(value) (UART_IER_FRAME_Msk & ((value) << UART_IER_FRAME_Pos)) +#define UART_IER_PARE_Pos _U_(7) /**< (UART_IER) Enable Parity Error Interrupt Position */ +#define UART_IER_PARE_Msk (_U_(0x1) << UART_IER_PARE_Pos) /**< (UART_IER) Enable Parity Error Interrupt Mask */ +#define UART_IER_PARE(value) (UART_IER_PARE_Msk & ((value) << UART_IER_PARE_Pos)) +#define UART_IER_TXEMPTY_Pos _U_(9) /**< (UART_IER) Enable TXEMPTY Interrupt Position */ +#define UART_IER_TXEMPTY_Msk (_U_(0x1) << UART_IER_TXEMPTY_Pos) /**< (UART_IER) Enable TXEMPTY Interrupt Mask */ +#define UART_IER_TXEMPTY(value) (UART_IER_TXEMPTY_Msk & ((value) << UART_IER_TXEMPTY_Pos)) +#define UART_IER_CMP_Pos _U_(15) /**< (UART_IER) Enable Comparison Interrupt Position */ +#define UART_IER_CMP_Msk (_U_(0x1) << UART_IER_CMP_Pos) /**< (UART_IER) Enable Comparison Interrupt Mask */ +#define UART_IER_CMP(value) (UART_IER_CMP_Msk & ((value) << UART_IER_CMP_Pos)) +#define UART_IER_Msk _U_(0x000082E3) /**< (UART_IER) Register Mask */ + + +/* -------- UART_IDR : (UART Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY_Pos _U_(0) /**< (UART_IDR) Disable RXRDY Interrupt Position */ +#define UART_IDR_RXRDY_Msk (_U_(0x1) << UART_IDR_RXRDY_Pos) /**< (UART_IDR) Disable RXRDY Interrupt Mask */ +#define UART_IDR_RXRDY(value) (UART_IDR_RXRDY_Msk & ((value) << UART_IDR_RXRDY_Pos)) +#define UART_IDR_TXRDY_Pos _U_(1) /**< (UART_IDR) Disable TXRDY Interrupt Position */ +#define UART_IDR_TXRDY_Msk (_U_(0x1) << UART_IDR_TXRDY_Pos) /**< (UART_IDR) Disable TXRDY Interrupt Mask */ +#define UART_IDR_TXRDY(value) (UART_IDR_TXRDY_Msk & ((value) << UART_IDR_TXRDY_Pos)) +#define UART_IDR_OVRE_Pos _U_(5) /**< (UART_IDR) Disable Overrun Error Interrupt Position */ +#define UART_IDR_OVRE_Msk (_U_(0x1) << UART_IDR_OVRE_Pos) /**< (UART_IDR) Disable Overrun Error Interrupt Mask */ +#define UART_IDR_OVRE(value) (UART_IDR_OVRE_Msk & ((value) << UART_IDR_OVRE_Pos)) +#define UART_IDR_FRAME_Pos _U_(6) /**< (UART_IDR) Disable Framing Error Interrupt Position */ +#define UART_IDR_FRAME_Msk (_U_(0x1) << UART_IDR_FRAME_Pos) /**< (UART_IDR) Disable Framing Error Interrupt Mask */ +#define UART_IDR_FRAME(value) (UART_IDR_FRAME_Msk & ((value) << UART_IDR_FRAME_Pos)) +#define UART_IDR_PARE_Pos _U_(7) /**< (UART_IDR) Disable Parity Error Interrupt Position */ +#define UART_IDR_PARE_Msk (_U_(0x1) << UART_IDR_PARE_Pos) /**< (UART_IDR) Disable Parity Error Interrupt Mask */ +#define UART_IDR_PARE(value) (UART_IDR_PARE_Msk & ((value) << UART_IDR_PARE_Pos)) +#define UART_IDR_TXEMPTY_Pos _U_(9) /**< (UART_IDR) Disable TXEMPTY Interrupt Position */ +#define UART_IDR_TXEMPTY_Msk (_U_(0x1) << UART_IDR_TXEMPTY_Pos) /**< (UART_IDR) Disable TXEMPTY Interrupt Mask */ +#define UART_IDR_TXEMPTY(value) (UART_IDR_TXEMPTY_Msk & ((value) << UART_IDR_TXEMPTY_Pos)) +#define UART_IDR_CMP_Pos _U_(15) /**< (UART_IDR) Disable Comparison Interrupt Position */ +#define UART_IDR_CMP_Msk (_U_(0x1) << UART_IDR_CMP_Pos) /**< (UART_IDR) Disable Comparison Interrupt Mask */ +#define UART_IDR_CMP(value) (UART_IDR_CMP_Msk & ((value) << UART_IDR_CMP_Pos)) +#define UART_IDR_Msk _U_(0x000082E3) /**< (UART_IDR) Register Mask */ + + +/* -------- UART_IMR : (UART Offset: 0x10) ( R/ 32) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY_Pos _U_(0) /**< (UART_IMR) Mask RXRDY Interrupt Position */ +#define UART_IMR_RXRDY_Msk (_U_(0x1) << UART_IMR_RXRDY_Pos) /**< (UART_IMR) Mask RXRDY Interrupt Mask */ +#define UART_IMR_RXRDY(value) (UART_IMR_RXRDY_Msk & ((value) << UART_IMR_RXRDY_Pos)) +#define UART_IMR_TXRDY_Pos _U_(1) /**< (UART_IMR) Disable TXRDY Interrupt Position */ +#define UART_IMR_TXRDY_Msk (_U_(0x1) << UART_IMR_TXRDY_Pos) /**< (UART_IMR) Disable TXRDY Interrupt Mask */ +#define UART_IMR_TXRDY(value) (UART_IMR_TXRDY_Msk & ((value) << UART_IMR_TXRDY_Pos)) +#define UART_IMR_OVRE_Pos _U_(5) /**< (UART_IMR) Mask Overrun Error Interrupt Position */ +#define UART_IMR_OVRE_Msk (_U_(0x1) << UART_IMR_OVRE_Pos) /**< (UART_IMR) Mask Overrun Error Interrupt Mask */ +#define UART_IMR_OVRE(value) (UART_IMR_OVRE_Msk & ((value) << UART_IMR_OVRE_Pos)) +#define UART_IMR_FRAME_Pos _U_(6) /**< (UART_IMR) Mask Framing Error Interrupt Position */ +#define UART_IMR_FRAME_Msk (_U_(0x1) << UART_IMR_FRAME_Pos) /**< (UART_IMR) Mask Framing Error Interrupt Mask */ +#define UART_IMR_FRAME(value) (UART_IMR_FRAME_Msk & ((value) << UART_IMR_FRAME_Pos)) +#define UART_IMR_PARE_Pos _U_(7) /**< (UART_IMR) Mask Parity Error Interrupt Position */ +#define UART_IMR_PARE_Msk (_U_(0x1) << UART_IMR_PARE_Pos) /**< (UART_IMR) Mask Parity Error Interrupt Mask */ +#define UART_IMR_PARE(value) (UART_IMR_PARE_Msk & ((value) << UART_IMR_PARE_Pos)) +#define UART_IMR_TXEMPTY_Pos _U_(9) /**< (UART_IMR) Mask TXEMPTY Interrupt Position */ +#define UART_IMR_TXEMPTY_Msk (_U_(0x1) << UART_IMR_TXEMPTY_Pos) /**< (UART_IMR) Mask TXEMPTY Interrupt Mask */ +#define UART_IMR_TXEMPTY(value) (UART_IMR_TXEMPTY_Msk & ((value) << UART_IMR_TXEMPTY_Pos)) +#define UART_IMR_CMP_Pos _U_(15) /**< (UART_IMR) Mask Comparison Interrupt Position */ +#define UART_IMR_CMP_Msk (_U_(0x1) << UART_IMR_CMP_Pos) /**< (UART_IMR) Mask Comparison Interrupt Mask */ +#define UART_IMR_CMP(value) (UART_IMR_CMP_Msk & ((value) << UART_IMR_CMP_Pos)) +#define UART_IMR_Msk _U_(0x000082E3) /**< (UART_IMR) Register Mask */ + + +/* -------- UART_SR : (UART Offset: 0x14) ( R/ 32) Status Register -------- */ +#define UART_SR_RXRDY_Pos _U_(0) /**< (UART_SR) Receiver Ready Position */ +#define UART_SR_RXRDY_Msk (_U_(0x1) << UART_SR_RXRDY_Pos) /**< (UART_SR) Receiver Ready Mask */ +#define UART_SR_RXRDY(value) (UART_SR_RXRDY_Msk & ((value) << UART_SR_RXRDY_Pos)) +#define UART_SR_TXRDY_Pos _U_(1) /**< (UART_SR) Transmitter Ready Position */ +#define UART_SR_TXRDY_Msk (_U_(0x1) << UART_SR_TXRDY_Pos) /**< (UART_SR) Transmitter Ready Mask */ +#define UART_SR_TXRDY(value) (UART_SR_TXRDY_Msk & ((value) << UART_SR_TXRDY_Pos)) +#define UART_SR_OVRE_Pos _U_(5) /**< (UART_SR) Overrun Error Position */ +#define UART_SR_OVRE_Msk (_U_(0x1) << UART_SR_OVRE_Pos) /**< (UART_SR) Overrun Error Mask */ +#define UART_SR_OVRE(value) (UART_SR_OVRE_Msk & ((value) << UART_SR_OVRE_Pos)) +#define UART_SR_FRAME_Pos _U_(6) /**< (UART_SR) Framing Error Position */ +#define UART_SR_FRAME_Msk (_U_(0x1) << UART_SR_FRAME_Pos) /**< (UART_SR) Framing Error Mask */ +#define UART_SR_FRAME(value) (UART_SR_FRAME_Msk & ((value) << UART_SR_FRAME_Pos)) +#define UART_SR_PARE_Pos _U_(7) /**< (UART_SR) Parity Error Position */ +#define UART_SR_PARE_Msk (_U_(0x1) << UART_SR_PARE_Pos) /**< (UART_SR) Parity Error Mask */ +#define UART_SR_PARE(value) (UART_SR_PARE_Msk & ((value) << UART_SR_PARE_Pos)) +#define UART_SR_TXEMPTY_Pos _U_(9) /**< (UART_SR) Transmitter Empty Position */ +#define UART_SR_TXEMPTY_Msk (_U_(0x1) << UART_SR_TXEMPTY_Pos) /**< (UART_SR) Transmitter Empty Mask */ +#define UART_SR_TXEMPTY(value) (UART_SR_TXEMPTY_Msk & ((value) << UART_SR_TXEMPTY_Pos)) +#define UART_SR_CMP_Pos _U_(15) /**< (UART_SR) Comparison Match Position */ +#define UART_SR_CMP_Msk (_U_(0x1) << UART_SR_CMP_Pos) /**< (UART_SR) Comparison Match Mask */ +#define UART_SR_CMP(value) (UART_SR_CMP_Msk & ((value) << UART_SR_CMP_Pos)) +#define UART_SR_Msk _U_(0x000082E3) /**< (UART_SR) Register Mask */ + + +/* -------- UART_RHR : (UART Offset: 0x18) ( R/ 32) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos _U_(0) /**< (UART_RHR) Received Character Position */ +#define UART_RHR_RXCHR_Msk (_U_(0xFF) << UART_RHR_RXCHR_Pos) /**< (UART_RHR) Received Character Mask */ +#define UART_RHR_RXCHR(value) (UART_RHR_RXCHR_Msk & ((value) << UART_RHR_RXCHR_Pos)) +#define UART_RHR_Msk _U_(0x000000FF) /**< (UART_RHR) Register Mask */ + + +/* -------- UART_THR : (UART Offset: 0x1C) ( /W 32) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos _U_(0) /**< (UART_THR) Character to be Transmitted Position */ +#define UART_THR_TXCHR_Msk (_U_(0xFF) << UART_THR_TXCHR_Pos) /**< (UART_THR) Character to be Transmitted Mask */ +#define UART_THR_TXCHR(value) (UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)) +#define UART_THR_Msk _U_(0x000000FF) /**< (UART_THR) Register Mask */ + + +/* -------- UART_BRGR : (UART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos _U_(0) /**< (UART_BRGR) Clock Divisor Position */ +#define UART_BRGR_CD_Msk (_U_(0xFFFF) << UART_BRGR_CD_Pos) /**< (UART_BRGR) Clock Divisor Mask */ +#define UART_BRGR_CD(value) (UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)) +#define UART_BRGR_Msk _U_(0x0000FFFF) /**< (UART_BRGR) Register Mask */ + + +/* -------- UART_CMPR : (UART Offset: 0x24) (R/W 32) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos _U_(0) /**< (UART_CMPR) First Comparison Value for Received Character Position */ +#define UART_CMPR_VAL1_Msk (_U_(0xFF) << UART_CMPR_VAL1_Pos) /**< (UART_CMPR) First Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL1(value) (UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)) +#define UART_CMPR_CMPMODE_Pos _U_(12) /**< (UART_CMPR) Comparison Mode Position */ +#define UART_CMPR_CMPMODE_Msk (_U_(0x1) << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison Mode Mask */ +#define UART_CMPR_CMPMODE(value) (UART_CMPR_CMPMODE_Msk & ((value) << UART_CMPR_CMPMODE_Pos)) +#define UART_CMPR_CMPMODE_FLAG_ONLY_Val _U_(0x0) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION_Val _U_(0x1) /**< (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (UART_CMPR_CMPMODE_FLAG_ONLY_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. Position */ +#define UART_CMPR_CMPMODE_START_CONDITION (UART_CMPR_CMPMODE_START_CONDITION_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison condition must be met to start reception. Position */ +#define UART_CMPR_CMPPAR_Pos _U_(14) /**< (UART_CMPR) Compare Parity Position */ +#define UART_CMPR_CMPPAR_Msk (_U_(0x1) << UART_CMPR_CMPPAR_Pos) /**< (UART_CMPR) Compare Parity Mask */ +#define UART_CMPR_CMPPAR(value) (UART_CMPR_CMPPAR_Msk & ((value) << UART_CMPR_CMPPAR_Pos)) +#define UART_CMPR_VAL2_Pos _U_(16) /**< (UART_CMPR) Second Comparison Value for Received Character Position */ +#define UART_CMPR_VAL2_Msk (_U_(0xFF) << UART_CMPR_VAL2_Pos) /**< (UART_CMPR) Second Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL2(value) (UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)) +#define UART_CMPR_Msk _U_(0x00FF50FF) /**< (UART_CMPR) Register Mask */ + + +/* -------- UART_WPMR : (UART Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN_Pos _U_(0) /**< (UART_WPMR) Write Protection Enable Position */ +#define UART_WPMR_WPEN_Msk (_U_(0x1) << UART_WPMR_WPEN_Pos) /**< (UART_WPMR) Write Protection Enable Mask */ +#define UART_WPMR_WPEN(value) (UART_WPMR_WPEN_Msk & ((value) << UART_WPMR_WPEN_Pos)) +#define UART_WPMR_WPKEY_Pos _U_(8) /**< (UART_WPMR) Write Protection Key Position */ +#define UART_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Write Protection Key Mask */ +#define UART_WPMR_WPKEY(value) (UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)) +#define UART_WPMR_WPKEY_PASSWD_Val _U_(0x554152) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define UART_WPMR_WPKEY_PASSWD (UART_WPMR_WPKEY_PASSWD_Val << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define UART_WPMR_Msk _U_(0xFFFFFF01) /**< (UART_WPMR) Register Mask */ + + +/** \brief UART register offsets definitions */ +#define UART_CR_REG_OFST (0x00) /**< (UART_CR) Control Register Offset */ +#define UART_MR_REG_OFST (0x04) /**< (UART_MR) Mode Register Offset */ +#define UART_IER_REG_OFST (0x08) /**< (UART_IER) Interrupt Enable Register Offset */ +#define UART_IDR_REG_OFST (0x0C) /**< (UART_IDR) Interrupt Disable Register Offset */ +#define UART_IMR_REG_OFST (0x10) /**< (UART_IMR) Interrupt Mask Register Offset */ +#define UART_SR_REG_OFST (0x14) /**< (UART_SR) Status Register Offset */ +#define UART_RHR_REG_OFST (0x18) /**< (UART_RHR) Receive Holding Register Offset */ +#define UART_THR_REG_OFST (0x1C) /**< (UART_THR) Transmit Holding Register Offset */ +#define UART_BRGR_REG_OFST (0x20) /**< (UART_BRGR) Baud Rate Generator Register Offset */ +#define UART_CMPR_REG_OFST (0x24) /**< (UART_CMPR) Comparison Register Offset */ +#define UART_WPMR_REG_OFST (0xE4) /**< (UART_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UART register API structure */ +typedef struct +{ + __O uint32_t UART_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t UART_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O uint32_t UART_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< Offset: 0x14 (R/ 32) Status Register */ + __I uint32_t UART_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O uint32_t UART_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< Offset: 0x24 (R/W 32) Comparison Register */ + __I uint8_t Reserved1[0xBC]; + __IO uint32_t UART_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} uart_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_UART_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/usart.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/usart.h new file mode 100644 index 00000000..3af869a2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/usart.h @@ -0,0 +1,802 @@ +/** + * \brief Component description for USART + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_USART_COMPONENT_H_ +#define _SAME70_USART_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USART */ +/* ************************************************************************** */ + +/* -------- US_CR : (USART Offset: 0x00) ( /W 32) Control Register -------- */ +#define US_CR_RSTRX_Pos _U_(2) /**< (US_CR) Reset Receiver Position */ +#define US_CR_RSTRX_Msk (_U_(0x1) << US_CR_RSTRX_Pos) /**< (US_CR) Reset Receiver Mask */ +#define US_CR_RSTRX(value) (US_CR_RSTRX_Msk & ((value) << US_CR_RSTRX_Pos)) +#define US_CR_RSTTX_Pos _U_(3) /**< (US_CR) Reset Transmitter Position */ +#define US_CR_RSTTX_Msk (_U_(0x1) << US_CR_RSTTX_Pos) /**< (US_CR) Reset Transmitter Mask */ +#define US_CR_RSTTX(value) (US_CR_RSTTX_Msk & ((value) << US_CR_RSTTX_Pos)) +#define US_CR_RXEN_Pos _U_(4) /**< (US_CR) Receiver Enable Position */ +#define US_CR_RXEN_Msk (_U_(0x1) << US_CR_RXEN_Pos) /**< (US_CR) Receiver Enable Mask */ +#define US_CR_RXEN(value) (US_CR_RXEN_Msk & ((value) << US_CR_RXEN_Pos)) +#define US_CR_RXDIS_Pos _U_(5) /**< (US_CR) Receiver Disable Position */ +#define US_CR_RXDIS_Msk (_U_(0x1) << US_CR_RXDIS_Pos) /**< (US_CR) Receiver Disable Mask */ +#define US_CR_RXDIS(value) (US_CR_RXDIS_Msk & ((value) << US_CR_RXDIS_Pos)) +#define US_CR_TXEN_Pos _U_(6) /**< (US_CR) Transmitter Enable Position */ +#define US_CR_TXEN_Msk (_U_(0x1) << US_CR_TXEN_Pos) /**< (US_CR) Transmitter Enable Mask */ +#define US_CR_TXEN(value) (US_CR_TXEN_Msk & ((value) << US_CR_TXEN_Pos)) +#define US_CR_TXDIS_Pos _U_(7) /**< (US_CR) Transmitter Disable Position */ +#define US_CR_TXDIS_Msk (_U_(0x1) << US_CR_TXDIS_Pos) /**< (US_CR) Transmitter Disable Mask */ +#define US_CR_TXDIS(value) (US_CR_TXDIS_Msk & ((value) << US_CR_TXDIS_Pos)) +#define US_CR_RSTSTA_Pos _U_(8) /**< (US_CR) Reset Status Bits Position */ +#define US_CR_RSTSTA_Msk (_U_(0x1) << US_CR_RSTSTA_Pos) /**< (US_CR) Reset Status Bits Mask */ +#define US_CR_RSTSTA(value) (US_CR_RSTSTA_Msk & ((value) << US_CR_RSTSTA_Pos)) +#define US_CR_STTBRK_Pos _U_(9) /**< (US_CR) Start Break Position */ +#define US_CR_STTBRK_Msk (_U_(0x1) << US_CR_STTBRK_Pos) /**< (US_CR) Start Break Mask */ +#define US_CR_STTBRK(value) (US_CR_STTBRK_Msk & ((value) << US_CR_STTBRK_Pos)) +#define US_CR_STPBRK_Pos _U_(10) /**< (US_CR) Stop Break Position */ +#define US_CR_STPBRK_Msk (_U_(0x1) << US_CR_STPBRK_Pos) /**< (US_CR) Stop Break Mask */ +#define US_CR_STPBRK(value) (US_CR_STPBRK_Msk & ((value) << US_CR_STPBRK_Pos)) +#define US_CR_STTTO_Pos _U_(11) /**< (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received Position */ +#define US_CR_STTTO_Msk (_U_(0x1) << US_CR_STTTO_Pos) /**< (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received Mask */ +#define US_CR_STTTO(value) (US_CR_STTTO_Msk & ((value) << US_CR_STTTO_Pos)) +#define US_CR_SENDA_Pos _U_(12) /**< (US_CR) Send Address Position */ +#define US_CR_SENDA_Msk (_U_(0x1) << US_CR_SENDA_Pos) /**< (US_CR) Send Address Mask */ +#define US_CR_SENDA(value) (US_CR_SENDA_Msk & ((value) << US_CR_SENDA_Pos)) +#define US_CR_RSTIT_Pos _U_(13) /**< (US_CR) Reset Iterations Position */ +#define US_CR_RSTIT_Msk (_U_(0x1) << US_CR_RSTIT_Pos) /**< (US_CR) Reset Iterations Mask */ +#define US_CR_RSTIT(value) (US_CR_RSTIT_Msk & ((value) << US_CR_RSTIT_Pos)) +#define US_CR_RSTNACK_Pos _U_(14) /**< (US_CR) Reset Non Acknowledge Position */ +#define US_CR_RSTNACK_Msk (_U_(0x1) << US_CR_RSTNACK_Pos) /**< (US_CR) Reset Non Acknowledge Mask */ +#define US_CR_RSTNACK(value) (US_CR_RSTNACK_Msk & ((value) << US_CR_RSTNACK_Pos)) +#define US_CR_RETTO_Pos _U_(15) /**< (US_CR) Start Time-out Immediately Position */ +#define US_CR_RETTO_Msk (_U_(0x1) << US_CR_RETTO_Pos) /**< (US_CR) Start Time-out Immediately Mask */ +#define US_CR_RETTO(value) (US_CR_RETTO_Msk & ((value) << US_CR_RETTO_Pos)) +#define US_CR_DTREN_Pos _U_(16) /**< (US_CR) Data Terminal Ready Enable Position */ +#define US_CR_DTREN_Msk (_U_(0x1) << US_CR_DTREN_Pos) /**< (US_CR) Data Terminal Ready Enable Mask */ +#define US_CR_DTREN(value) (US_CR_DTREN_Msk & ((value) << US_CR_DTREN_Pos)) +#define US_CR_DTRDIS_Pos _U_(17) /**< (US_CR) Data Terminal Ready Disable Position */ +#define US_CR_DTRDIS_Msk (_U_(0x1) << US_CR_DTRDIS_Pos) /**< (US_CR) Data Terminal Ready Disable Mask */ +#define US_CR_DTRDIS(value) (US_CR_DTRDIS_Msk & ((value) << US_CR_DTRDIS_Pos)) +#define US_CR_RTSEN_Pos _U_(18) /**< (US_CR) Request to Send Pin Control Position */ +#define US_CR_RTSEN_Msk (_U_(0x1) << US_CR_RTSEN_Pos) /**< (US_CR) Request to Send Pin Control Mask */ +#define US_CR_RTSEN(value) (US_CR_RTSEN_Msk & ((value) << US_CR_RTSEN_Pos)) +#define US_CR_RTSDIS_Pos _U_(19) /**< (US_CR) Request to Send Pin Control Position */ +#define US_CR_RTSDIS_Msk (_U_(0x1) << US_CR_RTSDIS_Pos) /**< (US_CR) Request to Send Pin Control Mask */ +#define US_CR_RTSDIS(value) (US_CR_RTSDIS_Msk & ((value) << US_CR_RTSDIS_Pos)) +#define US_CR_LINABT_Pos _U_(20) /**< (US_CR) Abort LIN Transmission Position */ +#define US_CR_LINABT_Msk (_U_(0x1) << US_CR_LINABT_Pos) /**< (US_CR) Abort LIN Transmission Mask */ +#define US_CR_LINABT(value) (US_CR_LINABT_Msk & ((value) << US_CR_LINABT_Pos)) +#define US_CR_LINWKUP_Pos _U_(21) /**< (US_CR) Send LIN Wakeup Signal Position */ +#define US_CR_LINWKUP_Msk (_U_(0x1) << US_CR_LINWKUP_Pos) /**< (US_CR) Send LIN Wakeup Signal Mask */ +#define US_CR_LINWKUP(value) (US_CR_LINWKUP_Msk & ((value) << US_CR_LINWKUP_Pos)) +#define US_CR_Msk _U_(0x003FFFFC) /**< (US_CR) Register Mask */ + + +/* -------- US_MR : (USART Offset: 0x04) (R/W 32) Mode Register -------- */ +#define US_MR_USART_MODE_Pos _U_(0) /**< (US_MR) USART Mode of Operation Position */ +#define US_MR_USART_MODE_Msk (_U_(0xF) << US_MR_USART_MODE_Pos) /**< (US_MR) USART Mode of Operation Mask */ +#define US_MR_USART_MODE(value) (US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)) +#define US_MR_USART_MODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485_Val _U_(0x1) /**< (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING_Val _U_(0x2) /**< (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM_Val _U_(0x3) /**< (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0_Val _U_(0x4) /**< (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1_Val _U_(0x6) /**< (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA_Val _U_(0x8) /**< (US_MR) IrDA */ +#define US_MR_USART_MODE_LON_Val _U_(0x9) /**< (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER_Val _U_(0xE) /**< (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE_Val _U_(0xF) /**< (US_MR) SPI Slave */ +#define US_MR_USART_MODE_NORMAL (US_MR_USART_MODE_NORMAL_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_USART_MODE_RS485 (US_MR_USART_MODE_RS485_Val << US_MR_USART_MODE_Pos) /**< (US_MR) RS485 Position */ +#define US_MR_USART_MODE_HW_HANDSHAKING (US_MR_USART_MODE_HW_HANDSHAKING_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Hardware Handshaking Position */ +#define US_MR_USART_MODE_MODEM (US_MR_USART_MODE_MODEM_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Modem Position */ +#define US_MR_USART_MODE_IS07816_T_0 (US_MR_USART_MODE_IS07816_T_0_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 0 Position */ +#define US_MR_USART_MODE_IS07816_T_1 (US_MR_USART_MODE_IS07816_T_1_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 1 Position */ +#define US_MR_USART_MODE_IRDA (US_MR_USART_MODE_IRDA_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IrDA Position */ +#define US_MR_USART_MODE_LON (US_MR_USART_MODE_LON_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LON Position */ +#define US_MR_USART_MODE_SPI_MASTER (US_MR_USART_MODE_SPI_MASTER_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI master Position */ +#define US_MR_USART_MODE_SPI_SLAVE (US_MR_USART_MODE_SPI_SLAVE_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI Slave Position */ +#define US_MR_USCLKS_Pos _U_(4) /**< (US_MR) Clock Selection Position */ +#define US_MR_USCLKS_Msk (_U_(0x3) << US_MR_USCLKS_Pos) /**< (US_MR) Clock Selection Mask */ +#define US_MR_USCLKS(value) (US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)) +#define US_MR_USCLKS_MCK_Val _U_(0x0) /**< (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV_Val _U_(0x1) /**< (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK_Val _U_(0x2) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK_Val _U_(0x3) /**< (US_MR) Serial clock (SCK) is selected */ +#define US_MR_USCLKS_MCK (US_MR_USCLKS_MCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) Peripheral clock is selected Position */ +#define US_MR_USCLKS_DIV (US_MR_USCLKS_DIV_Val << US_MR_USCLKS_Pos) /**< (US_MR) Peripheral clock divided (DIV=DIV=8) is selected Position */ +#define US_MR_USCLKS_PCK (US_MR_USCLKS_PCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. Position */ +#define US_MR_USCLKS_SCK (US_MR_USCLKS_SCK_Val << US_MR_USCLKS_Pos) /**< (US_MR) Serial clock (SCK) is selected Position */ +#define US_MR_CHRL_Pos _U_(6) /**< (US_MR) Character Length Position */ +#define US_MR_CHRL_Msk (_U_(0x3) << US_MR_CHRL_Pos) /**< (US_MR) Character Length Mask */ +#define US_MR_CHRL(value) (US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)) +#define US_MR_CHRL_5_BIT_Val _U_(0x0) /**< (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT_Val _U_(0x1) /**< (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT_Val _U_(0x2) /**< (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT_Val _U_(0x3) /**< (US_MR) Character length is 8 bits */ +#define US_MR_CHRL_5_BIT (US_MR_CHRL_5_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 5 bits Position */ +#define US_MR_CHRL_6_BIT (US_MR_CHRL_6_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 6 bits Position */ +#define US_MR_CHRL_7_BIT (US_MR_CHRL_7_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 7 bits Position */ +#define US_MR_CHRL_8_BIT (US_MR_CHRL_8_BIT_Val << US_MR_CHRL_Pos) /**< (US_MR) Character length is 8 bits Position */ +#define US_MR_SYNC_Pos _U_(8) /**< (US_MR) Synchronous Mode Select Position */ +#define US_MR_SYNC_Msk (_U_(0x1) << US_MR_SYNC_Pos) /**< (US_MR) Synchronous Mode Select Mask */ +#define US_MR_SYNC(value) (US_MR_SYNC_Msk & ((value) << US_MR_SYNC_Pos)) +#define US_MR_PAR_Pos _U_(9) /**< (US_MR) Parity Type Position */ +#define US_MR_PAR_Msk (_U_(0x7) << US_MR_PAR_Pos) /**< (US_MR) Parity Type Mask */ +#define US_MR_PAR(value) (US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)) +#define US_MR_PAR_EVEN_Val _U_(0x0) /**< (US_MR) Even parity */ +#define US_MR_PAR_ODD_Val _U_(0x1) /**< (US_MR) Odd parity */ +#define US_MR_PAR_SPACE_Val _U_(0x2) /**< (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK_Val _U_(0x3) /**< (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO_Val _U_(0x4) /**< (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP_Val _U_(0x6) /**< (US_MR) Multidrop mode */ +#define US_MR_PAR_EVEN (US_MR_PAR_EVEN_Val << US_MR_PAR_Pos) /**< (US_MR) Even parity Position */ +#define US_MR_PAR_ODD (US_MR_PAR_ODD_Val << US_MR_PAR_Pos) /**< (US_MR) Odd parity Position */ +#define US_MR_PAR_SPACE (US_MR_PAR_SPACE_Val << US_MR_PAR_Pos) /**< (US_MR) Parity forced to 0 (Space) Position */ +#define US_MR_PAR_MARK (US_MR_PAR_MARK_Val << US_MR_PAR_Pos) /**< (US_MR) Parity forced to 1 (Mark) Position */ +#define US_MR_PAR_NO (US_MR_PAR_NO_Val << US_MR_PAR_Pos) /**< (US_MR) No parity Position */ +#define US_MR_PAR_MULTIDROP (US_MR_PAR_MULTIDROP_Val << US_MR_PAR_Pos) /**< (US_MR) Multidrop mode Position */ +#define US_MR_NBSTOP_Pos _U_(12) /**< (US_MR) Number of Stop Bits Position */ +#define US_MR_NBSTOP_Msk (_U_(0x3) << US_MR_NBSTOP_Pos) /**< (US_MR) Number of Stop Bits Mask */ +#define US_MR_NBSTOP(value) (US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)) +#define US_MR_NBSTOP_1_BIT_Val _U_(0x0) /**< (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT_Val _U_(0x1) /**< (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT_Val _U_(0x2) /**< (US_MR) 2 stop bits */ +#define US_MR_NBSTOP_1_BIT (US_MR_NBSTOP_1_BIT_Val << US_MR_NBSTOP_Pos) /**< (US_MR) 1 stop bit Position */ +#define US_MR_NBSTOP_1_5_BIT (US_MR_NBSTOP_1_5_BIT_Val << US_MR_NBSTOP_Pos) /**< (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) Position */ +#define US_MR_NBSTOP_2_BIT (US_MR_NBSTOP_2_BIT_Val << US_MR_NBSTOP_Pos) /**< (US_MR) 2 stop bits Position */ +#define US_MR_CHMODE_Pos _U_(14) /**< (US_MR) Channel Mode Position */ +#define US_MR_CHMODE_Msk (_U_(0x3) << US_MR_CHMODE_Pos) /**< (US_MR) Channel Mode Mask */ +#define US_MR_CHMODE(value) (US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)) +#define US_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_CHMODE_NORMAL (US_MR_CHMODE_NORMAL_Val << US_MR_CHMODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_CHMODE_AUTOMATIC (US_MR_CHMODE_AUTOMATIC_Val << US_MR_CHMODE_Pos) /**< (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. Position */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (US_MR_CHMODE_LOCAL_LOOPBACK_Val << US_MR_CHMODE_Pos) /**< (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. Position */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (US_MR_CHMODE_REMOTE_LOOPBACK_Val << US_MR_CHMODE_Pos) /**< (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. Position */ +#define US_MR_MSBF_Pos _U_(16) /**< (US_MR) Bit Order Position */ +#define US_MR_MSBF_Msk (_U_(0x1) << US_MR_MSBF_Pos) /**< (US_MR) Bit Order Mask */ +#define US_MR_MSBF(value) (US_MR_MSBF_Msk & ((value) << US_MR_MSBF_Pos)) +#define US_MR_MODE9_Pos _U_(17) /**< (US_MR) 9-bit Character Length Position */ +#define US_MR_MODE9_Msk (_U_(0x1) << US_MR_MODE9_Pos) /**< (US_MR) 9-bit Character Length Mask */ +#define US_MR_MODE9(value) (US_MR_MODE9_Msk & ((value) << US_MR_MODE9_Pos)) +#define US_MR_CLKO_Pos _U_(18) /**< (US_MR) Clock Output Select Position */ +#define US_MR_CLKO_Msk (_U_(0x1) << US_MR_CLKO_Pos) /**< (US_MR) Clock Output Select Mask */ +#define US_MR_CLKO(value) (US_MR_CLKO_Msk & ((value) << US_MR_CLKO_Pos)) +#define US_MR_OVER_Pos _U_(19) /**< (US_MR) Oversampling Mode Position */ +#define US_MR_OVER_Msk (_U_(0x1) << US_MR_OVER_Pos) /**< (US_MR) Oversampling Mode Mask */ +#define US_MR_OVER(value) (US_MR_OVER_Msk & ((value) << US_MR_OVER_Pos)) +#define US_MR_INACK_Pos _U_(20) /**< (US_MR) Inhibit Non Acknowledge Position */ +#define US_MR_INACK_Msk (_U_(0x1) << US_MR_INACK_Pos) /**< (US_MR) Inhibit Non Acknowledge Mask */ +#define US_MR_INACK(value) (US_MR_INACK_Msk & ((value) << US_MR_INACK_Pos)) +#define US_MR_DSNACK_Pos _U_(21) /**< (US_MR) Disable Successive NACK Position */ +#define US_MR_DSNACK_Msk (_U_(0x1) << US_MR_DSNACK_Pos) /**< (US_MR) Disable Successive NACK Mask */ +#define US_MR_DSNACK(value) (US_MR_DSNACK_Msk & ((value) << US_MR_DSNACK_Pos)) +#define US_MR_VAR_SYNC_Pos _U_(22) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Position */ +#define US_MR_VAR_SYNC_Msk (_U_(0x1) << US_MR_VAR_SYNC_Pos) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Mask */ +#define US_MR_VAR_SYNC(value) (US_MR_VAR_SYNC_Msk & ((value) << US_MR_VAR_SYNC_Pos)) +#define US_MR_INVDATA_Pos _U_(23) /**< (US_MR) Inverted Data Position */ +#define US_MR_INVDATA_Msk (_U_(0x1) << US_MR_INVDATA_Pos) /**< (US_MR) Inverted Data Mask */ +#define US_MR_INVDATA(value) (US_MR_INVDATA_Msk & ((value) << US_MR_INVDATA_Pos)) +#define US_MR_MAX_ITERATION_Pos _U_(24) /**< (US_MR) Maximum Number of Automatic Iteration Position */ +#define US_MR_MAX_ITERATION_Msk (_U_(0x7) << US_MR_MAX_ITERATION_Pos) /**< (US_MR) Maximum Number of Automatic Iteration Mask */ +#define US_MR_MAX_ITERATION(value) (US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)) +#define US_MR_FILTER_Pos _U_(28) /**< (US_MR) Receive Line Filter Position */ +#define US_MR_FILTER_Msk (_U_(0x1) << US_MR_FILTER_Pos) /**< (US_MR) Receive Line Filter Mask */ +#define US_MR_FILTER(value) (US_MR_FILTER_Msk & ((value) << US_MR_FILTER_Pos)) +#define US_MR_MAN_Pos _U_(29) /**< (US_MR) Manchester Encoder/Decoder Enable Position */ +#define US_MR_MAN_Msk (_U_(0x1) << US_MR_MAN_Pos) /**< (US_MR) Manchester Encoder/Decoder Enable Mask */ +#define US_MR_MAN(value) (US_MR_MAN_Msk & ((value) << US_MR_MAN_Pos)) +#define US_MR_MODSYNC_Pos _U_(30) /**< (US_MR) Manchester Synchronization Mode Position */ +#define US_MR_MODSYNC_Msk (_U_(0x1) << US_MR_MODSYNC_Pos) /**< (US_MR) Manchester Synchronization Mode Mask */ +#define US_MR_MODSYNC(value) (US_MR_MODSYNC_Msk & ((value) << US_MR_MODSYNC_Pos)) +#define US_MR_ONEBIT_Pos _U_(31) /**< (US_MR) Start Frame Delimiter Selector Position */ +#define US_MR_ONEBIT_Msk (_U_(0x1) << US_MR_ONEBIT_Pos) /**< (US_MR) Start Frame Delimiter Selector Mask */ +#define US_MR_ONEBIT(value) (US_MR_ONEBIT_Msk & ((value) << US_MR_ONEBIT_Pos)) +#define US_MR_Msk _U_(0xF7FFFFFF) /**< (US_MR) Register Mask */ + +#define US_MR_MODE_Pos _U_(17) /**< (US_MR Position) 9-bit Character Length */ +#define US_MR_MODE_Msk (_U_(0x1) << US_MR_MODE_Pos) /**< (US_MR Mask) MODE */ +#define US_MR_MODE(value) (US_MR_MODE_Msk & ((value) << US_MR_MODE_Pos)) + +/* -------- US_IER : (USART Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */ +#define US_IER_RXRDY_Pos _U_(0) /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_RXRDY_Msk (_U_(0x1) << US_IER_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_RXRDY(value) (US_IER_RXRDY_Msk & ((value) << US_IER_RXRDY_Pos)) +#define US_IER_TXRDY_Pos _U_(1) /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_TXRDY_Msk (_U_(0x1) << US_IER_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_TXRDY(value) (US_IER_TXRDY_Msk & ((value) << US_IER_TXRDY_Pos)) +#define US_IER_RXBRK_Pos _U_(2) /**< (US_IER) Receiver Break Interrupt Enable Position */ +#define US_IER_RXBRK_Msk (_U_(0x1) << US_IER_RXBRK_Pos) /**< (US_IER) Receiver Break Interrupt Enable Mask */ +#define US_IER_RXBRK(value) (US_IER_RXBRK_Msk & ((value) << US_IER_RXBRK_Pos)) +#define US_IER_OVRE_Pos _U_(5) /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_OVRE_Msk (_U_(0x1) << US_IER_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_OVRE(value) (US_IER_OVRE_Msk & ((value) << US_IER_OVRE_Pos)) +#define US_IER_FRAME_Pos _U_(6) /**< (US_IER) Framing Error Interrupt Enable Position */ +#define US_IER_FRAME_Msk (_U_(0x1) << US_IER_FRAME_Pos) /**< (US_IER) Framing Error Interrupt Enable Mask */ +#define US_IER_FRAME(value) (US_IER_FRAME_Msk & ((value) << US_IER_FRAME_Pos)) +#define US_IER_PARE_Pos _U_(7) /**< (US_IER) Parity Error Interrupt Enable Position */ +#define US_IER_PARE_Msk (_U_(0x1) << US_IER_PARE_Pos) /**< (US_IER) Parity Error Interrupt Enable Mask */ +#define US_IER_PARE(value) (US_IER_PARE_Msk & ((value) << US_IER_PARE_Pos)) +#define US_IER_TIMEOUT_Pos _U_(8) /**< (US_IER) Time-out Interrupt Enable Position */ +#define US_IER_TIMEOUT_Msk (_U_(0x1) << US_IER_TIMEOUT_Pos) /**< (US_IER) Time-out Interrupt Enable Mask */ +#define US_IER_TIMEOUT(value) (US_IER_TIMEOUT_Msk & ((value) << US_IER_TIMEOUT_Pos)) +#define US_IER_TXEMPTY_Pos _U_(9) /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_TXEMPTY_Msk (_U_(0x1) << US_IER_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_TXEMPTY(value) (US_IER_TXEMPTY_Msk & ((value) << US_IER_TXEMPTY_Pos)) +#define US_IER_ITER_Pos _U_(10) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Position */ +#define US_IER_ITER_Msk (_U_(0x1) << US_IER_ITER_Pos) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Mask */ +#define US_IER_ITER(value) (US_IER_ITER_Msk & ((value) << US_IER_ITER_Pos)) +#define US_IER_NACK_Pos _U_(13) /**< (US_IER) Non Acknowledge Interrupt Enable Position */ +#define US_IER_NACK_Msk (_U_(0x1) << US_IER_NACK_Pos) /**< (US_IER) Non Acknowledge Interrupt Enable Mask */ +#define US_IER_NACK(value) (US_IER_NACK_Msk & ((value) << US_IER_NACK_Pos)) +#define US_IER_RIIC_Pos _U_(16) /**< (US_IER) Ring Indicator Input Change Enable Position */ +#define US_IER_RIIC_Msk (_U_(0x1) << US_IER_RIIC_Pos) /**< (US_IER) Ring Indicator Input Change Enable Mask */ +#define US_IER_RIIC(value) (US_IER_RIIC_Msk & ((value) << US_IER_RIIC_Pos)) +#define US_IER_DSRIC_Pos _U_(17) /**< (US_IER) Data Set Ready Input Change Enable Position */ +#define US_IER_DSRIC_Msk (_U_(0x1) << US_IER_DSRIC_Pos) /**< (US_IER) Data Set Ready Input Change Enable Mask */ +#define US_IER_DSRIC(value) (US_IER_DSRIC_Msk & ((value) << US_IER_DSRIC_Pos)) +#define US_IER_DCDIC_Pos _U_(18) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Position */ +#define US_IER_DCDIC_Msk (_U_(0x1) << US_IER_DCDIC_Pos) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Mask */ +#define US_IER_DCDIC(value) (US_IER_DCDIC_Msk & ((value) << US_IER_DCDIC_Pos)) +#define US_IER_CTSIC_Pos _U_(19) /**< (US_IER) Clear to Send Input Change Interrupt Enable Position */ +#define US_IER_CTSIC_Msk (_U_(0x1) << US_IER_CTSIC_Pos) /**< (US_IER) Clear to Send Input Change Interrupt Enable Mask */ +#define US_IER_CTSIC(value) (US_IER_CTSIC_Msk & ((value) << US_IER_CTSIC_Pos)) +#define US_IER_MANE_Pos _U_(24) /**< (US_IER) Manchester Error Interrupt Enable Position */ +#define US_IER_MANE_Msk (_U_(0x1) << US_IER_MANE_Pos) /**< (US_IER) Manchester Error Interrupt Enable Mask */ +#define US_IER_MANE(value) (US_IER_MANE_Msk & ((value) << US_IER_MANE_Pos)) +#define US_IER_Msk _U_(0x010F27E7) /**< (US_IER) Register Mask */ + + +/* -------- US_IDR : (USART Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY_Pos _U_(0) /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_RXRDY_Msk (_U_(0x1) << US_IDR_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_RXRDY(value) (US_IDR_RXRDY_Msk & ((value) << US_IDR_RXRDY_Pos)) +#define US_IDR_TXRDY_Pos _U_(1) /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_TXRDY_Msk (_U_(0x1) << US_IDR_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_TXRDY(value) (US_IDR_TXRDY_Msk & ((value) << US_IDR_TXRDY_Pos)) +#define US_IDR_RXBRK_Pos _U_(2) /**< (US_IDR) Receiver Break Interrupt Disable Position */ +#define US_IDR_RXBRK_Msk (_U_(0x1) << US_IDR_RXBRK_Pos) /**< (US_IDR) Receiver Break Interrupt Disable Mask */ +#define US_IDR_RXBRK(value) (US_IDR_RXBRK_Msk & ((value) << US_IDR_RXBRK_Pos)) +#define US_IDR_OVRE_Pos _U_(5) /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_OVRE_Msk (_U_(0x1) << US_IDR_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_OVRE(value) (US_IDR_OVRE_Msk & ((value) << US_IDR_OVRE_Pos)) +#define US_IDR_FRAME_Pos _U_(6) /**< (US_IDR) Framing Error Interrupt Disable Position */ +#define US_IDR_FRAME_Msk (_U_(0x1) << US_IDR_FRAME_Pos) /**< (US_IDR) Framing Error Interrupt Disable Mask */ +#define US_IDR_FRAME(value) (US_IDR_FRAME_Msk & ((value) << US_IDR_FRAME_Pos)) +#define US_IDR_PARE_Pos _U_(7) /**< (US_IDR) Parity Error Interrupt Disable Position */ +#define US_IDR_PARE_Msk (_U_(0x1) << US_IDR_PARE_Pos) /**< (US_IDR) Parity Error Interrupt Disable Mask */ +#define US_IDR_PARE(value) (US_IDR_PARE_Msk & ((value) << US_IDR_PARE_Pos)) +#define US_IDR_TIMEOUT_Pos _U_(8) /**< (US_IDR) Time-out Interrupt Disable Position */ +#define US_IDR_TIMEOUT_Msk (_U_(0x1) << US_IDR_TIMEOUT_Pos) /**< (US_IDR) Time-out Interrupt Disable Mask */ +#define US_IDR_TIMEOUT(value) (US_IDR_TIMEOUT_Msk & ((value) << US_IDR_TIMEOUT_Pos)) +#define US_IDR_TXEMPTY_Pos _U_(9) /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_TXEMPTY_Msk (_U_(0x1) << US_IDR_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_TXEMPTY(value) (US_IDR_TXEMPTY_Msk & ((value) << US_IDR_TXEMPTY_Pos)) +#define US_IDR_ITER_Pos _U_(10) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Position */ +#define US_IDR_ITER_Msk (_U_(0x1) << US_IDR_ITER_Pos) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Mask */ +#define US_IDR_ITER(value) (US_IDR_ITER_Msk & ((value) << US_IDR_ITER_Pos)) +#define US_IDR_NACK_Pos _U_(13) /**< (US_IDR) Non Acknowledge Interrupt Disable Position */ +#define US_IDR_NACK_Msk (_U_(0x1) << US_IDR_NACK_Pos) /**< (US_IDR) Non Acknowledge Interrupt Disable Mask */ +#define US_IDR_NACK(value) (US_IDR_NACK_Msk & ((value) << US_IDR_NACK_Pos)) +#define US_IDR_RIIC_Pos _U_(16) /**< (US_IDR) Ring Indicator Input Change Disable Position */ +#define US_IDR_RIIC_Msk (_U_(0x1) << US_IDR_RIIC_Pos) /**< (US_IDR) Ring Indicator Input Change Disable Mask */ +#define US_IDR_RIIC(value) (US_IDR_RIIC_Msk & ((value) << US_IDR_RIIC_Pos)) +#define US_IDR_DSRIC_Pos _U_(17) /**< (US_IDR) Data Set Ready Input Change Disable Position */ +#define US_IDR_DSRIC_Msk (_U_(0x1) << US_IDR_DSRIC_Pos) /**< (US_IDR) Data Set Ready Input Change Disable Mask */ +#define US_IDR_DSRIC(value) (US_IDR_DSRIC_Msk & ((value) << US_IDR_DSRIC_Pos)) +#define US_IDR_DCDIC_Pos _U_(18) /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Position */ +#define US_IDR_DCDIC_Msk (_U_(0x1) << US_IDR_DCDIC_Pos) /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Mask */ +#define US_IDR_DCDIC(value) (US_IDR_DCDIC_Msk & ((value) << US_IDR_DCDIC_Pos)) +#define US_IDR_CTSIC_Pos _U_(19) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Position */ +#define US_IDR_CTSIC_Msk (_U_(0x1) << US_IDR_CTSIC_Pos) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Mask */ +#define US_IDR_CTSIC(value) (US_IDR_CTSIC_Msk & ((value) << US_IDR_CTSIC_Pos)) +#define US_IDR_MANE_Pos _U_(24) /**< (US_IDR) Manchester Error Interrupt Disable Position */ +#define US_IDR_MANE_Msk (_U_(0x1) << US_IDR_MANE_Pos) /**< (US_IDR) Manchester Error Interrupt Disable Mask */ +#define US_IDR_MANE(value) (US_IDR_MANE_Msk & ((value) << US_IDR_MANE_Pos)) +#define US_IDR_Msk _U_(0x010F27E7) /**< (US_IDR) Register Mask */ + + +/* -------- US_IMR : (USART Offset: 0x10) ( R/ 32) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY_Pos _U_(0) /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_RXRDY_Msk (_U_(0x1) << US_IMR_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_RXRDY(value) (US_IMR_RXRDY_Msk & ((value) << US_IMR_RXRDY_Pos)) +#define US_IMR_TXRDY_Pos _U_(1) /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_TXRDY_Msk (_U_(0x1) << US_IMR_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_TXRDY(value) (US_IMR_TXRDY_Msk & ((value) << US_IMR_TXRDY_Pos)) +#define US_IMR_RXBRK_Pos _U_(2) /**< (US_IMR) Receiver Break Interrupt Mask Position */ +#define US_IMR_RXBRK_Msk (_U_(0x1) << US_IMR_RXBRK_Pos) /**< (US_IMR) Receiver Break Interrupt Mask Mask */ +#define US_IMR_RXBRK(value) (US_IMR_RXBRK_Msk & ((value) << US_IMR_RXBRK_Pos)) +#define US_IMR_OVRE_Pos _U_(5) /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_OVRE_Msk (_U_(0x1) << US_IMR_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_OVRE(value) (US_IMR_OVRE_Msk & ((value) << US_IMR_OVRE_Pos)) +#define US_IMR_FRAME_Pos _U_(6) /**< (US_IMR) Framing Error Interrupt Mask Position */ +#define US_IMR_FRAME_Msk (_U_(0x1) << US_IMR_FRAME_Pos) /**< (US_IMR) Framing Error Interrupt Mask Mask */ +#define US_IMR_FRAME(value) (US_IMR_FRAME_Msk & ((value) << US_IMR_FRAME_Pos)) +#define US_IMR_PARE_Pos _U_(7) /**< (US_IMR) Parity Error Interrupt Mask Position */ +#define US_IMR_PARE_Msk (_U_(0x1) << US_IMR_PARE_Pos) /**< (US_IMR) Parity Error Interrupt Mask Mask */ +#define US_IMR_PARE(value) (US_IMR_PARE_Msk & ((value) << US_IMR_PARE_Pos)) +#define US_IMR_TIMEOUT_Pos _U_(8) /**< (US_IMR) Time-out Interrupt Mask Position */ +#define US_IMR_TIMEOUT_Msk (_U_(0x1) << US_IMR_TIMEOUT_Pos) /**< (US_IMR) Time-out Interrupt Mask Mask */ +#define US_IMR_TIMEOUT(value) (US_IMR_TIMEOUT_Msk & ((value) << US_IMR_TIMEOUT_Pos)) +#define US_IMR_TXEMPTY_Pos _U_(9) /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_TXEMPTY_Msk (_U_(0x1) << US_IMR_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_TXEMPTY(value) (US_IMR_TXEMPTY_Msk & ((value) << US_IMR_TXEMPTY_Pos)) +#define US_IMR_ITER_Pos _U_(10) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Position */ +#define US_IMR_ITER_Msk (_U_(0x1) << US_IMR_ITER_Pos) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Mask */ +#define US_IMR_ITER(value) (US_IMR_ITER_Msk & ((value) << US_IMR_ITER_Pos)) +#define US_IMR_NACK_Pos _U_(13) /**< (US_IMR) Non Acknowledge Interrupt Mask Position */ +#define US_IMR_NACK_Msk (_U_(0x1) << US_IMR_NACK_Pos) /**< (US_IMR) Non Acknowledge Interrupt Mask Mask */ +#define US_IMR_NACK(value) (US_IMR_NACK_Msk & ((value) << US_IMR_NACK_Pos)) +#define US_IMR_RIIC_Pos _U_(16) /**< (US_IMR) Ring Indicator Input Change Mask Position */ +#define US_IMR_RIIC_Msk (_U_(0x1) << US_IMR_RIIC_Pos) /**< (US_IMR) Ring Indicator Input Change Mask Mask */ +#define US_IMR_RIIC(value) (US_IMR_RIIC_Msk & ((value) << US_IMR_RIIC_Pos)) +#define US_IMR_DSRIC_Pos _U_(17) /**< (US_IMR) Data Set Ready Input Change Mask Position */ +#define US_IMR_DSRIC_Msk (_U_(0x1) << US_IMR_DSRIC_Pos) /**< (US_IMR) Data Set Ready Input Change Mask Mask */ +#define US_IMR_DSRIC(value) (US_IMR_DSRIC_Msk & ((value) << US_IMR_DSRIC_Pos)) +#define US_IMR_DCDIC_Pos _U_(18) /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Position */ +#define US_IMR_DCDIC_Msk (_U_(0x1) << US_IMR_DCDIC_Pos) /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Mask */ +#define US_IMR_DCDIC(value) (US_IMR_DCDIC_Msk & ((value) << US_IMR_DCDIC_Pos)) +#define US_IMR_CTSIC_Pos _U_(19) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Position */ +#define US_IMR_CTSIC_Msk (_U_(0x1) << US_IMR_CTSIC_Pos) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Mask */ +#define US_IMR_CTSIC(value) (US_IMR_CTSIC_Msk & ((value) << US_IMR_CTSIC_Pos)) +#define US_IMR_MANE_Pos _U_(24) /**< (US_IMR) Manchester Error Interrupt Mask Position */ +#define US_IMR_MANE_Msk (_U_(0x1) << US_IMR_MANE_Pos) /**< (US_IMR) Manchester Error Interrupt Mask Mask */ +#define US_IMR_MANE(value) (US_IMR_MANE_Msk & ((value) << US_IMR_MANE_Pos)) +#define US_IMR_Msk _U_(0x010F27E7) /**< (US_IMR) Register Mask */ + + +/* -------- US_CSR : (USART Offset: 0x14) ( R/ 32) Channel Status Register -------- */ +#define US_CSR_RXRDY_Pos _U_(0) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_RXRDY_Msk (_U_(0x1) << US_CSR_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_RXRDY(value) (US_CSR_RXRDY_Msk & ((value) << US_CSR_RXRDY_Pos)) +#define US_CSR_TXRDY_Pos _U_(1) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_TXRDY_Msk (_U_(0x1) << US_CSR_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_TXRDY(value) (US_CSR_TXRDY_Msk & ((value) << US_CSR_TXRDY_Pos)) +#define US_CSR_RXBRK_Pos _U_(2) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_RXBRK_Msk (_U_(0x1) << US_CSR_RXBRK_Pos) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_RXBRK(value) (US_CSR_RXBRK_Msk & ((value) << US_CSR_RXBRK_Pos)) +#define US_CSR_OVRE_Pos _U_(5) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_OVRE_Msk (_U_(0x1) << US_CSR_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_OVRE(value) (US_CSR_OVRE_Msk & ((value) << US_CSR_OVRE_Pos)) +#define US_CSR_FRAME_Pos _U_(6) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_FRAME_Msk (_U_(0x1) << US_CSR_FRAME_Pos) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_FRAME(value) (US_CSR_FRAME_Msk & ((value) << US_CSR_FRAME_Pos)) +#define US_CSR_PARE_Pos _U_(7) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_PARE_Msk (_U_(0x1) << US_CSR_PARE_Pos) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_PARE(value) (US_CSR_PARE_Msk & ((value) << US_CSR_PARE_Pos)) +#define US_CSR_TIMEOUT_Pos _U_(8) /**< (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) Position */ +#define US_CSR_TIMEOUT_Msk (_U_(0x1) << US_CSR_TIMEOUT_Pos) /**< (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) Mask */ +#define US_CSR_TIMEOUT(value) (US_CSR_TIMEOUT_Msk & ((value) << US_CSR_TIMEOUT_Pos)) +#define US_CSR_TXEMPTY_Pos _U_(9) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_TXEMPTY_Msk (_U_(0x1) << US_CSR_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_TXEMPTY(value) (US_CSR_TXEMPTY_Msk & ((value) << US_CSR_TXEMPTY_Pos)) +#define US_CSR_ITER_Pos _U_(10) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Position */ +#define US_CSR_ITER_Msk (_U_(0x1) << US_CSR_ITER_Pos) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Mask */ +#define US_CSR_ITER(value) (US_CSR_ITER_Msk & ((value) << US_CSR_ITER_Pos)) +#define US_CSR_NACK_Pos _U_(13) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Position */ +#define US_CSR_NACK_Msk (_U_(0x1) << US_CSR_NACK_Pos) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Mask */ +#define US_CSR_NACK(value) (US_CSR_NACK_Msk & ((value) << US_CSR_NACK_Pos)) +#define US_CSR_RIIC_Pos _U_(16) /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Position */ +#define US_CSR_RIIC_Msk (_U_(0x1) << US_CSR_RIIC_Pos) /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Mask */ +#define US_CSR_RIIC(value) (US_CSR_RIIC_Msk & ((value) << US_CSR_RIIC_Pos)) +#define US_CSR_DSRIC_Pos _U_(17) /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Position */ +#define US_CSR_DSRIC_Msk (_U_(0x1) << US_CSR_DSRIC_Pos) /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Mask */ +#define US_CSR_DSRIC(value) (US_CSR_DSRIC_Msk & ((value) << US_CSR_DSRIC_Pos)) +#define US_CSR_DCDIC_Pos _U_(18) /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Position */ +#define US_CSR_DCDIC_Msk (_U_(0x1) << US_CSR_DCDIC_Pos) /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Mask */ +#define US_CSR_DCDIC(value) (US_CSR_DCDIC_Msk & ((value) << US_CSR_DCDIC_Pos)) +#define US_CSR_CTSIC_Pos _U_(19) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Position */ +#define US_CSR_CTSIC_Msk (_U_(0x1) << US_CSR_CTSIC_Pos) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Mask */ +#define US_CSR_CTSIC(value) (US_CSR_CTSIC_Msk & ((value) << US_CSR_CTSIC_Pos)) +#define US_CSR_RI_Pos _U_(20) /**< (US_CSR) Image of RI Input Position */ +#define US_CSR_RI_Msk (_U_(0x1) << US_CSR_RI_Pos) /**< (US_CSR) Image of RI Input Mask */ +#define US_CSR_RI(value) (US_CSR_RI_Msk & ((value) << US_CSR_RI_Pos)) +#define US_CSR_DSR_Pos _U_(21) /**< (US_CSR) Image of DSR Input Position */ +#define US_CSR_DSR_Msk (_U_(0x1) << US_CSR_DSR_Pos) /**< (US_CSR) Image of DSR Input Mask */ +#define US_CSR_DSR(value) (US_CSR_DSR_Msk & ((value) << US_CSR_DSR_Pos)) +#define US_CSR_DCD_Pos _U_(22) /**< (US_CSR) Image of DCD Input Position */ +#define US_CSR_DCD_Msk (_U_(0x1) << US_CSR_DCD_Pos) /**< (US_CSR) Image of DCD Input Mask */ +#define US_CSR_DCD(value) (US_CSR_DCD_Msk & ((value) << US_CSR_DCD_Pos)) +#define US_CSR_CTS_Pos _U_(23) /**< (US_CSR) Image of CTS Input Position */ +#define US_CSR_CTS_Msk (_U_(0x1) << US_CSR_CTS_Pos) /**< (US_CSR) Image of CTS Input Mask */ +#define US_CSR_CTS(value) (US_CSR_CTS_Msk & ((value) << US_CSR_CTS_Pos)) +#define US_CSR_MANERR_Pos _U_(24) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Position */ +#define US_CSR_MANERR_Msk (_U_(0x1) << US_CSR_MANERR_Pos) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Mask */ +#define US_CSR_MANERR(value) (US_CSR_MANERR_Msk & ((value) << US_CSR_MANERR_Pos)) +#define US_CSR_Msk _U_(0x01FF27E7) /**< (US_CSR) Register Mask */ + + +/* -------- US_RHR : (USART Offset: 0x18) ( R/ 32) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos _U_(0) /**< (US_RHR) Received Character Position */ +#define US_RHR_RXCHR_Msk (_U_(0x1FF) << US_RHR_RXCHR_Pos) /**< (US_RHR) Received Character Mask */ +#define US_RHR_RXCHR(value) (US_RHR_RXCHR_Msk & ((value) << US_RHR_RXCHR_Pos)) +#define US_RHR_RXSYNH_Pos _U_(15) /**< (US_RHR) Received Sync Position */ +#define US_RHR_RXSYNH_Msk (_U_(0x1) << US_RHR_RXSYNH_Pos) /**< (US_RHR) Received Sync Mask */ +#define US_RHR_RXSYNH(value) (US_RHR_RXSYNH_Msk & ((value) << US_RHR_RXSYNH_Pos)) +#define US_RHR_Msk _U_(0x000081FF) /**< (US_RHR) Register Mask */ + + +/* -------- US_THR : (USART Offset: 0x1C) ( /W 32) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos _U_(0) /**< (US_THR) Character to be Transmitted Position */ +#define US_THR_TXCHR_Msk (_U_(0x1FF) << US_THR_TXCHR_Pos) /**< (US_THR) Character to be Transmitted Mask */ +#define US_THR_TXCHR(value) (US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)) +#define US_THR_TXSYNH_Pos _U_(15) /**< (US_THR) Sync Field to be Transmitted Position */ +#define US_THR_TXSYNH_Msk (_U_(0x1) << US_THR_TXSYNH_Pos) /**< (US_THR) Sync Field to be Transmitted Mask */ +#define US_THR_TXSYNH(value) (US_THR_TXSYNH_Msk & ((value) << US_THR_TXSYNH_Pos)) +#define US_THR_Msk _U_(0x000081FF) /**< (US_THR) Register Mask */ + + +/* -------- US_BRGR : (USART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos _U_(0) /**< (US_BRGR) Clock Divider Position */ +#define US_BRGR_CD_Msk (_U_(0xFFFF) << US_BRGR_CD_Pos) /**< (US_BRGR) Clock Divider Mask */ +#define US_BRGR_CD(value) (US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)) +#define US_BRGR_FP_Pos _U_(16) /**< (US_BRGR) Fractional Part Position */ +#define US_BRGR_FP_Msk (_U_(0x7) << US_BRGR_FP_Pos) /**< (US_BRGR) Fractional Part Mask */ +#define US_BRGR_FP(value) (US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)) +#define US_BRGR_Msk _U_(0x0007FFFF) /**< (US_BRGR) Register Mask */ + + +/* -------- US_RTOR : (USART Offset: 0x24) (R/W 32) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos _U_(0) /**< (US_RTOR) Time-out Value Position */ +#define US_RTOR_TO_Msk (_U_(0x1FFFF) << US_RTOR_TO_Pos) /**< (US_RTOR) Time-out Value Mask */ +#define US_RTOR_TO(value) (US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)) +#define US_RTOR_Msk _U_(0x0001FFFF) /**< (US_RTOR) Register Mask */ + + +/* -------- US_TTGR : (USART Offset: 0x28) (R/W 32) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos _U_(0) /**< (US_TTGR) Timeguard Value Position */ +#define US_TTGR_TG_Msk (_U_(0xFF) << US_TTGR_TG_Pos) /**< (US_TTGR) Timeguard Value Mask */ +#define US_TTGR_TG(value) (US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)) +#define US_TTGR_Msk _U_(0x000000FF) /**< (US_TTGR) Register Mask */ + + +/* -------- US_FIDI : (USART Offset: 0x40) (R/W 32) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos _U_(0) /**< (US_FIDI) FI Over DI Ratio Value Position */ +#define US_FIDI_FI_DI_RATIO_Msk (_U_(0xFFFF) << US_FIDI_FI_DI_RATIO_Pos) /**< (US_FIDI) FI Over DI Ratio Value Mask */ +#define US_FIDI_FI_DI_RATIO(value) (US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)) +#define US_FIDI_Msk _U_(0x0000FFFF) /**< (US_FIDI) Register Mask */ + + +/* -------- US_NER : (USART Offset: 0x44) ( R/ 32) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos _U_(0) /**< (US_NER) Number of Errors Position */ +#define US_NER_NB_ERRORS_Msk (_U_(0xFF) << US_NER_NB_ERRORS_Pos) /**< (US_NER) Number of Errors Mask */ +#define US_NER_NB_ERRORS(value) (US_NER_NB_ERRORS_Msk & ((value) << US_NER_NB_ERRORS_Pos)) +#define US_NER_Msk _U_(0x000000FF) /**< (US_NER) Register Mask */ + + +/* -------- US_IF : (USART Offset: 0x4C) (R/W 32) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos _U_(0) /**< (US_IF) IrDA Filter Position */ +#define US_IF_IRDA_FILTER_Msk (_U_(0xFF) << US_IF_IRDA_FILTER_Pos) /**< (US_IF) IrDA Filter Mask */ +#define US_IF_IRDA_FILTER(value) (US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)) +#define US_IF_Msk _U_(0x000000FF) /**< (US_IF) Register Mask */ + + +/* -------- US_MAN : (USART Offset: 0x50) (R/W 32) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos _U_(0) /**< (US_MAN) Transmitter Preamble Length Position */ +#define US_MAN_TX_PL_Msk (_U_(0xF) << US_MAN_TX_PL_Pos) /**< (US_MAN) Transmitter Preamble Length Mask */ +#define US_MAN_TX_PL(value) (US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)) +#define US_MAN_TX_PP_Pos _U_(8) /**< (US_MAN) Transmitter Preamble Pattern Position */ +#define US_MAN_TX_PP_Msk (_U_(0x3) << US_MAN_TX_PP_Pos) /**< (US_MAN) Transmitter Preamble Pattern Mask */ +#define US_MAN_TX_PP(value) (US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)) +#define US_MAN_TX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_PP_ALL_ONE (US_MAN_TX_PP_ALL_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_TX_PP_ALL_ZERO (US_MAN_TX_PP_ALL_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_TX_PP_ZERO_ONE (US_MAN_TX_PP_ZERO_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_TX_PP_ONE_ZERO (US_MAN_TX_PP_ONE_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_TX_MPOL_Pos _U_(12) /**< (US_MAN) Transmitter Manchester Polarity Position */ +#define US_MAN_TX_MPOL_Msk (_U_(0x1) << US_MAN_TX_MPOL_Pos) /**< (US_MAN) Transmitter Manchester Polarity Mask */ +#define US_MAN_TX_MPOL(value) (US_MAN_TX_MPOL_Msk & ((value) << US_MAN_TX_MPOL_Pos)) +#define US_MAN_RX_PL_Pos _U_(16) /**< (US_MAN) Receiver Preamble Length Position */ +#define US_MAN_RX_PL_Msk (_U_(0xF) << US_MAN_RX_PL_Pos) /**< (US_MAN) Receiver Preamble Length Mask */ +#define US_MAN_RX_PL(value) (US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)) +#define US_MAN_RX_PP_Pos _U_(24) /**< (US_MAN) Receiver Preamble Pattern detected Position */ +#define US_MAN_RX_PP_Msk (_U_(0x3) << US_MAN_RX_PP_Pos) /**< (US_MAN) Receiver Preamble Pattern detected Mask */ +#define US_MAN_RX_PP(value) (US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)) +#define US_MAN_RX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_PP_ALL_ONE (US_MAN_RX_PP_ALL_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_RX_PP_ALL_ZERO (US_MAN_RX_PP_ALL_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_RX_PP_ZERO_ONE (US_MAN_RX_PP_ZERO_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_RX_PP_ONE_ZERO (US_MAN_RX_PP_ONE_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_RX_MPOL_Pos _U_(28) /**< (US_MAN) Receiver Manchester Polarity Position */ +#define US_MAN_RX_MPOL_Msk (_U_(0x1) << US_MAN_RX_MPOL_Pos) /**< (US_MAN) Receiver Manchester Polarity Mask */ +#define US_MAN_RX_MPOL(value) (US_MAN_RX_MPOL_Msk & ((value) << US_MAN_RX_MPOL_Pos)) +#define US_MAN_ONE_Pos _U_(29) /**< (US_MAN) Must Be Set to 1 Position */ +#define US_MAN_ONE_Msk (_U_(0x1) << US_MAN_ONE_Pos) /**< (US_MAN) Must Be Set to 1 Mask */ +#define US_MAN_ONE(value) (US_MAN_ONE_Msk & ((value) << US_MAN_ONE_Pos)) +#define US_MAN_DRIFT_Pos _U_(30) /**< (US_MAN) Drift Compensation Position */ +#define US_MAN_DRIFT_Msk (_U_(0x1) << US_MAN_DRIFT_Pos) /**< (US_MAN) Drift Compensation Mask */ +#define US_MAN_DRIFT(value) (US_MAN_DRIFT_Msk & ((value) << US_MAN_DRIFT_Pos)) +#define US_MAN_RXIDLEV_Pos _U_(31) /**< (US_MAN) Position */ +#define US_MAN_RXIDLEV_Msk (_U_(0x1) << US_MAN_RXIDLEV_Pos) /**< (US_MAN) Mask */ +#define US_MAN_RXIDLEV(value) (US_MAN_RXIDLEV_Msk & ((value) << US_MAN_RXIDLEV_Pos)) +#define US_MAN_Msk _U_(0xF30F130F) /**< (US_MAN) Register Mask */ + + +/* -------- US_LINMR : (USART Offset: 0x54) (R/W 32) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos _U_(0) /**< (US_LINMR) LIN Node Action Position */ +#define US_LINMR_NACT_Msk (_U_(0x3) << US_LINMR_NACT_Pos) /**< (US_LINMR) LIN Node Action Mask */ +#define US_LINMR_NACT(value) (US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)) +#define US_LINMR_NACT_PUBLISH_Val _U_(0x0) /**< (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE_Val _U_(0x1) /**< (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE_Val _U_(0x2) /**< (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_NACT_PUBLISH (US_LINMR_NACT_PUBLISH_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART transmits the response. Position */ +#define US_LINMR_NACT_SUBSCRIBE (US_LINMR_NACT_SUBSCRIBE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART receives the response. Position */ +#define US_LINMR_NACT_IGNORE (US_LINMR_NACT_IGNORE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART does not transmit and does not receive the response. Position */ +#define US_LINMR_PARDIS_Pos _U_(2) /**< (US_LINMR) Parity Disable Position */ +#define US_LINMR_PARDIS_Msk (_U_(0x1) << US_LINMR_PARDIS_Pos) /**< (US_LINMR) Parity Disable Mask */ +#define US_LINMR_PARDIS(value) (US_LINMR_PARDIS_Msk & ((value) << US_LINMR_PARDIS_Pos)) +#define US_LINMR_CHKDIS_Pos _U_(3) /**< (US_LINMR) Checksum Disable Position */ +#define US_LINMR_CHKDIS_Msk (_U_(0x1) << US_LINMR_CHKDIS_Pos) /**< (US_LINMR) Checksum Disable Mask */ +#define US_LINMR_CHKDIS(value) (US_LINMR_CHKDIS_Msk & ((value) << US_LINMR_CHKDIS_Pos)) +#define US_LINMR_CHKTYP_Pos _U_(4) /**< (US_LINMR) Checksum Type Position */ +#define US_LINMR_CHKTYP_Msk (_U_(0x1) << US_LINMR_CHKTYP_Pos) /**< (US_LINMR) Checksum Type Mask */ +#define US_LINMR_CHKTYP(value) (US_LINMR_CHKTYP_Msk & ((value) << US_LINMR_CHKTYP_Pos)) +#define US_LINMR_DLM_Pos _U_(5) /**< (US_LINMR) Data Length Mode Position */ +#define US_LINMR_DLM_Msk (_U_(0x1) << US_LINMR_DLM_Pos) /**< (US_LINMR) Data Length Mode Mask */ +#define US_LINMR_DLM(value) (US_LINMR_DLM_Msk & ((value) << US_LINMR_DLM_Pos)) +#define US_LINMR_FSDIS_Pos _U_(6) /**< (US_LINMR) Frame Slot Mode Disable Position */ +#define US_LINMR_FSDIS_Msk (_U_(0x1) << US_LINMR_FSDIS_Pos) /**< (US_LINMR) Frame Slot Mode Disable Mask */ +#define US_LINMR_FSDIS(value) (US_LINMR_FSDIS_Msk & ((value) << US_LINMR_FSDIS_Pos)) +#define US_LINMR_WKUPTYP_Pos _U_(7) /**< (US_LINMR) Wakeup Signal Type Position */ +#define US_LINMR_WKUPTYP_Msk (_U_(0x1) << US_LINMR_WKUPTYP_Pos) /**< (US_LINMR) Wakeup Signal Type Mask */ +#define US_LINMR_WKUPTYP(value) (US_LINMR_WKUPTYP_Msk & ((value) << US_LINMR_WKUPTYP_Pos)) +#define US_LINMR_DLC_Pos _U_(8) /**< (US_LINMR) Data Length Control Position */ +#define US_LINMR_DLC_Msk (_U_(0xFF) << US_LINMR_DLC_Pos) /**< (US_LINMR) Data Length Control Mask */ +#define US_LINMR_DLC(value) (US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)) +#define US_LINMR_PDCM_Pos _U_(16) /**< (US_LINMR) DMAC Mode Position */ +#define US_LINMR_PDCM_Msk (_U_(0x1) << US_LINMR_PDCM_Pos) /**< (US_LINMR) DMAC Mode Mask */ +#define US_LINMR_PDCM(value) (US_LINMR_PDCM_Msk & ((value) << US_LINMR_PDCM_Pos)) +#define US_LINMR_SYNCDIS_Pos _U_(17) /**< (US_LINMR) Synchronization Disable Position */ +#define US_LINMR_SYNCDIS_Msk (_U_(0x1) << US_LINMR_SYNCDIS_Pos) /**< (US_LINMR) Synchronization Disable Mask */ +#define US_LINMR_SYNCDIS(value) (US_LINMR_SYNCDIS_Msk & ((value) << US_LINMR_SYNCDIS_Pos)) +#define US_LINMR_Msk _U_(0x0003FFFF) /**< (US_LINMR) Register Mask */ + + +/* -------- US_LINIR : (USART Offset: 0x58) (R/W 32) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos _U_(0) /**< (US_LINIR) Identifier Character Position */ +#define US_LINIR_IDCHR_Msk (_U_(0xFF) << US_LINIR_IDCHR_Pos) /**< (US_LINIR) Identifier Character Mask */ +#define US_LINIR_IDCHR(value) (US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)) +#define US_LINIR_Msk _U_(0x000000FF) /**< (US_LINIR) Register Mask */ + + +/* -------- US_LINBRR : (USART Offset: 0x5C) ( R/ 32) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos _U_(0) /**< (US_LINBRR) Clock Divider after Synchronization Position */ +#define US_LINBRR_LINCD_Msk (_U_(0xFFFF) << US_LINBRR_LINCD_Pos) /**< (US_LINBRR) Clock Divider after Synchronization Mask */ +#define US_LINBRR_LINCD(value) (US_LINBRR_LINCD_Msk & ((value) << US_LINBRR_LINCD_Pos)) +#define US_LINBRR_LINFP_Pos _U_(16) /**< (US_LINBRR) Fractional Part after Synchronization Position */ +#define US_LINBRR_LINFP_Msk (_U_(0x7) << US_LINBRR_LINFP_Pos) /**< (US_LINBRR) Fractional Part after Synchronization Mask */ +#define US_LINBRR_LINFP(value) (US_LINBRR_LINFP_Msk & ((value) << US_LINBRR_LINFP_Pos)) +#define US_LINBRR_Msk _U_(0x0007FFFF) /**< (US_LINBRR) Register Mask */ + + +/* -------- US_LONMR : (USART Offset: 0x60) (R/W 32) LON Mode Register -------- */ +#define US_LONMR_COMMT_Pos _U_(0) /**< (US_LONMR) LON comm_type Parameter Value Position */ +#define US_LONMR_COMMT_Msk (_U_(0x1) << US_LONMR_COMMT_Pos) /**< (US_LONMR) LON comm_type Parameter Value Mask */ +#define US_LONMR_COMMT(value) (US_LONMR_COMMT_Msk & ((value) << US_LONMR_COMMT_Pos)) +#define US_LONMR_COLDET_Pos _U_(1) /**< (US_LONMR) LON Collision Detection Feature Position */ +#define US_LONMR_COLDET_Msk (_U_(0x1) << US_LONMR_COLDET_Pos) /**< (US_LONMR) LON Collision Detection Feature Mask */ +#define US_LONMR_COLDET(value) (US_LONMR_COLDET_Msk & ((value) << US_LONMR_COLDET_Pos)) +#define US_LONMR_TCOL_Pos _U_(2) /**< (US_LONMR) Terminate Frame upon Collision Notification Position */ +#define US_LONMR_TCOL_Msk (_U_(0x1) << US_LONMR_TCOL_Pos) /**< (US_LONMR) Terminate Frame upon Collision Notification Mask */ +#define US_LONMR_TCOL(value) (US_LONMR_TCOL_Msk & ((value) << US_LONMR_TCOL_Pos)) +#define US_LONMR_CDTAIL_Pos _U_(3) /**< (US_LONMR) LON Collision Detection on Frame Tail Position */ +#define US_LONMR_CDTAIL_Msk (_U_(0x1) << US_LONMR_CDTAIL_Pos) /**< (US_LONMR) LON Collision Detection on Frame Tail Mask */ +#define US_LONMR_CDTAIL(value) (US_LONMR_CDTAIL_Msk & ((value) << US_LONMR_CDTAIL_Pos)) +#define US_LONMR_DMAM_Pos _U_(4) /**< (US_LONMR) LON DMA Mode Position */ +#define US_LONMR_DMAM_Msk (_U_(0x1) << US_LONMR_DMAM_Pos) /**< (US_LONMR) LON DMA Mode Mask */ +#define US_LONMR_DMAM(value) (US_LONMR_DMAM_Msk & ((value) << US_LONMR_DMAM_Pos)) +#define US_LONMR_LCDS_Pos _U_(5) /**< (US_LONMR) LON Collision Detection Source Position */ +#define US_LONMR_LCDS_Msk (_U_(0x1) << US_LONMR_LCDS_Pos) /**< (US_LONMR) LON Collision Detection Source Mask */ +#define US_LONMR_LCDS(value) (US_LONMR_LCDS_Msk & ((value) << US_LONMR_LCDS_Pos)) +#define US_LONMR_EOFS_Pos _U_(16) /**< (US_LONMR) End of Frame Condition Size Position */ +#define US_LONMR_EOFS_Msk (_U_(0xFF) << US_LONMR_EOFS_Pos) /**< (US_LONMR) End of Frame Condition Size Mask */ +#define US_LONMR_EOFS(value) (US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)) +#define US_LONMR_Msk _U_(0x00FF003F) /**< (US_LONMR) Register Mask */ + + +/* -------- US_LONPR : (USART Offset: 0x64) (R/W 32) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos _U_(0) /**< (US_LONPR) LON Preamble Length Position */ +#define US_LONPR_LONPL_Msk (_U_(0x3FFF) << US_LONPR_LONPL_Pos) /**< (US_LONPR) LON Preamble Length Mask */ +#define US_LONPR_LONPL(value) (US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)) +#define US_LONPR_Msk _U_(0x00003FFF) /**< (US_LONPR) Register Mask */ + + +/* -------- US_LONDL : (USART Offset: 0x68) (R/W 32) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos _U_(0) /**< (US_LONDL) LON Data Length Position */ +#define US_LONDL_LONDL_Msk (_U_(0xFF) << US_LONDL_LONDL_Pos) /**< (US_LONDL) LON Data Length Mask */ +#define US_LONDL_LONDL(value) (US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)) +#define US_LONDL_Msk _U_(0x000000FF) /**< (US_LONDL) Register Mask */ + + +/* -------- US_LONL2HDR : (USART Offset: 0x6C) (R/W 32) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos _U_(0) /**< (US_LONL2HDR) LON Backlog Increment Position */ +#define US_LONL2HDR_BLI_Msk (_U_(0x3F) << US_LONL2HDR_BLI_Pos) /**< (US_LONL2HDR) LON Backlog Increment Mask */ +#define US_LONL2HDR_BLI(value) (US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)) +#define US_LONL2HDR_ALTP_Pos _U_(6) /**< (US_LONL2HDR) LON Alternate Path Bit Position */ +#define US_LONL2HDR_ALTP_Msk (_U_(0x1) << US_LONL2HDR_ALTP_Pos) /**< (US_LONL2HDR) LON Alternate Path Bit Mask */ +#define US_LONL2HDR_ALTP(value) (US_LONL2HDR_ALTP_Msk & ((value) << US_LONL2HDR_ALTP_Pos)) +#define US_LONL2HDR_PB_Pos _U_(7) /**< (US_LONL2HDR) LON Priority Bit Position */ +#define US_LONL2HDR_PB_Msk (_U_(0x1) << US_LONL2HDR_PB_Pos) /**< (US_LONL2HDR) LON Priority Bit Mask */ +#define US_LONL2HDR_PB(value) (US_LONL2HDR_PB_Msk & ((value) << US_LONL2HDR_PB_Pos)) +#define US_LONL2HDR_Msk _U_(0x000000FF) /**< (US_LONL2HDR) Register Mask */ + + +/* -------- US_LONBL : (USART Offset: 0x70) ( R/ 32) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos _U_(0) /**< (US_LONBL) LON Node Backlog Value Position */ +#define US_LONBL_LONBL_Msk (_U_(0x3F) << US_LONBL_LONBL_Pos) /**< (US_LONBL) LON Node Backlog Value Mask */ +#define US_LONBL_LONBL(value) (US_LONBL_LONBL_Msk & ((value) << US_LONBL_LONBL_Pos)) +#define US_LONBL_Msk _U_(0x0000003F) /**< (US_LONBL) Register Mask */ + + +/* -------- US_LONB1TX : (USART Offset: 0x74) (R/W 32) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos _U_(0) /**< (US_LONB1TX) LON Beta1 Length after Transmission Position */ +#define US_LONB1TX_BETA1TX_Msk (_U_(0xFFFFFF) << US_LONB1TX_BETA1TX_Pos) /**< (US_LONB1TX) LON Beta1 Length after Transmission Mask */ +#define US_LONB1TX_BETA1TX(value) (US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)) +#define US_LONB1TX_Msk _U_(0x00FFFFFF) /**< (US_LONB1TX) Register Mask */ + + +/* -------- US_LONB1RX : (USART Offset: 0x78) (R/W 32) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos _U_(0) /**< (US_LONB1RX) LON Beta1 Length after Reception Position */ +#define US_LONB1RX_BETA1RX_Msk (_U_(0xFFFFFF) << US_LONB1RX_BETA1RX_Pos) /**< (US_LONB1RX) LON Beta1 Length after Reception Mask */ +#define US_LONB1RX_BETA1RX(value) (US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)) +#define US_LONB1RX_Msk _U_(0x00FFFFFF) /**< (US_LONB1RX) Register Mask */ + + +/* -------- US_LONPRIO : (USART Offset: 0x7C) (R/W 32) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos _U_(0) /**< (US_LONPRIO) LON Priority Slot Number Position */ +#define US_LONPRIO_PSNB_Msk (_U_(0x7F) << US_LONPRIO_PSNB_Pos) /**< (US_LONPRIO) LON Priority Slot Number Mask */ +#define US_LONPRIO_PSNB(value) (US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)) +#define US_LONPRIO_NPS_Pos _U_(8) /**< (US_LONPRIO) LON Node Priority Slot Position */ +#define US_LONPRIO_NPS_Msk (_U_(0x7F) << US_LONPRIO_NPS_Pos) /**< (US_LONPRIO) LON Node Priority Slot Mask */ +#define US_LONPRIO_NPS(value) (US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)) +#define US_LONPRIO_Msk _U_(0x00007F7F) /**< (US_LONPRIO) Register Mask */ + + +/* -------- US_IDTTX : (USART Offset: 0x80) (R/W 32) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos _U_(0) /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Position */ +#define US_IDTTX_IDTTX_Msk (_U_(0xFFFFFF) << US_IDTTX_IDTTX_Pos) /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Mask */ +#define US_IDTTX_IDTTX(value) (US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)) +#define US_IDTTX_Msk _U_(0x00FFFFFF) /**< (US_IDTTX) Register Mask */ + + +/* -------- US_IDTRX : (USART Offset: 0x84) (R/W 32) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos _U_(0) /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Position */ +#define US_IDTRX_IDTRX_Msk (_U_(0xFFFFFF) << US_IDTRX_IDTRX_Pos) /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Mask */ +#define US_IDTRX_IDTRX(value) (US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)) +#define US_IDTRX_Msk _U_(0x00FFFFFF) /**< (US_IDTRX) Register Mask */ + + +/* -------- US_ICDIFF : (USART Offset: 0x88) (R/W 32) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos _U_(0) /**< (US_ICDIFF) IC Differentiator Number Position */ +#define US_ICDIFF_ICDIFF_Msk (_U_(0xF) << US_ICDIFF_ICDIFF_Pos) /**< (US_ICDIFF) IC Differentiator Number Mask */ +#define US_ICDIFF_ICDIFF(value) (US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)) +#define US_ICDIFF_Msk _U_(0x0000000F) /**< (US_ICDIFF) Register Mask */ + + +/* -------- US_WPMR : (USART Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN_Pos _U_(0) /**< (US_WPMR) Write Protection Enable Position */ +#define US_WPMR_WPEN_Msk (_U_(0x1) << US_WPMR_WPEN_Pos) /**< (US_WPMR) Write Protection Enable Mask */ +#define US_WPMR_WPEN(value) (US_WPMR_WPEN_Msk & ((value) << US_WPMR_WPEN_Pos)) +#define US_WPMR_WPKEY_Pos _U_(8) /**< (US_WPMR) Write Protection Key Position */ +#define US_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Write Protection Key Mask */ +#define US_WPMR_WPKEY(value) (US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)) +#define US_WPMR_WPKEY_PASSWD_Val _U_(0x555341) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define US_WPMR_WPKEY_PASSWD (US_WPMR_WPKEY_PASSWD_Val << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define US_WPMR_Msk _U_(0xFFFFFF01) /**< (US_WPMR) Register Mask */ + + +/* -------- US_WPSR : (USART Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define US_WPSR_WPVS_Pos _U_(0) /**< (US_WPSR) Write Protection Violation Status Position */ +#define US_WPSR_WPVS_Msk (_U_(0x1) << US_WPSR_WPVS_Pos) /**< (US_WPSR) Write Protection Violation Status Mask */ +#define US_WPSR_WPVS(value) (US_WPSR_WPVS_Msk & ((value) << US_WPSR_WPVS_Pos)) +#define US_WPSR_WPVSRC_Pos _U_(8) /**< (US_WPSR) Write Protection Violation Source Position */ +#define US_WPSR_WPVSRC_Msk (_U_(0xFFFF) << US_WPSR_WPVSRC_Pos) /**< (US_WPSR) Write Protection Violation Source Mask */ +#define US_WPSR_WPVSRC(value) (US_WPSR_WPVSRC_Msk & ((value) << US_WPSR_WPVSRC_Pos)) +#define US_WPSR_Msk _U_(0x00FFFF01) /**< (US_WPSR) Register Mask */ + + +/** \brief USART register offsets definitions */ +#define US_CR_REG_OFST (0x00) /**< (US_CR) Control Register Offset */ +#define US_MR_REG_OFST (0x04) /**< (US_MR) Mode Register Offset */ +#define US_IER_REG_OFST (0x08) /**< (US_IER) Interrupt Enable Register Offset */ +#define US_IDR_REG_OFST (0x0C) /**< (US_IDR) Interrupt Disable Register Offset */ +#define US_IMR_REG_OFST (0x10) /**< (US_IMR) Interrupt Mask Register Offset */ +#define US_CSR_REG_OFST (0x14) /**< (US_CSR) Channel Status Register Offset */ +#define US_RHR_REG_OFST (0x18) /**< (US_RHR) Receive Holding Register Offset */ +#define US_THR_REG_OFST (0x1C) /**< (US_THR) Transmit Holding Register Offset */ +#define US_BRGR_REG_OFST (0x20) /**< (US_BRGR) Baud Rate Generator Register Offset */ +#define US_RTOR_REG_OFST (0x24) /**< (US_RTOR) Receiver Time-out Register Offset */ +#define US_TTGR_REG_OFST (0x28) /**< (US_TTGR) Transmitter Timeguard Register Offset */ +#define US_FIDI_REG_OFST (0x40) /**< (US_FIDI) FI DI Ratio Register Offset */ +#define US_NER_REG_OFST (0x44) /**< (US_NER) Number of Errors Register Offset */ +#define US_IF_REG_OFST (0x4C) /**< (US_IF) IrDA Filter Register Offset */ +#define US_MAN_REG_OFST (0x50) /**< (US_MAN) Manchester Configuration Register Offset */ +#define US_LINMR_REG_OFST (0x54) /**< (US_LINMR) LIN Mode Register Offset */ +#define US_LINIR_REG_OFST (0x58) /**< (US_LINIR) LIN Identifier Register Offset */ +#define US_LINBRR_REG_OFST (0x5C) /**< (US_LINBRR) LIN Baud Rate Register Offset */ +#define US_LONMR_REG_OFST (0x60) /**< (US_LONMR) LON Mode Register Offset */ +#define US_LONPR_REG_OFST (0x64) /**< (US_LONPR) LON Preamble Register Offset */ +#define US_LONDL_REG_OFST (0x68) /**< (US_LONDL) LON Data Length Register Offset */ +#define US_LONL2HDR_REG_OFST (0x6C) /**< (US_LONL2HDR) LON L2HDR Register Offset */ +#define US_LONBL_REG_OFST (0x70) /**< (US_LONBL) LON Backlog Register Offset */ +#define US_LONB1TX_REG_OFST (0x74) /**< (US_LONB1TX) LON Beta1 Tx Register Offset */ +#define US_LONB1RX_REG_OFST (0x78) /**< (US_LONB1RX) LON Beta1 Rx Register Offset */ +#define US_LONPRIO_REG_OFST (0x7C) /**< (US_LONPRIO) LON Priority Register Offset */ +#define US_IDTTX_REG_OFST (0x80) /**< (US_IDTTX) LON IDT Tx Register Offset */ +#define US_IDTRX_REG_OFST (0x84) /**< (US_IDTRX) LON IDT Rx Register Offset */ +#define US_ICDIFF_REG_OFST (0x88) /**< (US_ICDIFF) IC DIFF Register Offset */ +#define US_WPMR_REG_OFST (0xE4) /**< (US_WPMR) Write Protection Mode Register Offset */ +#define US_WPSR_REG_OFST (0xE8) /**< (US_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief USART register API structure */ +typedef struct +{ + __O uint32_t US_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t US_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O uint32_t US_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< Offset: 0x14 (R/ 32) Channel Status Register */ + __I uint32_t US_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O uint32_t US_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< Offset: 0x24 (R/W 32) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< Offset: 0x28 (R/W 32) Transmitter Timeguard Register */ + __I uint8_t Reserved1[0x14]; + __IO uint32_t US_FIDI; /**< Offset: 0x40 (R/W 32) FI DI Ratio Register */ + __I uint32_t US_NER; /**< Offset: 0x44 (R/ 32) Number of Errors Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t US_IF; /**< Offset: 0x4C (R/W 32) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< Offset: 0x50 (R/W 32) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< Offset: 0x54 (R/W 32) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< Offset: 0x58 (R/W 32) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< Offset: 0x5C (R/ 32) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< Offset: 0x60 (R/W 32) LON Mode Register */ + __IO uint32_t US_LONPR; /**< Offset: 0x64 (R/W 32) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< Offset: 0x68 (R/W 32) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< Offset: 0x6C (R/W 32) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< Offset: 0x70 (R/ 32) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< Offset: 0x74 (R/W 32) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< Offset: 0x78 (R/W 32) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< Offset: 0x7C (R/W 32) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< Offset: 0x80 (R/W 32) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< Offset: 0x84 (R/W 32) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< Offset: 0x88 (R/W 32) IC DIFF Register */ + __I uint8_t Reserved3[0x58]; + __IO uint32_t US_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} usart_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_USART_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/usbhs.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/usbhs.h new file mode 100644 index 00000000..b146fe21 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/usbhs.h @@ -0,0 +1,2163 @@ +/** + * \brief Component description for USBHS + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_USBHS_COMPONENT_H_ +#define _SAME70_USBHS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USBHS */ +/* ************************************************************************** */ + +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register (n = 1) -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos _U_(0) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) (USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMANXTDSC) Register Mask */ + + +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register (n = 1) -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos _U_(0) /**< (USBHS_DEVDMAADDRESS) Buffer Address Position */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_DEVDMAADDRESS) Buffer Address Mask */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) (USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMAADDRESS) Register Mask */ + + +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register (n = 1) -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB_Pos _U_(0) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Position */ +#define USBHS_DEVDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Mask */ +#define USBHS_DEVDMACONTROL_CHANN_ENB(value) (USBHS_DEVDMACONTROL_CHANN_ENB_Msk & ((value) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos)) +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Pos _U_(1) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC(value) (USBHS_DEVDMACONTROL_LDNXT_DSC_Msk & ((value) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos)) +#define USBHS_DEVDMACONTROL_END_TR_EN_Pos _U_(2) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_DEVDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_DEVDMACONTROL_END_TR_EN(value) (USBHS_DEVDMACONTROL_END_TR_EN_Msk & ((value) << USBHS_DEVDMACONTROL_END_TR_EN_Pos)) +#define USBHS_DEVDMACONTROL_END_B_EN_Pos _U_(3) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_DEVDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_B_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_DEVDMACONTROL_END_B_EN(value) (USBHS_DEVDMACONTROL_END_B_EN_Msk & ((value) << USBHS_DEVDMACONTROL_END_B_EN_Pos)) +#define USBHS_DEVDMACONTROL_END_TR_IT_Pos _U_(4) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_IT_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_TR_IT(value) (USBHS_DEVDMACONTROL_END_TR_IT_Msk & ((value) << USBHS_DEVDMACONTROL_END_TR_IT_Pos)) +#define USBHS_DEVDMACONTROL_END_BUFFIT_Pos _U_(5) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_BUFFIT(value) (USBHS_DEVDMACONTROL_END_BUFFIT_Msk & ((value) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos)) +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Pos _U_(6) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT(value) (USBHS_DEVDMACONTROL_DESC_LD_IT_Msk & ((value) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos)) +#define USBHS_DEVDMACONTROL_BURST_LCK_Pos _U_(7) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Position */ +#define USBHS_DEVDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_BURST_LCK_Pos) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_DEVDMACONTROL_BURST_LCK(value) (USBHS_DEVDMACONTROL_BURST_LCK_Msk & ((value) << USBHS_DEVDMACONTROL_BURST_LCK_Pos)) +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos _U_(16) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) (USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_DEVDMACONTROL) Register Mask */ + + +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: 0x0C) (R/W 32) Device DMA Channel Status Register (n = 1) -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB_Pos _U_(0) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ENB(value) (USBHS_DEVDMASTATUS_CHANN_ENB_Msk & ((value) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos)) +#define USBHS_DEVDMASTATUS_CHANN_ACT_Pos _U_(1) /**< (USBHS_DEVDMASTATUS) Channel Active Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_DEVDMASTATUS) Channel Active Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ACT(value) (USBHS_DEVDMASTATUS_CHANN_ACT_Msk & ((value) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos)) +#define USBHS_DEVDMASTATUS_END_TR_ST_Pos _U_(4) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_DEVDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_TR_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_DEVDMASTATUS_END_TR_ST(value) (USBHS_DEVDMASTATUS_END_TR_ST_Msk & ((value) << USBHS_DEVDMASTATUS_END_TR_ST_Pos)) +#define USBHS_DEVDMASTATUS_END_BF_ST_Pos _U_(5) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_DEVDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_BF_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_DEVDMASTATUS_END_BF_ST(value) (USBHS_DEVDMASTATUS_END_BF_ST_Msk & ((value) << USBHS_DEVDMASTATUS_END_BF_ST_Pos)) +#define USBHS_DEVDMASTATUS_DESC_LDST_Pos _U_(6) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_DEVDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_DESC_LDST_Pos) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_DEVDMASTATUS_DESC_LDST(value) (USBHS_DEVDMASTATUS_DESC_LDST_Msk & ((value) << USBHS_DEVDMASTATUS_DESC_LDST_Pos)) +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos _U_(16) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Position */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) (USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_DEVDMASTATUS) Register Mask */ + + +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register (n = 1) -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos _U_(0) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) (USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMANXTDSC) Register Mask */ + + +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register (n = 1) -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos _U_(0) /**< (USBHS_HSTDMAADDRESS) Buffer Address Position */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_HSTDMAADDRESS) Buffer Address Mask */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) (USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMAADDRESS) Register Mask */ + + +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register (n = 1) -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB_Pos _U_(0) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Position */ +#define USBHS_HSTDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Mask */ +#define USBHS_HSTDMACONTROL_CHANN_ENB(value) (USBHS_HSTDMACONTROL_CHANN_ENB_Msk & ((value) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos)) +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Pos _U_(1) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC(value) (USBHS_HSTDMACONTROL_LDNXT_DSC_Msk & ((value) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos)) +#define USBHS_HSTDMACONTROL_END_TR_EN_Pos _U_(2) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_HSTDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_HSTDMACONTROL_END_TR_EN(value) (USBHS_HSTDMACONTROL_END_TR_EN_Msk & ((value) << USBHS_HSTDMACONTROL_END_TR_EN_Pos)) +#define USBHS_HSTDMACONTROL_END_B_EN_Pos _U_(3) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_HSTDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_B_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_HSTDMACONTROL_END_B_EN(value) (USBHS_HSTDMACONTROL_END_B_EN_Msk & ((value) << USBHS_HSTDMACONTROL_END_B_EN_Pos)) +#define USBHS_HSTDMACONTROL_END_TR_IT_Pos _U_(4) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_IT_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_TR_IT(value) (USBHS_HSTDMACONTROL_END_TR_IT_Msk & ((value) << USBHS_HSTDMACONTROL_END_TR_IT_Pos)) +#define USBHS_HSTDMACONTROL_END_BUFFIT_Pos _U_(5) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_BUFFIT(value) (USBHS_HSTDMACONTROL_END_BUFFIT_Msk & ((value) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos)) +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Pos _U_(6) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT(value) (USBHS_HSTDMACONTROL_DESC_LD_IT_Msk & ((value) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos)) +#define USBHS_HSTDMACONTROL_BURST_LCK_Pos _U_(7) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Position */ +#define USBHS_HSTDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_BURST_LCK_Pos) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_HSTDMACONTROL_BURST_LCK(value) (USBHS_HSTDMACONTROL_BURST_LCK_Msk & ((value) << USBHS_HSTDMACONTROL_BURST_LCK_Pos)) +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos _U_(16) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) (USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_HSTDMACONTROL) Register Mask */ + + +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: 0x0C) (R/W 32) Host DMA Channel Status Register (n = 1) -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB_Pos _U_(0) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ENB(value) (USBHS_HSTDMASTATUS_CHANN_ENB_Msk & ((value) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos)) +#define USBHS_HSTDMASTATUS_CHANN_ACT_Pos _U_(1) /**< (USBHS_HSTDMASTATUS) Channel Active Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_HSTDMASTATUS) Channel Active Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ACT(value) (USBHS_HSTDMASTATUS_CHANN_ACT_Msk & ((value) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos)) +#define USBHS_HSTDMASTATUS_END_TR_ST_Pos _U_(4) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_HSTDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_TR_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_HSTDMASTATUS_END_TR_ST(value) (USBHS_HSTDMASTATUS_END_TR_ST_Msk & ((value) << USBHS_HSTDMASTATUS_END_TR_ST_Pos)) +#define USBHS_HSTDMASTATUS_END_BF_ST_Pos _U_(5) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_HSTDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_BF_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_HSTDMASTATUS_END_BF_ST(value) (USBHS_HSTDMASTATUS_END_BF_ST_Msk & ((value) << USBHS_HSTDMASTATUS_END_BF_ST_Pos)) +#define USBHS_HSTDMASTATUS_DESC_LDST_Pos _U_(6) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_HSTDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_DESC_LDST_Pos) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_HSTDMASTATUS_DESC_LDST(value) (USBHS_HSTDMASTATUS_DESC_LDST_Msk & ((value) << USBHS_HSTDMASTATUS_DESC_LDST_Pos)) +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos _U_(16) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Position */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) (USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_HSTDMASTATUS) Register Mask */ + + +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos _U_(0) /**< (USBHS_DEVCTRL) USB Address Position */ +#define USBHS_DEVCTRL_UADD_Msk (_U_(0x7F) << USBHS_DEVCTRL_UADD_Pos) /**< (USBHS_DEVCTRL) USB Address Mask */ +#define USBHS_DEVCTRL_UADD(value) (USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)) +#define USBHS_DEVCTRL_ADDEN_Pos _U_(7) /**< (USBHS_DEVCTRL) Address Enable Position */ +#define USBHS_DEVCTRL_ADDEN_Msk (_U_(0x1) << USBHS_DEVCTRL_ADDEN_Pos) /**< (USBHS_DEVCTRL) Address Enable Mask */ +#define USBHS_DEVCTRL_ADDEN(value) (USBHS_DEVCTRL_ADDEN_Msk & ((value) << USBHS_DEVCTRL_ADDEN_Pos)) +#define USBHS_DEVCTRL_DETACH_Pos _U_(8) /**< (USBHS_DEVCTRL) Detach Position */ +#define USBHS_DEVCTRL_DETACH_Msk (_U_(0x1) << USBHS_DEVCTRL_DETACH_Pos) /**< (USBHS_DEVCTRL) Detach Mask */ +#define USBHS_DEVCTRL_DETACH(value) (USBHS_DEVCTRL_DETACH_Msk & ((value) << USBHS_DEVCTRL_DETACH_Pos)) +#define USBHS_DEVCTRL_RMWKUP_Pos _U_(9) /**< (USBHS_DEVCTRL) Remote Wake-Up Position */ +#define USBHS_DEVCTRL_RMWKUP_Msk (_U_(0x1) << USBHS_DEVCTRL_RMWKUP_Pos) /**< (USBHS_DEVCTRL) Remote Wake-Up Mask */ +#define USBHS_DEVCTRL_RMWKUP(value) (USBHS_DEVCTRL_RMWKUP_Msk & ((value) << USBHS_DEVCTRL_RMWKUP_Pos)) +#define USBHS_DEVCTRL_SPDCONF_Pos _U_(10) /**< (USBHS_DEVCTRL) Mode Configuration Position */ +#define USBHS_DEVCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Mode Configuration Mask */ +#define USBHS_DEVCTRL_SPDCONF(value) (USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)) +#define USBHS_DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_NORMAL (USBHS_DEVCTRL_SPDCONF_NORMAL_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_DEVCTRL_LS_Pos _U_(12) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Position */ +#define USBHS_DEVCTRL_LS_Msk (_U_(0x1) << USBHS_DEVCTRL_LS_Pos) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Mask */ +#define USBHS_DEVCTRL_LS(value) (USBHS_DEVCTRL_LS_Msk & ((value) << USBHS_DEVCTRL_LS_Pos)) +#define USBHS_DEVCTRL_TSTJ_Pos _U_(13) /**< (USBHS_DEVCTRL) Test mode J Position */ +#define USBHS_DEVCTRL_TSTJ_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTJ_Pos) /**< (USBHS_DEVCTRL) Test mode J Mask */ +#define USBHS_DEVCTRL_TSTJ(value) (USBHS_DEVCTRL_TSTJ_Msk & ((value) << USBHS_DEVCTRL_TSTJ_Pos)) +#define USBHS_DEVCTRL_TSTK_Pos _U_(14) /**< (USBHS_DEVCTRL) Test mode K Position */ +#define USBHS_DEVCTRL_TSTK_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTK_Pos) /**< (USBHS_DEVCTRL) Test mode K Mask */ +#define USBHS_DEVCTRL_TSTK(value) (USBHS_DEVCTRL_TSTK_Msk & ((value) << USBHS_DEVCTRL_TSTK_Pos)) +#define USBHS_DEVCTRL_TSTPCKT_Pos _U_(15) /**< (USBHS_DEVCTRL) Test packet mode Position */ +#define USBHS_DEVCTRL_TSTPCKT_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTPCKT_Pos) /**< (USBHS_DEVCTRL) Test packet mode Mask */ +#define USBHS_DEVCTRL_TSTPCKT(value) (USBHS_DEVCTRL_TSTPCKT_Msk & ((value) << USBHS_DEVCTRL_TSTPCKT_Pos)) +#define USBHS_DEVCTRL_OPMODE2_Pos _U_(16) /**< (USBHS_DEVCTRL) Specific Operational mode Position */ +#define USBHS_DEVCTRL_OPMODE2_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE2_Pos) /**< (USBHS_DEVCTRL) Specific Operational mode Mask */ +#define USBHS_DEVCTRL_OPMODE2(value) (USBHS_DEVCTRL_OPMODE2_Msk & ((value) << USBHS_DEVCTRL_OPMODE2_Pos)) +#define USBHS_DEVCTRL_Msk _U_(0x0001FFFF) /**< (USBHS_DEVCTRL) Register Mask */ + +#define USBHS_DEVCTRL_OPMODE_Pos _U_(16) /**< (USBHS_DEVCTRL Position) Specific Operational mode */ +#define USBHS_DEVCTRL_OPMODE_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE_Pos) /**< (USBHS_DEVCTRL Mask) OPMODE */ +#define USBHS_DEVCTRL_OPMODE(value) (USBHS_DEVCTRL_OPMODE_Msk & ((value) << USBHS_DEVCTRL_OPMODE_Pos)) + +/* -------- USBHS_DEVISR : (USBHS Offset: 0x04) ( R/ 32) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP_Pos _U_(0) /**< (USBHS_DEVISR) Suspend Interrupt Position */ +#define USBHS_DEVISR_SUSP_Msk (_U_(0x1) << USBHS_DEVISR_SUSP_Pos) /**< (USBHS_DEVISR) Suspend Interrupt Mask */ +#define USBHS_DEVISR_SUSP(value) (USBHS_DEVISR_SUSP_Msk & ((value) << USBHS_DEVISR_SUSP_Pos)) +#define USBHS_DEVISR_MSOF_Pos _U_(1) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Position */ +#define USBHS_DEVISR_MSOF_Msk (_U_(0x1) << USBHS_DEVISR_MSOF_Pos) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_MSOF(value) (USBHS_DEVISR_MSOF_Msk & ((value) << USBHS_DEVISR_MSOF_Pos)) +#define USBHS_DEVISR_SOF_Pos _U_(2) /**< (USBHS_DEVISR) Start of Frame Interrupt Position */ +#define USBHS_DEVISR_SOF_Msk (_U_(0x1) << USBHS_DEVISR_SOF_Pos) /**< (USBHS_DEVISR) Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_SOF(value) (USBHS_DEVISR_SOF_Msk & ((value) << USBHS_DEVISR_SOF_Pos)) +#define USBHS_DEVISR_EORST_Pos _U_(3) /**< (USBHS_DEVISR) End of Reset Interrupt Position */ +#define USBHS_DEVISR_EORST_Msk (_U_(0x1) << USBHS_DEVISR_EORST_Pos) /**< (USBHS_DEVISR) End of Reset Interrupt Mask */ +#define USBHS_DEVISR_EORST(value) (USBHS_DEVISR_EORST_Msk & ((value) << USBHS_DEVISR_EORST_Pos)) +#define USBHS_DEVISR_WAKEUP_Pos _U_(4) /**< (USBHS_DEVISR) Wake-Up Interrupt Position */ +#define USBHS_DEVISR_WAKEUP_Msk (_U_(0x1) << USBHS_DEVISR_WAKEUP_Pos) /**< (USBHS_DEVISR) Wake-Up Interrupt Mask */ +#define USBHS_DEVISR_WAKEUP(value) (USBHS_DEVISR_WAKEUP_Msk & ((value) << USBHS_DEVISR_WAKEUP_Pos)) +#define USBHS_DEVISR_EORSM_Pos _U_(5) /**< (USBHS_DEVISR) End of Resume Interrupt Position */ +#define USBHS_DEVISR_EORSM_Msk (_U_(0x1) << USBHS_DEVISR_EORSM_Pos) /**< (USBHS_DEVISR) End of Resume Interrupt Mask */ +#define USBHS_DEVISR_EORSM(value) (USBHS_DEVISR_EORSM_Msk & ((value) << USBHS_DEVISR_EORSM_Pos)) +#define USBHS_DEVISR_UPRSM_Pos _U_(6) /**< (USBHS_DEVISR) Upstream Resume Interrupt Position */ +#define USBHS_DEVISR_UPRSM_Msk (_U_(0x1) << USBHS_DEVISR_UPRSM_Pos) /**< (USBHS_DEVISR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVISR_UPRSM(value) (USBHS_DEVISR_UPRSM_Msk & ((value) << USBHS_DEVISR_UPRSM_Pos)) +#define USBHS_DEVISR_PEP_0_Pos _U_(12) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Position */ +#define USBHS_DEVISR_PEP_0_Msk (_U_(0x1) << USBHS_DEVISR_PEP_0_Pos) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVISR_PEP_0(value) (USBHS_DEVISR_PEP_0_Msk & ((value) << USBHS_DEVISR_PEP_0_Pos)) +#define USBHS_DEVISR_PEP_1_Pos _U_(13) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Position */ +#define USBHS_DEVISR_PEP_1_Msk (_U_(0x1) << USBHS_DEVISR_PEP_1_Pos) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVISR_PEP_1(value) (USBHS_DEVISR_PEP_1_Msk & ((value) << USBHS_DEVISR_PEP_1_Pos)) +#define USBHS_DEVISR_PEP_2_Pos _U_(14) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Position */ +#define USBHS_DEVISR_PEP_2_Msk (_U_(0x1) << USBHS_DEVISR_PEP_2_Pos) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVISR_PEP_2(value) (USBHS_DEVISR_PEP_2_Msk & ((value) << USBHS_DEVISR_PEP_2_Pos)) +#define USBHS_DEVISR_PEP_3_Pos _U_(15) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Position */ +#define USBHS_DEVISR_PEP_3_Msk (_U_(0x1) << USBHS_DEVISR_PEP_3_Pos) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVISR_PEP_3(value) (USBHS_DEVISR_PEP_3_Msk & ((value) << USBHS_DEVISR_PEP_3_Pos)) +#define USBHS_DEVISR_PEP_4_Pos _U_(16) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Position */ +#define USBHS_DEVISR_PEP_4_Msk (_U_(0x1) << USBHS_DEVISR_PEP_4_Pos) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVISR_PEP_4(value) (USBHS_DEVISR_PEP_4_Msk & ((value) << USBHS_DEVISR_PEP_4_Pos)) +#define USBHS_DEVISR_PEP_5_Pos _U_(17) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Position */ +#define USBHS_DEVISR_PEP_5_Msk (_U_(0x1) << USBHS_DEVISR_PEP_5_Pos) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVISR_PEP_5(value) (USBHS_DEVISR_PEP_5_Msk & ((value) << USBHS_DEVISR_PEP_5_Pos)) +#define USBHS_DEVISR_PEP_6_Pos _U_(18) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Position */ +#define USBHS_DEVISR_PEP_6_Msk (_U_(0x1) << USBHS_DEVISR_PEP_6_Pos) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVISR_PEP_6(value) (USBHS_DEVISR_PEP_6_Msk & ((value) << USBHS_DEVISR_PEP_6_Pos)) +#define USBHS_DEVISR_PEP_7_Pos _U_(19) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Position */ +#define USBHS_DEVISR_PEP_7_Msk (_U_(0x1) << USBHS_DEVISR_PEP_7_Pos) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVISR_PEP_7(value) (USBHS_DEVISR_PEP_7_Msk & ((value) << USBHS_DEVISR_PEP_7_Pos)) +#define USBHS_DEVISR_PEP_8_Pos _U_(20) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Position */ +#define USBHS_DEVISR_PEP_8_Msk (_U_(0x1) << USBHS_DEVISR_PEP_8_Pos) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVISR_PEP_8(value) (USBHS_DEVISR_PEP_8_Msk & ((value) << USBHS_DEVISR_PEP_8_Pos)) +#define USBHS_DEVISR_PEP_9_Pos _U_(21) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Position */ +#define USBHS_DEVISR_PEP_9_Msk (_U_(0x1) << USBHS_DEVISR_PEP_9_Pos) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVISR_PEP_9(value) (USBHS_DEVISR_PEP_9_Msk & ((value) << USBHS_DEVISR_PEP_9_Pos)) +#define USBHS_DEVISR_PEP_10_Pos _U_(22) /**< (USBHS_DEVISR) Endpoint 10 Interrupt Position */ +#define USBHS_DEVISR_PEP_10_Msk (_U_(0x1) << USBHS_DEVISR_PEP_10_Pos) /**< (USBHS_DEVISR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVISR_PEP_10(value) (USBHS_DEVISR_PEP_10_Msk & ((value) << USBHS_DEVISR_PEP_10_Pos)) +#define USBHS_DEVISR_PEP_11_Pos _U_(23) /**< (USBHS_DEVISR) Endpoint 11 Interrupt Position */ +#define USBHS_DEVISR_PEP_11_Msk (_U_(0x1) << USBHS_DEVISR_PEP_11_Pos) /**< (USBHS_DEVISR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVISR_PEP_11(value) (USBHS_DEVISR_PEP_11_Msk & ((value) << USBHS_DEVISR_PEP_11_Pos)) +#define USBHS_DEVISR_DMA_1_Pos _U_(25) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Position */ +#define USBHS_DEVISR_DMA_1_Msk (_U_(0x1) << USBHS_DEVISR_DMA_1_Pos) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVISR_DMA_1(value) (USBHS_DEVISR_DMA_1_Msk & ((value) << USBHS_DEVISR_DMA_1_Pos)) +#define USBHS_DEVISR_DMA_2_Pos _U_(26) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Position */ +#define USBHS_DEVISR_DMA_2_Msk (_U_(0x1) << USBHS_DEVISR_DMA_2_Pos) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVISR_DMA_2(value) (USBHS_DEVISR_DMA_2_Msk & ((value) << USBHS_DEVISR_DMA_2_Pos)) +#define USBHS_DEVISR_DMA_3_Pos _U_(27) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Position */ +#define USBHS_DEVISR_DMA_3_Msk (_U_(0x1) << USBHS_DEVISR_DMA_3_Pos) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVISR_DMA_3(value) (USBHS_DEVISR_DMA_3_Msk & ((value) << USBHS_DEVISR_DMA_3_Pos)) +#define USBHS_DEVISR_DMA_4_Pos _U_(28) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Position */ +#define USBHS_DEVISR_DMA_4_Msk (_U_(0x1) << USBHS_DEVISR_DMA_4_Pos) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVISR_DMA_4(value) (USBHS_DEVISR_DMA_4_Msk & ((value) << USBHS_DEVISR_DMA_4_Pos)) +#define USBHS_DEVISR_DMA_5_Pos _U_(29) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Position */ +#define USBHS_DEVISR_DMA_5_Msk (_U_(0x1) << USBHS_DEVISR_DMA_5_Pos) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVISR_DMA_5(value) (USBHS_DEVISR_DMA_5_Msk & ((value) << USBHS_DEVISR_DMA_5_Pos)) +#define USBHS_DEVISR_DMA_6_Pos _U_(30) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Position */ +#define USBHS_DEVISR_DMA_6_Msk (_U_(0x1) << USBHS_DEVISR_DMA_6_Pos) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVISR_DMA_6(value) (USBHS_DEVISR_DMA_6_Msk & ((value) << USBHS_DEVISR_DMA_6_Pos)) +#define USBHS_DEVISR_DMA_7_Pos _U_(31) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Position */ +#define USBHS_DEVISR_DMA_7_Msk (_U_(0x1) << USBHS_DEVISR_DMA_7_Pos) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVISR_DMA_7(value) (USBHS_DEVISR_DMA_7_Msk & ((value) << USBHS_DEVISR_DMA_7_Pos)) +#define USBHS_DEVISR_Msk _U_(0xFEFFF07F) /**< (USBHS_DEVISR) Register Mask */ + +#define USBHS_DEVISR_PEP__Pos _U_(12) /**< (USBHS_DEVISR Position) Endpoint x Interrupt */ +#define USBHS_DEVISR_PEP__Msk (_U_(0xFFF) << USBHS_DEVISR_PEP__Pos) /**< (USBHS_DEVISR Mask) PEP_ */ +#define USBHS_DEVISR_PEP_(value) (USBHS_DEVISR_PEP__Msk & ((value) << USBHS_DEVISR_PEP__Pos)) +#define USBHS_DEVISR_DMA__Pos _U_(25) /**< (USBHS_DEVISR Position) DMA Channel 7 Interrupt */ +#define USBHS_DEVISR_DMA__Msk (_U_(0x7F) << USBHS_DEVISR_DMA__Pos) /**< (USBHS_DEVISR Mask) DMA_ */ +#define USBHS_DEVISR_DMA_(value) (USBHS_DEVISR_DMA__Msk & ((value) << USBHS_DEVISR_DMA__Pos)) + +/* -------- USBHS_DEVICR : (USBHS Offset: 0x08) ( /W 32) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC_Pos _U_(0) /**< (USBHS_DEVICR) Suspend Interrupt Clear Position */ +#define USBHS_DEVICR_SUSPC_Msk (_U_(0x1) << USBHS_DEVICR_SUSPC_Pos) /**< (USBHS_DEVICR) Suspend Interrupt Clear Mask */ +#define USBHS_DEVICR_SUSPC(value) (USBHS_DEVICR_SUSPC_Msk & ((value) << USBHS_DEVICR_SUSPC_Pos)) +#define USBHS_DEVICR_MSOFC_Pos _U_(1) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_MSOFC_Msk (_U_(0x1) << USBHS_DEVICR_MSOFC_Pos) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_MSOFC(value) (USBHS_DEVICR_MSOFC_Msk & ((value) << USBHS_DEVICR_MSOFC_Pos)) +#define USBHS_DEVICR_SOFC_Pos _U_(2) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_SOFC_Msk (_U_(0x1) << USBHS_DEVICR_SOFC_Pos) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_SOFC(value) (USBHS_DEVICR_SOFC_Msk & ((value) << USBHS_DEVICR_SOFC_Pos)) +#define USBHS_DEVICR_EORSTC_Pos _U_(3) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Position */ +#define USBHS_DEVICR_EORSTC_Msk (_U_(0x1) << USBHS_DEVICR_EORSTC_Pos) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSTC(value) (USBHS_DEVICR_EORSTC_Msk & ((value) << USBHS_DEVICR_EORSTC_Pos)) +#define USBHS_DEVICR_WAKEUPC_Pos _U_(4) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Position */ +#define USBHS_DEVICR_WAKEUPC_Msk (_U_(0x1) << USBHS_DEVICR_WAKEUPC_Pos) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Mask */ +#define USBHS_DEVICR_WAKEUPC(value) (USBHS_DEVICR_WAKEUPC_Msk & ((value) << USBHS_DEVICR_WAKEUPC_Pos)) +#define USBHS_DEVICR_EORSMC_Pos _U_(5) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Position */ +#define USBHS_DEVICR_EORSMC_Msk (_U_(0x1) << USBHS_DEVICR_EORSMC_Pos) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSMC(value) (USBHS_DEVICR_EORSMC_Msk & ((value) << USBHS_DEVICR_EORSMC_Pos)) +#define USBHS_DEVICR_UPRSMC_Pos _U_(6) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Position */ +#define USBHS_DEVICR_UPRSMC_Msk (_U_(0x1) << USBHS_DEVICR_UPRSMC_Pos) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_UPRSMC(value) (USBHS_DEVICR_UPRSMC_Msk & ((value) << USBHS_DEVICR_UPRSMC_Pos)) +#define USBHS_DEVICR_Msk _U_(0x0000007F) /**< (USBHS_DEVICR) Register Mask */ + + +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x0C) ( /W 32) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS_Pos _U_(0) /**< (USBHS_DEVIFR) Suspend Interrupt Set Position */ +#define USBHS_DEVIFR_SUSPS_Msk (_U_(0x1) << USBHS_DEVIFR_SUSPS_Pos) /**< (USBHS_DEVIFR) Suspend Interrupt Set Mask */ +#define USBHS_DEVIFR_SUSPS(value) (USBHS_DEVIFR_SUSPS_Msk & ((value) << USBHS_DEVIFR_SUSPS_Pos)) +#define USBHS_DEVIFR_MSOFS_Pos _U_(1) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_MSOFS_Msk (_U_(0x1) << USBHS_DEVIFR_MSOFS_Pos) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_MSOFS(value) (USBHS_DEVIFR_MSOFS_Msk & ((value) << USBHS_DEVIFR_MSOFS_Pos)) +#define USBHS_DEVIFR_SOFS_Pos _U_(2) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_SOFS_Msk (_U_(0x1) << USBHS_DEVIFR_SOFS_Pos) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_SOFS(value) (USBHS_DEVIFR_SOFS_Msk & ((value) << USBHS_DEVIFR_SOFS_Pos)) +#define USBHS_DEVIFR_EORSTS_Pos _U_(3) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Position */ +#define USBHS_DEVIFR_EORSTS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSTS_Pos) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSTS(value) (USBHS_DEVIFR_EORSTS_Msk & ((value) << USBHS_DEVIFR_EORSTS_Pos)) +#define USBHS_DEVIFR_WAKEUPS_Pos _U_(4) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Position */ +#define USBHS_DEVIFR_WAKEUPS_Msk (_U_(0x1) << USBHS_DEVIFR_WAKEUPS_Pos) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Mask */ +#define USBHS_DEVIFR_WAKEUPS(value) (USBHS_DEVIFR_WAKEUPS_Msk & ((value) << USBHS_DEVIFR_WAKEUPS_Pos)) +#define USBHS_DEVIFR_EORSMS_Pos _U_(5) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Position */ +#define USBHS_DEVIFR_EORSMS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSMS_Pos) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSMS(value) (USBHS_DEVIFR_EORSMS_Msk & ((value) << USBHS_DEVIFR_EORSMS_Pos)) +#define USBHS_DEVIFR_UPRSMS_Pos _U_(6) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Position */ +#define USBHS_DEVIFR_UPRSMS_Msk (_U_(0x1) << USBHS_DEVIFR_UPRSMS_Pos) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_UPRSMS(value) (USBHS_DEVIFR_UPRSMS_Msk & ((value) << USBHS_DEVIFR_UPRSMS_Pos)) +#define USBHS_DEVIFR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_1_Pos) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_1(value) (USBHS_DEVIFR_DMA_1_Msk & ((value) << USBHS_DEVIFR_DMA_1_Pos)) +#define USBHS_DEVIFR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_2_Pos) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_2(value) (USBHS_DEVIFR_DMA_2_Msk & ((value) << USBHS_DEVIFR_DMA_2_Pos)) +#define USBHS_DEVIFR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_3_Pos) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_3(value) (USBHS_DEVIFR_DMA_3_Msk & ((value) << USBHS_DEVIFR_DMA_3_Pos)) +#define USBHS_DEVIFR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_4_Pos) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_4(value) (USBHS_DEVIFR_DMA_4_Msk & ((value) << USBHS_DEVIFR_DMA_4_Pos)) +#define USBHS_DEVIFR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_5_Pos) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_5(value) (USBHS_DEVIFR_DMA_5_Msk & ((value) << USBHS_DEVIFR_DMA_5_Pos)) +#define USBHS_DEVIFR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_6_Pos) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_6(value) (USBHS_DEVIFR_DMA_6_Msk & ((value) << USBHS_DEVIFR_DMA_6_Pos)) +#define USBHS_DEVIFR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_7_Pos) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_7(value) (USBHS_DEVIFR_DMA_7_Msk & ((value) << USBHS_DEVIFR_DMA_7_Pos)) +#define USBHS_DEVIFR_Msk _U_(0xFE00007F) /**< (USBHS_DEVIFR) Register Mask */ + +#define USBHS_DEVIFR_DMA__Pos _U_(25) /**< (USBHS_DEVIFR Position) DMA Channel 7 Interrupt Set */ +#define USBHS_DEVIFR_DMA__Msk (_U_(0x7F) << USBHS_DEVIFR_DMA__Pos) /**< (USBHS_DEVIFR Mask) DMA_ */ +#define USBHS_DEVIFR_DMA_(value) (USBHS_DEVIFR_DMA__Msk & ((value) << USBHS_DEVIFR_DMA__Pos)) + +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x10) ( R/ 32) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE_Pos _U_(0) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Position */ +#define USBHS_DEVIMR_SUSPE_Msk (_U_(0x1) << USBHS_DEVIMR_SUSPE_Pos) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Mask */ +#define USBHS_DEVIMR_SUSPE(value) (USBHS_DEVIMR_SUSPE_Msk & ((value) << USBHS_DEVIMR_SUSPE_Pos)) +#define USBHS_DEVIMR_MSOFE_Pos _U_(1) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_MSOFE_Msk (_U_(0x1) << USBHS_DEVIMR_MSOFE_Pos) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_MSOFE(value) (USBHS_DEVIMR_MSOFE_Msk & ((value) << USBHS_DEVIMR_MSOFE_Pos)) +#define USBHS_DEVIMR_SOFE_Pos _U_(2) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_SOFE_Msk (_U_(0x1) << USBHS_DEVIMR_SOFE_Pos) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_SOFE(value) (USBHS_DEVIMR_SOFE_Msk & ((value) << USBHS_DEVIMR_SOFE_Pos)) +#define USBHS_DEVIMR_EORSTE_Pos _U_(3) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSTE_Msk (_U_(0x1) << USBHS_DEVIMR_EORSTE_Pos) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSTE(value) (USBHS_DEVIMR_EORSTE_Msk & ((value) << USBHS_DEVIMR_EORSTE_Pos)) +#define USBHS_DEVIMR_WAKEUPE_Pos _U_(4) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Position */ +#define USBHS_DEVIMR_WAKEUPE_Msk (_U_(0x1) << USBHS_DEVIMR_WAKEUPE_Pos) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Mask */ +#define USBHS_DEVIMR_WAKEUPE(value) (USBHS_DEVIMR_WAKEUPE_Msk & ((value) << USBHS_DEVIMR_WAKEUPE_Pos)) +#define USBHS_DEVIMR_EORSME_Pos _U_(5) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSME_Msk (_U_(0x1) << USBHS_DEVIMR_EORSME_Pos) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSME(value) (USBHS_DEVIMR_EORSME_Msk & ((value) << USBHS_DEVIMR_EORSME_Pos)) +#define USBHS_DEVIMR_UPRSME_Pos _U_(6) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_UPRSME_Msk (_U_(0x1) << USBHS_DEVIMR_UPRSME_Pos) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_UPRSME(value) (USBHS_DEVIMR_UPRSME_Msk & ((value) << USBHS_DEVIMR_UPRSME_Pos)) +#define USBHS_DEVIMR_PEP_0_Pos _U_(12) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_0_Pos) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_0(value) (USBHS_DEVIMR_PEP_0_Msk & ((value) << USBHS_DEVIMR_PEP_0_Pos)) +#define USBHS_DEVIMR_PEP_1_Pos _U_(13) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_1_Pos) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_1(value) (USBHS_DEVIMR_PEP_1_Msk & ((value) << USBHS_DEVIMR_PEP_1_Pos)) +#define USBHS_DEVIMR_PEP_2_Pos _U_(14) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_2_Pos) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_2(value) (USBHS_DEVIMR_PEP_2_Msk & ((value) << USBHS_DEVIMR_PEP_2_Pos)) +#define USBHS_DEVIMR_PEP_3_Pos _U_(15) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_3_Pos) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_3(value) (USBHS_DEVIMR_PEP_3_Msk & ((value) << USBHS_DEVIMR_PEP_3_Pos)) +#define USBHS_DEVIMR_PEP_4_Pos _U_(16) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_4_Pos) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_4(value) (USBHS_DEVIMR_PEP_4_Msk & ((value) << USBHS_DEVIMR_PEP_4_Pos)) +#define USBHS_DEVIMR_PEP_5_Pos _U_(17) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_5_Pos) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_5(value) (USBHS_DEVIMR_PEP_5_Msk & ((value) << USBHS_DEVIMR_PEP_5_Pos)) +#define USBHS_DEVIMR_PEP_6_Pos _U_(18) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_6_Pos) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_6(value) (USBHS_DEVIMR_PEP_6_Msk & ((value) << USBHS_DEVIMR_PEP_6_Pos)) +#define USBHS_DEVIMR_PEP_7_Pos _U_(19) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_7_Pos) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_7(value) (USBHS_DEVIMR_PEP_7_Msk & ((value) << USBHS_DEVIMR_PEP_7_Pos)) +#define USBHS_DEVIMR_PEP_8_Pos _U_(20) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_8_Pos) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_8(value) (USBHS_DEVIMR_PEP_8_Msk & ((value) << USBHS_DEVIMR_PEP_8_Pos)) +#define USBHS_DEVIMR_PEP_9_Pos _U_(21) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_9_Pos) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_9(value) (USBHS_DEVIMR_PEP_9_Msk & ((value) << USBHS_DEVIMR_PEP_9_Pos)) +#define USBHS_DEVIMR_PEP_10_Pos _U_(22) /**< (USBHS_DEVIMR) Endpoint 10 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_10_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_10_Pos) /**< (USBHS_DEVIMR) Endpoint 10 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_10(value) (USBHS_DEVIMR_PEP_10_Msk & ((value) << USBHS_DEVIMR_PEP_10_Pos)) +#define USBHS_DEVIMR_PEP_11_Pos _U_(23) /**< (USBHS_DEVIMR) Endpoint 11 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_11_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_11_Pos) /**< (USBHS_DEVIMR) Endpoint 11 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_11(value) (USBHS_DEVIMR_PEP_11_Msk & ((value) << USBHS_DEVIMR_PEP_11_Pos)) +#define USBHS_DEVIMR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_1_Pos) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_1(value) (USBHS_DEVIMR_DMA_1_Msk & ((value) << USBHS_DEVIMR_DMA_1_Pos)) +#define USBHS_DEVIMR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_2_Pos) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_2(value) (USBHS_DEVIMR_DMA_2_Msk & ((value) << USBHS_DEVIMR_DMA_2_Pos)) +#define USBHS_DEVIMR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_3_Pos) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_3(value) (USBHS_DEVIMR_DMA_3_Msk & ((value) << USBHS_DEVIMR_DMA_3_Pos)) +#define USBHS_DEVIMR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_4_Pos) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_4(value) (USBHS_DEVIMR_DMA_4_Msk & ((value) << USBHS_DEVIMR_DMA_4_Pos)) +#define USBHS_DEVIMR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_5_Pos) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_5(value) (USBHS_DEVIMR_DMA_5_Msk & ((value) << USBHS_DEVIMR_DMA_5_Pos)) +#define USBHS_DEVIMR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_6_Pos) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_6(value) (USBHS_DEVIMR_DMA_6_Msk & ((value) << USBHS_DEVIMR_DMA_6_Pos)) +#define USBHS_DEVIMR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_7_Pos) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_7(value) (USBHS_DEVIMR_DMA_7_Msk & ((value) << USBHS_DEVIMR_DMA_7_Pos)) +#define USBHS_DEVIMR_Msk _U_(0xFEFFF07F) /**< (USBHS_DEVIMR) Register Mask */ + +#define USBHS_DEVIMR_PEP__Pos _U_(12) /**< (USBHS_DEVIMR Position) Endpoint x Interrupt Mask */ +#define USBHS_DEVIMR_PEP__Msk (_U_(0xFFF) << USBHS_DEVIMR_PEP__Pos) /**< (USBHS_DEVIMR Mask) PEP_ */ +#define USBHS_DEVIMR_PEP_(value) (USBHS_DEVIMR_PEP__Msk & ((value) << USBHS_DEVIMR_PEP__Pos)) +#define USBHS_DEVIMR_DMA__Pos _U_(25) /**< (USBHS_DEVIMR Position) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVIMR_DMA__Msk (_U_(0x7F) << USBHS_DEVIMR_DMA__Pos) /**< (USBHS_DEVIMR Mask) DMA_ */ +#define USBHS_DEVIMR_DMA_(value) (USBHS_DEVIMR_DMA__Msk & ((value) << USBHS_DEVIMR_DMA__Pos)) + +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x14) ( /W 32) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC_Pos _U_(0) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Position */ +#define USBHS_DEVIDR_SUSPEC_Msk (_U_(0x1) << USBHS_DEVIDR_SUSPEC_Pos) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Mask */ +#define USBHS_DEVIDR_SUSPEC(value) (USBHS_DEVIDR_SUSPEC_Msk & ((value) << USBHS_DEVIDR_SUSPEC_Pos)) +#define USBHS_DEVIDR_MSOFEC_Pos _U_(1) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_MSOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_MSOFEC_Pos) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_MSOFEC(value) (USBHS_DEVIDR_MSOFEC_Msk & ((value) << USBHS_DEVIDR_MSOFEC_Pos)) +#define USBHS_DEVIDR_SOFEC_Pos _U_(2) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_SOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_SOFEC_Pos) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_SOFEC(value) (USBHS_DEVIDR_SOFEC_Msk & ((value) << USBHS_DEVIDR_SOFEC_Pos)) +#define USBHS_DEVIDR_EORSTEC_Pos _U_(3) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSTEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSTEC_Pos) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSTEC(value) (USBHS_DEVIDR_EORSTEC_Msk & ((value) << USBHS_DEVIDR_EORSTEC_Pos)) +#define USBHS_DEVIDR_WAKEUPEC_Pos _U_(4) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Position */ +#define USBHS_DEVIDR_WAKEUPEC_Msk (_U_(0x1) << USBHS_DEVIDR_WAKEUPEC_Pos) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Mask */ +#define USBHS_DEVIDR_WAKEUPEC(value) (USBHS_DEVIDR_WAKEUPEC_Msk & ((value) << USBHS_DEVIDR_WAKEUPEC_Pos)) +#define USBHS_DEVIDR_EORSMEC_Pos _U_(5) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSMEC_Pos) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSMEC(value) (USBHS_DEVIDR_EORSMEC_Msk & ((value) << USBHS_DEVIDR_EORSMEC_Pos)) +#define USBHS_DEVIDR_UPRSMEC_Pos _U_(6) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_UPRSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_UPRSMEC_Pos) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_UPRSMEC(value) (USBHS_DEVIDR_UPRSMEC_Msk & ((value) << USBHS_DEVIDR_UPRSMEC_Pos)) +#define USBHS_DEVIDR_PEP_0_Pos _U_(12) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_0_Pos) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_0(value) (USBHS_DEVIDR_PEP_0_Msk & ((value) << USBHS_DEVIDR_PEP_0_Pos)) +#define USBHS_DEVIDR_PEP_1_Pos _U_(13) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_1_Pos) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_1(value) (USBHS_DEVIDR_PEP_1_Msk & ((value) << USBHS_DEVIDR_PEP_1_Pos)) +#define USBHS_DEVIDR_PEP_2_Pos _U_(14) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_2_Pos) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_2(value) (USBHS_DEVIDR_PEP_2_Msk & ((value) << USBHS_DEVIDR_PEP_2_Pos)) +#define USBHS_DEVIDR_PEP_3_Pos _U_(15) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_3_Pos) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_3(value) (USBHS_DEVIDR_PEP_3_Msk & ((value) << USBHS_DEVIDR_PEP_3_Pos)) +#define USBHS_DEVIDR_PEP_4_Pos _U_(16) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_4_Pos) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_4(value) (USBHS_DEVIDR_PEP_4_Msk & ((value) << USBHS_DEVIDR_PEP_4_Pos)) +#define USBHS_DEVIDR_PEP_5_Pos _U_(17) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_5_Pos) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_5(value) (USBHS_DEVIDR_PEP_5_Msk & ((value) << USBHS_DEVIDR_PEP_5_Pos)) +#define USBHS_DEVIDR_PEP_6_Pos _U_(18) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_6_Pos) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_6(value) (USBHS_DEVIDR_PEP_6_Msk & ((value) << USBHS_DEVIDR_PEP_6_Pos)) +#define USBHS_DEVIDR_PEP_7_Pos _U_(19) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_7_Pos) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_7(value) (USBHS_DEVIDR_PEP_7_Msk & ((value) << USBHS_DEVIDR_PEP_7_Pos)) +#define USBHS_DEVIDR_PEP_8_Pos _U_(20) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_8_Pos) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_8(value) (USBHS_DEVIDR_PEP_8_Msk & ((value) << USBHS_DEVIDR_PEP_8_Pos)) +#define USBHS_DEVIDR_PEP_9_Pos _U_(21) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_9_Pos) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_9(value) (USBHS_DEVIDR_PEP_9_Msk & ((value) << USBHS_DEVIDR_PEP_9_Pos)) +#define USBHS_DEVIDR_PEP_10_Pos _U_(22) /**< (USBHS_DEVIDR) Endpoint 10 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_10_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_10_Pos) /**< (USBHS_DEVIDR) Endpoint 10 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_10(value) (USBHS_DEVIDR_PEP_10_Msk & ((value) << USBHS_DEVIDR_PEP_10_Pos)) +#define USBHS_DEVIDR_PEP_11_Pos _U_(23) /**< (USBHS_DEVIDR) Endpoint 11 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_11_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_11_Pos) /**< (USBHS_DEVIDR) Endpoint 11 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_11(value) (USBHS_DEVIDR_PEP_11_Msk & ((value) << USBHS_DEVIDR_PEP_11_Pos)) +#define USBHS_DEVIDR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_1_Pos) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_1(value) (USBHS_DEVIDR_DMA_1_Msk & ((value) << USBHS_DEVIDR_DMA_1_Pos)) +#define USBHS_DEVIDR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_2_Pos) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_2(value) (USBHS_DEVIDR_DMA_2_Msk & ((value) << USBHS_DEVIDR_DMA_2_Pos)) +#define USBHS_DEVIDR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_3_Pos) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_3(value) (USBHS_DEVIDR_DMA_3_Msk & ((value) << USBHS_DEVIDR_DMA_3_Pos)) +#define USBHS_DEVIDR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_4_Pos) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_4(value) (USBHS_DEVIDR_DMA_4_Msk & ((value) << USBHS_DEVIDR_DMA_4_Pos)) +#define USBHS_DEVIDR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_5_Pos) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_5(value) (USBHS_DEVIDR_DMA_5_Msk & ((value) << USBHS_DEVIDR_DMA_5_Pos)) +#define USBHS_DEVIDR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_6_Pos) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_6(value) (USBHS_DEVIDR_DMA_6_Msk & ((value) << USBHS_DEVIDR_DMA_6_Pos)) +#define USBHS_DEVIDR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_7_Pos) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_7(value) (USBHS_DEVIDR_DMA_7_Msk & ((value) << USBHS_DEVIDR_DMA_7_Pos)) +#define USBHS_DEVIDR_Msk _U_(0xFEFFF07F) /**< (USBHS_DEVIDR) Register Mask */ + +#define USBHS_DEVIDR_PEP__Pos _U_(12) /**< (USBHS_DEVIDR Position) Endpoint x Interrupt Disable */ +#define USBHS_DEVIDR_PEP__Msk (_U_(0xFFF) << USBHS_DEVIDR_PEP__Pos) /**< (USBHS_DEVIDR Mask) PEP_ */ +#define USBHS_DEVIDR_PEP_(value) (USBHS_DEVIDR_PEP__Msk & ((value) << USBHS_DEVIDR_PEP__Pos)) +#define USBHS_DEVIDR_DMA__Pos _U_(25) /**< (USBHS_DEVIDR Position) DMA Channel 7 Interrupt Disable */ +#define USBHS_DEVIDR_DMA__Msk (_U_(0x7F) << USBHS_DEVIDR_DMA__Pos) /**< (USBHS_DEVIDR Mask) DMA_ */ +#define USBHS_DEVIDR_DMA_(value) (USBHS_DEVIDR_DMA__Msk & ((value) << USBHS_DEVIDR_DMA__Pos)) + +/* -------- USBHS_DEVIER : (USBHS Offset: 0x18) ( /W 32) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES_Pos _U_(0) /**< (USBHS_DEVIER) Suspend Interrupt Enable Position */ +#define USBHS_DEVIER_SUSPES_Msk (_U_(0x1) << USBHS_DEVIER_SUSPES_Pos) /**< (USBHS_DEVIER) Suspend Interrupt Enable Mask */ +#define USBHS_DEVIER_SUSPES(value) (USBHS_DEVIER_SUSPES_Msk & ((value) << USBHS_DEVIER_SUSPES_Pos)) +#define USBHS_DEVIER_MSOFES_Pos _U_(1) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_MSOFES_Msk (_U_(0x1) << USBHS_DEVIER_MSOFES_Pos) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_MSOFES(value) (USBHS_DEVIER_MSOFES_Msk & ((value) << USBHS_DEVIER_MSOFES_Pos)) +#define USBHS_DEVIER_SOFES_Pos _U_(2) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_SOFES_Msk (_U_(0x1) << USBHS_DEVIER_SOFES_Pos) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_SOFES(value) (USBHS_DEVIER_SOFES_Msk & ((value) << USBHS_DEVIER_SOFES_Pos)) +#define USBHS_DEVIER_EORSTES_Pos _U_(3) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Position */ +#define USBHS_DEVIER_EORSTES_Msk (_U_(0x1) << USBHS_DEVIER_EORSTES_Pos) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSTES(value) (USBHS_DEVIER_EORSTES_Msk & ((value) << USBHS_DEVIER_EORSTES_Pos)) +#define USBHS_DEVIER_WAKEUPES_Pos _U_(4) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Position */ +#define USBHS_DEVIER_WAKEUPES_Msk (_U_(0x1) << USBHS_DEVIER_WAKEUPES_Pos) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Mask */ +#define USBHS_DEVIER_WAKEUPES(value) (USBHS_DEVIER_WAKEUPES_Msk & ((value) << USBHS_DEVIER_WAKEUPES_Pos)) +#define USBHS_DEVIER_EORSMES_Pos _U_(5) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Position */ +#define USBHS_DEVIER_EORSMES_Msk (_U_(0x1) << USBHS_DEVIER_EORSMES_Pos) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSMES(value) (USBHS_DEVIER_EORSMES_Msk & ((value) << USBHS_DEVIER_EORSMES_Pos)) +#define USBHS_DEVIER_UPRSMES_Pos _U_(6) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Position */ +#define USBHS_DEVIER_UPRSMES_Msk (_U_(0x1) << USBHS_DEVIER_UPRSMES_Pos) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_UPRSMES(value) (USBHS_DEVIER_UPRSMES_Msk & ((value) << USBHS_DEVIER_UPRSMES_Pos)) +#define USBHS_DEVIER_PEP_0_Pos _U_(12) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_0_Msk (_U_(0x1) << USBHS_DEVIER_PEP_0_Pos) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_0(value) (USBHS_DEVIER_PEP_0_Msk & ((value) << USBHS_DEVIER_PEP_0_Pos)) +#define USBHS_DEVIER_PEP_1_Pos _U_(13) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_1_Msk (_U_(0x1) << USBHS_DEVIER_PEP_1_Pos) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_1(value) (USBHS_DEVIER_PEP_1_Msk & ((value) << USBHS_DEVIER_PEP_1_Pos)) +#define USBHS_DEVIER_PEP_2_Pos _U_(14) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_2_Msk (_U_(0x1) << USBHS_DEVIER_PEP_2_Pos) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_2(value) (USBHS_DEVIER_PEP_2_Msk & ((value) << USBHS_DEVIER_PEP_2_Pos)) +#define USBHS_DEVIER_PEP_3_Pos _U_(15) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_3_Msk (_U_(0x1) << USBHS_DEVIER_PEP_3_Pos) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_3(value) (USBHS_DEVIER_PEP_3_Msk & ((value) << USBHS_DEVIER_PEP_3_Pos)) +#define USBHS_DEVIER_PEP_4_Pos _U_(16) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_4_Msk (_U_(0x1) << USBHS_DEVIER_PEP_4_Pos) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_4(value) (USBHS_DEVIER_PEP_4_Msk & ((value) << USBHS_DEVIER_PEP_4_Pos)) +#define USBHS_DEVIER_PEP_5_Pos _U_(17) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_5_Msk (_U_(0x1) << USBHS_DEVIER_PEP_5_Pos) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_5(value) (USBHS_DEVIER_PEP_5_Msk & ((value) << USBHS_DEVIER_PEP_5_Pos)) +#define USBHS_DEVIER_PEP_6_Pos _U_(18) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_6_Msk (_U_(0x1) << USBHS_DEVIER_PEP_6_Pos) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_6(value) (USBHS_DEVIER_PEP_6_Msk & ((value) << USBHS_DEVIER_PEP_6_Pos)) +#define USBHS_DEVIER_PEP_7_Pos _U_(19) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_7_Msk (_U_(0x1) << USBHS_DEVIER_PEP_7_Pos) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_7(value) (USBHS_DEVIER_PEP_7_Msk & ((value) << USBHS_DEVIER_PEP_7_Pos)) +#define USBHS_DEVIER_PEP_8_Pos _U_(20) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_8_Msk (_U_(0x1) << USBHS_DEVIER_PEP_8_Pos) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_8(value) (USBHS_DEVIER_PEP_8_Msk & ((value) << USBHS_DEVIER_PEP_8_Pos)) +#define USBHS_DEVIER_PEP_9_Pos _U_(21) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_9_Msk (_U_(0x1) << USBHS_DEVIER_PEP_9_Pos) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_9(value) (USBHS_DEVIER_PEP_9_Msk & ((value) << USBHS_DEVIER_PEP_9_Pos)) +#define USBHS_DEVIER_PEP_10_Pos _U_(22) /**< (USBHS_DEVIER) Endpoint 10 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_10_Msk (_U_(0x1) << USBHS_DEVIER_PEP_10_Pos) /**< (USBHS_DEVIER) Endpoint 10 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_10(value) (USBHS_DEVIER_PEP_10_Msk & ((value) << USBHS_DEVIER_PEP_10_Pos)) +#define USBHS_DEVIER_PEP_11_Pos _U_(23) /**< (USBHS_DEVIER) Endpoint 11 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_11_Msk (_U_(0x1) << USBHS_DEVIER_PEP_11_Pos) /**< (USBHS_DEVIER) Endpoint 11 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_11(value) (USBHS_DEVIER_PEP_11_Msk & ((value) << USBHS_DEVIER_PEP_11_Pos)) +#define USBHS_DEVIER_DMA_1_Pos _U_(25) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_1_Msk (_U_(0x1) << USBHS_DEVIER_DMA_1_Pos) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_1(value) (USBHS_DEVIER_DMA_1_Msk & ((value) << USBHS_DEVIER_DMA_1_Pos)) +#define USBHS_DEVIER_DMA_2_Pos _U_(26) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_2_Msk (_U_(0x1) << USBHS_DEVIER_DMA_2_Pos) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_2(value) (USBHS_DEVIER_DMA_2_Msk & ((value) << USBHS_DEVIER_DMA_2_Pos)) +#define USBHS_DEVIER_DMA_3_Pos _U_(27) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_3_Msk (_U_(0x1) << USBHS_DEVIER_DMA_3_Pos) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_3(value) (USBHS_DEVIER_DMA_3_Msk & ((value) << USBHS_DEVIER_DMA_3_Pos)) +#define USBHS_DEVIER_DMA_4_Pos _U_(28) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_4_Msk (_U_(0x1) << USBHS_DEVIER_DMA_4_Pos) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_4(value) (USBHS_DEVIER_DMA_4_Msk & ((value) << USBHS_DEVIER_DMA_4_Pos)) +#define USBHS_DEVIER_DMA_5_Pos _U_(29) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_5_Msk (_U_(0x1) << USBHS_DEVIER_DMA_5_Pos) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_5(value) (USBHS_DEVIER_DMA_5_Msk & ((value) << USBHS_DEVIER_DMA_5_Pos)) +#define USBHS_DEVIER_DMA_6_Pos _U_(30) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_6_Msk (_U_(0x1) << USBHS_DEVIER_DMA_6_Pos) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_6(value) (USBHS_DEVIER_DMA_6_Msk & ((value) << USBHS_DEVIER_DMA_6_Pos)) +#define USBHS_DEVIER_DMA_7_Pos _U_(31) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_7_Msk (_U_(0x1) << USBHS_DEVIER_DMA_7_Pos) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_7(value) (USBHS_DEVIER_DMA_7_Msk & ((value) << USBHS_DEVIER_DMA_7_Pos)) +#define USBHS_DEVIER_Msk _U_(0xFEFFF07F) /**< (USBHS_DEVIER) Register Mask */ + +#define USBHS_DEVIER_PEP__Pos _U_(12) /**< (USBHS_DEVIER Position) Endpoint x Interrupt Enable */ +#define USBHS_DEVIER_PEP__Msk (_U_(0xFFF) << USBHS_DEVIER_PEP__Pos) /**< (USBHS_DEVIER Mask) PEP_ */ +#define USBHS_DEVIER_PEP_(value) (USBHS_DEVIER_PEP__Msk & ((value) << USBHS_DEVIER_PEP__Pos)) +#define USBHS_DEVIER_DMA__Pos _U_(25) /**< (USBHS_DEVIER Position) DMA Channel 7 Interrupt Enable */ +#define USBHS_DEVIER_DMA__Msk (_U_(0x7F) << USBHS_DEVIER_DMA__Pos) /**< (USBHS_DEVIER Mask) DMA_ */ +#define USBHS_DEVIER_DMA_(value) (USBHS_DEVIER_DMA__Msk & ((value) << USBHS_DEVIER_DMA__Pos)) + +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x1C) (R/W 32) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0_Pos _U_(0) /**< (USBHS_DEVEPT) Endpoint 0 Enable Position */ +#define USBHS_DEVEPT_EPEN0_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Enable Mask */ +#define USBHS_DEVEPT_EPEN0(value) (USBHS_DEVEPT_EPEN0_Msk & ((value) << USBHS_DEVEPT_EPEN0_Pos)) +#define USBHS_DEVEPT_EPEN1_Pos _U_(1) /**< (USBHS_DEVEPT) Endpoint 1 Enable Position */ +#define USBHS_DEVEPT_EPEN1_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Enable Mask */ +#define USBHS_DEVEPT_EPEN1(value) (USBHS_DEVEPT_EPEN1_Msk & ((value) << USBHS_DEVEPT_EPEN1_Pos)) +#define USBHS_DEVEPT_EPEN2_Pos _U_(2) /**< (USBHS_DEVEPT) Endpoint 2 Enable Position */ +#define USBHS_DEVEPT_EPEN2_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Enable Mask */ +#define USBHS_DEVEPT_EPEN2(value) (USBHS_DEVEPT_EPEN2_Msk & ((value) << USBHS_DEVEPT_EPEN2_Pos)) +#define USBHS_DEVEPT_EPEN3_Pos _U_(3) /**< (USBHS_DEVEPT) Endpoint 3 Enable Position */ +#define USBHS_DEVEPT_EPEN3_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Enable Mask */ +#define USBHS_DEVEPT_EPEN3(value) (USBHS_DEVEPT_EPEN3_Msk & ((value) << USBHS_DEVEPT_EPEN3_Pos)) +#define USBHS_DEVEPT_EPEN4_Pos _U_(4) /**< (USBHS_DEVEPT) Endpoint 4 Enable Position */ +#define USBHS_DEVEPT_EPEN4_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Enable Mask */ +#define USBHS_DEVEPT_EPEN4(value) (USBHS_DEVEPT_EPEN4_Msk & ((value) << USBHS_DEVEPT_EPEN4_Pos)) +#define USBHS_DEVEPT_EPEN5_Pos _U_(5) /**< (USBHS_DEVEPT) Endpoint 5 Enable Position */ +#define USBHS_DEVEPT_EPEN5_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Enable Mask */ +#define USBHS_DEVEPT_EPEN5(value) (USBHS_DEVEPT_EPEN5_Msk & ((value) << USBHS_DEVEPT_EPEN5_Pos)) +#define USBHS_DEVEPT_EPEN6_Pos _U_(6) /**< (USBHS_DEVEPT) Endpoint 6 Enable Position */ +#define USBHS_DEVEPT_EPEN6_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Enable Mask */ +#define USBHS_DEVEPT_EPEN6(value) (USBHS_DEVEPT_EPEN6_Msk & ((value) << USBHS_DEVEPT_EPEN6_Pos)) +#define USBHS_DEVEPT_EPEN7_Pos _U_(7) /**< (USBHS_DEVEPT) Endpoint 7 Enable Position */ +#define USBHS_DEVEPT_EPEN7_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Enable Mask */ +#define USBHS_DEVEPT_EPEN7(value) (USBHS_DEVEPT_EPEN7_Msk & ((value) << USBHS_DEVEPT_EPEN7_Pos)) +#define USBHS_DEVEPT_EPEN8_Pos _U_(8) /**< (USBHS_DEVEPT) Endpoint 8 Enable Position */ +#define USBHS_DEVEPT_EPEN8_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Enable Mask */ +#define USBHS_DEVEPT_EPEN8(value) (USBHS_DEVEPT_EPEN8_Msk & ((value) << USBHS_DEVEPT_EPEN8_Pos)) +#define USBHS_DEVEPT_EPEN9_Pos _U_(9) /**< (USBHS_DEVEPT) Endpoint 9 Enable Position */ +#define USBHS_DEVEPT_EPEN9_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Enable Mask */ +#define USBHS_DEVEPT_EPEN9(value) (USBHS_DEVEPT_EPEN9_Msk & ((value) << USBHS_DEVEPT_EPEN9_Pos)) +#define USBHS_DEVEPT_EPRST0_Pos _U_(16) /**< (USBHS_DEVEPT) Endpoint 0 Reset Position */ +#define USBHS_DEVEPT_EPRST0_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Reset Mask */ +#define USBHS_DEVEPT_EPRST0(value) (USBHS_DEVEPT_EPRST0_Msk & ((value) << USBHS_DEVEPT_EPRST0_Pos)) +#define USBHS_DEVEPT_EPRST1_Pos _U_(17) /**< (USBHS_DEVEPT) Endpoint 1 Reset Position */ +#define USBHS_DEVEPT_EPRST1_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Reset Mask */ +#define USBHS_DEVEPT_EPRST1(value) (USBHS_DEVEPT_EPRST1_Msk & ((value) << USBHS_DEVEPT_EPRST1_Pos)) +#define USBHS_DEVEPT_EPRST2_Pos _U_(18) /**< (USBHS_DEVEPT) Endpoint 2 Reset Position */ +#define USBHS_DEVEPT_EPRST2_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Reset Mask */ +#define USBHS_DEVEPT_EPRST2(value) (USBHS_DEVEPT_EPRST2_Msk & ((value) << USBHS_DEVEPT_EPRST2_Pos)) +#define USBHS_DEVEPT_EPRST3_Pos _U_(19) /**< (USBHS_DEVEPT) Endpoint 3 Reset Position */ +#define USBHS_DEVEPT_EPRST3_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Reset Mask */ +#define USBHS_DEVEPT_EPRST3(value) (USBHS_DEVEPT_EPRST3_Msk & ((value) << USBHS_DEVEPT_EPRST3_Pos)) +#define USBHS_DEVEPT_EPRST4_Pos _U_(20) /**< (USBHS_DEVEPT) Endpoint 4 Reset Position */ +#define USBHS_DEVEPT_EPRST4_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Reset Mask */ +#define USBHS_DEVEPT_EPRST4(value) (USBHS_DEVEPT_EPRST4_Msk & ((value) << USBHS_DEVEPT_EPRST4_Pos)) +#define USBHS_DEVEPT_EPRST5_Pos _U_(21) /**< (USBHS_DEVEPT) Endpoint 5 Reset Position */ +#define USBHS_DEVEPT_EPRST5_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Reset Mask */ +#define USBHS_DEVEPT_EPRST5(value) (USBHS_DEVEPT_EPRST5_Msk & ((value) << USBHS_DEVEPT_EPRST5_Pos)) +#define USBHS_DEVEPT_EPRST6_Pos _U_(22) /**< (USBHS_DEVEPT) Endpoint 6 Reset Position */ +#define USBHS_DEVEPT_EPRST6_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Reset Mask */ +#define USBHS_DEVEPT_EPRST6(value) (USBHS_DEVEPT_EPRST6_Msk & ((value) << USBHS_DEVEPT_EPRST6_Pos)) +#define USBHS_DEVEPT_EPRST7_Pos _U_(23) /**< (USBHS_DEVEPT) Endpoint 7 Reset Position */ +#define USBHS_DEVEPT_EPRST7_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Reset Mask */ +#define USBHS_DEVEPT_EPRST7(value) (USBHS_DEVEPT_EPRST7_Msk & ((value) << USBHS_DEVEPT_EPRST7_Pos)) +#define USBHS_DEVEPT_EPRST8_Pos _U_(24) /**< (USBHS_DEVEPT) Endpoint 8 Reset Position */ +#define USBHS_DEVEPT_EPRST8_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Reset Mask */ +#define USBHS_DEVEPT_EPRST8(value) (USBHS_DEVEPT_EPRST8_Msk & ((value) << USBHS_DEVEPT_EPRST8_Pos)) +#define USBHS_DEVEPT_EPRST9_Pos _U_(25) /**< (USBHS_DEVEPT) Endpoint 9 Reset Position */ +#define USBHS_DEVEPT_EPRST9_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Reset Mask */ +#define USBHS_DEVEPT_EPRST9(value) (USBHS_DEVEPT_EPRST9_Msk & ((value) << USBHS_DEVEPT_EPRST9_Pos)) +#define USBHS_DEVEPT_Msk _U_(0x03FF03FF) /**< (USBHS_DEVEPT) Register Mask */ + +#define USBHS_DEVEPT_EPEN_Pos _U_(0) /**< (USBHS_DEVEPT Position) Endpoint x Enable */ +#define USBHS_DEVEPT_EPEN_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPEN_Pos) /**< (USBHS_DEVEPT Mask) EPEN */ +#define USBHS_DEVEPT_EPEN(value) (USBHS_DEVEPT_EPEN_Msk & ((value) << USBHS_DEVEPT_EPEN_Pos)) +#define USBHS_DEVEPT_EPRST_Pos _U_(16) /**< (USBHS_DEVEPT Position) Endpoint 9 Reset */ +#define USBHS_DEVEPT_EPRST_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPRST_Pos) /**< (USBHS_DEVEPT Mask) EPRST */ +#define USBHS_DEVEPT_EPRST(value) (USBHS_DEVEPT_EPRST_Msk & ((value) << USBHS_DEVEPT_EPRST_Pos)) + +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x20) ( R/ 32) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos _U_(0) /**< (USBHS_DEVFNUM) Micro Frame Number Position */ +#define USBHS_DEVFNUM_MFNUM_Msk (_U_(0x7) << USBHS_DEVFNUM_MFNUM_Pos) /**< (USBHS_DEVFNUM) Micro Frame Number Mask */ +#define USBHS_DEVFNUM_MFNUM(value) (USBHS_DEVFNUM_MFNUM_Msk & ((value) << USBHS_DEVFNUM_MFNUM_Pos)) +#define USBHS_DEVFNUM_FNUM_Pos _U_(3) /**< (USBHS_DEVFNUM) Frame Number Position */ +#define USBHS_DEVFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_DEVFNUM_FNUM_Pos) /**< (USBHS_DEVFNUM) Frame Number Mask */ +#define USBHS_DEVFNUM_FNUM(value) (USBHS_DEVFNUM_FNUM_Msk & ((value) << USBHS_DEVFNUM_FNUM_Pos)) +#define USBHS_DEVFNUM_FNCERR_Pos _U_(15) /**< (USBHS_DEVFNUM) Frame Number CRC Error Position */ +#define USBHS_DEVFNUM_FNCERR_Msk (_U_(0x1) << USBHS_DEVFNUM_FNCERR_Pos) /**< (USBHS_DEVFNUM) Frame Number CRC Error Mask */ +#define USBHS_DEVFNUM_FNCERR(value) (USBHS_DEVFNUM_FNCERR_Msk & ((value) << USBHS_DEVFNUM_FNCERR_Pos)) +#define USBHS_DEVFNUM_Msk _U_(0x0000BFFF) /**< (USBHS_DEVFNUM) Register Mask */ + + +/* -------- USBHS_DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTCFG_ALLOC_Pos _U_(1) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Position */ +#define USBHS_DEVEPTCFG_ALLOC_Msk (_U_(0x1) << USBHS_DEVEPTCFG_ALLOC_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Mask */ +#define USBHS_DEVEPTCFG_ALLOC(value) (USBHS_DEVEPTCFG_ALLOC_Msk & ((value) << USBHS_DEVEPTCFG_ALLOC_Pos)) +#define USBHS_DEVEPTCFG_EPBK_Pos _U_(2) /**< (USBHS_DEVEPTCFG) Endpoint Banks Position */ +#define USBHS_DEVEPTCFG_EPBK_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Banks Mask */ +#define USBHS_DEVEPTCFG_EPBK(value) (USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)) +#define USBHS_DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_1_BANK (USBHS_DEVEPTCFG_EPBK_1_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Single-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (USBHS_DEVEPTCFG_EPBK_2_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Double-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (USBHS_DEVEPTCFG_EPBK_3_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos _U_(4) /**< (USBHS_DEVEPTCFG) Endpoint Size Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Msk (_U_(0x7) << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Size Mask */ +#define USBHS_DEVEPTCFG_EPSIZE(value) (USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_DEVEPTCFG) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_DEVEPTCFG) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_DEVEPTCFG) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_DEVEPTCFG) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 8 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 16 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 32 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 64 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 128 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 256 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 512 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 1024 bytes Position */ +#define USBHS_DEVEPTCFG_EPDIR_Pos _U_(8) /**< (USBHS_DEVEPTCFG) Endpoint Direction Position */ +#define USBHS_DEVEPTCFG_EPDIR_Msk (_U_(0x1) << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Direction Mask */ +#define USBHS_DEVEPTCFG_EPDIR(value) (USBHS_DEVEPTCFG_EPDIR_Msk & ((value) << USBHS_DEVEPTCFG_EPDIR_Pos)) +#define USBHS_DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (USBHS_DEVEPTCFG_EPDIR_OUT_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. Position */ +#define USBHS_DEVEPTCFG_EPDIR_IN (USBHS_DEVEPTCFG_EPDIR_IN_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Pos _U_(9) /**< (USBHS_DEVEPTCFG) Automatic Switch Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Msk (_U_(0x1) << USBHS_DEVEPTCFG_AUTOSW_Pos) /**< (USBHS_DEVEPTCFG) Automatic Switch Mask */ +#define USBHS_DEVEPTCFG_AUTOSW(value) (USBHS_DEVEPTCFG_AUTOSW_Msk & ((value) << USBHS_DEVEPTCFG_AUTOSW_Pos)) +#define USBHS_DEVEPTCFG_EPTYPE_Pos _U_(11) /**< (USBHS_DEVEPTCFG) Endpoint Type Position */ +#define USBHS_DEVEPTCFG_EPTYPE_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Type Mask */ +#define USBHS_DEVEPTCFG_EPTYPE(value) (USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Interrupt */ +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (USBHS_DEVEPTCFG_EPTYPE_CTRL_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Control Position */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (USBHS_DEVEPTCFG_EPTYPE_ISO_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Isochronous Position */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (USBHS_DEVEPTCFG_EPTYPE_BLK_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Bulk Position */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Interrupt Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos _U_(13) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Msk (_U_(0x3) << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ +#define USBHS_DEVEPTCFG_NBTRANS(value) (USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ +#define USBHS_DEVEPTCFG_Msk _U_(0x00007B7E) /**< (USBHS_DEVEPTCFG) Register Mask */ + + +/* -------- USBHS_DEVEPTISR : (USBHS Offset: 0x130) ( R/ 32) Device Endpoint Status Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTISR_TXINI_Pos _U_(0) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTISR_TXINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_TXINI_Pos) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTISR_TXINI(value) (USBHS_DEVEPTISR_TXINI_Msk & ((value) << USBHS_DEVEPTISR_TXINI_Pos)) +#define USBHS_DEVEPTISR_RXOUTI_Pos _U_(1) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTISR_RXOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_RXOUTI_Pos) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTISR_RXOUTI(value) (USBHS_DEVEPTISR_RXOUTI_Msk & ((value) << USBHS_DEVEPTISR_RXOUTI_Pos)) +#define USBHS_DEVEPTISR_RXSTPI_Pos _U_(2) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_RXSTPI(value) (USBHS_DEVEPTISR_RXSTPI_Msk & ((value) << USBHS_DEVEPTISR_RXSTPI_Pos)) +#define USBHS_DEVEPTISR_NAKOUTI_Pos _U_(3) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_NAKOUTI(value) (USBHS_DEVEPTISR_NAKOUTI_Msk & ((value) << USBHS_DEVEPTISR_NAKOUTI_Pos)) +#define USBHS_DEVEPTISR_NAKINI_Pos _U_(4) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_NAKINI(value) (USBHS_DEVEPTISR_NAKINI_Msk & ((value) << USBHS_DEVEPTISR_NAKINI_Pos)) +#define USBHS_DEVEPTISR_OVERFI_Pos _U_(5) /**< (USBHS_DEVEPTISR) Overflow Interrupt Position */ +#define USBHS_DEVEPTISR_OVERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_OVERFI_Pos) /**< (USBHS_DEVEPTISR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTISR_OVERFI(value) (USBHS_DEVEPTISR_OVERFI_Msk & ((value) << USBHS_DEVEPTISR_OVERFI_Pos)) +#define USBHS_DEVEPTISR_STALLEDI_Pos _U_(6) /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_STALLEDI(value) (USBHS_DEVEPTISR_STALLEDI_Msk & ((value) << USBHS_DEVEPTISR_STALLEDI_Pos)) +#define USBHS_DEVEPTISR_SHORTPACKET_Pos _U_(7) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTISR_SHORTPACKET_Msk (_U_(0x1) << USBHS_DEVEPTISR_SHORTPACKET_Pos) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTISR_SHORTPACKET(value) (USBHS_DEVEPTISR_SHORTPACKET_Msk & ((value) << USBHS_DEVEPTISR_SHORTPACKET_Pos)) +#define USBHS_DEVEPTISR_DTSEQ_Pos _U_(8) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_Msk (_U_(0x3) << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Mask */ +#define USBHS_DEVEPTISR_DTSEQ(value) (USBHS_DEVEPTISR_DTSEQ_Msk & ((value) << USBHS_DEVEPTISR_DTSEQ_Pos)) +#define USBHS_DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (USBHS_DEVEPTISR_DTSEQ_DATA0_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data0 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (USBHS_DEVEPTISR_DTSEQ_DATA1_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data1 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (USBHS_DEVEPTISR_DTSEQ_DATA2_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (USBHS_DEVEPTISR_DTSEQ_MDATA_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos _U_(12) /**< (USBHS_DEVEPTISR) Number of Busy Banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) Number of Busy Banks Mask */ +#define USBHS_DEVEPTISR_NBUSYBK(value) (USBHS_DEVEPTISR_NBUSYBK_Msk & ((value) << USBHS_DEVEPTISR_NBUSYBK_Pos)) +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_DEVEPTISR) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_DEVEPTISR) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_DEVEPTISR) 3 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) Position */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 1 busy bank Position */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 2 busy banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 3 busy banks Position */ +#define USBHS_DEVEPTISR_CURRBK_Pos _U_(14) /**< (USBHS_DEVEPTISR) Current Bank Position */ +#define USBHS_DEVEPTISR_CURRBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current Bank Mask */ +#define USBHS_DEVEPTISR_CURRBK(value) (USBHS_DEVEPTISR_CURRBK_Msk & ((value) << USBHS_DEVEPTISR_CURRBK_Pos)) +#define USBHS_DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Current bank is bank2 */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (USBHS_DEVEPTISR_CURRBK_BANK0_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank0 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (USBHS_DEVEPTISR_CURRBK_BANK1_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank1 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (USBHS_DEVEPTISR_CURRBK_BANK2_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank2 Position */ +#define USBHS_DEVEPTISR_RWALL_Pos _U_(16) /**< (USBHS_DEVEPTISR) Read/Write Allowed Position */ +#define USBHS_DEVEPTISR_RWALL_Msk (_U_(0x1) << USBHS_DEVEPTISR_RWALL_Pos) /**< (USBHS_DEVEPTISR) Read/Write Allowed Mask */ +#define USBHS_DEVEPTISR_RWALL(value) (USBHS_DEVEPTISR_RWALL_Msk & ((value) << USBHS_DEVEPTISR_RWALL_Pos)) +#define USBHS_DEVEPTISR_CTRLDIR_Pos _U_(17) /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_CTRLDIR(value) (USBHS_DEVEPTISR_CTRLDIR_Msk & ((value) << USBHS_DEVEPTISR_CTRLDIR_Pos)) +#define USBHS_DEVEPTISR_CFGOK_Pos _U_(18) /**< (USBHS_DEVEPTISR) Configuration OK Status Position */ +#define USBHS_DEVEPTISR_CFGOK_Msk (_U_(0x1) << USBHS_DEVEPTISR_CFGOK_Pos) /**< (USBHS_DEVEPTISR) Configuration OK Status Mask */ +#define USBHS_DEVEPTISR_CFGOK(value) (USBHS_DEVEPTISR_CFGOK_Msk & ((value) << USBHS_DEVEPTISR_CFGOK_Pos)) +#define USBHS_DEVEPTISR_BYCT_Pos _U_(20) /**< (USBHS_DEVEPTISR) Byte Count Position */ +#define USBHS_DEVEPTISR_BYCT_Msk (_U_(0x7FF) << USBHS_DEVEPTISR_BYCT_Pos) /**< (USBHS_DEVEPTISR) Byte Count Mask */ +#define USBHS_DEVEPTISR_BYCT(value) (USBHS_DEVEPTISR_BYCT_Msk & ((value) << USBHS_DEVEPTISR_BYCT_Pos)) +#define USBHS_DEVEPTISR_Msk _U_(0x7FF7F3FF) /**< (USBHS_DEVEPTISR) Register Mask */ + + +/* -------- USBHS_DEVEPTICR : (USBHS Offset: 0x160) ( /W 32) Device Endpoint Clear Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTICR_TXINIC_Pos _U_(0) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_TXINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_TXINIC_Pos) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_TXINIC(value) (USBHS_DEVEPTICR_TXINIC_Msk & ((value) << USBHS_DEVEPTICR_TXINIC_Pos)) +#define USBHS_DEVEPTICR_RXOUTIC_Pos _U_(1) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_RXOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_RXOUTIC_Pos) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_RXOUTIC(value) (USBHS_DEVEPTICR_RXOUTIC_Msk & ((value) << USBHS_DEVEPTICR_RXOUTIC_Pos)) +#define USBHS_DEVEPTICR_RXSTPIC_Pos _U_(2) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_RXSTPIC(value) (USBHS_DEVEPTICR_RXSTPIC_Msk & ((value) << USBHS_DEVEPTICR_RXSTPIC_Pos)) +#define USBHS_DEVEPTICR_NAKOUTIC_Pos _U_(3) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_NAKOUTIC(value) (USBHS_DEVEPTICR_NAKOUTIC_Msk & ((value) << USBHS_DEVEPTICR_NAKOUTIC_Pos)) +#define USBHS_DEVEPTICR_NAKINIC_Pos _U_(4) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_NAKINIC(value) (USBHS_DEVEPTICR_NAKINIC_Msk & ((value) << USBHS_DEVEPTICR_NAKINIC_Pos)) +#define USBHS_DEVEPTICR_OVERFIC_Pos _U_(5) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTICR_OVERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_OVERFIC_Pos) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_OVERFIC(value) (USBHS_DEVEPTICR_OVERFIC_Msk & ((value) << USBHS_DEVEPTICR_OVERFIC_Pos)) +#define USBHS_DEVEPTICR_STALLEDIC_Pos _U_(6) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_STALLEDIC(value) (USBHS_DEVEPTICR_STALLEDIC_Msk & ((value) << USBHS_DEVEPTICR_STALLEDIC_Pos)) +#define USBHS_DEVEPTICR_SHORTPACKETC_Pos _U_(7) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Position */ +#define USBHS_DEVEPTICR_SHORTPACKETC_Msk (_U_(0x1) << USBHS_DEVEPTICR_SHORTPACKETC_Pos) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_SHORTPACKETC(value) (USBHS_DEVEPTICR_SHORTPACKETC_Msk & ((value) << USBHS_DEVEPTICR_SHORTPACKETC_Pos)) +#define USBHS_DEVEPTICR_Msk _U_(0x000000FF) /**< (USBHS_DEVEPTICR) Register Mask */ + + +/* -------- USBHS_DEVEPTIFR : (USBHS Offset: 0x190) ( /W 32) Device Endpoint Set Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTIFR_TXINIS_Pos _U_(0) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_TXINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_TXINIS_Pos) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_TXINIS(value) (USBHS_DEVEPTIFR_TXINIS_Msk & ((value) << USBHS_DEVEPTIFR_TXINIS_Pos)) +#define USBHS_DEVEPTIFR_RXOUTIS_Pos _U_(1) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_RXOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_RXOUTIS_Pos) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_RXOUTIS(value) (USBHS_DEVEPTIFR_RXOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_RXOUTIS_Pos)) +#define USBHS_DEVEPTIFR_RXSTPIS_Pos _U_(2) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_RXSTPIS(value) (USBHS_DEVEPTIFR_RXSTPIS_Msk & ((value) << USBHS_DEVEPTIFR_RXSTPIS_Pos)) +#define USBHS_DEVEPTIFR_NAKOUTIS_Pos _U_(3) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NAKOUTIS(value) (USBHS_DEVEPTIFR_NAKOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_NAKOUTIS_Pos)) +#define USBHS_DEVEPTIFR_NAKINIS_Pos _U_(4) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NAKINIS(value) (USBHS_DEVEPTIFR_NAKINIS_Msk & ((value) << USBHS_DEVEPTIFR_NAKINIS_Pos)) +#define USBHS_DEVEPTIFR_OVERFIS_Pos _U_(5) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Position */ +#define USBHS_DEVEPTIFR_OVERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_OVERFIS_Pos) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_OVERFIS(value) (USBHS_DEVEPTIFR_OVERFIS_Msk & ((value) << USBHS_DEVEPTIFR_OVERFIS_Pos)) +#define USBHS_DEVEPTIFR_STALLEDIS_Pos _U_(6) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_STALLEDIS(value) (USBHS_DEVEPTIFR_STALLEDIS_Msk & ((value) << USBHS_DEVEPTIFR_STALLEDIS_Pos)) +#define USBHS_DEVEPTIFR_SHORTPACKETS_Pos _U_(7) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Position */ +#define USBHS_DEVEPTIFR_SHORTPACKETS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_SHORTPACKETS(value) (USBHS_DEVEPTIFR_SHORTPACKETS_Msk & ((value) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos)) +#define USBHS_DEVEPTIFR_NBUSYBKS_Pos _U_(12) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NBUSYBKS_Pos) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NBUSYBKS(value) (USBHS_DEVEPTIFR_NBUSYBKS_Msk & ((value) << USBHS_DEVEPTIFR_NBUSYBKS_Pos)) +#define USBHS_DEVEPTIFR_Msk _U_(0x000010FF) /**< (USBHS_DEVEPTIFR) Register Mask */ + + +/* -------- USBHS_DEVEPTIMR : (USBHS Offset: 0x1C0) ( R/ 32) Device Endpoint Mask Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTIMR_TXINE_Pos _U_(0) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTIMR_TXINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_TXINE_Pos) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_TXINE(value) (USBHS_DEVEPTIMR_TXINE_Msk & ((value) << USBHS_DEVEPTIMR_TXINE_Pos)) +#define USBHS_DEVEPTIMR_RXOUTE_Pos _U_(1) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTIMR_RXOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RXOUTE_Pos) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_RXOUTE(value) (USBHS_DEVEPTIMR_RXOUTE_Msk & ((value) << USBHS_DEVEPTIMR_RXOUTE_Pos)) +#define USBHS_DEVEPTIMR_RXSTPE_Pos _U_(2) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_RXSTPE(value) (USBHS_DEVEPTIMR_RXSTPE_Msk & ((value) << USBHS_DEVEPTIMR_RXSTPE_Pos)) +#define USBHS_DEVEPTIMR_NAKOUTE_Pos _U_(3) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_NAKOUTE(value) (USBHS_DEVEPTIMR_NAKOUTE_Msk & ((value) << USBHS_DEVEPTIMR_NAKOUTE_Pos)) +#define USBHS_DEVEPTIMR_NAKINE_Pos _U_(4) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_NAKINE(value) (USBHS_DEVEPTIMR_NAKINE_Msk & ((value) << USBHS_DEVEPTIMR_NAKINE_Pos)) +#define USBHS_DEVEPTIMR_OVERFE_Pos _U_(5) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Position */ +#define USBHS_DEVEPTIMR_OVERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_OVERFE_Pos) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTIMR_OVERFE(value) (USBHS_DEVEPTIMR_OVERFE_Msk & ((value) << USBHS_DEVEPTIMR_OVERFE_Pos)) +#define USBHS_DEVEPTIMR_STALLEDE_Pos _U_(6) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_STALLEDE(value) (USBHS_DEVEPTIMR_STALLEDE_Msk & ((value) << USBHS_DEVEPTIMR_STALLEDE_Pos)) +#define USBHS_DEVEPTIMR_SHORTPACKETE_Pos _U_(7) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTIMR_SHORTPACKETE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTIMR_SHORTPACKETE(value) (USBHS_DEVEPTIMR_SHORTPACKETE_Msk & ((value) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos)) +#define USBHS_DEVEPTIMR_NBUSYBKE_Pos _U_(12) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Position */ +#define USBHS_DEVEPTIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NBUSYBKE_Pos) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Mask */ +#define USBHS_DEVEPTIMR_NBUSYBKE(value) (USBHS_DEVEPTIMR_NBUSYBKE_Msk & ((value) << USBHS_DEVEPTIMR_NBUSYBKE_Pos)) +#define USBHS_DEVEPTIMR_KILLBK_Pos _U_(13) /**< (USBHS_DEVEPTIMR) Kill IN Bank Position */ +#define USBHS_DEVEPTIMR_KILLBK_Msk (_U_(0x1) << USBHS_DEVEPTIMR_KILLBK_Pos) /**< (USBHS_DEVEPTIMR) Kill IN Bank Mask */ +#define USBHS_DEVEPTIMR_KILLBK(value) (USBHS_DEVEPTIMR_KILLBK_Msk & ((value) << USBHS_DEVEPTIMR_KILLBK_Pos)) +#define USBHS_DEVEPTIMR_FIFOCON_Pos _U_(14) /**< (USBHS_DEVEPTIMR) FIFO Control Position */ +#define USBHS_DEVEPTIMR_FIFOCON_Msk (_U_(0x1) << USBHS_DEVEPTIMR_FIFOCON_Pos) /**< (USBHS_DEVEPTIMR) FIFO Control Mask */ +#define USBHS_DEVEPTIMR_FIFOCON(value) (USBHS_DEVEPTIMR_FIFOCON_Msk & ((value) << USBHS_DEVEPTIMR_FIFOCON_Pos)) +#define USBHS_DEVEPTIMR_EPDISHDMA_Pos _U_(16) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ +#define USBHS_DEVEPTIMR_EPDISHDMA_Msk (_U_(0x1) << USBHS_DEVEPTIMR_EPDISHDMA_Pos) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ +#define USBHS_DEVEPTIMR_EPDISHDMA(value) (USBHS_DEVEPTIMR_EPDISHDMA_Msk & ((value) << USBHS_DEVEPTIMR_EPDISHDMA_Pos)) +#define USBHS_DEVEPTIMR_NYETDIS_Pos _U_(17) /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_NYETDIS(value) (USBHS_DEVEPTIMR_NYETDIS_Msk & ((value) << USBHS_DEVEPTIMR_NYETDIS_Pos)) +#define USBHS_DEVEPTIMR_RSTDT_Pos _U_(18) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Position */ +#define USBHS_DEVEPTIMR_RSTDT_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RSTDT_Pos) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Mask */ +#define USBHS_DEVEPTIMR_RSTDT(value) (USBHS_DEVEPTIMR_RSTDT_Msk & ((value) << USBHS_DEVEPTIMR_RSTDT_Pos)) +#define USBHS_DEVEPTIMR_STALLRQ_Pos _U_(19) /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_STALLRQ(value) (USBHS_DEVEPTIMR_STALLRQ_Msk & ((value) << USBHS_DEVEPTIMR_STALLRQ_Pos)) +#define USBHS_DEVEPTIMR_Msk _U_(0x000F70FF) /**< (USBHS_DEVEPTIMR) Register Mask */ + + +/* -------- USBHS_DEVEPTIER : (USBHS Offset: 0x1F0) ( /W 32) Device Endpoint Enable Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTIER_TXINES_Pos _U_(0) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_TXINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_TXINES_Pos) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_TXINES(value) (USBHS_DEVEPTIER_TXINES_Msk & ((value) << USBHS_DEVEPTIER_TXINES_Pos)) +#define USBHS_DEVEPTIER_RXOUTES_Pos _U_(1) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_RXOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_RXOUTES_Pos) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_RXOUTES(value) (USBHS_DEVEPTIER_RXOUTES_Msk & ((value) << USBHS_DEVEPTIER_RXOUTES_Pos)) +#define USBHS_DEVEPTIER_RXSTPES_Pos _U_(2) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_RXSTPES(value) (USBHS_DEVEPTIER_RXSTPES_Msk & ((value) << USBHS_DEVEPTIER_RXSTPES_Pos)) +#define USBHS_DEVEPTIER_NAKOUTES_Pos _U_(3) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NAKOUTES(value) (USBHS_DEVEPTIER_NAKOUTES_Msk & ((value) << USBHS_DEVEPTIER_NAKOUTES_Pos)) +#define USBHS_DEVEPTIER_NAKINES_Pos _U_(4) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NAKINES(value) (USBHS_DEVEPTIER_NAKINES_Msk & ((value) << USBHS_DEVEPTIER_NAKINES_Pos)) +#define USBHS_DEVEPTIER_OVERFES_Pos _U_(5) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Position */ +#define USBHS_DEVEPTIER_OVERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_OVERFES_Pos) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_OVERFES(value) (USBHS_DEVEPTIER_OVERFES_Msk & ((value) << USBHS_DEVEPTIER_OVERFES_Pos)) +#define USBHS_DEVEPTIER_STALLEDES_Pos _U_(6) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_STALLEDES(value) (USBHS_DEVEPTIER_STALLEDES_Msk & ((value) << USBHS_DEVEPTIER_STALLEDES_Pos)) +#define USBHS_DEVEPTIER_SHORTPACKETES_Pos _U_(7) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Position */ +#define USBHS_DEVEPTIER_SHORTPACKETES_Msk (_U_(0x1) << USBHS_DEVEPTIER_SHORTPACKETES_Pos) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_SHORTPACKETES(value) (USBHS_DEVEPTIER_SHORTPACKETES_Msk & ((value) << USBHS_DEVEPTIER_SHORTPACKETES_Pos)) +#define USBHS_DEVEPTIER_NBUSYBKES_Pos _U_(12) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NBUSYBKES_Pos) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NBUSYBKES(value) (USBHS_DEVEPTIER_NBUSYBKES_Msk & ((value) << USBHS_DEVEPTIER_NBUSYBKES_Pos)) +#define USBHS_DEVEPTIER_KILLBKS_Pos _U_(13) /**< (USBHS_DEVEPTIER) Kill IN Bank Position */ +#define USBHS_DEVEPTIER_KILLBKS_Msk (_U_(0x1) << USBHS_DEVEPTIER_KILLBKS_Pos) /**< (USBHS_DEVEPTIER) Kill IN Bank Mask */ +#define USBHS_DEVEPTIER_KILLBKS(value) (USBHS_DEVEPTIER_KILLBKS_Msk & ((value) << USBHS_DEVEPTIER_KILLBKS_Pos)) +#define USBHS_DEVEPTIER_FIFOCONS_Pos _U_(14) /**< (USBHS_DEVEPTIER) FIFO Control Position */ +#define USBHS_DEVEPTIER_FIFOCONS_Msk (_U_(0x1) << USBHS_DEVEPTIER_FIFOCONS_Pos) /**< (USBHS_DEVEPTIER) FIFO Control Mask */ +#define USBHS_DEVEPTIER_FIFOCONS(value) (USBHS_DEVEPTIER_FIFOCONS_Msk & ((value) << USBHS_DEVEPTIER_FIFOCONS_Pos)) +#define USBHS_DEVEPTIER_EPDISHDMAS_Pos _U_(16) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ +#define USBHS_DEVEPTIER_EPDISHDMAS_Msk (_U_(0x1) << USBHS_DEVEPTIER_EPDISHDMAS_Pos) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_DEVEPTIER_EPDISHDMAS(value) (USBHS_DEVEPTIER_EPDISHDMAS_Msk & ((value) << USBHS_DEVEPTIER_EPDISHDMAS_Pos)) +#define USBHS_DEVEPTIER_NYETDISS_Pos _U_(17) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_NYETDISS(value) (USBHS_DEVEPTIER_NYETDISS_Msk & ((value) << USBHS_DEVEPTIER_NYETDISS_Pos)) +#define USBHS_DEVEPTIER_RSTDTS_Pos _U_(18) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Position */ +#define USBHS_DEVEPTIER_RSTDTS_Msk (_U_(0x1) << USBHS_DEVEPTIER_RSTDTS_Pos) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Mask */ +#define USBHS_DEVEPTIER_RSTDTS(value) (USBHS_DEVEPTIER_RSTDTS_Msk & ((value) << USBHS_DEVEPTIER_RSTDTS_Pos)) +#define USBHS_DEVEPTIER_STALLRQS_Pos _U_(19) /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_STALLRQS(value) (USBHS_DEVEPTIER_STALLRQS_Msk & ((value) << USBHS_DEVEPTIER_STALLRQS_Pos)) +#define USBHS_DEVEPTIER_Msk _U_(0x000F70FF) /**< (USBHS_DEVEPTIER) Register Mask */ + + +/* -------- USBHS_DEVEPTIDR : (USBHS Offset: 0x220) ( /W 32) Device Endpoint Disable Register (n = 0) 0 -------- */ +#define USBHS_DEVEPTIDR_TXINEC_Pos _U_(0) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_TXINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_TXINEC_Pos) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_TXINEC(value) (USBHS_DEVEPTIDR_TXINEC_Msk & ((value) << USBHS_DEVEPTIDR_TXINEC_Pos)) +#define USBHS_DEVEPTIDR_RXOUTEC_Pos _U_(1) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_RXOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_RXOUTEC_Pos) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_RXOUTEC(value) (USBHS_DEVEPTIDR_RXOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_RXOUTEC_Pos)) +#define USBHS_DEVEPTIDR_RXSTPEC_Pos _U_(2) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_RXSTPEC(value) (USBHS_DEVEPTIDR_RXSTPEC_Msk & ((value) << USBHS_DEVEPTIDR_RXSTPEC_Pos)) +#define USBHS_DEVEPTIDR_NAKOUTEC_Pos _U_(3) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NAKOUTEC(value) (USBHS_DEVEPTIDR_NAKOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_NAKOUTEC_Pos)) +#define USBHS_DEVEPTIDR_NAKINEC_Pos _U_(4) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NAKINEC(value) (USBHS_DEVEPTIDR_NAKINEC_Msk & ((value) << USBHS_DEVEPTIDR_NAKINEC_Pos)) +#define USBHS_DEVEPTIDR_OVERFEC_Pos _U_(5) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_OVERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_OVERFEC_Pos) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_OVERFEC(value) (USBHS_DEVEPTIDR_OVERFEC_Msk & ((value) << USBHS_DEVEPTIDR_OVERFEC_Pos)) +#define USBHS_DEVEPTIDR_STALLEDEC_Pos _U_(6) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_STALLEDEC(value) (USBHS_DEVEPTIDR_STALLEDEC_Msk & ((value) << USBHS_DEVEPTIDR_STALLEDEC_Pos)) +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Pos _U_(7) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC(value) (USBHS_DEVEPTIDR_SHORTPACKETEC_Msk & ((value) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos)) +#define USBHS_DEVEPTIDR_NBUSYBKEC_Pos _U_(12) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NBUSYBKEC(value) (USBHS_DEVEPTIDR_NBUSYBKEC_Msk & ((value) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos)) +#define USBHS_DEVEPTIDR_FIFOCONC_Pos _U_(14) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Position */ +#define USBHS_DEVEPTIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_FIFOCONC_Pos) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Mask */ +#define USBHS_DEVEPTIDR_FIFOCONC(value) (USBHS_DEVEPTIDR_FIFOCONC_Msk & ((value) << USBHS_DEVEPTIDR_FIFOCONC_Pos)) +#define USBHS_DEVEPTIDR_EPDISHDMAC_Pos _U_(16) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ +#define USBHS_DEVEPTIDR_EPDISHDMAC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ +#define USBHS_DEVEPTIDR_EPDISHDMAC(value) (USBHS_DEVEPTIDR_EPDISHDMAC_Msk & ((value) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos)) +#define USBHS_DEVEPTIDR_NYETDISC_Pos _U_(17) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_NYETDISC(value) (USBHS_DEVEPTIDR_NYETDISC_Msk & ((value) << USBHS_DEVEPTIDR_NYETDISC_Pos)) +#define USBHS_DEVEPTIDR_STALLRQC_Pos _U_(19) /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_STALLRQC(value) (USBHS_DEVEPTIDR_STALLRQC_Msk & ((value) << USBHS_DEVEPTIDR_STALLRQC_Pos)) +#define USBHS_DEVEPTIDR_Msk _U_(0x000B50FF) /**< (USBHS_DEVEPTIDR) Register Mask */ + + +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE_Pos _U_(8) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Position */ +#define USBHS_HSTCTRL_SOFE_Msk (_U_(0x1) << USBHS_HSTCTRL_SOFE_Pos) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Mask */ +#define USBHS_HSTCTRL_SOFE(value) (USBHS_HSTCTRL_SOFE_Msk & ((value) << USBHS_HSTCTRL_SOFE_Pos)) +#define USBHS_HSTCTRL_RESET_Pos _U_(9) /**< (USBHS_HSTCTRL) Send USB Reset Position */ +#define USBHS_HSTCTRL_RESET_Msk (_U_(0x1) << USBHS_HSTCTRL_RESET_Pos) /**< (USBHS_HSTCTRL) Send USB Reset Mask */ +#define USBHS_HSTCTRL_RESET(value) (USBHS_HSTCTRL_RESET_Msk & ((value) << USBHS_HSTCTRL_RESET_Pos)) +#define USBHS_HSTCTRL_RESUME_Pos _U_(10) /**< (USBHS_HSTCTRL) Send USB Resume Position */ +#define USBHS_HSTCTRL_RESUME_Msk (_U_(0x1) << USBHS_HSTCTRL_RESUME_Pos) /**< (USBHS_HSTCTRL) Send USB Resume Mask */ +#define USBHS_HSTCTRL_RESUME(value) (USBHS_HSTCTRL_RESUME_Msk & ((value) << USBHS_HSTCTRL_RESUME_Pos)) +#define USBHS_HSTCTRL_SPDCONF_Pos _U_(12) /**< (USBHS_HSTCTRL) Mode Configuration Position */ +#define USBHS_HSTCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Mode Configuration Mask */ +#define USBHS_HSTCTRL_SPDCONF(value) (USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)) +#define USBHS_HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_NORMAL (USBHS_HSTCTRL_SPDCONF_NORMAL_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_HSTCTRL_Msk _U_(0x00003700) /**< (USBHS_HSTCTRL) Register Mask */ + + +/* -------- USBHS_HSTISR : (USBHS Offset: 0x404) ( R/ 32) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI_Pos _U_(0) /**< (USBHS_HSTISR) Device Connection Interrupt Position */ +#define USBHS_HSTISR_DCONNI_Msk (_U_(0x1) << USBHS_HSTISR_DCONNI_Pos) /**< (USBHS_HSTISR) Device Connection Interrupt Mask */ +#define USBHS_HSTISR_DCONNI(value) (USBHS_HSTISR_DCONNI_Msk & ((value) << USBHS_HSTISR_DCONNI_Pos)) +#define USBHS_HSTISR_DDISCI_Pos _U_(1) /**< (USBHS_HSTISR) Device Disconnection Interrupt Position */ +#define USBHS_HSTISR_DDISCI_Msk (_U_(0x1) << USBHS_HSTISR_DDISCI_Pos) /**< (USBHS_HSTISR) Device Disconnection Interrupt Mask */ +#define USBHS_HSTISR_DDISCI(value) (USBHS_HSTISR_DDISCI_Msk & ((value) << USBHS_HSTISR_DDISCI_Pos)) +#define USBHS_HSTISR_RSTI_Pos _U_(2) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Position */ +#define USBHS_HSTISR_RSTI_Msk (_U_(0x1) << USBHS_HSTISR_RSTI_Pos) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Mask */ +#define USBHS_HSTISR_RSTI(value) (USBHS_HSTISR_RSTI_Msk & ((value) << USBHS_HSTISR_RSTI_Pos)) +#define USBHS_HSTISR_RSMEDI_Pos _U_(3) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Position */ +#define USBHS_HSTISR_RSMEDI_Msk (_U_(0x1) << USBHS_HSTISR_RSMEDI_Pos) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Mask */ +#define USBHS_HSTISR_RSMEDI(value) (USBHS_HSTISR_RSMEDI_Msk & ((value) << USBHS_HSTISR_RSMEDI_Pos)) +#define USBHS_HSTISR_RXRSMI_Pos _U_(4) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Position */ +#define USBHS_HSTISR_RXRSMI_Msk (_U_(0x1) << USBHS_HSTISR_RXRSMI_Pos) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Mask */ +#define USBHS_HSTISR_RXRSMI(value) (USBHS_HSTISR_RXRSMI_Msk & ((value) << USBHS_HSTISR_RXRSMI_Pos)) +#define USBHS_HSTISR_HSOFI_Pos _U_(5) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Position */ +#define USBHS_HSTISR_HSOFI_Msk (_U_(0x1) << USBHS_HSTISR_HSOFI_Pos) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Mask */ +#define USBHS_HSTISR_HSOFI(value) (USBHS_HSTISR_HSOFI_Msk & ((value) << USBHS_HSTISR_HSOFI_Pos)) +#define USBHS_HSTISR_HWUPI_Pos _U_(6) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Position */ +#define USBHS_HSTISR_HWUPI_Msk (_U_(0x1) << USBHS_HSTISR_HWUPI_Pos) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Mask */ +#define USBHS_HSTISR_HWUPI(value) (USBHS_HSTISR_HWUPI_Msk & ((value) << USBHS_HSTISR_HWUPI_Pos)) +#define USBHS_HSTISR_PEP_0_Pos _U_(8) /**< (USBHS_HSTISR) Pipe 0 Interrupt Position */ +#define USBHS_HSTISR_PEP_0_Msk (_U_(0x1) << USBHS_HSTISR_PEP_0_Pos) /**< (USBHS_HSTISR) Pipe 0 Interrupt Mask */ +#define USBHS_HSTISR_PEP_0(value) (USBHS_HSTISR_PEP_0_Msk & ((value) << USBHS_HSTISR_PEP_0_Pos)) +#define USBHS_HSTISR_PEP_1_Pos _U_(9) /**< (USBHS_HSTISR) Pipe 1 Interrupt Position */ +#define USBHS_HSTISR_PEP_1_Msk (_U_(0x1) << USBHS_HSTISR_PEP_1_Pos) /**< (USBHS_HSTISR) Pipe 1 Interrupt Mask */ +#define USBHS_HSTISR_PEP_1(value) (USBHS_HSTISR_PEP_1_Msk & ((value) << USBHS_HSTISR_PEP_1_Pos)) +#define USBHS_HSTISR_PEP_2_Pos _U_(10) /**< (USBHS_HSTISR) Pipe 2 Interrupt Position */ +#define USBHS_HSTISR_PEP_2_Msk (_U_(0x1) << USBHS_HSTISR_PEP_2_Pos) /**< (USBHS_HSTISR) Pipe 2 Interrupt Mask */ +#define USBHS_HSTISR_PEP_2(value) (USBHS_HSTISR_PEP_2_Msk & ((value) << USBHS_HSTISR_PEP_2_Pos)) +#define USBHS_HSTISR_PEP_3_Pos _U_(11) /**< (USBHS_HSTISR) Pipe 3 Interrupt Position */ +#define USBHS_HSTISR_PEP_3_Msk (_U_(0x1) << USBHS_HSTISR_PEP_3_Pos) /**< (USBHS_HSTISR) Pipe 3 Interrupt Mask */ +#define USBHS_HSTISR_PEP_3(value) (USBHS_HSTISR_PEP_3_Msk & ((value) << USBHS_HSTISR_PEP_3_Pos)) +#define USBHS_HSTISR_PEP_4_Pos _U_(12) /**< (USBHS_HSTISR) Pipe 4 Interrupt Position */ +#define USBHS_HSTISR_PEP_4_Msk (_U_(0x1) << USBHS_HSTISR_PEP_4_Pos) /**< (USBHS_HSTISR) Pipe 4 Interrupt Mask */ +#define USBHS_HSTISR_PEP_4(value) (USBHS_HSTISR_PEP_4_Msk & ((value) << USBHS_HSTISR_PEP_4_Pos)) +#define USBHS_HSTISR_PEP_5_Pos _U_(13) /**< (USBHS_HSTISR) Pipe 5 Interrupt Position */ +#define USBHS_HSTISR_PEP_5_Msk (_U_(0x1) << USBHS_HSTISR_PEP_5_Pos) /**< (USBHS_HSTISR) Pipe 5 Interrupt Mask */ +#define USBHS_HSTISR_PEP_5(value) (USBHS_HSTISR_PEP_5_Msk & ((value) << USBHS_HSTISR_PEP_5_Pos)) +#define USBHS_HSTISR_PEP_6_Pos _U_(14) /**< (USBHS_HSTISR) Pipe 6 Interrupt Position */ +#define USBHS_HSTISR_PEP_6_Msk (_U_(0x1) << USBHS_HSTISR_PEP_6_Pos) /**< (USBHS_HSTISR) Pipe 6 Interrupt Mask */ +#define USBHS_HSTISR_PEP_6(value) (USBHS_HSTISR_PEP_6_Msk & ((value) << USBHS_HSTISR_PEP_6_Pos)) +#define USBHS_HSTISR_PEP_7_Pos _U_(15) /**< (USBHS_HSTISR) Pipe 7 Interrupt Position */ +#define USBHS_HSTISR_PEP_7_Msk (_U_(0x1) << USBHS_HSTISR_PEP_7_Pos) /**< (USBHS_HSTISR) Pipe 7 Interrupt Mask */ +#define USBHS_HSTISR_PEP_7(value) (USBHS_HSTISR_PEP_7_Msk & ((value) << USBHS_HSTISR_PEP_7_Pos)) +#define USBHS_HSTISR_PEP_8_Pos _U_(16) /**< (USBHS_HSTISR) Pipe 8 Interrupt Position */ +#define USBHS_HSTISR_PEP_8_Msk (_U_(0x1) << USBHS_HSTISR_PEP_8_Pos) /**< (USBHS_HSTISR) Pipe 8 Interrupt Mask */ +#define USBHS_HSTISR_PEP_8(value) (USBHS_HSTISR_PEP_8_Msk & ((value) << USBHS_HSTISR_PEP_8_Pos)) +#define USBHS_HSTISR_PEP_9_Pos _U_(17) /**< (USBHS_HSTISR) Pipe 9 Interrupt Position */ +#define USBHS_HSTISR_PEP_9_Msk (_U_(0x1) << USBHS_HSTISR_PEP_9_Pos) /**< (USBHS_HSTISR) Pipe 9 Interrupt Mask */ +#define USBHS_HSTISR_PEP_9(value) (USBHS_HSTISR_PEP_9_Msk & ((value) << USBHS_HSTISR_PEP_9_Pos)) +#define USBHS_HSTISR_PEP_10_Pos _U_(18) /**< (USBHS_HSTISR) Pipe 10 Interrupt Position */ +#define USBHS_HSTISR_PEP_10_Msk (_U_(0x1) << USBHS_HSTISR_PEP_10_Pos) /**< (USBHS_HSTISR) Pipe 10 Interrupt Mask */ +#define USBHS_HSTISR_PEP_10(value) (USBHS_HSTISR_PEP_10_Msk & ((value) << USBHS_HSTISR_PEP_10_Pos)) +#define USBHS_HSTISR_PEP_11_Pos _U_(19) /**< (USBHS_HSTISR) Pipe 11 Interrupt Position */ +#define USBHS_HSTISR_PEP_11_Msk (_U_(0x1) << USBHS_HSTISR_PEP_11_Pos) /**< (USBHS_HSTISR) Pipe 11 Interrupt Mask */ +#define USBHS_HSTISR_PEP_11(value) (USBHS_HSTISR_PEP_11_Msk & ((value) << USBHS_HSTISR_PEP_11_Pos)) +#define USBHS_HSTISR_DMA_1_Pos _U_(25) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Position */ +#define USBHS_HSTISR_DMA_1_Msk (_U_(0x1) << USBHS_HSTISR_DMA_1_Pos) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_HSTISR_DMA_1(value) (USBHS_HSTISR_DMA_1_Msk & ((value) << USBHS_HSTISR_DMA_1_Pos)) +#define USBHS_HSTISR_DMA_2_Pos _U_(26) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Position */ +#define USBHS_HSTISR_DMA_2_Msk (_U_(0x1) << USBHS_HSTISR_DMA_2_Pos) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_HSTISR_DMA_2(value) (USBHS_HSTISR_DMA_2_Msk & ((value) << USBHS_HSTISR_DMA_2_Pos)) +#define USBHS_HSTISR_DMA_3_Pos _U_(27) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Position */ +#define USBHS_HSTISR_DMA_3_Msk (_U_(0x1) << USBHS_HSTISR_DMA_3_Pos) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_HSTISR_DMA_3(value) (USBHS_HSTISR_DMA_3_Msk & ((value) << USBHS_HSTISR_DMA_3_Pos)) +#define USBHS_HSTISR_DMA_4_Pos _U_(28) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Position */ +#define USBHS_HSTISR_DMA_4_Msk (_U_(0x1) << USBHS_HSTISR_DMA_4_Pos) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_HSTISR_DMA_4(value) (USBHS_HSTISR_DMA_4_Msk & ((value) << USBHS_HSTISR_DMA_4_Pos)) +#define USBHS_HSTISR_DMA_5_Pos _U_(29) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Position */ +#define USBHS_HSTISR_DMA_5_Msk (_U_(0x1) << USBHS_HSTISR_DMA_5_Pos) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_HSTISR_DMA_5(value) (USBHS_HSTISR_DMA_5_Msk & ((value) << USBHS_HSTISR_DMA_5_Pos)) +#define USBHS_HSTISR_DMA_6_Pos _U_(30) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Position */ +#define USBHS_HSTISR_DMA_6_Msk (_U_(0x1) << USBHS_HSTISR_DMA_6_Pos) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_HSTISR_DMA_6(value) (USBHS_HSTISR_DMA_6_Msk & ((value) << USBHS_HSTISR_DMA_6_Pos)) +#define USBHS_HSTISR_DMA_7_Pos _U_(31) /**< (USBHS_HSTISR) DMA Channel 7 Interrupt Position */ +#define USBHS_HSTISR_DMA_7_Msk (_U_(0x1) << USBHS_HSTISR_DMA_7_Pos) /**< (USBHS_HSTISR) DMA Channel 7 Interrupt Mask */ +#define USBHS_HSTISR_DMA_7(value) (USBHS_HSTISR_DMA_7_Msk & ((value) << USBHS_HSTISR_DMA_7_Pos)) +#define USBHS_HSTISR_Msk _U_(0xFE0FFF7F) /**< (USBHS_HSTISR) Register Mask */ + +#define USBHS_HSTISR_PEP__Pos _U_(8) /**< (USBHS_HSTISR Position) Pipe x Interrupt */ +#define USBHS_HSTISR_PEP__Msk (_U_(0xFFF) << USBHS_HSTISR_PEP__Pos) /**< (USBHS_HSTISR Mask) PEP_ */ +#define USBHS_HSTISR_PEP_(value) (USBHS_HSTISR_PEP__Msk & ((value) << USBHS_HSTISR_PEP__Pos)) +#define USBHS_HSTISR_DMA__Pos _U_(25) /**< (USBHS_HSTISR Position) DMA Channel 7 Interrupt */ +#define USBHS_HSTISR_DMA__Msk (_U_(0x7F) << USBHS_HSTISR_DMA__Pos) /**< (USBHS_HSTISR Mask) DMA_ */ +#define USBHS_HSTISR_DMA_(value) (USBHS_HSTISR_DMA__Msk & ((value) << USBHS_HSTISR_DMA__Pos)) + +/* -------- USBHS_HSTICR : (USBHS Offset: 0x408) ( /W 32) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC_Pos _U_(0) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Position */ +#define USBHS_HSTICR_DCONNIC_Msk (_U_(0x1) << USBHS_HSTICR_DCONNIC_Pos) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Mask */ +#define USBHS_HSTICR_DCONNIC(value) (USBHS_HSTICR_DCONNIC_Msk & ((value) << USBHS_HSTICR_DCONNIC_Pos)) +#define USBHS_HSTICR_DDISCIC_Pos _U_(1) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Position */ +#define USBHS_HSTICR_DDISCIC_Msk (_U_(0x1) << USBHS_HSTICR_DDISCIC_Pos) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Mask */ +#define USBHS_HSTICR_DDISCIC(value) (USBHS_HSTICR_DDISCIC_Msk & ((value) << USBHS_HSTICR_DDISCIC_Pos)) +#define USBHS_HSTICR_RSTIC_Pos _U_(2) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSTIC_Msk (_U_(0x1) << USBHS_HSTICR_RSTIC_Pos) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSTIC(value) (USBHS_HSTICR_RSTIC_Msk & ((value) << USBHS_HSTICR_RSTIC_Pos)) +#define USBHS_HSTICR_RSMEDIC_Pos _U_(3) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSMEDIC_Msk (_U_(0x1) << USBHS_HSTICR_RSMEDIC_Pos) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSMEDIC(value) (USBHS_HSTICR_RSMEDIC_Msk & ((value) << USBHS_HSTICR_RSMEDIC_Pos)) +#define USBHS_HSTICR_RXRSMIC_Pos _U_(4) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Position */ +#define USBHS_HSTICR_RXRSMIC_Msk (_U_(0x1) << USBHS_HSTICR_RXRSMIC_Pos) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Mask */ +#define USBHS_HSTICR_RXRSMIC(value) (USBHS_HSTICR_RXRSMIC_Msk & ((value) << USBHS_HSTICR_RXRSMIC_Pos)) +#define USBHS_HSTICR_HSOFIC_Pos _U_(5) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Position */ +#define USBHS_HSTICR_HSOFIC_Msk (_U_(0x1) << USBHS_HSTICR_HSOFIC_Pos) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Mask */ +#define USBHS_HSTICR_HSOFIC(value) (USBHS_HSTICR_HSOFIC_Msk & ((value) << USBHS_HSTICR_HSOFIC_Pos)) +#define USBHS_HSTICR_HWUPIC_Pos _U_(6) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Position */ +#define USBHS_HSTICR_HWUPIC_Msk (_U_(0x1) << USBHS_HSTICR_HWUPIC_Pos) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Mask */ +#define USBHS_HSTICR_HWUPIC(value) (USBHS_HSTICR_HWUPIC_Msk & ((value) << USBHS_HSTICR_HWUPIC_Pos)) +#define USBHS_HSTICR_Msk _U_(0x0000007F) /**< (USBHS_HSTICR) Register Mask */ + + +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x40C) ( /W 32) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS_Pos _U_(0) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Position */ +#define USBHS_HSTIFR_DCONNIS_Msk (_U_(0x1) << USBHS_HSTIFR_DCONNIS_Pos) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Mask */ +#define USBHS_HSTIFR_DCONNIS(value) (USBHS_HSTIFR_DCONNIS_Msk & ((value) << USBHS_HSTIFR_DCONNIS_Pos)) +#define USBHS_HSTIFR_DDISCIS_Pos _U_(1) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Position */ +#define USBHS_HSTIFR_DDISCIS_Msk (_U_(0x1) << USBHS_HSTIFR_DDISCIS_Pos) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Mask */ +#define USBHS_HSTIFR_DDISCIS(value) (USBHS_HSTIFR_DDISCIS_Msk & ((value) << USBHS_HSTIFR_DDISCIS_Pos)) +#define USBHS_HSTIFR_RSTIS_Pos _U_(2) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSTIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSTIS_Pos) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSTIS(value) (USBHS_HSTIFR_RSTIS_Msk & ((value) << USBHS_HSTIFR_RSTIS_Pos)) +#define USBHS_HSTIFR_RSMEDIS_Pos _U_(3) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSMEDIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSMEDIS_Pos) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSMEDIS(value) (USBHS_HSTIFR_RSMEDIS_Msk & ((value) << USBHS_HSTIFR_RSMEDIS_Pos)) +#define USBHS_HSTIFR_RXRSMIS_Pos _U_(4) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Position */ +#define USBHS_HSTIFR_RXRSMIS_Msk (_U_(0x1) << USBHS_HSTIFR_RXRSMIS_Pos) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Mask */ +#define USBHS_HSTIFR_RXRSMIS(value) (USBHS_HSTIFR_RXRSMIS_Msk & ((value) << USBHS_HSTIFR_RXRSMIS_Pos)) +#define USBHS_HSTIFR_HSOFIS_Pos _U_(5) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Position */ +#define USBHS_HSTIFR_HSOFIS_Msk (_U_(0x1) << USBHS_HSTIFR_HSOFIS_Pos) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Mask */ +#define USBHS_HSTIFR_HSOFIS(value) (USBHS_HSTIFR_HSOFIS_Msk & ((value) << USBHS_HSTIFR_HSOFIS_Pos)) +#define USBHS_HSTIFR_HWUPIS_Pos _U_(6) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Position */ +#define USBHS_HSTIFR_HWUPIS_Msk (_U_(0x1) << USBHS_HSTIFR_HWUPIS_Pos) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Mask */ +#define USBHS_HSTIFR_HWUPIS(value) (USBHS_HSTIFR_HWUPIS_Msk & ((value) << USBHS_HSTIFR_HWUPIS_Pos)) +#define USBHS_HSTIFR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_1_Pos) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_1(value) (USBHS_HSTIFR_DMA_1_Msk & ((value) << USBHS_HSTIFR_DMA_1_Pos)) +#define USBHS_HSTIFR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_2_Pos) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_2(value) (USBHS_HSTIFR_DMA_2_Msk & ((value) << USBHS_HSTIFR_DMA_2_Pos)) +#define USBHS_HSTIFR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_3_Pos) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_3(value) (USBHS_HSTIFR_DMA_3_Msk & ((value) << USBHS_HSTIFR_DMA_3_Pos)) +#define USBHS_HSTIFR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_4_Pos) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_4(value) (USBHS_HSTIFR_DMA_4_Msk & ((value) << USBHS_HSTIFR_DMA_4_Pos)) +#define USBHS_HSTIFR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_5_Pos) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_5(value) (USBHS_HSTIFR_DMA_5_Msk & ((value) << USBHS_HSTIFR_DMA_5_Pos)) +#define USBHS_HSTIFR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_6_Pos) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_6(value) (USBHS_HSTIFR_DMA_6_Msk & ((value) << USBHS_HSTIFR_DMA_6_Pos)) +#define USBHS_HSTIFR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIFR) DMA Channel 7 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_7_Pos) /**< (USBHS_HSTIFR) DMA Channel 7 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_7(value) (USBHS_HSTIFR_DMA_7_Msk & ((value) << USBHS_HSTIFR_DMA_7_Pos)) +#define USBHS_HSTIFR_Msk _U_(0xFE00007F) /**< (USBHS_HSTIFR) Register Mask */ + +#define USBHS_HSTIFR_DMA__Pos _U_(25) /**< (USBHS_HSTIFR Position) DMA Channel 7 Interrupt Set */ +#define USBHS_HSTIFR_DMA__Msk (_U_(0x7F) << USBHS_HSTIFR_DMA__Pos) /**< (USBHS_HSTIFR Mask) DMA_ */ +#define USBHS_HSTIFR_DMA_(value) (USBHS_HSTIFR_DMA__Msk & ((value) << USBHS_HSTIFR_DMA__Pos)) + +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x410) ( R/ 32) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE_Pos _U_(0) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIMR_DCONNIE_Msk (_U_(0x1) << USBHS_HSTIMR_DCONNIE_Pos) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DCONNIE(value) (USBHS_HSTIMR_DCONNIE_Msk & ((value) << USBHS_HSTIMR_DCONNIE_Pos)) +#define USBHS_HSTIMR_DDISCIE_Pos _U_(1) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIMR_DDISCIE_Msk (_U_(0x1) << USBHS_HSTIMR_DDISCIE_Pos) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DDISCIE(value) (USBHS_HSTIMR_DDISCIE_Msk & ((value) << USBHS_HSTIMR_DDISCIE_Pos)) +#define USBHS_HSTIMR_RSTIE_Pos _U_(2) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSTIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSTIE_Pos) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSTIE(value) (USBHS_HSTIMR_RSTIE_Msk & ((value) << USBHS_HSTIMR_RSTIE_Pos)) +#define USBHS_HSTIMR_RSMEDIE_Pos _U_(3) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSMEDIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSMEDIE_Pos) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSMEDIE(value) (USBHS_HSTIMR_RSMEDIE_Msk & ((value) << USBHS_HSTIMR_RSMEDIE_Pos)) +#define USBHS_HSTIMR_RXRSMIE_Pos _U_(4) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIMR_RXRSMIE_Msk (_U_(0x1) << USBHS_HSTIMR_RXRSMIE_Pos) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIMR_RXRSMIE(value) (USBHS_HSTIMR_RXRSMIE_Msk & ((value) << USBHS_HSTIMR_RXRSMIE_Pos)) +#define USBHS_HSTIMR_HSOFIE_Pos _U_(5) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIMR_HSOFIE_Msk (_U_(0x1) << USBHS_HSTIMR_HSOFIE_Pos) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIMR_HSOFIE(value) (USBHS_HSTIMR_HSOFIE_Msk & ((value) << USBHS_HSTIMR_HSOFIE_Pos)) +#define USBHS_HSTIMR_HWUPIE_Pos _U_(6) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIMR_HWUPIE_Msk (_U_(0x1) << USBHS_HSTIMR_HWUPIE_Pos) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIMR_HWUPIE(value) (USBHS_HSTIMR_HWUPIE_Msk & ((value) << USBHS_HSTIMR_HWUPIE_Pos)) +#define USBHS_HSTIMR_PEP_0_Pos _U_(8) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_0_Pos) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_0(value) (USBHS_HSTIMR_PEP_0_Msk & ((value) << USBHS_HSTIMR_PEP_0_Pos)) +#define USBHS_HSTIMR_PEP_1_Pos _U_(9) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_1_Pos) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_1(value) (USBHS_HSTIMR_PEP_1_Msk & ((value) << USBHS_HSTIMR_PEP_1_Pos)) +#define USBHS_HSTIMR_PEP_2_Pos _U_(10) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_2_Pos) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_2(value) (USBHS_HSTIMR_PEP_2_Msk & ((value) << USBHS_HSTIMR_PEP_2_Pos)) +#define USBHS_HSTIMR_PEP_3_Pos _U_(11) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_3_Pos) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_3(value) (USBHS_HSTIMR_PEP_3_Msk & ((value) << USBHS_HSTIMR_PEP_3_Pos)) +#define USBHS_HSTIMR_PEP_4_Pos _U_(12) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_4_Pos) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_4(value) (USBHS_HSTIMR_PEP_4_Msk & ((value) << USBHS_HSTIMR_PEP_4_Pos)) +#define USBHS_HSTIMR_PEP_5_Pos _U_(13) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_5_Pos) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_5(value) (USBHS_HSTIMR_PEP_5_Msk & ((value) << USBHS_HSTIMR_PEP_5_Pos)) +#define USBHS_HSTIMR_PEP_6_Pos _U_(14) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_6_Pos) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_6(value) (USBHS_HSTIMR_PEP_6_Msk & ((value) << USBHS_HSTIMR_PEP_6_Pos)) +#define USBHS_HSTIMR_PEP_7_Pos _U_(15) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_7_Pos) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_7(value) (USBHS_HSTIMR_PEP_7_Msk & ((value) << USBHS_HSTIMR_PEP_7_Pos)) +#define USBHS_HSTIMR_PEP_8_Pos _U_(16) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_8_Pos) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_8(value) (USBHS_HSTIMR_PEP_8_Msk & ((value) << USBHS_HSTIMR_PEP_8_Pos)) +#define USBHS_HSTIMR_PEP_9_Pos _U_(17) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_9_Pos) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_9(value) (USBHS_HSTIMR_PEP_9_Msk & ((value) << USBHS_HSTIMR_PEP_9_Pos)) +#define USBHS_HSTIMR_PEP_10_Pos _U_(18) /**< (USBHS_HSTIMR) Pipe 10 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_10_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_10_Pos) /**< (USBHS_HSTIMR) Pipe 10 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_10(value) (USBHS_HSTIMR_PEP_10_Msk & ((value) << USBHS_HSTIMR_PEP_10_Pos)) +#define USBHS_HSTIMR_PEP_11_Pos _U_(19) /**< (USBHS_HSTIMR) Pipe 11 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_11_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_11_Pos) /**< (USBHS_HSTIMR) Pipe 11 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_11(value) (USBHS_HSTIMR_PEP_11_Msk & ((value) << USBHS_HSTIMR_PEP_11_Pos)) +#define USBHS_HSTIMR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_1_Pos) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_1(value) (USBHS_HSTIMR_DMA_1_Msk & ((value) << USBHS_HSTIMR_DMA_1_Pos)) +#define USBHS_HSTIMR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_2_Pos) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_2(value) (USBHS_HSTIMR_DMA_2_Msk & ((value) << USBHS_HSTIMR_DMA_2_Pos)) +#define USBHS_HSTIMR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_3_Pos) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_3(value) (USBHS_HSTIMR_DMA_3_Msk & ((value) << USBHS_HSTIMR_DMA_3_Pos)) +#define USBHS_HSTIMR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_4_Pos) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_4(value) (USBHS_HSTIMR_DMA_4_Msk & ((value) << USBHS_HSTIMR_DMA_4_Pos)) +#define USBHS_HSTIMR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_5_Pos) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_5(value) (USBHS_HSTIMR_DMA_5_Msk & ((value) << USBHS_HSTIMR_DMA_5_Pos)) +#define USBHS_HSTIMR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_6_Pos) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_6(value) (USBHS_HSTIMR_DMA_6_Msk & ((value) << USBHS_HSTIMR_DMA_6_Pos)) +#define USBHS_HSTIMR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_7_Pos) /**< (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_7(value) (USBHS_HSTIMR_DMA_7_Msk & ((value) << USBHS_HSTIMR_DMA_7_Pos)) +#define USBHS_HSTIMR_Msk _U_(0xFE0FFF7F) /**< (USBHS_HSTIMR) Register Mask */ + +#define USBHS_HSTIMR_PEP__Pos _U_(8) /**< (USBHS_HSTIMR Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIMR_PEP__Msk (_U_(0xFFF) << USBHS_HSTIMR_PEP__Pos) /**< (USBHS_HSTIMR Mask) PEP_ */ +#define USBHS_HSTIMR_PEP_(value) (USBHS_HSTIMR_PEP__Msk & ((value) << USBHS_HSTIMR_PEP__Pos)) +#define USBHS_HSTIMR_DMA__Pos _U_(25) /**< (USBHS_HSTIMR Position) DMA Channel 7 Interrupt Enable */ +#define USBHS_HSTIMR_DMA__Msk (_U_(0x7F) << USBHS_HSTIMR_DMA__Pos) /**< (USBHS_HSTIMR Mask) DMA_ */ +#define USBHS_HSTIMR_DMA_(value) (USBHS_HSTIMR_DMA__Msk & ((value) << USBHS_HSTIMR_DMA__Pos)) + +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x414) ( /W 32) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC_Pos _U_(0) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Position */ +#define USBHS_HSTIDR_DCONNIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DCONNIEC_Pos) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DCONNIEC(value) (USBHS_HSTIDR_DCONNIEC_Msk & ((value) << USBHS_HSTIDR_DCONNIEC_Pos)) +#define USBHS_HSTIDR_DDISCIEC_Pos _U_(1) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Position */ +#define USBHS_HSTIDR_DDISCIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DDISCIEC_Pos) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DDISCIEC(value) (USBHS_HSTIDR_DDISCIEC_Msk & ((value) << USBHS_HSTIDR_DDISCIEC_Pos)) +#define USBHS_HSTIDR_RSTIEC_Pos _U_(2) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSTIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSTIEC_Pos) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSTIEC(value) (USBHS_HSTIDR_RSTIEC_Msk & ((value) << USBHS_HSTIDR_RSTIEC_Pos)) +#define USBHS_HSTIDR_RSMEDIEC_Pos _U_(3) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSMEDIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSMEDIEC_Pos) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSMEDIEC(value) (USBHS_HSTIDR_RSMEDIEC_Msk & ((value) << USBHS_HSTIDR_RSMEDIEC_Pos)) +#define USBHS_HSTIDR_RXRSMIEC_Pos _U_(4) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Position */ +#define USBHS_HSTIDR_RXRSMIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RXRSMIEC_Pos) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Mask */ +#define USBHS_HSTIDR_RXRSMIEC(value) (USBHS_HSTIDR_RXRSMIEC_Msk & ((value) << USBHS_HSTIDR_RXRSMIEC_Pos)) +#define USBHS_HSTIDR_HSOFIEC_Pos _U_(5) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Position */ +#define USBHS_HSTIDR_HSOFIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HSOFIEC_Pos) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Mask */ +#define USBHS_HSTIDR_HSOFIEC(value) (USBHS_HSTIDR_HSOFIEC_Msk & ((value) << USBHS_HSTIDR_HSOFIEC_Pos)) +#define USBHS_HSTIDR_HWUPIEC_Pos _U_(6) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Position */ +#define USBHS_HSTIDR_HWUPIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HWUPIEC_Pos) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Mask */ +#define USBHS_HSTIDR_HWUPIEC(value) (USBHS_HSTIDR_HWUPIEC_Msk & ((value) << USBHS_HSTIDR_HWUPIEC_Pos)) +#define USBHS_HSTIDR_PEP_0_Pos _U_(8) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_0_Pos) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_0(value) (USBHS_HSTIDR_PEP_0_Msk & ((value) << USBHS_HSTIDR_PEP_0_Pos)) +#define USBHS_HSTIDR_PEP_1_Pos _U_(9) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_1_Pos) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_1(value) (USBHS_HSTIDR_PEP_1_Msk & ((value) << USBHS_HSTIDR_PEP_1_Pos)) +#define USBHS_HSTIDR_PEP_2_Pos _U_(10) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_2_Pos) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_2(value) (USBHS_HSTIDR_PEP_2_Msk & ((value) << USBHS_HSTIDR_PEP_2_Pos)) +#define USBHS_HSTIDR_PEP_3_Pos _U_(11) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_3_Pos) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_3(value) (USBHS_HSTIDR_PEP_3_Msk & ((value) << USBHS_HSTIDR_PEP_3_Pos)) +#define USBHS_HSTIDR_PEP_4_Pos _U_(12) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_4_Pos) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_4(value) (USBHS_HSTIDR_PEP_4_Msk & ((value) << USBHS_HSTIDR_PEP_4_Pos)) +#define USBHS_HSTIDR_PEP_5_Pos _U_(13) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_5_Pos) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_5(value) (USBHS_HSTIDR_PEP_5_Msk & ((value) << USBHS_HSTIDR_PEP_5_Pos)) +#define USBHS_HSTIDR_PEP_6_Pos _U_(14) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_6_Pos) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_6(value) (USBHS_HSTIDR_PEP_6_Msk & ((value) << USBHS_HSTIDR_PEP_6_Pos)) +#define USBHS_HSTIDR_PEP_7_Pos _U_(15) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_7_Pos) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_7(value) (USBHS_HSTIDR_PEP_7_Msk & ((value) << USBHS_HSTIDR_PEP_7_Pos)) +#define USBHS_HSTIDR_PEP_8_Pos _U_(16) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_8_Pos) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_8(value) (USBHS_HSTIDR_PEP_8_Msk & ((value) << USBHS_HSTIDR_PEP_8_Pos)) +#define USBHS_HSTIDR_PEP_9_Pos _U_(17) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_9_Pos) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_9(value) (USBHS_HSTIDR_PEP_9_Msk & ((value) << USBHS_HSTIDR_PEP_9_Pos)) +#define USBHS_HSTIDR_PEP_10_Pos _U_(18) /**< (USBHS_HSTIDR) Pipe 10 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_10_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_10_Pos) /**< (USBHS_HSTIDR) Pipe 10 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_10(value) (USBHS_HSTIDR_PEP_10_Msk & ((value) << USBHS_HSTIDR_PEP_10_Pos)) +#define USBHS_HSTIDR_PEP_11_Pos _U_(19) /**< (USBHS_HSTIDR) Pipe 11 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_11_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_11_Pos) /**< (USBHS_HSTIDR) Pipe 11 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_11(value) (USBHS_HSTIDR_PEP_11_Msk & ((value) << USBHS_HSTIDR_PEP_11_Pos)) +#define USBHS_HSTIDR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_1_Pos) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_1(value) (USBHS_HSTIDR_DMA_1_Msk & ((value) << USBHS_HSTIDR_DMA_1_Pos)) +#define USBHS_HSTIDR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_2_Pos) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_2(value) (USBHS_HSTIDR_DMA_2_Msk & ((value) << USBHS_HSTIDR_DMA_2_Pos)) +#define USBHS_HSTIDR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_3_Pos) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_3(value) (USBHS_HSTIDR_DMA_3_Msk & ((value) << USBHS_HSTIDR_DMA_3_Pos)) +#define USBHS_HSTIDR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_4_Pos) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_4(value) (USBHS_HSTIDR_DMA_4_Msk & ((value) << USBHS_HSTIDR_DMA_4_Pos)) +#define USBHS_HSTIDR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_5_Pos) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_5(value) (USBHS_HSTIDR_DMA_5_Msk & ((value) << USBHS_HSTIDR_DMA_5_Pos)) +#define USBHS_HSTIDR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_6_Pos) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_6(value) (USBHS_HSTIDR_DMA_6_Msk & ((value) << USBHS_HSTIDR_DMA_6_Pos)) +#define USBHS_HSTIDR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_7_Pos) /**< (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_7(value) (USBHS_HSTIDR_DMA_7_Msk & ((value) << USBHS_HSTIDR_DMA_7_Pos)) +#define USBHS_HSTIDR_Msk _U_(0xFE0FFF7F) /**< (USBHS_HSTIDR) Register Mask */ + +#define USBHS_HSTIDR_PEP__Pos _U_(8) /**< (USBHS_HSTIDR Position) Pipe x Interrupt Disable */ +#define USBHS_HSTIDR_PEP__Msk (_U_(0xFFF) << USBHS_HSTIDR_PEP__Pos) /**< (USBHS_HSTIDR Mask) PEP_ */ +#define USBHS_HSTIDR_PEP_(value) (USBHS_HSTIDR_PEP__Msk & ((value) << USBHS_HSTIDR_PEP__Pos)) +#define USBHS_HSTIDR_DMA__Pos _U_(25) /**< (USBHS_HSTIDR Position) DMA Channel 7 Interrupt Disable */ +#define USBHS_HSTIDR_DMA__Msk (_U_(0x7F) << USBHS_HSTIDR_DMA__Pos) /**< (USBHS_HSTIDR Mask) DMA_ */ +#define USBHS_HSTIDR_DMA_(value) (USBHS_HSTIDR_DMA__Msk & ((value) << USBHS_HSTIDR_DMA__Pos)) + +/* -------- USBHS_HSTIER : (USBHS Offset: 0x418) ( /W 32) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES_Pos _U_(0) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIER_DCONNIES_Msk (_U_(0x1) << USBHS_HSTIER_DCONNIES_Pos) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIER_DCONNIES(value) (USBHS_HSTIER_DCONNIES_Msk & ((value) << USBHS_HSTIER_DCONNIES_Pos)) +#define USBHS_HSTIER_DDISCIES_Pos _U_(1) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIER_DDISCIES_Msk (_U_(0x1) << USBHS_HSTIER_DDISCIES_Pos) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIER_DDISCIES(value) (USBHS_HSTIER_DDISCIES_Msk & ((value) << USBHS_HSTIER_DDISCIES_Pos)) +#define USBHS_HSTIER_RSTIES_Pos _U_(2) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSTIES_Msk (_U_(0x1) << USBHS_HSTIER_RSTIES_Pos) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSTIES(value) (USBHS_HSTIER_RSTIES_Msk & ((value) << USBHS_HSTIER_RSTIES_Pos)) +#define USBHS_HSTIER_RSMEDIES_Pos _U_(3) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSMEDIES_Msk (_U_(0x1) << USBHS_HSTIER_RSMEDIES_Pos) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSMEDIES(value) (USBHS_HSTIER_RSMEDIES_Msk & ((value) << USBHS_HSTIER_RSMEDIES_Pos)) +#define USBHS_HSTIER_RXRSMIES_Pos _U_(4) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIER_RXRSMIES_Msk (_U_(0x1) << USBHS_HSTIER_RXRSMIES_Pos) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIER_RXRSMIES(value) (USBHS_HSTIER_RXRSMIES_Msk & ((value) << USBHS_HSTIER_RXRSMIES_Pos)) +#define USBHS_HSTIER_HSOFIES_Pos _U_(5) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIER_HSOFIES_Msk (_U_(0x1) << USBHS_HSTIER_HSOFIES_Pos) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIER_HSOFIES(value) (USBHS_HSTIER_HSOFIES_Msk & ((value) << USBHS_HSTIER_HSOFIES_Pos)) +#define USBHS_HSTIER_HWUPIES_Pos _U_(6) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIER_HWUPIES_Msk (_U_(0x1) << USBHS_HSTIER_HWUPIES_Pos) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIER_HWUPIES(value) (USBHS_HSTIER_HWUPIES_Msk & ((value) << USBHS_HSTIER_HWUPIES_Pos)) +#define USBHS_HSTIER_PEP_0_Pos _U_(8) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_0_Msk (_U_(0x1) << USBHS_HSTIER_PEP_0_Pos) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_0(value) (USBHS_HSTIER_PEP_0_Msk & ((value) << USBHS_HSTIER_PEP_0_Pos)) +#define USBHS_HSTIER_PEP_1_Pos _U_(9) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_1_Msk (_U_(0x1) << USBHS_HSTIER_PEP_1_Pos) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_1(value) (USBHS_HSTIER_PEP_1_Msk & ((value) << USBHS_HSTIER_PEP_1_Pos)) +#define USBHS_HSTIER_PEP_2_Pos _U_(10) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_2_Msk (_U_(0x1) << USBHS_HSTIER_PEP_2_Pos) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_2(value) (USBHS_HSTIER_PEP_2_Msk & ((value) << USBHS_HSTIER_PEP_2_Pos)) +#define USBHS_HSTIER_PEP_3_Pos _U_(11) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_3_Msk (_U_(0x1) << USBHS_HSTIER_PEP_3_Pos) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_3(value) (USBHS_HSTIER_PEP_3_Msk & ((value) << USBHS_HSTIER_PEP_3_Pos)) +#define USBHS_HSTIER_PEP_4_Pos _U_(12) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_4_Msk (_U_(0x1) << USBHS_HSTIER_PEP_4_Pos) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_4(value) (USBHS_HSTIER_PEP_4_Msk & ((value) << USBHS_HSTIER_PEP_4_Pos)) +#define USBHS_HSTIER_PEP_5_Pos _U_(13) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_5_Msk (_U_(0x1) << USBHS_HSTIER_PEP_5_Pos) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_5(value) (USBHS_HSTIER_PEP_5_Msk & ((value) << USBHS_HSTIER_PEP_5_Pos)) +#define USBHS_HSTIER_PEP_6_Pos _U_(14) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_6_Msk (_U_(0x1) << USBHS_HSTIER_PEP_6_Pos) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_6(value) (USBHS_HSTIER_PEP_6_Msk & ((value) << USBHS_HSTIER_PEP_6_Pos)) +#define USBHS_HSTIER_PEP_7_Pos _U_(15) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_7_Msk (_U_(0x1) << USBHS_HSTIER_PEP_7_Pos) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_7(value) (USBHS_HSTIER_PEP_7_Msk & ((value) << USBHS_HSTIER_PEP_7_Pos)) +#define USBHS_HSTIER_PEP_8_Pos _U_(16) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_8_Msk (_U_(0x1) << USBHS_HSTIER_PEP_8_Pos) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_8(value) (USBHS_HSTIER_PEP_8_Msk & ((value) << USBHS_HSTIER_PEP_8_Pos)) +#define USBHS_HSTIER_PEP_9_Pos _U_(17) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_9_Msk (_U_(0x1) << USBHS_HSTIER_PEP_9_Pos) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_9(value) (USBHS_HSTIER_PEP_9_Msk & ((value) << USBHS_HSTIER_PEP_9_Pos)) +#define USBHS_HSTIER_PEP_10_Pos _U_(18) /**< (USBHS_HSTIER) Pipe 10 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_10_Msk (_U_(0x1) << USBHS_HSTIER_PEP_10_Pos) /**< (USBHS_HSTIER) Pipe 10 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_10(value) (USBHS_HSTIER_PEP_10_Msk & ((value) << USBHS_HSTIER_PEP_10_Pos)) +#define USBHS_HSTIER_PEP_11_Pos _U_(19) /**< (USBHS_HSTIER) Pipe 11 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_11_Msk (_U_(0x1) << USBHS_HSTIER_PEP_11_Pos) /**< (USBHS_HSTIER) Pipe 11 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_11(value) (USBHS_HSTIER_PEP_11_Msk & ((value) << USBHS_HSTIER_PEP_11_Pos)) +#define USBHS_HSTIER_DMA_1_Pos _U_(25) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_1_Msk (_U_(0x1) << USBHS_HSTIER_DMA_1_Pos) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_1(value) (USBHS_HSTIER_DMA_1_Msk & ((value) << USBHS_HSTIER_DMA_1_Pos)) +#define USBHS_HSTIER_DMA_2_Pos _U_(26) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_2_Msk (_U_(0x1) << USBHS_HSTIER_DMA_2_Pos) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_2(value) (USBHS_HSTIER_DMA_2_Msk & ((value) << USBHS_HSTIER_DMA_2_Pos)) +#define USBHS_HSTIER_DMA_3_Pos _U_(27) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_3_Msk (_U_(0x1) << USBHS_HSTIER_DMA_3_Pos) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_3(value) (USBHS_HSTIER_DMA_3_Msk & ((value) << USBHS_HSTIER_DMA_3_Pos)) +#define USBHS_HSTIER_DMA_4_Pos _U_(28) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_4_Msk (_U_(0x1) << USBHS_HSTIER_DMA_4_Pos) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_4(value) (USBHS_HSTIER_DMA_4_Msk & ((value) << USBHS_HSTIER_DMA_4_Pos)) +#define USBHS_HSTIER_DMA_5_Pos _U_(29) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_5_Msk (_U_(0x1) << USBHS_HSTIER_DMA_5_Pos) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_5(value) (USBHS_HSTIER_DMA_5_Msk & ((value) << USBHS_HSTIER_DMA_5_Pos)) +#define USBHS_HSTIER_DMA_6_Pos _U_(30) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_6_Msk (_U_(0x1) << USBHS_HSTIER_DMA_6_Pos) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_6(value) (USBHS_HSTIER_DMA_6_Msk & ((value) << USBHS_HSTIER_DMA_6_Pos)) +#define USBHS_HSTIER_DMA_7_Pos _U_(31) /**< (USBHS_HSTIER) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_7_Msk (_U_(0x1) << USBHS_HSTIER_DMA_7_Pos) /**< (USBHS_HSTIER) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_7(value) (USBHS_HSTIER_DMA_7_Msk & ((value) << USBHS_HSTIER_DMA_7_Pos)) +#define USBHS_HSTIER_Msk _U_(0xFE0FFF7F) /**< (USBHS_HSTIER) Register Mask */ + +#define USBHS_HSTIER_PEP__Pos _U_(8) /**< (USBHS_HSTIER Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIER_PEP__Msk (_U_(0xFFF) << USBHS_HSTIER_PEP__Pos) /**< (USBHS_HSTIER Mask) PEP_ */ +#define USBHS_HSTIER_PEP_(value) (USBHS_HSTIER_PEP__Msk & ((value) << USBHS_HSTIER_PEP__Pos)) +#define USBHS_HSTIER_DMA__Pos _U_(25) /**< (USBHS_HSTIER Position) DMA Channel 7 Interrupt Enable */ +#define USBHS_HSTIER_DMA__Msk (_U_(0x7F) << USBHS_HSTIER_DMA__Pos) /**< (USBHS_HSTIER Mask) DMA_ */ +#define USBHS_HSTIER_DMA_(value) (USBHS_HSTIER_DMA__Msk & ((value) << USBHS_HSTIER_DMA__Pos)) + +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x41C) (R/W 32) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0_Pos _U_(0) /**< (USBHS_HSTPIP) Pipe 0 Enable Position */ +#define USBHS_HSTPIP_PEN0_Msk (_U_(0x1) << USBHS_HSTPIP_PEN0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Enable Mask */ +#define USBHS_HSTPIP_PEN0(value) (USBHS_HSTPIP_PEN0_Msk & ((value) << USBHS_HSTPIP_PEN0_Pos)) +#define USBHS_HSTPIP_PEN1_Pos _U_(1) /**< (USBHS_HSTPIP) Pipe 1 Enable Position */ +#define USBHS_HSTPIP_PEN1_Msk (_U_(0x1) << USBHS_HSTPIP_PEN1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Enable Mask */ +#define USBHS_HSTPIP_PEN1(value) (USBHS_HSTPIP_PEN1_Msk & ((value) << USBHS_HSTPIP_PEN1_Pos)) +#define USBHS_HSTPIP_PEN2_Pos _U_(2) /**< (USBHS_HSTPIP) Pipe 2 Enable Position */ +#define USBHS_HSTPIP_PEN2_Msk (_U_(0x1) << USBHS_HSTPIP_PEN2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Enable Mask */ +#define USBHS_HSTPIP_PEN2(value) (USBHS_HSTPIP_PEN2_Msk & ((value) << USBHS_HSTPIP_PEN2_Pos)) +#define USBHS_HSTPIP_PEN3_Pos _U_(3) /**< (USBHS_HSTPIP) Pipe 3 Enable Position */ +#define USBHS_HSTPIP_PEN3_Msk (_U_(0x1) << USBHS_HSTPIP_PEN3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Enable Mask */ +#define USBHS_HSTPIP_PEN3(value) (USBHS_HSTPIP_PEN3_Msk & ((value) << USBHS_HSTPIP_PEN3_Pos)) +#define USBHS_HSTPIP_PEN4_Pos _U_(4) /**< (USBHS_HSTPIP) Pipe 4 Enable Position */ +#define USBHS_HSTPIP_PEN4_Msk (_U_(0x1) << USBHS_HSTPIP_PEN4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Enable Mask */ +#define USBHS_HSTPIP_PEN4(value) (USBHS_HSTPIP_PEN4_Msk & ((value) << USBHS_HSTPIP_PEN4_Pos)) +#define USBHS_HSTPIP_PEN5_Pos _U_(5) /**< (USBHS_HSTPIP) Pipe 5 Enable Position */ +#define USBHS_HSTPIP_PEN5_Msk (_U_(0x1) << USBHS_HSTPIP_PEN5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Enable Mask */ +#define USBHS_HSTPIP_PEN5(value) (USBHS_HSTPIP_PEN5_Msk & ((value) << USBHS_HSTPIP_PEN5_Pos)) +#define USBHS_HSTPIP_PEN6_Pos _U_(6) /**< (USBHS_HSTPIP) Pipe 6 Enable Position */ +#define USBHS_HSTPIP_PEN6_Msk (_U_(0x1) << USBHS_HSTPIP_PEN6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Enable Mask */ +#define USBHS_HSTPIP_PEN6(value) (USBHS_HSTPIP_PEN6_Msk & ((value) << USBHS_HSTPIP_PEN6_Pos)) +#define USBHS_HSTPIP_PEN7_Pos _U_(7) /**< (USBHS_HSTPIP) Pipe 7 Enable Position */ +#define USBHS_HSTPIP_PEN7_Msk (_U_(0x1) << USBHS_HSTPIP_PEN7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Enable Mask */ +#define USBHS_HSTPIP_PEN7(value) (USBHS_HSTPIP_PEN7_Msk & ((value) << USBHS_HSTPIP_PEN7_Pos)) +#define USBHS_HSTPIP_PEN8_Pos _U_(8) /**< (USBHS_HSTPIP) Pipe 8 Enable Position */ +#define USBHS_HSTPIP_PEN8_Msk (_U_(0x1) << USBHS_HSTPIP_PEN8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Enable Mask */ +#define USBHS_HSTPIP_PEN8(value) (USBHS_HSTPIP_PEN8_Msk & ((value) << USBHS_HSTPIP_PEN8_Pos)) +#define USBHS_HSTPIP_PRST0_Pos _U_(16) /**< (USBHS_HSTPIP) Pipe 0 Reset Position */ +#define USBHS_HSTPIP_PRST0_Msk (_U_(0x1) << USBHS_HSTPIP_PRST0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Reset Mask */ +#define USBHS_HSTPIP_PRST0(value) (USBHS_HSTPIP_PRST0_Msk & ((value) << USBHS_HSTPIP_PRST0_Pos)) +#define USBHS_HSTPIP_PRST1_Pos _U_(17) /**< (USBHS_HSTPIP) Pipe 1 Reset Position */ +#define USBHS_HSTPIP_PRST1_Msk (_U_(0x1) << USBHS_HSTPIP_PRST1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Reset Mask */ +#define USBHS_HSTPIP_PRST1(value) (USBHS_HSTPIP_PRST1_Msk & ((value) << USBHS_HSTPIP_PRST1_Pos)) +#define USBHS_HSTPIP_PRST2_Pos _U_(18) /**< (USBHS_HSTPIP) Pipe 2 Reset Position */ +#define USBHS_HSTPIP_PRST2_Msk (_U_(0x1) << USBHS_HSTPIP_PRST2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Reset Mask */ +#define USBHS_HSTPIP_PRST2(value) (USBHS_HSTPIP_PRST2_Msk & ((value) << USBHS_HSTPIP_PRST2_Pos)) +#define USBHS_HSTPIP_PRST3_Pos _U_(19) /**< (USBHS_HSTPIP) Pipe 3 Reset Position */ +#define USBHS_HSTPIP_PRST3_Msk (_U_(0x1) << USBHS_HSTPIP_PRST3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Reset Mask */ +#define USBHS_HSTPIP_PRST3(value) (USBHS_HSTPIP_PRST3_Msk & ((value) << USBHS_HSTPIP_PRST3_Pos)) +#define USBHS_HSTPIP_PRST4_Pos _U_(20) /**< (USBHS_HSTPIP) Pipe 4 Reset Position */ +#define USBHS_HSTPIP_PRST4_Msk (_U_(0x1) << USBHS_HSTPIP_PRST4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Reset Mask */ +#define USBHS_HSTPIP_PRST4(value) (USBHS_HSTPIP_PRST4_Msk & ((value) << USBHS_HSTPIP_PRST4_Pos)) +#define USBHS_HSTPIP_PRST5_Pos _U_(21) /**< (USBHS_HSTPIP) Pipe 5 Reset Position */ +#define USBHS_HSTPIP_PRST5_Msk (_U_(0x1) << USBHS_HSTPIP_PRST5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Reset Mask */ +#define USBHS_HSTPIP_PRST5(value) (USBHS_HSTPIP_PRST5_Msk & ((value) << USBHS_HSTPIP_PRST5_Pos)) +#define USBHS_HSTPIP_PRST6_Pos _U_(22) /**< (USBHS_HSTPIP) Pipe 6 Reset Position */ +#define USBHS_HSTPIP_PRST6_Msk (_U_(0x1) << USBHS_HSTPIP_PRST6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Reset Mask */ +#define USBHS_HSTPIP_PRST6(value) (USBHS_HSTPIP_PRST6_Msk & ((value) << USBHS_HSTPIP_PRST6_Pos)) +#define USBHS_HSTPIP_PRST7_Pos _U_(23) /**< (USBHS_HSTPIP) Pipe 7 Reset Position */ +#define USBHS_HSTPIP_PRST7_Msk (_U_(0x1) << USBHS_HSTPIP_PRST7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Reset Mask */ +#define USBHS_HSTPIP_PRST7(value) (USBHS_HSTPIP_PRST7_Msk & ((value) << USBHS_HSTPIP_PRST7_Pos)) +#define USBHS_HSTPIP_PRST8_Pos _U_(24) /**< (USBHS_HSTPIP) Pipe 8 Reset Position */ +#define USBHS_HSTPIP_PRST8_Msk (_U_(0x1) << USBHS_HSTPIP_PRST8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Reset Mask */ +#define USBHS_HSTPIP_PRST8(value) (USBHS_HSTPIP_PRST8_Msk & ((value) << USBHS_HSTPIP_PRST8_Pos)) +#define USBHS_HSTPIP_Msk _U_(0x01FF01FF) /**< (USBHS_HSTPIP) Register Mask */ + +#define USBHS_HSTPIP_PEN_Pos _U_(0) /**< (USBHS_HSTPIP Position) Pipe x Enable */ +#define USBHS_HSTPIP_PEN_Msk (_U_(0x1FF) << USBHS_HSTPIP_PEN_Pos) /**< (USBHS_HSTPIP Mask) PEN */ +#define USBHS_HSTPIP_PEN(value) (USBHS_HSTPIP_PEN_Msk & ((value) << USBHS_HSTPIP_PEN_Pos)) +#define USBHS_HSTPIP_PRST_Pos _U_(16) /**< (USBHS_HSTPIP Position) Pipe 8 Reset */ +#define USBHS_HSTPIP_PRST_Msk (_U_(0x1FF) << USBHS_HSTPIP_PRST_Pos) /**< (USBHS_HSTPIP Mask) PRST */ +#define USBHS_HSTPIP_PRST(value) (USBHS_HSTPIP_PRST_Msk & ((value) << USBHS_HSTPIP_PRST_Pos)) + +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos _U_(0) /**< (USBHS_HSTFNUM) Micro Frame Number Position */ +#define USBHS_HSTFNUM_MFNUM_Msk (_U_(0x7) << USBHS_HSTFNUM_MFNUM_Pos) /**< (USBHS_HSTFNUM) Micro Frame Number Mask */ +#define USBHS_HSTFNUM_MFNUM(value) (USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)) +#define USBHS_HSTFNUM_FNUM_Pos _U_(3) /**< (USBHS_HSTFNUM) Frame Number Position */ +#define USBHS_HSTFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_HSTFNUM_FNUM_Pos) /**< (USBHS_HSTFNUM) Frame Number Mask */ +#define USBHS_HSTFNUM_FNUM(value) (USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)) +#define USBHS_HSTFNUM_FLENHIGH_Pos _U_(16) /**< (USBHS_HSTFNUM) Frame Length Position */ +#define USBHS_HSTFNUM_FLENHIGH_Msk (_U_(0xFF) << USBHS_HSTFNUM_FLENHIGH_Pos) /**< (USBHS_HSTFNUM) Frame Length Mask */ +#define USBHS_HSTFNUM_FLENHIGH(value) (USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)) +#define USBHS_HSTFNUM_Msk _U_(0x00FF3FFF) /**< (USBHS_HSTFNUM) Register Mask */ + + +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos _U_(0) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP0_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP0(value) (USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)) +#define USBHS_HSTADDR1_HSTADDRP1_Pos _U_(8) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP1_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP1(value) (USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)) +#define USBHS_HSTADDR1_HSTADDRP2_Pos _U_(16) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP2_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP2(value) (USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)) +#define USBHS_HSTADDR1_HSTADDRP3_Pos _U_(24) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP3_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP3(value) (USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)) +#define USBHS_HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR1) Register Mask */ + + +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos _U_(0) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP4_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP4(value) (USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)) +#define USBHS_HSTADDR2_HSTADDRP5_Pos _U_(8) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP5_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP5(value) (USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)) +#define USBHS_HSTADDR2_HSTADDRP6_Pos _U_(16) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP6_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP6(value) (USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)) +#define USBHS_HSTADDR2_HSTADDRP7_Pos _U_(24) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP7_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP7(value) (USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)) +#define USBHS_HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR2) Register Mask */ + + +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x42C) (R/W 32) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos _U_(0) /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP8_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP8(value) (USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)) +#define USBHS_HSTADDR3_HSTADDRP9_Pos _U_(8) /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP9_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP9(value) (USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)) +#define USBHS_HSTADDR3_Msk _U_(0x00007F7F) /**< (USBHS_HSTADDR3) Register Mask */ + + +/* -------- USBHS_HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPCFG_ALLOC_Pos _U_(1) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Position */ +#define USBHS_HSTPIPCFG_ALLOC_Msk (_U_(0x1) << USBHS_HSTPIPCFG_ALLOC_Pos) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Mask */ +#define USBHS_HSTPIPCFG_ALLOC(value) (USBHS_HSTPIPCFG_ALLOC_Msk & ((value) << USBHS_HSTPIPCFG_ALLOC_Pos)) +#define USBHS_HSTPIPCFG_PBK_Pos _U_(2) /**< (USBHS_HSTPIPCFG) Pipe Banks Position */ +#define USBHS_HSTPIPCFG_PBK_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Pipe Banks Mask */ +#define USBHS_HSTPIPCFG_PBK(value) (USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)) +#define USBHS_HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_1_BANK (USBHS_HSTPIPCFG_PBK_1_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Single-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (USBHS_HSTPIPCFG_PBK_2_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Double-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (USBHS_HSTPIPCFG_PBK_3_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Triple-bank pipe Position */ +#define USBHS_HSTPIPCFG_PSIZE_Pos _U_(4) /**< (USBHS_HSTPIPCFG) Pipe Size Position */ +#define USBHS_HSTPIPCFG_PSIZE_Msk (_U_(0x7) << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Size Mask */ +#define USBHS_HSTPIPCFG_PSIZE(value) (USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_HSTPIPCFG) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_HSTPIPCFG) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_HSTPIPCFG) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_HSTPIPCFG) 1024 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 8 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 16 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 32 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 64 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 128 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 256 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 512 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 1024 bytes Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos _U_(8) /**< (USBHS_HSTPIPCFG) Pipe Token Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) Pipe Token Mask */ +#define USBHS_HSTPIPCFG_PTOKEN(value) (USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) OUT */ +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (USBHS_HSTPIPCFG_PTOKEN_SETUP_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) SETUP Position */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (USBHS_HSTPIPCFG_PTOKEN_IN_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) IN Position */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (USBHS_HSTPIPCFG_PTOKEN_OUT_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) OUT Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Pos _U_(10) /**< (USBHS_HSTPIPCFG) Automatic Switch Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Msk (_U_(0x1) << USBHS_HSTPIPCFG_AUTOSW_Pos) /**< (USBHS_HSTPIPCFG) Automatic Switch Mask */ +#define USBHS_HSTPIPCFG_AUTOSW(value) (USBHS_HSTPIPCFG_AUTOSW_Msk & ((value) << USBHS_HSTPIPCFG_AUTOSW_Pos)) +#define USBHS_HSTPIPCFG_PTYPE_Pos _U_(12) /**< (USBHS_HSTPIPCFG) Pipe Type Position */ +#define USBHS_HSTPIPCFG_PTYPE_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Type Mask */ +#define USBHS_HSTPIPCFG_PTYPE(value) (USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)) +#define USBHS_HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) Interrupt */ +#define USBHS_HSTPIPCFG_PTYPE_CTRL (USBHS_HSTPIPCFG_PTYPE_CTRL_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Control Position */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (USBHS_HSTPIPCFG_PTYPE_ISO_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Isochronous Position */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (USBHS_HSTPIPCFG_PTYPE_BLK_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Bulk Position */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (USBHS_HSTPIPCFG_PTYPE_INTRPT_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Interrupt Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos _U_(16) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Msk (_U_(0xF) << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Mask */ +#define USBHS_HSTPIPCFG_PEPNUM(value) (USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)) +#define USBHS_HSTPIPCFG_INTFRQ_Pos _U_(24) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Position */ +#define USBHS_HSTPIPCFG_INTFRQ_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ +#define USBHS_HSTPIPCFG_INTFRQ(value) (USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)) +#define USBHS_HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (USBHS_HSTPIPCFG) Register Mask */ + + +/* -------- USBHS_HSTPIPISR : (USBHS Offset: 0x530) ( R/ 32) Host Pipe Status Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPISR_RXINI_Pos _U_(0) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Position */ +#define USBHS_HSTPIPISR_RXINI_Msk (_U_(0x1) << USBHS_HSTPIPISR_RXINI_Pos) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Mask */ +#define USBHS_HSTPIPISR_RXINI(value) (USBHS_HSTPIPISR_RXINI_Msk & ((value) << USBHS_HSTPIPISR_RXINI_Pos)) +#define USBHS_HSTPIPISR_TXOUTI_Pos _U_(1) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Position */ +#define USBHS_HSTPIPISR_TXOUTI_Msk (_U_(0x1) << USBHS_HSTPIPISR_TXOUTI_Pos) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Mask */ +#define USBHS_HSTPIPISR_TXOUTI(value) (USBHS_HSTPIPISR_TXOUTI_Msk & ((value) << USBHS_HSTPIPISR_TXOUTI_Pos)) +#define USBHS_HSTPIPISR_TXSTPI_Pos _U_(2) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_TXSTPI(value) (USBHS_HSTPIPISR_TXSTPI_Msk & ((value) << USBHS_HSTPIPISR_TXSTPI_Pos)) +#define USBHS_HSTPIPISR_PERRI_Pos _U_(3) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Position */ +#define USBHS_HSTPIPISR_PERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_PERRI_Pos) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Mask */ +#define USBHS_HSTPIPISR_PERRI(value) (USBHS_HSTPIPISR_PERRI_Msk & ((value) << USBHS_HSTPIPISR_PERRI_Pos)) +#define USBHS_HSTPIPISR_NAKEDI_Pos _U_(4) /**< (USBHS_HSTPIPISR) NAKed Interrupt Position */ +#define USBHS_HSTPIPISR_NAKEDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_NAKEDI_Pos) /**< (USBHS_HSTPIPISR) NAKed Interrupt Mask */ +#define USBHS_HSTPIPISR_NAKEDI(value) (USBHS_HSTPIPISR_NAKEDI_Msk & ((value) << USBHS_HSTPIPISR_NAKEDI_Pos)) +#define USBHS_HSTPIPISR_OVERFI_Pos _U_(5) /**< (USBHS_HSTPIPISR) Overflow Interrupt Position */ +#define USBHS_HSTPIPISR_OVERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_OVERFI_Pos) /**< (USBHS_HSTPIPISR) Overflow Interrupt Mask */ +#define USBHS_HSTPIPISR_OVERFI(value) (USBHS_HSTPIPISR_OVERFI_Msk & ((value) << USBHS_HSTPIPISR_OVERFI_Pos)) +#define USBHS_HSTPIPISR_RXSTALLDI_Pos _U_(6) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_RXSTALLDI(value) (USBHS_HSTPIPISR_RXSTALLDI_Msk & ((value) << USBHS_HSTPIPISR_RXSTALLDI_Pos)) +#define USBHS_HSTPIPISR_SHORTPACKETI_Pos _U_(7) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Position */ +#define USBHS_HSTPIPISR_SHORTPACKETI_Msk (_U_(0x1) << USBHS_HSTPIPISR_SHORTPACKETI_Pos) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Mask */ +#define USBHS_HSTPIPISR_SHORTPACKETI(value) (USBHS_HSTPIPISR_SHORTPACKETI_Msk & ((value) << USBHS_HSTPIPISR_SHORTPACKETI_Pos)) +#define USBHS_HSTPIPISR_DTSEQ_Pos _U_(8) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_Msk (_U_(0x3) << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Mask */ +#define USBHS_HSTPIPISR_DTSEQ(value) (USBHS_HSTPIPISR_DTSEQ_Msk & ((value) << USBHS_HSTPIPISR_DTSEQ_Pos)) +#define USBHS_HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (USBHS_HSTPIPISR_DTSEQ_DATA0_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data0 toggle sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (USBHS_HSTPIPISR_DTSEQ_DATA1_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data1 toggle sequence Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos _U_(12) /**< (USBHS_HSTPIPISR) Number of Busy Banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) Number of Busy Banks Mask */ +#define USBHS_HSTPIPISR_NBUSYBK(value) (USBHS_HSTPIPISR_NBUSYBK_Msk & ((value) << USBHS_HSTPIPISR_NBUSYBK_Pos)) +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_HSTPIPISR) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_HSTPIPISR) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_HSTPIPISR) 3 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) Position */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 1 busy bank Position */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 2 busy banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 3 busy banks Position */ +#define USBHS_HSTPIPISR_CURRBK_Pos _U_(14) /**< (USBHS_HSTPIPISR) Current Bank Position */ +#define USBHS_HSTPIPISR_CURRBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current Bank Mask */ +#define USBHS_HSTPIPISR_CURRBK(value) (USBHS_HSTPIPISR_CURRBK_Msk & ((value) << USBHS_HSTPIPISR_CURRBK_Pos)) +#define USBHS_HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_HSTPIPISR) Current bank is bank2 */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (USBHS_HSTPIPISR_CURRBK_BANK0_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank0 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (USBHS_HSTPIPISR_CURRBK_BANK1_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank1 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (USBHS_HSTPIPISR_CURRBK_BANK2_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank2 Position */ +#define USBHS_HSTPIPISR_RWALL_Pos _U_(16) /**< (USBHS_HSTPIPISR) Read/Write Allowed Position */ +#define USBHS_HSTPIPISR_RWALL_Msk (_U_(0x1) << USBHS_HSTPIPISR_RWALL_Pos) /**< (USBHS_HSTPIPISR) Read/Write Allowed Mask */ +#define USBHS_HSTPIPISR_RWALL(value) (USBHS_HSTPIPISR_RWALL_Msk & ((value) << USBHS_HSTPIPISR_RWALL_Pos)) +#define USBHS_HSTPIPISR_CFGOK_Pos _U_(18) /**< (USBHS_HSTPIPISR) Configuration OK Status Position */ +#define USBHS_HSTPIPISR_CFGOK_Msk (_U_(0x1) << USBHS_HSTPIPISR_CFGOK_Pos) /**< (USBHS_HSTPIPISR) Configuration OK Status Mask */ +#define USBHS_HSTPIPISR_CFGOK(value) (USBHS_HSTPIPISR_CFGOK_Msk & ((value) << USBHS_HSTPIPISR_CFGOK_Pos)) +#define USBHS_HSTPIPISR_PBYCT_Pos _U_(20) /**< (USBHS_HSTPIPISR) Pipe Byte Count Position */ +#define USBHS_HSTPIPISR_PBYCT_Msk (_U_(0x7FF) << USBHS_HSTPIPISR_PBYCT_Pos) /**< (USBHS_HSTPIPISR) Pipe Byte Count Mask */ +#define USBHS_HSTPIPISR_PBYCT(value) (USBHS_HSTPIPISR_PBYCT_Msk & ((value) << USBHS_HSTPIPISR_PBYCT_Pos)) +#define USBHS_HSTPIPISR_Msk _U_(0x7FF5F3FF) /**< (USBHS_HSTPIPISR) Register Mask */ + + +/* -------- USBHS_HSTPIPICR : (USBHS Offset: 0x560) ( /W 32) Host Pipe Clear Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPICR_RXINIC_Pos _U_(0) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_RXINIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_RXINIC_Pos) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_RXINIC(value) (USBHS_HSTPIPICR_RXINIC_Msk & ((value) << USBHS_HSTPIPICR_RXINIC_Pos)) +#define USBHS_HSTPIPICR_TXOUTIC_Pos _U_(1) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_TXOUTIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_TXOUTIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_TXOUTIC(value) (USBHS_HSTPIPICR_TXOUTIC_Msk & ((value) << USBHS_HSTPIPICR_TXOUTIC_Pos)) +#define USBHS_HSTPIPICR_TXSTPIC_Pos _U_(2) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_TXSTPIC(value) (USBHS_HSTPIPICR_TXSTPIC_Msk & ((value) << USBHS_HSTPIPICR_TXSTPIC_Pos)) +#define USBHS_HSTPIPICR_NAKEDIC_Pos _U_(4) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_NAKEDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_NAKEDIC_Pos) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_NAKEDIC(value) (USBHS_HSTPIPICR_NAKEDIC_Msk & ((value) << USBHS_HSTPIPICR_NAKEDIC_Pos)) +#define USBHS_HSTPIPICR_OVERFIC_Pos _U_(5) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_OVERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_OVERFIC_Pos) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_OVERFIC(value) (USBHS_HSTPIPICR_OVERFIC_Msk & ((value) << USBHS_HSTPIPICR_OVERFIC_Pos)) +#define USBHS_HSTPIPICR_RXSTALLDIC_Pos _U_(6) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_RXSTALLDIC(value) (USBHS_HSTPIPICR_RXSTALLDIC_Msk & ((value) << USBHS_HSTPIPICR_RXSTALLDIC_Pos)) +#define USBHS_HSTPIPICR_SHORTPACKETIC_Pos _U_(7) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Position */ +#define USBHS_HSTPIPICR_SHORTPACKETIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_SHORTPACKETIC(value) (USBHS_HSTPIPICR_SHORTPACKETIC_Msk & ((value) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos)) +#define USBHS_HSTPIPICR_Msk _U_(0x000000F7) /**< (USBHS_HSTPIPICR) Register Mask */ + + +/* -------- USBHS_HSTPIPIFR : (USBHS Offset: 0x590) ( /W 32) Host Pipe Set Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPIFR_RXINIS_Pos _U_(0) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_RXINIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_RXINIS_Pos) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_RXINIS(value) (USBHS_HSTPIPIFR_RXINIS_Msk & ((value) << USBHS_HSTPIPIFR_RXINIS_Pos)) +#define USBHS_HSTPIPIFR_TXOUTIS_Pos _U_(1) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_TXOUTIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_TXOUTIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_TXOUTIS(value) (USBHS_HSTPIPIFR_TXOUTIS_Msk & ((value) << USBHS_HSTPIPIFR_TXOUTIS_Pos)) +#define USBHS_HSTPIPIFR_TXSTPIS_Pos _U_(2) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_TXSTPIS(value) (USBHS_HSTPIPIFR_TXSTPIS_Msk & ((value) << USBHS_HSTPIPIFR_TXSTPIS_Pos)) +#define USBHS_HSTPIPIFR_PERRIS_Pos _U_(3) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Position */ +#define USBHS_HSTPIPIFR_PERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_PERRIS_Pos) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_PERRIS(value) (USBHS_HSTPIPIFR_PERRIS_Msk & ((value) << USBHS_HSTPIPIFR_PERRIS_Pos)) +#define USBHS_HSTPIPIFR_NAKEDIS_Pos _U_(4) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_NAKEDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NAKEDIS_Pos) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_NAKEDIS(value) (USBHS_HSTPIPIFR_NAKEDIS_Msk & ((value) << USBHS_HSTPIPIFR_NAKEDIS_Pos)) +#define USBHS_HSTPIPIFR_OVERFIS_Pos _U_(5) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_OVERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_OVERFIS_Pos) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_OVERFIS(value) (USBHS_HSTPIPIFR_OVERFIS_Msk & ((value) << USBHS_HSTPIPIFR_OVERFIS_Pos)) +#define USBHS_HSTPIPIFR_RXSTALLDIS_Pos _U_(6) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_RXSTALLDIS(value) (USBHS_HSTPIPIFR_RXSTALLDIS_Msk & ((value) << USBHS_HSTPIPIFR_RXSTALLDIS_Pos)) +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Pos _U_(7) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Position */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS(value) (USBHS_HSTPIPIFR_SHORTPACKETIS_Msk & ((value) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos)) +#define USBHS_HSTPIPIFR_NBUSYBKS_Pos _U_(12) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Position */ +#define USBHS_HSTPIPIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NBUSYBKS_Pos) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Mask */ +#define USBHS_HSTPIPIFR_NBUSYBKS(value) (USBHS_HSTPIPIFR_NBUSYBKS_Msk & ((value) << USBHS_HSTPIPIFR_NBUSYBKS_Pos)) +#define USBHS_HSTPIPIFR_Msk _U_(0x000010FF) /**< (USBHS_HSTPIPIFR) Register Mask */ + + +/* -------- USBHS_HSTPIPIMR : (USBHS Offset: 0x5C0) ( R/ 32) Host Pipe Mask Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPIMR_RXINE_Pos _U_(0) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_RXINE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RXINE_Pos) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_RXINE(value) (USBHS_HSTPIPIMR_RXINE_Msk & ((value) << USBHS_HSTPIPIMR_RXINE_Pos)) +#define USBHS_HSTPIPIMR_TXOUTE_Pos _U_(1) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_TXOUTE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_TXOUTE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_TXOUTE(value) (USBHS_HSTPIPIMR_TXOUTE_Msk & ((value) << USBHS_HSTPIPIMR_TXOUTE_Pos)) +#define USBHS_HSTPIPIMR_TXSTPE_Pos _U_(2) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_TXSTPE(value) (USBHS_HSTPIPIMR_TXSTPE_Msk & ((value) << USBHS_HSTPIPIMR_TXSTPE_Pos)) +#define USBHS_HSTPIPIMR_PERRE_Pos _U_(3) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_PERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PERRE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_PERRE(value) (USBHS_HSTPIPIMR_PERRE_Msk & ((value) << USBHS_HSTPIPIMR_PERRE_Pos)) +#define USBHS_HSTPIPIMR_NAKEDE_Pos _U_(4) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NAKEDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NAKEDE_Pos) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NAKEDE(value) (USBHS_HSTPIPIMR_NAKEDE_Msk & ((value) << USBHS_HSTPIPIMR_NAKEDE_Pos)) +#define USBHS_HSTPIPIMR_OVERFIE_Pos _U_(5) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_OVERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_OVERFIE_Pos) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_OVERFIE(value) (USBHS_HSTPIPIMR_OVERFIE_Msk & ((value) << USBHS_HSTPIPIMR_OVERFIE_Pos)) +#define USBHS_HSTPIPIMR_RXSTALLDE_Pos _U_(6) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_RXSTALLDE(value) (USBHS_HSTPIPIMR_RXSTALLDE_Msk & ((value) << USBHS_HSTPIPIMR_RXSTALLDE_Pos)) +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Pos _U_(7) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE(value) (USBHS_HSTPIPIMR_SHORTPACKETIE_Msk & ((value) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos)) +#define USBHS_HSTPIPIMR_NBUSYBKE_Pos _U_(12) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NBUSYBKE_Pos) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NBUSYBKE(value) (USBHS_HSTPIPIMR_NBUSYBKE_Msk & ((value) << USBHS_HSTPIPIMR_NBUSYBKE_Pos)) +#define USBHS_HSTPIPIMR_FIFOCON_Pos _U_(14) /**< (USBHS_HSTPIPIMR) FIFO Control Position */ +#define USBHS_HSTPIPIMR_FIFOCON_Msk (_U_(0x1) << USBHS_HSTPIPIMR_FIFOCON_Pos) /**< (USBHS_HSTPIPIMR) FIFO Control Mask */ +#define USBHS_HSTPIPIMR_FIFOCON(value) (USBHS_HSTPIPIMR_FIFOCON_Msk & ((value) << USBHS_HSTPIPIMR_FIFOCON_Pos)) +#define USBHS_HSTPIPIMR_PDISHDMA_Pos _U_(16) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIMR_PDISHDMA_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PDISHDMA_Pos) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIMR_PDISHDMA(value) (USBHS_HSTPIPIMR_PDISHDMA_Msk & ((value) << USBHS_HSTPIPIMR_PDISHDMA_Pos)) +#define USBHS_HSTPIPIMR_PFREEZE_Pos _U_(17) /**< (USBHS_HSTPIPIMR) Pipe Freeze Position */ +#define USBHS_HSTPIPIMR_PFREEZE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PFREEZE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Freeze Mask */ +#define USBHS_HSTPIPIMR_PFREEZE(value) (USBHS_HSTPIPIMR_PFREEZE_Msk & ((value) << USBHS_HSTPIPIMR_PFREEZE_Pos)) +#define USBHS_HSTPIPIMR_RSTDT_Pos _U_(18) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Position */ +#define USBHS_HSTPIPIMR_RSTDT_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RSTDT_Pos) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Mask */ +#define USBHS_HSTPIPIMR_RSTDT(value) (USBHS_HSTPIPIMR_RSTDT_Msk & ((value) << USBHS_HSTPIPIMR_RSTDT_Pos)) +#define USBHS_HSTPIPIMR_Msk _U_(0x000750FF) /**< (USBHS_HSTPIPIMR) Register Mask */ + + +/* -------- USBHS_HSTPIPIER : (USBHS Offset: 0x5F0) ( /W 32) Host Pipe Enable Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPIER_RXINES_Pos _U_(0) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_RXINES_Msk (_U_(0x1) << USBHS_HSTPIPIER_RXINES_Pos) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_RXINES(value) (USBHS_HSTPIPIER_RXINES_Msk & ((value) << USBHS_HSTPIPIER_RXINES_Pos)) +#define USBHS_HSTPIPIER_TXOUTES_Pos _U_(1) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_TXOUTES_Msk (_U_(0x1) << USBHS_HSTPIPIER_TXOUTES_Pos) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_TXOUTES(value) (USBHS_HSTPIPIER_TXOUTES_Msk & ((value) << USBHS_HSTPIPIER_TXOUTES_Pos)) +#define USBHS_HSTPIPIER_TXSTPES_Pos _U_(2) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_TXSTPES(value) (USBHS_HSTPIPIER_TXSTPES_Msk & ((value) << USBHS_HSTPIPIER_TXSTPES_Pos)) +#define USBHS_HSTPIPIER_PERRES_Pos _U_(3) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIER_PERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PERRES_Pos) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_PERRES(value) (USBHS_HSTPIPIER_PERRES_Msk & ((value) << USBHS_HSTPIPIER_PERRES_Pos)) +#define USBHS_HSTPIPIER_NAKEDES_Pos _U_(4) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_NAKEDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NAKEDES_Pos) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_NAKEDES(value) (USBHS_HSTPIPIER_NAKEDES_Msk & ((value) << USBHS_HSTPIPIER_NAKEDES_Pos)) +#define USBHS_HSTPIPIER_OVERFIES_Pos _U_(5) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_OVERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_OVERFIES_Pos) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_OVERFIES(value) (USBHS_HSTPIPIER_OVERFIES_Msk & ((value) << USBHS_HSTPIPIER_OVERFIES_Pos)) +#define USBHS_HSTPIPIER_RXSTALLDES_Pos _U_(6) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_RXSTALLDES(value) (USBHS_HSTPIPIER_RXSTALLDES_Msk & ((value) << USBHS_HSTPIPIER_RXSTALLDES_Pos)) +#define USBHS_HSTPIPIER_SHORTPACKETIES_Pos _U_(7) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIER_SHORTPACKETIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_SHORTPACKETIES(value) (USBHS_HSTPIPIER_SHORTPACKETIES_Msk & ((value) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos)) +#define USBHS_HSTPIPIER_NBUSYBKES_Pos _U_(12) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Position */ +#define USBHS_HSTPIPIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NBUSYBKES_Pos) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Mask */ +#define USBHS_HSTPIPIER_NBUSYBKES(value) (USBHS_HSTPIPIER_NBUSYBKES_Msk & ((value) << USBHS_HSTPIPIER_NBUSYBKES_Pos)) +#define USBHS_HSTPIPIER_PDISHDMAS_Pos _U_(16) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIER_PDISHDMAS_Msk (_U_(0x1) << USBHS_HSTPIPIER_PDISHDMAS_Pos) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIER_PDISHDMAS(value) (USBHS_HSTPIPIER_PDISHDMAS_Msk & ((value) << USBHS_HSTPIPIER_PDISHDMAS_Pos)) +#define USBHS_HSTPIPIER_PFREEZES_Pos _U_(17) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Position */ +#define USBHS_HSTPIPIER_PFREEZES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PFREEZES_Pos) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Mask */ +#define USBHS_HSTPIPIER_PFREEZES(value) (USBHS_HSTPIPIER_PFREEZES_Msk & ((value) << USBHS_HSTPIPIER_PFREEZES_Pos)) +#define USBHS_HSTPIPIER_RSTDTS_Pos _U_(18) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Position */ +#define USBHS_HSTPIPIER_RSTDTS_Msk (_U_(0x1) << USBHS_HSTPIPIER_RSTDTS_Pos) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Mask */ +#define USBHS_HSTPIPIER_RSTDTS(value) (USBHS_HSTPIPIER_RSTDTS_Msk & ((value) << USBHS_HSTPIPIER_RSTDTS_Pos)) +#define USBHS_HSTPIPIER_Msk _U_(0x000710FF) /**< (USBHS_HSTPIPIER) Register Mask */ + + +/* -------- USBHS_HSTPIPIDR : (USBHS Offset: 0x620) ( /W 32) Host Pipe Disable Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPIDR_RXINEC_Pos _U_(0) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_RXINEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_RXINEC_Pos) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_RXINEC(value) (USBHS_HSTPIPIDR_RXINEC_Msk & ((value) << USBHS_HSTPIPIDR_RXINEC_Pos)) +#define USBHS_HSTPIPIDR_TXOUTEC_Pos _U_(1) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_TXOUTEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_TXOUTEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_TXOUTEC(value) (USBHS_HSTPIPIDR_TXOUTEC_Msk & ((value) << USBHS_HSTPIPIDR_TXOUTEC_Pos)) +#define USBHS_HSTPIPIDR_TXSTPEC_Pos _U_(2) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_TXSTPEC(value) (USBHS_HSTPIPIDR_TXSTPEC_Msk & ((value) << USBHS_HSTPIPIDR_TXSTPEC_Pos)) +#define USBHS_HSTPIPIDR_PERREC_Pos _U_(3) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_PERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PERREC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_PERREC(value) (USBHS_HSTPIPIDR_PERREC_Msk & ((value) << USBHS_HSTPIPIDR_PERREC_Pos)) +#define USBHS_HSTPIPIDR_NAKEDEC_Pos _U_(4) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_NAKEDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NAKEDEC_Pos) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_NAKEDEC(value) (USBHS_HSTPIPIDR_NAKEDEC_Msk & ((value) << USBHS_HSTPIPIDR_NAKEDEC_Pos)) +#define USBHS_HSTPIPIDR_OVERFIEC_Pos _U_(5) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_OVERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_OVERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_OVERFIEC(value) (USBHS_HSTPIPIDR_OVERFIEC_Msk & ((value) << USBHS_HSTPIPIDR_OVERFIEC_Pos)) +#define USBHS_HSTPIPIDR_RXSTALLDEC_Pos _U_(6) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_RXSTALLDEC(value) (USBHS_HSTPIPIDR_RXSTALLDEC_Msk & ((value) << USBHS_HSTPIPIDR_RXSTALLDEC_Pos)) +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos _U_(7) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC(value) (USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk & ((value) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos)) +#define USBHS_HSTPIPIDR_NBUSYBKEC_Pos _U_(12) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Position */ +#define USBHS_HSTPIPIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Mask */ +#define USBHS_HSTPIPIDR_NBUSYBKEC(value) (USBHS_HSTPIPIDR_NBUSYBKEC_Msk & ((value) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos)) +#define USBHS_HSTPIPIDR_FIFOCONC_Pos _U_(14) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Position */ +#define USBHS_HSTPIPIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_FIFOCONC_Pos) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Mask */ +#define USBHS_HSTPIPIDR_FIFOCONC(value) (USBHS_HSTPIPIDR_FIFOCONC_Msk & ((value) << USBHS_HSTPIPIDR_FIFOCONC_Pos)) +#define USBHS_HSTPIPIDR_PDISHDMAC_Pos _U_(16) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ +#define USBHS_HSTPIPIDR_PDISHDMAC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PDISHDMAC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ +#define USBHS_HSTPIPIDR_PDISHDMAC(value) (USBHS_HSTPIPIDR_PDISHDMAC_Msk & ((value) << USBHS_HSTPIPIDR_PDISHDMAC_Pos)) +#define USBHS_HSTPIPIDR_PFREEZEC_Pos _U_(17) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Position */ +#define USBHS_HSTPIPIDR_PFREEZEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PFREEZEC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Mask */ +#define USBHS_HSTPIPIDR_PFREEZEC(value) (USBHS_HSTPIPIDR_PFREEZEC_Msk & ((value) << USBHS_HSTPIPIDR_PFREEZEC_Pos)) +#define USBHS_HSTPIPIDR_Msk _U_(0x000350FF) /**< (USBHS_HSTPIPIDR) Register Mask */ + + +/* -------- USBHS_HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos _U_(0) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Position */ +#define USBHS_HSTPIPINRQ_INRQ_Msk (_U_(0xFF) << USBHS_HSTPIPINRQ_INRQ_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Mask */ +#define USBHS_HSTPIPINRQ_INRQ(value) (USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)) +#define USBHS_HSTPIPINRQ_INMODE_Pos _U_(8) /**< (USBHS_HSTPIPINRQ) IN Request Mode Position */ +#define USBHS_HSTPIPINRQ_INMODE_Msk (_U_(0x1) << USBHS_HSTPIPINRQ_INMODE_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Mode Mask */ +#define USBHS_HSTPIPINRQ_INMODE(value) (USBHS_HSTPIPINRQ_INMODE_Msk & ((value) << USBHS_HSTPIPINRQ_INMODE_Pos)) +#define USBHS_HSTPIPINRQ_Msk _U_(0x000001FF) /**< (USBHS_HSTPIPINRQ) Register Mask */ + + +/* -------- USBHS_HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register (n = 0) 0 -------- */ +#define USBHS_HSTPIPERR_DATATGL_Pos _U_(0) /**< (USBHS_HSTPIPERR) Data Toggle Error Position */ +#define USBHS_HSTPIPERR_DATATGL_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATATGL_Pos) /**< (USBHS_HSTPIPERR) Data Toggle Error Mask */ +#define USBHS_HSTPIPERR_DATATGL(value) (USBHS_HSTPIPERR_DATATGL_Msk & ((value) << USBHS_HSTPIPERR_DATATGL_Pos)) +#define USBHS_HSTPIPERR_DATAPID_Pos _U_(1) /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_DATAPID_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATAPID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_DATAPID(value) (USBHS_HSTPIPERR_DATAPID_Msk & ((value) << USBHS_HSTPIPERR_DATAPID_Pos)) +#define USBHS_HSTPIPERR_PID_Pos _U_(2) /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_PID_Msk (_U_(0x1) << USBHS_HSTPIPERR_PID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_PID(value) (USBHS_HSTPIPERR_PID_Msk & ((value) << USBHS_HSTPIPERR_PID_Pos)) +#define USBHS_HSTPIPERR_TIMEOUT_Pos _U_(3) /**< (USBHS_HSTPIPERR) Time-Out Error Position */ +#define USBHS_HSTPIPERR_TIMEOUT_Msk (_U_(0x1) << USBHS_HSTPIPERR_TIMEOUT_Pos) /**< (USBHS_HSTPIPERR) Time-Out Error Mask */ +#define USBHS_HSTPIPERR_TIMEOUT(value) (USBHS_HSTPIPERR_TIMEOUT_Msk & ((value) << USBHS_HSTPIPERR_TIMEOUT_Pos)) +#define USBHS_HSTPIPERR_CRC16_Pos _U_(4) /**< (USBHS_HSTPIPERR) CRC16 Error Position */ +#define USBHS_HSTPIPERR_CRC16_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC16_Pos) /**< (USBHS_HSTPIPERR) CRC16 Error Mask */ +#define USBHS_HSTPIPERR_CRC16(value) (USBHS_HSTPIPERR_CRC16_Msk & ((value) << USBHS_HSTPIPERR_CRC16_Pos)) +#define USBHS_HSTPIPERR_COUNTER_Pos _U_(5) /**< (USBHS_HSTPIPERR) Error Counter Position */ +#define USBHS_HSTPIPERR_COUNTER_Msk (_U_(0x3) << USBHS_HSTPIPERR_COUNTER_Pos) /**< (USBHS_HSTPIPERR) Error Counter Mask */ +#define USBHS_HSTPIPERR_COUNTER(value) (USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)) +#define USBHS_HSTPIPERR_Msk _U_(0x0000007F) /**< (USBHS_HSTPIPERR) Register Mask */ + +#define USBHS_HSTPIPERR_CRC_Pos _U_(4) /**< (USBHS_HSTPIPERR Position) CRCx6 Error */ +#define USBHS_HSTPIPERR_CRC_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC_Pos) /**< (USBHS_HSTPIPERR Mask) CRC */ +#define USBHS_HSTPIPERR_CRC(value) (USBHS_HSTPIPERR_CRC_Msk & ((value) << USBHS_HSTPIPERR_CRC_Pos)) + +/* -------- USBHS_CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ +#define USBHS_CTRL_RDERRE_Pos _U_(4) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Position */ +#define USBHS_CTRL_RDERRE_Msk (_U_(0x1) << USBHS_CTRL_RDERRE_Pos) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Mask */ +#define USBHS_CTRL_RDERRE(value) (USBHS_CTRL_RDERRE_Msk & ((value) << USBHS_CTRL_RDERRE_Pos)) +#define USBHS_CTRL_VBUSHWC_Pos _U_(8) /**< (USBHS_CTRL) VBUS Hardware Control Position */ +#define USBHS_CTRL_VBUSHWC_Msk (_U_(0x1) << USBHS_CTRL_VBUSHWC_Pos) /**< (USBHS_CTRL) VBUS Hardware Control Mask */ +#define USBHS_CTRL_VBUSHWC(value) (USBHS_CTRL_VBUSHWC_Msk & ((value) << USBHS_CTRL_VBUSHWC_Pos)) +#define USBHS_CTRL_FRZCLK_Pos _U_(14) /**< (USBHS_CTRL) Freeze USB Clock Position */ +#define USBHS_CTRL_FRZCLK_Msk (_U_(0x1) << USBHS_CTRL_FRZCLK_Pos) /**< (USBHS_CTRL) Freeze USB Clock Mask */ +#define USBHS_CTRL_FRZCLK(value) (USBHS_CTRL_FRZCLK_Msk & ((value) << USBHS_CTRL_FRZCLK_Pos)) +#define USBHS_CTRL_USBE_Pos _U_(15) /**< (USBHS_CTRL) USBHS Enable Position */ +#define USBHS_CTRL_USBE_Msk (_U_(0x1) << USBHS_CTRL_USBE_Pos) /**< (USBHS_CTRL) USBHS Enable Mask */ +#define USBHS_CTRL_USBE(value) (USBHS_CTRL_USBE_Msk & ((value) << USBHS_CTRL_USBE_Pos)) +#define USBHS_CTRL_UIMOD_Pos _U_(25) /**< (USBHS_CTRL) USBHS Mode Position */ +#define USBHS_CTRL_UIMOD_Msk (_U_(0x1) << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) USBHS Mode Mask */ +#define USBHS_CTRL_UIMOD(value) (USBHS_CTRL_UIMOD_Msk & ((value) << USBHS_CTRL_UIMOD_Pos)) +#define USBHS_CTRL_UIMOD_HOST_Val _U_(0x0) /**< (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (USBHS_CTRL) The module is in USB Device mode. */ +#define USBHS_CTRL_UIMOD_HOST (USBHS_CTRL_UIMOD_HOST_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Host mode. Position */ +#define USBHS_CTRL_UIMOD_DEVICE (USBHS_CTRL_UIMOD_DEVICE_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Device mode. Position */ +#define USBHS_CTRL_Msk _U_(0x0200C110) /**< (USBHS_CTRL) Register Mask */ + + +/* -------- USBHS_SR : (USBHS Offset: 0x804) ( R/ 32) General Status Register -------- */ +#define USBHS_SR_RDERRI_Pos _U_(4) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Position */ +#define USBHS_SR_RDERRI_Msk (_U_(0x1) << USBHS_SR_RDERRI_Pos) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ +#define USBHS_SR_RDERRI(value) (USBHS_SR_RDERRI_Msk & ((value) << USBHS_SR_RDERRI_Pos)) +#define USBHS_SR_SPEED_Pos _U_(12) /**< (USBHS_SR) Speed Status (Device mode only) Position */ +#define USBHS_SR_SPEED_Msk (_U_(0x3) << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Speed Status (Device mode only) Mask */ +#define USBHS_SR_SPEED(value) (USBHS_SR_SPEED_Msk & ((value) << USBHS_SR_SPEED_Pos)) +#define USBHS_SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_SPEED_FULL_SPEED (USBHS_SR_SPEED_FULL_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Full-Speed mode Position */ +#define USBHS_SR_SPEED_HIGH_SPEED (USBHS_SR_SPEED_HIGH_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) High-Speed mode Position */ +#define USBHS_SR_SPEED_LOW_SPEED (USBHS_SR_SPEED_LOW_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Low-Speed mode Position */ +#define USBHS_SR_CLKUSABLE_Pos _U_(14) /**< (USBHS_SR) UTMI Clock Usable Position */ +#define USBHS_SR_CLKUSABLE_Msk (_U_(0x1) << USBHS_SR_CLKUSABLE_Pos) /**< (USBHS_SR) UTMI Clock Usable Mask */ +#define USBHS_SR_CLKUSABLE(value) (USBHS_SR_CLKUSABLE_Msk & ((value) << USBHS_SR_CLKUSABLE_Pos)) +#define USBHS_SR_Msk _U_(0x00007010) /**< (USBHS_SR) Register Mask */ + + +/* -------- USBHS_SCR : (USBHS Offset: 0x808) ( /W 32) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC_Pos _U_(4) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Position */ +#define USBHS_SCR_RDERRIC_Msk (_U_(0x1) << USBHS_SCR_RDERRIC_Pos) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Mask */ +#define USBHS_SCR_RDERRIC(value) (USBHS_SCR_RDERRIC_Msk & ((value) << USBHS_SCR_RDERRIC_Pos)) +#define USBHS_SCR_Msk _U_(0x00000010) /**< (USBHS_SCR) Register Mask */ + + +/* -------- USBHS_SFR : (USBHS Offset: 0x80C) ( /W 32) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS_Pos _U_(4) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Position */ +#define USBHS_SFR_RDERRIS_Msk (_U_(0x1) << USBHS_SFR_RDERRIS_Pos) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Mask */ +#define USBHS_SFR_RDERRIS(value) (USBHS_SFR_RDERRIS_Msk & ((value) << USBHS_SFR_RDERRIS_Pos)) +#define USBHS_SFR_VBUSRQS_Pos _U_(9) /**< (USBHS_SFR) VBUS Request Set Position */ +#define USBHS_SFR_VBUSRQS_Msk (_U_(0x1) << USBHS_SFR_VBUSRQS_Pos) /**< (USBHS_SFR) VBUS Request Set Mask */ +#define USBHS_SFR_VBUSRQS(value) (USBHS_SFR_VBUSRQS_Msk & ((value) << USBHS_SFR_VBUSRQS_Pos)) +#define USBHS_SFR_Msk _U_(0x00000210) /**< (USBHS_SFR) Register Mask */ + + +/** \brief USBHS register offsets definitions */ +#define USBHS_DEVDMANXTDSC_REG_OFST (0x00) /**< (USBHS_DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register (n = 1) Offset */ +#define USBHS_DEVDMAADDRESS_REG_OFST (0x04) /**< (USBHS_DEVDMAADDRESS) Device DMA Channel Address Register (n = 1) Offset */ +#define USBHS_DEVDMACONTROL_REG_OFST (0x08) /**< (USBHS_DEVDMACONTROL) Device DMA Channel Control Register (n = 1) Offset */ +#define USBHS_DEVDMASTATUS_REG_OFST (0x0C) /**< (USBHS_DEVDMASTATUS) Device DMA Channel Status Register (n = 1) Offset */ +#define USBHS_HSTDMANXTDSC_REG_OFST (0x00) /**< (USBHS_HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register (n = 1) Offset */ +#define USBHS_HSTDMAADDRESS_REG_OFST (0x04) /**< (USBHS_HSTDMAADDRESS) Host DMA Channel Address Register (n = 1) Offset */ +#define USBHS_HSTDMACONTROL_REG_OFST (0x08) /**< (USBHS_HSTDMACONTROL) Host DMA Channel Control Register (n = 1) Offset */ +#define USBHS_HSTDMASTATUS_REG_OFST (0x0C) /**< (USBHS_HSTDMASTATUS) Host DMA Channel Status Register (n = 1) Offset */ +#define USBHS_DEVCTRL_REG_OFST (0x00) /**< (USBHS_DEVCTRL) Device General Control Register Offset */ +#define USBHS_DEVISR_REG_OFST (0x04) /**< (USBHS_DEVISR) Device Global Interrupt Status Register Offset */ +#define USBHS_DEVICR_REG_OFST (0x08) /**< (USBHS_DEVICR) Device Global Interrupt Clear Register Offset */ +#define USBHS_DEVIFR_REG_OFST (0x0C) /**< (USBHS_DEVIFR) Device Global Interrupt Set Register Offset */ +#define USBHS_DEVIMR_REG_OFST (0x10) /**< (USBHS_DEVIMR) Device Global Interrupt Mask Register Offset */ +#define USBHS_DEVIDR_REG_OFST (0x14) /**< (USBHS_DEVIDR) Device Global Interrupt Disable Register Offset */ +#define USBHS_DEVIER_REG_OFST (0x18) /**< (USBHS_DEVIER) Device Global Interrupt Enable Register Offset */ +#define USBHS_DEVEPT_REG_OFST (0x1C) /**< (USBHS_DEVEPT) Device Endpoint Register Offset */ +#define USBHS_DEVFNUM_REG_OFST (0x20) /**< (USBHS_DEVFNUM) Device Frame Number Register Offset */ +#define USBHS_DEVEPTCFG_REG_OFST (0x100) /**< (USBHS_DEVEPTCFG) Device Endpoint Configuration Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTISR_REG_OFST (0x130) /**< (USBHS_DEVEPTISR) Device Endpoint Status Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTICR_REG_OFST (0x160) /**< (USBHS_DEVEPTICR) Device Endpoint Clear Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTIFR_REG_OFST (0x190) /**< (USBHS_DEVEPTIFR) Device Endpoint Set Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTIMR_REG_OFST (0x1C0) /**< (USBHS_DEVEPTIMR) Device Endpoint Mask Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTIER_REG_OFST (0x1F0) /**< (USBHS_DEVEPTIER) Device Endpoint Enable Register (n = 0) 0 Offset */ +#define USBHS_DEVEPTIDR_REG_OFST (0x220) /**< (USBHS_DEVEPTIDR) Device Endpoint Disable Register (n = 0) 0 Offset */ +#define USBHS_HSTCTRL_REG_OFST (0x400) /**< (USBHS_HSTCTRL) Host General Control Register Offset */ +#define USBHS_HSTISR_REG_OFST (0x404) /**< (USBHS_HSTISR) Host Global Interrupt Status Register Offset */ +#define USBHS_HSTICR_REG_OFST (0x408) /**< (USBHS_HSTICR) Host Global Interrupt Clear Register Offset */ +#define USBHS_HSTIFR_REG_OFST (0x40C) /**< (USBHS_HSTIFR) Host Global Interrupt Set Register Offset */ +#define USBHS_HSTIMR_REG_OFST (0x410) /**< (USBHS_HSTIMR) Host Global Interrupt Mask Register Offset */ +#define USBHS_HSTIDR_REG_OFST (0x414) /**< (USBHS_HSTIDR) Host Global Interrupt Disable Register Offset */ +#define USBHS_HSTIER_REG_OFST (0x418) /**< (USBHS_HSTIER) Host Global Interrupt Enable Register Offset */ +#define USBHS_HSTPIP_REG_OFST (0x41C) /**< (USBHS_HSTPIP) Host Pipe Register Offset */ +#define USBHS_HSTFNUM_REG_OFST (0x420) /**< (USBHS_HSTFNUM) Host Frame Number Register Offset */ +#define USBHS_HSTADDR1_REG_OFST (0x424) /**< (USBHS_HSTADDR1) Host Address 1 Register Offset */ +#define USBHS_HSTADDR2_REG_OFST (0x428) /**< (USBHS_HSTADDR2) Host Address 2 Register Offset */ +#define USBHS_HSTADDR3_REG_OFST (0x42C) /**< (USBHS_HSTADDR3) Host Address 3 Register Offset */ +#define USBHS_HSTPIPCFG_REG_OFST (0x500) /**< (USBHS_HSTPIPCFG) Host Pipe Configuration Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPISR_REG_OFST (0x530) /**< (USBHS_HSTPIPISR) Host Pipe Status Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPICR_REG_OFST (0x560) /**< (USBHS_HSTPIPICR) Host Pipe Clear Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPIFR_REG_OFST (0x590) /**< (USBHS_HSTPIPIFR) Host Pipe Set Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPIMR_REG_OFST (0x5C0) /**< (USBHS_HSTPIPIMR) Host Pipe Mask Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPIER_REG_OFST (0x5F0) /**< (USBHS_HSTPIPIER) Host Pipe Enable Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPIDR_REG_OFST (0x620) /**< (USBHS_HSTPIPIDR) Host Pipe Disable Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPINRQ_REG_OFST (0x650) /**< (USBHS_HSTPIPINRQ) Host Pipe IN Request Register (n = 0) 0 Offset */ +#define USBHS_HSTPIPERR_REG_OFST (0x680) /**< (USBHS_HSTPIPERR) Host Pipe Error Register (n = 0) 0 Offset */ +#define USBHS_CTRL_REG_OFST (0x800) /**< (USBHS_CTRL) General Control Register Offset */ +#define USBHS_SR_REG_OFST (0x804) /**< (USBHS_SR) General Status Register Offset */ +#define USBHS_SCR_REG_OFST (0x808) /**< (USBHS_SCR) General Status Clear Register Offset */ +#define USBHS_SFR_REG_OFST (0x80C) /**< (USBHS_SFR) General Status Set Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief USBHS_DEVDMA register API structure */ +typedef struct +{ + __IO uint32_t USBHS_DEVDMANXTDSC; /**< Offset: 0x00 (R/W 32) Device DMA Channel Next Descriptor Address Register (n = 1) */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< Offset: 0x04 (R/W 32) Device DMA Channel Address Register (n = 1) */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< Offset: 0x08 (R/W 32) Device DMA Channel Control Register (n = 1) */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< Offset: 0x0C (R/W 32) Device DMA Channel Status Register (n = 1) */ +} usbhs_devdma_registers_t; + +/** \brief USBHS_HSTDMA register API structure */ +typedef struct +{ + __IO uint32_t USBHS_HSTDMANXTDSC; /**< Offset: 0x00 (R/W 32) Host DMA Channel Next Descriptor Address Register (n = 1) */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< Offset: 0x04 (R/W 32) Host DMA Channel Address Register (n = 1) */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< Offset: 0x08 (R/W 32) Host DMA Channel Control Register (n = 1) */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< Offset: 0x0C (R/W 32) Host DMA Channel Status Register (n = 1) */ +} usbhs_hstdma_registers_t; + +#define USBHS_DEVDMA_NUMBER _U_(7) + +#define USBHS_HSTDMA_NUMBER _U_(7) + +/** \brief USBHS register API structure */ +typedef struct +{ + __IO uint32_t USBHS_DEVCTRL; /**< Offset: 0x00 (R/W 32) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< Offset: 0x04 (R/ 32) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< Offset: 0x08 ( /W 32) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< Offset: 0x0C ( /W 32) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< Offset: 0x10 (R/ 32) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< Offset: 0x14 ( /W 32) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< Offset: 0x18 ( /W 32) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< Offset: 0x1C (R/W 32) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< Offset: 0x20 (R/ 32) Device Frame Number Register */ + __I uint8_t Reserved1[0xDC]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< Offset: 0x100 (R/W 32) Device Endpoint Configuration Register (n = 0) 0 */ + __I uint8_t Reserved2[0x08]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< Offset: 0x130 (R/ 32) Device Endpoint Status Register (n = 0) 0 */ + __I uint8_t Reserved3[0x08]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< Offset: 0x160 ( /W 32) Device Endpoint Clear Register (n = 0) 0 */ + __I uint8_t Reserved4[0x08]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< Offset: 0x190 ( /W 32) Device Endpoint Set Register (n = 0) 0 */ + __I uint8_t Reserved5[0x08]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< Offset: 0x1C0 (R/ 32) Device Endpoint Mask Register (n = 0) 0 */ + __I uint8_t Reserved6[0x08]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< Offset: 0x1F0 ( /W 32) Device Endpoint Enable Register (n = 0) 0 */ + __I uint8_t Reserved7[0x08]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< Offset: 0x220 ( /W 32) Device Endpoint Disable Register (n = 0) 0 */ + __I uint8_t Reserved8[0xC8]; + usbhs_devdma_registers_t USBHS_DEVDMA[USBHS_DEVDMA_NUMBER]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register (n = 1) */ + __I uint8_t Reserved9[0x80]; + __IO uint32_t USBHS_HSTCTRL; /**< Offset: 0x400 (R/W 32) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< Offset: 0x404 (R/ 32) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< Offset: 0x408 ( /W 32) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< Offset: 0x40C ( /W 32) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< Offset: 0x410 (R/ 32) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< Offset: 0x414 ( /W 32) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< Offset: 0x418 ( /W 32) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< Offset: 0x41C (R/W 32) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< Offset: 0x420 (R/W 32) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< Offset: 0x424 (R/W 32) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< Offset: 0x428 (R/W 32) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< Offset: 0x42C (R/W 32) Host Address 3 Register */ + __I uint8_t Reserved10[0xD0]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< Offset: 0x500 (R/W 32) Host Pipe Configuration Register (n = 0) 0 */ + __I uint8_t Reserved11[0x08]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< Offset: 0x530 (R/ 32) Host Pipe Status Register (n = 0) 0 */ + __I uint8_t Reserved12[0x08]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< Offset: 0x560 ( /W 32) Host Pipe Clear Register (n = 0) 0 */ + __I uint8_t Reserved13[0x08]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< Offset: 0x590 ( /W 32) Host Pipe Set Register (n = 0) 0 */ + __I uint8_t Reserved14[0x08]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< Offset: 0x5C0 (R/ 32) Host Pipe Mask Register (n = 0) 0 */ + __I uint8_t Reserved15[0x08]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< Offset: 0x5F0 ( /W 32) Host Pipe Enable Register (n = 0) 0 */ + __I uint8_t Reserved16[0x08]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< Offset: 0x620 ( /W 32) Host Pipe Disable Register (n = 0) 0 */ + __I uint8_t Reserved17[0x08]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< Offset: 0x650 (R/W 32) Host Pipe IN Request Register (n = 0) 0 */ + __I uint8_t Reserved18[0x08]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< Offset: 0x680 (R/W 32) Host Pipe Error Register (n = 0) 0 */ + __I uint8_t Reserved19[0x68]; + usbhs_hstdma_registers_t USBHS_HSTDMA[USBHS_HSTDMA_NUMBER]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register (n = 1) */ + __I uint8_t Reserved20[0x80]; + __IO uint32_t USBHS_CTRL; /**< Offset: 0x800 (R/W 32) General Control Register */ + __I uint32_t USBHS_SR; /**< Offset: 0x804 (R/ 32) General Status Register */ + __O uint32_t USBHS_SCR; /**< Offset: 0x808 ( /W 32) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< Offset: 0x80C ( /W 32) General Status Set Register */ +} usbhs_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_USBHS_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/utmi.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/utmi.h new file mode 100644 index 00000000..6a7ed37a --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/utmi.h @@ -0,0 +1,77 @@ +/** + * \brief Component description for UTMI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_UTMI_COMPONENT_H_ +#define _SAME70_UTMI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR UTMI */ +/* ************************************************************************** */ + +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0_Pos _U_(0) /**< (UTMI_OHCIICR) USB PORTx Reset Position */ +#define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */ +#define UTMI_OHCIICR_RES0(value) (UTMI_OHCIICR_RES0_Msk & ((value) << UTMI_OHCIICR_RES0_Pos)) +#define UTMI_OHCIICR_ARIE_Pos _U_(4) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */ +#define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */ +#define UTMI_OHCIICR_ARIE(value) (UTMI_OHCIICR_ARIE_Msk & ((value) << UTMI_OHCIICR_ARIE_Pos)) +#define UTMI_OHCIICR_APPSTART_Pos _U_(5) /**< (UTMI_OHCIICR) Reserved Position */ +#define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */ +#define UTMI_OHCIICR_APPSTART(value) (UTMI_OHCIICR_APPSTART_Msk & ((value) << UTMI_OHCIICR_APPSTART_Pos)) +#define UTMI_OHCIICR_UDPPUDIS_Pos _U_(23) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */ +#define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */ +#define UTMI_OHCIICR_UDPPUDIS(value) (UTMI_OHCIICR_UDPPUDIS_Msk & ((value) << UTMI_OHCIICR_UDPPUDIS_Pos)) +#define UTMI_OHCIICR_Msk _U_(0x00800031) /**< (UTMI_OHCIICR) Register Mask */ + +#define UTMI_OHCIICR_RES_Pos _U_(0) /**< (UTMI_OHCIICR Position) USB PORTx Reset */ +#define UTMI_OHCIICR_RES_Msk (_U_(0x1) << UTMI_OHCIICR_RES_Pos) /**< (UTMI_OHCIICR Mask) RES */ +#define UTMI_OHCIICR_RES(value) (UTMI_OHCIICR_RES_Msk & ((value) << UTMI_OHCIICR_RES_Pos)) + +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos _U_(0) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */ +#define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */ +#define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)) +#define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */ +#define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */ +#define UTMI_CKTRIM_Msk _U_(0x00000003) /**< (UTMI_CKTRIM) Register Mask */ + + +/** \brief UTMI register offsets definitions */ +#define UTMI_OHCIICR_REG_OFST (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */ +#define UTMI_CKTRIM_REG_OFST (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UTMI register API structure */ +typedef struct +{ + __I uint8_t Reserved1[0x10]; + __IO uint32_t UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */ + __I uint8_t Reserved2[0x1C]; + __IO uint32_t UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */ +} utmi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_UTMI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/wdt.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/wdt.h new file mode 100644 index 00000000..d8a3aad3 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/wdt.h @@ -0,0 +1,94 @@ +/** + * \brief Component description for WDT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_WDT_COMPONENT_H_ +#define _SAME70_WDT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR WDT */ +/* ************************************************************************** */ + +/* -------- WDT_CR : (WDT Offset: 0x00) ( /W 32) Control Register -------- */ +#define WDT_CR_WDRSTT_Pos _U_(0) /**< (WDT_CR) Watchdog Restart Position */ +#define WDT_CR_WDRSTT_Msk (_U_(0x1) << WDT_CR_WDRSTT_Pos) /**< (WDT_CR) Watchdog Restart Mask */ +#define WDT_CR_WDRSTT(value) (WDT_CR_WDRSTT_Msk & ((value) << WDT_CR_WDRSTT_Pos)) +#define WDT_CR_KEY_Pos _U_(24) /**< (WDT_CR) Password Position */ +#define WDT_CR_KEY_Msk (_U_(0xFF) << WDT_CR_KEY_Pos) /**< (WDT_CR) Password Mask */ +#define WDT_CR_KEY(value) (WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)) +#define WDT_CR_KEY_PASSWD_Val _U_(0xA5) /**< (WDT_CR) Writing any other value in this field aborts the write operation. */ +#define WDT_CR_KEY_PASSWD (WDT_CR_KEY_PASSWD_Val << WDT_CR_KEY_Pos) /**< (WDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define WDT_CR_Msk _U_(0xFF000001) /**< (WDT_CR) Register Mask */ + + +/* -------- WDT_MR : (WDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#define WDT_MR_WDV_Pos _U_(0) /**< (WDT_MR) Watchdog Counter Value Position */ +#define WDT_MR_WDV_Msk (_U_(0xFFF) << WDT_MR_WDV_Pos) /**< (WDT_MR) Watchdog Counter Value Mask */ +#define WDT_MR_WDV(value) (WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)) +#define WDT_MR_WDFIEN_Pos _U_(12) /**< (WDT_MR) Watchdog Fault Interrupt Enable Position */ +#define WDT_MR_WDFIEN_Msk (_U_(0x1) << WDT_MR_WDFIEN_Pos) /**< (WDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define WDT_MR_WDFIEN(value) (WDT_MR_WDFIEN_Msk & ((value) << WDT_MR_WDFIEN_Pos)) +#define WDT_MR_WDRSTEN_Pos _U_(13) /**< (WDT_MR) Watchdog Reset Enable Position */ +#define WDT_MR_WDRSTEN_Msk (_U_(0x1) << WDT_MR_WDRSTEN_Pos) /**< (WDT_MR) Watchdog Reset Enable Mask */ +#define WDT_MR_WDRSTEN(value) (WDT_MR_WDRSTEN_Msk & ((value) << WDT_MR_WDRSTEN_Pos)) +#define WDT_MR_WDDIS_Pos _U_(15) /**< (WDT_MR) Watchdog Disable Position */ +#define WDT_MR_WDDIS_Msk (_U_(0x1) << WDT_MR_WDDIS_Pos) /**< (WDT_MR) Watchdog Disable Mask */ +#define WDT_MR_WDDIS(value) (WDT_MR_WDDIS_Msk & ((value) << WDT_MR_WDDIS_Pos)) +#define WDT_MR_WDD_Pos _U_(16) /**< (WDT_MR) Watchdog Delta Value Position */ +#define WDT_MR_WDD_Msk (_U_(0xFFF) << WDT_MR_WDD_Pos) /**< (WDT_MR) Watchdog Delta Value Mask */ +#define WDT_MR_WDD(value) (WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)) +#define WDT_MR_WDDBGHLT_Pos _U_(28) /**< (WDT_MR) Watchdog Debug Halt Position */ +#define WDT_MR_WDDBGHLT_Msk (_U_(0x1) << WDT_MR_WDDBGHLT_Pos) /**< (WDT_MR) Watchdog Debug Halt Mask */ +#define WDT_MR_WDDBGHLT(value) (WDT_MR_WDDBGHLT_Msk & ((value) << WDT_MR_WDDBGHLT_Pos)) +#define WDT_MR_WDIDLEHLT_Pos _U_(29) /**< (WDT_MR) Watchdog Idle Halt Position */ +#define WDT_MR_WDIDLEHLT_Msk (_U_(0x1) << WDT_MR_WDIDLEHLT_Pos) /**< (WDT_MR) Watchdog Idle Halt Mask */ +#define WDT_MR_WDIDLEHLT(value) (WDT_MR_WDIDLEHLT_Msk & ((value) << WDT_MR_WDIDLEHLT_Pos)) +#define WDT_MR_Msk _U_(0x3FFFBFFF) /**< (WDT_MR) Register Mask */ + + +/* -------- WDT_SR : (WDT Offset: 0x08) ( R/ 32) Status Register -------- */ +#define WDT_SR_WDUNF_Pos _U_(0) /**< (WDT_SR) Watchdog Underflow (cleared on read) Position */ +#define WDT_SR_WDUNF_Msk (_U_(0x1) << WDT_SR_WDUNF_Pos) /**< (WDT_SR) Watchdog Underflow (cleared on read) Mask */ +#define WDT_SR_WDUNF(value) (WDT_SR_WDUNF_Msk & ((value) << WDT_SR_WDUNF_Pos)) +#define WDT_SR_WDERR_Pos _U_(1) /**< (WDT_SR) Watchdog Error (cleared on read) Position */ +#define WDT_SR_WDERR_Msk (_U_(0x1) << WDT_SR_WDERR_Pos) /**< (WDT_SR) Watchdog Error (cleared on read) Mask */ +#define WDT_SR_WDERR(value) (WDT_SR_WDERR_Msk & ((value) << WDT_SR_WDERR_Pos)) +#define WDT_SR_Msk _U_(0x00000003) /**< (WDT_SR) Register Mask */ + + +/** \brief WDT register offsets definitions */ +#define WDT_CR_REG_OFST (0x00) /**< (WDT_CR) Control Register Offset */ +#define WDT_MR_REG_OFST (0x04) /**< (WDT_MR) Mode Register Offset */ +#define WDT_SR_REG_OFST (0x08) /**< (WDT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief WDT register API structure */ +typedef struct +{ + __O uint32_t WDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t WDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t WDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} wdt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_WDT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/component/xdmac.h b/arch/arm/SAME70/SAME70A/mcu/inc/component/xdmac.h new file mode 100644 index 00000000..7cb4b3e6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/component/xdmac.h @@ -0,0 +1,1590 @@ +/** + * \brief Component description for XDMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70_XDMAC_COMPONENT_H_ +#define _SAME70_XDMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR XDMAC */ +/* ************************************************************************** */ + +/* -------- XDMAC_CIE : (XDMAC Offset: 0x00) ( /W 32) Channel Interrupt Enable Register (chid = 0) -------- */ +#define XDMAC_CIE_BIE_Pos _U_(0) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Position */ +#define XDMAC_CIE_BIE_Msk (_U_(0x1) << XDMAC_CIE_BIE_Pos) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Mask */ +#define XDMAC_CIE_BIE(value) (XDMAC_CIE_BIE_Msk & ((value) << XDMAC_CIE_BIE_Pos)) +#define XDMAC_CIE_LIE_Pos _U_(1) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Position */ +#define XDMAC_CIE_LIE_Msk (_U_(0x1) << XDMAC_CIE_LIE_Pos) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Mask */ +#define XDMAC_CIE_LIE(value) (XDMAC_CIE_LIE_Msk & ((value) << XDMAC_CIE_LIE_Pos)) +#define XDMAC_CIE_DIE_Pos _U_(2) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Position */ +#define XDMAC_CIE_DIE_Msk (_U_(0x1) << XDMAC_CIE_DIE_Pos) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Mask */ +#define XDMAC_CIE_DIE(value) (XDMAC_CIE_DIE_Msk & ((value) << XDMAC_CIE_DIE_Pos)) +#define XDMAC_CIE_FIE_Pos _U_(3) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Position */ +#define XDMAC_CIE_FIE_Msk (_U_(0x1) << XDMAC_CIE_FIE_Pos) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Mask */ +#define XDMAC_CIE_FIE(value) (XDMAC_CIE_FIE_Msk & ((value) << XDMAC_CIE_FIE_Pos)) +#define XDMAC_CIE_RBIE_Pos _U_(4) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_RBIE_Msk (_U_(0x1) << XDMAC_CIE_RBIE_Pos) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_RBIE(value) (XDMAC_CIE_RBIE_Msk & ((value) << XDMAC_CIE_RBIE_Pos)) +#define XDMAC_CIE_WBIE_Pos _U_(5) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_WBIE_Msk (_U_(0x1) << XDMAC_CIE_WBIE_Pos) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_WBIE(value) (XDMAC_CIE_WBIE_Msk & ((value) << XDMAC_CIE_WBIE_Pos)) +#define XDMAC_CIE_ROIE_Pos _U_(6) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_ROIE_Msk (_U_(0x1) << XDMAC_CIE_ROIE_Pos) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_ROIE(value) (XDMAC_CIE_ROIE_Msk & ((value) << XDMAC_CIE_ROIE_Pos)) +#define XDMAC_CIE_Msk _U_(0x0000007F) /**< (XDMAC_CIE) Register Mask */ + + +/* -------- XDMAC_CID : (XDMAC Offset: 0x04) ( /W 32) Channel Interrupt Disable Register (chid = 0) -------- */ +#define XDMAC_CID_BID_Pos _U_(0) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Position */ +#define XDMAC_CID_BID_Msk (_U_(0x1) << XDMAC_CID_BID_Pos) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Mask */ +#define XDMAC_CID_BID(value) (XDMAC_CID_BID_Msk & ((value) << XDMAC_CID_BID_Pos)) +#define XDMAC_CID_LID_Pos _U_(1) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Position */ +#define XDMAC_CID_LID_Msk (_U_(0x1) << XDMAC_CID_LID_Pos) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Mask */ +#define XDMAC_CID_LID(value) (XDMAC_CID_LID_Msk & ((value) << XDMAC_CID_LID_Pos)) +#define XDMAC_CID_DID_Pos _U_(2) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Position */ +#define XDMAC_CID_DID_Msk (_U_(0x1) << XDMAC_CID_DID_Pos) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Mask */ +#define XDMAC_CID_DID(value) (XDMAC_CID_DID_Msk & ((value) << XDMAC_CID_DID_Pos)) +#define XDMAC_CID_FID_Pos _U_(3) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Position */ +#define XDMAC_CID_FID_Msk (_U_(0x1) << XDMAC_CID_FID_Pos) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Mask */ +#define XDMAC_CID_FID(value) (XDMAC_CID_FID_Msk & ((value) << XDMAC_CID_FID_Pos)) +#define XDMAC_CID_RBEID_Pos _U_(4) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_RBEID_Msk (_U_(0x1) << XDMAC_CID_RBEID_Pos) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_RBEID(value) (XDMAC_CID_RBEID_Msk & ((value) << XDMAC_CID_RBEID_Pos)) +#define XDMAC_CID_WBEID_Pos _U_(5) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_WBEID_Msk (_U_(0x1) << XDMAC_CID_WBEID_Pos) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_WBEID(value) (XDMAC_CID_WBEID_Msk & ((value) << XDMAC_CID_WBEID_Pos)) +#define XDMAC_CID_ROID_Pos _U_(6) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Position */ +#define XDMAC_CID_ROID_Msk (_U_(0x1) << XDMAC_CID_ROID_Pos) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_ROID(value) (XDMAC_CID_ROID_Msk & ((value) << XDMAC_CID_ROID_Pos)) +#define XDMAC_CID_Msk _U_(0x0000007F) /**< (XDMAC_CID) Register Mask */ + + +/* -------- XDMAC_CIM : (XDMAC Offset: 0x08) ( R/ 32) Channel Interrupt Mask Register (chid = 0) -------- */ +#define XDMAC_CIM_BIM_Pos _U_(0) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Position */ +#define XDMAC_CIM_BIM_Msk (_U_(0x1) << XDMAC_CIM_BIM_Pos) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Mask */ +#define XDMAC_CIM_BIM(value) (XDMAC_CIM_BIM_Msk & ((value) << XDMAC_CIM_BIM_Pos)) +#define XDMAC_CIM_LIM_Pos _U_(1) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Position */ +#define XDMAC_CIM_LIM_Msk (_U_(0x1) << XDMAC_CIM_LIM_Pos) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Mask */ +#define XDMAC_CIM_LIM(value) (XDMAC_CIM_LIM_Msk & ((value) << XDMAC_CIM_LIM_Pos)) +#define XDMAC_CIM_DIM_Pos _U_(2) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Position */ +#define XDMAC_CIM_DIM_Msk (_U_(0x1) << XDMAC_CIM_DIM_Pos) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Mask */ +#define XDMAC_CIM_DIM(value) (XDMAC_CIM_DIM_Msk & ((value) << XDMAC_CIM_DIM_Pos)) +#define XDMAC_CIM_FIM_Pos _U_(3) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Position */ +#define XDMAC_CIM_FIM_Msk (_U_(0x1) << XDMAC_CIM_FIM_Pos) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Mask */ +#define XDMAC_CIM_FIM(value) (XDMAC_CIM_FIM_Msk & ((value) << XDMAC_CIM_FIM_Pos)) +#define XDMAC_CIM_RBEIM_Pos _U_(4) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_RBEIM_Msk (_U_(0x1) << XDMAC_CIM_RBEIM_Pos) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_RBEIM(value) (XDMAC_CIM_RBEIM_Msk & ((value) << XDMAC_CIM_RBEIM_Pos)) +#define XDMAC_CIM_WBEIM_Pos _U_(5) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_WBEIM_Msk (_U_(0x1) << XDMAC_CIM_WBEIM_Pos) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_WBEIM(value) (XDMAC_CIM_WBEIM_Msk & ((value) << XDMAC_CIM_WBEIM_Pos)) +#define XDMAC_CIM_ROIM_Pos _U_(6) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_ROIM_Msk (_U_(0x1) << XDMAC_CIM_ROIM_Pos) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_ROIM(value) (XDMAC_CIM_ROIM_Msk & ((value) << XDMAC_CIM_ROIM_Pos)) +#define XDMAC_CIM_Msk _U_(0x0000007F) /**< (XDMAC_CIM) Register Mask */ + + +/* -------- XDMAC_CIS : (XDMAC Offset: 0x0C) ( R/ 32) Channel Interrupt Status Register (chid = 0) -------- */ +#define XDMAC_CIS_BIS_Pos _U_(0) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Position */ +#define XDMAC_CIS_BIS_Msk (_U_(0x1) << XDMAC_CIS_BIS_Pos) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Mask */ +#define XDMAC_CIS_BIS(value) (XDMAC_CIS_BIS_Msk & ((value) << XDMAC_CIS_BIS_Pos)) +#define XDMAC_CIS_LIS_Pos _U_(1) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Position */ +#define XDMAC_CIS_LIS_Msk (_U_(0x1) << XDMAC_CIS_LIS_Pos) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Mask */ +#define XDMAC_CIS_LIS(value) (XDMAC_CIS_LIS_Msk & ((value) << XDMAC_CIS_LIS_Pos)) +#define XDMAC_CIS_DIS_Pos _U_(2) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Position */ +#define XDMAC_CIS_DIS_Msk (_U_(0x1) << XDMAC_CIS_DIS_Pos) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Mask */ +#define XDMAC_CIS_DIS(value) (XDMAC_CIS_DIS_Msk & ((value) << XDMAC_CIS_DIS_Pos)) +#define XDMAC_CIS_FIS_Pos _U_(3) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Position */ +#define XDMAC_CIS_FIS_Msk (_U_(0x1) << XDMAC_CIS_FIS_Pos) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Mask */ +#define XDMAC_CIS_FIS(value) (XDMAC_CIS_FIS_Msk & ((value) << XDMAC_CIS_FIS_Pos)) +#define XDMAC_CIS_RBEIS_Pos _U_(4) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_RBEIS_Msk (_U_(0x1) << XDMAC_CIS_RBEIS_Pos) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_RBEIS(value) (XDMAC_CIS_RBEIS_Msk & ((value) << XDMAC_CIS_RBEIS_Pos)) +#define XDMAC_CIS_WBEIS_Pos _U_(5) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_WBEIS_Msk (_U_(0x1) << XDMAC_CIS_WBEIS_Pos) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_WBEIS(value) (XDMAC_CIS_WBEIS_Msk & ((value) << XDMAC_CIS_WBEIS_Pos)) +#define XDMAC_CIS_ROIS_Pos _U_(6) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Position */ +#define XDMAC_CIS_ROIS_Msk (_U_(0x1) << XDMAC_CIS_ROIS_Pos) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_ROIS(value) (XDMAC_CIS_ROIS_Msk & ((value) << XDMAC_CIS_ROIS_Pos)) +#define XDMAC_CIS_Msk _U_(0x0000007F) /**< (XDMAC_CIS) Register Mask */ + + +/* -------- XDMAC_CSA : (XDMAC Offset: 0x10) (R/W 32) Channel Source Address Register (chid = 0) -------- */ +#define XDMAC_CSA_SA_Pos _U_(0) /**< (XDMAC_CSA) Channel x Source Address Position */ +#define XDMAC_CSA_SA_Msk (_U_(0xFFFFFFFF) << XDMAC_CSA_SA_Pos) /**< (XDMAC_CSA) Channel x Source Address Mask */ +#define XDMAC_CSA_SA(value) (XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)) +#define XDMAC_CSA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CSA) Register Mask */ + + +/* -------- XDMAC_CDA : (XDMAC Offset: 0x14) (R/W 32) Channel Destination Address Register (chid = 0) -------- */ +#define XDMAC_CDA_DA_Pos _U_(0) /**< (XDMAC_CDA) Channel x Destination Address Position */ +#define XDMAC_CDA_DA_Msk (_U_(0xFFFFFFFF) << XDMAC_CDA_DA_Pos) /**< (XDMAC_CDA) Channel x Destination Address Mask */ +#define XDMAC_CDA_DA(value) (XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)) +#define XDMAC_CDA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDA) Register Mask */ + + +/* -------- XDMAC_CNDA : (XDMAC Offset: 0x18) (R/W 32) Channel Next Descriptor Address Register (chid = 0) -------- */ +#define XDMAC_CNDA_NDAIF_Pos _U_(0) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Position */ +#define XDMAC_CNDA_NDAIF_Msk (_U_(0x1) << XDMAC_CNDA_NDAIF_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Mask */ +#define XDMAC_CNDA_NDAIF(value) (XDMAC_CNDA_NDAIF_Msk & ((value) << XDMAC_CNDA_NDAIF_Pos)) +#define XDMAC_CNDA_NDA_Pos _U_(2) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Position */ +#define XDMAC_CNDA_NDA_Msk (_U_(0x3FFFFFFF) << XDMAC_CNDA_NDA_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Mask */ +#define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)) +#define XDMAC_CNDA_Msk _U_(0xFFFFFFFD) /**< (XDMAC_CNDA) Register Mask */ + + +/* -------- XDMAC_CNDC : (XDMAC Offset: 0x1C) (R/W 32) Channel Next Descriptor Control Register (chid = 0) -------- */ +#define XDMAC_CNDC_NDE_Pos _U_(0) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Position */ +#define XDMAC_CNDC_NDE_Msk (_U_(0x1) << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Mask */ +#define XDMAC_CNDC_NDE(value) (XDMAC_CNDC_NDE_Msk & ((value) << XDMAC_CNDC_NDE_Pos)) +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val _U_(0x0) /**< (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val _U_(0x1) /**< (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is disabled. Position */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is enabled. Position */ +#define XDMAC_CNDC_NDSUP_Pos _U_(1) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Position */ +#define XDMAC_CNDC_NDSUP_Msk (_U_(0x1) << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Mask */ +#define XDMAC_CNDC_NDSUP(value) (XDMAC_CNDC_NDSUP_Msk & ((value) << XDMAC_CNDC_NDSUP_Pos)) +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDDUP_Pos _U_(2) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Position */ +#define XDMAC_CNDC_NDDUP_Msk (_U_(0x1) << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Mask */ +#define XDMAC_CNDC_NDDUP(value) (XDMAC_CNDC_NDDUP_Msk & ((value) << XDMAC_CNDC_NDDUP_Pos)) +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDVIEW_Pos _U_(3) /**< (XDMAC_CNDC) Channel x Next Descriptor View Position */ +#define XDMAC_CNDC_NDVIEW_Msk (_U_(0x3) << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor View Mask */ +#define XDMAC_CNDC_NDVIEW(value) (XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)) +#define XDMAC_CNDC_NDVIEW_NDV0_Val _U_(0x0) /**< (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1_Val _U_(0x1) /**< (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2_Val _U_(0x2) /**< (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3_Val _U_(0x3) /**< (XDMAC_CNDC) Next Descriptor View 3 */ +#define XDMAC_CNDC_NDVIEW_NDV0 (XDMAC_CNDC_NDVIEW_NDV0_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 0 Position */ +#define XDMAC_CNDC_NDVIEW_NDV1 (XDMAC_CNDC_NDVIEW_NDV1_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 1 Position */ +#define XDMAC_CNDC_NDVIEW_NDV2 (XDMAC_CNDC_NDVIEW_NDV2_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 2 Position */ +#define XDMAC_CNDC_NDVIEW_NDV3 (XDMAC_CNDC_NDVIEW_NDV3_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 3 Position */ +#define XDMAC_CNDC_Msk _U_(0x0000001F) /**< (XDMAC_CNDC) Register Mask */ + + +/* -------- XDMAC_CUBC : (XDMAC Offset: 0x20) (R/W 32) Channel Microblock Control Register (chid = 0) -------- */ +#define XDMAC_CUBC_UBLEN_Pos _U_(0) /**< (XDMAC_CUBC) Channel x Microblock Length Position */ +#define XDMAC_CUBC_UBLEN_Msk (_U_(0xFFFFFF) << XDMAC_CUBC_UBLEN_Pos) /**< (XDMAC_CUBC) Channel x Microblock Length Mask */ +#define XDMAC_CUBC_UBLEN(value) (XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)) +#define XDMAC_CUBC_Msk _U_(0x00FFFFFF) /**< (XDMAC_CUBC) Register Mask */ + + +/* -------- XDMAC_CBC : (XDMAC Offset: 0x24) (R/W 32) Channel Block Control Register (chid = 0) -------- */ +#define XDMAC_CBC_BLEN_Pos _U_(0) /**< (XDMAC_CBC) Channel x Block Length Position */ +#define XDMAC_CBC_BLEN_Msk (_U_(0xFFF) << XDMAC_CBC_BLEN_Pos) /**< (XDMAC_CBC) Channel x Block Length Mask */ +#define XDMAC_CBC_BLEN(value) (XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)) +#define XDMAC_CBC_Msk _U_(0x00000FFF) /**< (XDMAC_CBC) Register Mask */ + + +/* -------- XDMAC_CC : (XDMAC Offset: 0x28) (R/W 32) Channel Configuration Register (chid = 0) -------- */ +#define XDMAC_CC_TYPE_Pos _U_(0) /**< (XDMAC_CC) Channel x Transfer Type Position */ +#define XDMAC_CC_TYPE_Msk (_U_(0x1) << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Channel x Transfer Type Mask */ +#define XDMAC_CC_TYPE(value) (XDMAC_CC_TYPE_Msk & ((value) << XDMAC_CC_TYPE_Pos)) +#define XDMAC_CC_TYPE_MEM_TRAN_Val _U_(0x0) /**< (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN_Val _U_(0x1) /**< (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_TYPE_MEM_TRAN (XDMAC_CC_TYPE_MEM_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). Position */ +#define XDMAC_CC_TYPE_PER_TRAN (XDMAC_CC_TYPE_PER_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). Position */ +#define XDMAC_CC_MBSIZE_Pos _U_(1) /**< (XDMAC_CC) Channel x Memory Burst Size Position */ +#define XDMAC_CC_MBSIZE_Msk (_U_(0x3) << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) Channel x Memory Burst Size Mask */ +#define XDMAC_CC_MBSIZE(value) (XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)) +#define XDMAC_CC_MBSIZE_SINGLE_Val _U_(0x0) /**< (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR_Val _U_(0x1) /**< (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT_Val _U_(0x2) /**< (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN_Val _U_(0x3) /**< (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_MBSIZE_SINGLE (XDMAC_CC_MBSIZE_SINGLE_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to one. Position */ +#define XDMAC_CC_MBSIZE_FOUR (XDMAC_CC_MBSIZE_FOUR_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to four. Position */ +#define XDMAC_CC_MBSIZE_EIGHT (XDMAC_CC_MBSIZE_EIGHT_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to eight. Position */ +#define XDMAC_CC_MBSIZE_SIXTEEN (XDMAC_CC_MBSIZE_SIXTEEN_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to sixteen. Position */ +#define XDMAC_CC_DSYNC_Pos _U_(4) /**< (XDMAC_CC) Channel x Synchronization Position */ +#define XDMAC_CC_DSYNC_Msk (_U_(0x1) << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Channel x Synchronization Mask */ +#define XDMAC_CC_DSYNC(value) (XDMAC_CC_DSYNC_Msk & ((value) << XDMAC_CC_DSYNC_Pos)) +#define XDMAC_CC_DSYNC_PER2MEM_Val _U_(0x0) /**< (XDMAC_CC) Peripheral to Memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER_Val _U_(0x1) /**< (XDMAC_CC) Memory to Peripheral transfer. */ +#define XDMAC_CC_DSYNC_PER2MEM (XDMAC_CC_DSYNC_PER2MEM_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Peripheral to Memory transfer. Position */ +#define XDMAC_CC_DSYNC_MEM2PER (XDMAC_CC_DSYNC_MEM2PER_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Memory to Peripheral transfer. Position */ +#define XDMAC_CC_SWREQ_Pos _U_(6) /**< (XDMAC_CC) Channel x Software Request Trigger Position */ +#define XDMAC_CC_SWREQ_Msk (_U_(0x1) << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Channel x Software Request Trigger Mask */ +#define XDMAC_CC_SWREQ(value) (XDMAC_CC_SWREQ_Msk & ((value) << XDMAC_CC_SWREQ_Pos)) +#define XDMAC_CC_SWREQ_HWR_CONNECTED_Val _U_(0x0) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED_Val _U_(0x1) /**< (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (XDMAC_CC_SWREQ_HWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. Position */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (XDMAC_CC_SWREQ_SWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Software request is connected to the peripheral request line. Position */ +#define XDMAC_CC_MEMSET_Pos _U_(7) /**< (XDMAC_CC) Channel x Fill Block of memory Position */ +#define XDMAC_CC_MEMSET_Msk (_U_(0x1) << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Channel x Fill Block of memory Mask */ +#define XDMAC_CC_MEMSET(value) (XDMAC_CC_MEMSET_Msk & ((value) << XDMAC_CC_MEMSET_Pos)) +#define XDMAC_CC_MEMSET_NORMAL_MODE_Val _U_(0x0) /**< (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE_Val _U_(0x1) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (XDMAC_CC_MEMSET_NORMAL_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Memset is not activated. Position */ +#define XDMAC_CC_MEMSET_HW_MODE (XDMAC_CC_MEMSET_HW_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. Position */ +#define XDMAC_CC_CSIZE_Pos _U_(8) /**< (XDMAC_CC) Channel x Chunk Size Position */ +#define XDMAC_CC_CSIZE_Msk (_U_(0x7) << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) Channel x Chunk Size Mask */ +#define XDMAC_CC_CSIZE(value) (XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)) +#define XDMAC_CC_CSIZE_CHK_1_Val _U_(0x0) /**< (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2_Val _U_(0x1) /**< (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4_Val _U_(0x2) /**< (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8_Val _U_(0x3) /**< (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16_Val _U_(0x4) /**< (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_CSIZE_CHK_1 (XDMAC_CC_CSIZE_CHK_1_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 1 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_2 (XDMAC_CC_CSIZE_CHK_2_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 2 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_4 (XDMAC_CC_CSIZE_CHK_4_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 4 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_8 (XDMAC_CC_CSIZE_CHK_8_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 8 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_16 (XDMAC_CC_CSIZE_CHK_16_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 16 data transferred Position */ +#define XDMAC_CC_DWIDTH_Pos _U_(11) /**< (XDMAC_CC) Channel x Data Width Position */ +#define XDMAC_CC_DWIDTH_Msk (_U_(0x3) << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) Channel x Data Width Mask */ +#define XDMAC_CC_DWIDTH(value) (XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)) +#define XDMAC_CC_DWIDTH_BYTE_Val _U_(0x0) /**< (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD_Val _U_(0x1) /**< (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD_Val _U_(0x2) /**< (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_DWIDTH_BYTE (XDMAC_CC_DWIDTH_BYTE_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 8 bits Position */ +#define XDMAC_CC_DWIDTH_HALFWORD (XDMAC_CC_DWIDTH_HALFWORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 16 bits Position */ +#define XDMAC_CC_DWIDTH_WORD (XDMAC_CC_DWIDTH_WORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 32 bits Position */ +#define XDMAC_CC_SIF_Pos _U_(13) /**< (XDMAC_CC) Channel x Source Interface Identifier Position */ +#define XDMAC_CC_SIF_Msk (_U_(0x1) << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) Channel x Source Interface Identifier Mask */ +#define XDMAC_CC_SIF(value) (XDMAC_CC_SIF_Msk & ((value) << XDMAC_CC_SIF_Pos)) +#define XDMAC_CC_SIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_SIF_AHB_IF0 (XDMAC_CC_SIF_AHB_IF0_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 0. Position */ +#define XDMAC_CC_SIF_AHB_IF1 (XDMAC_CC_SIF_AHB_IF1_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 1. Position */ +#define XDMAC_CC_DIF_Pos _U_(14) /**< (XDMAC_CC) Channel x Destination Interface Identifier Position */ +#define XDMAC_CC_DIF_Msk (_U_(0x1) << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) Channel x Destination Interface Identifier Mask */ +#define XDMAC_CC_DIF(value) (XDMAC_CC_DIF_Msk & ((value) << XDMAC_CC_DIF_Pos)) +#define XDMAC_CC_DIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_DIF_AHB_IF0 (XDMAC_CC_DIF_AHB_IF0_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written through the system bus interface 0. Position */ +#define XDMAC_CC_DIF_AHB_IF1 (XDMAC_CC_DIF_AHB_IF1_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written though the system bus interface 1. Position */ +#define XDMAC_CC_SAM_Pos _U_(16) /**< (XDMAC_CC) Channel x Source Addressing Mode Position */ +#define XDMAC_CC_SAM_Msk (_U_(0x3) << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) Channel x Source Addressing Mode Mask */ +#define XDMAC_CC_SAM(value) (XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)) +#define XDMAC_CC_SAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_SAM_FIXED_AM (XDMAC_CC_SAM_FIXED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_SAM_INCREMENTED_AM (XDMAC_CC_SAM_INCREMENTED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_SAM_UBS_AM (XDMAC_CC_SAM_UBS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_SAM_UBS_DS_AM (XDMAC_CC_SAM_UBS_DS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Position */ +#define XDMAC_CC_DAM_Pos _U_(18) /**< (XDMAC_CC) Channel x Destination Addressing Mode Position */ +#define XDMAC_CC_DAM_Msk (_U_(0x3) << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) Channel x Destination Addressing Mode Mask */ +#define XDMAC_CC_DAM(value) (XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)) +#define XDMAC_CC_DAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_FIXED_AM (XDMAC_CC_DAM_FIXED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_DAM_INCREMENTED_AM (XDMAC_CC_DAM_INCREMENTED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_DAM_UBS_AM (XDMAC_CC_DAM_UBS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_DAM_UBS_DS_AM (XDMAC_CC_DAM_UBS_DS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Position */ +#define XDMAC_CC_INITD_Pos _U_(21) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Position */ +#define XDMAC_CC_INITD_Msk (_U_(0x1) << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Mask */ +#define XDMAC_CC_INITD(value) (XDMAC_CC_INITD_Msk & ((value) << XDMAC_CC_INITD_Pos)) +#define XDMAC_CC_INITD_IN_PROGRESS_Val _U_(0x0) /**< (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_TERMINATED_Val _U_(0x1) /**< (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_INITD_IN_PROGRESS (XDMAC_CC_INITD_IN_PROGRESS_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is in progress. Position */ +#define XDMAC_CC_INITD_TERMINATED (XDMAC_CC_INITD_TERMINATED_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is completed. Position */ +#define XDMAC_CC_RDIP_Pos _U_(22) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Position */ +#define XDMAC_CC_RDIP_Msk (_U_(0x1) << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_RDIP(value) (XDMAC_CC_RDIP_Msk & ((value) << XDMAC_CC_RDIP_Pos)) +#define XDMAC_CC_RDIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_RDIP_DONE (XDMAC_CC_RDIP_DONE_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) No Active read transaction on the bus. Position */ +#define XDMAC_CC_RDIP_IN_PROGRESS (XDMAC_CC_RDIP_IN_PROGRESS_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) A read transaction is in progress. Position */ +#define XDMAC_CC_WRIP_Pos _U_(23) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Position */ +#define XDMAC_CC_WRIP_Msk (_U_(0x1) << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_WRIP(value) (XDMAC_CC_WRIP_Msk & ((value) << XDMAC_CC_WRIP_Pos)) +#define XDMAC_CC_WRIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_WRIP_DONE (XDMAC_CC_WRIP_DONE_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) No Active write transaction on the bus. Position */ +#define XDMAC_CC_WRIP_IN_PROGRESS (XDMAC_CC_WRIP_IN_PROGRESS_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) A Write transaction is in progress. Position */ +#define XDMAC_CC_PERID_Pos _U_(24) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Position */ +#define XDMAC_CC_PERID_Msk (_U_(0x7F) << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Mask */ +#define XDMAC_CC_PERID(value) (XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)) +#define XDMAC_CC_Msk _U_(0x7FEF7FD7) /**< (XDMAC_CC) Register Mask */ + + +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: 0x2C) (R/W 32) Channel Data Stride Memory Set Pattern (chid = 0) -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos _U_(0) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_SDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_SDS_MSP(value) (XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)) +#define XDMAC_CDS_MSP_DDS_MSP_Pos _U_(16) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_DDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_DDS_MSP(value) (XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)) +#define XDMAC_CDS_MSP_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDS_MSP) Register Mask */ + + +/* -------- XDMAC_CSUS : (XDMAC Offset: 0x30) (R/W 32) Channel Source Microblock Stride (chid = 0) -------- */ +#define XDMAC_CSUS_SUBS_Pos _U_(0) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Position */ +#define XDMAC_CSUS_SUBS_Msk (_U_(0xFFFFFF) << XDMAC_CSUS_SUBS_Pos) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Mask */ +#define XDMAC_CSUS_SUBS(value) (XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)) +#define XDMAC_CSUS_Msk _U_(0x00FFFFFF) /**< (XDMAC_CSUS) Register Mask */ + + +/* -------- XDMAC_CDUS : (XDMAC Offset: 0x34) (R/W 32) Channel Destination Microblock Stride (chid = 0) -------- */ +#define XDMAC_CDUS_DUBS_Pos _U_(0) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Position */ +#define XDMAC_CDUS_DUBS_Msk (_U_(0xFFFFFF) << XDMAC_CDUS_DUBS_Pos) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Mask */ +#define XDMAC_CDUS_DUBS(value) (XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)) +#define XDMAC_CDUS_Msk _U_(0x00FFFFFF) /**< (XDMAC_CDUS) Register Mask */ + + +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) ( R/ 32) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos _U_(0) /**< (XDMAC_GTYPE) Number of Channels Minus One Position */ +#define XDMAC_GTYPE_NB_CH_Msk (_U_(0x1F) << XDMAC_GTYPE_NB_CH_Pos) /**< (XDMAC_GTYPE) Number of Channels Minus One Mask */ +#define XDMAC_GTYPE_NB_CH(value) (XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)) +#define XDMAC_GTYPE_FIFO_SZ_Pos _U_(5) /**< (XDMAC_GTYPE) Number of Bytes Position */ +#define XDMAC_GTYPE_FIFO_SZ_Msk (_U_(0x7FF) << XDMAC_GTYPE_FIFO_SZ_Pos) /**< (XDMAC_GTYPE) Number of Bytes Mask */ +#define XDMAC_GTYPE_FIFO_SZ(value) (XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)) +#define XDMAC_GTYPE_NB_REQ_Pos _U_(16) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Position */ +#define XDMAC_GTYPE_NB_REQ_Msk (_U_(0x7F) << XDMAC_GTYPE_NB_REQ_Pos) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Mask */ +#define XDMAC_GTYPE_NB_REQ(value) (XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)) +#define XDMAC_GTYPE_Msk _U_(0x007FFFFF) /**< (XDMAC_GTYPE) Register Mask */ + + +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) (R/W 32) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG_Pos _U_(0) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISREG_Msk (_U_(0x1) << XDMAC_GCFG_CGDISREG_Pos) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISREG(value) (XDMAC_GCFG_CGDISREG_Msk & ((value) << XDMAC_GCFG_CGDISREG_Pos)) +#define XDMAC_GCFG_CGDISPIPE_Pos _U_(1) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISPIPE_Msk (_U_(0x1) << XDMAC_GCFG_CGDISPIPE_Pos) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISPIPE(value) (XDMAC_GCFG_CGDISPIPE_Msk & ((value) << XDMAC_GCFG_CGDISPIPE_Pos)) +#define XDMAC_GCFG_CGDISFIFO_Pos _U_(2) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISFIFO_Msk (_U_(0x1) << XDMAC_GCFG_CGDISFIFO_Pos) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISFIFO(value) (XDMAC_GCFG_CGDISFIFO_Msk & ((value) << XDMAC_GCFG_CGDISFIFO_Pos)) +#define XDMAC_GCFG_CGDISIF_Pos _U_(3) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISIF_Msk (_U_(0x1) << XDMAC_GCFG_CGDISIF_Pos) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISIF(value) (XDMAC_GCFG_CGDISIF_Msk & ((value) << XDMAC_GCFG_CGDISIF_Pos)) +#define XDMAC_GCFG_BXKBEN_Pos _U_(8) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Position */ +#define XDMAC_GCFG_BXKBEN_Msk (_U_(0x1) << XDMAC_GCFG_BXKBEN_Pos) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Mask */ +#define XDMAC_GCFG_BXKBEN(value) (XDMAC_GCFG_BXKBEN_Msk & ((value) << XDMAC_GCFG_BXKBEN_Pos)) +#define XDMAC_GCFG_Msk _U_(0x0000010F) /**< (XDMAC_GCFG) Register Mask */ + + +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) (R/W 32) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos _U_(0) /**< (XDMAC_GWAC) Pool Weight 0 Position */ +#define XDMAC_GWAC_PW0_Msk (_U_(0xF) << XDMAC_GWAC_PW0_Pos) /**< (XDMAC_GWAC) Pool Weight 0 Mask */ +#define XDMAC_GWAC_PW0(value) (XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)) +#define XDMAC_GWAC_PW1_Pos _U_(4) /**< (XDMAC_GWAC) Pool Weight 1 Position */ +#define XDMAC_GWAC_PW1_Msk (_U_(0xF) << XDMAC_GWAC_PW1_Pos) /**< (XDMAC_GWAC) Pool Weight 1 Mask */ +#define XDMAC_GWAC_PW1(value) (XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)) +#define XDMAC_GWAC_PW2_Pos _U_(8) /**< (XDMAC_GWAC) Pool Weight 2 Position */ +#define XDMAC_GWAC_PW2_Msk (_U_(0xF) << XDMAC_GWAC_PW2_Pos) /**< (XDMAC_GWAC) Pool Weight 2 Mask */ +#define XDMAC_GWAC_PW2(value) (XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)) +#define XDMAC_GWAC_PW3_Pos _U_(12) /**< (XDMAC_GWAC) Pool Weight 3 Position */ +#define XDMAC_GWAC_PW3_Msk (_U_(0xF) << XDMAC_GWAC_PW3_Pos) /**< (XDMAC_GWAC) Pool Weight 3 Mask */ +#define XDMAC_GWAC_PW3(value) (XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)) +#define XDMAC_GWAC_Msk _U_(0x0000FFFF) /**< (XDMAC_GWAC) Register Mask */ + + +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) ( /W 32) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0_Pos _U_(0) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE0_Msk (_U_(0x1) << XDMAC_GIE_IE0_Pos) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE0(value) (XDMAC_GIE_IE0_Msk & ((value) << XDMAC_GIE_IE0_Pos)) +#define XDMAC_GIE_IE1_Pos _U_(1) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE1_Msk (_U_(0x1) << XDMAC_GIE_IE1_Pos) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE1(value) (XDMAC_GIE_IE1_Msk & ((value) << XDMAC_GIE_IE1_Pos)) +#define XDMAC_GIE_IE2_Pos _U_(2) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE2_Msk (_U_(0x1) << XDMAC_GIE_IE2_Pos) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE2(value) (XDMAC_GIE_IE2_Msk & ((value) << XDMAC_GIE_IE2_Pos)) +#define XDMAC_GIE_IE3_Pos _U_(3) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE3_Msk (_U_(0x1) << XDMAC_GIE_IE3_Pos) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE3(value) (XDMAC_GIE_IE3_Msk & ((value) << XDMAC_GIE_IE3_Pos)) +#define XDMAC_GIE_IE4_Pos _U_(4) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE4_Msk (_U_(0x1) << XDMAC_GIE_IE4_Pos) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE4(value) (XDMAC_GIE_IE4_Msk & ((value) << XDMAC_GIE_IE4_Pos)) +#define XDMAC_GIE_IE5_Pos _U_(5) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE5_Msk (_U_(0x1) << XDMAC_GIE_IE5_Pos) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE5(value) (XDMAC_GIE_IE5_Msk & ((value) << XDMAC_GIE_IE5_Pos)) +#define XDMAC_GIE_IE6_Pos _U_(6) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE6_Msk (_U_(0x1) << XDMAC_GIE_IE6_Pos) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE6(value) (XDMAC_GIE_IE6_Msk & ((value) << XDMAC_GIE_IE6_Pos)) +#define XDMAC_GIE_IE7_Pos _U_(7) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE7_Msk (_U_(0x1) << XDMAC_GIE_IE7_Pos) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE7(value) (XDMAC_GIE_IE7_Msk & ((value) << XDMAC_GIE_IE7_Pos)) +#define XDMAC_GIE_IE8_Pos _U_(8) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE8_Msk (_U_(0x1) << XDMAC_GIE_IE8_Pos) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE8(value) (XDMAC_GIE_IE8_Msk & ((value) << XDMAC_GIE_IE8_Pos)) +#define XDMAC_GIE_IE9_Pos _U_(9) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE9_Msk (_U_(0x1) << XDMAC_GIE_IE9_Pos) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE9(value) (XDMAC_GIE_IE9_Msk & ((value) << XDMAC_GIE_IE9_Pos)) +#define XDMAC_GIE_IE10_Pos _U_(10) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE10_Msk (_U_(0x1) << XDMAC_GIE_IE10_Pos) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE10(value) (XDMAC_GIE_IE10_Msk & ((value) << XDMAC_GIE_IE10_Pos)) +#define XDMAC_GIE_IE11_Pos _U_(11) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE11_Msk (_U_(0x1) << XDMAC_GIE_IE11_Pos) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE11(value) (XDMAC_GIE_IE11_Msk & ((value) << XDMAC_GIE_IE11_Pos)) +#define XDMAC_GIE_IE12_Pos _U_(12) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE12_Msk (_U_(0x1) << XDMAC_GIE_IE12_Pos) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE12(value) (XDMAC_GIE_IE12_Msk & ((value) << XDMAC_GIE_IE12_Pos)) +#define XDMAC_GIE_IE13_Pos _U_(13) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE13_Msk (_U_(0x1) << XDMAC_GIE_IE13_Pos) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE13(value) (XDMAC_GIE_IE13_Msk & ((value) << XDMAC_GIE_IE13_Pos)) +#define XDMAC_GIE_IE14_Pos _U_(14) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE14_Msk (_U_(0x1) << XDMAC_GIE_IE14_Pos) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE14(value) (XDMAC_GIE_IE14_Msk & ((value) << XDMAC_GIE_IE14_Pos)) +#define XDMAC_GIE_IE15_Pos _U_(15) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE15_Msk (_U_(0x1) << XDMAC_GIE_IE15_Pos) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE15(value) (XDMAC_GIE_IE15_Msk & ((value) << XDMAC_GIE_IE15_Pos)) +#define XDMAC_GIE_IE16_Pos _U_(16) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE16_Msk (_U_(0x1) << XDMAC_GIE_IE16_Pos) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE16(value) (XDMAC_GIE_IE16_Msk & ((value) << XDMAC_GIE_IE16_Pos)) +#define XDMAC_GIE_IE17_Pos _U_(17) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE17_Msk (_U_(0x1) << XDMAC_GIE_IE17_Pos) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE17(value) (XDMAC_GIE_IE17_Msk & ((value) << XDMAC_GIE_IE17_Pos)) +#define XDMAC_GIE_IE18_Pos _U_(18) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE18_Msk (_U_(0x1) << XDMAC_GIE_IE18_Pos) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE18(value) (XDMAC_GIE_IE18_Msk & ((value) << XDMAC_GIE_IE18_Pos)) +#define XDMAC_GIE_IE19_Pos _U_(19) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE19_Msk (_U_(0x1) << XDMAC_GIE_IE19_Pos) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE19(value) (XDMAC_GIE_IE19_Msk & ((value) << XDMAC_GIE_IE19_Pos)) +#define XDMAC_GIE_IE20_Pos _U_(20) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE20_Msk (_U_(0x1) << XDMAC_GIE_IE20_Pos) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE20(value) (XDMAC_GIE_IE20_Msk & ((value) << XDMAC_GIE_IE20_Pos)) +#define XDMAC_GIE_IE21_Pos _U_(21) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE21_Msk (_U_(0x1) << XDMAC_GIE_IE21_Pos) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE21(value) (XDMAC_GIE_IE21_Msk & ((value) << XDMAC_GIE_IE21_Pos)) +#define XDMAC_GIE_IE22_Pos _U_(22) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE22_Msk (_U_(0x1) << XDMAC_GIE_IE22_Pos) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE22(value) (XDMAC_GIE_IE22_Msk & ((value) << XDMAC_GIE_IE22_Pos)) +#define XDMAC_GIE_IE23_Pos _U_(23) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE23_Msk (_U_(0x1) << XDMAC_GIE_IE23_Pos) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE23(value) (XDMAC_GIE_IE23_Msk & ((value) << XDMAC_GIE_IE23_Pos)) +#define XDMAC_GIE_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIE) Register Mask */ + +#define XDMAC_GIE_IE_Pos _U_(0) /**< (XDMAC_GIE Position) XDMAC Channel 23 Interrupt Enable Bit */ +#define XDMAC_GIE_IE_Msk (_U_(0xFFFFFF) << XDMAC_GIE_IE_Pos) /**< (XDMAC_GIE Mask) IE */ +#define XDMAC_GIE_IE(value) (XDMAC_GIE_IE_Msk & ((value) << XDMAC_GIE_IE_Pos)) + +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) ( /W 32) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0_Pos _U_(0) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID0_Msk (_U_(0x1) << XDMAC_GID_ID0_Pos) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID0(value) (XDMAC_GID_ID0_Msk & ((value) << XDMAC_GID_ID0_Pos)) +#define XDMAC_GID_ID1_Pos _U_(1) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID1_Msk (_U_(0x1) << XDMAC_GID_ID1_Pos) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID1(value) (XDMAC_GID_ID1_Msk & ((value) << XDMAC_GID_ID1_Pos)) +#define XDMAC_GID_ID2_Pos _U_(2) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID2_Msk (_U_(0x1) << XDMAC_GID_ID2_Pos) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID2(value) (XDMAC_GID_ID2_Msk & ((value) << XDMAC_GID_ID2_Pos)) +#define XDMAC_GID_ID3_Pos _U_(3) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID3_Msk (_U_(0x1) << XDMAC_GID_ID3_Pos) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID3(value) (XDMAC_GID_ID3_Msk & ((value) << XDMAC_GID_ID3_Pos)) +#define XDMAC_GID_ID4_Pos _U_(4) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID4_Msk (_U_(0x1) << XDMAC_GID_ID4_Pos) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID4(value) (XDMAC_GID_ID4_Msk & ((value) << XDMAC_GID_ID4_Pos)) +#define XDMAC_GID_ID5_Pos _U_(5) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID5_Msk (_U_(0x1) << XDMAC_GID_ID5_Pos) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID5(value) (XDMAC_GID_ID5_Msk & ((value) << XDMAC_GID_ID5_Pos)) +#define XDMAC_GID_ID6_Pos _U_(6) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID6_Msk (_U_(0x1) << XDMAC_GID_ID6_Pos) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID6(value) (XDMAC_GID_ID6_Msk & ((value) << XDMAC_GID_ID6_Pos)) +#define XDMAC_GID_ID7_Pos _U_(7) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID7_Msk (_U_(0x1) << XDMAC_GID_ID7_Pos) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID7(value) (XDMAC_GID_ID7_Msk & ((value) << XDMAC_GID_ID7_Pos)) +#define XDMAC_GID_ID8_Pos _U_(8) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID8_Msk (_U_(0x1) << XDMAC_GID_ID8_Pos) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID8(value) (XDMAC_GID_ID8_Msk & ((value) << XDMAC_GID_ID8_Pos)) +#define XDMAC_GID_ID9_Pos _U_(9) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID9_Msk (_U_(0x1) << XDMAC_GID_ID9_Pos) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID9(value) (XDMAC_GID_ID9_Msk & ((value) << XDMAC_GID_ID9_Pos)) +#define XDMAC_GID_ID10_Pos _U_(10) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID10_Msk (_U_(0x1) << XDMAC_GID_ID10_Pos) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID10(value) (XDMAC_GID_ID10_Msk & ((value) << XDMAC_GID_ID10_Pos)) +#define XDMAC_GID_ID11_Pos _U_(11) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID11_Msk (_U_(0x1) << XDMAC_GID_ID11_Pos) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID11(value) (XDMAC_GID_ID11_Msk & ((value) << XDMAC_GID_ID11_Pos)) +#define XDMAC_GID_ID12_Pos _U_(12) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID12_Msk (_U_(0x1) << XDMAC_GID_ID12_Pos) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID12(value) (XDMAC_GID_ID12_Msk & ((value) << XDMAC_GID_ID12_Pos)) +#define XDMAC_GID_ID13_Pos _U_(13) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID13_Msk (_U_(0x1) << XDMAC_GID_ID13_Pos) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID13(value) (XDMAC_GID_ID13_Msk & ((value) << XDMAC_GID_ID13_Pos)) +#define XDMAC_GID_ID14_Pos _U_(14) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID14_Msk (_U_(0x1) << XDMAC_GID_ID14_Pos) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID14(value) (XDMAC_GID_ID14_Msk & ((value) << XDMAC_GID_ID14_Pos)) +#define XDMAC_GID_ID15_Pos _U_(15) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID15_Msk (_U_(0x1) << XDMAC_GID_ID15_Pos) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID15(value) (XDMAC_GID_ID15_Msk & ((value) << XDMAC_GID_ID15_Pos)) +#define XDMAC_GID_ID16_Pos _U_(16) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID16_Msk (_U_(0x1) << XDMAC_GID_ID16_Pos) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID16(value) (XDMAC_GID_ID16_Msk & ((value) << XDMAC_GID_ID16_Pos)) +#define XDMAC_GID_ID17_Pos _U_(17) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID17_Msk (_U_(0x1) << XDMAC_GID_ID17_Pos) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID17(value) (XDMAC_GID_ID17_Msk & ((value) << XDMAC_GID_ID17_Pos)) +#define XDMAC_GID_ID18_Pos _U_(18) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID18_Msk (_U_(0x1) << XDMAC_GID_ID18_Pos) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID18(value) (XDMAC_GID_ID18_Msk & ((value) << XDMAC_GID_ID18_Pos)) +#define XDMAC_GID_ID19_Pos _U_(19) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID19_Msk (_U_(0x1) << XDMAC_GID_ID19_Pos) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID19(value) (XDMAC_GID_ID19_Msk & ((value) << XDMAC_GID_ID19_Pos)) +#define XDMAC_GID_ID20_Pos _U_(20) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID20_Msk (_U_(0x1) << XDMAC_GID_ID20_Pos) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID20(value) (XDMAC_GID_ID20_Msk & ((value) << XDMAC_GID_ID20_Pos)) +#define XDMAC_GID_ID21_Pos _U_(21) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID21_Msk (_U_(0x1) << XDMAC_GID_ID21_Pos) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID21(value) (XDMAC_GID_ID21_Msk & ((value) << XDMAC_GID_ID21_Pos)) +#define XDMAC_GID_ID22_Pos _U_(22) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID22_Msk (_U_(0x1) << XDMAC_GID_ID22_Pos) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID22(value) (XDMAC_GID_ID22_Msk & ((value) << XDMAC_GID_ID22_Pos)) +#define XDMAC_GID_ID23_Pos _U_(23) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID23_Msk (_U_(0x1) << XDMAC_GID_ID23_Pos) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID23(value) (XDMAC_GID_ID23_Msk & ((value) << XDMAC_GID_ID23_Pos)) +#define XDMAC_GID_Msk _U_(0x00FFFFFF) /**< (XDMAC_GID) Register Mask */ + +#define XDMAC_GID_ID_Pos _U_(0) /**< (XDMAC_GID Position) XDMAC Channel 23 Interrupt Disable Bit */ +#define XDMAC_GID_ID_Msk (_U_(0xFFFFFF) << XDMAC_GID_ID_Pos) /**< (XDMAC_GID Mask) ID */ +#define XDMAC_GID_ID(value) (XDMAC_GID_ID_Msk & ((value) << XDMAC_GID_ID_Pos)) + +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) ( R/ 32) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0_Pos _U_(0) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM0_Msk (_U_(0x1) << XDMAC_GIM_IM0_Pos) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM0(value) (XDMAC_GIM_IM0_Msk & ((value) << XDMAC_GIM_IM0_Pos)) +#define XDMAC_GIM_IM1_Pos _U_(1) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM1_Msk (_U_(0x1) << XDMAC_GIM_IM1_Pos) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM1(value) (XDMAC_GIM_IM1_Msk & ((value) << XDMAC_GIM_IM1_Pos)) +#define XDMAC_GIM_IM2_Pos _U_(2) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM2_Msk (_U_(0x1) << XDMAC_GIM_IM2_Pos) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM2(value) (XDMAC_GIM_IM2_Msk & ((value) << XDMAC_GIM_IM2_Pos)) +#define XDMAC_GIM_IM3_Pos _U_(3) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM3_Msk (_U_(0x1) << XDMAC_GIM_IM3_Pos) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM3(value) (XDMAC_GIM_IM3_Msk & ((value) << XDMAC_GIM_IM3_Pos)) +#define XDMAC_GIM_IM4_Pos _U_(4) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM4_Msk (_U_(0x1) << XDMAC_GIM_IM4_Pos) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM4(value) (XDMAC_GIM_IM4_Msk & ((value) << XDMAC_GIM_IM4_Pos)) +#define XDMAC_GIM_IM5_Pos _U_(5) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM5_Msk (_U_(0x1) << XDMAC_GIM_IM5_Pos) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM5(value) (XDMAC_GIM_IM5_Msk & ((value) << XDMAC_GIM_IM5_Pos)) +#define XDMAC_GIM_IM6_Pos _U_(6) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM6_Msk (_U_(0x1) << XDMAC_GIM_IM6_Pos) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM6(value) (XDMAC_GIM_IM6_Msk & ((value) << XDMAC_GIM_IM6_Pos)) +#define XDMAC_GIM_IM7_Pos _U_(7) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM7_Msk (_U_(0x1) << XDMAC_GIM_IM7_Pos) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM7(value) (XDMAC_GIM_IM7_Msk & ((value) << XDMAC_GIM_IM7_Pos)) +#define XDMAC_GIM_IM8_Pos _U_(8) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM8_Msk (_U_(0x1) << XDMAC_GIM_IM8_Pos) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM8(value) (XDMAC_GIM_IM8_Msk & ((value) << XDMAC_GIM_IM8_Pos)) +#define XDMAC_GIM_IM9_Pos _U_(9) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM9_Msk (_U_(0x1) << XDMAC_GIM_IM9_Pos) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM9(value) (XDMAC_GIM_IM9_Msk & ((value) << XDMAC_GIM_IM9_Pos)) +#define XDMAC_GIM_IM10_Pos _U_(10) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM10_Msk (_U_(0x1) << XDMAC_GIM_IM10_Pos) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM10(value) (XDMAC_GIM_IM10_Msk & ((value) << XDMAC_GIM_IM10_Pos)) +#define XDMAC_GIM_IM11_Pos _U_(11) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM11_Msk (_U_(0x1) << XDMAC_GIM_IM11_Pos) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM11(value) (XDMAC_GIM_IM11_Msk & ((value) << XDMAC_GIM_IM11_Pos)) +#define XDMAC_GIM_IM12_Pos _U_(12) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM12_Msk (_U_(0x1) << XDMAC_GIM_IM12_Pos) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM12(value) (XDMAC_GIM_IM12_Msk & ((value) << XDMAC_GIM_IM12_Pos)) +#define XDMAC_GIM_IM13_Pos _U_(13) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM13_Msk (_U_(0x1) << XDMAC_GIM_IM13_Pos) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM13(value) (XDMAC_GIM_IM13_Msk & ((value) << XDMAC_GIM_IM13_Pos)) +#define XDMAC_GIM_IM14_Pos _U_(14) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM14_Msk (_U_(0x1) << XDMAC_GIM_IM14_Pos) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM14(value) (XDMAC_GIM_IM14_Msk & ((value) << XDMAC_GIM_IM14_Pos)) +#define XDMAC_GIM_IM15_Pos _U_(15) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM15_Msk (_U_(0x1) << XDMAC_GIM_IM15_Pos) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM15(value) (XDMAC_GIM_IM15_Msk & ((value) << XDMAC_GIM_IM15_Pos)) +#define XDMAC_GIM_IM16_Pos _U_(16) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM16_Msk (_U_(0x1) << XDMAC_GIM_IM16_Pos) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM16(value) (XDMAC_GIM_IM16_Msk & ((value) << XDMAC_GIM_IM16_Pos)) +#define XDMAC_GIM_IM17_Pos _U_(17) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM17_Msk (_U_(0x1) << XDMAC_GIM_IM17_Pos) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM17(value) (XDMAC_GIM_IM17_Msk & ((value) << XDMAC_GIM_IM17_Pos)) +#define XDMAC_GIM_IM18_Pos _U_(18) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM18_Msk (_U_(0x1) << XDMAC_GIM_IM18_Pos) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM18(value) (XDMAC_GIM_IM18_Msk & ((value) << XDMAC_GIM_IM18_Pos)) +#define XDMAC_GIM_IM19_Pos _U_(19) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM19_Msk (_U_(0x1) << XDMAC_GIM_IM19_Pos) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM19(value) (XDMAC_GIM_IM19_Msk & ((value) << XDMAC_GIM_IM19_Pos)) +#define XDMAC_GIM_IM20_Pos _U_(20) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM20_Msk (_U_(0x1) << XDMAC_GIM_IM20_Pos) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM20(value) (XDMAC_GIM_IM20_Msk & ((value) << XDMAC_GIM_IM20_Pos)) +#define XDMAC_GIM_IM21_Pos _U_(21) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM21_Msk (_U_(0x1) << XDMAC_GIM_IM21_Pos) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM21(value) (XDMAC_GIM_IM21_Msk & ((value) << XDMAC_GIM_IM21_Pos)) +#define XDMAC_GIM_IM22_Pos _U_(22) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM22_Msk (_U_(0x1) << XDMAC_GIM_IM22_Pos) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM22(value) (XDMAC_GIM_IM22_Msk & ((value) << XDMAC_GIM_IM22_Pos)) +#define XDMAC_GIM_IM23_Pos _U_(23) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM23_Msk (_U_(0x1) << XDMAC_GIM_IM23_Pos) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM23(value) (XDMAC_GIM_IM23_Msk & ((value) << XDMAC_GIM_IM23_Pos)) +#define XDMAC_GIM_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIM) Register Mask */ + +#define XDMAC_GIM_IM_Pos _U_(0) /**< (XDMAC_GIM Position) XDMAC Channel 23 Interrupt Mask Bit */ +#define XDMAC_GIM_IM_Msk (_U_(0xFFFFFF) << XDMAC_GIM_IM_Pos) /**< (XDMAC_GIM Mask) IM */ +#define XDMAC_GIM_IM(value) (XDMAC_GIM_IM_Msk & ((value) << XDMAC_GIM_IM_Pos)) + +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) ( R/ 32) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0_Pos _U_(0) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS0_Msk (_U_(0x1) << XDMAC_GIS_IS0_Pos) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS0(value) (XDMAC_GIS_IS0_Msk & ((value) << XDMAC_GIS_IS0_Pos)) +#define XDMAC_GIS_IS1_Pos _U_(1) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS1_Msk (_U_(0x1) << XDMAC_GIS_IS1_Pos) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS1(value) (XDMAC_GIS_IS1_Msk & ((value) << XDMAC_GIS_IS1_Pos)) +#define XDMAC_GIS_IS2_Pos _U_(2) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS2_Msk (_U_(0x1) << XDMAC_GIS_IS2_Pos) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS2(value) (XDMAC_GIS_IS2_Msk & ((value) << XDMAC_GIS_IS2_Pos)) +#define XDMAC_GIS_IS3_Pos _U_(3) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS3_Msk (_U_(0x1) << XDMAC_GIS_IS3_Pos) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS3(value) (XDMAC_GIS_IS3_Msk & ((value) << XDMAC_GIS_IS3_Pos)) +#define XDMAC_GIS_IS4_Pos _U_(4) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS4_Msk (_U_(0x1) << XDMAC_GIS_IS4_Pos) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS4(value) (XDMAC_GIS_IS4_Msk & ((value) << XDMAC_GIS_IS4_Pos)) +#define XDMAC_GIS_IS5_Pos _U_(5) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS5_Msk (_U_(0x1) << XDMAC_GIS_IS5_Pos) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS5(value) (XDMAC_GIS_IS5_Msk & ((value) << XDMAC_GIS_IS5_Pos)) +#define XDMAC_GIS_IS6_Pos _U_(6) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS6_Msk (_U_(0x1) << XDMAC_GIS_IS6_Pos) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS6(value) (XDMAC_GIS_IS6_Msk & ((value) << XDMAC_GIS_IS6_Pos)) +#define XDMAC_GIS_IS7_Pos _U_(7) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS7_Msk (_U_(0x1) << XDMAC_GIS_IS7_Pos) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS7(value) (XDMAC_GIS_IS7_Msk & ((value) << XDMAC_GIS_IS7_Pos)) +#define XDMAC_GIS_IS8_Pos _U_(8) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS8_Msk (_U_(0x1) << XDMAC_GIS_IS8_Pos) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS8(value) (XDMAC_GIS_IS8_Msk & ((value) << XDMAC_GIS_IS8_Pos)) +#define XDMAC_GIS_IS9_Pos _U_(9) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS9_Msk (_U_(0x1) << XDMAC_GIS_IS9_Pos) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS9(value) (XDMAC_GIS_IS9_Msk & ((value) << XDMAC_GIS_IS9_Pos)) +#define XDMAC_GIS_IS10_Pos _U_(10) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS10_Msk (_U_(0x1) << XDMAC_GIS_IS10_Pos) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS10(value) (XDMAC_GIS_IS10_Msk & ((value) << XDMAC_GIS_IS10_Pos)) +#define XDMAC_GIS_IS11_Pos _U_(11) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS11_Msk (_U_(0x1) << XDMAC_GIS_IS11_Pos) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS11(value) (XDMAC_GIS_IS11_Msk & ((value) << XDMAC_GIS_IS11_Pos)) +#define XDMAC_GIS_IS12_Pos _U_(12) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS12_Msk (_U_(0x1) << XDMAC_GIS_IS12_Pos) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS12(value) (XDMAC_GIS_IS12_Msk & ((value) << XDMAC_GIS_IS12_Pos)) +#define XDMAC_GIS_IS13_Pos _U_(13) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS13_Msk (_U_(0x1) << XDMAC_GIS_IS13_Pos) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS13(value) (XDMAC_GIS_IS13_Msk & ((value) << XDMAC_GIS_IS13_Pos)) +#define XDMAC_GIS_IS14_Pos _U_(14) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS14_Msk (_U_(0x1) << XDMAC_GIS_IS14_Pos) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS14(value) (XDMAC_GIS_IS14_Msk & ((value) << XDMAC_GIS_IS14_Pos)) +#define XDMAC_GIS_IS15_Pos _U_(15) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS15_Msk (_U_(0x1) << XDMAC_GIS_IS15_Pos) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS15(value) (XDMAC_GIS_IS15_Msk & ((value) << XDMAC_GIS_IS15_Pos)) +#define XDMAC_GIS_IS16_Pos _U_(16) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS16_Msk (_U_(0x1) << XDMAC_GIS_IS16_Pos) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS16(value) (XDMAC_GIS_IS16_Msk & ((value) << XDMAC_GIS_IS16_Pos)) +#define XDMAC_GIS_IS17_Pos _U_(17) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS17_Msk (_U_(0x1) << XDMAC_GIS_IS17_Pos) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS17(value) (XDMAC_GIS_IS17_Msk & ((value) << XDMAC_GIS_IS17_Pos)) +#define XDMAC_GIS_IS18_Pos _U_(18) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS18_Msk (_U_(0x1) << XDMAC_GIS_IS18_Pos) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS18(value) (XDMAC_GIS_IS18_Msk & ((value) << XDMAC_GIS_IS18_Pos)) +#define XDMAC_GIS_IS19_Pos _U_(19) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS19_Msk (_U_(0x1) << XDMAC_GIS_IS19_Pos) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS19(value) (XDMAC_GIS_IS19_Msk & ((value) << XDMAC_GIS_IS19_Pos)) +#define XDMAC_GIS_IS20_Pos _U_(20) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS20_Msk (_U_(0x1) << XDMAC_GIS_IS20_Pos) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS20(value) (XDMAC_GIS_IS20_Msk & ((value) << XDMAC_GIS_IS20_Pos)) +#define XDMAC_GIS_IS21_Pos _U_(21) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS21_Msk (_U_(0x1) << XDMAC_GIS_IS21_Pos) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS21(value) (XDMAC_GIS_IS21_Msk & ((value) << XDMAC_GIS_IS21_Pos)) +#define XDMAC_GIS_IS22_Pos _U_(22) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS22_Msk (_U_(0x1) << XDMAC_GIS_IS22_Pos) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS22(value) (XDMAC_GIS_IS22_Msk & ((value) << XDMAC_GIS_IS22_Pos)) +#define XDMAC_GIS_IS23_Pos _U_(23) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS23_Msk (_U_(0x1) << XDMAC_GIS_IS23_Pos) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS23(value) (XDMAC_GIS_IS23_Msk & ((value) << XDMAC_GIS_IS23_Pos)) +#define XDMAC_GIS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIS) Register Mask */ + +#define XDMAC_GIS_IS_Pos _U_(0) /**< (XDMAC_GIS Position) XDMAC Channel 23 Interrupt Status Bit */ +#define XDMAC_GIS_IS_Msk (_U_(0xFFFFFF) << XDMAC_GIS_IS_Pos) /**< (XDMAC_GIS Mask) IS */ +#define XDMAC_GIS_IS(value) (XDMAC_GIS_IS_Msk & ((value) << XDMAC_GIS_IS_Pos)) + +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) ( /W 32) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0_Pos _U_(0) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Position */ +#define XDMAC_GE_EN0_Msk (_U_(0x1) << XDMAC_GE_EN0_Pos) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Mask */ +#define XDMAC_GE_EN0(value) (XDMAC_GE_EN0_Msk & ((value) << XDMAC_GE_EN0_Pos)) +#define XDMAC_GE_EN1_Pos _U_(1) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Position */ +#define XDMAC_GE_EN1_Msk (_U_(0x1) << XDMAC_GE_EN1_Pos) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Mask */ +#define XDMAC_GE_EN1(value) (XDMAC_GE_EN1_Msk & ((value) << XDMAC_GE_EN1_Pos)) +#define XDMAC_GE_EN2_Pos _U_(2) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Position */ +#define XDMAC_GE_EN2_Msk (_U_(0x1) << XDMAC_GE_EN2_Pos) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Mask */ +#define XDMAC_GE_EN2(value) (XDMAC_GE_EN2_Msk & ((value) << XDMAC_GE_EN2_Pos)) +#define XDMAC_GE_EN3_Pos _U_(3) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Position */ +#define XDMAC_GE_EN3_Msk (_U_(0x1) << XDMAC_GE_EN3_Pos) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Mask */ +#define XDMAC_GE_EN3(value) (XDMAC_GE_EN3_Msk & ((value) << XDMAC_GE_EN3_Pos)) +#define XDMAC_GE_EN4_Pos _U_(4) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Position */ +#define XDMAC_GE_EN4_Msk (_U_(0x1) << XDMAC_GE_EN4_Pos) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Mask */ +#define XDMAC_GE_EN4(value) (XDMAC_GE_EN4_Msk & ((value) << XDMAC_GE_EN4_Pos)) +#define XDMAC_GE_EN5_Pos _U_(5) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Position */ +#define XDMAC_GE_EN5_Msk (_U_(0x1) << XDMAC_GE_EN5_Pos) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Mask */ +#define XDMAC_GE_EN5(value) (XDMAC_GE_EN5_Msk & ((value) << XDMAC_GE_EN5_Pos)) +#define XDMAC_GE_EN6_Pos _U_(6) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Position */ +#define XDMAC_GE_EN6_Msk (_U_(0x1) << XDMAC_GE_EN6_Pos) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Mask */ +#define XDMAC_GE_EN6(value) (XDMAC_GE_EN6_Msk & ((value) << XDMAC_GE_EN6_Pos)) +#define XDMAC_GE_EN7_Pos _U_(7) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Position */ +#define XDMAC_GE_EN7_Msk (_U_(0x1) << XDMAC_GE_EN7_Pos) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Mask */ +#define XDMAC_GE_EN7(value) (XDMAC_GE_EN7_Msk & ((value) << XDMAC_GE_EN7_Pos)) +#define XDMAC_GE_EN8_Pos _U_(8) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Position */ +#define XDMAC_GE_EN8_Msk (_U_(0x1) << XDMAC_GE_EN8_Pos) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Mask */ +#define XDMAC_GE_EN8(value) (XDMAC_GE_EN8_Msk & ((value) << XDMAC_GE_EN8_Pos)) +#define XDMAC_GE_EN9_Pos _U_(9) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Position */ +#define XDMAC_GE_EN9_Msk (_U_(0x1) << XDMAC_GE_EN9_Pos) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Mask */ +#define XDMAC_GE_EN9(value) (XDMAC_GE_EN9_Msk & ((value) << XDMAC_GE_EN9_Pos)) +#define XDMAC_GE_EN10_Pos _U_(10) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Position */ +#define XDMAC_GE_EN10_Msk (_U_(0x1) << XDMAC_GE_EN10_Pos) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Mask */ +#define XDMAC_GE_EN10(value) (XDMAC_GE_EN10_Msk & ((value) << XDMAC_GE_EN10_Pos)) +#define XDMAC_GE_EN11_Pos _U_(11) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Position */ +#define XDMAC_GE_EN11_Msk (_U_(0x1) << XDMAC_GE_EN11_Pos) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Mask */ +#define XDMAC_GE_EN11(value) (XDMAC_GE_EN11_Msk & ((value) << XDMAC_GE_EN11_Pos)) +#define XDMAC_GE_EN12_Pos _U_(12) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Position */ +#define XDMAC_GE_EN12_Msk (_U_(0x1) << XDMAC_GE_EN12_Pos) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Mask */ +#define XDMAC_GE_EN12(value) (XDMAC_GE_EN12_Msk & ((value) << XDMAC_GE_EN12_Pos)) +#define XDMAC_GE_EN13_Pos _U_(13) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Position */ +#define XDMAC_GE_EN13_Msk (_U_(0x1) << XDMAC_GE_EN13_Pos) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Mask */ +#define XDMAC_GE_EN13(value) (XDMAC_GE_EN13_Msk & ((value) << XDMAC_GE_EN13_Pos)) +#define XDMAC_GE_EN14_Pos _U_(14) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Position */ +#define XDMAC_GE_EN14_Msk (_U_(0x1) << XDMAC_GE_EN14_Pos) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Mask */ +#define XDMAC_GE_EN14(value) (XDMAC_GE_EN14_Msk & ((value) << XDMAC_GE_EN14_Pos)) +#define XDMAC_GE_EN15_Pos _U_(15) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Position */ +#define XDMAC_GE_EN15_Msk (_U_(0x1) << XDMAC_GE_EN15_Pos) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Mask */ +#define XDMAC_GE_EN15(value) (XDMAC_GE_EN15_Msk & ((value) << XDMAC_GE_EN15_Pos)) +#define XDMAC_GE_EN16_Pos _U_(16) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Position */ +#define XDMAC_GE_EN16_Msk (_U_(0x1) << XDMAC_GE_EN16_Pos) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Mask */ +#define XDMAC_GE_EN16(value) (XDMAC_GE_EN16_Msk & ((value) << XDMAC_GE_EN16_Pos)) +#define XDMAC_GE_EN17_Pos _U_(17) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Position */ +#define XDMAC_GE_EN17_Msk (_U_(0x1) << XDMAC_GE_EN17_Pos) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Mask */ +#define XDMAC_GE_EN17(value) (XDMAC_GE_EN17_Msk & ((value) << XDMAC_GE_EN17_Pos)) +#define XDMAC_GE_EN18_Pos _U_(18) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Position */ +#define XDMAC_GE_EN18_Msk (_U_(0x1) << XDMAC_GE_EN18_Pos) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Mask */ +#define XDMAC_GE_EN18(value) (XDMAC_GE_EN18_Msk & ((value) << XDMAC_GE_EN18_Pos)) +#define XDMAC_GE_EN19_Pos _U_(19) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Position */ +#define XDMAC_GE_EN19_Msk (_U_(0x1) << XDMAC_GE_EN19_Pos) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Mask */ +#define XDMAC_GE_EN19(value) (XDMAC_GE_EN19_Msk & ((value) << XDMAC_GE_EN19_Pos)) +#define XDMAC_GE_EN20_Pos _U_(20) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Position */ +#define XDMAC_GE_EN20_Msk (_U_(0x1) << XDMAC_GE_EN20_Pos) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Mask */ +#define XDMAC_GE_EN20(value) (XDMAC_GE_EN20_Msk & ((value) << XDMAC_GE_EN20_Pos)) +#define XDMAC_GE_EN21_Pos _U_(21) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Position */ +#define XDMAC_GE_EN21_Msk (_U_(0x1) << XDMAC_GE_EN21_Pos) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Mask */ +#define XDMAC_GE_EN21(value) (XDMAC_GE_EN21_Msk & ((value) << XDMAC_GE_EN21_Pos)) +#define XDMAC_GE_EN22_Pos _U_(22) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Position */ +#define XDMAC_GE_EN22_Msk (_U_(0x1) << XDMAC_GE_EN22_Pos) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Mask */ +#define XDMAC_GE_EN22(value) (XDMAC_GE_EN22_Msk & ((value) << XDMAC_GE_EN22_Pos)) +#define XDMAC_GE_EN23_Pos _U_(23) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Position */ +#define XDMAC_GE_EN23_Msk (_U_(0x1) << XDMAC_GE_EN23_Pos) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Mask */ +#define XDMAC_GE_EN23(value) (XDMAC_GE_EN23_Msk & ((value) << XDMAC_GE_EN23_Pos)) +#define XDMAC_GE_Msk _U_(0x00FFFFFF) /**< (XDMAC_GE) Register Mask */ + +#define XDMAC_GE_EN_Pos _U_(0) /**< (XDMAC_GE Position) XDMAC Channel 23 Enable Bit */ +#define XDMAC_GE_EN_Msk (_U_(0xFFFFFF) << XDMAC_GE_EN_Pos) /**< (XDMAC_GE Mask) EN */ +#define XDMAC_GE_EN(value) (XDMAC_GE_EN_Msk & ((value) << XDMAC_GE_EN_Pos)) + +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) ( /W 32) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0_Pos _U_(0) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Position */ +#define XDMAC_GD_DI0_Msk (_U_(0x1) << XDMAC_GD_DI0_Pos) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Mask */ +#define XDMAC_GD_DI0(value) (XDMAC_GD_DI0_Msk & ((value) << XDMAC_GD_DI0_Pos)) +#define XDMAC_GD_DI1_Pos _U_(1) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Position */ +#define XDMAC_GD_DI1_Msk (_U_(0x1) << XDMAC_GD_DI1_Pos) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Mask */ +#define XDMAC_GD_DI1(value) (XDMAC_GD_DI1_Msk & ((value) << XDMAC_GD_DI1_Pos)) +#define XDMAC_GD_DI2_Pos _U_(2) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Position */ +#define XDMAC_GD_DI2_Msk (_U_(0x1) << XDMAC_GD_DI2_Pos) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Mask */ +#define XDMAC_GD_DI2(value) (XDMAC_GD_DI2_Msk & ((value) << XDMAC_GD_DI2_Pos)) +#define XDMAC_GD_DI3_Pos _U_(3) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Position */ +#define XDMAC_GD_DI3_Msk (_U_(0x1) << XDMAC_GD_DI3_Pos) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Mask */ +#define XDMAC_GD_DI3(value) (XDMAC_GD_DI3_Msk & ((value) << XDMAC_GD_DI3_Pos)) +#define XDMAC_GD_DI4_Pos _U_(4) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Position */ +#define XDMAC_GD_DI4_Msk (_U_(0x1) << XDMAC_GD_DI4_Pos) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Mask */ +#define XDMAC_GD_DI4(value) (XDMAC_GD_DI4_Msk & ((value) << XDMAC_GD_DI4_Pos)) +#define XDMAC_GD_DI5_Pos _U_(5) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Position */ +#define XDMAC_GD_DI5_Msk (_U_(0x1) << XDMAC_GD_DI5_Pos) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Mask */ +#define XDMAC_GD_DI5(value) (XDMAC_GD_DI5_Msk & ((value) << XDMAC_GD_DI5_Pos)) +#define XDMAC_GD_DI6_Pos _U_(6) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Position */ +#define XDMAC_GD_DI6_Msk (_U_(0x1) << XDMAC_GD_DI6_Pos) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Mask */ +#define XDMAC_GD_DI6(value) (XDMAC_GD_DI6_Msk & ((value) << XDMAC_GD_DI6_Pos)) +#define XDMAC_GD_DI7_Pos _U_(7) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Position */ +#define XDMAC_GD_DI7_Msk (_U_(0x1) << XDMAC_GD_DI7_Pos) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Mask */ +#define XDMAC_GD_DI7(value) (XDMAC_GD_DI7_Msk & ((value) << XDMAC_GD_DI7_Pos)) +#define XDMAC_GD_DI8_Pos _U_(8) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Position */ +#define XDMAC_GD_DI8_Msk (_U_(0x1) << XDMAC_GD_DI8_Pos) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Mask */ +#define XDMAC_GD_DI8(value) (XDMAC_GD_DI8_Msk & ((value) << XDMAC_GD_DI8_Pos)) +#define XDMAC_GD_DI9_Pos _U_(9) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Position */ +#define XDMAC_GD_DI9_Msk (_U_(0x1) << XDMAC_GD_DI9_Pos) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Mask */ +#define XDMAC_GD_DI9(value) (XDMAC_GD_DI9_Msk & ((value) << XDMAC_GD_DI9_Pos)) +#define XDMAC_GD_DI10_Pos _U_(10) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Position */ +#define XDMAC_GD_DI10_Msk (_U_(0x1) << XDMAC_GD_DI10_Pos) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Mask */ +#define XDMAC_GD_DI10(value) (XDMAC_GD_DI10_Msk & ((value) << XDMAC_GD_DI10_Pos)) +#define XDMAC_GD_DI11_Pos _U_(11) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Position */ +#define XDMAC_GD_DI11_Msk (_U_(0x1) << XDMAC_GD_DI11_Pos) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Mask */ +#define XDMAC_GD_DI11(value) (XDMAC_GD_DI11_Msk & ((value) << XDMAC_GD_DI11_Pos)) +#define XDMAC_GD_DI12_Pos _U_(12) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Position */ +#define XDMAC_GD_DI12_Msk (_U_(0x1) << XDMAC_GD_DI12_Pos) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Mask */ +#define XDMAC_GD_DI12(value) (XDMAC_GD_DI12_Msk & ((value) << XDMAC_GD_DI12_Pos)) +#define XDMAC_GD_DI13_Pos _U_(13) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Position */ +#define XDMAC_GD_DI13_Msk (_U_(0x1) << XDMAC_GD_DI13_Pos) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Mask */ +#define XDMAC_GD_DI13(value) (XDMAC_GD_DI13_Msk & ((value) << XDMAC_GD_DI13_Pos)) +#define XDMAC_GD_DI14_Pos _U_(14) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Position */ +#define XDMAC_GD_DI14_Msk (_U_(0x1) << XDMAC_GD_DI14_Pos) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Mask */ +#define XDMAC_GD_DI14(value) (XDMAC_GD_DI14_Msk & ((value) << XDMAC_GD_DI14_Pos)) +#define XDMAC_GD_DI15_Pos _U_(15) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Position */ +#define XDMAC_GD_DI15_Msk (_U_(0x1) << XDMAC_GD_DI15_Pos) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Mask */ +#define XDMAC_GD_DI15(value) (XDMAC_GD_DI15_Msk & ((value) << XDMAC_GD_DI15_Pos)) +#define XDMAC_GD_DI16_Pos _U_(16) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Position */ +#define XDMAC_GD_DI16_Msk (_U_(0x1) << XDMAC_GD_DI16_Pos) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Mask */ +#define XDMAC_GD_DI16(value) (XDMAC_GD_DI16_Msk & ((value) << XDMAC_GD_DI16_Pos)) +#define XDMAC_GD_DI17_Pos _U_(17) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Position */ +#define XDMAC_GD_DI17_Msk (_U_(0x1) << XDMAC_GD_DI17_Pos) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Mask */ +#define XDMAC_GD_DI17(value) (XDMAC_GD_DI17_Msk & ((value) << XDMAC_GD_DI17_Pos)) +#define XDMAC_GD_DI18_Pos _U_(18) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Position */ +#define XDMAC_GD_DI18_Msk (_U_(0x1) << XDMAC_GD_DI18_Pos) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Mask */ +#define XDMAC_GD_DI18(value) (XDMAC_GD_DI18_Msk & ((value) << XDMAC_GD_DI18_Pos)) +#define XDMAC_GD_DI19_Pos _U_(19) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Position */ +#define XDMAC_GD_DI19_Msk (_U_(0x1) << XDMAC_GD_DI19_Pos) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Mask */ +#define XDMAC_GD_DI19(value) (XDMAC_GD_DI19_Msk & ((value) << XDMAC_GD_DI19_Pos)) +#define XDMAC_GD_DI20_Pos _U_(20) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Position */ +#define XDMAC_GD_DI20_Msk (_U_(0x1) << XDMAC_GD_DI20_Pos) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Mask */ +#define XDMAC_GD_DI20(value) (XDMAC_GD_DI20_Msk & ((value) << XDMAC_GD_DI20_Pos)) +#define XDMAC_GD_DI21_Pos _U_(21) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Position */ +#define XDMAC_GD_DI21_Msk (_U_(0x1) << XDMAC_GD_DI21_Pos) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Mask */ +#define XDMAC_GD_DI21(value) (XDMAC_GD_DI21_Msk & ((value) << XDMAC_GD_DI21_Pos)) +#define XDMAC_GD_DI22_Pos _U_(22) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Position */ +#define XDMAC_GD_DI22_Msk (_U_(0x1) << XDMAC_GD_DI22_Pos) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Mask */ +#define XDMAC_GD_DI22(value) (XDMAC_GD_DI22_Msk & ((value) << XDMAC_GD_DI22_Pos)) +#define XDMAC_GD_DI23_Pos _U_(23) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Position */ +#define XDMAC_GD_DI23_Msk (_U_(0x1) << XDMAC_GD_DI23_Pos) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Mask */ +#define XDMAC_GD_DI23(value) (XDMAC_GD_DI23_Msk & ((value) << XDMAC_GD_DI23_Pos)) +#define XDMAC_GD_Msk _U_(0x00FFFFFF) /**< (XDMAC_GD) Register Mask */ + +#define XDMAC_GD_DI_Pos _U_(0) /**< (XDMAC_GD Position) XDMAC Channel 23 Disable Bit */ +#define XDMAC_GD_DI_Msk (_U_(0xFFFFFF) << XDMAC_GD_DI_Pos) /**< (XDMAC_GD Mask) DI */ +#define XDMAC_GD_DI(value) (XDMAC_GD_DI_Msk & ((value) << XDMAC_GD_DI_Pos)) + +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) ( R/ 32) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0_Pos _U_(0) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Position */ +#define XDMAC_GS_ST0_Msk (_U_(0x1) << XDMAC_GS_ST0_Pos) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Mask */ +#define XDMAC_GS_ST0(value) (XDMAC_GS_ST0_Msk & ((value) << XDMAC_GS_ST0_Pos)) +#define XDMAC_GS_ST1_Pos _U_(1) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Position */ +#define XDMAC_GS_ST1_Msk (_U_(0x1) << XDMAC_GS_ST1_Pos) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Mask */ +#define XDMAC_GS_ST1(value) (XDMAC_GS_ST1_Msk & ((value) << XDMAC_GS_ST1_Pos)) +#define XDMAC_GS_ST2_Pos _U_(2) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Position */ +#define XDMAC_GS_ST2_Msk (_U_(0x1) << XDMAC_GS_ST2_Pos) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Mask */ +#define XDMAC_GS_ST2(value) (XDMAC_GS_ST2_Msk & ((value) << XDMAC_GS_ST2_Pos)) +#define XDMAC_GS_ST3_Pos _U_(3) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Position */ +#define XDMAC_GS_ST3_Msk (_U_(0x1) << XDMAC_GS_ST3_Pos) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Mask */ +#define XDMAC_GS_ST3(value) (XDMAC_GS_ST3_Msk & ((value) << XDMAC_GS_ST3_Pos)) +#define XDMAC_GS_ST4_Pos _U_(4) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Position */ +#define XDMAC_GS_ST4_Msk (_U_(0x1) << XDMAC_GS_ST4_Pos) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Mask */ +#define XDMAC_GS_ST4(value) (XDMAC_GS_ST4_Msk & ((value) << XDMAC_GS_ST4_Pos)) +#define XDMAC_GS_ST5_Pos _U_(5) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Position */ +#define XDMAC_GS_ST5_Msk (_U_(0x1) << XDMAC_GS_ST5_Pos) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Mask */ +#define XDMAC_GS_ST5(value) (XDMAC_GS_ST5_Msk & ((value) << XDMAC_GS_ST5_Pos)) +#define XDMAC_GS_ST6_Pos _U_(6) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Position */ +#define XDMAC_GS_ST6_Msk (_U_(0x1) << XDMAC_GS_ST6_Pos) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Mask */ +#define XDMAC_GS_ST6(value) (XDMAC_GS_ST6_Msk & ((value) << XDMAC_GS_ST6_Pos)) +#define XDMAC_GS_ST7_Pos _U_(7) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Position */ +#define XDMAC_GS_ST7_Msk (_U_(0x1) << XDMAC_GS_ST7_Pos) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Mask */ +#define XDMAC_GS_ST7(value) (XDMAC_GS_ST7_Msk & ((value) << XDMAC_GS_ST7_Pos)) +#define XDMAC_GS_ST8_Pos _U_(8) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Position */ +#define XDMAC_GS_ST8_Msk (_U_(0x1) << XDMAC_GS_ST8_Pos) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Mask */ +#define XDMAC_GS_ST8(value) (XDMAC_GS_ST8_Msk & ((value) << XDMAC_GS_ST8_Pos)) +#define XDMAC_GS_ST9_Pos _U_(9) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Position */ +#define XDMAC_GS_ST9_Msk (_U_(0x1) << XDMAC_GS_ST9_Pos) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Mask */ +#define XDMAC_GS_ST9(value) (XDMAC_GS_ST9_Msk & ((value) << XDMAC_GS_ST9_Pos)) +#define XDMAC_GS_ST10_Pos _U_(10) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Position */ +#define XDMAC_GS_ST10_Msk (_U_(0x1) << XDMAC_GS_ST10_Pos) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Mask */ +#define XDMAC_GS_ST10(value) (XDMAC_GS_ST10_Msk & ((value) << XDMAC_GS_ST10_Pos)) +#define XDMAC_GS_ST11_Pos _U_(11) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Position */ +#define XDMAC_GS_ST11_Msk (_U_(0x1) << XDMAC_GS_ST11_Pos) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Mask */ +#define XDMAC_GS_ST11(value) (XDMAC_GS_ST11_Msk & ((value) << XDMAC_GS_ST11_Pos)) +#define XDMAC_GS_ST12_Pos _U_(12) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Position */ +#define XDMAC_GS_ST12_Msk (_U_(0x1) << XDMAC_GS_ST12_Pos) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Mask */ +#define XDMAC_GS_ST12(value) (XDMAC_GS_ST12_Msk & ((value) << XDMAC_GS_ST12_Pos)) +#define XDMAC_GS_ST13_Pos _U_(13) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Position */ +#define XDMAC_GS_ST13_Msk (_U_(0x1) << XDMAC_GS_ST13_Pos) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Mask */ +#define XDMAC_GS_ST13(value) (XDMAC_GS_ST13_Msk & ((value) << XDMAC_GS_ST13_Pos)) +#define XDMAC_GS_ST14_Pos _U_(14) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Position */ +#define XDMAC_GS_ST14_Msk (_U_(0x1) << XDMAC_GS_ST14_Pos) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Mask */ +#define XDMAC_GS_ST14(value) (XDMAC_GS_ST14_Msk & ((value) << XDMAC_GS_ST14_Pos)) +#define XDMAC_GS_ST15_Pos _U_(15) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Position */ +#define XDMAC_GS_ST15_Msk (_U_(0x1) << XDMAC_GS_ST15_Pos) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Mask */ +#define XDMAC_GS_ST15(value) (XDMAC_GS_ST15_Msk & ((value) << XDMAC_GS_ST15_Pos)) +#define XDMAC_GS_ST16_Pos _U_(16) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Position */ +#define XDMAC_GS_ST16_Msk (_U_(0x1) << XDMAC_GS_ST16_Pos) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Mask */ +#define XDMAC_GS_ST16(value) (XDMAC_GS_ST16_Msk & ((value) << XDMAC_GS_ST16_Pos)) +#define XDMAC_GS_ST17_Pos _U_(17) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Position */ +#define XDMAC_GS_ST17_Msk (_U_(0x1) << XDMAC_GS_ST17_Pos) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Mask */ +#define XDMAC_GS_ST17(value) (XDMAC_GS_ST17_Msk & ((value) << XDMAC_GS_ST17_Pos)) +#define XDMAC_GS_ST18_Pos _U_(18) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Position */ +#define XDMAC_GS_ST18_Msk (_U_(0x1) << XDMAC_GS_ST18_Pos) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Mask */ +#define XDMAC_GS_ST18(value) (XDMAC_GS_ST18_Msk & ((value) << XDMAC_GS_ST18_Pos)) +#define XDMAC_GS_ST19_Pos _U_(19) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Position */ +#define XDMAC_GS_ST19_Msk (_U_(0x1) << XDMAC_GS_ST19_Pos) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Mask */ +#define XDMAC_GS_ST19(value) (XDMAC_GS_ST19_Msk & ((value) << XDMAC_GS_ST19_Pos)) +#define XDMAC_GS_ST20_Pos _U_(20) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Position */ +#define XDMAC_GS_ST20_Msk (_U_(0x1) << XDMAC_GS_ST20_Pos) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Mask */ +#define XDMAC_GS_ST20(value) (XDMAC_GS_ST20_Msk & ((value) << XDMAC_GS_ST20_Pos)) +#define XDMAC_GS_ST21_Pos _U_(21) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Position */ +#define XDMAC_GS_ST21_Msk (_U_(0x1) << XDMAC_GS_ST21_Pos) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Mask */ +#define XDMAC_GS_ST21(value) (XDMAC_GS_ST21_Msk & ((value) << XDMAC_GS_ST21_Pos)) +#define XDMAC_GS_ST22_Pos _U_(22) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Position */ +#define XDMAC_GS_ST22_Msk (_U_(0x1) << XDMAC_GS_ST22_Pos) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Mask */ +#define XDMAC_GS_ST22(value) (XDMAC_GS_ST22_Msk & ((value) << XDMAC_GS_ST22_Pos)) +#define XDMAC_GS_ST23_Pos _U_(23) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Position */ +#define XDMAC_GS_ST23_Msk (_U_(0x1) << XDMAC_GS_ST23_Pos) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Mask */ +#define XDMAC_GS_ST23(value) (XDMAC_GS_ST23_Msk & ((value) << XDMAC_GS_ST23_Pos)) +#define XDMAC_GS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GS) Register Mask */ + +#define XDMAC_GS_ST_Pos _U_(0) /**< (XDMAC_GS Position) XDMAC Channel 23 Status Bit */ +#define XDMAC_GS_ST_Msk (_U_(0xFFFFFF) << XDMAC_GS_ST_Pos) /**< (XDMAC_GS Mask) ST */ +#define XDMAC_GS_ST(value) (XDMAC_GS_ST_Msk & ((value) << XDMAC_GS_ST_Pos)) + +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) (R/W 32) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0_Pos _U_(0) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Position */ +#define XDMAC_GRS_RS0_Msk (_U_(0x1) << XDMAC_GRS_RS0_Pos) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS0(value) (XDMAC_GRS_RS0_Msk & ((value) << XDMAC_GRS_RS0_Pos)) +#define XDMAC_GRS_RS1_Pos _U_(1) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Position */ +#define XDMAC_GRS_RS1_Msk (_U_(0x1) << XDMAC_GRS_RS1_Pos) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS1(value) (XDMAC_GRS_RS1_Msk & ((value) << XDMAC_GRS_RS1_Pos)) +#define XDMAC_GRS_RS2_Pos _U_(2) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Position */ +#define XDMAC_GRS_RS2_Msk (_U_(0x1) << XDMAC_GRS_RS2_Pos) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS2(value) (XDMAC_GRS_RS2_Msk & ((value) << XDMAC_GRS_RS2_Pos)) +#define XDMAC_GRS_RS3_Pos _U_(3) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Position */ +#define XDMAC_GRS_RS3_Msk (_U_(0x1) << XDMAC_GRS_RS3_Pos) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS3(value) (XDMAC_GRS_RS3_Msk & ((value) << XDMAC_GRS_RS3_Pos)) +#define XDMAC_GRS_RS4_Pos _U_(4) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Position */ +#define XDMAC_GRS_RS4_Msk (_U_(0x1) << XDMAC_GRS_RS4_Pos) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS4(value) (XDMAC_GRS_RS4_Msk & ((value) << XDMAC_GRS_RS4_Pos)) +#define XDMAC_GRS_RS5_Pos _U_(5) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Position */ +#define XDMAC_GRS_RS5_Msk (_U_(0x1) << XDMAC_GRS_RS5_Pos) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS5(value) (XDMAC_GRS_RS5_Msk & ((value) << XDMAC_GRS_RS5_Pos)) +#define XDMAC_GRS_RS6_Pos _U_(6) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Position */ +#define XDMAC_GRS_RS6_Msk (_U_(0x1) << XDMAC_GRS_RS6_Pos) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS6(value) (XDMAC_GRS_RS6_Msk & ((value) << XDMAC_GRS_RS6_Pos)) +#define XDMAC_GRS_RS7_Pos _U_(7) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Position */ +#define XDMAC_GRS_RS7_Msk (_U_(0x1) << XDMAC_GRS_RS7_Pos) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS7(value) (XDMAC_GRS_RS7_Msk & ((value) << XDMAC_GRS_RS7_Pos)) +#define XDMAC_GRS_RS8_Pos _U_(8) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Position */ +#define XDMAC_GRS_RS8_Msk (_U_(0x1) << XDMAC_GRS_RS8_Pos) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS8(value) (XDMAC_GRS_RS8_Msk & ((value) << XDMAC_GRS_RS8_Pos)) +#define XDMAC_GRS_RS9_Pos _U_(9) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Position */ +#define XDMAC_GRS_RS9_Msk (_U_(0x1) << XDMAC_GRS_RS9_Pos) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS9(value) (XDMAC_GRS_RS9_Msk & ((value) << XDMAC_GRS_RS9_Pos)) +#define XDMAC_GRS_RS10_Pos _U_(10) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Position */ +#define XDMAC_GRS_RS10_Msk (_U_(0x1) << XDMAC_GRS_RS10_Pos) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS10(value) (XDMAC_GRS_RS10_Msk & ((value) << XDMAC_GRS_RS10_Pos)) +#define XDMAC_GRS_RS11_Pos _U_(11) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Position */ +#define XDMAC_GRS_RS11_Msk (_U_(0x1) << XDMAC_GRS_RS11_Pos) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS11(value) (XDMAC_GRS_RS11_Msk & ((value) << XDMAC_GRS_RS11_Pos)) +#define XDMAC_GRS_RS12_Pos _U_(12) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Position */ +#define XDMAC_GRS_RS12_Msk (_U_(0x1) << XDMAC_GRS_RS12_Pos) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS12(value) (XDMAC_GRS_RS12_Msk & ((value) << XDMAC_GRS_RS12_Pos)) +#define XDMAC_GRS_RS13_Pos _U_(13) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Position */ +#define XDMAC_GRS_RS13_Msk (_U_(0x1) << XDMAC_GRS_RS13_Pos) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS13(value) (XDMAC_GRS_RS13_Msk & ((value) << XDMAC_GRS_RS13_Pos)) +#define XDMAC_GRS_RS14_Pos _U_(14) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Position */ +#define XDMAC_GRS_RS14_Msk (_U_(0x1) << XDMAC_GRS_RS14_Pos) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS14(value) (XDMAC_GRS_RS14_Msk & ((value) << XDMAC_GRS_RS14_Pos)) +#define XDMAC_GRS_RS15_Pos _U_(15) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Position */ +#define XDMAC_GRS_RS15_Msk (_U_(0x1) << XDMAC_GRS_RS15_Pos) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS15(value) (XDMAC_GRS_RS15_Msk & ((value) << XDMAC_GRS_RS15_Pos)) +#define XDMAC_GRS_RS16_Pos _U_(16) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Position */ +#define XDMAC_GRS_RS16_Msk (_U_(0x1) << XDMAC_GRS_RS16_Pos) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS16(value) (XDMAC_GRS_RS16_Msk & ((value) << XDMAC_GRS_RS16_Pos)) +#define XDMAC_GRS_RS17_Pos _U_(17) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Position */ +#define XDMAC_GRS_RS17_Msk (_U_(0x1) << XDMAC_GRS_RS17_Pos) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS17(value) (XDMAC_GRS_RS17_Msk & ((value) << XDMAC_GRS_RS17_Pos)) +#define XDMAC_GRS_RS18_Pos _U_(18) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Position */ +#define XDMAC_GRS_RS18_Msk (_U_(0x1) << XDMAC_GRS_RS18_Pos) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS18(value) (XDMAC_GRS_RS18_Msk & ((value) << XDMAC_GRS_RS18_Pos)) +#define XDMAC_GRS_RS19_Pos _U_(19) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Position */ +#define XDMAC_GRS_RS19_Msk (_U_(0x1) << XDMAC_GRS_RS19_Pos) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS19(value) (XDMAC_GRS_RS19_Msk & ((value) << XDMAC_GRS_RS19_Pos)) +#define XDMAC_GRS_RS20_Pos _U_(20) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Position */ +#define XDMAC_GRS_RS20_Msk (_U_(0x1) << XDMAC_GRS_RS20_Pos) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS20(value) (XDMAC_GRS_RS20_Msk & ((value) << XDMAC_GRS_RS20_Pos)) +#define XDMAC_GRS_RS21_Pos _U_(21) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Position */ +#define XDMAC_GRS_RS21_Msk (_U_(0x1) << XDMAC_GRS_RS21_Pos) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS21(value) (XDMAC_GRS_RS21_Msk & ((value) << XDMAC_GRS_RS21_Pos)) +#define XDMAC_GRS_RS22_Pos _U_(22) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Position */ +#define XDMAC_GRS_RS22_Msk (_U_(0x1) << XDMAC_GRS_RS22_Pos) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS22(value) (XDMAC_GRS_RS22_Msk & ((value) << XDMAC_GRS_RS22_Pos)) +#define XDMAC_GRS_RS23_Pos _U_(23) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Position */ +#define XDMAC_GRS_RS23_Msk (_U_(0x1) << XDMAC_GRS_RS23_Pos) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS23(value) (XDMAC_GRS_RS23_Msk & ((value) << XDMAC_GRS_RS23_Pos)) +#define XDMAC_GRS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRS) Register Mask */ + +#define XDMAC_GRS_RS_Pos _U_(0) /**< (XDMAC_GRS Position) XDMAC Channel 23 Read Suspend Bit */ +#define XDMAC_GRS_RS_Msk (_U_(0xFFFFFF) << XDMAC_GRS_RS_Pos) /**< (XDMAC_GRS Mask) RS */ +#define XDMAC_GRS_RS(value) (XDMAC_GRS_RS_Msk & ((value) << XDMAC_GRS_RS_Pos)) + +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) (R/W 32) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0_Pos _U_(0) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Position */ +#define XDMAC_GWS_WS0_Msk (_U_(0x1) << XDMAC_GWS_WS0_Pos) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS0(value) (XDMAC_GWS_WS0_Msk & ((value) << XDMAC_GWS_WS0_Pos)) +#define XDMAC_GWS_WS1_Pos _U_(1) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Position */ +#define XDMAC_GWS_WS1_Msk (_U_(0x1) << XDMAC_GWS_WS1_Pos) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS1(value) (XDMAC_GWS_WS1_Msk & ((value) << XDMAC_GWS_WS1_Pos)) +#define XDMAC_GWS_WS2_Pos _U_(2) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Position */ +#define XDMAC_GWS_WS2_Msk (_U_(0x1) << XDMAC_GWS_WS2_Pos) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS2(value) (XDMAC_GWS_WS2_Msk & ((value) << XDMAC_GWS_WS2_Pos)) +#define XDMAC_GWS_WS3_Pos _U_(3) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Position */ +#define XDMAC_GWS_WS3_Msk (_U_(0x1) << XDMAC_GWS_WS3_Pos) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS3(value) (XDMAC_GWS_WS3_Msk & ((value) << XDMAC_GWS_WS3_Pos)) +#define XDMAC_GWS_WS4_Pos _U_(4) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Position */ +#define XDMAC_GWS_WS4_Msk (_U_(0x1) << XDMAC_GWS_WS4_Pos) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS4(value) (XDMAC_GWS_WS4_Msk & ((value) << XDMAC_GWS_WS4_Pos)) +#define XDMAC_GWS_WS5_Pos _U_(5) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Position */ +#define XDMAC_GWS_WS5_Msk (_U_(0x1) << XDMAC_GWS_WS5_Pos) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS5(value) (XDMAC_GWS_WS5_Msk & ((value) << XDMAC_GWS_WS5_Pos)) +#define XDMAC_GWS_WS6_Pos _U_(6) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Position */ +#define XDMAC_GWS_WS6_Msk (_U_(0x1) << XDMAC_GWS_WS6_Pos) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS6(value) (XDMAC_GWS_WS6_Msk & ((value) << XDMAC_GWS_WS6_Pos)) +#define XDMAC_GWS_WS7_Pos _U_(7) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Position */ +#define XDMAC_GWS_WS7_Msk (_U_(0x1) << XDMAC_GWS_WS7_Pos) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS7(value) (XDMAC_GWS_WS7_Msk & ((value) << XDMAC_GWS_WS7_Pos)) +#define XDMAC_GWS_WS8_Pos _U_(8) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Position */ +#define XDMAC_GWS_WS8_Msk (_U_(0x1) << XDMAC_GWS_WS8_Pos) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS8(value) (XDMAC_GWS_WS8_Msk & ((value) << XDMAC_GWS_WS8_Pos)) +#define XDMAC_GWS_WS9_Pos _U_(9) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Position */ +#define XDMAC_GWS_WS9_Msk (_U_(0x1) << XDMAC_GWS_WS9_Pos) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS9(value) (XDMAC_GWS_WS9_Msk & ((value) << XDMAC_GWS_WS9_Pos)) +#define XDMAC_GWS_WS10_Pos _U_(10) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Position */ +#define XDMAC_GWS_WS10_Msk (_U_(0x1) << XDMAC_GWS_WS10_Pos) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS10(value) (XDMAC_GWS_WS10_Msk & ((value) << XDMAC_GWS_WS10_Pos)) +#define XDMAC_GWS_WS11_Pos _U_(11) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Position */ +#define XDMAC_GWS_WS11_Msk (_U_(0x1) << XDMAC_GWS_WS11_Pos) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS11(value) (XDMAC_GWS_WS11_Msk & ((value) << XDMAC_GWS_WS11_Pos)) +#define XDMAC_GWS_WS12_Pos _U_(12) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Position */ +#define XDMAC_GWS_WS12_Msk (_U_(0x1) << XDMAC_GWS_WS12_Pos) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS12(value) (XDMAC_GWS_WS12_Msk & ((value) << XDMAC_GWS_WS12_Pos)) +#define XDMAC_GWS_WS13_Pos _U_(13) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Position */ +#define XDMAC_GWS_WS13_Msk (_U_(0x1) << XDMAC_GWS_WS13_Pos) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS13(value) (XDMAC_GWS_WS13_Msk & ((value) << XDMAC_GWS_WS13_Pos)) +#define XDMAC_GWS_WS14_Pos _U_(14) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Position */ +#define XDMAC_GWS_WS14_Msk (_U_(0x1) << XDMAC_GWS_WS14_Pos) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS14(value) (XDMAC_GWS_WS14_Msk & ((value) << XDMAC_GWS_WS14_Pos)) +#define XDMAC_GWS_WS15_Pos _U_(15) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Position */ +#define XDMAC_GWS_WS15_Msk (_U_(0x1) << XDMAC_GWS_WS15_Pos) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS15(value) (XDMAC_GWS_WS15_Msk & ((value) << XDMAC_GWS_WS15_Pos)) +#define XDMAC_GWS_WS16_Pos _U_(16) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Position */ +#define XDMAC_GWS_WS16_Msk (_U_(0x1) << XDMAC_GWS_WS16_Pos) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS16(value) (XDMAC_GWS_WS16_Msk & ((value) << XDMAC_GWS_WS16_Pos)) +#define XDMAC_GWS_WS17_Pos _U_(17) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Position */ +#define XDMAC_GWS_WS17_Msk (_U_(0x1) << XDMAC_GWS_WS17_Pos) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS17(value) (XDMAC_GWS_WS17_Msk & ((value) << XDMAC_GWS_WS17_Pos)) +#define XDMAC_GWS_WS18_Pos _U_(18) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Position */ +#define XDMAC_GWS_WS18_Msk (_U_(0x1) << XDMAC_GWS_WS18_Pos) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS18(value) (XDMAC_GWS_WS18_Msk & ((value) << XDMAC_GWS_WS18_Pos)) +#define XDMAC_GWS_WS19_Pos _U_(19) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Position */ +#define XDMAC_GWS_WS19_Msk (_U_(0x1) << XDMAC_GWS_WS19_Pos) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS19(value) (XDMAC_GWS_WS19_Msk & ((value) << XDMAC_GWS_WS19_Pos)) +#define XDMAC_GWS_WS20_Pos _U_(20) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Position */ +#define XDMAC_GWS_WS20_Msk (_U_(0x1) << XDMAC_GWS_WS20_Pos) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS20(value) (XDMAC_GWS_WS20_Msk & ((value) << XDMAC_GWS_WS20_Pos)) +#define XDMAC_GWS_WS21_Pos _U_(21) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Position */ +#define XDMAC_GWS_WS21_Msk (_U_(0x1) << XDMAC_GWS_WS21_Pos) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS21(value) (XDMAC_GWS_WS21_Msk & ((value) << XDMAC_GWS_WS21_Pos)) +#define XDMAC_GWS_WS22_Pos _U_(22) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Position */ +#define XDMAC_GWS_WS22_Msk (_U_(0x1) << XDMAC_GWS_WS22_Pos) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS22(value) (XDMAC_GWS_WS22_Msk & ((value) << XDMAC_GWS_WS22_Pos)) +#define XDMAC_GWS_WS23_Pos _U_(23) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Position */ +#define XDMAC_GWS_WS23_Msk (_U_(0x1) << XDMAC_GWS_WS23_Pos) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS23(value) (XDMAC_GWS_WS23_Msk & ((value) << XDMAC_GWS_WS23_Pos)) +#define XDMAC_GWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GWS) Register Mask */ + +#define XDMAC_GWS_WS_Pos _U_(0) /**< (XDMAC_GWS Position) XDMAC Channel 23 Write Suspend Bit */ +#define XDMAC_GWS_WS_Msk (_U_(0xFFFFFF) << XDMAC_GWS_WS_Pos) /**< (XDMAC_GWS Mask) WS */ +#define XDMAC_GWS_WS(value) (XDMAC_GWS_WS_Msk & ((value) << XDMAC_GWS_WS_Pos)) + +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) ( /W 32) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0_Pos _U_(0) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS0_Msk (_U_(0x1) << XDMAC_GRWS_RWS0_Pos) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS0(value) (XDMAC_GRWS_RWS0_Msk & ((value) << XDMAC_GRWS_RWS0_Pos)) +#define XDMAC_GRWS_RWS1_Pos _U_(1) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS1_Msk (_U_(0x1) << XDMAC_GRWS_RWS1_Pos) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS1(value) (XDMAC_GRWS_RWS1_Msk & ((value) << XDMAC_GRWS_RWS1_Pos)) +#define XDMAC_GRWS_RWS2_Pos _U_(2) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS2_Msk (_U_(0x1) << XDMAC_GRWS_RWS2_Pos) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS2(value) (XDMAC_GRWS_RWS2_Msk & ((value) << XDMAC_GRWS_RWS2_Pos)) +#define XDMAC_GRWS_RWS3_Pos _U_(3) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS3_Msk (_U_(0x1) << XDMAC_GRWS_RWS3_Pos) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS3(value) (XDMAC_GRWS_RWS3_Msk & ((value) << XDMAC_GRWS_RWS3_Pos)) +#define XDMAC_GRWS_RWS4_Pos _U_(4) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS4_Msk (_U_(0x1) << XDMAC_GRWS_RWS4_Pos) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS4(value) (XDMAC_GRWS_RWS4_Msk & ((value) << XDMAC_GRWS_RWS4_Pos)) +#define XDMAC_GRWS_RWS5_Pos _U_(5) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS5_Msk (_U_(0x1) << XDMAC_GRWS_RWS5_Pos) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS5(value) (XDMAC_GRWS_RWS5_Msk & ((value) << XDMAC_GRWS_RWS5_Pos)) +#define XDMAC_GRWS_RWS6_Pos _U_(6) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS6_Msk (_U_(0x1) << XDMAC_GRWS_RWS6_Pos) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS6(value) (XDMAC_GRWS_RWS6_Msk & ((value) << XDMAC_GRWS_RWS6_Pos)) +#define XDMAC_GRWS_RWS7_Pos _U_(7) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS7_Msk (_U_(0x1) << XDMAC_GRWS_RWS7_Pos) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS7(value) (XDMAC_GRWS_RWS7_Msk & ((value) << XDMAC_GRWS_RWS7_Pos)) +#define XDMAC_GRWS_RWS8_Pos _U_(8) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS8_Msk (_U_(0x1) << XDMAC_GRWS_RWS8_Pos) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS8(value) (XDMAC_GRWS_RWS8_Msk & ((value) << XDMAC_GRWS_RWS8_Pos)) +#define XDMAC_GRWS_RWS9_Pos _U_(9) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS9_Msk (_U_(0x1) << XDMAC_GRWS_RWS9_Pos) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS9(value) (XDMAC_GRWS_RWS9_Msk & ((value) << XDMAC_GRWS_RWS9_Pos)) +#define XDMAC_GRWS_RWS10_Pos _U_(10) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS10_Msk (_U_(0x1) << XDMAC_GRWS_RWS10_Pos) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS10(value) (XDMAC_GRWS_RWS10_Msk & ((value) << XDMAC_GRWS_RWS10_Pos)) +#define XDMAC_GRWS_RWS11_Pos _U_(11) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS11_Msk (_U_(0x1) << XDMAC_GRWS_RWS11_Pos) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS11(value) (XDMAC_GRWS_RWS11_Msk & ((value) << XDMAC_GRWS_RWS11_Pos)) +#define XDMAC_GRWS_RWS12_Pos _U_(12) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS12_Msk (_U_(0x1) << XDMAC_GRWS_RWS12_Pos) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS12(value) (XDMAC_GRWS_RWS12_Msk & ((value) << XDMAC_GRWS_RWS12_Pos)) +#define XDMAC_GRWS_RWS13_Pos _U_(13) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS13_Msk (_U_(0x1) << XDMAC_GRWS_RWS13_Pos) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS13(value) (XDMAC_GRWS_RWS13_Msk & ((value) << XDMAC_GRWS_RWS13_Pos)) +#define XDMAC_GRWS_RWS14_Pos _U_(14) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS14_Msk (_U_(0x1) << XDMAC_GRWS_RWS14_Pos) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS14(value) (XDMAC_GRWS_RWS14_Msk & ((value) << XDMAC_GRWS_RWS14_Pos)) +#define XDMAC_GRWS_RWS15_Pos _U_(15) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS15_Msk (_U_(0x1) << XDMAC_GRWS_RWS15_Pos) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS15(value) (XDMAC_GRWS_RWS15_Msk & ((value) << XDMAC_GRWS_RWS15_Pos)) +#define XDMAC_GRWS_RWS16_Pos _U_(16) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS16_Msk (_U_(0x1) << XDMAC_GRWS_RWS16_Pos) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS16(value) (XDMAC_GRWS_RWS16_Msk & ((value) << XDMAC_GRWS_RWS16_Pos)) +#define XDMAC_GRWS_RWS17_Pos _U_(17) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS17_Msk (_U_(0x1) << XDMAC_GRWS_RWS17_Pos) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS17(value) (XDMAC_GRWS_RWS17_Msk & ((value) << XDMAC_GRWS_RWS17_Pos)) +#define XDMAC_GRWS_RWS18_Pos _U_(18) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS18_Msk (_U_(0x1) << XDMAC_GRWS_RWS18_Pos) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS18(value) (XDMAC_GRWS_RWS18_Msk & ((value) << XDMAC_GRWS_RWS18_Pos)) +#define XDMAC_GRWS_RWS19_Pos _U_(19) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS19_Msk (_U_(0x1) << XDMAC_GRWS_RWS19_Pos) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS19(value) (XDMAC_GRWS_RWS19_Msk & ((value) << XDMAC_GRWS_RWS19_Pos)) +#define XDMAC_GRWS_RWS20_Pos _U_(20) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS20_Msk (_U_(0x1) << XDMAC_GRWS_RWS20_Pos) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS20(value) (XDMAC_GRWS_RWS20_Msk & ((value) << XDMAC_GRWS_RWS20_Pos)) +#define XDMAC_GRWS_RWS21_Pos _U_(21) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS21_Msk (_U_(0x1) << XDMAC_GRWS_RWS21_Pos) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS21(value) (XDMAC_GRWS_RWS21_Msk & ((value) << XDMAC_GRWS_RWS21_Pos)) +#define XDMAC_GRWS_RWS22_Pos _U_(22) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS22_Msk (_U_(0x1) << XDMAC_GRWS_RWS22_Pos) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS22(value) (XDMAC_GRWS_RWS22_Msk & ((value) << XDMAC_GRWS_RWS22_Pos)) +#define XDMAC_GRWS_RWS23_Pos _U_(23) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS23_Msk (_U_(0x1) << XDMAC_GRWS_RWS23_Pos) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS23(value) (XDMAC_GRWS_RWS23_Msk & ((value) << XDMAC_GRWS_RWS23_Pos)) +#define XDMAC_GRWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRWS) Register Mask */ + +#define XDMAC_GRWS_RWS_Pos _U_(0) /**< (XDMAC_GRWS Position) XDMAC Channel 23 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS_Msk (_U_(0xFFFFFF) << XDMAC_GRWS_RWS_Pos) /**< (XDMAC_GRWS Mask) RWS */ +#define XDMAC_GRWS_RWS(value) (XDMAC_GRWS_RWS_Msk & ((value) << XDMAC_GRWS_RWS_Pos)) + +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) ( /W 32) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0_Pos _U_(0) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR0_Msk (_U_(0x1) << XDMAC_GRWR_RWR0_Pos) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR0(value) (XDMAC_GRWR_RWR0_Msk & ((value) << XDMAC_GRWR_RWR0_Pos)) +#define XDMAC_GRWR_RWR1_Pos _U_(1) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR1_Msk (_U_(0x1) << XDMAC_GRWR_RWR1_Pos) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR1(value) (XDMAC_GRWR_RWR1_Msk & ((value) << XDMAC_GRWR_RWR1_Pos)) +#define XDMAC_GRWR_RWR2_Pos _U_(2) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR2_Msk (_U_(0x1) << XDMAC_GRWR_RWR2_Pos) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR2(value) (XDMAC_GRWR_RWR2_Msk & ((value) << XDMAC_GRWR_RWR2_Pos)) +#define XDMAC_GRWR_RWR3_Pos _U_(3) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR3_Msk (_U_(0x1) << XDMAC_GRWR_RWR3_Pos) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR3(value) (XDMAC_GRWR_RWR3_Msk & ((value) << XDMAC_GRWR_RWR3_Pos)) +#define XDMAC_GRWR_RWR4_Pos _U_(4) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR4_Msk (_U_(0x1) << XDMAC_GRWR_RWR4_Pos) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR4(value) (XDMAC_GRWR_RWR4_Msk & ((value) << XDMAC_GRWR_RWR4_Pos)) +#define XDMAC_GRWR_RWR5_Pos _U_(5) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR5_Msk (_U_(0x1) << XDMAC_GRWR_RWR5_Pos) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR5(value) (XDMAC_GRWR_RWR5_Msk & ((value) << XDMAC_GRWR_RWR5_Pos)) +#define XDMAC_GRWR_RWR6_Pos _U_(6) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR6_Msk (_U_(0x1) << XDMAC_GRWR_RWR6_Pos) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR6(value) (XDMAC_GRWR_RWR6_Msk & ((value) << XDMAC_GRWR_RWR6_Pos)) +#define XDMAC_GRWR_RWR7_Pos _U_(7) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR7_Msk (_U_(0x1) << XDMAC_GRWR_RWR7_Pos) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR7(value) (XDMAC_GRWR_RWR7_Msk & ((value) << XDMAC_GRWR_RWR7_Pos)) +#define XDMAC_GRWR_RWR8_Pos _U_(8) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR8_Msk (_U_(0x1) << XDMAC_GRWR_RWR8_Pos) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR8(value) (XDMAC_GRWR_RWR8_Msk & ((value) << XDMAC_GRWR_RWR8_Pos)) +#define XDMAC_GRWR_RWR9_Pos _U_(9) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR9_Msk (_U_(0x1) << XDMAC_GRWR_RWR9_Pos) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR9(value) (XDMAC_GRWR_RWR9_Msk & ((value) << XDMAC_GRWR_RWR9_Pos)) +#define XDMAC_GRWR_RWR10_Pos _U_(10) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR10_Msk (_U_(0x1) << XDMAC_GRWR_RWR10_Pos) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR10(value) (XDMAC_GRWR_RWR10_Msk & ((value) << XDMAC_GRWR_RWR10_Pos)) +#define XDMAC_GRWR_RWR11_Pos _U_(11) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR11_Msk (_U_(0x1) << XDMAC_GRWR_RWR11_Pos) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR11(value) (XDMAC_GRWR_RWR11_Msk & ((value) << XDMAC_GRWR_RWR11_Pos)) +#define XDMAC_GRWR_RWR12_Pos _U_(12) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR12_Msk (_U_(0x1) << XDMAC_GRWR_RWR12_Pos) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR12(value) (XDMAC_GRWR_RWR12_Msk & ((value) << XDMAC_GRWR_RWR12_Pos)) +#define XDMAC_GRWR_RWR13_Pos _U_(13) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR13_Msk (_U_(0x1) << XDMAC_GRWR_RWR13_Pos) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR13(value) (XDMAC_GRWR_RWR13_Msk & ((value) << XDMAC_GRWR_RWR13_Pos)) +#define XDMAC_GRWR_RWR14_Pos _U_(14) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR14_Msk (_U_(0x1) << XDMAC_GRWR_RWR14_Pos) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR14(value) (XDMAC_GRWR_RWR14_Msk & ((value) << XDMAC_GRWR_RWR14_Pos)) +#define XDMAC_GRWR_RWR15_Pos _U_(15) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR15_Msk (_U_(0x1) << XDMAC_GRWR_RWR15_Pos) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR15(value) (XDMAC_GRWR_RWR15_Msk & ((value) << XDMAC_GRWR_RWR15_Pos)) +#define XDMAC_GRWR_RWR16_Pos _U_(16) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR16_Msk (_U_(0x1) << XDMAC_GRWR_RWR16_Pos) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR16(value) (XDMAC_GRWR_RWR16_Msk & ((value) << XDMAC_GRWR_RWR16_Pos)) +#define XDMAC_GRWR_RWR17_Pos _U_(17) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR17_Msk (_U_(0x1) << XDMAC_GRWR_RWR17_Pos) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR17(value) (XDMAC_GRWR_RWR17_Msk & ((value) << XDMAC_GRWR_RWR17_Pos)) +#define XDMAC_GRWR_RWR18_Pos _U_(18) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR18_Msk (_U_(0x1) << XDMAC_GRWR_RWR18_Pos) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR18(value) (XDMAC_GRWR_RWR18_Msk & ((value) << XDMAC_GRWR_RWR18_Pos)) +#define XDMAC_GRWR_RWR19_Pos _U_(19) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR19_Msk (_U_(0x1) << XDMAC_GRWR_RWR19_Pos) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR19(value) (XDMAC_GRWR_RWR19_Msk & ((value) << XDMAC_GRWR_RWR19_Pos)) +#define XDMAC_GRWR_RWR20_Pos _U_(20) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR20_Msk (_U_(0x1) << XDMAC_GRWR_RWR20_Pos) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR20(value) (XDMAC_GRWR_RWR20_Msk & ((value) << XDMAC_GRWR_RWR20_Pos)) +#define XDMAC_GRWR_RWR21_Pos _U_(21) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR21_Msk (_U_(0x1) << XDMAC_GRWR_RWR21_Pos) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR21(value) (XDMAC_GRWR_RWR21_Msk & ((value) << XDMAC_GRWR_RWR21_Pos)) +#define XDMAC_GRWR_RWR22_Pos _U_(22) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR22_Msk (_U_(0x1) << XDMAC_GRWR_RWR22_Pos) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR22(value) (XDMAC_GRWR_RWR22_Msk & ((value) << XDMAC_GRWR_RWR22_Pos)) +#define XDMAC_GRWR_RWR23_Pos _U_(23) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR23_Msk (_U_(0x1) << XDMAC_GRWR_RWR23_Pos) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR23(value) (XDMAC_GRWR_RWR23_Msk & ((value) << XDMAC_GRWR_RWR23_Pos)) +#define XDMAC_GRWR_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRWR) Register Mask */ + +#define XDMAC_GRWR_RWR_Pos _U_(0) /**< (XDMAC_GRWR Position) XDMAC Channel 23 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR_Msk (_U_(0xFFFFFF) << XDMAC_GRWR_RWR_Pos) /**< (XDMAC_GRWR Mask) RWR */ +#define XDMAC_GRWR_RWR(value) (XDMAC_GRWR_RWR_Msk & ((value) << XDMAC_GRWR_RWR_Pos)) + +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) ( /W 32) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0_Pos _U_(0) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ0_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ0_Pos) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ0(value) (XDMAC_GSWR_SWREQ0_Msk & ((value) << XDMAC_GSWR_SWREQ0_Pos)) +#define XDMAC_GSWR_SWREQ1_Pos _U_(1) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ1_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ1_Pos) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ1(value) (XDMAC_GSWR_SWREQ1_Msk & ((value) << XDMAC_GSWR_SWREQ1_Pos)) +#define XDMAC_GSWR_SWREQ2_Pos _U_(2) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ2_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ2_Pos) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ2(value) (XDMAC_GSWR_SWREQ2_Msk & ((value) << XDMAC_GSWR_SWREQ2_Pos)) +#define XDMAC_GSWR_SWREQ3_Pos _U_(3) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ3_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ3_Pos) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ3(value) (XDMAC_GSWR_SWREQ3_Msk & ((value) << XDMAC_GSWR_SWREQ3_Pos)) +#define XDMAC_GSWR_SWREQ4_Pos _U_(4) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ4_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ4_Pos) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ4(value) (XDMAC_GSWR_SWREQ4_Msk & ((value) << XDMAC_GSWR_SWREQ4_Pos)) +#define XDMAC_GSWR_SWREQ5_Pos _U_(5) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ5_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ5_Pos) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ5(value) (XDMAC_GSWR_SWREQ5_Msk & ((value) << XDMAC_GSWR_SWREQ5_Pos)) +#define XDMAC_GSWR_SWREQ6_Pos _U_(6) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ6_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ6_Pos) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ6(value) (XDMAC_GSWR_SWREQ6_Msk & ((value) << XDMAC_GSWR_SWREQ6_Pos)) +#define XDMAC_GSWR_SWREQ7_Pos _U_(7) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ7_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ7_Pos) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ7(value) (XDMAC_GSWR_SWREQ7_Msk & ((value) << XDMAC_GSWR_SWREQ7_Pos)) +#define XDMAC_GSWR_SWREQ8_Pos _U_(8) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ8_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ8_Pos) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ8(value) (XDMAC_GSWR_SWREQ8_Msk & ((value) << XDMAC_GSWR_SWREQ8_Pos)) +#define XDMAC_GSWR_SWREQ9_Pos _U_(9) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ9_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ9_Pos) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ9(value) (XDMAC_GSWR_SWREQ9_Msk & ((value) << XDMAC_GSWR_SWREQ9_Pos)) +#define XDMAC_GSWR_SWREQ10_Pos _U_(10) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ10_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ10_Pos) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ10(value) (XDMAC_GSWR_SWREQ10_Msk & ((value) << XDMAC_GSWR_SWREQ10_Pos)) +#define XDMAC_GSWR_SWREQ11_Pos _U_(11) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ11_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ11_Pos) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ11(value) (XDMAC_GSWR_SWREQ11_Msk & ((value) << XDMAC_GSWR_SWREQ11_Pos)) +#define XDMAC_GSWR_SWREQ12_Pos _U_(12) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ12_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ12_Pos) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ12(value) (XDMAC_GSWR_SWREQ12_Msk & ((value) << XDMAC_GSWR_SWREQ12_Pos)) +#define XDMAC_GSWR_SWREQ13_Pos _U_(13) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ13_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ13_Pos) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ13(value) (XDMAC_GSWR_SWREQ13_Msk & ((value) << XDMAC_GSWR_SWREQ13_Pos)) +#define XDMAC_GSWR_SWREQ14_Pos _U_(14) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ14_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ14_Pos) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ14(value) (XDMAC_GSWR_SWREQ14_Msk & ((value) << XDMAC_GSWR_SWREQ14_Pos)) +#define XDMAC_GSWR_SWREQ15_Pos _U_(15) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ15_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ15_Pos) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ15(value) (XDMAC_GSWR_SWREQ15_Msk & ((value) << XDMAC_GSWR_SWREQ15_Pos)) +#define XDMAC_GSWR_SWREQ16_Pos _U_(16) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ16_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ16_Pos) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ16(value) (XDMAC_GSWR_SWREQ16_Msk & ((value) << XDMAC_GSWR_SWREQ16_Pos)) +#define XDMAC_GSWR_SWREQ17_Pos _U_(17) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ17_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ17_Pos) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ17(value) (XDMAC_GSWR_SWREQ17_Msk & ((value) << XDMAC_GSWR_SWREQ17_Pos)) +#define XDMAC_GSWR_SWREQ18_Pos _U_(18) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ18_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ18_Pos) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ18(value) (XDMAC_GSWR_SWREQ18_Msk & ((value) << XDMAC_GSWR_SWREQ18_Pos)) +#define XDMAC_GSWR_SWREQ19_Pos _U_(19) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ19_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ19_Pos) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ19(value) (XDMAC_GSWR_SWREQ19_Msk & ((value) << XDMAC_GSWR_SWREQ19_Pos)) +#define XDMAC_GSWR_SWREQ20_Pos _U_(20) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ20_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ20_Pos) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ20(value) (XDMAC_GSWR_SWREQ20_Msk & ((value) << XDMAC_GSWR_SWREQ20_Pos)) +#define XDMAC_GSWR_SWREQ21_Pos _U_(21) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ21_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ21_Pos) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ21(value) (XDMAC_GSWR_SWREQ21_Msk & ((value) << XDMAC_GSWR_SWREQ21_Pos)) +#define XDMAC_GSWR_SWREQ22_Pos _U_(22) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ22_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ22_Pos) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ22(value) (XDMAC_GSWR_SWREQ22_Msk & ((value) << XDMAC_GSWR_SWREQ22_Pos)) +#define XDMAC_GSWR_SWREQ23_Pos _U_(23) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ23_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ23_Pos) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ23(value) (XDMAC_GSWR_SWREQ23_Msk & ((value) << XDMAC_GSWR_SWREQ23_Pos)) +#define XDMAC_GSWR_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWR) Register Mask */ + +#define XDMAC_GSWR_SWREQ_Pos _U_(0) /**< (XDMAC_GSWR Position) XDMAC Channel 23 Software Request Bit */ +#define XDMAC_GSWR_SWREQ_Msk (_U_(0xFFFFFF) << XDMAC_GSWR_SWREQ_Pos) /**< (XDMAC_GSWR Mask) SWREQ */ +#define XDMAC_GSWR_SWREQ(value) (XDMAC_GSWR_SWREQ_Msk & ((value) << XDMAC_GSWR_SWREQ_Pos)) + +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) ( R/ 32) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0_Pos _U_(0) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS0_Msk (_U_(0x1) << XDMAC_GSWS_SWRS0_Pos) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS0(value) (XDMAC_GSWS_SWRS0_Msk & ((value) << XDMAC_GSWS_SWRS0_Pos)) +#define XDMAC_GSWS_SWRS1_Pos _U_(1) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS1_Msk (_U_(0x1) << XDMAC_GSWS_SWRS1_Pos) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS1(value) (XDMAC_GSWS_SWRS1_Msk & ((value) << XDMAC_GSWS_SWRS1_Pos)) +#define XDMAC_GSWS_SWRS2_Pos _U_(2) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS2_Msk (_U_(0x1) << XDMAC_GSWS_SWRS2_Pos) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS2(value) (XDMAC_GSWS_SWRS2_Msk & ((value) << XDMAC_GSWS_SWRS2_Pos)) +#define XDMAC_GSWS_SWRS3_Pos _U_(3) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS3_Msk (_U_(0x1) << XDMAC_GSWS_SWRS3_Pos) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS3(value) (XDMAC_GSWS_SWRS3_Msk & ((value) << XDMAC_GSWS_SWRS3_Pos)) +#define XDMAC_GSWS_SWRS4_Pos _U_(4) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS4_Msk (_U_(0x1) << XDMAC_GSWS_SWRS4_Pos) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS4(value) (XDMAC_GSWS_SWRS4_Msk & ((value) << XDMAC_GSWS_SWRS4_Pos)) +#define XDMAC_GSWS_SWRS5_Pos _U_(5) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS5_Msk (_U_(0x1) << XDMAC_GSWS_SWRS5_Pos) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS5(value) (XDMAC_GSWS_SWRS5_Msk & ((value) << XDMAC_GSWS_SWRS5_Pos)) +#define XDMAC_GSWS_SWRS6_Pos _U_(6) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS6_Msk (_U_(0x1) << XDMAC_GSWS_SWRS6_Pos) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS6(value) (XDMAC_GSWS_SWRS6_Msk & ((value) << XDMAC_GSWS_SWRS6_Pos)) +#define XDMAC_GSWS_SWRS7_Pos _U_(7) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS7_Msk (_U_(0x1) << XDMAC_GSWS_SWRS7_Pos) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS7(value) (XDMAC_GSWS_SWRS7_Msk & ((value) << XDMAC_GSWS_SWRS7_Pos)) +#define XDMAC_GSWS_SWRS8_Pos _U_(8) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS8_Msk (_U_(0x1) << XDMAC_GSWS_SWRS8_Pos) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS8(value) (XDMAC_GSWS_SWRS8_Msk & ((value) << XDMAC_GSWS_SWRS8_Pos)) +#define XDMAC_GSWS_SWRS9_Pos _U_(9) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS9_Msk (_U_(0x1) << XDMAC_GSWS_SWRS9_Pos) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS9(value) (XDMAC_GSWS_SWRS9_Msk & ((value) << XDMAC_GSWS_SWRS9_Pos)) +#define XDMAC_GSWS_SWRS10_Pos _U_(10) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS10_Msk (_U_(0x1) << XDMAC_GSWS_SWRS10_Pos) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS10(value) (XDMAC_GSWS_SWRS10_Msk & ((value) << XDMAC_GSWS_SWRS10_Pos)) +#define XDMAC_GSWS_SWRS11_Pos _U_(11) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS11_Msk (_U_(0x1) << XDMAC_GSWS_SWRS11_Pos) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS11(value) (XDMAC_GSWS_SWRS11_Msk & ((value) << XDMAC_GSWS_SWRS11_Pos)) +#define XDMAC_GSWS_SWRS12_Pos _U_(12) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS12_Msk (_U_(0x1) << XDMAC_GSWS_SWRS12_Pos) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS12(value) (XDMAC_GSWS_SWRS12_Msk & ((value) << XDMAC_GSWS_SWRS12_Pos)) +#define XDMAC_GSWS_SWRS13_Pos _U_(13) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS13_Msk (_U_(0x1) << XDMAC_GSWS_SWRS13_Pos) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS13(value) (XDMAC_GSWS_SWRS13_Msk & ((value) << XDMAC_GSWS_SWRS13_Pos)) +#define XDMAC_GSWS_SWRS14_Pos _U_(14) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS14_Msk (_U_(0x1) << XDMAC_GSWS_SWRS14_Pos) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS14(value) (XDMAC_GSWS_SWRS14_Msk & ((value) << XDMAC_GSWS_SWRS14_Pos)) +#define XDMAC_GSWS_SWRS15_Pos _U_(15) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS15_Msk (_U_(0x1) << XDMAC_GSWS_SWRS15_Pos) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS15(value) (XDMAC_GSWS_SWRS15_Msk & ((value) << XDMAC_GSWS_SWRS15_Pos)) +#define XDMAC_GSWS_SWRS16_Pos _U_(16) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS16_Msk (_U_(0x1) << XDMAC_GSWS_SWRS16_Pos) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS16(value) (XDMAC_GSWS_SWRS16_Msk & ((value) << XDMAC_GSWS_SWRS16_Pos)) +#define XDMAC_GSWS_SWRS17_Pos _U_(17) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS17_Msk (_U_(0x1) << XDMAC_GSWS_SWRS17_Pos) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS17(value) (XDMAC_GSWS_SWRS17_Msk & ((value) << XDMAC_GSWS_SWRS17_Pos)) +#define XDMAC_GSWS_SWRS18_Pos _U_(18) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS18_Msk (_U_(0x1) << XDMAC_GSWS_SWRS18_Pos) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS18(value) (XDMAC_GSWS_SWRS18_Msk & ((value) << XDMAC_GSWS_SWRS18_Pos)) +#define XDMAC_GSWS_SWRS19_Pos _U_(19) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS19_Msk (_U_(0x1) << XDMAC_GSWS_SWRS19_Pos) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS19(value) (XDMAC_GSWS_SWRS19_Msk & ((value) << XDMAC_GSWS_SWRS19_Pos)) +#define XDMAC_GSWS_SWRS20_Pos _U_(20) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS20_Msk (_U_(0x1) << XDMAC_GSWS_SWRS20_Pos) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS20(value) (XDMAC_GSWS_SWRS20_Msk & ((value) << XDMAC_GSWS_SWRS20_Pos)) +#define XDMAC_GSWS_SWRS21_Pos _U_(21) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS21_Msk (_U_(0x1) << XDMAC_GSWS_SWRS21_Pos) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS21(value) (XDMAC_GSWS_SWRS21_Msk & ((value) << XDMAC_GSWS_SWRS21_Pos)) +#define XDMAC_GSWS_SWRS22_Pos _U_(22) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS22_Msk (_U_(0x1) << XDMAC_GSWS_SWRS22_Pos) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS22(value) (XDMAC_GSWS_SWRS22_Msk & ((value) << XDMAC_GSWS_SWRS22_Pos)) +#define XDMAC_GSWS_SWRS23_Pos _U_(23) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS23_Msk (_U_(0x1) << XDMAC_GSWS_SWRS23_Pos) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS23(value) (XDMAC_GSWS_SWRS23_Msk & ((value) << XDMAC_GSWS_SWRS23_Pos)) +#define XDMAC_GSWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWS) Register Mask */ + +#define XDMAC_GSWS_SWRS_Pos _U_(0) /**< (XDMAC_GSWS Position) XDMAC Channel 23 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS_Msk (_U_(0xFFFFFF) << XDMAC_GSWS_SWRS_Pos) /**< (XDMAC_GSWS Mask) SWRS */ +#define XDMAC_GSWS_SWRS(value) (XDMAC_GSWS_SWRS_Msk & ((value) << XDMAC_GSWS_SWRS_Pos)) + +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) ( /W 32) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0_Pos _U_(0) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF0_Msk (_U_(0x1) << XDMAC_GSWF_SWF0_Pos) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF0(value) (XDMAC_GSWF_SWF0_Msk & ((value) << XDMAC_GSWF_SWF0_Pos)) +#define XDMAC_GSWF_SWF1_Pos _U_(1) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF1_Msk (_U_(0x1) << XDMAC_GSWF_SWF1_Pos) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF1(value) (XDMAC_GSWF_SWF1_Msk & ((value) << XDMAC_GSWF_SWF1_Pos)) +#define XDMAC_GSWF_SWF2_Pos _U_(2) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF2_Msk (_U_(0x1) << XDMAC_GSWF_SWF2_Pos) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF2(value) (XDMAC_GSWF_SWF2_Msk & ((value) << XDMAC_GSWF_SWF2_Pos)) +#define XDMAC_GSWF_SWF3_Pos _U_(3) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF3_Msk (_U_(0x1) << XDMAC_GSWF_SWF3_Pos) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF3(value) (XDMAC_GSWF_SWF3_Msk & ((value) << XDMAC_GSWF_SWF3_Pos)) +#define XDMAC_GSWF_SWF4_Pos _U_(4) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF4_Msk (_U_(0x1) << XDMAC_GSWF_SWF4_Pos) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF4(value) (XDMAC_GSWF_SWF4_Msk & ((value) << XDMAC_GSWF_SWF4_Pos)) +#define XDMAC_GSWF_SWF5_Pos _U_(5) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF5_Msk (_U_(0x1) << XDMAC_GSWF_SWF5_Pos) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF5(value) (XDMAC_GSWF_SWF5_Msk & ((value) << XDMAC_GSWF_SWF5_Pos)) +#define XDMAC_GSWF_SWF6_Pos _U_(6) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF6_Msk (_U_(0x1) << XDMAC_GSWF_SWF6_Pos) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF6(value) (XDMAC_GSWF_SWF6_Msk & ((value) << XDMAC_GSWF_SWF6_Pos)) +#define XDMAC_GSWF_SWF7_Pos _U_(7) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF7_Msk (_U_(0x1) << XDMAC_GSWF_SWF7_Pos) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF7(value) (XDMAC_GSWF_SWF7_Msk & ((value) << XDMAC_GSWF_SWF7_Pos)) +#define XDMAC_GSWF_SWF8_Pos _U_(8) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF8_Msk (_U_(0x1) << XDMAC_GSWF_SWF8_Pos) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF8(value) (XDMAC_GSWF_SWF8_Msk & ((value) << XDMAC_GSWF_SWF8_Pos)) +#define XDMAC_GSWF_SWF9_Pos _U_(9) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF9_Msk (_U_(0x1) << XDMAC_GSWF_SWF9_Pos) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF9(value) (XDMAC_GSWF_SWF9_Msk & ((value) << XDMAC_GSWF_SWF9_Pos)) +#define XDMAC_GSWF_SWF10_Pos _U_(10) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF10_Msk (_U_(0x1) << XDMAC_GSWF_SWF10_Pos) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF10(value) (XDMAC_GSWF_SWF10_Msk & ((value) << XDMAC_GSWF_SWF10_Pos)) +#define XDMAC_GSWF_SWF11_Pos _U_(11) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF11_Msk (_U_(0x1) << XDMAC_GSWF_SWF11_Pos) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF11(value) (XDMAC_GSWF_SWF11_Msk & ((value) << XDMAC_GSWF_SWF11_Pos)) +#define XDMAC_GSWF_SWF12_Pos _U_(12) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF12_Msk (_U_(0x1) << XDMAC_GSWF_SWF12_Pos) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF12(value) (XDMAC_GSWF_SWF12_Msk & ((value) << XDMAC_GSWF_SWF12_Pos)) +#define XDMAC_GSWF_SWF13_Pos _U_(13) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF13_Msk (_U_(0x1) << XDMAC_GSWF_SWF13_Pos) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF13(value) (XDMAC_GSWF_SWF13_Msk & ((value) << XDMAC_GSWF_SWF13_Pos)) +#define XDMAC_GSWF_SWF14_Pos _U_(14) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF14_Msk (_U_(0x1) << XDMAC_GSWF_SWF14_Pos) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF14(value) (XDMAC_GSWF_SWF14_Msk & ((value) << XDMAC_GSWF_SWF14_Pos)) +#define XDMAC_GSWF_SWF15_Pos _U_(15) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF15_Msk (_U_(0x1) << XDMAC_GSWF_SWF15_Pos) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF15(value) (XDMAC_GSWF_SWF15_Msk & ((value) << XDMAC_GSWF_SWF15_Pos)) +#define XDMAC_GSWF_SWF16_Pos _U_(16) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF16_Msk (_U_(0x1) << XDMAC_GSWF_SWF16_Pos) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF16(value) (XDMAC_GSWF_SWF16_Msk & ((value) << XDMAC_GSWF_SWF16_Pos)) +#define XDMAC_GSWF_SWF17_Pos _U_(17) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF17_Msk (_U_(0x1) << XDMAC_GSWF_SWF17_Pos) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF17(value) (XDMAC_GSWF_SWF17_Msk & ((value) << XDMAC_GSWF_SWF17_Pos)) +#define XDMAC_GSWF_SWF18_Pos _U_(18) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF18_Msk (_U_(0x1) << XDMAC_GSWF_SWF18_Pos) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF18(value) (XDMAC_GSWF_SWF18_Msk & ((value) << XDMAC_GSWF_SWF18_Pos)) +#define XDMAC_GSWF_SWF19_Pos _U_(19) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF19_Msk (_U_(0x1) << XDMAC_GSWF_SWF19_Pos) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF19(value) (XDMAC_GSWF_SWF19_Msk & ((value) << XDMAC_GSWF_SWF19_Pos)) +#define XDMAC_GSWF_SWF20_Pos _U_(20) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF20_Msk (_U_(0x1) << XDMAC_GSWF_SWF20_Pos) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF20(value) (XDMAC_GSWF_SWF20_Msk & ((value) << XDMAC_GSWF_SWF20_Pos)) +#define XDMAC_GSWF_SWF21_Pos _U_(21) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF21_Msk (_U_(0x1) << XDMAC_GSWF_SWF21_Pos) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF21(value) (XDMAC_GSWF_SWF21_Msk & ((value) << XDMAC_GSWF_SWF21_Pos)) +#define XDMAC_GSWF_SWF22_Pos _U_(22) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF22_Msk (_U_(0x1) << XDMAC_GSWF_SWF22_Pos) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF22(value) (XDMAC_GSWF_SWF22_Msk & ((value) << XDMAC_GSWF_SWF22_Pos)) +#define XDMAC_GSWF_SWF23_Pos _U_(23) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF23_Msk (_U_(0x1) << XDMAC_GSWF_SWF23_Pos) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF23(value) (XDMAC_GSWF_SWF23_Msk & ((value) << XDMAC_GSWF_SWF23_Pos)) +#define XDMAC_GSWF_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWF) Register Mask */ + +#define XDMAC_GSWF_SWF_Pos _U_(0) /**< (XDMAC_GSWF Position) XDMAC Channel 23 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF_Msk (_U_(0xFFFFFF) << XDMAC_GSWF_SWF_Pos) /**< (XDMAC_GSWF Mask) SWF */ +#define XDMAC_GSWF_SWF(value) (XDMAC_GSWF_SWF_Msk & ((value) << XDMAC_GSWF_SWF_Pos)) + +/** \brief XDMAC register offsets definitions */ +#define XDMAC_CIE_REG_OFST (0x00) /**< (XDMAC_CIE) Channel Interrupt Enable Register (chid = 0) Offset */ +#define XDMAC_CID_REG_OFST (0x04) /**< (XDMAC_CID) Channel Interrupt Disable Register (chid = 0) Offset */ +#define XDMAC_CIM_REG_OFST (0x08) /**< (XDMAC_CIM) Channel Interrupt Mask Register (chid = 0) Offset */ +#define XDMAC_CIS_REG_OFST (0x0C) /**< (XDMAC_CIS) Channel Interrupt Status Register (chid = 0) Offset */ +#define XDMAC_CSA_REG_OFST (0x10) /**< (XDMAC_CSA) Channel Source Address Register (chid = 0) Offset */ +#define XDMAC_CDA_REG_OFST (0x14) /**< (XDMAC_CDA) Channel Destination Address Register (chid = 0) Offset */ +#define XDMAC_CNDA_REG_OFST (0x18) /**< (XDMAC_CNDA) Channel Next Descriptor Address Register (chid = 0) Offset */ +#define XDMAC_CNDC_REG_OFST (0x1C) /**< (XDMAC_CNDC) Channel Next Descriptor Control Register (chid = 0) Offset */ +#define XDMAC_CUBC_REG_OFST (0x20) /**< (XDMAC_CUBC) Channel Microblock Control Register (chid = 0) Offset */ +#define XDMAC_CBC_REG_OFST (0x24) /**< (XDMAC_CBC) Channel Block Control Register (chid = 0) Offset */ +#define XDMAC_CC_REG_OFST (0x28) /**< (XDMAC_CC) Channel Configuration Register (chid = 0) Offset */ +#define XDMAC_CDS_MSP_REG_OFST (0x2C) /**< (XDMAC_CDS_MSP) Channel Data Stride Memory Set Pattern (chid = 0) Offset */ +#define XDMAC_CSUS_REG_OFST (0x30) /**< (XDMAC_CSUS) Channel Source Microblock Stride (chid = 0) Offset */ +#define XDMAC_CDUS_REG_OFST (0x34) /**< (XDMAC_CDUS) Channel Destination Microblock Stride (chid = 0) Offset */ +#define XDMAC_GTYPE_REG_OFST (0x00) /**< (XDMAC_GTYPE) Global Type Register Offset */ +#define XDMAC_GCFG_REG_OFST (0x04) /**< (XDMAC_GCFG) Global Configuration Register Offset */ +#define XDMAC_GWAC_REG_OFST (0x08) /**< (XDMAC_GWAC) Global Weighted Arbiter Configuration Register Offset */ +#define XDMAC_GIE_REG_OFST (0x0C) /**< (XDMAC_GIE) Global Interrupt Enable Register Offset */ +#define XDMAC_GID_REG_OFST (0x10) /**< (XDMAC_GID) Global Interrupt Disable Register Offset */ +#define XDMAC_GIM_REG_OFST (0x14) /**< (XDMAC_GIM) Global Interrupt Mask Register Offset */ +#define XDMAC_GIS_REG_OFST (0x18) /**< (XDMAC_GIS) Global Interrupt Status Register Offset */ +#define XDMAC_GE_REG_OFST (0x1C) /**< (XDMAC_GE) Global Channel Enable Register Offset */ +#define XDMAC_GD_REG_OFST (0x20) /**< (XDMAC_GD) Global Channel Disable Register Offset */ +#define XDMAC_GS_REG_OFST (0x24) /**< (XDMAC_GS) Global Channel Status Register Offset */ +#define XDMAC_GRS_REG_OFST (0x28) /**< (XDMAC_GRS) Global Channel Read Suspend Register Offset */ +#define XDMAC_GWS_REG_OFST (0x2C) /**< (XDMAC_GWS) Global Channel Write Suspend Register Offset */ +#define XDMAC_GRWS_REG_OFST (0x30) /**< (XDMAC_GRWS) Global Channel Read Write Suspend Register Offset */ +#define XDMAC_GRWR_REG_OFST (0x34) /**< (XDMAC_GRWR) Global Channel Read Write Resume Register Offset */ +#define XDMAC_GSWR_REG_OFST (0x38) /**< (XDMAC_GSWR) Global Channel Software Request Register Offset */ +#define XDMAC_GSWS_REG_OFST (0x3C) /**< (XDMAC_GSWS) Global Channel Software Request Status Register Offset */ +#define XDMAC_GSWF_REG_OFST (0x40) /**< (XDMAC_GSWF) Global Channel Software Flush Request Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XDMAC_CHID register API structure */ +typedef struct +{ + __O uint32_t XDMAC_CIE; /**< Offset: 0x00 ( /W 32) Channel Interrupt Enable Register (chid = 0) */ + __O uint32_t XDMAC_CID; /**< Offset: 0x04 ( /W 32) Channel Interrupt Disable Register (chid = 0) */ + __I uint32_t XDMAC_CIM; /**< Offset: 0x08 (R/ 32) Channel Interrupt Mask Register (chid = 0) */ + __I uint32_t XDMAC_CIS; /**< Offset: 0x0C (R/ 32) Channel Interrupt Status Register (chid = 0) */ + __IO uint32_t XDMAC_CSA; /**< Offset: 0x10 (R/W 32) Channel Source Address Register (chid = 0) */ + __IO uint32_t XDMAC_CDA; /**< Offset: 0x14 (R/W 32) Channel Destination Address Register (chid = 0) */ + __IO uint32_t XDMAC_CNDA; /**< Offset: 0x18 (R/W 32) Channel Next Descriptor Address Register (chid = 0) */ + __IO uint32_t XDMAC_CNDC; /**< Offset: 0x1C (R/W 32) Channel Next Descriptor Control Register (chid = 0) */ + __IO uint32_t XDMAC_CUBC; /**< Offset: 0x20 (R/W 32) Channel Microblock Control Register (chid = 0) */ + __IO uint32_t XDMAC_CBC; /**< Offset: 0x24 (R/W 32) Channel Block Control Register (chid = 0) */ + __IO uint32_t XDMAC_CC; /**< Offset: 0x28 (R/W 32) Channel Configuration Register (chid = 0) */ + __IO uint32_t XDMAC_CDS_MSP; /**< Offset: 0x2C (R/W 32) Channel Data Stride Memory Set Pattern (chid = 0) */ + __IO uint32_t XDMAC_CSUS; /**< Offset: 0x30 (R/W 32) Channel Source Microblock Stride (chid = 0) */ + __IO uint32_t XDMAC_CDUS; /**< Offset: 0x34 (R/W 32) Channel Destination Microblock Stride (chid = 0) */ + __I uint8_t Reserved1[0x08]; +} xdmac_chid_registers_t; + +#define XDMAC_CHID_NUMBER _U_(24) + +/** \brief XDMAC register API structure */ +typedef struct +{ + __I uint32_t XDMAC_GTYPE; /**< Offset: 0x00 (R/ 32) Global Type Register */ + __IO uint32_t XDMAC_GCFG; /**< Offset: 0x04 (R/W 32) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< Offset: 0x08 (R/W 32) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< Offset: 0x0C ( /W 32) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< Offset: 0x10 ( /W 32) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< Offset: 0x14 (R/ 32) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< Offset: 0x18 (R/ 32) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< Offset: 0x1C ( /W 32) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< Offset: 0x20 ( /W 32) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< Offset: 0x24 (R/ 32) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< Offset: 0x28 (R/W 32) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< Offset: 0x2C (R/W 32) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< Offset: 0x30 ( /W 32) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< Offset: 0x34 ( /W 32) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< Offset: 0x38 ( /W 32) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< Offset: 0x3C (R/ 32) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< Offset: 0x40 ( /W 32) Global Channel Software Flush Request Register */ + __I uint8_t Reserved1[0x0C]; + xdmac_chid_registers_t XDMAC_CHID[XDMAC_CHID_NUMBER]; /**< Offset: 0x50 Channel Interrupt Enable Register (chid = 0) */ +} xdmac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_XDMAC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j19.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j19.h new file mode 100644 index 00000000..7f577baa --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j19.h @@ -0,0 +1,724 @@ +/** + * \brief Peripheral I/O description for SAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2018-01-08T14:00:00Z */ +#ifndef _SAME70J19_GPIO_H_ +#define _SAME70J19_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ + +#endif /* _SAME70J19_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j20.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j20.h new file mode 100644 index 00000000..06b9cd3a --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j20.h @@ -0,0 +1,724 @@ +/** + * \brief Peripheral I/O description for SAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70J20_GPIO_H_ +#define _SAME70J20_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ + +#endif /* _SAME70J20_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j21.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j21.h new file mode 100644 index 00000000..cadfe1fe --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70j21.h @@ -0,0 +1,724 @@ +/** + * \brief Peripheral I/O description for SAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70J21_GPIO_H_ +#define _SAME70J21_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ + +#endif /* _SAME70J21_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n19.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n19.h new file mode 100644 index 00000000..ab901ac2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n19.h @@ -0,0 +1,848 @@ +/** + * \brief Peripheral I/O description for SAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N19_GPIO_H_ +#define _SAME70N19_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ + +#endif /* _SAME70N19_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n20.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n20.h new file mode 100644 index 00000000..b0ba6bbb --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n20.h @@ -0,0 +1,848 @@ +/** + * \brief Peripheral I/O description for SAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N20_GPIO_H_ +#define _SAME70N20_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ + +#endif /* _SAME70N20_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n21.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n21.h new file mode 100644 index 00000000..0950dce7 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70n21.h @@ -0,0 +1,848 @@ +/** + * \brief Peripheral I/O description for SAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N21_GPIO_H_ +#define _SAME70N21_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ + +#endif /* _SAME70N21_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q19.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q19.h new file mode 100644 index 00000000..eb8fe40a --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q19.h @@ -0,0 +1,1712 @@ +/** + * \brief Peripheral I/O description for SAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70Q19_GPIO_H_ +#define _SAME70Q19_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SDRAMC peripheral ========== */ +#define PIN_PC18A_SDRAMC_A0 _L_(82) /**< SDRAMC signal: SDRAMC_A0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_A0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A0 */ +#define PIO_PC18A_SDRAMC_A0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A0 */ +#define PIN_PC19A_SDRAMC_A1 _L_(83) /**< SDRAMC signal: SDRAMC_A1 on PC19 mux A */ +#define MUX_PC19A_SDRAMC_A1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A1 */ +#define PIO_PC19A_SDRAMC_A1 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A1 */ +#define PIN_PC20A_SDRAMC_A2 _L_(84) /**< SDRAMC signal: SDRAMC_A2 on PC20 mux A */ +#define MUX_PC20A_SDRAMC_A2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A2 */ +#define PIO_PC20A_SDRAMC_A2 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A2 */ +#define PIN_PC21A_SDRAMC_A3 _L_(85) /**< SDRAMC signal: SDRAMC_A3 on PC21 mux A */ +#define MUX_PC21A_SDRAMC_A3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A3 */ +#define PIO_PC21A_SDRAMC_A3 (_U_(1) << 21) /**< SDRAMC signal: SDRAMC_A3 */ +#define PIN_PC22A_SDRAMC_A4 _L_(86) /**< SDRAMC signal: SDRAMC_A4 on PC22 mux A */ +#define MUX_PC22A_SDRAMC_A4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A4 */ +#define PIO_PC22A_SDRAMC_A4 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_A4 */ +#define PIN_PC23A_SDRAMC_A5 _L_(87) /**< SDRAMC signal: SDRAMC_A5 on PC23 mux A */ +#define MUX_PC23A_SDRAMC_A5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A5 */ +#define PIO_PC23A_SDRAMC_A5 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A5 */ +#define PIN_PC24A_SDRAMC_A6 _L_(88) /**< SDRAMC signal: SDRAMC_A6 on PC24 mux A */ +#define MUX_PC24A_SDRAMC_A6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A6 */ +#define PIO_PC24A_SDRAMC_A6 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A6 */ +#define PIN_PC25A_SDRAMC_A7 _L_(89) /**< SDRAMC signal: SDRAMC_A7 on PC25 mux A */ +#define MUX_PC25A_SDRAMC_A7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A7 */ +#define PIO_PC25A_SDRAMC_A7 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A7 */ +#define PIN_PC26A_SDRAMC_A8 _L_(90) /**< SDRAMC signal: SDRAMC_A8 on PC26 mux A */ +#define MUX_PC26A_SDRAMC_A8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A8 */ +#define PIO_PC26A_SDRAMC_A8 (_U_(1) << 26) /**< SDRAMC signal: SDRAMC_A8 */ +#define PIN_PC27A_SDRAMC_A9 _L_(91) /**< SDRAMC signal: SDRAMC_A9 on PC27 mux A */ +#define MUX_PC27A_SDRAMC_A9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A9 */ +#define PIO_PC27A_SDRAMC_A9 (_U_(1) << 27) /**< SDRAMC signal: SDRAMC_A9 */ +#define PIN_PC28A_SDRAMC_A10 _L_(92) /**< SDRAMC signal: SDRAMC_A10 on PC28 mux A */ +#define MUX_PC28A_SDRAMC_A10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A10 */ +#define PIO_PC28A_SDRAMC_A10 (_U_(1) << 28) /**< SDRAMC signal: SDRAMC_A10 */ +#define PIN_PC29A_SDRAMC_A11 _L_(93) /**< SDRAMC signal: SDRAMC_A11 on PC29 mux A */ +#define MUX_PC29A_SDRAMC_A11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A11 */ +#define PIO_PC29A_SDRAMC_A11 (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_A11 */ +#define PIN_PC30A_SDRAMC_A12 _L_(94) /**< SDRAMC signal: SDRAMC_A12 on PC30 mux A */ +#define MUX_PC30A_SDRAMC_A12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A12 */ +#define PIO_PC30A_SDRAMC_A12 (_U_(1) << 30) /**< SDRAMC signal: SDRAMC_A12 */ +#define PIN_PC31A_SDRAMC_A13 _L_(95) /**< SDRAMC signal: SDRAMC_A13 on PC31 mux A */ +#define MUX_PC31A_SDRAMC_A13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A13 */ +#define PIO_PC31A_SDRAMC_A13 (_U_(1) << 31) /**< SDRAMC signal: SDRAMC_A13 */ +#define PIN_PA18C_SDRAMC_A14 _L_(18) /**< SDRAMC signal: SDRAMC_A14 on PA18 mux C */ +#define MUX_PA18C_SDRAMC_A14 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A14 */ +#define PIO_PA18C_SDRAMC_A14 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A14 */ +#define PIN_PA19C_SDRAMC_A15 _L_(19) /**< SDRAMC signal: SDRAMC_A15 on PA19 mux C */ +#define MUX_PA19C_SDRAMC_A15 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A15 */ +#define PIO_PA19C_SDRAMC_A15 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A15 */ +#define PIN_PA20C_SDRAMC_A16 _L_(20) /**< SDRAMC signal: SDRAMC_A16 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_A16 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A16 */ +#define PIO_PA20C_SDRAMC_A16 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A16 */ +#define PIN_PA0C_SDRAMC_A17 _L_(0) /**< SDRAMC signal: SDRAMC_A17 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_A17 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A17 */ +#define PIO_PA0C_SDRAMC_A17 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_A17 */ +#define PIN_PA1C_SDRAMC_A18 _L_(1) /**< SDRAMC signal: SDRAMC_A18 on PA1 mux C */ +#define MUX_PA1C_SDRAMC_A18 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A18 */ +#define PIO_PA1C_SDRAMC_A18 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_A18 */ +#define PIN_PA23C_SDRAMC_A19 _L_(23) /**< SDRAMC signal: SDRAMC_A19 on PA23 mux C */ +#define MUX_PA23C_SDRAMC_A19 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A19 */ +#define PIO_PA23C_SDRAMC_A19 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A19 */ +#define PIN_PA24C_SDRAMC_A20 _L_(24) /**< SDRAMC signal: SDRAMC_A20 on PA24 mux C */ +#define MUX_PA24C_SDRAMC_A20 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A20 */ +#define PIO_PA24C_SDRAMC_A20 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A20 */ +#define PIN_PC16A_SDRAMC_A21 _L_(80) /**< SDRAMC signal: SDRAMC_A21 on PC16 mux A */ +#define MUX_PC16A_SDRAMC_A21 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A21 */ +#define PIO_PC16A_SDRAMC_A21 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_A21 */ +#define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: SDRAMC_A22 on PC17 mux A */ +#define MUX_PC17A_SDRAMC_A22 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A22 */ +#define PIO_PC17A_SDRAMC_A22 (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_A22 */ +#define PIN_PA25C_SDRAMC_A23 _L_(25) /**< SDRAMC signal: SDRAMC_A23 on PA25 mux C */ +#define MUX_PA25C_SDRAMC_A23 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A23 */ +#define PIO_PA25C_SDRAMC_A23 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A23 */ +#define PIN_PA20C_SDRAMC_BA0 _L_(20) /**< SDRAMC signal: SDRAMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_BA0 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA0 */ +#define PIO_PA20C_SDRAMC_BA0 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_BA0 */ +#define PIN_PA0C_SDRAMC_BA1 _L_(0) /**< SDRAMC signal: SDRAMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_BA1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA1 */ +#define PIO_PA0C_SDRAMC_BA1 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_BA1 */ +#define PIN_PD17C_SDRAMC_CAS _L_(113) /**< SDRAMC signal: SDRAMC_CAS on PD17 mux C */ +#define MUX_PD17C_SDRAMC_CAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_CAS */ +#define PIO_PD17C_SDRAMC_CAS (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_CAS */ +#define PIN_PC0A_SDRAMC_D0 _L_(64) /**< SDRAMC signal: SDRAMC_D0 on PC0 mux A */ +#define MUX_PC0A_SDRAMC_D0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D0 */ +#define PIO_PC0A_SDRAMC_D0 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D0 */ +#define PIN_PC1A_SDRAMC_D1 _L_(65) /**< SDRAMC signal: SDRAMC_D1 on PC1 mux A */ +#define MUX_PC1A_SDRAMC_D1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D1 */ +#define PIO_PC1A_SDRAMC_D1 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D1 */ +#define PIN_PC2A_SDRAMC_D2 _L_(66) /**< SDRAMC signal: SDRAMC_D2 on PC2 mux A */ +#define MUX_PC2A_SDRAMC_D2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D2 */ +#define PIO_PC2A_SDRAMC_D2 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D2 */ +#define PIN_PC3A_SDRAMC_D3 _L_(67) /**< SDRAMC signal: SDRAMC_D3 on PC3 mux A */ +#define MUX_PC3A_SDRAMC_D3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D3 */ +#define PIO_PC3A_SDRAMC_D3 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D3 */ +#define PIN_PC4A_SDRAMC_D4 _L_(68) /**< SDRAMC signal: SDRAMC_D4 on PC4 mux A */ +#define MUX_PC4A_SDRAMC_D4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D4 */ +#define PIO_PC4A_SDRAMC_D4 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D4 */ +#define PIN_PC5A_SDRAMC_D5 _L_(69) /**< SDRAMC signal: SDRAMC_D5 on PC5 mux A */ +#define MUX_PC5A_SDRAMC_D5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D5 */ +#define PIO_PC5A_SDRAMC_D5 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D5 */ +#define PIN_PC6A_SDRAMC_D6 _L_(70) /**< SDRAMC signal: SDRAMC_D6 on PC6 mux A */ +#define MUX_PC6A_SDRAMC_D6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D6 */ +#define PIO_PC6A_SDRAMC_D6 (_U_(1) << 6) /**< SDRAMC signal: SDRAMC_D6 */ +#define PIN_PC7A_SDRAMC_D7 _L_(71) /**< SDRAMC signal: SDRAMC_D7 on PC7 mux A */ +#define MUX_PC7A_SDRAMC_D7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D7 */ +#define PIO_PC7A_SDRAMC_D7 (_U_(1) << 7) /**< SDRAMC signal: SDRAMC_D7 */ +#define PIN_PE0A_SDRAMC_D8 _L_(128) /**< SDRAMC signal: SDRAMC_D8 on PE0 mux A */ +#define MUX_PE0A_SDRAMC_D8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D8 */ +#define PIO_PE0A_SDRAMC_D8 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D8 */ +#define PIN_PE1A_SDRAMC_D9 _L_(129) /**< SDRAMC signal: SDRAMC_D9 on PE1 mux A */ +#define MUX_PE1A_SDRAMC_D9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D9 */ +#define PIO_PE1A_SDRAMC_D9 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D9 */ +#define PIN_PE2A_SDRAMC_D10 _L_(130) /**< SDRAMC signal: SDRAMC_D10 on PE2 mux A */ +#define MUX_PE2A_SDRAMC_D10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D10 */ +#define PIO_PE2A_SDRAMC_D10 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D10 */ +#define PIN_PE3A_SDRAMC_D11 _L_(131) /**< SDRAMC signal: SDRAMC_D11 on PE3 mux A */ +#define MUX_PE3A_SDRAMC_D11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D11 */ +#define PIO_PE3A_SDRAMC_D11 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D11 */ +#define PIN_PE4A_SDRAMC_D12 _L_(132) /**< SDRAMC signal: SDRAMC_D12 on PE4 mux A */ +#define MUX_PE4A_SDRAMC_D12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D12 */ +#define PIO_PE4A_SDRAMC_D12 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D12 */ +#define PIN_PE5A_SDRAMC_D13 _L_(133) /**< SDRAMC signal: SDRAMC_D13 on PE5 mux A */ +#define MUX_PE5A_SDRAMC_D13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D13 */ +#define PIO_PE5A_SDRAMC_D13 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D13 */ +#define PIN_PA15A_SDRAMC_D14 _L_(15) /**< SDRAMC signal: SDRAMC_D14 on PA15 mux A */ +#define MUX_PA15A_SDRAMC_D14 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D14 */ +#define PIO_PA15A_SDRAMC_D14 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_D14 */ +#define PIN_PA16A_SDRAMC_D15 _L_(16) /**< SDRAMC signal: SDRAMC_D15 on PA16 mux A */ +#define MUX_PA16A_SDRAMC_D15 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D15 */ +#define PIO_PA16A_SDRAMC_D15 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_D15 */ +#define PIN_PC16A_SDRAMC_NANDALE _L_(80) /**< SDRAMC signal: SDRAMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SDRAMC_NANDALE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDALE */ +#define PIO_PC16A_SDRAMC_NANDALE (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_NANDALE */ +#define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: SDRAMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SDRAMC_NANDCLE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDCLE */ +#define PIO_PC17A_SDRAMC_NANDCLE (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_NANDCLE */ +#define PIN_PC9A_SDRAMC_NANDOE _L_(73) /**< SDRAMC signal: SDRAMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SDRAMC_NANDOE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDOE */ +#define PIO_PC9A_SDRAMC_NANDOE (_U_(1) << 9) /**< SDRAMC signal: SDRAMC_NANDOE */ +#define PIN_PC10A_SDRAMC_NANDWE _L_(74) /**< SDRAMC signal: SDRAMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SDRAMC_NANDWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDWE */ +#define PIO_PC10A_SDRAMC_NANDWE (_U_(1) << 10) /**< SDRAMC signal: SDRAMC_NANDWE */ +#define PIN_PC18A_SDRAMC_NBS0 _L_(82) /**< SDRAMC signal: SDRAMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_NBS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NBS0 */ +#define PIO_PC18A_SDRAMC_NBS0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NBS0 */ +#define PIN_PD15C_SDRAMC_NBS1 _L_(111) /**< SDRAMC signal: SDRAMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NBS1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NBS1 */ +#define PIO_PD15C_SDRAMC_NBS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NBS1 */ +#define PIN_PC14A_SDRAMC_NCS0 _L_(78) /**< SDRAMC signal: SDRAMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SDRAMC_NCS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS0 */ +#define PIO_PC14A_SDRAMC_NCS0 (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_NCS0 */ +#define PIN_PC15A_SDRAMC_NCS1 _L_(79) /**< SDRAMC signal: SDRAMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PC15A_SDRAMC_NCS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PD18A_SDRAMC_NCS1 _L_(114) /**< SDRAMC signal: SDRAMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PD18A_SDRAMC_NCS1 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PA22C_SDRAMC_NCS2 _L_(22) /**< SDRAMC signal: SDRAMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SDRAMC_NCS2 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NCS2 */ +#define PIO_PA22C_SDRAMC_NCS2 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_NCS2 */ +#define PIN_PC12A_SDRAMC_NCS3 _L_(76) /**< SDRAMC signal: SDRAMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PC12A_SDRAMC_NCS3 (_U_(1) << 12) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PD19A_SDRAMC_NCS3 _L_(115) /**< SDRAMC signal: SDRAMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PD19A_SDRAMC_NCS3 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PC11A_SDRAMC_NRD _L_(75) /**< SDRAMC signal: SDRAMC_NRD on PC11 mux A */ +#define MUX_PC11A_SDRAMC_NRD _L_(0) /**< SDRAMC signal line function value: SDRAMC_NRD */ +#define PIO_PC11A_SDRAMC_NRD (_U_(1) << 11) /**< SDRAMC signal: SDRAMC_NRD */ +#define PIN_PC13A_SDRAMC_NWAIT _L_(77) /**< SDRAMC signal: SDRAMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SDRAMC_NWAIT _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWAIT */ +#define PIO_PC13A_SDRAMC_NWAIT (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_NWAIT */ +#define PIN_PC8A_SDRAMC_NWE _L_(72) /**< SDRAMC signal: SDRAMC_NWE on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWE */ +#define PIO_PC8A_SDRAMC_NWE (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWE */ +#define PIN_PC8A_SDRAMC_NWR0 _L_(72) /**< SDRAMC signal: SDRAMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWR0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWR0 */ +#define PIO_PC8A_SDRAMC_NWR0 (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWR0 */ +#define PIN_PD15C_SDRAMC_NWR1 _L_(111) /**< SDRAMC signal: SDRAMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NWR1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NWR1 */ +#define PIO_PD15C_SDRAMC_NWR1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NWR1 */ +#define PIN_PD16C_SDRAMC_RAS _L_(112) /**< SDRAMC signal: SDRAMC_RAS on PD16 mux C */ +#define MUX_PD16C_SDRAMC_RAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_RAS */ +#define PIO_PD16C_SDRAMC_RAS (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_RAS */ +#define PIN_PC13C_SDRAMC_SDA10 _L_(77) /**< SDRAMC signal: SDRAMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PC13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD13C_SDRAMC_SDA10 _L_(109) /**< SDRAMC signal: SDRAMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PD13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD23C_SDRAMC_SDCK _L_(119) /**< SDRAMC signal: SDRAMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SDRAMC_SDCK _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCK */ +#define PIO_PD23C_SDRAMC_SDCK (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_SDCK */ +#define PIN_PD14C_SDRAMC_SDCKE _L_(110) /**< SDRAMC signal: SDRAMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SDRAMC_SDCKE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCKE */ +#define PIO_PD14C_SDRAMC_SDCKE (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_SDCKE */ +#define PIN_PC15A_SDRAMC_SDCS _L_(79) /**< SDRAMC signal: SDRAMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PC15A_SDRAMC_SDCS (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD18A_SDRAMC_SDCS _L_(114) /**< SDRAMC signal: SDRAMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PD18A_SDRAMC_SDCS (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD29C_SDRAMC_SDWE _L_(125) /**< SDRAMC signal: SDRAMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SDRAMC_SDWE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDWE */ +#define PIO_PD29C_SDRAMC_SDWE (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_SDWE */ +/* ========== PIO definition for SMC peripheral ========== */ +#define PIN_PC18A_SMC_A0 _L_(82) /**< SMC signal: SMC_A0 on PC18 mux A */ +#define MUX_PC18A_SMC_A0 _L_(0) /**< SMC signal line function value: SMC_A0 */ +#define PIO_PC18A_SMC_A0 (_U_(1) << 18) /**< SMC signal: SMC_A0 */ +#define PIN_PC19A_SMC_A1 _L_(83) /**< SMC signal: SMC_A1 on PC19 mux A */ +#define MUX_PC19A_SMC_A1 _L_(0) /**< SMC signal line function value: SMC_A1 */ +#define PIO_PC19A_SMC_A1 (_U_(1) << 19) /**< SMC signal: SMC_A1 */ +#define PIN_PC20A_SMC_A2 _L_(84) /**< SMC signal: SMC_A2 on PC20 mux A */ +#define MUX_PC20A_SMC_A2 _L_(0) /**< SMC signal line function value: SMC_A2 */ +#define PIO_PC20A_SMC_A2 (_U_(1) << 20) /**< SMC signal: SMC_A2 */ +#define PIN_PC21A_SMC_A3 _L_(85) /**< SMC signal: SMC_A3 on PC21 mux A */ +#define MUX_PC21A_SMC_A3 _L_(0) /**< SMC signal line function value: SMC_A3 */ +#define PIO_PC21A_SMC_A3 (_U_(1) << 21) /**< SMC signal: SMC_A3 */ +#define PIN_PC22A_SMC_A4 _L_(86) /**< SMC signal: SMC_A4 on PC22 mux A */ +#define MUX_PC22A_SMC_A4 _L_(0) /**< SMC signal line function value: SMC_A4 */ +#define PIO_PC22A_SMC_A4 (_U_(1) << 22) /**< SMC signal: SMC_A4 */ +#define PIN_PC23A_SMC_A5 _L_(87) /**< SMC signal: SMC_A5 on PC23 mux A */ +#define MUX_PC23A_SMC_A5 _L_(0) /**< SMC signal line function value: SMC_A5 */ +#define PIO_PC23A_SMC_A5 (_U_(1) << 23) /**< SMC signal: SMC_A5 */ +#define PIN_PC24A_SMC_A6 _L_(88) /**< SMC signal: SMC_A6 on PC24 mux A */ +#define MUX_PC24A_SMC_A6 _L_(0) /**< SMC signal line function value: SMC_A6 */ +#define PIO_PC24A_SMC_A6 (_U_(1) << 24) /**< SMC signal: SMC_A6 */ +#define PIN_PC25A_SMC_A7 _L_(89) /**< SMC signal: SMC_A7 on PC25 mux A */ +#define MUX_PC25A_SMC_A7 _L_(0) /**< SMC signal line function value: SMC_A7 */ +#define PIO_PC25A_SMC_A7 (_U_(1) << 25) /**< SMC signal: SMC_A7 */ +#define PIN_PC26A_SMC_A8 _L_(90) /**< SMC signal: SMC_A8 on PC26 mux A */ +#define MUX_PC26A_SMC_A8 _L_(0) /**< SMC signal line function value: SMC_A8 */ +#define PIO_PC26A_SMC_A8 (_U_(1) << 26) /**< SMC signal: SMC_A8 */ +#define PIN_PC27A_SMC_A9 _L_(91) /**< SMC signal: SMC_A9 on PC27 mux A */ +#define MUX_PC27A_SMC_A9 _L_(0) /**< SMC signal line function value: SMC_A9 */ +#define PIO_PC27A_SMC_A9 (_U_(1) << 27) /**< SMC signal: SMC_A9 */ +#define PIN_PC28A_SMC_A10 _L_(92) /**< SMC signal: SMC_A10 on PC28 mux A */ +#define MUX_PC28A_SMC_A10 _L_(0) /**< SMC signal line function value: SMC_A10 */ +#define PIO_PC28A_SMC_A10 (_U_(1) << 28) /**< SMC signal: SMC_A10 */ +#define PIN_PC29A_SMC_A11 _L_(93) /**< SMC signal: SMC_A11 on PC29 mux A */ +#define MUX_PC29A_SMC_A11 _L_(0) /**< SMC signal line function value: SMC_A11 */ +#define PIO_PC29A_SMC_A11 (_U_(1) << 29) /**< SMC signal: SMC_A11 */ +#define PIN_PC30A_SMC_A12 _L_(94) /**< SMC signal: SMC_A12 on PC30 mux A */ +#define MUX_PC30A_SMC_A12 _L_(0) /**< SMC signal line function value: SMC_A12 */ +#define PIO_PC30A_SMC_A12 (_U_(1) << 30) /**< SMC signal: SMC_A12 */ +#define PIN_PC31A_SMC_A13 _L_(95) /**< SMC signal: SMC_A13 on PC31 mux A */ +#define MUX_PC31A_SMC_A13 _L_(0) /**< SMC signal line function value: SMC_A13 */ +#define PIO_PC31A_SMC_A13 (_U_(1) << 31) /**< SMC signal: SMC_A13 */ +#define PIN_PA18C_SMC_A14 _L_(18) /**< SMC signal: SMC_A14 on PA18 mux C */ +#define MUX_PA18C_SMC_A14 _L_(2) /**< SMC signal line function value: SMC_A14 */ +#define PIO_PA18C_SMC_A14 (_U_(1) << 18) /**< SMC signal: SMC_A14 */ +#define PIN_PA19C_SMC_A15 _L_(19) /**< SMC signal: SMC_A15 on PA19 mux C */ +#define MUX_PA19C_SMC_A15 _L_(2) /**< SMC signal line function value: SMC_A15 */ +#define PIO_PA19C_SMC_A15 (_U_(1) << 19) /**< SMC signal: SMC_A15 */ +#define PIN_PA20C_SMC_A16 _L_(20) /**< SMC signal: SMC_A16 on PA20 mux C */ +#define MUX_PA20C_SMC_A16 _L_(2) /**< SMC signal line function value: SMC_A16 */ +#define PIO_PA20C_SMC_A16 (_U_(1) << 20) /**< SMC signal: SMC_A16 */ +#define PIN_PA0C_SMC_A17 _L_(0) /**< SMC signal: SMC_A17 on PA0 mux C */ +#define MUX_PA0C_SMC_A17 _L_(2) /**< SMC signal line function value: SMC_A17 */ +#define PIO_PA0C_SMC_A17 (_U_(1) << 0) /**< SMC signal: SMC_A17 */ +#define PIN_PA1C_SMC_A18 _L_(1) /**< SMC signal: SMC_A18 on PA1 mux C */ +#define MUX_PA1C_SMC_A18 _L_(2) /**< SMC signal line function value: SMC_A18 */ +#define PIO_PA1C_SMC_A18 (_U_(1) << 1) /**< SMC signal: SMC_A18 */ +#define PIN_PA23C_SMC_A19 _L_(23) /**< SMC signal: SMC_A19 on PA23 mux C */ +#define MUX_PA23C_SMC_A19 _L_(2) /**< SMC signal line function value: SMC_A19 */ +#define PIO_PA23C_SMC_A19 (_U_(1) << 23) /**< SMC signal: SMC_A19 */ +#define PIN_PA24C_SMC_A20 _L_(24) /**< SMC signal: SMC_A20 on PA24 mux C */ +#define MUX_PA24C_SMC_A20 _L_(2) /**< SMC signal line function value: SMC_A20 */ +#define PIO_PA24C_SMC_A20 (_U_(1) << 24) /**< SMC signal: SMC_A20 */ +#define PIN_PC16A_SMC_A21 _L_(80) /**< SMC signal: SMC_A21 on PC16 mux A */ +#define MUX_PC16A_SMC_A21 _L_(0) /**< SMC signal line function value: SMC_A21 */ +#define PIO_PC16A_SMC_A21 (_U_(1) << 16) /**< SMC signal: SMC_A21 */ +#define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: SMC_A22 on PC17 mux A */ +#define MUX_PC17A_SMC_A22 _L_(0) /**< SMC signal line function value: SMC_A22 */ +#define PIO_PC17A_SMC_A22 (_U_(1) << 17) /**< SMC signal: SMC_A22 */ +#define PIN_PA25C_SMC_A23 _L_(25) /**< SMC signal: SMC_A23 on PA25 mux C */ +#define MUX_PA25C_SMC_A23 _L_(2) /**< SMC signal line function value: SMC_A23 */ +#define PIO_PA25C_SMC_A23 (_U_(1) << 25) /**< SMC signal: SMC_A23 */ +#define PIN_PA20C_SMC_BA0 _L_(20) /**< SMC signal: SMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SMC_BA0 _L_(2) /**< SMC signal line function value: SMC_BA0 */ +#define PIO_PA20C_SMC_BA0 (_U_(1) << 20) /**< SMC signal: SMC_BA0 */ +#define PIN_PA0C_SMC_BA1 _L_(0) /**< SMC signal: SMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SMC_BA1 _L_(2) /**< SMC signal line function value: SMC_BA1 */ +#define PIO_PA0C_SMC_BA1 (_U_(1) << 0) /**< SMC signal: SMC_BA1 */ +#define PIN_PD17C_SMC_CAS _L_(113) /**< SMC signal: SMC_CAS on PD17 mux C */ +#define MUX_PD17C_SMC_CAS _L_(2) /**< SMC signal line function value: SMC_CAS */ +#define PIO_PD17C_SMC_CAS (_U_(1) << 17) /**< SMC signal: SMC_CAS */ +#define PIN_PC0A_SMC_D0 _L_(64) /**< SMC signal: SMC_D0 on PC0 mux A */ +#define MUX_PC0A_SMC_D0 _L_(0) /**< SMC signal line function value: SMC_D0 */ +#define PIO_PC0A_SMC_D0 (_U_(1) << 0) /**< SMC signal: SMC_D0 */ +#define PIN_PC1A_SMC_D1 _L_(65) /**< SMC signal: SMC_D1 on PC1 mux A */ +#define MUX_PC1A_SMC_D1 _L_(0) /**< SMC signal line function value: SMC_D1 */ +#define PIO_PC1A_SMC_D1 (_U_(1) << 1) /**< SMC signal: SMC_D1 */ +#define PIN_PC2A_SMC_D2 _L_(66) /**< SMC signal: SMC_D2 on PC2 mux A */ +#define MUX_PC2A_SMC_D2 _L_(0) /**< SMC signal line function value: SMC_D2 */ +#define PIO_PC2A_SMC_D2 (_U_(1) << 2) /**< SMC signal: SMC_D2 */ +#define PIN_PC3A_SMC_D3 _L_(67) /**< SMC signal: SMC_D3 on PC3 mux A */ +#define MUX_PC3A_SMC_D3 _L_(0) /**< SMC signal line function value: SMC_D3 */ +#define PIO_PC3A_SMC_D3 (_U_(1) << 3) /**< SMC signal: SMC_D3 */ +#define PIN_PC4A_SMC_D4 _L_(68) /**< SMC signal: SMC_D4 on PC4 mux A */ +#define MUX_PC4A_SMC_D4 _L_(0) /**< SMC signal line function value: SMC_D4 */ +#define PIO_PC4A_SMC_D4 (_U_(1) << 4) /**< SMC signal: SMC_D4 */ +#define PIN_PC5A_SMC_D5 _L_(69) /**< SMC signal: SMC_D5 on PC5 mux A */ +#define MUX_PC5A_SMC_D5 _L_(0) /**< SMC signal line function value: SMC_D5 */ +#define PIO_PC5A_SMC_D5 (_U_(1) << 5) /**< SMC signal: SMC_D5 */ +#define PIN_PC6A_SMC_D6 _L_(70) /**< SMC signal: SMC_D6 on PC6 mux A */ +#define MUX_PC6A_SMC_D6 _L_(0) /**< SMC signal line function value: SMC_D6 */ +#define PIO_PC6A_SMC_D6 (_U_(1) << 6) /**< SMC signal: SMC_D6 */ +#define PIN_PC7A_SMC_D7 _L_(71) /**< SMC signal: SMC_D7 on PC7 mux A */ +#define MUX_PC7A_SMC_D7 _L_(0) /**< SMC signal line function value: SMC_D7 */ +#define PIO_PC7A_SMC_D7 (_U_(1) << 7) /**< SMC signal: SMC_D7 */ +#define PIN_PE0A_SMC_D8 _L_(128) /**< SMC signal: SMC_D8 on PE0 mux A */ +#define MUX_PE0A_SMC_D8 _L_(0) /**< SMC signal line function value: SMC_D8 */ +#define PIO_PE0A_SMC_D8 (_U_(1) << 0) /**< SMC signal: SMC_D8 */ +#define PIN_PE1A_SMC_D9 _L_(129) /**< SMC signal: SMC_D9 on PE1 mux A */ +#define MUX_PE1A_SMC_D9 _L_(0) /**< SMC signal line function value: SMC_D9 */ +#define PIO_PE1A_SMC_D9 (_U_(1) << 1) /**< SMC signal: SMC_D9 */ +#define PIN_PE2A_SMC_D10 _L_(130) /**< SMC signal: SMC_D10 on PE2 mux A */ +#define MUX_PE2A_SMC_D10 _L_(0) /**< SMC signal line function value: SMC_D10 */ +#define PIO_PE2A_SMC_D10 (_U_(1) << 2) /**< SMC signal: SMC_D10 */ +#define PIN_PE3A_SMC_D11 _L_(131) /**< SMC signal: SMC_D11 on PE3 mux A */ +#define MUX_PE3A_SMC_D11 _L_(0) /**< SMC signal line function value: SMC_D11 */ +#define PIO_PE3A_SMC_D11 (_U_(1) << 3) /**< SMC signal: SMC_D11 */ +#define PIN_PE4A_SMC_D12 _L_(132) /**< SMC signal: SMC_D12 on PE4 mux A */ +#define MUX_PE4A_SMC_D12 _L_(0) /**< SMC signal line function value: SMC_D12 */ +#define PIO_PE4A_SMC_D12 (_U_(1) << 4) /**< SMC signal: SMC_D12 */ +#define PIN_PE5A_SMC_D13 _L_(133) /**< SMC signal: SMC_D13 on PE5 mux A */ +#define MUX_PE5A_SMC_D13 _L_(0) /**< SMC signal line function value: SMC_D13 */ +#define PIO_PE5A_SMC_D13 (_U_(1) << 5) /**< SMC signal: SMC_D13 */ +#define PIN_PA15A_SMC_D14 _L_(15) /**< SMC signal: SMC_D14 on PA15 mux A */ +#define MUX_PA15A_SMC_D14 _L_(0) /**< SMC signal line function value: SMC_D14 */ +#define PIO_PA15A_SMC_D14 (_U_(1) << 15) /**< SMC signal: SMC_D14 */ +#define PIN_PA16A_SMC_D15 _L_(16) /**< SMC signal: SMC_D15 on PA16 mux A */ +#define MUX_PA16A_SMC_D15 _L_(0) /**< SMC signal line function value: SMC_D15 */ +#define PIO_PA16A_SMC_D15 (_U_(1) << 16) /**< SMC signal: SMC_D15 */ +#define PIN_PC16A_SMC_NANDALE _L_(80) /**< SMC signal: SMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SMC_NANDALE _L_(0) /**< SMC signal line function value: SMC_NANDALE */ +#define PIO_PC16A_SMC_NANDALE (_U_(1) << 16) /**< SMC signal: SMC_NANDALE */ +#define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: SMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SMC_NANDCLE _L_(0) /**< SMC signal line function value: SMC_NANDCLE */ +#define PIO_PC17A_SMC_NANDCLE (_U_(1) << 17) /**< SMC signal: SMC_NANDCLE */ +#define PIN_PC9A_SMC_NANDOE _L_(73) /**< SMC signal: SMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SMC_NANDOE _L_(0) /**< SMC signal line function value: SMC_NANDOE */ +#define PIO_PC9A_SMC_NANDOE (_U_(1) << 9) /**< SMC signal: SMC_NANDOE */ +#define PIN_PC10A_SMC_NANDWE _L_(74) /**< SMC signal: SMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SMC_NANDWE _L_(0) /**< SMC signal line function value: SMC_NANDWE */ +#define PIO_PC10A_SMC_NANDWE (_U_(1) << 10) /**< SMC signal: SMC_NANDWE */ +#define PIN_PC18A_SMC_NBS0 _L_(82) /**< SMC signal: SMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SMC_NBS0 _L_(0) /**< SMC signal line function value: SMC_NBS0 */ +#define PIO_PC18A_SMC_NBS0 (_U_(1) << 18) /**< SMC signal: SMC_NBS0 */ +#define PIN_PD15C_SMC_NBS1 _L_(111) /**< SMC signal: SMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SMC_NBS1 _L_(2) /**< SMC signal line function value: SMC_NBS1 */ +#define PIO_PD15C_SMC_NBS1 (_U_(1) << 15) /**< SMC signal: SMC_NBS1 */ +#define PIN_PC14A_SMC_NCS0 _L_(78) /**< SMC signal: SMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SMC_NCS0 _L_(0) /**< SMC signal line function value: SMC_NCS0 */ +#define PIO_PC14A_SMC_NCS0 (_U_(1) << 14) /**< SMC signal: SMC_NCS0 */ +#define PIN_PC15A_SMC_NCS1 _L_(79) /**< SMC signal: SMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PC15A_SMC_NCS1 (_U_(1) << 15) /**< SMC signal: SMC_NCS1 */ +#define PIN_PD18A_SMC_NCS1 _L_(114) /**< SMC signal: SMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PD18A_SMC_NCS1 (_U_(1) << 18) /**< SMC signal: SMC_NCS1 */ +#define PIN_PA22C_SMC_NCS2 _L_(22) /**< SMC signal: SMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SMC_NCS2 _L_(2) /**< SMC signal line function value: SMC_NCS2 */ +#define PIO_PA22C_SMC_NCS2 (_U_(1) << 22) /**< SMC signal: SMC_NCS2 */ +#define PIN_PC12A_SMC_NCS3 _L_(76) /**< SMC signal: SMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PC12A_SMC_NCS3 (_U_(1) << 12) /**< SMC signal: SMC_NCS3 */ +#define PIN_PD19A_SMC_NCS3 _L_(115) /**< SMC signal: SMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PD19A_SMC_NCS3 (_U_(1) << 19) /**< SMC signal: SMC_NCS3 */ +#define PIN_PC11A_SMC_NRD _L_(75) /**< SMC signal: SMC_NRD on PC11 mux A */ +#define MUX_PC11A_SMC_NRD _L_(0) /**< SMC signal line function value: SMC_NRD */ +#define PIO_PC11A_SMC_NRD (_U_(1) << 11) /**< SMC signal: SMC_NRD */ +#define PIN_PC13A_SMC_NWAIT _L_(77) /**< SMC signal: SMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SMC_NWAIT _L_(0) /**< SMC signal line function value: SMC_NWAIT */ +#define PIO_PC13A_SMC_NWAIT (_U_(1) << 13) /**< SMC signal: SMC_NWAIT */ +#define PIN_PC8A_SMC_NWE _L_(72) /**< SMC signal: SMC_NWE on PC8 mux A */ +#define MUX_PC8A_SMC_NWE _L_(0) /**< SMC signal line function value: SMC_NWE */ +#define PIO_PC8A_SMC_NWE (_U_(1) << 8) /**< SMC signal: SMC_NWE */ +#define PIN_PC8A_SMC_NWR0 _L_(72) /**< SMC signal: SMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SMC_NWR0 _L_(0) /**< SMC signal line function value: SMC_NWR0 */ +#define PIO_PC8A_SMC_NWR0 (_U_(1) << 8) /**< SMC signal: SMC_NWR0 */ +#define PIN_PD15C_SMC_NWR1 _L_(111) /**< SMC signal: SMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SMC_NWR1 _L_(2) /**< SMC signal line function value: SMC_NWR1 */ +#define PIO_PD15C_SMC_NWR1 (_U_(1) << 15) /**< SMC signal: SMC_NWR1 */ +#define PIN_PD16C_SMC_RAS _L_(112) /**< SMC signal: SMC_RAS on PD16 mux C */ +#define MUX_PD16C_SMC_RAS _L_(2) /**< SMC signal line function value: SMC_RAS */ +#define PIO_PD16C_SMC_RAS (_U_(1) << 16) /**< SMC signal: SMC_RAS */ +#define PIN_PC13C_SMC_SDA10 _L_(77) /**< SMC signal: SMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PC13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD13C_SMC_SDA10 _L_(109) /**< SMC signal: SMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PD13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD23C_SMC_SDCK _L_(119) /**< SMC signal: SMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SMC_SDCK _L_(2) /**< SMC signal line function value: SMC_SDCK */ +#define PIO_PD23C_SMC_SDCK (_U_(1) << 23) /**< SMC signal: SMC_SDCK */ +#define PIN_PD14C_SMC_SDCKE _L_(110) /**< SMC signal: SMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SMC_SDCKE _L_(2) /**< SMC signal line function value: SMC_SDCKE */ +#define PIO_PD14C_SMC_SDCKE (_U_(1) << 14) /**< SMC signal: SMC_SDCKE */ +#define PIN_PC15A_SMC_SDCS _L_(79) /**< SMC signal: SMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PC15A_SMC_SDCS (_U_(1) << 15) /**< SMC signal: SMC_SDCS */ +#define PIN_PD18A_SMC_SDCS _L_(114) /**< SMC signal: SMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PD18A_SMC_SDCS (_U_(1) << 18) /**< SMC signal: SMC_SDCS */ +#define PIN_PD29C_SMC_SDWE _L_(125) /**< SMC signal: SMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SMC_SDWE _L_(2) /**< SMC signal line function value: SMC_SDWE */ +#define PIO_PD29C_SMC_SDWE (_U_(1) << 29) /**< SMC signal: SMC_SDWE */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ + +#endif /* _SAME70Q19_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q20.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q20.h new file mode 100644 index 00000000..2e5bf431 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q20.h @@ -0,0 +1,1712 @@ +/** + * \brief Peripheral I/O description for SAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70Q20_GPIO_H_ +#define _SAME70Q20_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SDRAMC peripheral ========== */ +#define PIN_PC18A_SDRAMC_A0 _L_(82) /**< SDRAMC signal: SDRAMC_A0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_A0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A0 */ +#define PIO_PC18A_SDRAMC_A0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A0 */ +#define PIN_PC19A_SDRAMC_A1 _L_(83) /**< SDRAMC signal: SDRAMC_A1 on PC19 mux A */ +#define MUX_PC19A_SDRAMC_A1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A1 */ +#define PIO_PC19A_SDRAMC_A1 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A1 */ +#define PIN_PC20A_SDRAMC_A2 _L_(84) /**< SDRAMC signal: SDRAMC_A2 on PC20 mux A */ +#define MUX_PC20A_SDRAMC_A2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A2 */ +#define PIO_PC20A_SDRAMC_A2 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A2 */ +#define PIN_PC21A_SDRAMC_A3 _L_(85) /**< SDRAMC signal: SDRAMC_A3 on PC21 mux A */ +#define MUX_PC21A_SDRAMC_A3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A3 */ +#define PIO_PC21A_SDRAMC_A3 (_U_(1) << 21) /**< SDRAMC signal: SDRAMC_A3 */ +#define PIN_PC22A_SDRAMC_A4 _L_(86) /**< SDRAMC signal: SDRAMC_A4 on PC22 mux A */ +#define MUX_PC22A_SDRAMC_A4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A4 */ +#define PIO_PC22A_SDRAMC_A4 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_A4 */ +#define PIN_PC23A_SDRAMC_A5 _L_(87) /**< SDRAMC signal: SDRAMC_A5 on PC23 mux A */ +#define MUX_PC23A_SDRAMC_A5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A5 */ +#define PIO_PC23A_SDRAMC_A5 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A5 */ +#define PIN_PC24A_SDRAMC_A6 _L_(88) /**< SDRAMC signal: SDRAMC_A6 on PC24 mux A */ +#define MUX_PC24A_SDRAMC_A6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A6 */ +#define PIO_PC24A_SDRAMC_A6 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A6 */ +#define PIN_PC25A_SDRAMC_A7 _L_(89) /**< SDRAMC signal: SDRAMC_A7 on PC25 mux A */ +#define MUX_PC25A_SDRAMC_A7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A7 */ +#define PIO_PC25A_SDRAMC_A7 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A7 */ +#define PIN_PC26A_SDRAMC_A8 _L_(90) /**< SDRAMC signal: SDRAMC_A8 on PC26 mux A */ +#define MUX_PC26A_SDRAMC_A8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A8 */ +#define PIO_PC26A_SDRAMC_A8 (_U_(1) << 26) /**< SDRAMC signal: SDRAMC_A8 */ +#define PIN_PC27A_SDRAMC_A9 _L_(91) /**< SDRAMC signal: SDRAMC_A9 on PC27 mux A */ +#define MUX_PC27A_SDRAMC_A9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A9 */ +#define PIO_PC27A_SDRAMC_A9 (_U_(1) << 27) /**< SDRAMC signal: SDRAMC_A9 */ +#define PIN_PC28A_SDRAMC_A10 _L_(92) /**< SDRAMC signal: SDRAMC_A10 on PC28 mux A */ +#define MUX_PC28A_SDRAMC_A10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A10 */ +#define PIO_PC28A_SDRAMC_A10 (_U_(1) << 28) /**< SDRAMC signal: SDRAMC_A10 */ +#define PIN_PC29A_SDRAMC_A11 _L_(93) /**< SDRAMC signal: SDRAMC_A11 on PC29 mux A */ +#define MUX_PC29A_SDRAMC_A11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A11 */ +#define PIO_PC29A_SDRAMC_A11 (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_A11 */ +#define PIN_PC30A_SDRAMC_A12 _L_(94) /**< SDRAMC signal: SDRAMC_A12 on PC30 mux A */ +#define MUX_PC30A_SDRAMC_A12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A12 */ +#define PIO_PC30A_SDRAMC_A12 (_U_(1) << 30) /**< SDRAMC signal: SDRAMC_A12 */ +#define PIN_PC31A_SDRAMC_A13 _L_(95) /**< SDRAMC signal: SDRAMC_A13 on PC31 mux A */ +#define MUX_PC31A_SDRAMC_A13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A13 */ +#define PIO_PC31A_SDRAMC_A13 (_U_(1) << 31) /**< SDRAMC signal: SDRAMC_A13 */ +#define PIN_PA18C_SDRAMC_A14 _L_(18) /**< SDRAMC signal: SDRAMC_A14 on PA18 mux C */ +#define MUX_PA18C_SDRAMC_A14 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A14 */ +#define PIO_PA18C_SDRAMC_A14 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A14 */ +#define PIN_PA19C_SDRAMC_A15 _L_(19) /**< SDRAMC signal: SDRAMC_A15 on PA19 mux C */ +#define MUX_PA19C_SDRAMC_A15 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A15 */ +#define PIO_PA19C_SDRAMC_A15 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A15 */ +#define PIN_PA20C_SDRAMC_A16 _L_(20) /**< SDRAMC signal: SDRAMC_A16 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_A16 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A16 */ +#define PIO_PA20C_SDRAMC_A16 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A16 */ +#define PIN_PA0C_SDRAMC_A17 _L_(0) /**< SDRAMC signal: SDRAMC_A17 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_A17 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A17 */ +#define PIO_PA0C_SDRAMC_A17 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_A17 */ +#define PIN_PA1C_SDRAMC_A18 _L_(1) /**< SDRAMC signal: SDRAMC_A18 on PA1 mux C */ +#define MUX_PA1C_SDRAMC_A18 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A18 */ +#define PIO_PA1C_SDRAMC_A18 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_A18 */ +#define PIN_PA23C_SDRAMC_A19 _L_(23) /**< SDRAMC signal: SDRAMC_A19 on PA23 mux C */ +#define MUX_PA23C_SDRAMC_A19 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A19 */ +#define PIO_PA23C_SDRAMC_A19 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A19 */ +#define PIN_PA24C_SDRAMC_A20 _L_(24) /**< SDRAMC signal: SDRAMC_A20 on PA24 mux C */ +#define MUX_PA24C_SDRAMC_A20 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A20 */ +#define PIO_PA24C_SDRAMC_A20 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A20 */ +#define PIN_PC16A_SDRAMC_A21 _L_(80) /**< SDRAMC signal: SDRAMC_A21 on PC16 mux A */ +#define MUX_PC16A_SDRAMC_A21 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A21 */ +#define PIO_PC16A_SDRAMC_A21 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_A21 */ +#define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: SDRAMC_A22 on PC17 mux A */ +#define MUX_PC17A_SDRAMC_A22 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A22 */ +#define PIO_PC17A_SDRAMC_A22 (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_A22 */ +#define PIN_PA25C_SDRAMC_A23 _L_(25) /**< SDRAMC signal: SDRAMC_A23 on PA25 mux C */ +#define MUX_PA25C_SDRAMC_A23 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A23 */ +#define PIO_PA25C_SDRAMC_A23 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A23 */ +#define PIN_PA20C_SDRAMC_BA0 _L_(20) /**< SDRAMC signal: SDRAMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_BA0 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA0 */ +#define PIO_PA20C_SDRAMC_BA0 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_BA0 */ +#define PIN_PA0C_SDRAMC_BA1 _L_(0) /**< SDRAMC signal: SDRAMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_BA1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA1 */ +#define PIO_PA0C_SDRAMC_BA1 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_BA1 */ +#define PIN_PD17C_SDRAMC_CAS _L_(113) /**< SDRAMC signal: SDRAMC_CAS on PD17 mux C */ +#define MUX_PD17C_SDRAMC_CAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_CAS */ +#define PIO_PD17C_SDRAMC_CAS (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_CAS */ +#define PIN_PC0A_SDRAMC_D0 _L_(64) /**< SDRAMC signal: SDRAMC_D0 on PC0 mux A */ +#define MUX_PC0A_SDRAMC_D0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D0 */ +#define PIO_PC0A_SDRAMC_D0 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D0 */ +#define PIN_PC1A_SDRAMC_D1 _L_(65) /**< SDRAMC signal: SDRAMC_D1 on PC1 mux A */ +#define MUX_PC1A_SDRAMC_D1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D1 */ +#define PIO_PC1A_SDRAMC_D1 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D1 */ +#define PIN_PC2A_SDRAMC_D2 _L_(66) /**< SDRAMC signal: SDRAMC_D2 on PC2 mux A */ +#define MUX_PC2A_SDRAMC_D2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D2 */ +#define PIO_PC2A_SDRAMC_D2 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D2 */ +#define PIN_PC3A_SDRAMC_D3 _L_(67) /**< SDRAMC signal: SDRAMC_D3 on PC3 mux A */ +#define MUX_PC3A_SDRAMC_D3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D3 */ +#define PIO_PC3A_SDRAMC_D3 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D3 */ +#define PIN_PC4A_SDRAMC_D4 _L_(68) /**< SDRAMC signal: SDRAMC_D4 on PC4 mux A */ +#define MUX_PC4A_SDRAMC_D4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D4 */ +#define PIO_PC4A_SDRAMC_D4 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D4 */ +#define PIN_PC5A_SDRAMC_D5 _L_(69) /**< SDRAMC signal: SDRAMC_D5 on PC5 mux A */ +#define MUX_PC5A_SDRAMC_D5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D5 */ +#define PIO_PC5A_SDRAMC_D5 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D5 */ +#define PIN_PC6A_SDRAMC_D6 _L_(70) /**< SDRAMC signal: SDRAMC_D6 on PC6 mux A */ +#define MUX_PC6A_SDRAMC_D6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D6 */ +#define PIO_PC6A_SDRAMC_D6 (_U_(1) << 6) /**< SDRAMC signal: SDRAMC_D6 */ +#define PIN_PC7A_SDRAMC_D7 _L_(71) /**< SDRAMC signal: SDRAMC_D7 on PC7 mux A */ +#define MUX_PC7A_SDRAMC_D7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D7 */ +#define PIO_PC7A_SDRAMC_D7 (_U_(1) << 7) /**< SDRAMC signal: SDRAMC_D7 */ +#define PIN_PE0A_SDRAMC_D8 _L_(128) /**< SDRAMC signal: SDRAMC_D8 on PE0 mux A */ +#define MUX_PE0A_SDRAMC_D8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D8 */ +#define PIO_PE0A_SDRAMC_D8 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D8 */ +#define PIN_PE1A_SDRAMC_D9 _L_(129) /**< SDRAMC signal: SDRAMC_D9 on PE1 mux A */ +#define MUX_PE1A_SDRAMC_D9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D9 */ +#define PIO_PE1A_SDRAMC_D9 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D9 */ +#define PIN_PE2A_SDRAMC_D10 _L_(130) /**< SDRAMC signal: SDRAMC_D10 on PE2 mux A */ +#define MUX_PE2A_SDRAMC_D10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D10 */ +#define PIO_PE2A_SDRAMC_D10 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D10 */ +#define PIN_PE3A_SDRAMC_D11 _L_(131) /**< SDRAMC signal: SDRAMC_D11 on PE3 mux A */ +#define MUX_PE3A_SDRAMC_D11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D11 */ +#define PIO_PE3A_SDRAMC_D11 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D11 */ +#define PIN_PE4A_SDRAMC_D12 _L_(132) /**< SDRAMC signal: SDRAMC_D12 on PE4 mux A */ +#define MUX_PE4A_SDRAMC_D12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D12 */ +#define PIO_PE4A_SDRAMC_D12 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D12 */ +#define PIN_PE5A_SDRAMC_D13 _L_(133) /**< SDRAMC signal: SDRAMC_D13 on PE5 mux A */ +#define MUX_PE5A_SDRAMC_D13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D13 */ +#define PIO_PE5A_SDRAMC_D13 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D13 */ +#define PIN_PA15A_SDRAMC_D14 _L_(15) /**< SDRAMC signal: SDRAMC_D14 on PA15 mux A */ +#define MUX_PA15A_SDRAMC_D14 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D14 */ +#define PIO_PA15A_SDRAMC_D14 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_D14 */ +#define PIN_PA16A_SDRAMC_D15 _L_(16) /**< SDRAMC signal: SDRAMC_D15 on PA16 mux A */ +#define MUX_PA16A_SDRAMC_D15 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D15 */ +#define PIO_PA16A_SDRAMC_D15 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_D15 */ +#define PIN_PC16A_SDRAMC_NANDALE _L_(80) /**< SDRAMC signal: SDRAMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SDRAMC_NANDALE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDALE */ +#define PIO_PC16A_SDRAMC_NANDALE (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_NANDALE */ +#define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: SDRAMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SDRAMC_NANDCLE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDCLE */ +#define PIO_PC17A_SDRAMC_NANDCLE (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_NANDCLE */ +#define PIN_PC9A_SDRAMC_NANDOE _L_(73) /**< SDRAMC signal: SDRAMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SDRAMC_NANDOE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDOE */ +#define PIO_PC9A_SDRAMC_NANDOE (_U_(1) << 9) /**< SDRAMC signal: SDRAMC_NANDOE */ +#define PIN_PC10A_SDRAMC_NANDWE _L_(74) /**< SDRAMC signal: SDRAMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SDRAMC_NANDWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDWE */ +#define PIO_PC10A_SDRAMC_NANDWE (_U_(1) << 10) /**< SDRAMC signal: SDRAMC_NANDWE */ +#define PIN_PC18A_SDRAMC_NBS0 _L_(82) /**< SDRAMC signal: SDRAMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_NBS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NBS0 */ +#define PIO_PC18A_SDRAMC_NBS0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NBS0 */ +#define PIN_PD15C_SDRAMC_NBS1 _L_(111) /**< SDRAMC signal: SDRAMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NBS1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NBS1 */ +#define PIO_PD15C_SDRAMC_NBS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NBS1 */ +#define PIN_PC14A_SDRAMC_NCS0 _L_(78) /**< SDRAMC signal: SDRAMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SDRAMC_NCS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS0 */ +#define PIO_PC14A_SDRAMC_NCS0 (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_NCS0 */ +#define PIN_PC15A_SDRAMC_NCS1 _L_(79) /**< SDRAMC signal: SDRAMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PC15A_SDRAMC_NCS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PD18A_SDRAMC_NCS1 _L_(114) /**< SDRAMC signal: SDRAMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PD18A_SDRAMC_NCS1 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PA22C_SDRAMC_NCS2 _L_(22) /**< SDRAMC signal: SDRAMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SDRAMC_NCS2 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NCS2 */ +#define PIO_PA22C_SDRAMC_NCS2 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_NCS2 */ +#define PIN_PC12A_SDRAMC_NCS3 _L_(76) /**< SDRAMC signal: SDRAMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PC12A_SDRAMC_NCS3 (_U_(1) << 12) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PD19A_SDRAMC_NCS3 _L_(115) /**< SDRAMC signal: SDRAMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PD19A_SDRAMC_NCS3 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PC11A_SDRAMC_NRD _L_(75) /**< SDRAMC signal: SDRAMC_NRD on PC11 mux A */ +#define MUX_PC11A_SDRAMC_NRD _L_(0) /**< SDRAMC signal line function value: SDRAMC_NRD */ +#define PIO_PC11A_SDRAMC_NRD (_U_(1) << 11) /**< SDRAMC signal: SDRAMC_NRD */ +#define PIN_PC13A_SDRAMC_NWAIT _L_(77) /**< SDRAMC signal: SDRAMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SDRAMC_NWAIT _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWAIT */ +#define PIO_PC13A_SDRAMC_NWAIT (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_NWAIT */ +#define PIN_PC8A_SDRAMC_NWE _L_(72) /**< SDRAMC signal: SDRAMC_NWE on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWE */ +#define PIO_PC8A_SDRAMC_NWE (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWE */ +#define PIN_PC8A_SDRAMC_NWR0 _L_(72) /**< SDRAMC signal: SDRAMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWR0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWR0 */ +#define PIO_PC8A_SDRAMC_NWR0 (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWR0 */ +#define PIN_PD15C_SDRAMC_NWR1 _L_(111) /**< SDRAMC signal: SDRAMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NWR1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NWR1 */ +#define PIO_PD15C_SDRAMC_NWR1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NWR1 */ +#define PIN_PD16C_SDRAMC_RAS _L_(112) /**< SDRAMC signal: SDRAMC_RAS on PD16 mux C */ +#define MUX_PD16C_SDRAMC_RAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_RAS */ +#define PIO_PD16C_SDRAMC_RAS (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_RAS */ +#define PIN_PC13C_SDRAMC_SDA10 _L_(77) /**< SDRAMC signal: SDRAMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PC13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD13C_SDRAMC_SDA10 _L_(109) /**< SDRAMC signal: SDRAMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PD13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD23C_SDRAMC_SDCK _L_(119) /**< SDRAMC signal: SDRAMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SDRAMC_SDCK _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCK */ +#define PIO_PD23C_SDRAMC_SDCK (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_SDCK */ +#define PIN_PD14C_SDRAMC_SDCKE _L_(110) /**< SDRAMC signal: SDRAMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SDRAMC_SDCKE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCKE */ +#define PIO_PD14C_SDRAMC_SDCKE (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_SDCKE */ +#define PIN_PC15A_SDRAMC_SDCS _L_(79) /**< SDRAMC signal: SDRAMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PC15A_SDRAMC_SDCS (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD18A_SDRAMC_SDCS _L_(114) /**< SDRAMC signal: SDRAMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PD18A_SDRAMC_SDCS (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD29C_SDRAMC_SDWE _L_(125) /**< SDRAMC signal: SDRAMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SDRAMC_SDWE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDWE */ +#define PIO_PD29C_SDRAMC_SDWE (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_SDWE */ +/* ========== PIO definition for SMC peripheral ========== */ +#define PIN_PC18A_SMC_A0 _L_(82) /**< SMC signal: SMC_A0 on PC18 mux A */ +#define MUX_PC18A_SMC_A0 _L_(0) /**< SMC signal line function value: SMC_A0 */ +#define PIO_PC18A_SMC_A0 (_U_(1) << 18) /**< SMC signal: SMC_A0 */ +#define PIN_PC19A_SMC_A1 _L_(83) /**< SMC signal: SMC_A1 on PC19 mux A */ +#define MUX_PC19A_SMC_A1 _L_(0) /**< SMC signal line function value: SMC_A1 */ +#define PIO_PC19A_SMC_A1 (_U_(1) << 19) /**< SMC signal: SMC_A1 */ +#define PIN_PC20A_SMC_A2 _L_(84) /**< SMC signal: SMC_A2 on PC20 mux A */ +#define MUX_PC20A_SMC_A2 _L_(0) /**< SMC signal line function value: SMC_A2 */ +#define PIO_PC20A_SMC_A2 (_U_(1) << 20) /**< SMC signal: SMC_A2 */ +#define PIN_PC21A_SMC_A3 _L_(85) /**< SMC signal: SMC_A3 on PC21 mux A */ +#define MUX_PC21A_SMC_A3 _L_(0) /**< SMC signal line function value: SMC_A3 */ +#define PIO_PC21A_SMC_A3 (_U_(1) << 21) /**< SMC signal: SMC_A3 */ +#define PIN_PC22A_SMC_A4 _L_(86) /**< SMC signal: SMC_A4 on PC22 mux A */ +#define MUX_PC22A_SMC_A4 _L_(0) /**< SMC signal line function value: SMC_A4 */ +#define PIO_PC22A_SMC_A4 (_U_(1) << 22) /**< SMC signal: SMC_A4 */ +#define PIN_PC23A_SMC_A5 _L_(87) /**< SMC signal: SMC_A5 on PC23 mux A */ +#define MUX_PC23A_SMC_A5 _L_(0) /**< SMC signal line function value: SMC_A5 */ +#define PIO_PC23A_SMC_A5 (_U_(1) << 23) /**< SMC signal: SMC_A5 */ +#define PIN_PC24A_SMC_A6 _L_(88) /**< SMC signal: SMC_A6 on PC24 mux A */ +#define MUX_PC24A_SMC_A6 _L_(0) /**< SMC signal line function value: SMC_A6 */ +#define PIO_PC24A_SMC_A6 (_U_(1) << 24) /**< SMC signal: SMC_A6 */ +#define PIN_PC25A_SMC_A7 _L_(89) /**< SMC signal: SMC_A7 on PC25 mux A */ +#define MUX_PC25A_SMC_A7 _L_(0) /**< SMC signal line function value: SMC_A7 */ +#define PIO_PC25A_SMC_A7 (_U_(1) << 25) /**< SMC signal: SMC_A7 */ +#define PIN_PC26A_SMC_A8 _L_(90) /**< SMC signal: SMC_A8 on PC26 mux A */ +#define MUX_PC26A_SMC_A8 _L_(0) /**< SMC signal line function value: SMC_A8 */ +#define PIO_PC26A_SMC_A8 (_U_(1) << 26) /**< SMC signal: SMC_A8 */ +#define PIN_PC27A_SMC_A9 _L_(91) /**< SMC signal: SMC_A9 on PC27 mux A */ +#define MUX_PC27A_SMC_A9 _L_(0) /**< SMC signal line function value: SMC_A9 */ +#define PIO_PC27A_SMC_A9 (_U_(1) << 27) /**< SMC signal: SMC_A9 */ +#define PIN_PC28A_SMC_A10 _L_(92) /**< SMC signal: SMC_A10 on PC28 mux A */ +#define MUX_PC28A_SMC_A10 _L_(0) /**< SMC signal line function value: SMC_A10 */ +#define PIO_PC28A_SMC_A10 (_U_(1) << 28) /**< SMC signal: SMC_A10 */ +#define PIN_PC29A_SMC_A11 _L_(93) /**< SMC signal: SMC_A11 on PC29 mux A */ +#define MUX_PC29A_SMC_A11 _L_(0) /**< SMC signal line function value: SMC_A11 */ +#define PIO_PC29A_SMC_A11 (_U_(1) << 29) /**< SMC signal: SMC_A11 */ +#define PIN_PC30A_SMC_A12 _L_(94) /**< SMC signal: SMC_A12 on PC30 mux A */ +#define MUX_PC30A_SMC_A12 _L_(0) /**< SMC signal line function value: SMC_A12 */ +#define PIO_PC30A_SMC_A12 (_U_(1) << 30) /**< SMC signal: SMC_A12 */ +#define PIN_PC31A_SMC_A13 _L_(95) /**< SMC signal: SMC_A13 on PC31 mux A */ +#define MUX_PC31A_SMC_A13 _L_(0) /**< SMC signal line function value: SMC_A13 */ +#define PIO_PC31A_SMC_A13 (_U_(1) << 31) /**< SMC signal: SMC_A13 */ +#define PIN_PA18C_SMC_A14 _L_(18) /**< SMC signal: SMC_A14 on PA18 mux C */ +#define MUX_PA18C_SMC_A14 _L_(2) /**< SMC signal line function value: SMC_A14 */ +#define PIO_PA18C_SMC_A14 (_U_(1) << 18) /**< SMC signal: SMC_A14 */ +#define PIN_PA19C_SMC_A15 _L_(19) /**< SMC signal: SMC_A15 on PA19 mux C */ +#define MUX_PA19C_SMC_A15 _L_(2) /**< SMC signal line function value: SMC_A15 */ +#define PIO_PA19C_SMC_A15 (_U_(1) << 19) /**< SMC signal: SMC_A15 */ +#define PIN_PA20C_SMC_A16 _L_(20) /**< SMC signal: SMC_A16 on PA20 mux C */ +#define MUX_PA20C_SMC_A16 _L_(2) /**< SMC signal line function value: SMC_A16 */ +#define PIO_PA20C_SMC_A16 (_U_(1) << 20) /**< SMC signal: SMC_A16 */ +#define PIN_PA0C_SMC_A17 _L_(0) /**< SMC signal: SMC_A17 on PA0 mux C */ +#define MUX_PA0C_SMC_A17 _L_(2) /**< SMC signal line function value: SMC_A17 */ +#define PIO_PA0C_SMC_A17 (_U_(1) << 0) /**< SMC signal: SMC_A17 */ +#define PIN_PA1C_SMC_A18 _L_(1) /**< SMC signal: SMC_A18 on PA1 mux C */ +#define MUX_PA1C_SMC_A18 _L_(2) /**< SMC signal line function value: SMC_A18 */ +#define PIO_PA1C_SMC_A18 (_U_(1) << 1) /**< SMC signal: SMC_A18 */ +#define PIN_PA23C_SMC_A19 _L_(23) /**< SMC signal: SMC_A19 on PA23 mux C */ +#define MUX_PA23C_SMC_A19 _L_(2) /**< SMC signal line function value: SMC_A19 */ +#define PIO_PA23C_SMC_A19 (_U_(1) << 23) /**< SMC signal: SMC_A19 */ +#define PIN_PA24C_SMC_A20 _L_(24) /**< SMC signal: SMC_A20 on PA24 mux C */ +#define MUX_PA24C_SMC_A20 _L_(2) /**< SMC signal line function value: SMC_A20 */ +#define PIO_PA24C_SMC_A20 (_U_(1) << 24) /**< SMC signal: SMC_A20 */ +#define PIN_PC16A_SMC_A21 _L_(80) /**< SMC signal: SMC_A21 on PC16 mux A */ +#define MUX_PC16A_SMC_A21 _L_(0) /**< SMC signal line function value: SMC_A21 */ +#define PIO_PC16A_SMC_A21 (_U_(1) << 16) /**< SMC signal: SMC_A21 */ +#define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: SMC_A22 on PC17 mux A */ +#define MUX_PC17A_SMC_A22 _L_(0) /**< SMC signal line function value: SMC_A22 */ +#define PIO_PC17A_SMC_A22 (_U_(1) << 17) /**< SMC signal: SMC_A22 */ +#define PIN_PA25C_SMC_A23 _L_(25) /**< SMC signal: SMC_A23 on PA25 mux C */ +#define MUX_PA25C_SMC_A23 _L_(2) /**< SMC signal line function value: SMC_A23 */ +#define PIO_PA25C_SMC_A23 (_U_(1) << 25) /**< SMC signal: SMC_A23 */ +#define PIN_PA20C_SMC_BA0 _L_(20) /**< SMC signal: SMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SMC_BA0 _L_(2) /**< SMC signal line function value: SMC_BA0 */ +#define PIO_PA20C_SMC_BA0 (_U_(1) << 20) /**< SMC signal: SMC_BA0 */ +#define PIN_PA0C_SMC_BA1 _L_(0) /**< SMC signal: SMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SMC_BA1 _L_(2) /**< SMC signal line function value: SMC_BA1 */ +#define PIO_PA0C_SMC_BA1 (_U_(1) << 0) /**< SMC signal: SMC_BA1 */ +#define PIN_PD17C_SMC_CAS _L_(113) /**< SMC signal: SMC_CAS on PD17 mux C */ +#define MUX_PD17C_SMC_CAS _L_(2) /**< SMC signal line function value: SMC_CAS */ +#define PIO_PD17C_SMC_CAS (_U_(1) << 17) /**< SMC signal: SMC_CAS */ +#define PIN_PC0A_SMC_D0 _L_(64) /**< SMC signal: SMC_D0 on PC0 mux A */ +#define MUX_PC0A_SMC_D0 _L_(0) /**< SMC signal line function value: SMC_D0 */ +#define PIO_PC0A_SMC_D0 (_U_(1) << 0) /**< SMC signal: SMC_D0 */ +#define PIN_PC1A_SMC_D1 _L_(65) /**< SMC signal: SMC_D1 on PC1 mux A */ +#define MUX_PC1A_SMC_D1 _L_(0) /**< SMC signal line function value: SMC_D1 */ +#define PIO_PC1A_SMC_D1 (_U_(1) << 1) /**< SMC signal: SMC_D1 */ +#define PIN_PC2A_SMC_D2 _L_(66) /**< SMC signal: SMC_D2 on PC2 mux A */ +#define MUX_PC2A_SMC_D2 _L_(0) /**< SMC signal line function value: SMC_D2 */ +#define PIO_PC2A_SMC_D2 (_U_(1) << 2) /**< SMC signal: SMC_D2 */ +#define PIN_PC3A_SMC_D3 _L_(67) /**< SMC signal: SMC_D3 on PC3 mux A */ +#define MUX_PC3A_SMC_D3 _L_(0) /**< SMC signal line function value: SMC_D3 */ +#define PIO_PC3A_SMC_D3 (_U_(1) << 3) /**< SMC signal: SMC_D3 */ +#define PIN_PC4A_SMC_D4 _L_(68) /**< SMC signal: SMC_D4 on PC4 mux A */ +#define MUX_PC4A_SMC_D4 _L_(0) /**< SMC signal line function value: SMC_D4 */ +#define PIO_PC4A_SMC_D4 (_U_(1) << 4) /**< SMC signal: SMC_D4 */ +#define PIN_PC5A_SMC_D5 _L_(69) /**< SMC signal: SMC_D5 on PC5 mux A */ +#define MUX_PC5A_SMC_D5 _L_(0) /**< SMC signal line function value: SMC_D5 */ +#define PIO_PC5A_SMC_D5 (_U_(1) << 5) /**< SMC signal: SMC_D5 */ +#define PIN_PC6A_SMC_D6 _L_(70) /**< SMC signal: SMC_D6 on PC6 mux A */ +#define MUX_PC6A_SMC_D6 _L_(0) /**< SMC signal line function value: SMC_D6 */ +#define PIO_PC6A_SMC_D6 (_U_(1) << 6) /**< SMC signal: SMC_D6 */ +#define PIN_PC7A_SMC_D7 _L_(71) /**< SMC signal: SMC_D7 on PC7 mux A */ +#define MUX_PC7A_SMC_D7 _L_(0) /**< SMC signal line function value: SMC_D7 */ +#define PIO_PC7A_SMC_D7 (_U_(1) << 7) /**< SMC signal: SMC_D7 */ +#define PIN_PE0A_SMC_D8 _L_(128) /**< SMC signal: SMC_D8 on PE0 mux A */ +#define MUX_PE0A_SMC_D8 _L_(0) /**< SMC signal line function value: SMC_D8 */ +#define PIO_PE0A_SMC_D8 (_U_(1) << 0) /**< SMC signal: SMC_D8 */ +#define PIN_PE1A_SMC_D9 _L_(129) /**< SMC signal: SMC_D9 on PE1 mux A */ +#define MUX_PE1A_SMC_D9 _L_(0) /**< SMC signal line function value: SMC_D9 */ +#define PIO_PE1A_SMC_D9 (_U_(1) << 1) /**< SMC signal: SMC_D9 */ +#define PIN_PE2A_SMC_D10 _L_(130) /**< SMC signal: SMC_D10 on PE2 mux A */ +#define MUX_PE2A_SMC_D10 _L_(0) /**< SMC signal line function value: SMC_D10 */ +#define PIO_PE2A_SMC_D10 (_U_(1) << 2) /**< SMC signal: SMC_D10 */ +#define PIN_PE3A_SMC_D11 _L_(131) /**< SMC signal: SMC_D11 on PE3 mux A */ +#define MUX_PE3A_SMC_D11 _L_(0) /**< SMC signal line function value: SMC_D11 */ +#define PIO_PE3A_SMC_D11 (_U_(1) << 3) /**< SMC signal: SMC_D11 */ +#define PIN_PE4A_SMC_D12 _L_(132) /**< SMC signal: SMC_D12 on PE4 mux A */ +#define MUX_PE4A_SMC_D12 _L_(0) /**< SMC signal line function value: SMC_D12 */ +#define PIO_PE4A_SMC_D12 (_U_(1) << 4) /**< SMC signal: SMC_D12 */ +#define PIN_PE5A_SMC_D13 _L_(133) /**< SMC signal: SMC_D13 on PE5 mux A */ +#define MUX_PE5A_SMC_D13 _L_(0) /**< SMC signal line function value: SMC_D13 */ +#define PIO_PE5A_SMC_D13 (_U_(1) << 5) /**< SMC signal: SMC_D13 */ +#define PIN_PA15A_SMC_D14 _L_(15) /**< SMC signal: SMC_D14 on PA15 mux A */ +#define MUX_PA15A_SMC_D14 _L_(0) /**< SMC signal line function value: SMC_D14 */ +#define PIO_PA15A_SMC_D14 (_U_(1) << 15) /**< SMC signal: SMC_D14 */ +#define PIN_PA16A_SMC_D15 _L_(16) /**< SMC signal: SMC_D15 on PA16 mux A */ +#define MUX_PA16A_SMC_D15 _L_(0) /**< SMC signal line function value: SMC_D15 */ +#define PIO_PA16A_SMC_D15 (_U_(1) << 16) /**< SMC signal: SMC_D15 */ +#define PIN_PC16A_SMC_NANDALE _L_(80) /**< SMC signal: SMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SMC_NANDALE _L_(0) /**< SMC signal line function value: SMC_NANDALE */ +#define PIO_PC16A_SMC_NANDALE (_U_(1) << 16) /**< SMC signal: SMC_NANDALE */ +#define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: SMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SMC_NANDCLE _L_(0) /**< SMC signal line function value: SMC_NANDCLE */ +#define PIO_PC17A_SMC_NANDCLE (_U_(1) << 17) /**< SMC signal: SMC_NANDCLE */ +#define PIN_PC9A_SMC_NANDOE _L_(73) /**< SMC signal: SMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SMC_NANDOE _L_(0) /**< SMC signal line function value: SMC_NANDOE */ +#define PIO_PC9A_SMC_NANDOE (_U_(1) << 9) /**< SMC signal: SMC_NANDOE */ +#define PIN_PC10A_SMC_NANDWE _L_(74) /**< SMC signal: SMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SMC_NANDWE _L_(0) /**< SMC signal line function value: SMC_NANDWE */ +#define PIO_PC10A_SMC_NANDWE (_U_(1) << 10) /**< SMC signal: SMC_NANDWE */ +#define PIN_PC18A_SMC_NBS0 _L_(82) /**< SMC signal: SMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SMC_NBS0 _L_(0) /**< SMC signal line function value: SMC_NBS0 */ +#define PIO_PC18A_SMC_NBS0 (_U_(1) << 18) /**< SMC signal: SMC_NBS0 */ +#define PIN_PD15C_SMC_NBS1 _L_(111) /**< SMC signal: SMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SMC_NBS1 _L_(2) /**< SMC signal line function value: SMC_NBS1 */ +#define PIO_PD15C_SMC_NBS1 (_U_(1) << 15) /**< SMC signal: SMC_NBS1 */ +#define PIN_PC14A_SMC_NCS0 _L_(78) /**< SMC signal: SMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SMC_NCS0 _L_(0) /**< SMC signal line function value: SMC_NCS0 */ +#define PIO_PC14A_SMC_NCS0 (_U_(1) << 14) /**< SMC signal: SMC_NCS0 */ +#define PIN_PC15A_SMC_NCS1 _L_(79) /**< SMC signal: SMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PC15A_SMC_NCS1 (_U_(1) << 15) /**< SMC signal: SMC_NCS1 */ +#define PIN_PD18A_SMC_NCS1 _L_(114) /**< SMC signal: SMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PD18A_SMC_NCS1 (_U_(1) << 18) /**< SMC signal: SMC_NCS1 */ +#define PIN_PA22C_SMC_NCS2 _L_(22) /**< SMC signal: SMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SMC_NCS2 _L_(2) /**< SMC signal line function value: SMC_NCS2 */ +#define PIO_PA22C_SMC_NCS2 (_U_(1) << 22) /**< SMC signal: SMC_NCS2 */ +#define PIN_PC12A_SMC_NCS3 _L_(76) /**< SMC signal: SMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PC12A_SMC_NCS3 (_U_(1) << 12) /**< SMC signal: SMC_NCS3 */ +#define PIN_PD19A_SMC_NCS3 _L_(115) /**< SMC signal: SMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PD19A_SMC_NCS3 (_U_(1) << 19) /**< SMC signal: SMC_NCS3 */ +#define PIN_PC11A_SMC_NRD _L_(75) /**< SMC signal: SMC_NRD on PC11 mux A */ +#define MUX_PC11A_SMC_NRD _L_(0) /**< SMC signal line function value: SMC_NRD */ +#define PIO_PC11A_SMC_NRD (_U_(1) << 11) /**< SMC signal: SMC_NRD */ +#define PIN_PC13A_SMC_NWAIT _L_(77) /**< SMC signal: SMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SMC_NWAIT _L_(0) /**< SMC signal line function value: SMC_NWAIT */ +#define PIO_PC13A_SMC_NWAIT (_U_(1) << 13) /**< SMC signal: SMC_NWAIT */ +#define PIN_PC8A_SMC_NWE _L_(72) /**< SMC signal: SMC_NWE on PC8 mux A */ +#define MUX_PC8A_SMC_NWE _L_(0) /**< SMC signal line function value: SMC_NWE */ +#define PIO_PC8A_SMC_NWE (_U_(1) << 8) /**< SMC signal: SMC_NWE */ +#define PIN_PC8A_SMC_NWR0 _L_(72) /**< SMC signal: SMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SMC_NWR0 _L_(0) /**< SMC signal line function value: SMC_NWR0 */ +#define PIO_PC8A_SMC_NWR0 (_U_(1) << 8) /**< SMC signal: SMC_NWR0 */ +#define PIN_PD15C_SMC_NWR1 _L_(111) /**< SMC signal: SMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SMC_NWR1 _L_(2) /**< SMC signal line function value: SMC_NWR1 */ +#define PIO_PD15C_SMC_NWR1 (_U_(1) << 15) /**< SMC signal: SMC_NWR1 */ +#define PIN_PD16C_SMC_RAS _L_(112) /**< SMC signal: SMC_RAS on PD16 mux C */ +#define MUX_PD16C_SMC_RAS _L_(2) /**< SMC signal line function value: SMC_RAS */ +#define PIO_PD16C_SMC_RAS (_U_(1) << 16) /**< SMC signal: SMC_RAS */ +#define PIN_PC13C_SMC_SDA10 _L_(77) /**< SMC signal: SMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PC13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD13C_SMC_SDA10 _L_(109) /**< SMC signal: SMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PD13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD23C_SMC_SDCK _L_(119) /**< SMC signal: SMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SMC_SDCK _L_(2) /**< SMC signal line function value: SMC_SDCK */ +#define PIO_PD23C_SMC_SDCK (_U_(1) << 23) /**< SMC signal: SMC_SDCK */ +#define PIN_PD14C_SMC_SDCKE _L_(110) /**< SMC signal: SMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SMC_SDCKE _L_(2) /**< SMC signal line function value: SMC_SDCKE */ +#define PIO_PD14C_SMC_SDCKE (_U_(1) << 14) /**< SMC signal: SMC_SDCKE */ +#define PIN_PC15A_SMC_SDCS _L_(79) /**< SMC signal: SMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PC15A_SMC_SDCS (_U_(1) << 15) /**< SMC signal: SMC_SDCS */ +#define PIN_PD18A_SMC_SDCS _L_(114) /**< SMC signal: SMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PD18A_SMC_SDCS (_U_(1) << 18) /**< SMC signal: SMC_SDCS */ +#define PIN_PD29C_SMC_SDWE _L_(125) /**< SMC signal: SMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SMC_SDWE _L_(2) /**< SMC signal line function value: SMC_SDWE */ +#define PIO_PD29C_SMC_SDWE (_U_(1) << 29) /**< SMC signal: SMC_SDWE */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ + +#endif /* _SAME70Q20_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q21.h b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q21.h new file mode 100644 index 00000000..7f745cb6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/pio/same70q21.h @@ -0,0 +1,1712 @@ +/** + * \brief Peripheral I/O description for SAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70Q21_GPIO_H_ +#define _SAME70Q21_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +#define PIN_PA21X1_AFEC0_PIODCEN2 _L_(21) /**< AFEC0 signal: AFEC0_PIODCEN2 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_PIODCEN2 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_PIODCEN2 */ +#define PIN_PB0X1_AFEC0_RTCOUT0 _L_(32) /**< AFEC0 signal: AFEC0_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_RTCOUT0 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_RTCOUT0 */ +#define PIN_PA19X1_AFEC0_WKUP9 _L_(19) /**< AFEC0 signal: AFEC0_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_WKUP9 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_WKUP9 */ +#define PIN_PA20X1_AFEC0_WKUP10 _L_(20) /**< AFEC0 signal: AFEC0_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_WKUP10 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_WKUP10 */ +#define PIN_PB3X1_AFEC0_WKUP12 _L_(35) /**< AFEC0 signal: AFEC0_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_WKUP12 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_WKUP12 */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +#define PIN_PB1X1_AFEC1_RTCOUT1 _L_(33) /**< AFEC1 signal: AFEC1_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_RTCOUT1 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_RTCOUT1 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for SDRAMC peripheral ========== */ +#define PIN_PC18A_SDRAMC_A0 _L_(82) /**< SDRAMC signal: SDRAMC_A0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_A0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A0 */ +#define PIO_PC18A_SDRAMC_A0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A0 */ +#define PIN_PC19A_SDRAMC_A1 _L_(83) /**< SDRAMC signal: SDRAMC_A1 on PC19 mux A */ +#define MUX_PC19A_SDRAMC_A1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A1 */ +#define PIO_PC19A_SDRAMC_A1 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A1 */ +#define PIN_PC20A_SDRAMC_A2 _L_(84) /**< SDRAMC signal: SDRAMC_A2 on PC20 mux A */ +#define MUX_PC20A_SDRAMC_A2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A2 */ +#define PIO_PC20A_SDRAMC_A2 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A2 */ +#define PIN_PC21A_SDRAMC_A3 _L_(85) /**< SDRAMC signal: SDRAMC_A3 on PC21 mux A */ +#define MUX_PC21A_SDRAMC_A3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A3 */ +#define PIO_PC21A_SDRAMC_A3 (_U_(1) << 21) /**< SDRAMC signal: SDRAMC_A3 */ +#define PIN_PC22A_SDRAMC_A4 _L_(86) /**< SDRAMC signal: SDRAMC_A4 on PC22 mux A */ +#define MUX_PC22A_SDRAMC_A4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A4 */ +#define PIO_PC22A_SDRAMC_A4 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_A4 */ +#define PIN_PC23A_SDRAMC_A5 _L_(87) /**< SDRAMC signal: SDRAMC_A5 on PC23 mux A */ +#define MUX_PC23A_SDRAMC_A5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A5 */ +#define PIO_PC23A_SDRAMC_A5 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A5 */ +#define PIN_PC24A_SDRAMC_A6 _L_(88) /**< SDRAMC signal: SDRAMC_A6 on PC24 mux A */ +#define MUX_PC24A_SDRAMC_A6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A6 */ +#define PIO_PC24A_SDRAMC_A6 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A6 */ +#define PIN_PC25A_SDRAMC_A7 _L_(89) /**< SDRAMC signal: SDRAMC_A7 on PC25 mux A */ +#define MUX_PC25A_SDRAMC_A7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A7 */ +#define PIO_PC25A_SDRAMC_A7 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A7 */ +#define PIN_PC26A_SDRAMC_A8 _L_(90) /**< SDRAMC signal: SDRAMC_A8 on PC26 mux A */ +#define MUX_PC26A_SDRAMC_A8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A8 */ +#define PIO_PC26A_SDRAMC_A8 (_U_(1) << 26) /**< SDRAMC signal: SDRAMC_A8 */ +#define PIN_PC27A_SDRAMC_A9 _L_(91) /**< SDRAMC signal: SDRAMC_A9 on PC27 mux A */ +#define MUX_PC27A_SDRAMC_A9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A9 */ +#define PIO_PC27A_SDRAMC_A9 (_U_(1) << 27) /**< SDRAMC signal: SDRAMC_A9 */ +#define PIN_PC28A_SDRAMC_A10 _L_(92) /**< SDRAMC signal: SDRAMC_A10 on PC28 mux A */ +#define MUX_PC28A_SDRAMC_A10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A10 */ +#define PIO_PC28A_SDRAMC_A10 (_U_(1) << 28) /**< SDRAMC signal: SDRAMC_A10 */ +#define PIN_PC29A_SDRAMC_A11 _L_(93) /**< SDRAMC signal: SDRAMC_A11 on PC29 mux A */ +#define MUX_PC29A_SDRAMC_A11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A11 */ +#define PIO_PC29A_SDRAMC_A11 (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_A11 */ +#define PIN_PC30A_SDRAMC_A12 _L_(94) /**< SDRAMC signal: SDRAMC_A12 on PC30 mux A */ +#define MUX_PC30A_SDRAMC_A12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A12 */ +#define PIO_PC30A_SDRAMC_A12 (_U_(1) << 30) /**< SDRAMC signal: SDRAMC_A12 */ +#define PIN_PC31A_SDRAMC_A13 _L_(95) /**< SDRAMC signal: SDRAMC_A13 on PC31 mux A */ +#define MUX_PC31A_SDRAMC_A13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A13 */ +#define PIO_PC31A_SDRAMC_A13 (_U_(1) << 31) /**< SDRAMC signal: SDRAMC_A13 */ +#define PIN_PA18C_SDRAMC_A14 _L_(18) /**< SDRAMC signal: SDRAMC_A14 on PA18 mux C */ +#define MUX_PA18C_SDRAMC_A14 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A14 */ +#define PIO_PA18C_SDRAMC_A14 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_A14 */ +#define PIN_PA19C_SDRAMC_A15 _L_(19) /**< SDRAMC signal: SDRAMC_A15 on PA19 mux C */ +#define MUX_PA19C_SDRAMC_A15 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A15 */ +#define PIO_PA19C_SDRAMC_A15 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_A15 */ +#define PIN_PA20C_SDRAMC_A16 _L_(20) /**< SDRAMC signal: SDRAMC_A16 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_A16 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A16 */ +#define PIO_PA20C_SDRAMC_A16 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_A16 */ +#define PIN_PA0C_SDRAMC_A17 _L_(0) /**< SDRAMC signal: SDRAMC_A17 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_A17 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A17 */ +#define PIO_PA0C_SDRAMC_A17 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_A17 */ +#define PIN_PA1C_SDRAMC_A18 _L_(1) /**< SDRAMC signal: SDRAMC_A18 on PA1 mux C */ +#define MUX_PA1C_SDRAMC_A18 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A18 */ +#define PIO_PA1C_SDRAMC_A18 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_A18 */ +#define PIN_PA23C_SDRAMC_A19 _L_(23) /**< SDRAMC signal: SDRAMC_A19 on PA23 mux C */ +#define MUX_PA23C_SDRAMC_A19 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A19 */ +#define PIO_PA23C_SDRAMC_A19 (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_A19 */ +#define PIN_PA24C_SDRAMC_A20 _L_(24) /**< SDRAMC signal: SDRAMC_A20 on PA24 mux C */ +#define MUX_PA24C_SDRAMC_A20 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A20 */ +#define PIO_PA24C_SDRAMC_A20 (_U_(1) << 24) /**< SDRAMC signal: SDRAMC_A20 */ +#define PIN_PC16A_SDRAMC_A21 _L_(80) /**< SDRAMC signal: SDRAMC_A21 on PC16 mux A */ +#define MUX_PC16A_SDRAMC_A21 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A21 */ +#define PIO_PC16A_SDRAMC_A21 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_A21 */ +#define PIN_PC17A_SDRAMC_A22 _L_(81) /**< SDRAMC signal: SDRAMC_A22 on PC17 mux A */ +#define MUX_PC17A_SDRAMC_A22 _L_(0) /**< SDRAMC signal line function value: SDRAMC_A22 */ +#define PIO_PC17A_SDRAMC_A22 (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_A22 */ +#define PIN_PA25C_SDRAMC_A23 _L_(25) /**< SDRAMC signal: SDRAMC_A23 on PA25 mux C */ +#define MUX_PA25C_SDRAMC_A23 _L_(2) /**< SDRAMC signal line function value: SDRAMC_A23 */ +#define PIO_PA25C_SDRAMC_A23 (_U_(1) << 25) /**< SDRAMC signal: SDRAMC_A23 */ +#define PIN_PA20C_SDRAMC_BA0 _L_(20) /**< SDRAMC signal: SDRAMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SDRAMC_BA0 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA0 */ +#define PIO_PA20C_SDRAMC_BA0 (_U_(1) << 20) /**< SDRAMC signal: SDRAMC_BA0 */ +#define PIN_PA0C_SDRAMC_BA1 _L_(0) /**< SDRAMC signal: SDRAMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SDRAMC_BA1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_BA1 */ +#define PIO_PA0C_SDRAMC_BA1 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_BA1 */ +#define PIN_PD17C_SDRAMC_CAS _L_(113) /**< SDRAMC signal: SDRAMC_CAS on PD17 mux C */ +#define MUX_PD17C_SDRAMC_CAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_CAS */ +#define PIO_PD17C_SDRAMC_CAS (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_CAS */ +#define PIN_PC0A_SDRAMC_D0 _L_(64) /**< SDRAMC signal: SDRAMC_D0 on PC0 mux A */ +#define MUX_PC0A_SDRAMC_D0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D0 */ +#define PIO_PC0A_SDRAMC_D0 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D0 */ +#define PIN_PC1A_SDRAMC_D1 _L_(65) /**< SDRAMC signal: SDRAMC_D1 on PC1 mux A */ +#define MUX_PC1A_SDRAMC_D1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D1 */ +#define PIO_PC1A_SDRAMC_D1 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D1 */ +#define PIN_PC2A_SDRAMC_D2 _L_(66) /**< SDRAMC signal: SDRAMC_D2 on PC2 mux A */ +#define MUX_PC2A_SDRAMC_D2 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D2 */ +#define PIO_PC2A_SDRAMC_D2 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D2 */ +#define PIN_PC3A_SDRAMC_D3 _L_(67) /**< SDRAMC signal: SDRAMC_D3 on PC3 mux A */ +#define MUX_PC3A_SDRAMC_D3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D3 */ +#define PIO_PC3A_SDRAMC_D3 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D3 */ +#define PIN_PC4A_SDRAMC_D4 _L_(68) /**< SDRAMC signal: SDRAMC_D4 on PC4 mux A */ +#define MUX_PC4A_SDRAMC_D4 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D4 */ +#define PIO_PC4A_SDRAMC_D4 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D4 */ +#define PIN_PC5A_SDRAMC_D5 _L_(69) /**< SDRAMC signal: SDRAMC_D5 on PC5 mux A */ +#define MUX_PC5A_SDRAMC_D5 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D5 */ +#define PIO_PC5A_SDRAMC_D5 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D5 */ +#define PIN_PC6A_SDRAMC_D6 _L_(70) /**< SDRAMC signal: SDRAMC_D6 on PC6 mux A */ +#define MUX_PC6A_SDRAMC_D6 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D6 */ +#define PIO_PC6A_SDRAMC_D6 (_U_(1) << 6) /**< SDRAMC signal: SDRAMC_D6 */ +#define PIN_PC7A_SDRAMC_D7 _L_(71) /**< SDRAMC signal: SDRAMC_D7 on PC7 mux A */ +#define MUX_PC7A_SDRAMC_D7 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D7 */ +#define PIO_PC7A_SDRAMC_D7 (_U_(1) << 7) /**< SDRAMC signal: SDRAMC_D7 */ +#define PIN_PE0A_SDRAMC_D8 _L_(128) /**< SDRAMC signal: SDRAMC_D8 on PE0 mux A */ +#define MUX_PE0A_SDRAMC_D8 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D8 */ +#define PIO_PE0A_SDRAMC_D8 (_U_(1) << 0) /**< SDRAMC signal: SDRAMC_D8 */ +#define PIN_PE1A_SDRAMC_D9 _L_(129) /**< SDRAMC signal: SDRAMC_D9 on PE1 mux A */ +#define MUX_PE1A_SDRAMC_D9 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D9 */ +#define PIO_PE1A_SDRAMC_D9 (_U_(1) << 1) /**< SDRAMC signal: SDRAMC_D9 */ +#define PIN_PE2A_SDRAMC_D10 _L_(130) /**< SDRAMC signal: SDRAMC_D10 on PE2 mux A */ +#define MUX_PE2A_SDRAMC_D10 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D10 */ +#define PIO_PE2A_SDRAMC_D10 (_U_(1) << 2) /**< SDRAMC signal: SDRAMC_D10 */ +#define PIN_PE3A_SDRAMC_D11 _L_(131) /**< SDRAMC signal: SDRAMC_D11 on PE3 mux A */ +#define MUX_PE3A_SDRAMC_D11 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D11 */ +#define PIO_PE3A_SDRAMC_D11 (_U_(1) << 3) /**< SDRAMC signal: SDRAMC_D11 */ +#define PIN_PE4A_SDRAMC_D12 _L_(132) /**< SDRAMC signal: SDRAMC_D12 on PE4 mux A */ +#define MUX_PE4A_SDRAMC_D12 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D12 */ +#define PIO_PE4A_SDRAMC_D12 (_U_(1) << 4) /**< SDRAMC signal: SDRAMC_D12 */ +#define PIN_PE5A_SDRAMC_D13 _L_(133) /**< SDRAMC signal: SDRAMC_D13 on PE5 mux A */ +#define MUX_PE5A_SDRAMC_D13 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D13 */ +#define PIO_PE5A_SDRAMC_D13 (_U_(1) << 5) /**< SDRAMC signal: SDRAMC_D13 */ +#define PIN_PA15A_SDRAMC_D14 _L_(15) /**< SDRAMC signal: SDRAMC_D14 on PA15 mux A */ +#define MUX_PA15A_SDRAMC_D14 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D14 */ +#define PIO_PA15A_SDRAMC_D14 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_D14 */ +#define PIN_PA16A_SDRAMC_D15 _L_(16) /**< SDRAMC signal: SDRAMC_D15 on PA16 mux A */ +#define MUX_PA16A_SDRAMC_D15 _L_(0) /**< SDRAMC signal line function value: SDRAMC_D15 */ +#define PIO_PA16A_SDRAMC_D15 (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_D15 */ +#define PIN_PC16A_SDRAMC_NANDALE _L_(80) /**< SDRAMC signal: SDRAMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SDRAMC_NANDALE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDALE */ +#define PIO_PC16A_SDRAMC_NANDALE (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_NANDALE */ +#define PIN_PC17A_SDRAMC_NANDCLE _L_(81) /**< SDRAMC signal: SDRAMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SDRAMC_NANDCLE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDCLE */ +#define PIO_PC17A_SDRAMC_NANDCLE (_U_(1) << 17) /**< SDRAMC signal: SDRAMC_NANDCLE */ +#define PIN_PC9A_SDRAMC_NANDOE _L_(73) /**< SDRAMC signal: SDRAMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SDRAMC_NANDOE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDOE */ +#define PIO_PC9A_SDRAMC_NANDOE (_U_(1) << 9) /**< SDRAMC signal: SDRAMC_NANDOE */ +#define PIN_PC10A_SDRAMC_NANDWE _L_(74) /**< SDRAMC signal: SDRAMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SDRAMC_NANDWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NANDWE */ +#define PIO_PC10A_SDRAMC_NANDWE (_U_(1) << 10) /**< SDRAMC signal: SDRAMC_NANDWE */ +#define PIN_PC18A_SDRAMC_NBS0 _L_(82) /**< SDRAMC signal: SDRAMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SDRAMC_NBS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NBS0 */ +#define PIO_PC18A_SDRAMC_NBS0 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NBS0 */ +#define PIN_PD15C_SDRAMC_NBS1 _L_(111) /**< SDRAMC signal: SDRAMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NBS1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NBS1 */ +#define PIO_PD15C_SDRAMC_NBS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NBS1 */ +#define PIN_PC14A_SDRAMC_NCS0 _L_(78) /**< SDRAMC signal: SDRAMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SDRAMC_NCS0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS0 */ +#define PIO_PC14A_SDRAMC_NCS0 (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_NCS0 */ +#define PIN_PC15A_SDRAMC_NCS1 _L_(79) /**< SDRAMC signal: SDRAMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PC15A_SDRAMC_NCS1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PD18A_SDRAMC_NCS1 _L_(114) /**< SDRAMC signal: SDRAMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SDRAMC_NCS1 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS1 */ +#define PIO_PD18A_SDRAMC_NCS1 (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_NCS1 */ +#define PIN_PA22C_SDRAMC_NCS2 _L_(22) /**< SDRAMC signal: SDRAMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SDRAMC_NCS2 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NCS2 */ +#define PIO_PA22C_SDRAMC_NCS2 (_U_(1) << 22) /**< SDRAMC signal: SDRAMC_NCS2 */ +#define PIN_PC12A_SDRAMC_NCS3 _L_(76) /**< SDRAMC signal: SDRAMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PC12A_SDRAMC_NCS3 (_U_(1) << 12) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PD19A_SDRAMC_NCS3 _L_(115) /**< SDRAMC signal: SDRAMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SDRAMC_NCS3 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NCS3 */ +#define PIO_PD19A_SDRAMC_NCS3 (_U_(1) << 19) /**< SDRAMC signal: SDRAMC_NCS3 */ +#define PIN_PC11A_SDRAMC_NRD _L_(75) /**< SDRAMC signal: SDRAMC_NRD on PC11 mux A */ +#define MUX_PC11A_SDRAMC_NRD _L_(0) /**< SDRAMC signal line function value: SDRAMC_NRD */ +#define PIO_PC11A_SDRAMC_NRD (_U_(1) << 11) /**< SDRAMC signal: SDRAMC_NRD */ +#define PIN_PC13A_SDRAMC_NWAIT _L_(77) /**< SDRAMC signal: SDRAMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SDRAMC_NWAIT _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWAIT */ +#define PIO_PC13A_SDRAMC_NWAIT (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_NWAIT */ +#define PIN_PC8A_SDRAMC_NWE _L_(72) /**< SDRAMC signal: SDRAMC_NWE on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWE _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWE */ +#define PIO_PC8A_SDRAMC_NWE (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWE */ +#define PIN_PC8A_SDRAMC_NWR0 _L_(72) /**< SDRAMC signal: SDRAMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SDRAMC_NWR0 _L_(0) /**< SDRAMC signal line function value: SDRAMC_NWR0 */ +#define PIO_PC8A_SDRAMC_NWR0 (_U_(1) << 8) /**< SDRAMC signal: SDRAMC_NWR0 */ +#define PIN_PD15C_SDRAMC_NWR1 _L_(111) /**< SDRAMC signal: SDRAMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SDRAMC_NWR1 _L_(2) /**< SDRAMC signal line function value: SDRAMC_NWR1 */ +#define PIO_PD15C_SDRAMC_NWR1 (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_NWR1 */ +#define PIN_PD16C_SDRAMC_RAS _L_(112) /**< SDRAMC signal: SDRAMC_RAS on PD16 mux C */ +#define MUX_PD16C_SDRAMC_RAS _L_(2) /**< SDRAMC signal line function value: SDRAMC_RAS */ +#define PIO_PD16C_SDRAMC_RAS (_U_(1) << 16) /**< SDRAMC signal: SDRAMC_RAS */ +#define PIN_PC13C_SDRAMC_SDA10 _L_(77) /**< SDRAMC signal: SDRAMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PC13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD13C_SDRAMC_SDA10 _L_(109) /**< SDRAMC signal: SDRAMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SDRAMC_SDA10 _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDA10 */ +#define PIO_PD13C_SDRAMC_SDA10 (_U_(1) << 13) /**< SDRAMC signal: SDRAMC_SDA10 */ +#define PIN_PD23C_SDRAMC_SDCK _L_(119) /**< SDRAMC signal: SDRAMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SDRAMC_SDCK _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCK */ +#define PIO_PD23C_SDRAMC_SDCK (_U_(1) << 23) /**< SDRAMC signal: SDRAMC_SDCK */ +#define PIN_PD14C_SDRAMC_SDCKE _L_(110) /**< SDRAMC signal: SDRAMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SDRAMC_SDCKE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDCKE */ +#define PIO_PD14C_SDRAMC_SDCKE (_U_(1) << 14) /**< SDRAMC signal: SDRAMC_SDCKE */ +#define PIN_PC15A_SDRAMC_SDCS _L_(79) /**< SDRAMC signal: SDRAMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PC15A_SDRAMC_SDCS (_U_(1) << 15) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD18A_SDRAMC_SDCS _L_(114) /**< SDRAMC signal: SDRAMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SDRAMC_SDCS _L_(0) /**< SDRAMC signal line function value: SDRAMC_SDCS */ +#define PIO_PD18A_SDRAMC_SDCS (_U_(1) << 18) /**< SDRAMC signal: SDRAMC_SDCS */ +#define PIN_PD29C_SDRAMC_SDWE _L_(125) /**< SDRAMC signal: SDRAMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SDRAMC_SDWE _L_(2) /**< SDRAMC signal line function value: SDRAMC_SDWE */ +#define PIO_PD29C_SDRAMC_SDWE (_U_(1) << 29) /**< SDRAMC signal: SDRAMC_SDWE */ +/* ========== PIO definition for SMC peripheral ========== */ +#define PIN_PC18A_SMC_A0 _L_(82) /**< SMC signal: SMC_A0 on PC18 mux A */ +#define MUX_PC18A_SMC_A0 _L_(0) /**< SMC signal line function value: SMC_A0 */ +#define PIO_PC18A_SMC_A0 (_U_(1) << 18) /**< SMC signal: SMC_A0 */ +#define PIN_PC19A_SMC_A1 _L_(83) /**< SMC signal: SMC_A1 on PC19 mux A */ +#define MUX_PC19A_SMC_A1 _L_(0) /**< SMC signal line function value: SMC_A1 */ +#define PIO_PC19A_SMC_A1 (_U_(1) << 19) /**< SMC signal: SMC_A1 */ +#define PIN_PC20A_SMC_A2 _L_(84) /**< SMC signal: SMC_A2 on PC20 mux A */ +#define MUX_PC20A_SMC_A2 _L_(0) /**< SMC signal line function value: SMC_A2 */ +#define PIO_PC20A_SMC_A2 (_U_(1) << 20) /**< SMC signal: SMC_A2 */ +#define PIN_PC21A_SMC_A3 _L_(85) /**< SMC signal: SMC_A3 on PC21 mux A */ +#define MUX_PC21A_SMC_A3 _L_(0) /**< SMC signal line function value: SMC_A3 */ +#define PIO_PC21A_SMC_A3 (_U_(1) << 21) /**< SMC signal: SMC_A3 */ +#define PIN_PC22A_SMC_A4 _L_(86) /**< SMC signal: SMC_A4 on PC22 mux A */ +#define MUX_PC22A_SMC_A4 _L_(0) /**< SMC signal line function value: SMC_A4 */ +#define PIO_PC22A_SMC_A4 (_U_(1) << 22) /**< SMC signal: SMC_A4 */ +#define PIN_PC23A_SMC_A5 _L_(87) /**< SMC signal: SMC_A5 on PC23 mux A */ +#define MUX_PC23A_SMC_A5 _L_(0) /**< SMC signal line function value: SMC_A5 */ +#define PIO_PC23A_SMC_A5 (_U_(1) << 23) /**< SMC signal: SMC_A5 */ +#define PIN_PC24A_SMC_A6 _L_(88) /**< SMC signal: SMC_A6 on PC24 mux A */ +#define MUX_PC24A_SMC_A6 _L_(0) /**< SMC signal line function value: SMC_A6 */ +#define PIO_PC24A_SMC_A6 (_U_(1) << 24) /**< SMC signal: SMC_A6 */ +#define PIN_PC25A_SMC_A7 _L_(89) /**< SMC signal: SMC_A7 on PC25 mux A */ +#define MUX_PC25A_SMC_A7 _L_(0) /**< SMC signal line function value: SMC_A7 */ +#define PIO_PC25A_SMC_A7 (_U_(1) << 25) /**< SMC signal: SMC_A7 */ +#define PIN_PC26A_SMC_A8 _L_(90) /**< SMC signal: SMC_A8 on PC26 mux A */ +#define MUX_PC26A_SMC_A8 _L_(0) /**< SMC signal line function value: SMC_A8 */ +#define PIO_PC26A_SMC_A8 (_U_(1) << 26) /**< SMC signal: SMC_A8 */ +#define PIN_PC27A_SMC_A9 _L_(91) /**< SMC signal: SMC_A9 on PC27 mux A */ +#define MUX_PC27A_SMC_A9 _L_(0) /**< SMC signal line function value: SMC_A9 */ +#define PIO_PC27A_SMC_A9 (_U_(1) << 27) /**< SMC signal: SMC_A9 */ +#define PIN_PC28A_SMC_A10 _L_(92) /**< SMC signal: SMC_A10 on PC28 mux A */ +#define MUX_PC28A_SMC_A10 _L_(0) /**< SMC signal line function value: SMC_A10 */ +#define PIO_PC28A_SMC_A10 (_U_(1) << 28) /**< SMC signal: SMC_A10 */ +#define PIN_PC29A_SMC_A11 _L_(93) /**< SMC signal: SMC_A11 on PC29 mux A */ +#define MUX_PC29A_SMC_A11 _L_(0) /**< SMC signal line function value: SMC_A11 */ +#define PIO_PC29A_SMC_A11 (_U_(1) << 29) /**< SMC signal: SMC_A11 */ +#define PIN_PC30A_SMC_A12 _L_(94) /**< SMC signal: SMC_A12 on PC30 mux A */ +#define MUX_PC30A_SMC_A12 _L_(0) /**< SMC signal line function value: SMC_A12 */ +#define PIO_PC30A_SMC_A12 (_U_(1) << 30) /**< SMC signal: SMC_A12 */ +#define PIN_PC31A_SMC_A13 _L_(95) /**< SMC signal: SMC_A13 on PC31 mux A */ +#define MUX_PC31A_SMC_A13 _L_(0) /**< SMC signal line function value: SMC_A13 */ +#define PIO_PC31A_SMC_A13 (_U_(1) << 31) /**< SMC signal: SMC_A13 */ +#define PIN_PA18C_SMC_A14 _L_(18) /**< SMC signal: SMC_A14 on PA18 mux C */ +#define MUX_PA18C_SMC_A14 _L_(2) /**< SMC signal line function value: SMC_A14 */ +#define PIO_PA18C_SMC_A14 (_U_(1) << 18) /**< SMC signal: SMC_A14 */ +#define PIN_PA19C_SMC_A15 _L_(19) /**< SMC signal: SMC_A15 on PA19 mux C */ +#define MUX_PA19C_SMC_A15 _L_(2) /**< SMC signal line function value: SMC_A15 */ +#define PIO_PA19C_SMC_A15 (_U_(1) << 19) /**< SMC signal: SMC_A15 */ +#define PIN_PA20C_SMC_A16 _L_(20) /**< SMC signal: SMC_A16 on PA20 mux C */ +#define MUX_PA20C_SMC_A16 _L_(2) /**< SMC signal line function value: SMC_A16 */ +#define PIO_PA20C_SMC_A16 (_U_(1) << 20) /**< SMC signal: SMC_A16 */ +#define PIN_PA0C_SMC_A17 _L_(0) /**< SMC signal: SMC_A17 on PA0 mux C */ +#define MUX_PA0C_SMC_A17 _L_(2) /**< SMC signal line function value: SMC_A17 */ +#define PIO_PA0C_SMC_A17 (_U_(1) << 0) /**< SMC signal: SMC_A17 */ +#define PIN_PA1C_SMC_A18 _L_(1) /**< SMC signal: SMC_A18 on PA1 mux C */ +#define MUX_PA1C_SMC_A18 _L_(2) /**< SMC signal line function value: SMC_A18 */ +#define PIO_PA1C_SMC_A18 (_U_(1) << 1) /**< SMC signal: SMC_A18 */ +#define PIN_PA23C_SMC_A19 _L_(23) /**< SMC signal: SMC_A19 on PA23 mux C */ +#define MUX_PA23C_SMC_A19 _L_(2) /**< SMC signal line function value: SMC_A19 */ +#define PIO_PA23C_SMC_A19 (_U_(1) << 23) /**< SMC signal: SMC_A19 */ +#define PIN_PA24C_SMC_A20 _L_(24) /**< SMC signal: SMC_A20 on PA24 mux C */ +#define MUX_PA24C_SMC_A20 _L_(2) /**< SMC signal line function value: SMC_A20 */ +#define PIO_PA24C_SMC_A20 (_U_(1) << 24) /**< SMC signal: SMC_A20 */ +#define PIN_PC16A_SMC_A21 _L_(80) /**< SMC signal: SMC_A21 on PC16 mux A */ +#define MUX_PC16A_SMC_A21 _L_(0) /**< SMC signal line function value: SMC_A21 */ +#define PIO_PC16A_SMC_A21 (_U_(1) << 16) /**< SMC signal: SMC_A21 */ +#define PIN_PC17A_SMC_A22 _L_(81) /**< SMC signal: SMC_A22 on PC17 mux A */ +#define MUX_PC17A_SMC_A22 _L_(0) /**< SMC signal line function value: SMC_A22 */ +#define PIO_PC17A_SMC_A22 (_U_(1) << 17) /**< SMC signal: SMC_A22 */ +#define PIN_PA25C_SMC_A23 _L_(25) /**< SMC signal: SMC_A23 on PA25 mux C */ +#define MUX_PA25C_SMC_A23 _L_(2) /**< SMC signal line function value: SMC_A23 */ +#define PIO_PA25C_SMC_A23 (_U_(1) << 25) /**< SMC signal: SMC_A23 */ +#define PIN_PA20C_SMC_BA0 _L_(20) /**< SMC signal: SMC_BA0 on PA20 mux C */ +#define MUX_PA20C_SMC_BA0 _L_(2) /**< SMC signal line function value: SMC_BA0 */ +#define PIO_PA20C_SMC_BA0 (_U_(1) << 20) /**< SMC signal: SMC_BA0 */ +#define PIN_PA0C_SMC_BA1 _L_(0) /**< SMC signal: SMC_BA1 on PA0 mux C */ +#define MUX_PA0C_SMC_BA1 _L_(2) /**< SMC signal line function value: SMC_BA1 */ +#define PIO_PA0C_SMC_BA1 (_U_(1) << 0) /**< SMC signal: SMC_BA1 */ +#define PIN_PD17C_SMC_CAS _L_(113) /**< SMC signal: SMC_CAS on PD17 mux C */ +#define MUX_PD17C_SMC_CAS _L_(2) /**< SMC signal line function value: SMC_CAS */ +#define PIO_PD17C_SMC_CAS (_U_(1) << 17) /**< SMC signal: SMC_CAS */ +#define PIN_PC0A_SMC_D0 _L_(64) /**< SMC signal: SMC_D0 on PC0 mux A */ +#define MUX_PC0A_SMC_D0 _L_(0) /**< SMC signal line function value: SMC_D0 */ +#define PIO_PC0A_SMC_D0 (_U_(1) << 0) /**< SMC signal: SMC_D0 */ +#define PIN_PC1A_SMC_D1 _L_(65) /**< SMC signal: SMC_D1 on PC1 mux A */ +#define MUX_PC1A_SMC_D1 _L_(0) /**< SMC signal line function value: SMC_D1 */ +#define PIO_PC1A_SMC_D1 (_U_(1) << 1) /**< SMC signal: SMC_D1 */ +#define PIN_PC2A_SMC_D2 _L_(66) /**< SMC signal: SMC_D2 on PC2 mux A */ +#define MUX_PC2A_SMC_D2 _L_(0) /**< SMC signal line function value: SMC_D2 */ +#define PIO_PC2A_SMC_D2 (_U_(1) << 2) /**< SMC signal: SMC_D2 */ +#define PIN_PC3A_SMC_D3 _L_(67) /**< SMC signal: SMC_D3 on PC3 mux A */ +#define MUX_PC3A_SMC_D3 _L_(0) /**< SMC signal line function value: SMC_D3 */ +#define PIO_PC3A_SMC_D3 (_U_(1) << 3) /**< SMC signal: SMC_D3 */ +#define PIN_PC4A_SMC_D4 _L_(68) /**< SMC signal: SMC_D4 on PC4 mux A */ +#define MUX_PC4A_SMC_D4 _L_(0) /**< SMC signal line function value: SMC_D4 */ +#define PIO_PC4A_SMC_D4 (_U_(1) << 4) /**< SMC signal: SMC_D4 */ +#define PIN_PC5A_SMC_D5 _L_(69) /**< SMC signal: SMC_D5 on PC5 mux A */ +#define MUX_PC5A_SMC_D5 _L_(0) /**< SMC signal line function value: SMC_D5 */ +#define PIO_PC5A_SMC_D5 (_U_(1) << 5) /**< SMC signal: SMC_D5 */ +#define PIN_PC6A_SMC_D6 _L_(70) /**< SMC signal: SMC_D6 on PC6 mux A */ +#define MUX_PC6A_SMC_D6 _L_(0) /**< SMC signal line function value: SMC_D6 */ +#define PIO_PC6A_SMC_D6 (_U_(1) << 6) /**< SMC signal: SMC_D6 */ +#define PIN_PC7A_SMC_D7 _L_(71) /**< SMC signal: SMC_D7 on PC7 mux A */ +#define MUX_PC7A_SMC_D7 _L_(0) /**< SMC signal line function value: SMC_D7 */ +#define PIO_PC7A_SMC_D7 (_U_(1) << 7) /**< SMC signal: SMC_D7 */ +#define PIN_PE0A_SMC_D8 _L_(128) /**< SMC signal: SMC_D8 on PE0 mux A */ +#define MUX_PE0A_SMC_D8 _L_(0) /**< SMC signal line function value: SMC_D8 */ +#define PIO_PE0A_SMC_D8 (_U_(1) << 0) /**< SMC signal: SMC_D8 */ +#define PIN_PE1A_SMC_D9 _L_(129) /**< SMC signal: SMC_D9 on PE1 mux A */ +#define MUX_PE1A_SMC_D9 _L_(0) /**< SMC signal line function value: SMC_D9 */ +#define PIO_PE1A_SMC_D9 (_U_(1) << 1) /**< SMC signal: SMC_D9 */ +#define PIN_PE2A_SMC_D10 _L_(130) /**< SMC signal: SMC_D10 on PE2 mux A */ +#define MUX_PE2A_SMC_D10 _L_(0) /**< SMC signal line function value: SMC_D10 */ +#define PIO_PE2A_SMC_D10 (_U_(1) << 2) /**< SMC signal: SMC_D10 */ +#define PIN_PE3A_SMC_D11 _L_(131) /**< SMC signal: SMC_D11 on PE3 mux A */ +#define MUX_PE3A_SMC_D11 _L_(0) /**< SMC signal line function value: SMC_D11 */ +#define PIO_PE3A_SMC_D11 (_U_(1) << 3) /**< SMC signal: SMC_D11 */ +#define PIN_PE4A_SMC_D12 _L_(132) /**< SMC signal: SMC_D12 on PE4 mux A */ +#define MUX_PE4A_SMC_D12 _L_(0) /**< SMC signal line function value: SMC_D12 */ +#define PIO_PE4A_SMC_D12 (_U_(1) << 4) /**< SMC signal: SMC_D12 */ +#define PIN_PE5A_SMC_D13 _L_(133) /**< SMC signal: SMC_D13 on PE5 mux A */ +#define MUX_PE5A_SMC_D13 _L_(0) /**< SMC signal line function value: SMC_D13 */ +#define PIO_PE5A_SMC_D13 (_U_(1) << 5) /**< SMC signal: SMC_D13 */ +#define PIN_PA15A_SMC_D14 _L_(15) /**< SMC signal: SMC_D14 on PA15 mux A */ +#define MUX_PA15A_SMC_D14 _L_(0) /**< SMC signal line function value: SMC_D14 */ +#define PIO_PA15A_SMC_D14 (_U_(1) << 15) /**< SMC signal: SMC_D14 */ +#define PIN_PA16A_SMC_D15 _L_(16) /**< SMC signal: SMC_D15 on PA16 mux A */ +#define MUX_PA16A_SMC_D15 _L_(0) /**< SMC signal line function value: SMC_D15 */ +#define PIO_PA16A_SMC_D15 (_U_(1) << 16) /**< SMC signal: SMC_D15 */ +#define PIN_PC16A_SMC_NANDALE _L_(80) /**< SMC signal: SMC_NANDALE on PC16 mux A */ +#define MUX_PC16A_SMC_NANDALE _L_(0) /**< SMC signal line function value: SMC_NANDALE */ +#define PIO_PC16A_SMC_NANDALE (_U_(1) << 16) /**< SMC signal: SMC_NANDALE */ +#define PIN_PC17A_SMC_NANDCLE _L_(81) /**< SMC signal: SMC_NANDCLE on PC17 mux A */ +#define MUX_PC17A_SMC_NANDCLE _L_(0) /**< SMC signal line function value: SMC_NANDCLE */ +#define PIO_PC17A_SMC_NANDCLE (_U_(1) << 17) /**< SMC signal: SMC_NANDCLE */ +#define PIN_PC9A_SMC_NANDOE _L_(73) /**< SMC signal: SMC_NANDOE on PC9 mux A */ +#define MUX_PC9A_SMC_NANDOE _L_(0) /**< SMC signal line function value: SMC_NANDOE */ +#define PIO_PC9A_SMC_NANDOE (_U_(1) << 9) /**< SMC signal: SMC_NANDOE */ +#define PIN_PC10A_SMC_NANDWE _L_(74) /**< SMC signal: SMC_NANDWE on PC10 mux A */ +#define MUX_PC10A_SMC_NANDWE _L_(0) /**< SMC signal line function value: SMC_NANDWE */ +#define PIO_PC10A_SMC_NANDWE (_U_(1) << 10) /**< SMC signal: SMC_NANDWE */ +#define PIN_PC18A_SMC_NBS0 _L_(82) /**< SMC signal: SMC_NBS0 on PC18 mux A */ +#define MUX_PC18A_SMC_NBS0 _L_(0) /**< SMC signal line function value: SMC_NBS0 */ +#define PIO_PC18A_SMC_NBS0 (_U_(1) << 18) /**< SMC signal: SMC_NBS0 */ +#define PIN_PD15C_SMC_NBS1 _L_(111) /**< SMC signal: SMC_NBS1 on PD15 mux C */ +#define MUX_PD15C_SMC_NBS1 _L_(2) /**< SMC signal line function value: SMC_NBS1 */ +#define PIO_PD15C_SMC_NBS1 (_U_(1) << 15) /**< SMC signal: SMC_NBS1 */ +#define PIN_PC14A_SMC_NCS0 _L_(78) /**< SMC signal: SMC_NCS0 on PC14 mux A */ +#define MUX_PC14A_SMC_NCS0 _L_(0) /**< SMC signal line function value: SMC_NCS0 */ +#define PIO_PC14A_SMC_NCS0 (_U_(1) << 14) /**< SMC signal: SMC_NCS0 */ +#define PIN_PC15A_SMC_NCS1 _L_(79) /**< SMC signal: SMC_NCS1 on PC15 mux A */ +#define MUX_PC15A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PC15A_SMC_NCS1 (_U_(1) << 15) /**< SMC signal: SMC_NCS1 */ +#define PIN_PD18A_SMC_NCS1 _L_(114) /**< SMC signal: SMC_NCS1 on PD18 mux A */ +#define MUX_PD18A_SMC_NCS1 _L_(0) /**< SMC signal line function value: SMC_NCS1 */ +#define PIO_PD18A_SMC_NCS1 (_U_(1) << 18) /**< SMC signal: SMC_NCS1 */ +#define PIN_PA22C_SMC_NCS2 _L_(22) /**< SMC signal: SMC_NCS2 on PA22 mux C */ +#define MUX_PA22C_SMC_NCS2 _L_(2) /**< SMC signal line function value: SMC_NCS2 */ +#define PIO_PA22C_SMC_NCS2 (_U_(1) << 22) /**< SMC signal: SMC_NCS2 */ +#define PIN_PC12A_SMC_NCS3 _L_(76) /**< SMC signal: SMC_NCS3 on PC12 mux A */ +#define MUX_PC12A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PC12A_SMC_NCS3 (_U_(1) << 12) /**< SMC signal: SMC_NCS3 */ +#define PIN_PD19A_SMC_NCS3 _L_(115) /**< SMC signal: SMC_NCS3 on PD19 mux A */ +#define MUX_PD19A_SMC_NCS3 _L_(0) /**< SMC signal line function value: SMC_NCS3 */ +#define PIO_PD19A_SMC_NCS3 (_U_(1) << 19) /**< SMC signal: SMC_NCS3 */ +#define PIN_PC11A_SMC_NRD _L_(75) /**< SMC signal: SMC_NRD on PC11 mux A */ +#define MUX_PC11A_SMC_NRD _L_(0) /**< SMC signal line function value: SMC_NRD */ +#define PIO_PC11A_SMC_NRD (_U_(1) << 11) /**< SMC signal: SMC_NRD */ +#define PIN_PC13A_SMC_NWAIT _L_(77) /**< SMC signal: SMC_NWAIT on PC13 mux A */ +#define MUX_PC13A_SMC_NWAIT _L_(0) /**< SMC signal line function value: SMC_NWAIT */ +#define PIO_PC13A_SMC_NWAIT (_U_(1) << 13) /**< SMC signal: SMC_NWAIT */ +#define PIN_PC8A_SMC_NWE _L_(72) /**< SMC signal: SMC_NWE on PC8 mux A */ +#define MUX_PC8A_SMC_NWE _L_(0) /**< SMC signal line function value: SMC_NWE */ +#define PIO_PC8A_SMC_NWE (_U_(1) << 8) /**< SMC signal: SMC_NWE */ +#define PIN_PC8A_SMC_NWR0 _L_(72) /**< SMC signal: SMC_NWR0 on PC8 mux A */ +#define MUX_PC8A_SMC_NWR0 _L_(0) /**< SMC signal line function value: SMC_NWR0 */ +#define PIO_PC8A_SMC_NWR0 (_U_(1) << 8) /**< SMC signal: SMC_NWR0 */ +#define PIN_PD15C_SMC_NWR1 _L_(111) /**< SMC signal: SMC_NWR1 on PD15 mux C */ +#define MUX_PD15C_SMC_NWR1 _L_(2) /**< SMC signal line function value: SMC_NWR1 */ +#define PIO_PD15C_SMC_NWR1 (_U_(1) << 15) /**< SMC signal: SMC_NWR1 */ +#define PIN_PD16C_SMC_RAS _L_(112) /**< SMC signal: SMC_RAS on PD16 mux C */ +#define MUX_PD16C_SMC_RAS _L_(2) /**< SMC signal line function value: SMC_RAS */ +#define PIO_PD16C_SMC_RAS (_U_(1) << 16) /**< SMC signal: SMC_RAS */ +#define PIN_PC13C_SMC_SDA10 _L_(77) /**< SMC signal: SMC_SDA10 on PC13 mux C */ +#define MUX_PC13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PC13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD13C_SMC_SDA10 _L_(109) /**< SMC signal: SMC_SDA10 on PD13 mux C */ +#define MUX_PD13C_SMC_SDA10 _L_(2) /**< SMC signal line function value: SMC_SDA10 */ +#define PIO_PD13C_SMC_SDA10 (_U_(1) << 13) /**< SMC signal: SMC_SDA10 */ +#define PIN_PD23C_SMC_SDCK _L_(119) /**< SMC signal: SMC_SDCK on PD23 mux C */ +#define MUX_PD23C_SMC_SDCK _L_(2) /**< SMC signal line function value: SMC_SDCK */ +#define PIO_PD23C_SMC_SDCK (_U_(1) << 23) /**< SMC signal: SMC_SDCK */ +#define PIN_PD14C_SMC_SDCKE _L_(110) /**< SMC signal: SMC_SDCKE on PD14 mux C */ +#define MUX_PD14C_SMC_SDCKE _L_(2) /**< SMC signal line function value: SMC_SDCKE */ +#define PIO_PD14C_SMC_SDCKE (_U_(1) << 14) /**< SMC signal: SMC_SDCKE */ +#define PIN_PC15A_SMC_SDCS _L_(79) /**< SMC signal: SMC_SDCS on PC15 mux A */ +#define MUX_PC15A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PC15A_SMC_SDCS (_U_(1) << 15) /**< SMC signal: SMC_SDCS */ +#define PIN_PD18A_SMC_SDCS _L_(114) /**< SMC signal: SMC_SDCS on PD18 mux A */ +#define MUX_PD18A_SMC_SDCS _L_(0) /**< SMC signal line function value: SMC_SDCS */ +#define PIO_PD18A_SMC_SDCS (_U_(1) << 18) /**< SMC signal: SMC_SDCS */ +#define PIN_PD29C_SMC_SDWE _L_(125) /**< SMC signal: SMC_SDWE on PD29 mux C */ +#define MUX_PD29C_SMC_SDWE _L_(2) /**< SMC signal line function value: SMC_SDWE */ +#define PIO_PD29C_SMC_SDWE (_U_(1) << 29) /**< SMC signal: SMC_SDWE */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ + +#endif /* _SAME70Q21_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/sam.h b/arch/arm/SAME70/SAME70A/mcu/inc/sam.h new file mode 100644 index 00000000..5080147d --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/sam.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME70Q19__) || defined(__ATSAME70Q19__) + #include "same70q19.h" +#elif defined(__SAME70J21__) || defined(__ATSAME70J21__) + #include "same70j21.h" +#elif defined(__SAME70N21__) || defined(__ATSAME70N21__) + #include "same70n21.h" +#elif defined(__SAME70Q21__) || defined(__ATSAME70Q21__) + #include "same70q21.h" +#elif defined(__SAME70J19__) || defined(__ATSAME70J19__) + #include "same70j19.h" +#elif defined(__SAME70N20__) || defined(__ATSAME70N20__) + #include "same70n20.h" +#elif defined(__SAME70J20__) || defined(__ATSAME70J20__) + #include "same70j20.h" +#elif defined(__SAME70N19__) || defined(__ATSAME70N19__) + #include "same70n19.h" +#elif defined(__SAME70Q20__) || defined(__ATSAME70Q20__) + #include "same70q20.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70j19.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70j19.h new file mode 100644 index 00000000..c309391c --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70j19.h @@ -0,0 +1,617 @@ +/** + * \brief Header file for ATSAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2018-01-08T14:00:00Z */ +#ifndef _SAME70J19_H_ +#define _SAME70J19_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J19_definitions SAME70J19 definitions + This file defines all structures and symbols for SAME70J19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J19 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J19_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J19_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J19_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#include "pio/same70j19.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J19 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A00) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J19 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J19 definitions */ + + +#endif /* _SAME70J19_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70j20.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70j20.h new file mode 100644 index 00000000..8eaea2e2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70j20.h @@ -0,0 +1,617 @@ +/** + * \brief Header file for ATSAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70J20_H_ +#define _SAME70J20_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J20_definitions SAME70J20 definitions + This file defines all structures and symbols for SAME70J20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J20 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J20_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J20_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J20_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#include "pio/same70j20.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J20 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C00) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J20 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J20 definitions */ + + +#endif /* _SAME70J20_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70j21.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70j21.h new file mode 100644 index 00000000..85ec52d0 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70j21.h @@ -0,0 +1,615 @@ +/** + * \brief Header file for ATSAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70J21_H_ +#define _SAME70J21_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J21_definitions SAME70J21 definitions + This file defines all structures and symbols for SAME70J21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J21 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J21_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J21_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J21_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#include "pio/same70j21.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J21 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E00) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J21 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J21 definitions */ + + +#endif /* _SAME70J21_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70n19.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70n19.h new file mode 100644 index 00000000..5306fb9b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70n19.h @@ -0,0 +1,656 @@ +/** + * \brief Header file for ATSAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N19_H_ +#define _SAME70N19_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N19_definitions SAME70N19 definitions + This file defines all structures and symbols for SAME70N19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N19 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N19_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N19_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N19_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#include "pio/same70n19.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N19 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A00) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N19 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N19 definitions */ + + +#endif /* _SAME70N19_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70n20.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70n20.h new file mode 100644 index 00000000..f1b7dd2b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70n20.h @@ -0,0 +1,656 @@ +/** + * \brief Header file for ATSAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N20_H_ +#define _SAME70N20_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N20_definitions SAME70N20 definitions + This file defines all structures and symbols for SAME70N20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N20 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N20_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N20_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N20_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#include "pio/same70n20.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N20 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C00) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N20 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N20 definitions */ + + +#endif /* _SAME70N20_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70n21.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70n21.h new file mode 100644 index 00000000..5f961cb0 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70n21.h @@ -0,0 +1,656 @@ +/** + * \brief Header file for ATSAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70N21_H_ +#define _SAME70N21_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N21_definitions SAME70N21 definitions + This file defines all structures and symbols for SAME70N21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N21 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N21_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N21_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N21_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#include "pio/same70n21.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N21 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E00) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N21 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N21 definitions */ + + +#endif /* _SAME70N21_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70q19.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70q19.h new file mode 100644 index 00000000..42dfd6e6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70q19.h @@ -0,0 +1,689 @@ +/** + * \brief Header file for ATSAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70Q19_H_ +#define _SAME70Q19_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q19_definitions SAME70Q19 definitions + This file defines all structures and symbols for SAME70Q19: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q19 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q19_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q19_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q19_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q19_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#include "pio/same70q19.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q19 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A00) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q19 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q19 definitions */ + + +#endif /* _SAME70Q19_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70q20.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70q20.h new file mode 100644 index 00000000..18922252 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70q20.h @@ -0,0 +1,689 @@ +/** + * \brief Header file for ATSAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-01-08T14:00:00Z */ +#ifndef _SAME70Q20_H_ +#define _SAME70Q20_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q20_definitions SAME70Q20 definitions + This file defines all structures and symbols for SAME70Q20: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q20 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q20_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q20_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q20_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q20_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#include "pio/same70q20.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q20 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C00) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q20 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q20 definitions */ + + +#endif /* _SAME70Q20_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/same70q21.h b/arch/arm/SAME70/SAME70A/mcu/inc/same70q21.h new file mode 100644 index 00000000..c9c2cc8e --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/same70q21.h @@ -0,0 +1,689 @@ +/** + * \brief Header file for ATSAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2017-08-25T14:00:00Z */ +#ifndef _SAME70Q21_H_ +#define _SAME70Q21_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q21_definitions SAME70Q21 definitions + This file defines all structures and symbols for SAME70Q21: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q21 specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 Timer Counter (TC0) */ + TC1_IRQn = 24, /**< 24 Timer Counter (TC0) */ + TC2_IRQn = 25, /**< 25 Timer Counter (TC0) */ + TC3_IRQn = 26, /**< 26 Timer Counter (TC1) */ + TC4_IRQn = 27, /**< 27 Timer Counter (TC1) */ + TC5_IRQn = 28, /**< 28 Timer Counter (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC6_IRQn = 47, /**< 47 Timer Counter (TC2) */ + TC7_IRQn = 48, /**< 48 Timer Counter (TC2) */ + TC8_IRQn = 49, /**< 49 Timer Counter (TC2) */ + TC9_IRQn = 50, /**< 50 Timer Counter (TC3) */ + TC10_IRQn = 51, /**< 51 Timer Counter (TC3) */ + TC11_IRQn = 52, /**< 52 Timer Counter (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 CCW (SystemControl) */ + CCF_IRQn = 65, /**< 65 CCF (SystemControl) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + + PERIPH_MAX_IRQn = 68 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_Handler; /* 23 Timer Counter (TC0) */ + void* pfnTC1_Handler; /* 24 Timer Counter (TC0) */ + void* pfnTC2_Handler; /* 25 Timer Counter (TC0) */ + void* pfnTC3_Handler; /* 26 Timer Counter (TC1) */ + void* pfnTC4_Handler; /* 27 Timer Counter (TC1) */ + void* pfnTC5_Handler; /* 28 Timer Counter (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC6_Handler; /* 47 Timer Counter (TC2) */ + void* pfnTC7_Handler; /* 48 Timer Counter (TC2) */ + void* pfnTC8_Handler; /* 49 Timer Counter (TC2) */ + void* pfnTC9_Handler; /* 50 Timer Counter (TC3) */ + void* pfnTC10_Handler; /* 51 Timer Counter (TC3) */ + void* pfnTC11_Handler; /* 52 Timer Counter (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pvReserved64; + void* pvReserved65; + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q21_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21 */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q21_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q21_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q21_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#include "pio/same70q21.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q21 */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E00) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q21 */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q21 definitions */ + + +#endif /* _SAME70Q21_H_ */ + diff --git a/arch/arm/SAME70/SAME70A/mcu/inc/system_same70.h b/arch/arm/SAME70/SAME70A/mcu/inc/system_same70.h new file mode 100644 index 00000000..d673cb6d --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/inc/system_same70.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon device startup + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SYSTEM_SAME70_H_INCLUDED_ +#define _SYSTEM_SAME70_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAME70_H_INCLUDED */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j19.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j19.c new file mode 100644 index 00000000..41ba73d2 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j19.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j19.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j20.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j20.c new file mode 100644 index 00000000..6cad5a05 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j20.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j20.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j21.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j21.c new file mode 100644 index 00000000..bf9e0370 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70j21.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n19.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n19.c new file mode 100644 index 00000000..9b9c86c0 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n19.c @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n19.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n20.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n20.c new file mode 100644 index 00000000..cddc2ba7 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n20.c @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n20.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n21.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n21.c new file mode 100644 index 00000000..7af2f3fb --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70n21.c @@ -0,0 +1,266 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q19.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q19.c new file mode 100644 index 00000000..7aa4fdaf --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q19.c @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q19.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q20.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q20.c new file mode 100644 index 00000000..431f2be9 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q20.c @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q20.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q21.c b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q21.c new file mode 100644 index 00000000..fa7b5e39 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/startup_same70q21.c @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer Counter */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer Counter */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer Counter */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer Counter */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer Counter */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer Counter */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer Counter */ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer Counter */ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer Counter */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer Counter */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer Counter */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer Counter */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler /* 68 Floating Point Unit */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70j19.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j19.c new file mode 100644 index 00000000..ae6f0766 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j19.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j19.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70j20.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j20.c new file mode 100644 index 00000000..7d5c9ba6 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j20.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j20.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70j21.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j21.c new file mode 100644 index 00000000..21378f32 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70j21.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j21.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70n19.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n19.c new file mode 100644 index 00000000..95ee491f --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n19.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n19.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70n20.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n20.c new file mode 100644 index 00000000..b53931cd --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n20.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n20.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70n21.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n21.c new file mode 100644 index 00000000..2cec358b --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70n21.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n21.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70q19.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q19.c new file mode 100644 index 00000000..72a6a7e3 --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q19.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q19 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q19.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70q20.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q20.c new file mode 100644 index 00000000..4d38b6aa --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q20.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q20 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q20.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70A/mcu/src/system_same70q21.c b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q21.c new file mode 100644 index 00000000..a9852e8f --- /dev/null +++ b/arch/arm/SAME70/SAME70A/mcu/src/system_same70q21.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q21 + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/ld/same70j19b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70j19b_flash.ld new file mode 100644 index 00000000..52042c1c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j19b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70j19b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70j19b_sram.ld new file mode 100644 index 00000000..45f7877d --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j19b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70j20b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70j20b_flash.ld new file mode 100644 index 00000000..3714d6b9 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j20b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70j20b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70j20b_sram.ld new file mode 100644 index 00000000..3ce5fbd8 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j20b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70j21b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70j21b_flash.ld new file mode 100644 index 00000000..5dca1593 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j21b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70J21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70j21b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70j21b_sram.ld new file mode 100644 index 00000000..97e9f185 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70j21b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70J21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70n19b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70n19b_flash.ld new file mode 100644 index 00000000..3b50f538 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n19b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70n19b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70n19b_sram.ld new file mode 100644 index 00000000..c10cc379 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n19b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70n20b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70n20b_flash.ld new file mode 100644 index 00000000..473a4ba7 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n20b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70n20b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70n20b_sram.ld new file mode 100644 index 00000000..9291bcd5 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n20b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70n21b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70n21b_flash.ld new file mode 100644 index 00000000..1ddce388 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n21b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70N21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70n21b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70n21b_sram.ld new file mode 100644 index 00000000..8d711a38 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70n21b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70N21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70q19b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70q19b_flash.ld new file mode 100644 index 00000000..b6ad2862 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q19b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70q19b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70q19b_sram.ld new file mode 100644 index 00000000..3c9623c0 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q19b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q19B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70q20b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70q20b_flash.ld new file mode 100644 index 00000000..779979f0 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q20b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70q20b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70q20b_sram.ld new file mode 100644 index 00000000..4bd16574 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q20b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q20B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/ld/same70q21b_flash.ld b/arch/arm/SAME70/SAME70B/ld/same70q21b_flash.ld new file mode 100644 index 00000000..97469c40 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q21b_flash.ld @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief GCC linker script (flash) for ATSAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAME70Q21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} diff --git a/arch/arm/SAME70/SAME70B/ld/same70q21b_sram.ld b/arch/arm/SAME70/SAME70B/ld/same70q21b_sram.ld new file mode 100644 index 00000000..eaaa123f --- /dev/null +++ b/arch/arm/SAME70/SAME70B/ld/same70q21b_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief GCC linker script (sram) for ATSAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAME70Q21B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */ + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */ +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ; +} + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component-version.h b/arch/arm/SAME70/SAME70B/mcu/inc/component-version.h new file mode 100644 index 00000000..d7b31ead --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 4 +#define COMPONENT_VERSION_MINOR 4 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 40004 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 78 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "4.4" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2020-09-24 08:35:02" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/acc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/acc.h new file mode 100644 index 00000000..e6124f8f --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/acc.h @@ -0,0 +1,215 @@ +/** + * \brief Component description for ACC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_ACC_COMPONENT_H_ +#define _SAME70_ACC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ACC */ +/* ************************************************************************** */ + +/* -------- ACC_CR : (ACC Offset: 0x00) ( /W 32) Control Register -------- */ +#define ACC_CR_SWRST_Pos _U_(0) /**< (ACC_CR) Software Reset Position */ +#define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */ +#define ACC_CR_SWRST(value) (ACC_CR_SWRST_Msk & ((value) << ACC_CR_SWRST_Pos)) +#define ACC_CR_Msk _U_(0x00000001) /**< (ACC_CR) Register Mask */ + + +/* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos _U_(0) /**< (ACC_MR) Selection for Minus Comparator Input Position */ +#define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */ +#define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)) +#define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */ +#define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */ +#define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */ +#define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */ +#define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_Pos _U_(4) /**< (ACC_MR) Selection For Plus Comparator Input Position */ +#define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */ +#define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)) +#define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ +#define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ +#define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ +#define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ +#define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */ +#define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */ +#define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */ +#define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */ +#define ACC_MR_ACEN_Pos _U_(8) /**< (ACC_MR) Analog Comparator Enable Position */ +#define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */ +#define ACC_MR_ACEN(value) (ACC_MR_ACEN_Msk & ((value) << ACC_MR_ACEN_Pos)) +#define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */ +#define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */ +#define ACC_MR_EDGETYP_Pos _U_(9) /**< (ACC_MR) Edge Type Position */ +#define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */ +#define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)) +#define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */ +#define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */ +#define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */ +#define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */ +#define ACC_MR_INV_Pos _U_(12) /**< (ACC_MR) Invert Comparator Output Position */ +#define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */ +#define ACC_MR_INV(value) (ACC_MR_INV_Msk & ((value) << ACC_MR_INV_Pos)) +#define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */ +#define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */ +#define ACC_MR_SELFS_Pos _U_(13) /**< (ACC_MR) Selection Of Fault Source Position */ +#define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */ +#define ACC_MR_SELFS(value) (ACC_MR_SELFS_Msk & ((value) << ACC_MR_SELFS_Pos)) +#define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */ +#define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */ +#define ACC_MR_FE_Pos _U_(14) /**< (ACC_MR) Fault Enable Position */ +#define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */ +#define ACC_MR_FE(value) (ACC_MR_FE_Msk & ((value) << ACC_MR_FE_Pos)) +#define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +#define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */ +#define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */ +#define ACC_MR_Msk _U_(0x00007777) /**< (ACC_MR) Register Mask */ + + +/* -------- ACC_IER : (ACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define ACC_IER_CE_Pos _U_(0) /**< (ACC_IER) Comparison Edge Position */ +#define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */ +#define ACC_IER_CE(value) (ACC_IER_CE_Msk & ((value) << ACC_IER_CE_Pos)) +#define ACC_IER_Msk _U_(0x00000001) /**< (ACC_IER) Register Mask */ + + +/* -------- ACC_IDR : (ACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define ACC_IDR_CE_Pos _U_(0) /**< (ACC_IDR) Comparison Edge Position */ +#define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */ +#define ACC_IDR_CE(value) (ACC_IDR_CE_Msk & ((value) << ACC_IDR_CE_Pos)) +#define ACC_IDR_Msk _U_(0x00000001) /**< (ACC_IDR) Register Mask */ + + +/* -------- ACC_IMR : (ACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define ACC_IMR_CE_Pos _U_(0) /**< (ACC_IMR) Comparison Edge Position */ +#define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */ +#define ACC_IMR_CE(value) (ACC_IMR_CE_Msk & ((value) << ACC_IMR_CE_Pos)) +#define ACC_IMR_Msk _U_(0x00000001) /**< (ACC_IMR) Register Mask */ + + +/* -------- ACC_ISR : (ACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */ +#define ACC_ISR_CE_Pos _U_(0) /**< (ACC_ISR) Comparison Edge (cleared on read) Position */ +#define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */ +#define ACC_ISR_CE(value) (ACC_ISR_CE_Msk & ((value) << ACC_ISR_CE_Pos)) +#define ACC_ISR_SCO_Pos _U_(1) /**< (ACC_ISR) Synchronized Comparator Output Position */ +#define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */ +#define ACC_ISR_SCO(value) (ACC_ISR_SCO_Msk & ((value) << ACC_ISR_SCO_Pos)) +#define ACC_ISR_MASK_Pos _U_(31) /**< (ACC_ISR) Flag Mask Position */ +#define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */ +#define ACC_ISR_MASK(value) (ACC_ISR_MASK_Msk & ((value) << ACC_ISR_MASK_Pos)) +#define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */ + + +/* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */ +#define ACC_ACR_ISEL_Pos _U_(0) /**< (ACC_ACR) Current Selection Position */ +#define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */ +#define ACC_ACR_ISEL(value) (ACC_ACR_ISEL_Msk & ((value) << ACC_ACR_ISEL_Pos)) +#define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */ +#define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */ +#define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */ +#define ACC_ACR_HYST_Pos _U_(1) /**< (ACC_ACR) Hysteresis Selection Position */ +#define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */ +#define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)) +#define ACC_ACR_Msk _U_(0x00000007) /**< (ACC_ACR) Register Mask */ + + +/* -------- ACC_WPMR : (ACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN_Pos _U_(0) /**< (ACC_WPMR) Write Protection Enable Position */ +#define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */ +#define ACC_WPMR_WPEN(value) (ACC_WPMR_WPEN_Msk & ((value) << ACC_WPMR_WPEN_Pos)) +#define ACC_WPMR_WPKEY_Pos _U_(8) /**< (ACC_WPMR) Write Protection Key Position */ +#define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */ +#define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)) +#define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */ + + +/* -------- ACC_WPSR : (ACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS_Pos _U_(0) /**< (ACC_WPSR) Write Protection Violation Status Position */ +#define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */ +#define ACC_WPSR_WPVS(value) (ACC_WPSR_WPVS_Msk & ((value) << ACC_WPSR_WPVS_Pos)) +#define ACC_WPSR_Msk _U_(0x00000001) /**< (ACC_WPSR) Register Mask */ + + +/** \brief ACC register offsets definitions */ +#define ACC_CR_REG_OFST (0x00) /**< (ACC_CR) Control Register Offset */ +#define ACC_MR_REG_OFST (0x04) /**< (ACC_MR) Mode Register Offset */ +#define ACC_IER_REG_OFST (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */ +#define ACC_IDR_REG_OFST (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */ +#define ACC_IMR_REG_OFST (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */ +#define ACC_ISR_REG_OFST (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */ +#define ACC_ACR_REG_OFST (0x94) /**< (ACC_ACR) Analog Control Register Offset */ +#define ACC_WPMR_REG_OFST (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */ +#define ACC_WPSR_REG_OFST (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ACC register API structure */ +typedef struct +{ + __O uint32_t ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[0x1C]; + __O uint32_t ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x60]; + __IO uint32_t ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */ + __I uint8_t Reserved3[0x4C]; + __IO uint32_t ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} acc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ACC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/aes.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/aes.h new file mode 100644 index 00000000..d9173b85 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/aes.h @@ -0,0 +1,298 @@ +/** + * \brief Component description for AES + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_AES_COMPONENT_H_ +#define _SAME70_AES_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AES */ +/* ************************************************************************** */ + +/* -------- AES_CR : (AES Offset: 0x00) ( /W 32) Control Register -------- */ +#define AES_CR_START_Pos _U_(0) /**< (AES_CR) Start Processing Position */ +#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */ +#define AES_CR_START(value) (AES_CR_START_Msk & ((value) << AES_CR_START_Pos)) +#define AES_CR_SWRST_Pos _U_(8) /**< (AES_CR) Software Reset Position */ +#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */ +#define AES_CR_SWRST(value) (AES_CR_SWRST_Msk & ((value) << AES_CR_SWRST_Pos)) +#define AES_CR_LOADSEED_Pos _U_(16) /**< (AES_CR) Random Number Generator Seed Loading Position */ +#define AES_CR_LOADSEED_Msk (_U_(0x1) << AES_CR_LOADSEED_Pos) /**< (AES_CR) Random Number Generator Seed Loading Mask */ +#define AES_CR_LOADSEED(value) (AES_CR_LOADSEED_Msk & ((value) << AES_CR_LOADSEED_Pos)) +#define AES_CR_Msk _U_(0x00010101) /**< (AES_CR) Register Mask */ + + +/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */ +#define AES_MR_CIPHER_Pos _U_(0) /**< (AES_MR) Processing Mode Position */ +#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */ +#define AES_MR_CIPHER(value) (AES_MR_CIPHER_Msk & ((value) << AES_MR_CIPHER_Pos)) +#define AES_MR_GTAGEN_Pos _U_(1) /**< (AES_MR) GCM Automatic Tag Generation Enable Position */ +#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */ +#define AES_MR_GTAGEN(value) (AES_MR_GTAGEN_Msk & ((value) << AES_MR_GTAGEN_Pos)) +#define AES_MR_DUALBUFF_Pos _U_(3) /**< (AES_MR) Dual Input Buffer Position */ +#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */ +#define AES_MR_DUALBUFF(value) (AES_MR_DUALBUFF_Msk & ((value) << AES_MR_DUALBUFF_Pos)) +#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ +#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */ +#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */ +#define AES_MR_PROCDLY_Pos _U_(4) /**< (AES_MR) Processing Delay Position */ +#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */ +#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)) +#define AES_MR_SMOD_Pos _U_(8) /**< (AES_MR) Start Mode Position */ +#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */ +#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)) +#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */ +#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */ +#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */ +#define AES_MR_KEYSIZE_Pos _U_(10) /**< (AES_MR) Key Size Position */ +#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */ +#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)) +#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */ +#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */ +#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */ +#define AES_MR_OPMOD_Pos _U_(12) /**< (AES_MR) Operating Mode Position */ +#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */ +#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)) +#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */ +#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */ +#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */ +#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */ +#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */ +#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */ +#define AES_MR_LOD_Pos _U_(15) /**< (AES_MR) Last Output Data Mode Position */ +#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */ +#define AES_MR_LOD(value) (AES_MR_LOD_Msk & ((value) << AES_MR_LOD_Pos)) +#define AES_MR_CFBS_Pos _U_(16) /**< (AES_MR) Cipher Feedback Data Size Position */ +#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */ +#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)) +#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */ +#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */ +#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */ +#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */ +#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */ +#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */ +#define AES_MR_CKEY_Pos _U_(20) /**< (AES_MR) Countermeasure Key Position */ +#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */ +#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)) +#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ +#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */ +#define AES_MR_Msk _U_(0x00F7FFFB) /**< (AES_MR) Register Mask */ + + +/* -------- AES_IER : (AES Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY_Pos _U_(0) /**< (AES_IER) Data Ready Interrupt Enable Position */ +#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */ +#define AES_IER_DATRDY(value) (AES_IER_DATRDY_Msk & ((value) << AES_IER_DATRDY_Pos)) +#define AES_IER_URAD_Pos _U_(8) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */ +#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */ +#define AES_IER_URAD(value) (AES_IER_URAD_Msk & ((value) << AES_IER_URAD_Pos)) +#define AES_IER_TAGRDY_Pos _U_(16) /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */ +#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */ +#define AES_IER_TAGRDY(value) (AES_IER_TAGRDY_Msk & ((value) << AES_IER_TAGRDY_Pos)) +#define AES_IER_Msk _U_(0x00010101) /**< (AES_IER) Register Mask */ + + +/* -------- AES_IDR : (AES Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY_Pos _U_(0) /**< (AES_IDR) Data Ready Interrupt Disable Position */ +#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */ +#define AES_IDR_DATRDY(value) (AES_IDR_DATRDY_Msk & ((value) << AES_IDR_DATRDY_Pos)) +#define AES_IDR_URAD_Pos _U_(8) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */ +#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */ +#define AES_IDR_URAD(value) (AES_IDR_URAD_Msk & ((value) << AES_IDR_URAD_Pos)) +#define AES_IDR_TAGRDY_Pos _U_(16) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */ +#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */ +#define AES_IDR_TAGRDY(value) (AES_IDR_TAGRDY_Msk & ((value) << AES_IDR_TAGRDY_Pos)) +#define AES_IDR_Msk _U_(0x00010101) /**< (AES_IDR) Register Mask */ + + +/* -------- AES_IMR : (AES Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY_Pos _U_(0) /**< (AES_IMR) Data Ready Interrupt Mask Position */ +#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */ +#define AES_IMR_DATRDY(value) (AES_IMR_DATRDY_Msk & ((value) << AES_IMR_DATRDY_Pos)) +#define AES_IMR_URAD_Pos _U_(8) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */ +#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */ +#define AES_IMR_URAD(value) (AES_IMR_URAD_Msk & ((value) << AES_IMR_URAD_Pos)) +#define AES_IMR_TAGRDY_Pos _U_(16) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */ +#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */ +#define AES_IMR_TAGRDY(value) (AES_IMR_TAGRDY_Msk & ((value) << AES_IMR_TAGRDY_Pos)) +#define AES_IMR_Msk _U_(0x00010101) /**< (AES_IMR) Register Mask */ + + +/* -------- AES_ISR : (AES Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY_Pos _U_(0) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */ +#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */ +#define AES_ISR_DATRDY(value) (AES_ISR_DATRDY_Msk & ((value) << AES_ISR_DATRDY_Pos)) +#define AES_ISR_URAD_Pos _U_(8) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAD(value) (AES_ISR_URAD_Msk & ((value) << AES_ISR_URAD_Pos)) +#define AES_ISR_URAT_Pos _U_(12) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */ +#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */ +#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos)) +#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */ +#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */ +#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */ +#define AES_ISR_TAGRDY_Pos _U_(16) /**< (AES_ISR) GCM Tag Ready Position */ +#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */ +#define AES_ISR_TAGRDY(value) (AES_ISR_TAGRDY_Msk & ((value) << AES_ISR_TAGRDY_Pos)) +#define AES_ISR_Msk _U_(0x0001F101) /**< (AES_ISR) Register Mask */ + + +/* -------- AES_KEYWR : (AES Offset: 0x20) ( /W 32) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos _U_(0) /**< (AES_KEYWR) Key Word Position */ +#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */ +#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)) +#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */ + + +/* -------- AES_IDATAR : (AES Offset: 0x40) ( /W 32) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos _U_(0) /**< (AES_IDATAR) Input Data Word Position */ +#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */ +#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)) +#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */ + + +/* -------- AES_ODATAR : (AES Offset: 0x50) ( R/ 32) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos _U_(0) /**< (AES_ODATAR) Output Data Position */ +#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */ +#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos)) +#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */ + + +/* -------- AES_IVR : (AES Offset: 0x60) ( /W 32) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos _U_(0) /**< (AES_IVR) Initialization Vector Position */ +#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */ +#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)) +#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */ + + +/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos _U_(0) /**< (AES_AADLENR) Additional Authenticated Data Length Position */ +#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */ +#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)) +#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */ + + +/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos _U_(0) /**< (AES_CLENR) Plaintext/Ciphertext Length Position */ +#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */ +#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)) +#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */ + + +/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos _U_(0) /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */ +#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */ +#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)) +#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */ + + +/* -------- AES_TAGR : (AES Offset: 0x88) ( R/ 32) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos _U_(0) /**< (AES_TAGR) GCM Authentication Tag x Position */ +#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */ +#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos)) +#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */ + + +/* -------- AES_CTRR : (AES Offset: 0x98) ( R/ 32) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos _U_(0) /**< (AES_CTRR) GCM Encryption Counter Position */ +#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */ +#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos)) +#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */ + + +/* -------- AES_GCMHR : (AES Offset: 0x9C) (R/W 32) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos _U_(0) /**< (AES_GCMHR) GCM H Word x Position */ +#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */ +#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)) +#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */ + + +/** \brief AES register offsets definitions */ +#define AES_CR_REG_OFST (0x00) /**< (AES_CR) Control Register Offset */ +#define AES_MR_REG_OFST (0x04) /**< (AES_MR) Mode Register Offset */ +#define AES_IER_REG_OFST (0x10) /**< (AES_IER) Interrupt Enable Register Offset */ +#define AES_IDR_REG_OFST (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */ +#define AES_IMR_REG_OFST (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */ +#define AES_ISR_REG_OFST (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */ +#define AES_KEYWR_REG_OFST (0x20) /**< (AES_KEYWR) Key Word Register Offset */ +#define AES_IDATAR_REG_OFST (0x40) /**< (AES_IDATAR) Input Data Register Offset */ +#define AES_ODATAR_REG_OFST (0x50) /**< (AES_ODATAR) Output Data Register Offset */ +#define AES_IVR_REG_OFST (0x60) /**< (AES_IVR) Initialization Vector Register Offset */ +#define AES_AADLENR_REG_OFST (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */ +#define AES_CLENR_REG_OFST (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */ +#define AES_GHASHR_REG_OFST (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register Offset */ +#define AES_TAGR_REG_OFST (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register Offset */ +#define AES_CTRR_REG_OFST (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */ +#define AES_GCMHR_REG_OFST (0x9C) /**< (AES_GCMHR) GCM H Word Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AES register API structure */ +typedef struct +{ + __O uint32_t AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint8_t Reserved1[0x08]; + __O uint32_t AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register */ +} aes_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_AES_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/afec.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/afec.h new file mode 100644 index 00000000..a9860084 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/afec.h @@ -0,0 +1,998 @@ +/** + * \brief Component description for AFEC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_AFEC_COMPONENT_H_ +#define _SAME70_AFEC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR AFEC */ +/* ************************************************************************** */ + +/* -------- AFEC_CR : (AFEC Offset: 0x00) ( /W 32) AFEC Control Register -------- */ +#define AFEC_CR_SWRST_Pos _U_(0) /**< (AFEC_CR) Software Reset Position */ +#define AFEC_CR_SWRST_Msk (_U_(0x1) << AFEC_CR_SWRST_Pos) /**< (AFEC_CR) Software Reset Mask */ +#define AFEC_CR_SWRST(value) (AFEC_CR_SWRST_Msk & ((value) << AFEC_CR_SWRST_Pos)) +#define AFEC_CR_START_Pos _U_(1) /**< (AFEC_CR) Start Conversion Position */ +#define AFEC_CR_START_Msk (_U_(0x1) << AFEC_CR_START_Pos) /**< (AFEC_CR) Start Conversion Mask */ +#define AFEC_CR_START(value) (AFEC_CR_START_Msk & ((value) << AFEC_CR_START_Pos)) +#define AFEC_CR_Msk _U_(0x00000003) /**< (AFEC_CR) Register Mask */ + + +/* -------- AFEC_MR : (AFEC Offset: 0x04) (R/W 32) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN_Pos _U_(0) /**< (AFEC_MR) Trigger Enable Position */ +#define AFEC_MR_TRGEN_Msk (_U_(0x1) << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Trigger Enable Mask */ +#define AFEC_MR_TRGEN(value) (AFEC_MR_TRGEN_Msk & ((value) << AFEC_MR_TRGEN_Pos)) +#define AFEC_MR_TRGEN_DIS_Val _U_(0x0) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN_Val _U_(0x1) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGEN_DIS (AFEC_MR_TRGEN_DIS_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. Position */ +#define AFEC_MR_TRGEN_EN (AFEC_MR_TRGEN_EN_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. Position */ +#define AFEC_MR_TRGSEL_Pos _U_(1) /**< (AFEC_MR) Trigger Selection Position */ +#define AFEC_MR_TRGSEL_Msk (_U_(0x7) << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Trigger Selection Mask */ +#define AFEC_MR_TRGSEL(value) (AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)) +#define AFEC_MR_TRGSEL_AFEC_TRIG0_Val _U_(0x0) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1_Val _U_(0x1) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2_Val _U_(0x2) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3_Val _U_(0x3) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4_Val _U_(0x4) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5_Val _U_(0x5) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6_Val _U_(0x6) /**< (AFEC_MR) Analog Comparator */ +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (AFEC_MR_TRGSEL_AFEC_TRIG0_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (AFEC_MR_TRGSEL_AFEC_TRIG1_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (AFEC_MR_TRGSEL_AFEC_TRIG2_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (AFEC_MR_TRGSEL_AFEC_TRIG3_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (AFEC_MR_TRGSEL_AFEC_TRIG4_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (AFEC_MR_TRGSEL_AFEC_TRIG5_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 Position */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (AFEC_MR_TRGSEL_AFEC_TRIG6_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Analog Comparator Position */ +#define AFEC_MR_SLEEP_Pos _U_(5) /**< (AFEC_MR) Sleep Mode Position */ +#define AFEC_MR_SLEEP_Msk (_U_(0x1) << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep Mode Mask */ +#define AFEC_MR_SLEEP(value) (AFEC_MR_SLEEP_Msk & ((value) << AFEC_MR_SLEEP_Pos)) +#define AFEC_MR_SLEEP_NORMAL_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP_Val _U_(0x1) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_SLEEP_NORMAL (AFEC_MR_SLEEP_NORMAL_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. Position */ +#define AFEC_MR_SLEEP_SLEEP (AFEC_MR_SLEEP_SLEEP_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. Position */ +#define AFEC_MR_FWUP_Pos _U_(6) /**< (AFEC_MR) Fast Wake-up Position */ +#define AFEC_MR_FWUP_Msk (_U_(0x1) << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast Wake-up Mask */ +#define AFEC_MR_FWUP(value) (AFEC_MR_FWUP_Msk & ((value) << AFEC_MR_FWUP_Pos)) +#define AFEC_MR_FWUP_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON_Val _U_(0x1) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FWUP_OFF (AFEC_MR_FWUP_OFF_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. Position */ +#define AFEC_MR_FWUP_ON (AFEC_MR_FWUP_ON_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. Position */ +#define AFEC_MR_FREERUN_Pos _U_(7) /**< (AFEC_MR) Free Run Mode Position */ +#define AFEC_MR_FREERUN_Msk (_U_(0x1) << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run Mode Mask */ +#define AFEC_MR_FREERUN(value) (AFEC_MR_FREERUN_Msk & ((value) << AFEC_MR_FREERUN_Pos)) +#define AFEC_MR_FREERUN_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON_Val _U_(0x1) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_FREERUN_OFF (AFEC_MR_FREERUN_OFF_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Normal mode Position */ +#define AFEC_MR_FREERUN_ON (AFEC_MR_FREERUN_ON_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. Position */ +#define AFEC_MR_PRESCAL_Pos _U_(8) /**< (AFEC_MR) Prescaler Rate Selection Position */ +#define AFEC_MR_PRESCAL_Msk (_U_(0xFF) << AFEC_MR_PRESCAL_Pos) /**< (AFEC_MR) Prescaler Rate Selection Mask */ +#define AFEC_MR_PRESCAL(value) (AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)) +#define AFEC_MR_STARTUP_Pos _U_(16) /**< (AFEC_MR) Start-up Time Position */ +#define AFEC_MR_STARTUP_Msk (_U_(0xF) << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) Start-up Time Mask */ +#define AFEC_MR_STARTUP(value) (AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)) +#define AFEC_MR_STARTUP_SUT0_Val _U_(0x0) /**< (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8_Val _U_(0x1) /**< (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16_Val _U_(0x2) /**< (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24_Val _U_(0x3) /**< (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64_Val _U_(0x4) /**< (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80_Val _U_(0x5) /**< (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96_Val _U_(0x6) /**< (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112_Val _U_(0x7) /**< (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512_Val _U_(0x8) /**< (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576_Val _U_(0x9) /**< (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640_Val _U_(0xA) /**< (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704_Val _U_(0xB) /**< (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768_Val _U_(0xC) /**< (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832_Val _U_(0xD) /**< (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896_Val _U_(0xE) /**< (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960_Val _U_(0xF) /**< (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT0 (AFEC_MR_STARTUP_SUT0_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 0 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT8 (AFEC_MR_STARTUP_SUT8_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 8 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT16 (AFEC_MR_STARTUP_SUT16_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 16 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT24 (AFEC_MR_STARTUP_SUT24_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 24 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT64 (AFEC_MR_STARTUP_SUT64_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 64 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT80 (AFEC_MR_STARTUP_SUT80_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 80 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT96 (AFEC_MR_STARTUP_SUT96_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 96 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT112 (AFEC_MR_STARTUP_SUT112_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 112 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT512 (AFEC_MR_STARTUP_SUT512_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 512 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT576 (AFEC_MR_STARTUP_SUT576_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 576 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT640 (AFEC_MR_STARTUP_SUT640_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 640 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT704 (AFEC_MR_STARTUP_SUT704_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 704 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT768 (AFEC_MR_STARTUP_SUT768_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 768 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT832 (AFEC_MR_STARTUP_SUT832_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 832 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT896 (AFEC_MR_STARTUP_SUT896_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 896 periods of AFE clock Position */ +#define AFEC_MR_STARTUP_SUT960 (AFEC_MR_STARTUP_SUT960_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 960 periods of AFE clock Position */ +#define AFEC_MR_ONE_Pos _U_(23) /**< (AFEC_MR) One Position */ +#define AFEC_MR_ONE_Msk (_U_(0x1) << AFEC_MR_ONE_Pos) /**< (AFEC_MR) One Mask */ +#define AFEC_MR_ONE(value) (AFEC_MR_ONE_Msk & ((value) << AFEC_MR_ONE_Pos)) +#define AFEC_MR_TRACKTIM_Pos _U_(24) /**< (AFEC_MR) Tracking Time Position */ +#define AFEC_MR_TRACKTIM_Msk (_U_(0xF) << AFEC_MR_TRACKTIM_Pos) /**< (AFEC_MR) Tracking Time Mask */ +#define AFEC_MR_TRACKTIM(value) (AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)) +#define AFEC_MR_TRANSFER_Pos _U_(28) /**< (AFEC_MR) Transfer Period Position */ +#define AFEC_MR_TRANSFER_Msk (_U_(0x3) << AFEC_MR_TRANSFER_Pos) /**< (AFEC_MR) Transfer Period Mask */ +#define AFEC_MR_TRANSFER(value) (AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)) +#define AFEC_MR_USEQ_Pos _U_(31) /**< (AFEC_MR) User Sequence Enable Position */ +#define AFEC_MR_USEQ_Msk (_U_(0x1) << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence Enable Mask */ +#define AFEC_MR_USEQ(value) (AFEC_MR_USEQ_Msk & ((value) << AFEC_MR_USEQ_Pos)) +#define AFEC_MR_USEQ_NUM_ORDER_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER_Val _U_(0x1) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +#define AFEC_MR_USEQ_NUM_ORDER (AFEC_MR_USEQ_NUM_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. Position */ +#define AFEC_MR_USEQ_REG_ORDER (AFEC_MR_USEQ_REG_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. Position */ +#define AFEC_MR_Msk _U_(0xBF8FFFEF) /**< (AFEC_MR) Register Mask */ + + +/* -------- AFEC_EMR : (AFEC Offset: 0x08) (R/W 32) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos _U_(0) /**< (AFEC_EMR) Comparison Mode Position */ +#define AFEC_EMR_CMPMODE_Msk (_U_(0x3) << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Comparison Mode Mask */ +#define AFEC_EMR_CMPMODE(value) (AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)) +#define AFEC_EMR_CMPMODE_LOW_Val _U_(0x0) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH_Val _U_(0x1) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN_Val _U_(0x2) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT_Val _U_(0x3) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPMODE_LOW (AFEC_EMR_CMPMODE_LOW_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_HIGH (AFEC_EMR_CMPMODE_HIGH_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_EMR_CMPMODE_IN (AFEC_EMR_CMPMODE_IN_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_EMR_CMPMODE_OUT (AFEC_EMR_CMPMODE_OUT_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_EMR_CMPSEL_Pos _U_(3) /**< (AFEC_EMR) Comparison Selected Channel Position */ +#define AFEC_EMR_CMPSEL_Msk (_U_(0x1F) << AFEC_EMR_CMPSEL_Pos) /**< (AFEC_EMR) Comparison Selected Channel Mask */ +#define AFEC_EMR_CMPSEL(value) (AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)) +#define AFEC_EMR_CMPALL_Pos _U_(9) /**< (AFEC_EMR) Compare All Channels Position */ +#define AFEC_EMR_CMPALL_Msk (_U_(0x1) << AFEC_EMR_CMPALL_Pos) /**< (AFEC_EMR) Compare All Channels Mask */ +#define AFEC_EMR_CMPALL(value) (AFEC_EMR_CMPALL_Msk & ((value) << AFEC_EMR_CMPALL_Pos)) +#define AFEC_EMR_CMPFILTER_Pos _U_(12) /**< (AFEC_EMR) Compare Event Filtering Position */ +#define AFEC_EMR_CMPFILTER_Msk (_U_(0x3) << AFEC_EMR_CMPFILTER_Pos) /**< (AFEC_EMR) Compare Event Filtering Mask */ +#define AFEC_EMR_CMPFILTER(value) (AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)) +#define AFEC_EMR_RES_Pos _U_(16) /**< (AFEC_EMR) Resolution Position */ +#define AFEC_EMR_RES_Msk (_U_(0x7) << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) Resolution Mask */ +#define AFEC_EMR_RES(value) (AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)) +#define AFEC_EMR_RES_NO_AVERAGE_Val _U_(0x0) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4_Val _U_(0x2) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16_Val _U_(0x3) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64_Val _U_(0x4) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256_Val _U_(0x5) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_RES_NO_AVERAGE (AFEC_EMR_RES_NO_AVERAGE_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). Position */ +#define AFEC_EMR_RES_OSR4 (AFEC_EMR_RES_OSR4_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). Position */ +#define AFEC_EMR_RES_OSR16 (AFEC_EMR_RES_OSR16_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). Position */ +#define AFEC_EMR_RES_OSR64 (AFEC_EMR_RES_OSR64_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). Position */ +#define AFEC_EMR_RES_OSR256 (AFEC_EMR_RES_OSR256_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). Position */ +#define AFEC_EMR_TAG_Pos _U_(24) /**< (AFEC_EMR) TAG of the AFEC_LDCR Position */ +#define AFEC_EMR_TAG_Msk (_U_(0x1) << AFEC_EMR_TAG_Pos) /**< (AFEC_EMR) TAG of the AFEC_LDCR Mask */ +#define AFEC_EMR_TAG(value) (AFEC_EMR_TAG_Msk & ((value) << AFEC_EMR_TAG_Pos)) +#define AFEC_EMR_STM_Pos _U_(25) /**< (AFEC_EMR) Single Trigger Mode Position */ +#define AFEC_EMR_STM_Msk (_U_(0x1) << AFEC_EMR_STM_Pos) /**< (AFEC_EMR) Single Trigger Mode Mask */ +#define AFEC_EMR_STM(value) (AFEC_EMR_STM_Msk & ((value) << AFEC_EMR_STM_Pos)) +#define AFEC_EMR_SIGNMODE_Pos _U_(28) /**< (AFEC_EMR) Sign Mode Position */ +#define AFEC_EMR_SIGNMODE_Msk (_U_(0x3) << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Sign Mode Mask */ +#define AFEC_EMR_SIGNMODE(value) (AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val _U_(0x0) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val _U_(0x1) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val _U_(0x2) /**< (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED_Val _U_(0x3) /**< (AFEC_EMR) All channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. Position */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Unsigned conversions. Position */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (AFEC_EMR_SIGNMODE_ALL_SIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Signed conversions. Position */ +#define AFEC_EMR_Msk _U_(0x330732FB) /**< (AFEC_EMR) Register Mask */ + + +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) (R/W 32) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos _U_(0) /**< (AFEC_SEQ1R) User Sequence Number 0 Position */ +#define AFEC_SEQ1R_USCH0_Msk (_U_(0xF) << AFEC_SEQ1R_USCH0_Pos) /**< (AFEC_SEQ1R) User Sequence Number 0 Mask */ +#define AFEC_SEQ1R_USCH0(value) (AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)) +#define AFEC_SEQ1R_USCH1_Pos _U_(4) /**< (AFEC_SEQ1R) User Sequence Number 1 Position */ +#define AFEC_SEQ1R_USCH1_Msk (_U_(0xF) << AFEC_SEQ1R_USCH1_Pos) /**< (AFEC_SEQ1R) User Sequence Number 1 Mask */ +#define AFEC_SEQ1R_USCH1(value) (AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)) +#define AFEC_SEQ1R_USCH2_Pos _U_(8) /**< (AFEC_SEQ1R) User Sequence Number 2 Position */ +#define AFEC_SEQ1R_USCH2_Msk (_U_(0xF) << AFEC_SEQ1R_USCH2_Pos) /**< (AFEC_SEQ1R) User Sequence Number 2 Mask */ +#define AFEC_SEQ1R_USCH2(value) (AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)) +#define AFEC_SEQ1R_USCH3_Pos _U_(12) /**< (AFEC_SEQ1R) User Sequence Number 3 Position */ +#define AFEC_SEQ1R_USCH3_Msk (_U_(0xF) << AFEC_SEQ1R_USCH3_Pos) /**< (AFEC_SEQ1R) User Sequence Number 3 Mask */ +#define AFEC_SEQ1R_USCH3(value) (AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)) +#define AFEC_SEQ1R_USCH4_Pos _U_(16) /**< (AFEC_SEQ1R) User Sequence Number 4 Position */ +#define AFEC_SEQ1R_USCH4_Msk (_U_(0xF) << AFEC_SEQ1R_USCH4_Pos) /**< (AFEC_SEQ1R) User Sequence Number 4 Mask */ +#define AFEC_SEQ1R_USCH4(value) (AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)) +#define AFEC_SEQ1R_USCH5_Pos _U_(20) /**< (AFEC_SEQ1R) User Sequence Number 5 Position */ +#define AFEC_SEQ1R_USCH5_Msk (_U_(0xF) << AFEC_SEQ1R_USCH5_Pos) /**< (AFEC_SEQ1R) User Sequence Number 5 Mask */ +#define AFEC_SEQ1R_USCH5(value) (AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)) +#define AFEC_SEQ1R_USCH6_Pos _U_(24) /**< (AFEC_SEQ1R) User Sequence Number 6 Position */ +#define AFEC_SEQ1R_USCH6_Msk (_U_(0xF) << AFEC_SEQ1R_USCH6_Pos) /**< (AFEC_SEQ1R) User Sequence Number 6 Mask */ +#define AFEC_SEQ1R_USCH6(value) (AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)) +#define AFEC_SEQ1R_USCH7_Pos _U_(28) /**< (AFEC_SEQ1R) User Sequence Number 7 Position */ +#define AFEC_SEQ1R_USCH7_Msk (_U_(0xF) << AFEC_SEQ1R_USCH7_Pos) /**< (AFEC_SEQ1R) User Sequence Number 7 Mask */ +#define AFEC_SEQ1R_USCH7(value) (AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)) +#define AFEC_SEQ1R_Msk _U_(0xFFFFFFFF) /**< (AFEC_SEQ1R) Register Mask */ + + +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) (R/W 32) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos _U_(0) /**< (AFEC_SEQ2R) User Sequence Number 8 Position */ +#define AFEC_SEQ2R_USCH8_Msk (_U_(0xF) << AFEC_SEQ2R_USCH8_Pos) /**< (AFEC_SEQ2R) User Sequence Number 8 Mask */ +#define AFEC_SEQ2R_USCH8(value) (AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)) +#define AFEC_SEQ2R_USCH9_Pos _U_(4) /**< (AFEC_SEQ2R) User Sequence Number 9 Position */ +#define AFEC_SEQ2R_USCH9_Msk (_U_(0xF) << AFEC_SEQ2R_USCH9_Pos) /**< (AFEC_SEQ2R) User Sequence Number 9 Mask */ +#define AFEC_SEQ2R_USCH9(value) (AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)) +#define AFEC_SEQ2R_USCH10_Pos _U_(8) /**< (AFEC_SEQ2R) User Sequence Number 10 Position */ +#define AFEC_SEQ2R_USCH10_Msk (_U_(0xF) << AFEC_SEQ2R_USCH10_Pos) /**< (AFEC_SEQ2R) User Sequence Number 10 Mask */ +#define AFEC_SEQ2R_USCH10(value) (AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)) +#define AFEC_SEQ2R_USCH11_Pos _U_(12) /**< (AFEC_SEQ2R) User Sequence Number 11 Position */ +#define AFEC_SEQ2R_USCH11_Msk (_U_(0xF) << AFEC_SEQ2R_USCH11_Pos) /**< (AFEC_SEQ2R) User Sequence Number 11 Mask */ +#define AFEC_SEQ2R_USCH11(value) (AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)) +#define AFEC_SEQ2R_Msk _U_(0x0000FFFF) /**< (AFEC_SEQ2R) Register Mask */ + + +/* -------- AFEC_CHER : (AFEC Offset: 0x14) ( /W 32) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0_Pos _U_(0) /**< (AFEC_CHER) Channel 0 Enable Position */ +#define AFEC_CHER_CH0_Msk (_U_(0x1) << AFEC_CHER_CH0_Pos) /**< (AFEC_CHER) Channel 0 Enable Mask */ +#define AFEC_CHER_CH0(value) (AFEC_CHER_CH0_Msk & ((value) << AFEC_CHER_CH0_Pos)) +#define AFEC_CHER_CH1_Pos _U_(1) /**< (AFEC_CHER) Channel 1 Enable Position */ +#define AFEC_CHER_CH1_Msk (_U_(0x1) << AFEC_CHER_CH1_Pos) /**< (AFEC_CHER) Channel 1 Enable Mask */ +#define AFEC_CHER_CH1(value) (AFEC_CHER_CH1_Msk & ((value) << AFEC_CHER_CH1_Pos)) +#define AFEC_CHER_CH2_Pos _U_(2) /**< (AFEC_CHER) Channel 2 Enable Position */ +#define AFEC_CHER_CH2_Msk (_U_(0x1) << AFEC_CHER_CH2_Pos) /**< (AFEC_CHER) Channel 2 Enable Mask */ +#define AFEC_CHER_CH2(value) (AFEC_CHER_CH2_Msk & ((value) << AFEC_CHER_CH2_Pos)) +#define AFEC_CHER_CH3_Pos _U_(3) /**< (AFEC_CHER) Channel 3 Enable Position */ +#define AFEC_CHER_CH3_Msk (_U_(0x1) << AFEC_CHER_CH3_Pos) /**< (AFEC_CHER) Channel 3 Enable Mask */ +#define AFEC_CHER_CH3(value) (AFEC_CHER_CH3_Msk & ((value) << AFEC_CHER_CH3_Pos)) +#define AFEC_CHER_CH4_Pos _U_(4) /**< (AFEC_CHER) Channel 4 Enable Position */ +#define AFEC_CHER_CH4_Msk (_U_(0x1) << AFEC_CHER_CH4_Pos) /**< (AFEC_CHER) Channel 4 Enable Mask */ +#define AFEC_CHER_CH4(value) (AFEC_CHER_CH4_Msk & ((value) << AFEC_CHER_CH4_Pos)) +#define AFEC_CHER_CH5_Pos _U_(5) /**< (AFEC_CHER) Channel 5 Enable Position */ +#define AFEC_CHER_CH5_Msk (_U_(0x1) << AFEC_CHER_CH5_Pos) /**< (AFEC_CHER) Channel 5 Enable Mask */ +#define AFEC_CHER_CH5(value) (AFEC_CHER_CH5_Msk & ((value) << AFEC_CHER_CH5_Pos)) +#define AFEC_CHER_CH6_Pos _U_(6) /**< (AFEC_CHER) Channel 6 Enable Position */ +#define AFEC_CHER_CH6_Msk (_U_(0x1) << AFEC_CHER_CH6_Pos) /**< (AFEC_CHER) Channel 6 Enable Mask */ +#define AFEC_CHER_CH6(value) (AFEC_CHER_CH6_Msk & ((value) << AFEC_CHER_CH6_Pos)) +#define AFEC_CHER_CH7_Pos _U_(7) /**< (AFEC_CHER) Channel 7 Enable Position */ +#define AFEC_CHER_CH7_Msk (_U_(0x1) << AFEC_CHER_CH7_Pos) /**< (AFEC_CHER) Channel 7 Enable Mask */ +#define AFEC_CHER_CH7(value) (AFEC_CHER_CH7_Msk & ((value) << AFEC_CHER_CH7_Pos)) +#define AFEC_CHER_CH8_Pos _U_(8) /**< (AFEC_CHER) Channel 8 Enable Position */ +#define AFEC_CHER_CH8_Msk (_U_(0x1) << AFEC_CHER_CH8_Pos) /**< (AFEC_CHER) Channel 8 Enable Mask */ +#define AFEC_CHER_CH8(value) (AFEC_CHER_CH8_Msk & ((value) << AFEC_CHER_CH8_Pos)) +#define AFEC_CHER_CH9_Pos _U_(9) /**< (AFEC_CHER) Channel 9 Enable Position */ +#define AFEC_CHER_CH9_Msk (_U_(0x1) << AFEC_CHER_CH9_Pos) /**< (AFEC_CHER) Channel 9 Enable Mask */ +#define AFEC_CHER_CH9(value) (AFEC_CHER_CH9_Msk & ((value) << AFEC_CHER_CH9_Pos)) +#define AFEC_CHER_CH10_Pos _U_(10) /**< (AFEC_CHER) Channel 10 Enable Position */ +#define AFEC_CHER_CH10_Msk (_U_(0x1) << AFEC_CHER_CH10_Pos) /**< (AFEC_CHER) Channel 10 Enable Mask */ +#define AFEC_CHER_CH10(value) (AFEC_CHER_CH10_Msk & ((value) << AFEC_CHER_CH10_Pos)) +#define AFEC_CHER_CH11_Pos _U_(11) /**< (AFEC_CHER) Channel 11 Enable Position */ +#define AFEC_CHER_CH11_Msk (_U_(0x1) << AFEC_CHER_CH11_Pos) /**< (AFEC_CHER) Channel 11 Enable Mask */ +#define AFEC_CHER_CH11(value) (AFEC_CHER_CH11_Msk & ((value) << AFEC_CHER_CH11_Pos)) +#define AFEC_CHER_Msk _U_(0x00000FFF) /**< (AFEC_CHER) Register Mask */ + +#define AFEC_CHER_CH_Pos _U_(0) /**< (AFEC_CHER Position) Channel xx Enable */ +#define AFEC_CHER_CH_Msk (_U_(0xFFF) << AFEC_CHER_CH_Pos) /**< (AFEC_CHER Mask) CH */ +#define AFEC_CHER_CH(value) (AFEC_CHER_CH_Msk & ((value) << AFEC_CHER_CH_Pos)) + +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) ( /W 32) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0_Pos _U_(0) /**< (AFEC_CHDR) Channel 0 Disable Position */ +#define AFEC_CHDR_CH0_Msk (_U_(0x1) << AFEC_CHDR_CH0_Pos) /**< (AFEC_CHDR) Channel 0 Disable Mask */ +#define AFEC_CHDR_CH0(value) (AFEC_CHDR_CH0_Msk & ((value) << AFEC_CHDR_CH0_Pos)) +#define AFEC_CHDR_CH1_Pos _U_(1) /**< (AFEC_CHDR) Channel 1 Disable Position */ +#define AFEC_CHDR_CH1_Msk (_U_(0x1) << AFEC_CHDR_CH1_Pos) /**< (AFEC_CHDR) Channel 1 Disable Mask */ +#define AFEC_CHDR_CH1(value) (AFEC_CHDR_CH1_Msk & ((value) << AFEC_CHDR_CH1_Pos)) +#define AFEC_CHDR_CH2_Pos _U_(2) /**< (AFEC_CHDR) Channel 2 Disable Position */ +#define AFEC_CHDR_CH2_Msk (_U_(0x1) << AFEC_CHDR_CH2_Pos) /**< (AFEC_CHDR) Channel 2 Disable Mask */ +#define AFEC_CHDR_CH2(value) (AFEC_CHDR_CH2_Msk & ((value) << AFEC_CHDR_CH2_Pos)) +#define AFEC_CHDR_CH3_Pos _U_(3) /**< (AFEC_CHDR) Channel 3 Disable Position */ +#define AFEC_CHDR_CH3_Msk (_U_(0x1) << AFEC_CHDR_CH3_Pos) /**< (AFEC_CHDR) Channel 3 Disable Mask */ +#define AFEC_CHDR_CH3(value) (AFEC_CHDR_CH3_Msk & ((value) << AFEC_CHDR_CH3_Pos)) +#define AFEC_CHDR_CH4_Pos _U_(4) /**< (AFEC_CHDR) Channel 4 Disable Position */ +#define AFEC_CHDR_CH4_Msk (_U_(0x1) << AFEC_CHDR_CH4_Pos) /**< (AFEC_CHDR) Channel 4 Disable Mask */ +#define AFEC_CHDR_CH4(value) (AFEC_CHDR_CH4_Msk & ((value) << AFEC_CHDR_CH4_Pos)) +#define AFEC_CHDR_CH5_Pos _U_(5) /**< (AFEC_CHDR) Channel 5 Disable Position */ +#define AFEC_CHDR_CH5_Msk (_U_(0x1) << AFEC_CHDR_CH5_Pos) /**< (AFEC_CHDR) Channel 5 Disable Mask */ +#define AFEC_CHDR_CH5(value) (AFEC_CHDR_CH5_Msk & ((value) << AFEC_CHDR_CH5_Pos)) +#define AFEC_CHDR_CH6_Pos _U_(6) /**< (AFEC_CHDR) Channel 6 Disable Position */ +#define AFEC_CHDR_CH6_Msk (_U_(0x1) << AFEC_CHDR_CH6_Pos) /**< (AFEC_CHDR) Channel 6 Disable Mask */ +#define AFEC_CHDR_CH6(value) (AFEC_CHDR_CH6_Msk & ((value) << AFEC_CHDR_CH6_Pos)) +#define AFEC_CHDR_CH7_Pos _U_(7) /**< (AFEC_CHDR) Channel 7 Disable Position */ +#define AFEC_CHDR_CH7_Msk (_U_(0x1) << AFEC_CHDR_CH7_Pos) /**< (AFEC_CHDR) Channel 7 Disable Mask */ +#define AFEC_CHDR_CH7(value) (AFEC_CHDR_CH7_Msk & ((value) << AFEC_CHDR_CH7_Pos)) +#define AFEC_CHDR_CH8_Pos _U_(8) /**< (AFEC_CHDR) Channel 8 Disable Position */ +#define AFEC_CHDR_CH8_Msk (_U_(0x1) << AFEC_CHDR_CH8_Pos) /**< (AFEC_CHDR) Channel 8 Disable Mask */ +#define AFEC_CHDR_CH8(value) (AFEC_CHDR_CH8_Msk & ((value) << AFEC_CHDR_CH8_Pos)) +#define AFEC_CHDR_CH9_Pos _U_(9) /**< (AFEC_CHDR) Channel 9 Disable Position */ +#define AFEC_CHDR_CH9_Msk (_U_(0x1) << AFEC_CHDR_CH9_Pos) /**< (AFEC_CHDR) Channel 9 Disable Mask */ +#define AFEC_CHDR_CH9(value) (AFEC_CHDR_CH9_Msk & ((value) << AFEC_CHDR_CH9_Pos)) +#define AFEC_CHDR_CH10_Pos _U_(10) /**< (AFEC_CHDR) Channel 10 Disable Position */ +#define AFEC_CHDR_CH10_Msk (_U_(0x1) << AFEC_CHDR_CH10_Pos) /**< (AFEC_CHDR) Channel 10 Disable Mask */ +#define AFEC_CHDR_CH10(value) (AFEC_CHDR_CH10_Msk & ((value) << AFEC_CHDR_CH10_Pos)) +#define AFEC_CHDR_CH11_Pos _U_(11) /**< (AFEC_CHDR) Channel 11 Disable Position */ +#define AFEC_CHDR_CH11_Msk (_U_(0x1) << AFEC_CHDR_CH11_Pos) /**< (AFEC_CHDR) Channel 11 Disable Mask */ +#define AFEC_CHDR_CH11(value) (AFEC_CHDR_CH11_Msk & ((value) << AFEC_CHDR_CH11_Pos)) +#define AFEC_CHDR_Msk _U_(0x00000FFF) /**< (AFEC_CHDR) Register Mask */ + +#define AFEC_CHDR_CH_Pos _U_(0) /**< (AFEC_CHDR Position) Channel xx Disable */ +#define AFEC_CHDR_CH_Msk (_U_(0xFFF) << AFEC_CHDR_CH_Pos) /**< (AFEC_CHDR Mask) CH */ +#define AFEC_CHDR_CH(value) (AFEC_CHDR_CH_Msk & ((value) << AFEC_CHDR_CH_Pos)) + +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) ( R/ 32) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0_Pos _U_(0) /**< (AFEC_CHSR) Channel 0 Status Position */ +#define AFEC_CHSR_CH0_Msk (_U_(0x1) << AFEC_CHSR_CH0_Pos) /**< (AFEC_CHSR) Channel 0 Status Mask */ +#define AFEC_CHSR_CH0(value) (AFEC_CHSR_CH0_Msk & ((value) << AFEC_CHSR_CH0_Pos)) +#define AFEC_CHSR_CH1_Pos _U_(1) /**< (AFEC_CHSR) Channel 1 Status Position */ +#define AFEC_CHSR_CH1_Msk (_U_(0x1) << AFEC_CHSR_CH1_Pos) /**< (AFEC_CHSR) Channel 1 Status Mask */ +#define AFEC_CHSR_CH1(value) (AFEC_CHSR_CH1_Msk & ((value) << AFEC_CHSR_CH1_Pos)) +#define AFEC_CHSR_CH2_Pos _U_(2) /**< (AFEC_CHSR) Channel 2 Status Position */ +#define AFEC_CHSR_CH2_Msk (_U_(0x1) << AFEC_CHSR_CH2_Pos) /**< (AFEC_CHSR) Channel 2 Status Mask */ +#define AFEC_CHSR_CH2(value) (AFEC_CHSR_CH2_Msk & ((value) << AFEC_CHSR_CH2_Pos)) +#define AFEC_CHSR_CH3_Pos _U_(3) /**< (AFEC_CHSR) Channel 3 Status Position */ +#define AFEC_CHSR_CH3_Msk (_U_(0x1) << AFEC_CHSR_CH3_Pos) /**< (AFEC_CHSR) Channel 3 Status Mask */ +#define AFEC_CHSR_CH3(value) (AFEC_CHSR_CH3_Msk & ((value) << AFEC_CHSR_CH3_Pos)) +#define AFEC_CHSR_CH4_Pos _U_(4) /**< (AFEC_CHSR) Channel 4 Status Position */ +#define AFEC_CHSR_CH4_Msk (_U_(0x1) << AFEC_CHSR_CH4_Pos) /**< (AFEC_CHSR) Channel 4 Status Mask */ +#define AFEC_CHSR_CH4(value) (AFEC_CHSR_CH4_Msk & ((value) << AFEC_CHSR_CH4_Pos)) +#define AFEC_CHSR_CH5_Pos _U_(5) /**< (AFEC_CHSR) Channel 5 Status Position */ +#define AFEC_CHSR_CH5_Msk (_U_(0x1) << AFEC_CHSR_CH5_Pos) /**< (AFEC_CHSR) Channel 5 Status Mask */ +#define AFEC_CHSR_CH5(value) (AFEC_CHSR_CH5_Msk & ((value) << AFEC_CHSR_CH5_Pos)) +#define AFEC_CHSR_CH6_Pos _U_(6) /**< (AFEC_CHSR) Channel 6 Status Position */ +#define AFEC_CHSR_CH6_Msk (_U_(0x1) << AFEC_CHSR_CH6_Pos) /**< (AFEC_CHSR) Channel 6 Status Mask */ +#define AFEC_CHSR_CH6(value) (AFEC_CHSR_CH6_Msk & ((value) << AFEC_CHSR_CH6_Pos)) +#define AFEC_CHSR_CH7_Pos _U_(7) /**< (AFEC_CHSR) Channel 7 Status Position */ +#define AFEC_CHSR_CH7_Msk (_U_(0x1) << AFEC_CHSR_CH7_Pos) /**< (AFEC_CHSR) Channel 7 Status Mask */ +#define AFEC_CHSR_CH7(value) (AFEC_CHSR_CH7_Msk & ((value) << AFEC_CHSR_CH7_Pos)) +#define AFEC_CHSR_CH8_Pos _U_(8) /**< (AFEC_CHSR) Channel 8 Status Position */ +#define AFEC_CHSR_CH8_Msk (_U_(0x1) << AFEC_CHSR_CH8_Pos) /**< (AFEC_CHSR) Channel 8 Status Mask */ +#define AFEC_CHSR_CH8(value) (AFEC_CHSR_CH8_Msk & ((value) << AFEC_CHSR_CH8_Pos)) +#define AFEC_CHSR_CH9_Pos _U_(9) /**< (AFEC_CHSR) Channel 9 Status Position */ +#define AFEC_CHSR_CH9_Msk (_U_(0x1) << AFEC_CHSR_CH9_Pos) /**< (AFEC_CHSR) Channel 9 Status Mask */ +#define AFEC_CHSR_CH9(value) (AFEC_CHSR_CH9_Msk & ((value) << AFEC_CHSR_CH9_Pos)) +#define AFEC_CHSR_CH10_Pos _U_(10) /**< (AFEC_CHSR) Channel 10 Status Position */ +#define AFEC_CHSR_CH10_Msk (_U_(0x1) << AFEC_CHSR_CH10_Pos) /**< (AFEC_CHSR) Channel 10 Status Mask */ +#define AFEC_CHSR_CH10(value) (AFEC_CHSR_CH10_Msk & ((value) << AFEC_CHSR_CH10_Pos)) +#define AFEC_CHSR_CH11_Pos _U_(11) /**< (AFEC_CHSR) Channel 11 Status Position */ +#define AFEC_CHSR_CH11_Msk (_U_(0x1) << AFEC_CHSR_CH11_Pos) /**< (AFEC_CHSR) Channel 11 Status Mask */ +#define AFEC_CHSR_CH11(value) (AFEC_CHSR_CH11_Msk & ((value) << AFEC_CHSR_CH11_Pos)) +#define AFEC_CHSR_Msk _U_(0x00000FFF) /**< (AFEC_CHSR) Register Mask */ + +#define AFEC_CHSR_CH_Pos _U_(0) /**< (AFEC_CHSR Position) Channel xx Status */ +#define AFEC_CHSR_CH_Msk (_U_(0xFFF) << AFEC_CHSR_CH_Pos) /**< (AFEC_CHSR Mask) CH */ +#define AFEC_CHSR_CH(value) (AFEC_CHSR_CH_Msk & ((value) << AFEC_CHSR_CH_Pos)) + +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) ( R/ 32) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos _U_(0) /**< (AFEC_LCDR) Last Data Converted Position */ +#define AFEC_LCDR_LDATA_Msk (_U_(0xFFFF) << AFEC_LCDR_LDATA_Pos) /**< (AFEC_LCDR) Last Data Converted Mask */ +#define AFEC_LCDR_LDATA(value) (AFEC_LCDR_LDATA_Msk & ((value) << AFEC_LCDR_LDATA_Pos)) +#define AFEC_LCDR_CHNB_Pos _U_(24) /**< (AFEC_LCDR) Channel Number Position */ +#define AFEC_LCDR_CHNB_Msk (_U_(0xF) << AFEC_LCDR_CHNB_Pos) /**< (AFEC_LCDR) Channel Number Mask */ +#define AFEC_LCDR_CHNB(value) (AFEC_LCDR_CHNB_Msk & ((value) << AFEC_LCDR_CHNB_Pos)) +#define AFEC_LCDR_Msk _U_(0x0F00FFFF) /**< (AFEC_LCDR) Register Mask */ + + +/* -------- AFEC_IER : (AFEC Offset: 0x24) ( /W 32) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0_Pos _U_(0) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Position */ +#define AFEC_IER_EOC0_Msk (_U_(0x1) << AFEC_IER_EOC0_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Mask */ +#define AFEC_IER_EOC0(value) (AFEC_IER_EOC0_Msk & ((value) << AFEC_IER_EOC0_Pos)) +#define AFEC_IER_EOC1_Pos _U_(1) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Position */ +#define AFEC_IER_EOC1_Msk (_U_(0x1) << AFEC_IER_EOC1_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Mask */ +#define AFEC_IER_EOC1(value) (AFEC_IER_EOC1_Msk & ((value) << AFEC_IER_EOC1_Pos)) +#define AFEC_IER_EOC2_Pos _U_(2) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Position */ +#define AFEC_IER_EOC2_Msk (_U_(0x1) << AFEC_IER_EOC2_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Mask */ +#define AFEC_IER_EOC2(value) (AFEC_IER_EOC2_Msk & ((value) << AFEC_IER_EOC2_Pos)) +#define AFEC_IER_EOC3_Pos _U_(3) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Position */ +#define AFEC_IER_EOC3_Msk (_U_(0x1) << AFEC_IER_EOC3_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Mask */ +#define AFEC_IER_EOC3(value) (AFEC_IER_EOC3_Msk & ((value) << AFEC_IER_EOC3_Pos)) +#define AFEC_IER_EOC4_Pos _U_(4) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Position */ +#define AFEC_IER_EOC4_Msk (_U_(0x1) << AFEC_IER_EOC4_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Mask */ +#define AFEC_IER_EOC4(value) (AFEC_IER_EOC4_Msk & ((value) << AFEC_IER_EOC4_Pos)) +#define AFEC_IER_EOC5_Pos _U_(5) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Position */ +#define AFEC_IER_EOC5_Msk (_U_(0x1) << AFEC_IER_EOC5_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Mask */ +#define AFEC_IER_EOC5(value) (AFEC_IER_EOC5_Msk & ((value) << AFEC_IER_EOC5_Pos)) +#define AFEC_IER_EOC6_Pos _U_(6) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Position */ +#define AFEC_IER_EOC6_Msk (_U_(0x1) << AFEC_IER_EOC6_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Mask */ +#define AFEC_IER_EOC6(value) (AFEC_IER_EOC6_Msk & ((value) << AFEC_IER_EOC6_Pos)) +#define AFEC_IER_EOC7_Pos _U_(7) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Position */ +#define AFEC_IER_EOC7_Msk (_U_(0x1) << AFEC_IER_EOC7_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Mask */ +#define AFEC_IER_EOC7(value) (AFEC_IER_EOC7_Msk & ((value) << AFEC_IER_EOC7_Pos)) +#define AFEC_IER_EOC8_Pos _U_(8) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Position */ +#define AFEC_IER_EOC8_Msk (_U_(0x1) << AFEC_IER_EOC8_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Mask */ +#define AFEC_IER_EOC8(value) (AFEC_IER_EOC8_Msk & ((value) << AFEC_IER_EOC8_Pos)) +#define AFEC_IER_EOC9_Pos _U_(9) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Position */ +#define AFEC_IER_EOC9_Msk (_U_(0x1) << AFEC_IER_EOC9_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Mask */ +#define AFEC_IER_EOC9(value) (AFEC_IER_EOC9_Msk & ((value) << AFEC_IER_EOC9_Pos)) +#define AFEC_IER_EOC10_Pos _U_(10) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Position */ +#define AFEC_IER_EOC10_Msk (_U_(0x1) << AFEC_IER_EOC10_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Mask */ +#define AFEC_IER_EOC10(value) (AFEC_IER_EOC10_Msk & ((value) << AFEC_IER_EOC10_Pos)) +#define AFEC_IER_EOC11_Pos _U_(11) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Position */ +#define AFEC_IER_EOC11_Msk (_U_(0x1) << AFEC_IER_EOC11_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Mask */ +#define AFEC_IER_EOC11(value) (AFEC_IER_EOC11_Msk & ((value) << AFEC_IER_EOC11_Pos)) +#define AFEC_IER_DRDY_Pos _U_(24) /**< (AFEC_IER) Data Ready Interrupt Enable Position */ +#define AFEC_IER_DRDY_Msk (_U_(0x1) << AFEC_IER_DRDY_Pos) /**< (AFEC_IER) Data Ready Interrupt Enable Mask */ +#define AFEC_IER_DRDY(value) (AFEC_IER_DRDY_Msk & ((value) << AFEC_IER_DRDY_Pos)) +#define AFEC_IER_GOVRE_Pos _U_(25) /**< (AFEC_IER) General Overrun Error Interrupt Enable Position */ +#define AFEC_IER_GOVRE_Msk (_U_(0x1) << AFEC_IER_GOVRE_Pos) /**< (AFEC_IER) General Overrun Error Interrupt Enable Mask */ +#define AFEC_IER_GOVRE(value) (AFEC_IER_GOVRE_Msk & ((value) << AFEC_IER_GOVRE_Pos)) +#define AFEC_IER_COMPE_Pos _U_(26) /**< (AFEC_IER) Comparison Event Interrupt Enable Position */ +#define AFEC_IER_COMPE_Msk (_U_(0x1) << AFEC_IER_COMPE_Pos) /**< (AFEC_IER) Comparison Event Interrupt Enable Mask */ +#define AFEC_IER_COMPE(value) (AFEC_IER_COMPE_Msk & ((value) << AFEC_IER_COMPE_Pos)) +#define AFEC_IER_TEMPCHG_Pos _U_(30) /**< (AFEC_IER) Temperature Change Interrupt Enable Position */ +#define AFEC_IER_TEMPCHG_Msk (_U_(0x1) << AFEC_IER_TEMPCHG_Pos) /**< (AFEC_IER) Temperature Change Interrupt Enable Mask */ +#define AFEC_IER_TEMPCHG(value) (AFEC_IER_TEMPCHG_Msk & ((value) << AFEC_IER_TEMPCHG_Pos)) +#define AFEC_IER_Msk _U_(0x47000FFF) /**< (AFEC_IER) Register Mask */ + +#define AFEC_IER_EOC_Pos _U_(0) /**< (AFEC_IER Position) End of Conversion Interrupt Enable x */ +#define AFEC_IER_EOC_Msk (_U_(0xFFF) << AFEC_IER_EOC_Pos) /**< (AFEC_IER Mask) EOC */ +#define AFEC_IER_EOC(value) (AFEC_IER_EOC_Msk & ((value) << AFEC_IER_EOC_Pos)) + +/* -------- AFEC_IDR : (AFEC Offset: 0x28) ( /W 32) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0_Pos _U_(0) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Position */ +#define AFEC_IDR_EOC0_Msk (_U_(0x1) << AFEC_IDR_EOC0_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Mask */ +#define AFEC_IDR_EOC0(value) (AFEC_IDR_EOC0_Msk & ((value) << AFEC_IDR_EOC0_Pos)) +#define AFEC_IDR_EOC1_Pos _U_(1) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Position */ +#define AFEC_IDR_EOC1_Msk (_U_(0x1) << AFEC_IDR_EOC1_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Mask */ +#define AFEC_IDR_EOC1(value) (AFEC_IDR_EOC1_Msk & ((value) << AFEC_IDR_EOC1_Pos)) +#define AFEC_IDR_EOC2_Pos _U_(2) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Position */ +#define AFEC_IDR_EOC2_Msk (_U_(0x1) << AFEC_IDR_EOC2_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Mask */ +#define AFEC_IDR_EOC2(value) (AFEC_IDR_EOC2_Msk & ((value) << AFEC_IDR_EOC2_Pos)) +#define AFEC_IDR_EOC3_Pos _U_(3) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Position */ +#define AFEC_IDR_EOC3_Msk (_U_(0x1) << AFEC_IDR_EOC3_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Mask */ +#define AFEC_IDR_EOC3(value) (AFEC_IDR_EOC3_Msk & ((value) << AFEC_IDR_EOC3_Pos)) +#define AFEC_IDR_EOC4_Pos _U_(4) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Position */ +#define AFEC_IDR_EOC4_Msk (_U_(0x1) << AFEC_IDR_EOC4_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Mask */ +#define AFEC_IDR_EOC4(value) (AFEC_IDR_EOC4_Msk & ((value) << AFEC_IDR_EOC4_Pos)) +#define AFEC_IDR_EOC5_Pos _U_(5) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Position */ +#define AFEC_IDR_EOC5_Msk (_U_(0x1) << AFEC_IDR_EOC5_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Mask */ +#define AFEC_IDR_EOC5(value) (AFEC_IDR_EOC5_Msk & ((value) << AFEC_IDR_EOC5_Pos)) +#define AFEC_IDR_EOC6_Pos _U_(6) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Position */ +#define AFEC_IDR_EOC6_Msk (_U_(0x1) << AFEC_IDR_EOC6_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Mask */ +#define AFEC_IDR_EOC6(value) (AFEC_IDR_EOC6_Msk & ((value) << AFEC_IDR_EOC6_Pos)) +#define AFEC_IDR_EOC7_Pos _U_(7) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Position */ +#define AFEC_IDR_EOC7_Msk (_U_(0x1) << AFEC_IDR_EOC7_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Mask */ +#define AFEC_IDR_EOC7(value) (AFEC_IDR_EOC7_Msk & ((value) << AFEC_IDR_EOC7_Pos)) +#define AFEC_IDR_EOC8_Pos _U_(8) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Position */ +#define AFEC_IDR_EOC8_Msk (_U_(0x1) << AFEC_IDR_EOC8_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Mask */ +#define AFEC_IDR_EOC8(value) (AFEC_IDR_EOC8_Msk & ((value) << AFEC_IDR_EOC8_Pos)) +#define AFEC_IDR_EOC9_Pos _U_(9) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Position */ +#define AFEC_IDR_EOC9_Msk (_U_(0x1) << AFEC_IDR_EOC9_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Mask */ +#define AFEC_IDR_EOC9(value) (AFEC_IDR_EOC9_Msk & ((value) << AFEC_IDR_EOC9_Pos)) +#define AFEC_IDR_EOC10_Pos _U_(10) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Position */ +#define AFEC_IDR_EOC10_Msk (_U_(0x1) << AFEC_IDR_EOC10_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Mask */ +#define AFEC_IDR_EOC10(value) (AFEC_IDR_EOC10_Msk & ((value) << AFEC_IDR_EOC10_Pos)) +#define AFEC_IDR_EOC11_Pos _U_(11) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Position */ +#define AFEC_IDR_EOC11_Msk (_U_(0x1) << AFEC_IDR_EOC11_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Mask */ +#define AFEC_IDR_EOC11(value) (AFEC_IDR_EOC11_Msk & ((value) << AFEC_IDR_EOC11_Pos)) +#define AFEC_IDR_DRDY_Pos _U_(24) /**< (AFEC_IDR) Data Ready Interrupt Disable Position */ +#define AFEC_IDR_DRDY_Msk (_U_(0x1) << AFEC_IDR_DRDY_Pos) /**< (AFEC_IDR) Data Ready Interrupt Disable Mask */ +#define AFEC_IDR_DRDY(value) (AFEC_IDR_DRDY_Msk & ((value) << AFEC_IDR_DRDY_Pos)) +#define AFEC_IDR_GOVRE_Pos _U_(25) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Position */ +#define AFEC_IDR_GOVRE_Msk (_U_(0x1) << AFEC_IDR_GOVRE_Pos) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Mask */ +#define AFEC_IDR_GOVRE(value) (AFEC_IDR_GOVRE_Msk & ((value) << AFEC_IDR_GOVRE_Pos)) +#define AFEC_IDR_COMPE_Pos _U_(26) /**< (AFEC_IDR) Comparison Event Interrupt Disable Position */ +#define AFEC_IDR_COMPE_Msk (_U_(0x1) << AFEC_IDR_COMPE_Pos) /**< (AFEC_IDR) Comparison Event Interrupt Disable Mask */ +#define AFEC_IDR_COMPE(value) (AFEC_IDR_COMPE_Msk & ((value) << AFEC_IDR_COMPE_Pos)) +#define AFEC_IDR_TEMPCHG_Pos _U_(30) /**< (AFEC_IDR) Temperature Change Interrupt Disable Position */ +#define AFEC_IDR_TEMPCHG_Msk (_U_(0x1) << AFEC_IDR_TEMPCHG_Pos) /**< (AFEC_IDR) Temperature Change Interrupt Disable Mask */ +#define AFEC_IDR_TEMPCHG(value) (AFEC_IDR_TEMPCHG_Msk & ((value) << AFEC_IDR_TEMPCHG_Pos)) +#define AFEC_IDR_Msk _U_(0x47000FFF) /**< (AFEC_IDR) Register Mask */ + +#define AFEC_IDR_EOC_Pos _U_(0) /**< (AFEC_IDR Position) End of Conversion Interrupt Disable x */ +#define AFEC_IDR_EOC_Msk (_U_(0xFFF) << AFEC_IDR_EOC_Pos) /**< (AFEC_IDR Mask) EOC */ +#define AFEC_IDR_EOC(value) (AFEC_IDR_EOC_Msk & ((value) << AFEC_IDR_EOC_Pos)) + +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) ( R/ 32) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0_Pos _U_(0) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Position */ +#define AFEC_IMR_EOC0_Msk (_U_(0x1) << AFEC_IMR_EOC0_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Mask */ +#define AFEC_IMR_EOC0(value) (AFEC_IMR_EOC0_Msk & ((value) << AFEC_IMR_EOC0_Pos)) +#define AFEC_IMR_EOC1_Pos _U_(1) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Position */ +#define AFEC_IMR_EOC1_Msk (_U_(0x1) << AFEC_IMR_EOC1_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Mask */ +#define AFEC_IMR_EOC1(value) (AFEC_IMR_EOC1_Msk & ((value) << AFEC_IMR_EOC1_Pos)) +#define AFEC_IMR_EOC2_Pos _U_(2) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Position */ +#define AFEC_IMR_EOC2_Msk (_U_(0x1) << AFEC_IMR_EOC2_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Mask */ +#define AFEC_IMR_EOC2(value) (AFEC_IMR_EOC2_Msk & ((value) << AFEC_IMR_EOC2_Pos)) +#define AFEC_IMR_EOC3_Pos _U_(3) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Position */ +#define AFEC_IMR_EOC3_Msk (_U_(0x1) << AFEC_IMR_EOC3_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Mask */ +#define AFEC_IMR_EOC3(value) (AFEC_IMR_EOC3_Msk & ((value) << AFEC_IMR_EOC3_Pos)) +#define AFEC_IMR_EOC4_Pos _U_(4) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Position */ +#define AFEC_IMR_EOC4_Msk (_U_(0x1) << AFEC_IMR_EOC4_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Mask */ +#define AFEC_IMR_EOC4(value) (AFEC_IMR_EOC4_Msk & ((value) << AFEC_IMR_EOC4_Pos)) +#define AFEC_IMR_EOC5_Pos _U_(5) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Position */ +#define AFEC_IMR_EOC5_Msk (_U_(0x1) << AFEC_IMR_EOC5_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Mask */ +#define AFEC_IMR_EOC5(value) (AFEC_IMR_EOC5_Msk & ((value) << AFEC_IMR_EOC5_Pos)) +#define AFEC_IMR_EOC6_Pos _U_(6) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Position */ +#define AFEC_IMR_EOC6_Msk (_U_(0x1) << AFEC_IMR_EOC6_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Mask */ +#define AFEC_IMR_EOC6(value) (AFEC_IMR_EOC6_Msk & ((value) << AFEC_IMR_EOC6_Pos)) +#define AFEC_IMR_EOC7_Pos _U_(7) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Position */ +#define AFEC_IMR_EOC7_Msk (_U_(0x1) << AFEC_IMR_EOC7_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Mask */ +#define AFEC_IMR_EOC7(value) (AFEC_IMR_EOC7_Msk & ((value) << AFEC_IMR_EOC7_Pos)) +#define AFEC_IMR_EOC8_Pos _U_(8) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Position */ +#define AFEC_IMR_EOC8_Msk (_U_(0x1) << AFEC_IMR_EOC8_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Mask */ +#define AFEC_IMR_EOC8(value) (AFEC_IMR_EOC8_Msk & ((value) << AFEC_IMR_EOC8_Pos)) +#define AFEC_IMR_EOC9_Pos _U_(9) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Position */ +#define AFEC_IMR_EOC9_Msk (_U_(0x1) << AFEC_IMR_EOC9_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Mask */ +#define AFEC_IMR_EOC9(value) (AFEC_IMR_EOC9_Msk & ((value) << AFEC_IMR_EOC9_Pos)) +#define AFEC_IMR_EOC10_Pos _U_(10) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Position */ +#define AFEC_IMR_EOC10_Msk (_U_(0x1) << AFEC_IMR_EOC10_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Mask */ +#define AFEC_IMR_EOC10(value) (AFEC_IMR_EOC10_Msk & ((value) << AFEC_IMR_EOC10_Pos)) +#define AFEC_IMR_EOC11_Pos _U_(11) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Position */ +#define AFEC_IMR_EOC11_Msk (_U_(0x1) << AFEC_IMR_EOC11_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Mask */ +#define AFEC_IMR_EOC11(value) (AFEC_IMR_EOC11_Msk & ((value) << AFEC_IMR_EOC11_Pos)) +#define AFEC_IMR_DRDY_Pos _U_(24) /**< (AFEC_IMR) Data Ready Interrupt Mask Position */ +#define AFEC_IMR_DRDY_Msk (_U_(0x1) << AFEC_IMR_DRDY_Pos) /**< (AFEC_IMR) Data Ready Interrupt Mask Mask */ +#define AFEC_IMR_DRDY(value) (AFEC_IMR_DRDY_Msk & ((value) << AFEC_IMR_DRDY_Pos)) +#define AFEC_IMR_GOVRE_Pos _U_(25) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Position */ +#define AFEC_IMR_GOVRE_Msk (_U_(0x1) << AFEC_IMR_GOVRE_Pos) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Mask */ +#define AFEC_IMR_GOVRE(value) (AFEC_IMR_GOVRE_Msk & ((value) << AFEC_IMR_GOVRE_Pos)) +#define AFEC_IMR_COMPE_Pos _U_(26) /**< (AFEC_IMR) Comparison Event Interrupt Mask Position */ +#define AFEC_IMR_COMPE_Msk (_U_(0x1) << AFEC_IMR_COMPE_Pos) /**< (AFEC_IMR) Comparison Event Interrupt Mask Mask */ +#define AFEC_IMR_COMPE(value) (AFEC_IMR_COMPE_Msk & ((value) << AFEC_IMR_COMPE_Pos)) +#define AFEC_IMR_TEMPCHG_Pos _U_(30) /**< (AFEC_IMR) Temperature Change Interrupt Mask Position */ +#define AFEC_IMR_TEMPCHG_Msk (_U_(0x1) << AFEC_IMR_TEMPCHG_Pos) /**< (AFEC_IMR) Temperature Change Interrupt Mask Mask */ +#define AFEC_IMR_TEMPCHG(value) (AFEC_IMR_TEMPCHG_Msk & ((value) << AFEC_IMR_TEMPCHG_Pos)) +#define AFEC_IMR_Msk _U_(0x47000FFF) /**< (AFEC_IMR) Register Mask */ + +#define AFEC_IMR_EOC_Pos _U_(0) /**< (AFEC_IMR Position) End of Conversion Interrupt Mask x */ +#define AFEC_IMR_EOC_Msk (_U_(0xFFF) << AFEC_IMR_EOC_Pos) /**< (AFEC_IMR Mask) EOC */ +#define AFEC_IMR_EOC(value) (AFEC_IMR_EOC_Msk & ((value) << AFEC_IMR_EOC_Pos)) + +/* -------- AFEC_ISR : (AFEC Offset: 0x30) ( R/ 32) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0_Pos _U_(0) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC0_Msk (_U_(0x1) << AFEC_ISR_EOC0_Pos) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC0(value) (AFEC_ISR_EOC0_Msk & ((value) << AFEC_ISR_EOC0_Pos)) +#define AFEC_ISR_EOC1_Pos _U_(1) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC1_Msk (_U_(0x1) << AFEC_ISR_EOC1_Pos) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC1(value) (AFEC_ISR_EOC1_Msk & ((value) << AFEC_ISR_EOC1_Pos)) +#define AFEC_ISR_EOC2_Pos _U_(2) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC2_Msk (_U_(0x1) << AFEC_ISR_EOC2_Pos) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC2(value) (AFEC_ISR_EOC2_Msk & ((value) << AFEC_ISR_EOC2_Pos)) +#define AFEC_ISR_EOC3_Pos _U_(3) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC3_Msk (_U_(0x1) << AFEC_ISR_EOC3_Pos) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC3(value) (AFEC_ISR_EOC3_Msk & ((value) << AFEC_ISR_EOC3_Pos)) +#define AFEC_ISR_EOC4_Pos _U_(4) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC4_Msk (_U_(0x1) << AFEC_ISR_EOC4_Pos) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC4(value) (AFEC_ISR_EOC4_Msk & ((value) << AFEC_ISR_EOC4_Pos)) +#define AFEC_ISR_EOC5_Pos _U_(5) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC5_Msk (_U_(0x1) << AFEC_ISR_EOC5_Pos) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC5(value) (AFEC_ISR_EOC5_Msk & ((value) << AFEC_ISR_EOC5_Pos)) +#define AFEC_ISR_EOC6_Pos _U_(6) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC6_Msk (_U_(0x1) << AFEC_ISR_EOC6_Pos) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC6(value) (AFEC_ISR_EOC6_Msk & ((value) << AFEC_ISR_EOC6_Pos)) +#define AFEC_ISR_EOC7_Pos _U_(7) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC7_Msk (_U_(0x1) << AFEC_ISR_EOC7_Pos) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC7(value) (AFEC_ISR_EOC7_Msk & ((value) << AFEC_ISR_EOC7_Pos)) +#define AFEC_ISR_EOC8_Pos _U_(8) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC8_Msk (_U_(0x1) << AFEC_ISR_EOC8_Pos) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC8(value) (AFEC_ISR_EOC8_Msk & ((value) << AFEC_ISR_EOC8_Pos)) +#define AFEC_ISR_EOC9_Pos _U_(9) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC9_Msk (_U_(0x1) << AFEC_ISR_EOC9_Pos) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC9(value) (AFEC_ISR_EOC9_Msk & ((value) << AFEC_ISR_EOC9_Pos)) +#define AFEC_ISR_EOC10_Pos _U_(10) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC10_Msk (_U_(0x1) << AFEC_ISR_EOC10_Pos) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC10(value) (AFEC_ISR_EOC10_Msk & ((value) << AFEC_ISR_EOC10_Pos)) +#define AFEC_ISR_EOC11_Pos _U_(11) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Position */ +#define AFEC_ISR_EOC11_Msk (_U_(0x1) << AFEC_ISR_EOC11_Pos) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Mask */ +#define AFEC_ISR_EOC11(value) (AFEC_ISR_EOC11_Msk & ((value) << AFEC_ISR_EOC11_Pos)) +#define AFEC_ISR_DRDY_Pos _U_(24) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Position */ +#define AFEC_ISR_DRDY_Msk (_U_(0x1) << AFEC_ISR_DRDY_Pos) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Mask */ +#define AFEC_ISR_DRDY(value) (AFEC_ISR_DRDY_Msk & ((value) << AFEC_ISR_DRDY_Pos)) +#define AFEC_ISR_GOVRE_Pos _U_(25) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_GOVRE_Msk (_U_(0x1) << AFEC_ISR_GOVRE_Pos) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_GOVRE(value) (AFEC_ISR_GOVRE_Msk & ((value) << AFEC_ISR_GOVRE_Pos)) +#define AFEC_ISR_COMPE_Pos _U_(26) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Position */ +#define AFEC_ISR_COMPE_Msk (_U_(0x1) << AFEC_ISR_COMPE_Pos) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Mask */ +#define AFEC_ISR_COMPE(value) (AFEC_ISR_COMPE_Msk & ((value) << AFEC_ISR_COMPE_Pos)) +#define AFEC_ISR_TEMPCHG_Pos _U_(30) /**< (AFEC_ISR) Temperature Change (cleared on read) Position */ +#define AFEC_ISR_TEMPCHG_Msk (_U_(0x1) << AFEC_ISR_TEMPCHG_Pos) /**< (AFEC_ISR) Temperature Change (cleared on read) Mask */ +#define AFEC_ISR_TEMPCHG(value) (AFEC_ISR_TEMPCHG_Msk & ((value) << AFEC_ISR_TEMPCHG_Pos)) +#define AFEC_ISR_Msk _U_(0x47000FFF) /**< (AFEC_ISR) Register Mask */ + +#define AFEC_ISR_EOC_Pos _U_(0) /**< (AFEC_ISR Position) End of Conversion x (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC_Msk (_U_(0xFFF) << AFEC_ISR_EOC_Pos) /**< (AFEC_ISR Mask) EOC */ +#define AFEC_ISR_EOC(value) (AFEC_ISR_EOC_Msk & ((value) << AFEC_ISR_EOC_Pos)) + +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) ( R/ 32) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0_Pos _U_(0) /**< (AFEC_OVER) Overrun Error 0 Position */ +#define AFEC_OVER_OVRE0_Msk (_U_(0x1) << AFEC_OVER_OVRE0_Pos) /**< (AFEC_OVER) Overrun Error 0 Mask */ +#define AFEC_OVER_OVRE0(value) (AFEC_OVER_OVRE0_Msk & ((value) << AFEC_OVER_OVRE0_Pos)) +#define AFEC_OVER_OVRE1_Pos _U_(1) /**< (AFEC_OVER) Overrun Error 1 Position */ +#define AFEC_OVER_OVRE1_Msk (_U_(0x1) << AFEC_OVER_OVRE1_Pos) /**< (AFEC_OVER) Overrun Error 1 Mask */ +#define AFEC_OVER_OVRE1(value) (AFEC_OVER_OVRE1_Msk & ((value) << AFEC_OVER_OVRE1_Pos)) +#define AFEC_OVER_OVRE2_Pos _U_(2) /**< (AFEC_OVER) Overrun Error 2 Position */ +#define AFEC_OVER_OVRE2_Msk (_U_(0x1) << AFEC_OVER_OVRE2_Pos) /**< (AFEC_OVER) Overrun Error 2 Mask */ +#define AFEC_OVER_OVRE2(value) (AFEC_OVER_OVRE2_Msk & ((value) << AFEC_OVER_OVRE2_Pos)) +#define AFEC_OVER_OVRE3_Pos _U_(3) /**< (AFEC_OVER) Overrun Error 3 Position */ +#define AFEC_OVER_OVRE3_Msk (_U_(0x1) << AFEC_OVER_OVRE3_Pos) /**< (AFEC_OVER) Overrun Error 3 Mask */ +#define AFEC_OVER_OVRE3(value) (AFEC_OVER_OVRE3_Msk & ((value) << AFEC_OVER_OVRE3_Pos)) +#define AFEC_OVER_OVRE4_Pos _U_(4) /**< (AFEC_OVER) Overrun Error 4 Position */ +#define AFEC_OVER_OVRE4_Msk (_U_(0x1) << AFEC_OVER_OVRE4_Pos) /**< (AFEC_OVER) Overrun Error 4 Mask */ +#define AFEC_OVER_OVRE4(value) (AFEC_OVER_OVRE4_Msk & ((value) << AFEC_OVER_OVRE4_Pos)) +#define AFEC_OVER_OVRE5_Pos _U_(5) /**< (AFEC_OVER) Overrun Error 5 Position */ +#define AFEC_OVER_OVRE5_Msk (_U_(0x1) << AFEC_OVER_OVRE5_Pos) /**< (AFEC_OVER) Overrun Error 5 Mask */ +#define AFEC_OVER_OVRE5(value) (AFEC_OVER_OVRE5_Msk & ((value) << AFEC_OVER_OVRE5_Pos)) +#define AFEC_OVER_OVRE6_Pos _U_(6) /**< (AFEC_OVER) Overrun Error 6 Position */ +#define AFEC_OVER_OVRE6_Msk (_U_(0x1) << AFEC_OVER_OVRE6_Pos) /**< (AFEC_OVER) Overrun Error 6 Mask */ +#define AFEC_OVER_OVRE6(value) (AFEC_OVER_OVRE6_Msk & ((value) << AFEC_OVER_OVRE6_Pos)) +#define AFEC_OVER_OVRE7_Pos _U_(7) /**< (AFEC_OVER) Overrun Error 7 Position */ +#define AFEC_OVER_OVRE7_Msk (_U_(0x1) << AFEC_OVER_OVRE7_Pos) /**< (AFEC_OVER) Overrun Error 7 Mask */ +#define AFEC_OVER_OVRE7(value) (AFEC_OVER_OVRE7_Msk & ((value) << AFEC_OVER_OVRE7_Pos)) +#define AFEC_OVER_OVRE8_Pos _U_(8) /**< (AFEC_OVER) Overrun Error 8 Position */ +#define AFEC_OVER_OVRE8_Msk (_U_(0x1) << AFEC_OVER_OVRE8_Pos) /**< (AFEC_OVER) Overrun Error 8 Mask */ +#define AFEC_OVER_OVRE8(value) (AFEC_OVER_OVRE8_Msk & ((value) << AFEC_OVER_OVRE8_Pos)) +#define AFEC_OVER_OVRE9_Pos _U_(9) /**< (AFEC_OVER) Overrun Error 9 Position */ +#define AFEC_OVER_OVRE9_Msk (_U_(0x1) << AFEC_OVER_OVRE9_Pos) /**< (AFEC_OVER) Overrun Error 9 Mask */ +#define AFEC_OVER_OVRE9(value) (AFEC_OVER_OVRE9_Msk & ((value) << AFEC_OVER_OVRE9_Pos)) +#define AFEC_OVER_OVRE10_Pos _U_(10) /**< (AFEC_OVER) Overrun Error 10 Position */ +#define AFEC_OVER_OVRE10_Msk (_U_(0x1) << AFEC_OVER_OVRE10_Pos) /**< (AFEC_OVER) Overrun Error 10 Mask */ +#define AFEC_OVER_OVRE10(value) (AFEC_OVER_OVRE10_Msk & ((value) << AFEC_OVER_OVRE10_Pos)) +#define AFEC_OVER_OVRE11_Pos _U_(11) /**< (AFEC_OVER) Overrun Error 11 Position */ +#define AFEC_OVER_OVRE11_Msk (_U_(0x1) << AFEC_OVER_OVRE11_Pos) /**< (AFEC_OVER) Overrun Error 11 Mask */ +#define AFEC_OVER_OVRE11(value) (AFEC_OVER_OVRE11_Msk & ((value) << AFEC_OVER_OVRE11_Pos)) +#define AFEC_OVER_Msk _U_(0x00000FFF) /**< (AFEC_OVER) Register Mask */ + +#define AFEC_OVER_OVRE_Pos _U_(0) /**< (AFEC_OVER Position) Overrun Error xx */ +#define AFEC_OVER_OVRE_Msk (_U_(0xFFF) << AFEC_OVER_OVRE_Pos) /**< (AFEC_OVER Mask) OVRE */ +#define AFEC_OVER_OVRE(value) (AFEC_OVER_OVRE_Msk & ((value) << AFEC_OVER_OVRE_Pos)) + +/* -------- AFEC_CWR : (AFEC Offset: 0x50) (R/W 32) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos _U_(0) /**< (AFEC_CWR) Low Threshold Position */ +#define AFEC_CWR_LOWTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_LOWTHRES_Pos) /**< (AFEC_CWR) Low Threshold Mask */ +#define AFEC_CWR_LOWTHRES(value) (AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)) +#define AFEC_CWR_HIGHTHRES_Pos _U_(16) /**< (AFEC_CWR) High Threshold Position */ +#define AFEC_CWR_HIGHTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_HIGHTHRES_Pos) /**< (AFEC_CWR) High Threshold Mask */ +#define AFEC_CWR_HIGHTHRES(value) (AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)) +#define AFEC_CWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CWR) Register Mask */ + + +/* -------- AFEC_CGR : (AFEC Offset: 0x54) (R/W 32) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos _U_(0) /**< (AFEC_CGR) Gain for Channel 0 Position */ +#define AFEC_CGR_GAIN0_Msk (_U_(0x3) << AFEC_CGR_GAIN0_Pos) /**< (AFEC_CGR) Gain for Channel 0 Mask */ +#define AFEC_CGR_GAIN0(value) (AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)) +#define AFEC_CGR_GAIN1_Pos _U_(2) /**< (AFEC_CGR) Gain for Channel 1 Position */ +#define AFEC_CGR_GAIN1_Msk (_U_(0x3) << AFEC_CGR_GAIN1_Pos) /**< (AFEC_CGR) Gain for Channel 1 Mask */ +#define AFEC_CGR_GAIN1(value) (AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)) +#define AFEC_CGR_GAIN2_Pos _U_(4) /**< (AFEC_CGR) Gain for Channel 2 Position */ +#define AFEC_CGR_GAIN2_Msk (_U_(0x3) << AFEC_CGR_GAIN2_Pos) /**< (AFEC_CGR) Gain for Channel 2 Mask */ +#define AFEC_CGR_GAIN2(value) (AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)) +#define AFEC_CGR_GAIN3_Pos _U_(6) /**< (AFEC_CGR) Gain for Channel 3 Position */ +#define AFEC_CGR_GAIN3_Msk (_U_(0x3) << AFEC_CGR_GAIN3_Pos) /**< (AFEC_CGR) Gain for Channel 3 Mask */ +#define AFEC_CGR_GAIN3(value) (AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)) +#define AFEC_CGR_GAIN4_Pos _U_(8) /**< (AFEC_CGR) Gain for Channel 4 Position */ +#define AFEC_CGR_GAIN4_Msk (_U_(0x3) << AFEC_CGR_GAIN4_Pos) /**< (AFEC_CGR) Gain for Channel 4 Mask */ +#define AFEC_CGR_GAIN4(value) (AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)) +#define AFEC_CGR_GAIN5_Pos _U_(10) /**< (AFEC_CGR) Gain for Channel 5 Position */ +#define AFEC_CGR_GAIN5_Msk (_U_(0x3) << AFEC_CGR_GAIN5_Pos) /**< (AFEC_CGR) Gain for Channel 5 Mask */ +#define AFEC_CGR_GAIN5(value) (AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)) +#define AFEC_CGR_GAIN6_Pos _U_(12) /**< (AFEC_CGR) Gain for Channel 6 Position */ +#define AFEC_CGR_GAIN6_Msk (_U_(0x3) << AFEC_CGR_GAIN6_Pos) /**< (AFEC_CGR) Gain for Channel 6 Mask */ +#define AFEC_CGR_GAIN6(value) (AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)) +#define AFEC_CGR_GAIN7_Pos _U_(14) /**< (AFEC_CGR) Gain for Channel 7 Position */ +#define AFEC_CGR_GAIN7_Msk (_U_(0x3) << AFEC_CGR_GAIN7_Pos) /**< (AFEC_CGR) Gain for Channel 7 Mask */ +#define AFEC_CGR_GAIN7(value) (AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)) +#define AFEC_CGR_GAIN8_Pos _U_(16) /**< (AFEC_CGR) Gain for Channel 8 Position */ +#define AFEC_CGR_GAIN8_Msk (_U_(0x3) << AFEC_CGR_GAIN8_Pos) /**< (AFEC_CGR) Gain for Channel 8 Mask */ +#define AFEC_CGR_GAIN8(value) (AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)) +#define AFEC_CGR_GAIN9_Pos _U_(18) /**< (AFEC_CGR) Gain for Channel 9 Position */ +#define AFEC_CGR_GAIN9_Msk (_U_(0x3) << AFEC_CGR_GAIN9_Pos) /**< (AFEC_CGR) Gain for Channel 9 Mask */ +#define AFEC_CGR_GAIN9(value) (AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)) +#define AFEC_CGR_GAIN10_Pos _U_(20) /**< (AFEC_CGR) Gain for Channel 10 Position */ +#define AFEC_CGR_GAIN10_Msk (_U_(0x3) << AFEC_CGR_GAIN10_Pos) /**< (AFEC_CGR) Gain for Channel 10 Mask */ +#define AFEC_CGR_GAIN10(value) (AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)) +#define AFEC_CGR_GAIN11_Pos _U_(22) /**< (AFEC_CGR) Gain for Channel 11 Position */ +#define AFEC_CGR_GAIN11_Msk (_U_(0x3) << AFEC_CGR_GAIN11_Pos) /**< (AFEC_CGR) Gain for Channel 11 Mask */ +#define AFEC_CGR_GAIN11(value) (AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)) +#define AFEC_CGR_Msk _U_(0x00FFFFFF) /**< (AFEC_CGR) Register Mask */ + + +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) (R/W 32) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0_Pos _U_(0) /**< (AFEC_DIFFR) Differential inputs for channel 0 Position */ +#define AFEC_DIFFR_DIFF0_Msk (_U_(0x1) << AFEC_DIFFR_DIFF0_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 0 Mask */ +#define AFEC_DIFFR_DIFF0(value) (AFEC_DIFFR_DIFF0_Msk & ((value) << AFEC_DIFFR_DIFF0_Pos)) +#define AFEC_DIFFR_DIFF1_Pos _U_(1) /**< (AFEC_DIFFR) Differential inputs for channel 1 Position */ +#define AFEC_DIFFR_DIFF1_Msk (_U_(0x1) << AFEC_DIFFR_DIFF1_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 1 Mask */ +#define AFEC_DIFFR_DIFF1(value) (AFEC_DIFFR_DIFF1_Msk & ((value) << AFEC_DIFFR_DIFF1_Pos)) +#define AFEC_DIFFR_DIFF2_Pos _U_(2) /**< (AFEC_DIFFR) Differential inputs for channel 2 Position */ +#define AFEC_DIFFR_DIFF2_Msk (_U_(0x1) << AFEC_DIFFR_DIFF2_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 2 Mask */ +#define AFEC_DIFFR_DIFF2(value) (AFEC_DIFFR_DIFF2_Msk & ((value) << AFEC_DIFFR_DIFF2_Pos)) +#define AFEC_DIFFR_DIFF3_Pos _U_(3) /**< (AFEC_DIFFR) Differential inputs for channel 3 Position */ +#define AFEC_DIFFR_DIFF3_Msk (_U_(0x1) << AFEC_DIFFR_DIFF3_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 3 Mask */ +#define AFEC_DIFFR_DIFF3(value) (AFEC_DIFFR_DIFF3_Msk & ((value) << AFEC_DIFFR_DIFF3_Pos)) +#define AFEC_DIFFR_DIFF4_Pos _U_(4) /**< (AFEC_DIFFR) Differential inputs for channel 4 Position */ +#define AFEC_DIFFR_DIFF4_Msk (_U_(0x1) << AFEC_DIFFR_DIFF4_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 4 Mask */ +#define AFEC_DIFFR_DIFF4(value) (AFEC_DIFFR_DIFF4_Msk & ((value) << AFEC_DIFFR_DIFF4_Pos)) +#define AFEC_DIFFR_DIFF5_Pos _U_(5) /**< (AFEC_DIFFR) Differential inputs for channel 5 Position */ +#define AFEC_DIFFR_DIFF5_Msk (_U_(0x1) << AFEC_DIFFR_DIFF5_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 5 Mask */ +#define AFEC_DIFFR_DIFF5(value) (AFEC_DIFFR_DIFF5_Msk & ((value) << AFEC_DIFFR_DIFF5_Pos)) +#define AFEC_DIFFR_DIFF6_Pos _U_(6) /**< (AFEC_DIFFR) Differential inputs for channel 6 Position */ +#define AFEC_DIFFR_DIFF6_Msk (_U_(0x1) << AFEC_DIFFR_DIFF6_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 6 Mask */ +#define AFEC_DIFFR_DIFF6(value) (AFEC_DIFFR_DIFF6_Msk & ((value) << AFEC_DIFFR_DIFF6_Pos)) +#define AFEC_DIFFR_DIFF7_Pos _U_(7) /**< (AFEC_DIFFR) Differential inputs for channel 7 Position */ +#define AFEC_DIFFR_DIFF7_Msk (_U_(0x1) << AFEC_DIFFR_DIFF7_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 7 Mask */ +#define AFEC_DIFFR_DIFF7(value) (AFEC_DIFFR_DIFF7_Msk & ((value) << AFEC_DIFFR_DIFF7_Pos)) +#define AFEC_DIFFR_DIFF8_Pos _U_(8) /**< (AFEC_DIFFR) Differential inputs for channel 8 Position */ +#define AFEC_DIFFR_DIFF8_Msk (_U_(0x1) << AFEC_DIFFR_DIFF8_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 8 Mask */ +#define AFEC_DIFFR_DIFF8(value) (AFEC_DIFFR_DIFF8_Msk & ((value) << AFEC_DIFFR_DIFF8_Pos)) +#define AFEC_DIFFR_DIFF9_Pos _U_(9) /**< (AFEC_DIFFR) Differential inputs for channel 9 Position */ +#define AFEC_DIFFR_DIFF9_Msk (_U_(0x1) << AFEC_DIFFR_DIFF9_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 9 Mask */ +#define AFEC_DIFFR_DIFF9(value) (AFEC_DIFFR_DIFF9_Msk & ((value) << AFEC_DIFFR_DIFF9_Pos)) +#define AFEC_DIFFR_DIFF10_Pos _U_(10) /**< (AFEC_DIFFR) Differential inputs for channel 10 Position */ +#define AFEC_DIFFR_DIFF10_Msk (_U_(0x1) << AFEC_DIFFR_DIFF10_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 10 Mask */ +#define AFEC_DIFFR_DIFF10(value) (AFEC_DIFFR_DIFF10_Msk & ((value) << AFEC_DIFFR_DIFF10_Pos)) +#define AFEC_DIFFR_DIFF11_Pos _U_(11) /**< (AFEC_DIFFR) Differential inputs for channel 11 Position */ +#define AFEC_DIFFR_DIFF11_Msk (_U_(0x1) << AFEC_DIFFR_DIFF11_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 11 Mask */ +#define AFEC_DIFFR_DIFF11(value) (AFEC_DIFFR_DIFF11_Msk & ((value) << AFEC_DIFFR_DIFF11_Pos)) +#define AFEC_DIFFR_Msk _U_(0x00000FFF) /**< (AFEC_DIFFR) Register Mask */ + +#define AFEC_DIFFR_DIFF_Pos _U_(0) /**< (AFEC_DIFFR Position) Differential inputs for channel xx */ +#define AFEC_DIFFR_DIFF_Msk (_U_(0xFFF) << AFEC_DIFFR_DIFF_Pos) /**< (AFEC_DIFFR Mask) DIFF */ +#define AFEC_DIFFR_DIFF(value) (AFEC_DIFFR_DIFF_Msk & ((value) << AFEC_DIFFR_DIFF_Pos)) + +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) (R/W 32) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos _U_(0) /**< (AFEC_CSELR) Channel Selection Position */ +#define AFEC_CSELR_CSEL_Msk (_U_(0xF) << AFEC_CSELR_CSEL_Pos) /**< (AFEC_CSELR) Channel Selection Mask */ +#define AFEC_CSELR_CSEL(value) (AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)) +#define AFEC_CSELR_Msk _U_(0x0000000F) /**< (AFEC_CSELR) Register Mask */ + + +/* -------- AFEC_CDR : (AFEC Offset: 0x68) ( R/ 32) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos _U_(0) /**< (AFEC_CDR) Converted Data Position */ +#define AFEC_CDR_DATA_Msk (_U_(0xFFFF) << AFEC_CDR_DATA_Pos) /**< (AFEC_CDR) Converted Data Mask */ +#define AFEC_CDR_DATA(value) (AFEC_CDR_DATA_Msk & ((value) << AFEC_CDR_DATA_Pos)) +#define AFEC_CDR_Msk _U_(0x0000FFFF) /**< (AFEC_CDR) Register Mask */ + + +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) (R/W 32) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos _U_(0) /**< (AFEC_COCR) Analog Offset Position */ +#define AFEC_COCR_AOFF_Msk (_U_(0x3FF) << AFEC_COCR_AOFF_Pos) /**< (AFEC_COCR) Analog Offset Mask */ +#define AFEC_COCR_AOFF(value) (AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)) +#define AFEC_COCR_Msk _U_(0x000003FF) /**< (AFEC_COCR) Register Mask */ + + +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) (R/W 32) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT_Pos _U_(0) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Position */ +#define AFEC_TEMPMR_RTCT_Msk (_U_(0x1) << AFEC_TEMPMR_RTCT_Pos) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Mask */ +#define AFEC_TEMPMR_RTCT(value) (AFEC_TEMPMR_RTCT_Msk & ((value) << AFEC_TEMPMR_RTCT_Pos)) +#define AFEC_TEMPMR_TEMPCMPMOD_Pos _U_(4) /**< (AFEC_TEMPMR) Temperature Comparison Mode Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (_U_(0x3) << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Temperature Comparison Mode Mask */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) (AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW_Val _U_(0x0) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val _U_(0x1) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN_Val _U_(0x2) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT_Val _U_(0x3) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (AFEC_TEMPMR_TEMPCMPMOD_LOW_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (AFEC_TEMPMR_TEMPCMPMOD_IN_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. Position */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (AFEC_TEMPMR_TEMPCMPMOD_OUT_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. Position */ +#define AFEC_TEMPMR_Msk _U_(0x00000031) /**< (AFEC_TEMPMR) Register Mask */ + + +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) (R/W 32) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos _U_(0) /**< (AFEC_TEMPCWR) Temperature Low Threshold Position */ +#define AFEC_TEMPCWR_TLOWTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature Low Threshold Mask */ +#define AFEC_TEMPCWR_TLOWTHRES(value) (AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)) +#define AFEC_TEMPCWR_THIGHTHRES_Pos _U_(16) /**< (AFEC_TEMPCWR) Temperature High Threshold Position */ +#define AFEC_TEMPCWR_THIGHTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature High Threshold Mask */ +#define AFEC_TEMPCWR_THIGHTHRES(value) (AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)) +#define AFEC_TEMPCWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_TEMPCWR) Register Mask */ + + +/* -------- AFEC_ACR : (AFEC Offset: 0x94) (R/W 32) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN_Pos _U_(2) /**< (AFEC_ACR) PGA0 Enable Position */ +#define AFEC_ACR_PGA0EN_Msk (_U_(0x1) << AFEC_ACR_PGA0EN_Pos) /**< (AFEC_ACR) PGA0 Enable Mask */ +#define AFEC_ACR_PGA0EN(value) (AFEC_ACR_PGA0EN_Msk & ((value) << AFEC_ACR_PGA0EN_Pos)) +#define AFEC_ACR_PGA1EN_Pos _U_(3) /**< (AFEC_ACR) PGA1 Enable Position */ +#define AFEC_ACR_PGA1EN_Msk (_U_(0x1) << AFEC_ACR_PGA1EN_Pos) /**< (AFEC_ACR) PGA1 Enable Mask */ +#define AFEC_ACR_PGA1EN(value) (AFEC_ACR_PGA1EN_Msk & ((value) << AFEC_ACR_PGA1EN_Pos)) +#define AFEC_ACR_IBCTL_Pos _U_(8) /**< (AFEC_ACR) AFE Bias Current Control Position */ +#define AFEC_ACR_IBCTL_Msk (_U_(0x3) << AFEC_ACR_IBCTL_Pos) /**< (AFEC_ACR) AFE Bias Current Control Mask */ +#define AFEC_ACR_IBCTL(value) (AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)) +#define AFEC_ACR_Msk _U_(0x0000030C) /**< (AFEC_ACR) Register Mask */ + + +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) (R/W 32) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0_Pos _U_(0) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Position */ +#define AFEC_SHMR_DUAL0_Msk (_U_(0x1) << AFEC_SHMR_DUAL0_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Mask */ +#define AFEC_SHMR_DUAL0(value) (AFEC_SHMR_DUAL0_Msk & ((value) << AFEC_SHMR_DUAL0_Pos)) +#define AFEC_SHMR_DUAL1_Pos _U_(1) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Position */ +#define AFEC_SHMR_DUAL1_Msk (_U_(0x1) << AFEC_SHMR_DUAL1_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Mask */ +#define AFEC_SHMR_DUAL1(value) (AFEC_SHMR_DUAL1_Msk & ((value) << AFEC_SHMR_DUAL1_Pos)) +#define AFEC_SHMR_DUAL2_Pos _U_(2) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Position */ +#define AFEC_SHMR_DUAL2_Msk (_U_(0x1) << AFEC_SHMR_DUAL2_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Mask */ +#define AFEC_SHMR_DUAL2(value) (AFEC_SHMR_DUAL2_Msk & ((value) << AFEC_SHMR_DUAL2_Pos)) +#define AFEC_SHMR_DUAL3_Pos _U_(3) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Position */ +#define AFEC_SHMR_DUAL3_Msk (_U_(0x1) << AFEC_SHMR_DUAL3_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Mask */ +#define AFEC_SHMR_DUAL3(value) (AFEC_SHMR_DUAL3_Msk & ((value) << AFEC_SHMR_DUAL3_Pos)) +#define AFEC_SHMR_DUAL4_Pos _U_(4) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Position */ +#define AFEC_SHMR_DUAL4_Msk (_U_(0x1) << AFEC_SHMR_DUAL4_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Mask */ +#define AFEC_SHMR_DUAL4(value) (AFEC_SHMR_DUAL4_Msk & ((value) << AFEC_SHMR_DUAL4_Pos)) +#define AFEC_SHMR_DUAL5_Pos _U_(5) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Position */ +#define AFEC_SHMR_DUAL5_Msk (_U_(0x1) << AFEC_SHMR_DUAL5_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Mask */ +#define AFEC_SHMR_DUAL5(value) (AFEC_SHMR_DUAL5_Msk & ((value) << AFEC_SHMR_DUAL5_Pos)) +#define AFEC_SHMR_DUAL6_Pos _U_(6) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Position */ +#define AFEC_SHMR_DUAL6_Msk (_U_(0x1) << AFEC_SHMR_DUAL6_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Mask */ +#define AFEC_SHMR_DUAL6(value) (AFEC_SHMR_DUAL6_Msk & ((value) << AFEC_SHMR_DUAL6_Pos)) +#define AFEC_SHMR_DUAL7_Pos _U_(7) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Position */ +#define AFEC_SHMR_DUAL7_Msk (_U_(0x1) << AFEC_SHMR_DUAL7_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Mask */ +#define AFEC_SHMR_DUAL7(value) (AFEC_SHMR_DUAL7_Msk & ((value) << AFEC_SHMR_DUAL7_Pos)) +#define AFEC_SHMR_DUAL8_Pos _U_(8) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Position */ +#define AFEC_SHMR_DUAL8_Msk (_U_(0x1) << AFEC_SHMR_DUAL8_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Mask */ +#define AFEC_SHMR_DUAL8(value) (AFEC_SHMR_DUAL8_Msk & ((value) << AFEC_SHMR_DUAL8_Pos)) +#define AFEC_SHMR_DUAL9_Pos _U_(9) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Position */ +#define AFEC_SHMR_DUAL9_Msk (_U_(0x1) << AFEC_SHMR_DUAL9_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Mask */ +#define AFEC_SHMR_DUAL9(value) (AFEC_SHMR_DUAL9_Msk & ((value) << AFEC_SHMR_DUAL9_Pos)) +#define AFEC_SHMR_DUAL10_Pos _U_(10) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Position */ +#define AFEC_SHMR_DUAL10_Msk (_U_(0x1) << AFEC_SHMR_DUAL10_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Mask */ +#define AFEC_SHMR_DUAL10(value) (AFEC_SHMR_DUAL10_Msk & ((value) << AFEC_SHMR_DUAL10_Pos)) +#define AFEC_SHMR_DUAL11_Pos _U_(11) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Position */ +#define AFEC_SHMR_DUAL11_Msk (_U_(0x1) << AFEC_SHMR_DUAL11_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Mask */ +#define AFEC_SHMR_DUAL11(value) (AFEC_SHMR_DUAL11_Msk & ((value) << AFEC_SHMR_DUAL11_Pos)) +#define AFEC_SHMR_Msk _U_(0x00000FFF) /**< (AFEC_SHMR) Register Mask */ + +#define AFEC_SHMR_DUAL_Pos _U_(0) /**< (AFEC_SHMR Position) Dual Sample & Hold for channel xx */ +#define AFEC_SHMR_DUAL_Msk (_U_(0xFFF) << AFEC_SHMR_DUAL_Pos) /**< (AFEC_SHMR Mask) DUAL */ +#define AFEC_SHMR_DUAL(value) (AFEC_SHMR_DUAL_Msk & ((value) << AFEC_SHMR_DUAL_Pos)) + +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) (R/W 32) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL_Pos _U_(0) /**< (AFEC_COSR) Sample & Hold unit Correction Select Position */ +#define AFEC_COSR_CSEL_Msk (_U_(0x1) << AFEC_COSR_CSEL_Pos) /**< (AFEC_COSR) Sample & Hold unit Correction Select Mask */ +#define AFEC_COSR_CSEL(value) (AFEC_COSR_CSEL_Msk & ((value) << AFEC_COSR_CSEL_Pos)) +#define AFEC_COSR_Msk _U_(0x00000001) /**< (AFEC_COSR) Register Mask */ + + +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) (R/W 32) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos _U_(0) /**< (AFEC_CVR) Offset Correction Position */ +#define AFEC_CVR_OFFSETCORR_Msk (_U_(0xFFFF) << AFEC_CVR_OFFSETCORR_Pos) /**< (AFEC_CVR) Offset Correction Mask */ +#define AFEC_CVR_OFFSETCORR(value) (AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)) +#define AFEC_CVR_GAINCORR_Pos _U_(16) /**< (AFEC_CVR) Gain Correction Position */ +#define AFEC_CVR_GAINCORR_Msk (_U_(0xFFFF) << AFEC_CVR_GAINCORR_Pos) /**< (AFEC_CVR) Gain Correction Mask */ +#define AFEC_CVR_GAINCORR(value) (AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)) +#define AFEC_CVR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CVR) Register Mask */ + + +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) (R/W 32) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0_Pos _U_(0) /**< (AFEC_CECR) Error Correction Enable for channel 0 Position */ +#define AFEC_CECR_ECORR0_Msk (_U_(0x1) << AFEC_CECR_ECORR0_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 0 Mask */ +#define AFEC_CECR_ECORR0(value) (AFEC_CECR_ECORR0_Msk & ((value) << AFEC_CECR_ECORR0_Pos)) +#define AFEC_CECR_ECORR1_Pos _U_(1) /**< (AFEC_CECR) Error Correction Enable for channel 1 Position */ +#define AFEC_CECR_ECORR1_Msk (_U_(0x1) << AFEC_CECR_ECORR1_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 1 Mask */ +#define AFEC_CECR_ECORR1(value) (AFEC_CECR_ECORR1_Msk & ((value) << AFEC_CECR_ECORR1_Pos)) +#define AFEC_CECR_ECORR2_Pos _U_(2) /**< (AFEC_CECR) Error Correction Enable for channel 2 Position */ +#define AFEC_CECR_ECORR2_Msk (_U_(0x1) << AFEC_CECR_ECORR2_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 2 Mask */ +#define AFEC_CECR_ECORR2(value) (AFEC_CECR_ECORR2_Msk & ((value) << AFEC_CECR_ECORR2_Pos)) +#define AFEC_CECR_ECORR3_Pos _U_(3) /**< (AFEC_CECR) Error Correction Enable for channel 3 Position */ +#define AFEC_CECR_ECORR3_Msk (_U_(0x1) << AFEC_CECR_ECORR3_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 3 Mask */ +#define AFEC_CECR_ECORR3(value) (AFEC_CECR_ECORR3_Msk & ((value) << AFEC_CECR_ECORR3_Pos)) +#define AFEC_CECR_ECORR4_Pos _U_(4) /**< (AFEC_CECR) Error Correction Enable for channel 4 Position */ +#define AFEC_CECR_ECORR4_Msk (_U_(0x1) << AFEC_CECR_ECORR4_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 4 Mask */ +#define AFEC_CECR_ECORR4(value) (AFEC_CECR_ECORR4_Msk & ((value) << AFEC_CECR_ECORR4_Pos)) +#define AFEC_CECR_ECORR5_Pos _U_(5) /**< (AFEC_CECR) Error Correction Enable for channel 5 Position */ +#define AFEC_CECR_ECORR5_Msk (_U_(0x1) << AFEC_CECR_ECORR5_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 5 Mask */ +#define AFEC_CECR_ECORR5(value) (AFEC_CECR_ECORR5_Msk & ((value) << AFEC_CECR_ECORR5_Pos)) +#define AFEC_CECR_ECORR6_Pos _U_(6) /**< (AFEC_CECR) Error Correction Enable for channel 6 Position */ +#define AFEC_CECR_ECORR6_Msk (_U_(0x1) << AFEC_CECR_ECORR6_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 6 Mask */ +#define AFEC_CECR_ECORR6(value) (AFEC_CECR_ECORR6_Msk & ((value) << AFEC_CECR_ECORR6_Pos)) +#define AFEC_CECR_ECORR7_Pos _U_(7) /**< (AFEC_CECR) Error Correction Enable for channel 7 Position */ +#define AFEC_CECR_ECORR7_Msk (_U_(0x1) << AFEC_CECR_ECORR7_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 7 Mask */ +#define AFEC_CECR_ECORR7(value) (AFEC_CECR_ECORR7_Msk & ((value) << AFEC_CECR_ECORR7_Pos)) +#define AFEC_CECR_ECORR8_Pos _U_(8) /**< (AFEC_CECR) Error Correction Enable for channel 8 Position */ +#define AFEC_CECR_ECORR8_Msk (_U_(0x1) << AFEC_CECR_ECORR8_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 8 Mask */ +#define AFEC_CECR_ECORR8(value) (AFEC_CECR_ECORR8_Msk & ((value) << AFEC_CECR_ECORR8_Pos)) +#define AFEC_CECR_ECORR9_Pos _U_(9) /**< (AFEC_CECR) Error Correction Enable for channel 9 Position */ +#define AFEC_CECR_ECORR9_Msk (_U_(0x1) << AFEC_CECR_ECORR9_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 9 Mask */ +#define AFEC_CECR_ECORR9(value) (AFEC_CECR_ECORR9_Msk & ((value) << AFEC_CECR_ECORR9_Pos)) +#define AFEC_CECR_ECORR10_Pos _U_(10) /**< (AFEC_CECR) Error Correction Enable for channel 10 Position */ +#define AFEC_CECR_ECORR10_Msk (_U_(0x1) << AFEC_CECR_ECORR10_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 10 Mask */ +#define AFEC_CECR_ECORR10(value) (AFEC_CECR_ECORR10_Msk & ((value) << AFEC_CECR_ECORR10_Pos)) +#define AFEC_CECR_ECORR11_Pos _U_(11) /**< (AFEC_CECR) Error Correction Enable for channel 11 Position */ +#define AFEC_CECR_ECORR11_Msk (_U_(0x1) << AFEC_CECR_ECORR11_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 11 Mask */ +#define AFEC_CECR_ECORR11(value) (AFEC_CECR_ECORR11_Msk & ((value) << AFEC_CECR_ECORR11_Pos)) +#define AFEC_CECR_Msk _U_(0x00000FFF) /**< (AFEC_CECR) Register Mask */ + +#define AFEC_CECR_ECORR_Pos _U_(0) /**< (AFEC_CECR Position) Error Correction Enable for channel xx */ +#define AFEC_CECR_ECORR_Msk (_U_(0xFFF) << AFEC_CECR_ECORR_Pos) /**< (AFEC_CECR Mask) ECORR */ +#define AFEC_CECR_ECORR(value) (AFEC_CECR_ECORR_Msk & ((value) << AFEC_CECR_ECORR_Pos)) + +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) (R/W 32) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN_Pos _U_(0) /**< (AFEC_WPMR) Write Protection Enable Position */ +#define AFEC_WPMR_WPEN_Msk (_U_(0x1) << AFEC_WPMR_WPEN_Pos) /**< (AFEC_WPMR) Write Protection Enable Mask */ +#define AFEC_WPMR_WPEN(value) (AFEC_WPMR_WPEN_Msk & ((value) << AFEC_WPMR_WPEN_Pos)) +#define AFEC_WPMR_WPKEY_Pos _U_(8) /**< (AFEC_WPMR) Write Protect KEY Position */ +#define AFEC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Write Protect KEY Mask */ +#define AFEC_WPMR_WPKEY(value) (AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)) +#define AFEC_WPMR_WPKEY_PASSWD_Val _U_(0x414443) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define AFEC_WPMR_WPKEY_PASSWD (AFEC_WPMR_WPKEY_PASSWD_Val << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define AFEC_WPMR_Msk _U_(0xFFFFFF01) /**< (AFEC_WPMR) Register Mask */ + + +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) ( R/ 32) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS_Pos _U_(0) /**< (AFEC_WPSR) Write Protect Violation Status Position */ +#define AFEC_WPSR_WPVS_Msk (_U_(0x1) << AFEC_WPSR_WPVS_Pos) /**< (AFEC_WPSR) Write Protect Violation Status Mask */ +#define AFEC_WPSR_WPVS(value) (AFEC_WPSR_WPVS_Msk & ((value) << AFEC_WPSR_WPVS_Pos)) +#define AFEC_WPSR_WPVSRC_Pos _U_(8) /**< (AFEC_WPSR) Write Protect Violation Source Position */ +#define AFEC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << AFEC_WPSR_WPVSRC_Pos) /**< (AFEC_WPSR) Write Protect Violation Source Mask */ +#define AFEC_WPSR_WPVSRC(value) (AFEC_WPSR_WPVSRC_Msk & ((value) << AFEC_WPSR_WPVSRC_Pos)) +#define AFEC_WPSR_Msk _U_(0x00FFFF01) /**< (AFEC_WPSR) Register Mask */ + + +/** \brief AFEC register offsets definitions */ +#define AFEC_CR_REG_OFST (0x00) /**< (AFEC_CR) AFEC Control Register Offset */ +#define AFEC_MR_REG_OFST (0x04) /**< (AFEC_MR) AFEC Mode Register Offset */ +#define AFEC_EMR_REG_OFST (0x08) /**< (AFEC_EMR) AFEC Extended Mode Register Offset */ +#define AFEC_SEQ1R_REG_OFST (0x0C) /**< (AFEC_SEQ1R) AFEC Channel Sequence 1 Register Offset */ +#define AFEC_SEQ2R_REG_OFST (0x10) /**< (AFEC_SEQ2R) AFEC Channel Sequence 2 Register Offset */ +#define AFEC_CHER_REG_OFST (0x14) /**< (AFEC_CHER) AFEC Channel Enable Register Offset */ +#define AFEC_CHDR_REG_OFST (0x18) /**< (AFEC_CHDR) AFEC Channel Disable Register Offset */ +#define AFEC_CHSR_REG_OFST (0x1C) /**< (AFEC_CHSR) AFEC Channel Status Register Offset */ +#define AFEC_LCDR_REG_OFST (0x20) /**< (AFEC_LCDR) AFEC Last Converted Data Register Offset */ +#define AFEC_IER_REG_OFST (0x24) /**< (AFEC_IER) AFEC Interrupt Enable Register Offset */ +#define AFEC_IDR_REG_OFST (0x28) /**< (AFEC_IDR) AFEC Interrupt Disable Register Offset */ +#define AFEC_IMR_REG_OFST (0x2C) /**< (AFEC_IMR) AFEC Interrupt Mask Register Offset */ +#define AFEC_ISR_REG_OFST (0x30) /**< (AFEC_ISR) AFEC Interrupt Status Register Offset */ +#define AFEC_OVER_REG_OFST (0x4C) /**< (AFEC_OVER) AFEC Overrun Status Register Offset */ +#define AFEC_CWR_REG_OFST (0x50) /**< (AFEC_CWR) AFEC Compare Window Register Offset */ +#define AFEC_CGR_REG_OFST (0x54) /**< (AFEC_CGR) AFEC Channel Gain Register Offset */ +#define AFEC_DIFFR_REG_OFST (0x60) /**< (AFEC_DIFFR) AFEC Channel Differential Register Offset */ +#define AFEC_CSELR_REG_OFST (0x64) /**< (AFEC_CSELR) AFEC Channel Selection Register Offset */ +#define AFEC_CDR_REG_OFST (0x68) /**< (AFEC_CDR) AFEC Channel Data Register Offset */ +#define AFEC_COCR_REG_OFST (0x6C) /**< (AFEC_COCR) AFEC Channel Offset Compensation Register Offset */ +#define AFEC_TEMPMR_REG_OFST (0x70) /**< (AFEC_TEMPMR) AFEC Temperature Sensor Mode Register Offset */ +#define AFEC_TEMPCWR_REG_OFST (0x74) /**< (AFEC_TEMPCWR) AFEC Temperature Compare Window Register Offset */ +#define AFEC_ACR_REG_OFST (0x94) /**< (AFEC_ACR) AFEC Analog Control Register Offset */ +#define AFEC_SHMR_REG_OFST (0xA0) /**< (AFEC_SHMR) AFEC Sample & Hold Mode Register Offset */ +#define AFEC_COSR_REG_OFST (0xD0) /**< (AFEC_COSR) AFEC Correction Select Register Offset */ +#define AFEC_CVR_REG_OFST (0xD4) /**< (AFEC_CVR) AFEC Correction Values Register Offset */ +#define AFEC_CECR_REG_OFST (0xD8) /**< (AFEC_CECR) AFEC Channel Error Correction Register Offset */ +#define AFEC_WPMR_REG_OFST (0xE4) /**< (AFEC_WPMR) AFEC Write Protection Mode Register Offset */ +#define AFEC_WPSR_REG_OFST (0xE8) /**< (AFEC_WPSR) AFEC Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief AFEC register API structure */ +typedef struct +{ + __O uint32_t AFEC_CR; /**< Offset: 0x00 ( /W 32) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< Offset: 0x04 (R/W 32) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< Offset: 0x08 (R/W 32) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< Offset: 0x0C (R/W 32) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< Offset: 0x10 (R/W 32) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< Offset: 0x14 ( /W 32) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< Offset: 0x18 ( /W 32) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< Offset: 0x1C (R/ 32) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< Offset: 0x20 (R/ 32) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< Offset: 0x24 ( /W 32) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< Offset: 0x28 ( /W 32) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< Offset: 0x2C (R/ 32) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< Offset: 0x30 (R/ 32) AFEC Interrupt Status Register */ + __I uint8_t Reserved1[0x18]; + __I uint32_t AFEC_OVER; /**< Offset: 0x4C (R/ 32) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< Offset: 0x50 (R/W 32) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< Offset: 0x54 (R/W 32) AFEC Channel Gain Register */ + __I uint8_t Reserved2[0x08]; + __IO uint32_t AFEC_DIFFR; /**< Offset: 0x60 (R/W 32) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< Offset: 0x64 (R/W 32) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< Offset: 0x68 (R/ 32) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< Offset: 0x6C (R/W 32) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< Offset: 0x70 (R/W 32) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< Offset: 0x74 (R/W 32) AFEC Temperature Compare Window Register */ + __I uint8_t Reserved3[0x1C]; + __IO uint32_t AFEC_ACR; /**< Offset: 0x94 (R/W 32) AFEC Analog Control Register */ + __I uint8_t Reserved4[0x08]; + __IO uint32_t AFEC_SHMR; /**< Offset: 0xA0 (R/W 32) AFEC Sample & Hold Mode Register */ + __I uint8_t Reserved5[0x2C]; + __IO uint32_t AFEC_COSR; /**< Offset: 0xD0 (R/W 32) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< Offset: 0xD4 (R/W 32) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< Offset: 0xD8 (R/W 32) AFEC Channel Error Correction Register */ + __I uint8_t Reserved6[0x08]; + __IO uint32_t AFEC_WPMR; /**< Offset: 0xE4 (R/W 32) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< Offset: 0xE8 (R/ 32) AFEC Write Protection Status Register */ +} afec_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_AFEC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/chipid.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/chipid.h new file mode 100644 index 00000000..0c93813e --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/chipid.h @@ -0,0 +1,188 @@ +/** + * \brief Component description for CHIPID + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_CHIPID_COMPONENT_H_ +#define _SAME70_CHIPID_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR CHIPID */ +/* ************************************************************************** */ + +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) ( R/ 32) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos _U_(0) /**< (CHIPID_CIDR) Version of the Device Position */ +#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */ +#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos)) +#define CHIPID_CIDR_EPROC_Pos _U_(5) /**< (CHIPID_CIDR) Embedded Processor Position */ +#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */ +#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos)) +#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */ +#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */ +#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */ +#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */ +#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */ +#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */ +#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */ +#define CHIPID_CIDR_NVPSIZ_Pos _U_(8) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos)) +#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_Pos _U_(12) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */ +#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */ +#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos)) +#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */ +#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ +#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_Pos _U_(16) /**< (CHIPID_CIDR) Internal SRAM Size Position */ +#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */ +#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos)) +#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */ +#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ +#define CHIPID_CIDR_ARCH_Pos _U_(20) /**< (CHIPID_CIDR) Architecture Identifier Position */ +#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */ +#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos)) +#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */ +#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */ +#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */ +#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */ +#define CHIPID_CIDR_NVPTYP_Pos _U_(28) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */ +#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */ +#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos)) +#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */ +#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */ +#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */ +#define CHIPID_CIDR_EXT_Pos _U_(31) /**< (CHIPID_CIDR) Extension Flag Position */ +#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */ +#define CHIPID_CIDR_EXT(value) (CHIPID_CIDR_EXT_Msk & ((value) << CHIPID_CIDR_EXT_Pos)) +#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */ + + +/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) ( R/ 32) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos _U_(0) /**< (CHIPID_EXID) Chip ID Extension Position */ +#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */ +#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos)) +#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */ + + +/** \brief CHIPID register offsets definitions */ +#define CHIPID_CIDR_REG_OFST (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */ +#define CHIPID_EXID_REG_OFST (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief CHIPID register API structure */ +typedef struct +{ + __I uint32_t CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */ +} chipid_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_CHIPID_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/dacc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/dacc.h new file mode 100644 index 00000000..0d5aef2e --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/dacc.h @@ -0,0 +1,387 @@ +/** + * \brief Component description for DACC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_DACC_COMPONENT_H_ +#define _SAME70_DACC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR DACC */ +/* ************************************************************************** */ + +/* -------- DACC_CR : (DACC Offset: 0x00) ( /W 32) Control Register -------- */ +#define DACC_CR_SWRST_Pos _U_(0) /**< (DACC_CR) Software Reset Position */ +#define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */ +#define DACC_CR_SWRST(value) (DACC_CR_SWRST_Msk & ((value) << DACC_CR_SWRST_Pos)) +#define DACC_CR_Msk _U_(0x00000001) /**< (DACC_CR) Register Mask */ + + +/* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define DACC_MR_MAXS0_Pos _U_(0) /**< (DACC_MR) Max Speed Mode for Channel 0 Position */ +#define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */ +#define DACC_MR_MAXS0(value) (DACC_MR_MAXS0_Msk & ((value) << DACC_MR_MAXS0_Pos)) +#define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_MAXS1_Pos _U_(1) /**< (DACC_MR) Max Speed Mode for Channel 1 Position */ +#define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */ +#define DACC_MR_MAXS1(value) (DACC_MR_MAXS1_Msk & ((value) << DACC_MR_MAXS1_Pos)) +#define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */ +#define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */ +#define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */ +#define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */ +#define DACC_MR_WORD_Pos _U_(4) /**< (DACC_MR) Word Transfer Mode Position */ +#define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */ +#define DACC_MR_WORD(value) (DACC_MR_WORD_Msk & ((value) << DACC_MR_WORD_Pos)) +#define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */ +#define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */ +#define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */ +#define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */ +#define DACC_MR_ZERO_Pos _U_(5) /**< (DACC_MR) Must always be written to 0. Position */ +#define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */ +#define DACC_MR_ZERO(value) (DACC_MR_ZERO_Msk & ((value) << DACC_MR_ZERO_Pos)) +#define DACC_MR_DIFF_Pos _U_(23) /**< (DACC_MR) Differential Mode Position */ +#define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */ +#define DACC_MR_DIFF(value) (DACC_MR_DIFF_Msk & ((value) << DACC_MR_DIFF_Pos)) +#define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */ +#define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */ +#define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */ +#define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */ +#define DACC_MR_PRESCALER_Pos _U_(24) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */ +#define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */ +#define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)) +#define DACC_MR_Msk _U_(0x0F800033) /**< (DACC_MR) Register Mask */ + +#define DACC_MR_MAXS_Pos _U_(0) /**< (DACC_MR Position) Max Speed Mode for Channel x */ +#define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */ +#define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos)) + +/* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0_Pos _U_(0) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */ +#define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */ +#define DACC_TRIGR_TRGEN0(value) (DACC_TRIGR_TRGEN0_Msk & ((value) << DACC_TRIGR_TRGEN0_Pos)) +#define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGEN1_Pos _U_(1) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */ +#define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */ +#define DACC_TRIGR_TRGEN1(value) (DACC_TRIGR_TRGEN1_Msk & ((value) << DACC_TRIGR_TRGEN1_Pos)) +#define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */ +#define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */ +#define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */ +#define DACC_TRIGR_TRGSEL0_Pos _U_(4) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */ +#define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */ +#define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)) +#define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 Event Line 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 Event Line 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 Event Line 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 Event Line 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL1_Pos _U_(8) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */ +#define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */ +#define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)) +#define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 Event Line 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 Event Line 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 Event Line 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 Event Line 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DAC External Trigger Input (DATRG) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 0 Output (TIOA0) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 1 Output (TIOA1) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 Channel 2 Output (TIOA2) Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 Event Line 1 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 Event Line 0 Position */ +#define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 Event Line 1 Position */ +#define DACC_TRIGR_OSR0_Pos _U_(16) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */ +#define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */ +#define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)) +#define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_OSR1_Pos _U_(20) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */ +#define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */ +#define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)) +#define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */ +#define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */ +#define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */ +#define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */ +#define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */ +#define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */ +#define DACC_TRIGR_Msk _U_(0x00770773) /**< (DACC_TRIGR) Register Mask */ + +#define DACC_TRIGR_TRGEN_Pos _U_(0) /**< (DACC_TRIGR Position) Trigger Enable of Channel x */ +#define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */ +#define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos)) + +/* -------- DACC_CHER : (DACC Offset: 0x10) ( /W 32) Channel Enable Register -------- */ +#define DACC_CHER_CH0_Pos _U_(0) /**< (DACC_CHER) Channel 0 Enable Position */ +#define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */ +#define DACC_CHER_CH0(value) (DACC_CHER_CH0_Msk & ((value) << DACC_CHER_CH0_Pos)) +#define DACC_CHER_CH1_Pos _U_(1) /**< (DACC_CHER) Channel 1 Enable Position */ +#define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */ +#define DACC_CHER_CH1(value) (DACC_CHER_CH1_Msk & ((value) << DACC_CHER_CH1_Pos)) +#define DACC_CHER_Msk _U_(0x00000003) /**< (DACC_CHER) Register Mask */ + +#define DACC_CHER_CH_Pos _U_(0) /**< (DACC_CHER Position) Channel x Enable */ +#define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */ +#define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos)) + +/* -------- DACC_CHDR : (DACC Offset: 0x14) ( /W 32) Channel Disable Register -------- */ +#define DACC_CHDR_CH0_Pos _U_(0) /**< (DACC_CHDR) Channel 0 Disable Position */ +#define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */ +#define DACC_CHDR_CH0(value) (DACC_CHDR_CH0_Msk & ((value) << DACC_CHDR_CH0_Pos)) +#define DACC_CHDR_CH1_Pos _U_(1) /**< (DACC_CHDR) Channel 1 Disable Position */ +#define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */ +#define DACC_CHDR_CH1(value) (DACC_CHDR_CH1_Msk & ((value) << DACC_CHDR_CH1_Pos)) +#define DACC_CHDR_Msk _U_(0x00000003) /**< (DACC_CHDR) Register Mask */ + +#define DACC_CHDR_CH_Pos _U_(0) /**< (DACC_CHDR Position) Channel x Disable */ +#define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */ +#define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos)) + +/* -------- DACC_CHSR : (DACC Offset: 0x18) ( R/ 32) Channel Status Register -------- */ +#define DACC_CHSR_CH0_Pos _U_(0) /**< (DACC_CHSR) Channel 0 Status Position */ +#define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */ +#define DACC_CHSR_CH0(value) (DACC_CHSR_CH0_Msk & ((value) << DACC_CHSR_CH0_Pos)) +#define DACC_CHSR_CH1_Pos _U_(1) /**< (DACC_CHSR) Channel 1 Status Position */ +#define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */ +#define DACC_CHSR_CH1(value) (DACC_CHSR_CH1_Msk & ((value) << DACC_CHSR_CH1_Pos)) +#define DACC_CHSR_DACRDY0_Pos _U_(8) /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY0(value) (DACC_CHSR_DACRDY0_Msk & ((value) << DACC_CHSR_DACRDY0_Pos)) +#define DACC_CHSR_DACRDY1_Pos _U_(9) /**< (DACC_CHSR) DAC Ready Flag Position */ +#define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */ +#define DACC_CHSR_DACRDY1(value) (DACC_CHSR_DACRDY1_Msk & ((value) << DACC_CHSR_DACRDY1_Pos)) +#define DACC_CHSR_Msk _U_(0x00000303) /**< (DACC_CHSR) Register Mask */ + +#define DACC_CHSR_CH_Pos _U_(0) /**< (DACC_CHSR Position) Channel x Status */ +#define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */ +#define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos)) +#define DACC_CHSR_DACRDY_Pos _U_(8) /**< (DACC_CHSR Position) DAC Ready Flag */ +#define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */ +#define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos)) + +/* -------- DACC_CDR : (DACC Offset: 0x1C) ( /W 32) Conversion Data Register 0 -------- */ +#define DACC_CDR_DATA0_Pos _U_(0) /**< (DACC_CDR) Data to Convert for channel 0 Position */ +#define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */ +#define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)) +#define DACC_CDR_DATA1_Pos _U_(16) /**< (DACC_CDR) Data to Convert for channel 1 Position */ +#define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */ +#define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)) +#define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */ + + +/* -------- DACC_IER : (DACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0_Pos _U_(0) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */ +#define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */ +#define DACC_IER_TXRDY0(value) (DACC_IER_TXRDY0_Msk & ((value) << DACC_IER_TXRDY0_Pos)) +#define DACC_IER_TXRDY1_Pos _U_(1) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */ +#define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */ +#define DACC_IER_TXRDY1(value) (DACC_IER_TXRDY1_Msk & ((value) << DACC_IER_TXRDY1_Pos)) +#define DACC_IER_EOC0_Pos _U_(4) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */ +#define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */ +#define DACC_IER_EOC0(value) (DACC_IER_EOC0_Msk & ((value) << DACC_IER_EOC0_Pos)) +#define DACC_IER_EOC1_Pos _U_(5) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */ +#define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */ +#define DACC_IER_EOC1(value) (DACC_IER_EOC1_Msk & ((value) << DACC_IER_EOC1_Pos)) +#define DACC_IER_Msk _U_(0x00000033) /**< (DACC_IER) Register Mask */ + +#define DACC_IER_TXRDY_Pos _U_(0) /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */ +#define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */ +#define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos)) +#define DACC_IER_EOC_Pos _U_(4) /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */ +#define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */ +#define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos)) + +/* -------- DACC_IDR : (DACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0_Pos _U_(0) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */ +#define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_TXRDY0(value) (DACC_IDR_TXRDY0_Msk & ((value) << DACC_IDR_TXRDY0_Pos)) +#define DACC_IDR_TXRDY1_Pos _U_(1) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */ +#define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_TXRDY1(value) (DACC_IDR_TXRDY1_Msk & ((value) << DACC_IDR_TXRDY1_Pos)) +#define DACC_IDR_EOC0_Pos _U_(4) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */ +#define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */ +#define DACC_IDR_EOC0(value) (DACC_IDR_EOC0_Msk & ((value) << DACC_IDR_EOC0_Pos)) +#define DACC_IDR_EOC1_Pos _U_(5) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */ +#define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */ +#define DACC_IDR_EOC1(value) (DACC_IDR_EOC1_Msk & ((value) << DACC_IDR_EOC1_Pos)) +#define DACC_IDR_Msk _U_(0x00000033) /**< (DACC_IDR) Register Mask */ + +#define DACC_IDR_TXRDY_Pos _U_(0) /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */ +#define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */ +#define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos)) +#define DACC_IDR_EOC_Pos _U_(4) /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */ +#define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */ +#define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos)) + +/* -------- DACC_IMR : (DACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0_Pos _U_(0) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */ +#define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_TXRDY0(value) (DACC_IMR_TXRDY0_Msk & ((value) << DACC_IMR_TXRDY0_Pos)) +#define DACC_IMR_TXRDY1_Pos _U_(1) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */ +#define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_TXRDY1(value) (DACC_IMR_TXRDY1_Msk & ((value) << DACC_IMR_TXRDY1_Pos)) +#define DACC_IMR_EOC0_Pos _U_(4) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */ +#define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */ +#define DACC_IMR_EOC0(value) (DACC_IMR_EOC0_Msk & ((value) << DACC_IMR_EOC0_Pos)) +#define DACC_IMR_EOC1_Pos _U_(5) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */ +#define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */ +#define DACC_IMR_EOC1(value) (DACC_IMR_EOC1_Msk & ((value) << DACC_IMR_EOC1_Pos)) +#define DACC_IMR_Msk _U_(0x00000033) /**< (DACC_IMR) Register Mask */ + +#define DACC_IMR_TXRDY_Pos _U_(0) /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */ +#define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */ +#define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos)) +#define DACC_IMR_EOC_Pos _U_(4) /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */ +#define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */ +#define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos)) + +/* -------- DACC_ISR : (DACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0_Pos _U_(0) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */ +#define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_TXRDY0(value) (DACC_ISR_TXRDY0_Msk & ((value) << DACC_ISR_TXRDY0_Pos)) +#define DACC_ISR_TXRDY1_Pos _U_(1) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */ +#define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_TXRDY1(value) (DACC_ISR_TXRDY1_Msk & ((value) << DACC_ISR_TXRDY1_Pos)) +#define DACC_ISR_EOC0_Pos _U_(4) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */ +#define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */ +#define DACC_ISR_EOC0(value) (DACC_ISR_EOC0_Msk & ((value) << DACC_ISR_EOC0_Pos)) +#define DACC_ISR_EOC1_Pos _U_(5) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */ +#define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */ +#define DACC_ISR_EOC1(value) (DACC_ISR_EOC1_Msk & ((value) << DACC_ISR_EOC1_Pos)) +#define DACC_ISR_Msk _U_(0x00000033) /**< (DACC_ISR) Register Mask */ + +#define DACC_ISR_TXRDY_Pos _U_(0) /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */ +#define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */ +#define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos)) +#define DACC_ISR_EOC_Pos _U_(4) /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */ +#define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */ +#define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos)) + +/* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos _U_(0) /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)) +#define DACC_ACR_IBCTLCH1_Pos _U_(2) /**< (DACC_ACR) Analog Output Current Control Position */ +#define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */ +#define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)) +#define DACC_ACR_Msk _U_(0x0000000F) /**< (DACC_ACR) Register Mask */ + + +/* -------- DACC_WPMR : (DACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define DACC_WPMR_WPEN_Pos _U_(0) /**< (DACC_WPMR) Write Protection Enable Position */ +#define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */ +#define DACC_WPMR_WPEN(value) (DACC_WPMR_WPEN_Msk & ((value) << DACC_WPMR_WPEN_Pos)) +#define DACC_WPMR_WPKEY_Pos _U_(8) /**< (DACC_WPMR) Write Protect Key Position */ +#define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */ +#define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)) +#define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +#define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */ +#define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */ + + +/* -------- DACC_WPSR : (DACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define DACC_WPSR_WPVS_Pos _U_(0) /**< (DACC_WPSR) Write Protection Violation Status Position */ +#define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */ +#define DACC_WPSR_WPVS(value) (DACC_WPSR_WPVS_Msk & ((value) << DACC_WPSR_WPVS_Pos)) +#define DACC_WPSR_WPVSRC_Pos _U_(8) /**< (DACC_WPSR) Write Protection Violation Source Position */ +#define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */ +#define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos)) +#define DACC_WPSR_Msk _U_(0x0000FF01) /**< (DACC_WPSR) Register Mask */ + + +/** \brief DACC register offsets definitions */ +#define DACC_CR_REG_OFST (0x00) /**< (DACC_CR) Control Register Offset */ +#define DACC_MR_REG_OFST (0x04) /**< (DACC_MR) Mode Register Offset */ +#define DACC_TRIGR_REG_OFST (0x08) /**< (DACC_TRIGR) Trigger Register Offset */ +#define DACC_CHER_REG_OFST (0x10) /**< (DACC_CHER) Channel Enable Register Offset */ +#define DACC_CHDR_REG_OFST (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */ +#define DACC_CHSR_REG_OFST (0x18) /**< (DACC_CHSR) Channel Status Register Offset */ +#define DACC_CDR_REG_OFST (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */ +#define DACC_IER_REG_OFST (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */ +#define DACC_IDR_REG_OFST (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */ +#define DACC_IMR_REG_OFST (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */ +#define DACC_ISR_REG_OFST (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */ +#define DACC_ACR_REG_OFST (0x94) /**< (DACC_ACR) Analog Current Register Offset */ +#define DACC_WPMR_REG_OFST (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */ +#define DACC_WPSR_REG_OFST (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief DACC register API structure */ +typedef struct +{ + __O uint32_t DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */ + __O uint32_t DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x60]; + __IO uint32_t DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */ + __I uint8_t Reserved3[0x4C]; + __IO uint32_t DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} dacc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_DACC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/efc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/efc.h new file mode 100644 index 00000000..e17d4be1 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/efc.h @@ -0,0 +1,172 @@ +/** + * \brief Component description for EFC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_EFC_COMPONENT_H_ +#define _SAME70_EFC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR EFC */ +/* ************************************************************************** */ + +/* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY_Pos _U_(0) /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */ +#define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */ +#define EEFC_FMR_FRDY(value) (EEFC_FMR_FRDY_Msk & ((value) << EEFC_FMR_FRDY_Pos)) +#define EEFC_FMR_FWS_Pos _U_(8) /**< (EEFC_FMR) Flash Wait State Position */ +#define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */ +#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)) +#define EEFC_FMR_SCOD_Pos _U_(16) /**< (EEFC_FMR) Sequential Code Optimization Disable Position */ +#define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */ +#define EEFC_FMR_SCOD(value) (EEFC_FMR_SCOD_Msk & ((value) << EEFC_FMR_SCOD_Pos)) +#define EEFC_FMR_CLOE_Pos _U_(26) /**< (EEFC_FMR) Code Loop Optimization Enable Position */ +#define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */ +#define EEFC_FMR_CLOE(value) (EEFC_FMR_CLOE_Msk & ((value) << EEFC_FMR_CLOE_Pos)) +#define EEFC_FMR_Msk _U_(0x04010F01) /**< (EEFC_FMR) Register Mask */ + + +/* -------- EEFC_FCR : (EFC Offset: 0x04) ( /W 32) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos _U_(0) /**< (EEFC_FCR) Flash Command Position */ +#define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */ +#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)) +#define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */ +#define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */ +#define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */ +#define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */ +#define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */ +#define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */ +#define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */ +#define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */ +#define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */ +#define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */ +#define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */ +#define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */ +#define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */ +#define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */ +#define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */ +#define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */ +#define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */ +#define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */ +#define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */ +#define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */ +#define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */ +#define EEFC_FCR_FARG_Pos _U_(8) /**< (EEFC_FCR) Flash Command Argument Position */ +#define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */ +#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)) +#define EEFC_FCR_FKEY_Pos _U_(24) /**< (EEFC_FCR) Flash Writing Protection Key Position */ +#define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */ +#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)) +#define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +#define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */ +#define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */ + + +/* -------- EEFC_FSR : (EFC Offset: 0x08) ( R/ 32) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY_Pos _U_(0) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */ +#define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */ +#define EEFC_FSR_FRDY(value) (EEFC_FSR_FRDY_Msk & ((value) << EEFC_FSR_FRDY_Pos)) +#define EEFC_FSR_FCMDE_Pos _U_(1) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */ +#define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */ +#define EEFC_FSR_FCMDE(value) (EEFC_FSR_FCMDE_Msk & ((value) << EEFC_FSR_FCMDE_Pos)) +#define EEFC_FSR_FLOCKE_Pos _U_(2) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */ +#define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */ +#define EEFC_FSR_FLOCKE(value) (EEFC_FSR_FLOCKE_Msk & ((value) << EEFC_FSR_FLOCKE_Pos)) +#define EEFC_FSR_FLERR_Pos _U_(3) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */ +#define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */ +#define EEFC_FSR_FLERR(value) (EEFC_FSR_FLERR_Msk & ((value) << EEFC_FSR_FLERR_Pos)) +#define EEFC_FSR_UECCELSB_Pos _U_(16) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCELSB(value) (EEFC_FSR_UECCELSB_Msk & ((value) << EEFC_FSR_UECCELSB_Pos)) +#define EEFC_FSR_MECCELSB_Pos _U_(17) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCELSB(value) (EEFC_FSR_MECCELSB_Msk & ((value) << EEFC_FSR_MECCELSB_Pos)) +#define EEFC_FSR_UECCEMSB_Pos _U_(18) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_UECCEMSB(value) (EEFC_FSR_UECCEMSB_Msk & ((value) << EEFC_FSR_UECCEMSB_Pos)) +#define EEFC_FSR_MECCEMSB_Pos _U_(19) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ +#define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ +#define EEFC_FSR_MECCEMSB(value) (EEFC_FSR_MECCEMSB_Msk & ((value) << EEFC_FSR_MECCEMSB_Pos)) +#define EEFC_FSR_Msk _U_(0x000F000F) /**< (EEFC_FSR) Register Mask */ + + +/* -------- EEFC_FRR : (EFC Offset: 0x0C) ( R/ 32) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos _U_(0) /**< (EEFC_FRR) Flash Result Value Position */ +#define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */ +#define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos)) +#define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */ + + +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN_Pos _U_(0) /**< (EEFC_WPMR) Write Protection Enable Position */ +#define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */ +#define EEFC_WPMR_WPEN(value) (EEFC_WPMR_WPEN_Msk & ((value) << EEFC_WPMR_WPEN_Pos)) +#define EEFC_WPMR_WPKEY_Pos _U_(8) /**< (EEFC_WPMR) Write Protection Key Position */ +#define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */ +#define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)) +#define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */ + + +/** \brief EFC register offsets definitions */ +#define EEFC_FMR_REG_OFST (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */ +#define EEFC_FCR_REG_OFST (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */ +#define EEFC_FSR_REG_OFST (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */ +#define EEFC_FRR_REG_OFST (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */ +#define EEFC_WPMR_REG_OFST (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief EFC register API structure */ +typedef struct +{ + __IO uint32_t EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */ + __I uint8_t Reserved1[0xD4]; + __IO uint32_t EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} efc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_EFC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/gmac.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/gmac.h new file mode 100644 index 00000000..9e3f5ef2 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/gmac.h @@ -0,0 +1,1839 @@ +/** + * \brief Component description for GMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_GMAC_COMPONENT_H_ +#define _SAME70_GMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR GMAC */ +/* ************************************************************************** */ + +/* -------- GMAC_SAB : (GMAC Offset: 0x00) (R/W 32) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos _U_(0) /**< (GMAC_SAB) Specific Address 1 Position */ +#define GMAC_SAB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAB_ADDR_Pos) /**< (GMAC_SAB) Specific Address 1 Mask */ +#define GMAC_SAB_ADDR(value) (GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)) +#define GMAC_SAB_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAB) Register Mask */ + + +/* -------- GMAC_SAT : (GMAC Offset: 0x04) (R/W 32) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos _U_(0) /**< (GMAC_SAT) Specific Address 1 Position */ +#define GMAC_SAT_ADDR_Msk (_U_(0xFFFF) << GMAC_SAT_ADDR_Pos) /**< (GMAC_SAT) Specific Address 1 Mask */ +#define GMAC_SAT_ADDR(value) (GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)) +#define GMAC_SAT_Msk _U_(0x0000FFFF) /**< (GMAC_SAT) Register Mask */ + + +/* -------- GMAC_ST2CW0 : (GMAC Offset: 0x00) (R/W 32) Screening Type 2 Compare Word 0 Register -------- */ +#define GMAC_ST2CW0_MASKVAL_Pos _U_(0) /**< (GMAC_ST2CW0) Mask Value Position */ +#define GMAC_ST2CW0_MASKVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_MASKVAL_Pos) /**< (GMAC_ST2CW0) Mask Value Mask */ +#define GMAC_ST2CW0_MASKVAL(value) (GMAC_ST2CW0_MASKVAL_Msk & ((value) << GMAC_ST2CW0_MASKVAL_Pos)) +#define GMAC_ST2CW0_COMPVAL_Pos _U_(16) /**< (GMAC_ST2CW0) Compare Value Position */ +#define GMAC_ST2CW0_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2CW0_COMPVAL_Pos) /**< (GMAC_ST2CW0) Compare Value Mask */ +#define GMAC_ST2CW0_COMPVAL(value) (GMAC_ST2CW0_COMPVAL_Msk & ((value) << GMAC_ST2CW0_COMPVAL_Pos)) +#define GMAC_ST2CW0_Msk _U_(0xFFFFFFFF) /**< (GMAC_ST2CW0) Register Mask */ + + +/* -------- GMAC_ST2CW1 : (GMAC Offset: 0x04) (R/W 32) Screening Type 2 Compare Word 1 Register -------- */ +#define GMAC_ST2CW1_OFFSVAL_Pos _U_(0) /**< (GMAC_ST2CW1) Offset Value in Bytes Position */ +#define GMAC_ST2CW1_OFFSVAL_Msk (_U_(0x7F) << GMAC_ST2CW1_OFFSVAL_Pos) /**< (GMAC_ST2CW1) Offset Value in Bytes Mask */ +#define GMAC_ST2CW1_OFFSVAL(value) (GMAC_ST2CW1_OFFSVAL_Msk & ((value) << GMAC_ST2CW1_OFFSVAL_Pos)) +#define GMAC_ST2CW1_OFFSSTRT_Pos _U_(7) /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Position */ +#define GMAC_ST2CW1_OFFSSTRT_Msk (_U_(0x3) << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Ethernet Frame Offset Start Mask */ +#define GMAC_ST2CW1_OFFSSTRT(value) (GMAC_ST2CW1_OFFSSTRT_Msk & ((value) << GMAC_ST2CW1_OFFSSTRT_Pos)) +#define GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val _U_(0x0) /**< (GMAC_ST2CW1) Offset from the start of the frame */ +#define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val _U_(0x1) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field */ +#define GMAC_ST2CW1_OFFSSTRT_IP_Val _U_(0x2) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field */ +#define GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val _U_(0x3) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field */ +#define GMAC_ST2CW1_OFFSSTRT_FRAMESTART (GMAC_ST2CW1_OFFSSTRT_FRAMESTART_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the start of the frame Position */ +#define GMAC_ST2CW1_OFFSSTRT_ETHERTYPE (GMAC_ST2CW1_OFFSSTRT_ETHERTYPE_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the EtherType field Position */ +#define GMAC_ST2CW1_OFFSSTRT_IP (GMAC_ST2CW1_OFFSSTRT_IP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the IP header field Position */ +#define GMAC_ST2CW1_OFFSSTRT_TCP_UDP (GMAC_ST2CW1_OFFSSTRT_TCP_UDP_Val << GMAC_ST2CW1_OFFSSTRT_Pos) /**< (GMAC_ST2CW1) Offset from the byte after the TCP/UDP header field Position */ +#define GMAC_ST2CW1_Msk _U_(0x000001FF) /**< (GMAC_ST2CW1) Register Mask */ + + +/* -------- GMAC_NCR : (GMAC Offset: 0x00) (R/W 32) Network Control Register -------- */ +#define GMAC_NCR_LBL_Pos _U_(1) /**< (GMAC_NCR) Loop Back Local Position */ +#define GMAC_NCR_LBL_Msk (_U_(0x1) << GMAC_NCR_LBL_Pos) /**< (GMAC_NCR) Loop Back Local Mask */ +#define GMAC_NCR_LBL(value) (GMAC_NCR_LBL_Msk & ((value) << GMAC_NCR_LBL_Pos)) +#define GMAC_NCR_RXEN_Pos _U_(2) /**< (GMAC_NCR) Receive Enable Position */ +#define GMAC_NCR_RXEN_Msk (_U_(0x1) << GMAC_NCR_RXEN_Pos) /**< (GMAC_NCR) Receive Enable Mask */ +#define GMAC_NCR_RXEN(value) (GMAC_NCR_RXEN_Msk & ((value) << GMAC_NCR_RXEN_Pos)) +#define GMAC_NCR_TXEN_Pos _U_(3) /**< (GMAC_NCR) Transmit Enable Position */ +#define GMAC_NCR_TXEN_Msk (_U_(0x1) << GMAC_NCR_TXEN_Pos) /**< (GMAC_NCR) Transmit Enable Mask */ +#define GMAC_NCR_TXEN(value) (GMAC_NCR_TXEN_Msk & ((value) << GMAC_NCR_TXEN_Pos)) +#define GMAC_NCR_MPE_Pos _U_(4) /**< (GMAC_NCR) Management Port Enable Position */ +#define GMAC_NCR_MPE_Msk (_U_(0x1) << GMAC_NCR_MPE_Pos) /**< (GMAC_NCR) Management Port Enable Mask */ +#define GMAC_NCR_MPE(value) (GMAC_NCR_MPE_Msk & ((value) << GMAC_NCR_MPE_Pos)) +#define GMAC_NCR_CLRSTAT_Pos _U_(5) /**< (GMAC_NCR) Clear Statistics Registers Position */ +#define GMAC_NCR_CLRSTAT_Msk (_U_(0x1) << GMAC_NCR_CLRSTAT_Pos) /**< (GMAC_NCR) Clear Statistics Registers Mask */ +#define GMAC_NCR_CLRSTAT(value) (GMAC_NCR_CLRSTAT_Msk & ((value) << GMAC_NCR_CLRSTAT_Pos)) +#define GMAC_NCR_INCSTAT_Pos _U_(6) /**< (GMAC_NCR) Increment Statistics Registers Position */ +#define GMAC_NCR_INCSTAT_Msk (_U_(0x1) << GMAC_NCR_INCSTAT_Pos) /**< (GMAC_NCR) Increment Statistics Registers Mask */ +#define GMAC_NCR_INCSTAT(value) (GMAC_NCR_INCSTAT_Msk & ((value) << GMAC_NCR_INCSTAT_Pos)) +#define GMAC_NCR_WESTAT_Pos _U_(7) /**< (GMAC_NCR) Write Enable for Statistics Registers Position */ +#define GMAC_NCR_WESTAT_Msk (_U_(0x1) << GMAC_NCR_WESTAT_Pos) /**< (GMAC_NCR) Write Enable for Statistics Registers Mask */ +#define GMAC_NCR_WESTAT(value) (GMAC_NCR_WESTAT_Msk & ((value) << GMAC_NCR_WESTAT_Pos)) +#define GMAC_NCR_BP_Pos _U_(8) /**< (GMAC_NCR) Back pressure Position */ +#define GMAC_NCR_BP_Msk (_U_(0x1) << GMAC_NCR_BP_Pos) /**< (GMAC_NCR) Back pressure Mask */ +#define GMAC_NCR_BP(value) (GMAC_NCR_BP_Msk & ((value) << GMAC_NCR_BP_Pos)) +#define GMAC_NCR_TSTART_Pos _U_(9) /**< (GMAC_NCR) Start Transmission Position */ +#define GMAC_NCR_TSTART_Msk (_U_(0x1) << GMAC_NCR_TSTART_Pos) /**< (GMAC_NCR) Start Transmission Mask */ +#define GMAC_NCR_TSTART(value) (GMAC_NCR_TSTART_Msk & ((value) << GMAC_NCR_TSTART_Pos)) +#define GMAC_NCR_THALT_Pos _U_(10) /**< (GMAC_NCR) Transmit Halt Position */ +#define GMAC_NCR_THALT_Msk (_U_(0x1) << GMAC_NCR_THALT_Pos) /**< (GMAC_NCR) Transmit Halt Mask */ +#define GMAC_NCR_THALT(value) (GMAC_NCR_THALT_Msk & ((value) << GMAC_NCR_THALT_Pos)) +#define GMAC_NCR_TXPF_Pos _U_(11) /**< (GMAC_NCR) Transmit Pause Frame Position */ +#define GMAC_NCR_TXPF_Msk (_U_(0x1) << GMAC_NCR_TXPF_Pos) /**< (GMAC_NCR) Transmit Pause Frame Mask */ +#define GMAC_NCR_TXPF(value) (GMAC_NCR_TXPF_Msk & ((value) << GMAC_NCR_TXPF_Pos)) +#define GMAC_NCR_TXZQPF_Pos _U_(12) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Position */ +#define GMAC_NCR_TXZQPF_Msk (_U_(0x1) << GMAC_NCR_TXZQPF_Pos) /**< (GMAC_NCR) Transmit Zero Quantum Pause Frame Mask */ +#define GMAC_NCR_TXZQPF(value) (GMAC_NCR_TXZQPF_Msk & ((value) << GMAC_NCR_TXZQPF_Pos)) +#define GMAC_NCR_SRTSM_Pos _U_(15) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Position */ +#define GMAC_NCR_SRTSM_Msk (_U_(0x1) << GMAC_NCR_SRTSM_Pos) /**< (GMAC_NCR) Store Receive Time Stamp to Memory Mask */ +#define GMAC_NCR_SRTSM(value) (GMAC_NCR_SRTSM_Msk & ((value) << GMAC_NCR_SRTSM_Pos)) +#define GMAC_NCR_ENPBPR_Pos _U_(16) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Position */ +#define GMAC_NCR_ENPBPR_Msk (_U_(0x1) << GMAC_NCR_ENPBPR_Pos) /**< (GMAC_NCR) Enable PFC Priority-based Pause Reception Mask */ +#define GMAC_NCR_ENPBPR(value) (GMAC_NCR_ENPBPR_Msk & ((value) << GMAC_NCR_ENPBPR_Pos)) +#define GMAC_NCR_TXPBPF_Pos _U_(17) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Position */ +#define GMAC_NCR_TXPBPF_Msk (_U_(0x1) << GMAC_NCR_TXPBPF_Pos) /**< (GMAC_NCR) Transmit PFC Priority-based Pause Frame Mask */ +#define GMAC_NCR_TXPBPF(value) (GMAC_NCR_TXPBPF_Msk & ((value) << GMAC_NCR_TXPBPF_Pos)) +#define GMAC_NCR_FNP_Pos _U_(18) /**< (GMAC_NCR) Flush Next Packet Position */ +#define GMAC_NCR_FNP_Msk (_U_(0x1) << GMAC_NCR_FNP_Pos) /**< (GMAC_NCR) Flush Next Packet Mask */ +#define GMAC_NCR_FNP(value) (GMAC_NCR_FNP_Msk & ((value) << GMAC_NCR_FNP_Pos)) +#define GMAC_NCR_TXLPIEN_Pos _U_(19) /**< (GMAC_NCR) Enable LPI Transmission Position */ +#define GMAC_NCR_TXLPIEN_Msk (_U_(0x1) << GMAC_NCR_TXLPIEN_Pos) /**< (GMAC_NCR) Enable LPI Transmission Mask */ +#define GMAC_NCR_TXLPIEN(value) (GMAC_NCR_TXLPIEN_Msk & ((value) << GMAC_NCR_TXLPIEN_Pos)) +#define GMAC_NCR_Msk _U_(0x000F9FFE) /**< (GMAC_NCR) Register Mask */ + + +/* -------- GMAC_NCFGR : (GMAC Offset: 0x04) (R/W 32) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD_Pos _U_(0) /**< (GMAC_NCFGR) Speed Position */ +#define GMAC_NCFGR_SPD_Msk (_U_(0x1) << GMAC_NCFGR_SPD_Pos) /**< (GMAC_NCFGR) Speed Mask */ +#define GMAC_NCFGR_SPD(value) (GMAC_NCFGR_SPD_Msk & ((value) << GMAC_NCFGR_SPD_Pos)) +#define GMAC_NCFGR_FD_Pos _U_(1) /**< (GMAC_NCFGR) Full Duplex Position */ +#define GMAC_NCFGR_FD_Msk (_U_(0x1) << GMAC_NCFGR_FD_Pos) /**< (GMAC_NCFGR) Full Duplex Mask */ +#define GMAC_NCFGR_FD(value) (GMAC_NCFGR_FD_Msk & ((value) << GMAC_NCFGR_FD_Pos)) +#define GMAC_NCFGR_DNVLAN_Pos _U_(2) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Position */ +#define GMAC_NCFGR_DNVLAN_Msk (_U_(0x1) << GMAC_NCFGR_DNVLAN_Pos) /**< (GMAC_NCFGR) Discard Non-VLAN FRAMES Mask */ +#define GMAC_NCFGR_DNVLAN(value) (GMAC_NCFGR_DNVLAN_Msk & ((value) << GMAC_NCFGR_DNVLAN_Pos)) +#define GMAC_NCFGR_JFRAME_Pos _U_(3) /**< (GMAC_NCFGR) Jumbo Frame Size Position */ +#define GMAC_NCFGR_JFRAME_Msk (_U_(0x1) << GMAC_NCFGR_JFRAME_Pos) /**< (GMAC_NCFGR) Jumbo Frame Size Mask */ +#define GMAC_NCFGR_JFRAME(value) (GMAC_NCFGR_JFRAME_Msk & ((value) << GMAC_NCFGR_JFRAME_Pos)) +#define GMAC_NCFGR_CAF_Pos _U_(4) /**< (GMAC_NCFGR) Copy All Frames Position */ +#define GMAC_NCFGR_CAF_Msk (_U_(0x1) << GMAC_NCFGR_CAF_Pos) /**< (GMAC_NCFGR) Copy All Frames Mask */ +#define GMAC_NCFGR_CAF(value) (GMAC_NCFGR_CAF_Msk & ((value) << GMAC_NCFGR_CAF_Pos)) +#define GMAC_NCFGR_NBC_Pos _U_(5) /**< (GMAC_NCFGR) No Broadcast Position */ +#define GMAC_NCFGR_NBC_Msk (_U_(0x1) << GMAC_NCFGR_NBC_Pos) /**< (GMAC_NCFGR) No Broadcast Mask */ +#define GMAC_NCFGR_NBC(value) (GMAC_NCFGR_NBC_Msk & ((value) << GMAC_NCFGR_NBC_Pos)) +#define GMAC_NCFGR_MTIHEN_Pos _U_(6) /**< (GMAC_NCFGR) Multicast Hash Enable Position */ +#define GMAC_NCFGR_MTIHEN_Msk (_U_(0x1) << GMAC_NCFGR_MTIHEN_Pos) /**< (GMAC_NCFGR) Multicast Hash Enable Mask */ +#define GMAC_NCFGR_MTIHEN(value) (GMAC_NCFGR_MTIHEN_Msk & ((value) << GMAC_NCFGR_MTIHEN_Pos)) +#define GMAC_NCFGR_UNIHEN_Pos _U_(7) /**< (GMAC_NCFGR) Unicast Hash Enable Position */ +#define GMAC_NCFGR_UNIHEN_Msk (_U_(0x1) << GMAC_NCFGR_UNIHEN_Pos) /**< (GMAC_NCFGR) Unicast Hash Enable Mask */ +#define GMAC_NCFGR_UNIHEN(value) (GMAC_NCFGR_UNIHEN_Msk & ((value) << GMAC_NCFGR_UNIHEN_Pos)) +#define GMAC_NCFGR_MAXFS_Pos _U_(8) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Position */ +#define GMAC_NCFGR_MAXFS_Msk (_U_(0x1) << GMAC_NCFGR_MAXFS_Pos) /**< (GMAC_NCFGR) 1536 Maximum Frame Size Mask */ +#define GMAC_NCFGR_MAXFS(value) (GMAC_NCFGR_MAXFS_Msk & ((value) << GMAC_NCFGR_MAXFS_Pos)) +#define GMAC_NCFGR_RTY_Pos _U_(12) /**< (GMAC_NCFGR) Retry Test Position */ +#define GMAC_NCFGR_RTY_Msk (_U_(0x1) << GMAC_NCFGR_RTY_Pos) /**< (GMAC_NCFGR) Retry Test Mask */ +#define GMAC_NCFGR_RTY(value) (GMAC_NCFGR_RTY_Msk & ((value) << GMAC_NCFGR_RTY_Pos)) +#define GMAC_NCFGR_PEN_Pos _U_(13) /**< (GMAC_NCFGR) Pause Enable Position */ +#define GMAC_NCFGR_PEN_Msk (_U_(0x1) << GMAC_NCFGR_PEN_Pos) /**< (GMAC_NCFGR) Pause Enable Mask */ +#define GMAC_NCFGR_PEN(value) (GMAC_NCFGR_PEN_Msk & ((value) << GMAC_NCFGR_PEN_Pos)) +#define GMAC_NCFGR_RXBUFO_Pos _U_(14) /**< (GMAC_NCFGR) Receive Buffer Offset Position */ +#define GMAC_NCFGR_RXBUFO_Msk (_U_(0x3) << GMAC_NCFGR_RXBUFO_Pos) /**< (GMAC_NCFGR) Receive Buffer Offset Mask */ +#define GMAC_NCFGR_RXBUFO(value) (GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)) +#define GMAC_NCFGR_LFERD_Pos _U_(16) /**< (GMAC_NCFGR) Length Field Error Frame Discard Position */ +#define GMAC_NCFGR_LFERD_Msk (_U_(0x1) << GMAC_NCFGR_LFERD_Pos) /**< (GMAC_NCFGR) Length Field Error Frame Discard Mask */ +#define GMAC_NCFGR_LFERD(value) (GMAC_NCFGR_LFERD_Msk & ((value) << GMAC_NCFGR_LFERD_Pos)) +#define GMAC_NCFGR_RFCS_Pos _U_(17) /**< (GMAC_NCFGR) Remove FCS Position */ +#define GMAC_NCFGR_RFCS_Msk (_U_(0x1) << GMAC_NCFGR_RFCS_Pos) /**< (GMAC_NCFGR) Remove FCS Mask */ +#define GMAC_NCFGR_RFCS(value) (GMAC_NCFGR_RFCS_Msk & ((value) << GMAC_NCFGR_RFCS_Pos)) +#define GMAC_NCFGR_CLK_Pos _U_(18) /**< (GMAC_NCFGR) MDC CLock Division Position */ +#define GMAC_NCFGR_CLK_Msk (_U_(0x7) << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MDC CLock Division Mask */ +#define GMAC_NCFGR_CLK(value) (GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)) +#define GMAC_NCFGR_CLK_MCK_8_Val _U_(0x0) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16_Val _U_(0x1) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32_Val _U_(0x2) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48_Val _U_(0x3) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64_Val _U_(0x4) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96_Val _U_(0x5) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_CLK_MCK_8 (GMAC_NCFGR_CLK_MCK_8_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_16 (GMAC_NCFGR_CLK_MCK_16_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_32 (GMAC_NCFGR_CLK_MCK_32_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_48 (GMAC_NCFGR_CLK_MCK_48_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_64 (GMAC_NCFGR_CLK_MCK_64_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) Position */ +#define GMAC_NCFGR_CLK_MCK_96 (GMAC_NCFGR_CLK_MCK_96_Val << GMAC_NCFGR_CLK_Pos) /**< (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) Position */ +#define GMAC_NCFGR_DBW_Pos _U_(21) /**< (GMAC_NCFGR) Data Bus Width Position */ +#define GMAC_NCFGR_DBW_Msk (_U_(0x3) << GMAC_NCFGR_DBW_Pos) /**< (GMAC_NCFGR) Data Bus Width Mask */ +#define GMAC_NCFGR_DBW(value) (GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)) +#define GMAC_NCFGR_DCPF_Pos _U_(23) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Position */ +#define GMAC_NCFGR_DCPF_Msk (_U_(0x1) << GMAC_NCFGR_DCPF_Pos) /**< (GMAC_NCFGR) Disable Copy of Pause Frames Mask */ +#define GMAC_NCFGR_DCPF(value) (GMAC_NCFGR_DCPF_Msk & ((value) << GMAC_NCFGR_DCPF_Pos)) +#define GMAC_NCFGR_RXCOEN_Pos _U_(24) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Position */ +#define GMAC_NCFGR_RXCOEN_Msk (_U_(0x1) << GMAC_NCFGR_RXCOEN_Pos) /**< (GMAC_NCFGR) Receive Checksum Offload Enable Mask */ +#define GMAC_NCFGR_RXCOEN(value) (GMAC_NCFGR_RXCOEN_Msk & ((value) << GMAC_NCFGR_RXCOEN_Pos)) +#define GMAC_NCFGR_EFRHD_Pos _U_(25) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Position */ +#define GMAC_NCFGR_EFRHD_Msk (_U_(0x1) << GMAC_NCFGR_EFRHD_Pos) /**< (GMAC_NCFGR) Enable Frames Received in Half Duplex Mask */ +#define GMAC_NCFGR_EFRHD(value) (GMAC_NCFGR_EFRHD_Msk & ((value) << GMAC_NCFGR_EFRHD_Pos)) +#define GMAC_NCFGR_IRXFCS_Pos _U_(26) /**< (GMAC_NCFGR) Ignore RX FCS Position */ +#define GMAC_NCFGR_IRXFCS_Msk (_U_(0x1) << GMAC_NCFGR_IRXFCS_Pos) /**< (GMAC_NCFGR) Ignore RX FCS Mask */ +#define GMAC_NCFGR_IRXFCS(value) (GMAC_NCFGR_IRXFCS_Msk & ((value) << GMAC_NCFGR_IRXFCS_Pos)) +#define GMAC_NCFGR_IPGSEN_Pos _U_(28) /**< (GMAC_NCFGR) IP Stretch Enable Position */ +#define GMAC_NCFGR_IPGSEN_Msk (_U_(0x1) << GMAC_NCFGR_IPGSEN_Pos) /**< (GMAC_NCFGR) IP Stretch Enable Mask */ +#define GMAC_NCFGR_IPGSEN(value) (GMAC_NCFGR_IPGSEN_Msk & ((value) << GMAC_NCFGR_IPGSEN_Pos)) +#define GMAC_NCFGR_RXBP_Pos _U_(29) /**< (GMAC_NCFGR) Receive Bad Preamble Position */ +#define GMAC_NCFGR_RXBP_Msk (_U_(0x1) << GMAC_NCFGR_RXBP_Pos) /**< (GMAC_NCFGR) Receive Bad Preamble Mask */ +#define GMAC_NCFGR_RXBP(value) (GMAC_NCFGR_RXBP_Msk & ((value) << GMAC_NCFGR_RXBP_Pos)) +#define GMAC_NCFGR_IRXER_Pos _U_(30) /**< (GMAC_NCFGR) Ignore IPG GRXER Position */ +#define GMAC_NCFGR_IRXER_Msk (_U_(0x1) << GMAC_NCFGR_IRXER_Pos) /**< (GMAC_NCFGR) Ignore IPG GRXER Mask */ +#define GMAC_NCFGR_IRXER(value) (GMAC_NCFGR_IRXER_Msk & ((value) << GMAC_NCFGR_IRXER_Pos)) +#define GMAC_NCFGR_Msk _U_(0x77FFF1FF) /**< (GMAC_NCFGR) Register Mask */ + + +/* -------- GMAC_NSR : (GMAC Offset: 0x08) ( R/ 32) Network Status Register -------- */ +#define GMAC_NSR_MDIO_Pos _U_(1) /**< (GMAC_NSR) MDIO Input Status Position */ +#define GMAC_NSR_MDIO_Msk (_U_(0x1) << GMAC_NSR_MDIO_Pos) /**< (GMAC_NSR) MDIO Input Status Mask */ +#define GMAC_NSR_MDIO(value) (GMAC_NSR_MDIO_Msk & ((value) << GMAC_NSR_MDIO_Pos)) +#define GMAC_NSR_IDLE_Pos _U_(2) /**< (GMAC_NSR) PHY Management Logic Idle Position */ +#define GMAC_NSR_IDLE_Msk (_U_(0x1) << GMAC_NSR_IDLE_Pos) /**< (GMAC_NSR) PHY Management Logic Idle Mask */ +#define GMAC_NSR_IDLE(value) (GMAC_NSR_IDLE_Msk & ((value) << GMAC_NSR_IDLE_Pos)) +#define GMAC_NSR_RXLPIS_Pos _U_(7) /**< (GMAC_NSR) LPI Indication Position */ +#define GMAC_NSR_RXLPIS_Msk (_U_(0x1) << GMAC_NSR_RXLPIS_Pos) /**< (GMAC_NSR) LPI Indication Mask */ +#define GMAC_NSR_RXLPIS(value) (GMAC_NSR_RXLPIS_Msk & ((value) << GMAC_NSR_RXLPIS_Pos)) +#define GMAC_NSR_Msk _U_(0x00000086) /**< (GMAC_NSR) Register Mask */ + + +/* -------- GMAC_UR : (GMAC Offset: 0x0C) (R/W 32) User Register -------- */ +#define GMAC_UR_RMII_Pos _U_(0) /**< (GMAC_UR) Reduced MII Mode Position */ +#define GMAC_UR_RMII_Msk (_U_(0x1) << GMAC_UR_RMII_Pos) /**< (GMAC_UR) Reduced MII Mode Mask */ +#define GMAC_UR_RMII(value) (GMAC_UR_RMII_Msk & ((value) << GMAC_UR_RMII_Pos)) +#define GMAC_UR_Msk _U_(0x00000001) /**< (GMAC_UR) Register Mask */ + + +/* -------- GMAC_DCFGR : (GMAC Offset: 0x10) (R/W 32) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos _U_(0) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Position */ +#define GMAC_DCFGR_FBLDO_Msk (_U_(0x1F) << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: Mask */ +#define GMAC_DCFGR_FBLDO(value) (GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)) +#define GMAC_DCFGR_FBLDO_SINGLE_Val _U_(0x1) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4_Val _U_(0x4) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8_Val _U_(0x8) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16_Val _U_(0x10) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_FBLDO_SINGLE (GMAC_DCFGR_FBLDO_SINGLE_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR4 (GMAC_DCFGR_FBLDO_INCR4_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) Position */ +#define GMAC_DCFGR_FBLDO_INCR8 (GMAC_DCFGR_FBLDO_INCR8_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts Position */ +#define GMAC_DCFGR_FBLDO_INCR16 (GMAC_DCFGR_FBLDO_INCR16_Val << GMAC_DCFGR_FBLDO_Pos) /**< (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts Position */ +#define GMAC_DCFGR_ESMA_Pos _U_(6) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Position */ +#define GMAC_DCFGR_ESMA_Msk (_U_(0x1) << GMAC_DCFGR_ESMA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses Mask */ +#define GMAC_DCFGR_ESMA(value) (GMAC_DCFGR_ESMA_Msk & ((value) << GMAC_DCFGR_ESMA_Pos)) +#define GMAC_DCFGR_ESPA_Pos _U_(7) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Position */ +#define GMAC_DCFGR_ESPA_Msk (_U_(0x1) << GMAC_DCFGR_ESPA_Pos) /**< (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses Mask */ +#define GMAC_DCFGR_ESPA(value) (GMAC_DCFGR_ESPA_Msk & ((value) << GMAC_DCFGR_ESPA_Pos)) +#define GMAC_DCFGR_RXBMS_Pos _U_(8) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_RXBMS_Msk (_U_(0x3) << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_RXBMS(value) (GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)) +#define GMAC_DCFGR_RXBMS_EIGHTH_Val _U_(0x0) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER_Val _U_(0x1) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF_Val _U_(0x2) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL_Val _U_(0x3) /**< (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_EIGHTH (GMAC_DCFGR_RXBMS_EIGHTH_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/8 Kbyte Memory Size Position */ +#define GMAC_DCFGR_RXBMS_QUARTER (GMAC_DCFGR_RXBMS_QUARTER_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_HALF (GMAC_DCFGR_RXBMS_HALF_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4/2 Kbytes Memory Size Position */ +#define GMAC_DCFGR_RXBMS_FULL (GMAC_DCFGR_RXBMS_FULL_Val << GMAC_DCFGR_RXBMS_Pos) /**< (GMAC_DCFGR) 4 Kbytes Memory Size Position */ +#define GMAC_DCFGR_TXPBMS_Pos _U_(10) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Position */ +#define GMAC_DCFGR_TXPBMS_Msk (_U_(0x1) << GMAC_DCFGR_TXPBMS_Pos) /**< (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select Mask */ +#define GMAC_DCFGR_TXPBMS(value) (GMAC_DCFGR_TXPBMS_Msk & ((value) << GMAC_DCFGR_TXPBMS_Pos)) +#define GMAC_DCFGR_TXCOEN_Pos _U_(11) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Position */ +#define GMAC_DCFGR_TXCOEN_Msk (_U_(0x1) << GMAC_DCFGR_TXCOEN_Pos) /**< (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable Mask */ +#define GMAC_DCFGR_TXCOEN(value) (GMAC_DCFGR_TXCOEN_Msk & ((value) << GMAC_DCFGR_TXCOEN_Pos)) +#define GMAC_DCFGR_DRBS_Pos _U_(16) /**< (GMAC_DCFGR) DMA Receive Buffer Size Position */ +#define GMAC_DCFGR_DRBS_Msk (_U_(0xFF) << GMAC_DCFGR_DRBS_Pos) /**< (GMAC_DCFGR) DMA Receive Buffer Size Mask */ +#define GMAC_DCFGR_DRBS(value) (GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)) +#define GMAC_DCFGR_DDRP_Pos _U_(24) /**< (GMAC_DCFGR) DMA Discard Receive Packets Position */ +#define GMAC_DCFGR_DDRP_Msk (_U_(0x1) << GMAC_DCFGR_DDRP_Pos) /**< (GMAC_DCFGR) DMA Discard Receive Packets Mask */ +#define GMAC_DCFGR_DDRP(value) (GMAC_DCFGR_DDRP_Msk & ((value) << GMAC_DCFGR_DDRP_Pos)) +#define GMAC_DCFGR_Msk _U_(0x01FF0FDF) /**< (GMAC_DCFGR) Register Mask */ + + +/* -------- GMAC_TSR : (GMAC Offset: 0x14) (R/W 32) Transmit Status Register -------- */ +#define GMAC_TSR_UBR_Pos _U_(0) /**< (GMAC_TSR) Used Bit Read Position */ +#define GMAC_TSR_UBR_Msk (_U_(0x1) << GMAC_TSR_UBR_Pos) /**< (GMAC_TSR) Used Bit Read Mask */ +#define GMAC_TSR_UBR(value) (GMAC_TSR_UBR_Msk & ((value) << GMAC_TSR_UBR_Pos)) +#define GMAC_TSR_COL_Pos _U_(1) /**< (GMAC_TSR) Collision Occurred Position */ +#define GMAC_TSR_COL_Msk (_U_(0x1) << GMAC_TSR_COL_Pos) /**< (GMAC_TSR) Collision Occurred Mask */ +#define GMAC_TSR_COL(value) (GMAC_TSR_COL_Msk & ((value) << GMAC_TSR_COL_Pos)) +#define GMAC_TSR_RLE_Pos _U_(2) /**< (GMAC_TSR) Retry Limit Exceeded Position */ +#define GMAC_TSR_RLE_Msk (_U_(0x1) << GMAC_TSR_RLE_Pos) /**< (GMAC_TSR) Retry Limit Exceeded Mask */ +#define GMAC_TSR_RLE(value) (GMAC_TSR_RLE_Msk & ((value) << GMAC_TSR_RLE_Pos)) +#define GMAC_TSR_TXGO_Pos _U_(3) /**< (GMAC_TSR) Transmit Go Position */ +#define GMAC_TSR_TXGO_Msk (_U_(0x1) << GMAC_TSR_TXGO_Pos) /**< (GMAC_TSR) Transmit Go Mask */ +#define GMAC_TSR_TXGO(value) (GMAC_TSR_TXGO_Msk & ((value) << GMAC_TSR_TXGO_Pos)) +#define GMAC_TSR_TFC_Pos _U_(4) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_TSR_TFC_Msk (_U_(0x1) << GMAC_TSR_TFC_Pos) /**< (GMAC_TSR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_TSR_TFC(value) (GMAC_TSR_TFC_Msk & ((value) << GMAC_TSR_TFC_Pos)) +#define GMAC_TSR_TXCOMP_Pos _U_(5) /**< (GMAC_TSR) Transmit Complete Position */ +#define GMAC_TSR_TXCOMP_Msk (_U_(0x1) << GMAC_TSR_TXCOMP_Pos) /**< (GMAC_TSR) Transmit Complete Mask */ +#define GMAC_TSR_TXCOMP(value) (GMAC_TSR_TXCOMP_Msk & ((value) << GMAC_TSR_TXCOMP_Pos)) +#define GMAC_TSR_HRESP_Pos _U_(8) /**< (GMAC_TSR) HRESP Not OK Position */ +#define GMAC_TSR_HRESP_Msk (_U_(0x1) << GMAC_TSR_HRESP_Pos) /**< (GMAC_TSR) HRESP Not OK Mask */ +#define GMAC_TSR_HRESP(value) (GMAC_TSR_HRESP_Msk & ((value) << GMAC_TSR_HRESP_Pos)) +#define GMAC_TSR_Msk _U_(0x0000013F) /**< (GMAC_TSR) Register Mask */ + + +/* -------- GMAC_RBQB : (GMAC Offset: 0x18) (R/W 32) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos _U_(2) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_RBQB_ADDR_Pos) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQB_ADDR(value) (GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)) +#define GMAC_RBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQB) Register Mask */ + + +/* -------- GMAC_TBQB : (GMAC Offset: 0x1C) (R/W 32) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos _U_(2) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQB_ADDR_Msk (_U_(0x3FFFFFFF) << GMAC_TBQB_ADDR_Pos) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQB_ADDR(value) (GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)) +#define GMAC_TBQB_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQB) Register Mask */ + + +/* -------- GMAC_RSR : (GMAC Offset: 0x20) (R/W 32) Receive Status Register -------- */ +#define GMAC_RSR_BNA_Pos _U_(0) /**< (GMAC_RSR) Buffer Not Available Position */ +#define GMAC_RSR_BNA_Msk (_U_(0x1) << GMAC_RSR_BNA_Pos) /**< (GMAC_RSR) Buffer Not Available Mask */ +#define GMAC_RSR_BNA(value) (GMAC_RSR_BNA_Msk & ((value) << GMAC_RSR_BNA_Pos)) +#define GMAC_RSR_REC_Pos _U_(1) /**< (GMAC_RSR) Frame Received Position */ +#define GMAC_RSR_REC_Msk (_U_(0x1) << GMAC_RSR_REC_Pos) /**< (GMAC_RSR) Frame Received Mask */ +#define GMAC_RSR_REC(value) (GMAC_RSR_REC_Msk & ((value) << GMAC_RSR_REC_Pos)) +#define GMAC_RSR_RXOVR_Pos _U_(2) /**< (GMAC_RSR) Receive Overrun Position */ +#define GMAC_RSR_RXOVR_Msk (_U_(0x1) << GMAC_RSR_RXOVR_Pos) /**< (GMAC_RSR) Receive Overrun Mask */ +#define GMAC_RSR_RXOVR(value) (GMAC_RSR_RXOVR_Msk & ((value) << GMAC_RSR_RXOVR_Pos)) +#define GMAC_RSR_HNO_Pos _U_(3) /**< (GMAC_RSR) HRESP Not OK Position */ +#define GMAC_RSR_HNO_Msk (_U_(0x1) << GMAC_RSR_HNO_Pos) /**< (GMAC_RSR) HRESP Not OK Mask */ +#define GMAC_RSR_HNO(value) (GMAC_RSR_HNO_Msk & ((value) << GMAC_RSR_HNO_Pos)) +#define GMAC_RSR_Msk _U_(0x0000000F) /**< (GMAC_RSR) Register Mask */ + + +/* -------- GMAC_ISR : (GMAC Offset: 0x24) ( R/ 32) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS_Pos _U_(0) /**< (GMAC_ISR) Management Frame Sent Position */ +#define GMAC_ISR_MFS_Msk (_U_(0x1) << GMAC_ISR_MFS_Pos) /**< (GMAC_ISR) Management Frame Sent Mask */ +#define GMAC_ISR_MFS(value) (GMAC_ISR_MFS_Msk & ((value) << GMAC_ISR_MFS_Pos)) +#define GMAC_ISR_RCOMP_Pos _U_(1) /**< (GMAC_ISR) Receive Complete Position */ +#define GMAC_ISR_RCOMP_Msk (_U_(0x1) << GMAC_ISR_RCOMP_Pos) /**< (GMAC_ISR) Receive Complete Mask */ +#define GMAC_ISR_RCOMP(value) (GMAC_ISR_RCOMP_Msk & ((value) << GMAC_ISR_RCOMP_Pos)) +#define GMAC_ISR_RXUBR_Pos _U_(2) /**< (GMAC_ISR) RX Used Bit Read Position */ +#define GMAC_ISR_RXUBR_Msk (_U_(0x1) << GMAC_ISR_RXUBR_Pos) /**< (GMAC_ISR) RX Used Bit Read Mask */ +#define GMAC_ISR_RXUBR(value) (GMAC_ISR_RXUBR_Msk & ((value) << GMAC_ISR_RXUBR_Pos)) +#define GMAC_ISR_TXUBR_Pos _U_(3) /**< (GMAC_ISR) TX Used Bit Read Position */ +#define GMAC_ISR_TXUBR_Msk (_U_(0x1) << GMAC_ISR_TXUBR_Pos) /**< (GMAC_ISR) TX Used Bit Read Mask */ +#define GMAC_ISR_TXUBR(value) (GMAC_ISR_TXUBR_Msk & ((value) << GMAC_ISR_TXUBR_Pos)) +#define GMAC_ISR_TUR_Pos _U_(4) /**< (GMAC_ISR) Transmit Underrun Position */ +#define GMAC_ISR_TUR_Msk (_U_(0x1) << GMAC_ISR_TUR_Pos) /**< (GMAC_ISR) Transmit Underrun Mask */ +#define GMAC_ISR_TUR(value) (GMAC_ISR_TUR_Msk & ((value) << GMAC_ISR_TUR_Pos)) +#define GMAC_ISR_RLEX_Pos _U_(5) /**< (GMAC_ISR) Retry Limit Exceeded Position */ +#define GMAC_ISR_RLEX_Msk (_U_(0x1) << GMAC_ISR_RLEX_Pos) /**< (GMAC_ISR) Retry Limit Exceeded Mask */ +#define GMAC_ISR_RLEX(value) (GMAC_ISR_RLEX_Msk & ((value) << GMAC_ISR_RLEX_Pos)) +#define GMAC_ISR_TFC_Pos _U_(6) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISR_TFC_Msk (_U_(0x1) << GMAC_ISR_TFC_Pos) /**< (GMAC_ISR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISR_TFC(value) (GMAC_ISR_TFC_Msk & ((value) << GMAC_ISR_TFC_Pos)) +#define GMAC_ISR_TCOMP_Pos _U_(7) /**< (GMAC_ISR) Transmit Complete Position */ +#define GMAC_ISR_TCOMP_Msk (_U_(0x1) << GMAC_ISR_TCOMP_Pos) /**< (GMAC_ISR) Transmit Complete Mask */ +#define GMAC_ISR_TCOMP(value) (GMAC_ISR_TCOMP_Msk & ((value) << GMAC_ISR_TCOMP_Pos)) +#define GMAC_ISR_ROVR_Pos _U_(10) /**< (GMAC_ISR) Receive Overrun Position */ +#define GMAC_ISR_ROVR_Msk (_U_(0x1) << GMAC_ISR_ROVR_Pos) /**< (GMAC_ISR) Receive Overrun Mask */ +#define GMAC_ISR_ROVR(value) (GMAC_ISR_ROVR_Msk & ((value) << GMAC_ISR_ROVR_Pos)) +#define GMAC_ISR_HRESP_Pos _U_(11) /**< (GMAC_ISR) HRESP Not OK Position */ +#define GMAC_ISR_HRESP_Msk (_U_(0x1) << GMAC_ISR_HRESP_Pos) /**< (GMAC_ISR) HRESP Not OK Mask */ +#define GMAC_ISR_HRESP(value) (GMAC_ISR_HRESP_Msk & ((value) << GMAC_ISR_HRESP_Pos)) +#define GMAC_ISR_PFNZ_Pos _U_(12) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_ISR_PFNZ_Msk (_U_(0x1) << GMAC_ISR_PFNZ_Pos) /**< (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_ISR_PFNZ(value) (GMAC_ISR_PFNZ_Msk & ((value) << GMAC_ISR_PFNZ_Pos)) +#define GMAC_ISR_PTZ_Pos _U_(13) /**< (GMAC_ISR) Pause Time Zero Position */ +#define GMAC_ISR_PTZ_Msk (_U_(0x1) << GMAC_ISR_PTZ_Pos) /**< (GMAC_ISR) Pause Time Zero Mask */ +#define GMAC_ISR_PTZ(value) (GMAC_ISR_PTZ_Msk & ((value) << GMAC_ISR_PTZ_Pos)) +#define GMAC_ISR_PFTR_Pos _U_(14) /**< (GMAC_ISR) Pause Frame Transmitted Position */ +#define GMAC_ISR_PFTR_Msk (_U_(0x1) << GMAC_ISR_PFTR_Pos) /**< (GMAC_ISR) Pause Frame Transmitted Mask */ +#define GMAC_ISR_PFTR(value) (GMAC_ISR_PFTR_Msk & ((value) << GMAC_ISR_PFTR_Pos)) +#define GMAC_ISR_DRQFR_Pos _U_(18) /**< (GMAC_ISR) PTP Delay Request Frame Received Position */ +#define GMAC_ISR_DRQFR_Msk (_U_(0x1) << GMAC_ISR_DRQFR_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Received Mask */ +#define GMAC_ISR_DRQFR(value) (GMAC_ISR_DRQFR_Msk & ((value) << GMAC_ISR_DRQFR_Pos)) +#define GMAC_ISR_SFR_Pos _U_(19) /**< (GMAC_ISR) PTP Sync Frame Received Position */ +#define GMAC_ISR_SFR_Msk (_U_(0x1) << GMAC_ISR_SFR_Pos) /**< (GMAC_ISR) PTP Sync Frame Received Mask */ +#define GMAC_ISR_SFR(value) (GMAC_ISR_SFR_Msk & ((value) << GMAC_ISR_SFR_Pos)) +#define GMAC_ISR_DRQFT_Pos _U_(20) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_ISR_DRQFT_Msk (_U_(0x1) << GMAC_ISR_DRQFT_Pos) /**< (GMAC_ISR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_ISR_DRQFT(value) (GMAC_ISR_DRQFT_Msk & ((value) << GMAC_ISR_DRQFT_Pos)) +#define GMAC_ISR_SFT_Pos _U_(21) /**< (GMAC_ISR) PTP Sync Frame Transmitted Position */ +#define GMAC_ISR_SFT_Msk (_U_(0x1) << GMAC_ISR_SFT_Pos) /**< (GMAC_ISR) PTP Sync Frame Transmitted Mask */ +#define GMAC_ISR_SFT(value) (GMAC_ISR_SFT_Msk & ((value) << GMAC_ISR_SFT_Pos)) +#define GMAC_ISR_PDRQFR_Pos _U_(22) /**< (GMAC_ISR) PDelay Request Frame Received Position */ +#define GMAC_ISR_PDRQFR_Msk (_U_(0x1) << GMAC_ISR_PDRQFR_Pos) /**< (GMAC_ISR) PDelay Request Frame Received Mask */ +#define GMAC_ISR_PDRQFR(value) (GMAC_ISR_PDRQFR_Msk & ((value) << GMAC_ISR_PDRQFR_Pos)) +#define GMAC_ISR_PDRSFR_Pos _U_(23) /**< (GMAC_ISR) PDelay Response Frame Received Position */ +#define GMAC_ISR_PDRSFR_Msk (_U_(0x1) << GMAC_ISR_PDRSFR_Pos) /**< (GMAC_ISR) PDelay Response Frame Received Mask */ +#define GMAC_ISR_PDRSFR(value) (GMAC_ISR_PDRSFR_Msk & ((value) << GMAC_ISR_PDRSFR_Pos)) +#define GMAC_ISR_PDRQFT_Pos _U_(24) /**< (GMAC_ISR) PDelay Request Frame Transmitted Position */ +#define GMAC_ISR_PDRQFT_Msk (_U_(0x1) << GMAC_ISR_PDRQFT_Pos) /**< (GMAC_ISR) PDelay Request Frame Transmitted Mask */ +#define GMAC_ISR_PDRQFT(value) (GMAC_ISR_PDRQFT_Msk & ((value) << GMAC_ISR_PDRQFT_Pos)) +#define GMAC_ISR_PDRSFT_Pos _U_(25) /**< (GMAC_ISR) PDelay Response Frame Transmitted Position */ +#define GMAC_ISR_PDRSFT_Msk (_U_(0x1) << GMAC_ISR_PDRSFT_Pos) /**< (GMAC_ISR) PDelay Response Frame Transmitted Mask */ +#define GMAC_ISR_PDRSFT(value) (GMAC_ISR_PDRSFT_Msk & ((value) << GMAC_ISR_PDRSFT_Pos)) +#define GMAC_ISR_SRI_Pos _U_(26) /**< (GMAC_ISR) TSU Seconds Register Increment Position */ +#define GMAC_ISR_SRI_Msk (_U_(0x1) << GMAC_ISR_SRI_Pos) /**< (GMAC_ISR) TSU Seconds Register Increment Mask */ +#define GMAC_ISR_SRI(value) (GMAC_ISR_SRI_Msk & ((value) << GMAC_ISR_SRI_Pos)) +#define GMAC_ISR_RXLPISBC_Pos _U_(27) /**< (GMAC_ISR) Receive LPI indication Status Bit Change Position */ +#define GMAC_ISR_RXLPISBC_Msk (_U_(0x1) << GMAC_ISR_RXLPISBC_Pos) /**< (GMAC_ISR) Receive LPI indication Status Bit Change Mask */ +#define GMAC_ISR_RXLPISBC(value) (GMAC_ISR_RXLPISBC_Msk & ((value) << GMAC_ISR_RXLPISBC_Pos)) +#define GMAC_ISR_WOL_Pos _U_(28) /**< (GMAC_ISR) Wake On LAN Position */ +#define GMAC_ISR_WOL_Msk (_U_(0x1) << GMAC_ISR_WOL_Pos) /**< (GMAC_ISR) Wake On LAN Mask */ +#define GMAC_ISR_WOL(value) (GMAC_ISR_WOL_Msk & ((value) << GMAC_ISR_WOL_Pos)) +#define GMAC_ISR_TSUTIMCOMP_Pos _U_(29) /**< (GMAC_ISR) TSU Timer Comparison Position */ +#define GMAC_ISR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_ISR_TSUTIMCOMP_Pos) /**< (GMAC_ISR) TSU Timer Comparison Mask */ +#define GMAC_ISR_TSUTIMCOMP(value) (GMAC_ISR_TSUTIMCOMP_Msk & ((value) << GMAC_ISR_TSUTIMCOMP_Pos)) +#define GMAC_ISR_Msk _U_(0x3FFC7CFF) /**< (GMAC_ISR) Register Mask */ + + +/* -------- GMAC_IER : (GMAC Offset: 0x28) ( /W 32) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS_Pos _U_(0) /**< (GMAC_IER) Management Frame Sent Position */ +#define GMAC_IER_MFS_Msk (_U_(0x1) << GMAC_IER_MFS_Pos) /**< (GMAC_IER) Management Frame Sent Mask */ +#define GMAC_IER_MFS(value) (GMAC_IER_MFS_Msk & ((value) << GMAC_IER_MFS_Pos)) +#define GMAC_IER_RCOMP_Pos _U_(1) /**< (GMAC_IER) Receive Complete Position */ +#define GMAC_IER_RCOMP_Msk (_U_(0x1) << GMAC_IER_RCOMP_Pos) /**< (GMAC_IER) Receive Complete Mask */ +#define GMAC_IER_RCOMP(value) (GMAC_IER_RCOMP_Msk & ((value) << GMAC_IER_RCOMP_Pos)) +#define GMAC_IER_RXUBR_Pos _U_(2) /**< (GMAC_IER) RX Used Bit Read Position */ +#define GMAC_IER_RXUBR_Msk (_U_(0x1) << GMAC_IER_RXUBR_Pos) /**< (GMAC_IER) RX Used Bit Read Mask */ +#define GMAC_IER_RXUBR(value) (GMAC_IER_RXUBR_Msk & ((value) << GMAC_IER_RXUBR_Pos)) +#define GMAC_IER_TXUBR_Pos _U_(3) /**< (GMAC_IER) TX Used Bit Read Position */ +#define GMAC_IER_TXUBR_Msk (_U_(0x1) << GMAC_IER_TXUBR_Pos) /**< (GMAC_IER) TX Used Bit Read Mask */ +#define GMAC_IER_TXUBR(value) (GMAC_IER_TXUBR_Msk & ((value) << GMAC_IER_TXUBR_Pos)) +#define GMAC_IER_TUR_Pos _U_(4) /**< (GMAC_IER) Transmit Underrun Position */ +#define GMAC_IER_TUR_Msk (_U_(0x1) << GMAC_IER_TUR_Pos) /**< (GMAC_IER) Transmit Underrun Mask */ +#define GMAC_IER_TUR(value) (GMAC_IER_TUR_Msk & ((value) << GMAC_IER_TUR_Pos)) +#define GMAC_IER_RLEX_Pos _U_(5) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IER_RLEX_Msk (_U_(0x1) << GMAC_IER_RLEX_Pos) /**< (GMAC_IER) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IER_RLEX(value) (GMAC_IER_RLEX_Msk & ((value) << GMAC_IER_RLEX_Pos)) +#define GMAC_IER_TFC_Pos _U_(6) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IER_TFC_Msk (_U_(0x1) << GMAC_IER_TFC_Pos) /**< (GMAC_IER) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IER_TFC(value) (GMAC_IER_TFC_Msk & ((value) << GMAC_IER_TFC_Pos)) +#define GMAC_IER_TCOMP_Pos _U_(7) /**< (GMAC_IER) Transmit Complete Position */ +#define GMAC_IER_TCOMP_Msk (_U_(0x1) << GMAC_IER_TCOMP_Pos) /**< (GMAC_IER) Transmit Complete Mask */ +#define GMAC_IER_TCOMP(value) (GMAC_IER_TCOMP_Msk & ((value) << GMAC_IER_TCOMP_Pos)) +#define GMAC_IER_ROVR_Pos _U_(10) /**< (GMAC_IER) Receive Overrun Position */ +#define GMAC_IER_ROVR_Msk (_U_(0x1) << GMAC_IER_ROVR_Pos) /**< (GMAC_IER) Receive Overrun Mask */ +#define GMAC_IER_ROVR(value) (GMAC_IER_ROVR_Msk & ((value) << GMAC_IER_ROVR_Pos)) +#define GMAC_IER_HRESP_Pos _U_(11) /**< (GMAC_IER) HRESP Not OK Position */ +#define GMAC_IER_HRESP_Msk (_U_(0x1) << GMAC_IER_HRESP_Pos) /**< (GMAC_IER) HRESP Not OK Mask */ +#define GMAC_IER_HRESP(value) (GMAC_IER_HRESP_Msk & ((value) << GMAC_IER_HRESP_Pos)) +#define GMAC_IER_PFNZ_Pos _U_(12) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IER_PFNZ_Msk (_U_(0x1) << GMAC_IER_PFNZ_Pos) /**< (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IER_PFNZ(value) (GMAC_IER_PFNZ_Msk & ((value) << GMAC_IER_PFNZ_Pos)) +#define GMAC_IER_PTZ_Pos _U_(13) /**< (GMAC_IER) Pause Time Zero Position */ +#define GMAC_IER_PTZ_Msk (_U_(0x1) << GMAC_IER_PTZ_Pos) /**< (GMAC_IER) Pause Time Zero Mask */ +#define GMAC_IER_PTZ(value) (GMAC_IER_PTZ_Msk & ((value) << GMAC_IER_PTZ_Pos)) +#define GMAC_IER_PFTR_Pos _U_(14) /**< (GMAC_IER) Pause Frame Transmitted Position */ +#define GMAC_IER_PFTR_Msk (_U_(0x1) << GMAC_IER_PFTR_Pos) /**< (GMAC_IER) Pause Frame Transmitted Mask */ +#define GMAC_IER_PFTR(value) (GMAC_IER_PFTR_Msk & ((value) << GMAC_IER_PFTR_Pos)) +#define GMAC_IER_EXINT_Pos _U_(15) /**< (GMAC_IER) External Interrupt Position */ +#define GMAC_IER_EXINT_Msk (_U_(0x1) << GMAC_IER_EXINT_Pos) /**< (GMAC_IER) External Interrupt Mask */ +#define GMAC_IER_EXINT(value) (GMAC_IER_EXINT_Msk & ((value) << GMAC_IER_EXINT_Pos)) +#define GMAC_IER_DRQFR_Pos _U_(18) /**< (GMAC_IER) PTP Delay Request Frame Received Position */ +#define GMAC_IER_DRQFR_Msk (_U_(0x1) << GMAC_IER_DRQFR_Pos) /**< (GMAC_IER) PTP Delay Request Frame Received Mask */ +#define GMAC_IER_DRQFR(value) (GMAC_IER_DRQFR_Msk & ((value) << GMAC_IER_DRQFR_Pos)) +#define GMAC_IER_SFR_Pos _U_(19) /**< (GMAC_IER) PTP Sync Frame Received Position */ +#define GMAC_IER_SFR_Msk (_U_(0x1) << GMAC_IER_SFR_Pos) /**< (GMAC_IER) PTP Sync Frame Received Mask */ +#define GMAC_IER_SFR(value) (GMAC_IER_SFR_Msk & ((value) << GMAC_IER_SFR_Pos)) +#define GMAC_IER_DRQFT_Pos _U_(20) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IER_DRQFT_Msk (_U_(0x1) << GMAC_IER_DRQFT_Pos) /**< (GMAC_IER) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IER_DRQFT(value) (GMAC_IER_DRQFT_Msk & ((value) << GMAC_IER_DRQFT_Pos)) +#define GMAC_IER_SFT_Pos _U_(21) /**< (GMAC_IER) PTP Sync Frame Transmitted Position */ +#define GMAC_IER_SFT_Msk (_U_(0x1) << GMAC_IER_SFT_Pos) /**< (GMAC_IER) PTP Sync Frame Transmitted Mask */ +#define GMAC_IER_SFT(value) (GMAC_IER_SFT_Msk & ((value) << GMAC_IER_SFT_Pos)) +#define GMAC_IER_PDRQFR_Pos _U_(22) /**< (GMAC_IER) PDelay Request Frame Received Position */ +#define GMAC_IER_PDRQFR_Msk (_U_(0x1) << GMAC_IER_PDRQFR_Pos) /**< (GMAC_IER) PDelay Request Frame Received Mask */ +#define GMAC_IER_PDRQFR(value) (GMAC_IER_PDRQFR_Msk & ((value) << GMAC_IER_PDRQFR_Pos)) +#define GMAC_IER_PDRSFR_Pos _U_(23) /**< (GMAC_IER) PDelay Response Frame Received Position */ +#define GMAC_IER_PDRSFR_Msk (_U_(0x1) << GMAC_IER_PDRSFR_Pos) /**< (GMAC_IER) PDelay Response Frame Received Mask */ +#define GMAC_IER_PDRSFR(value) (GMAC_IER_PDRSFR_Msk & ((value) << GMAC_IER_PDRSFR_Pos)) +#define GMAC_IER_PDRQFT_Pos _U_(24) /**< (GMAC_IER) PDelay Request Frame Transmitted Position */ +#define GMAC_IER_PDRQFT_Msk (_U_(0x1) << GMAC_IER_PDRQFT_Pos) /**< (GMAC_IER) PDelay Request Frame Transmitted Mask */ +#define GMAC_IER_PDRQFT(value) (GMAC_IER_PDRQFT_Msk & ((value) << GMAC_IER_PDRQFT_Pos)) +#define GMAC_IER_PDRSFT_Pos _U_(25) /**< (GMAC_IER) PDelay Response Frame Transmitted Position */ +#define GMAC_IER_PDRSFT_Msk (_U_(0x1) << GMAC_IER_PDRSFT_Pos) /**< (GMAC_IER) PDelay Response Frame Transmitted Mask */ +#define GMAC_IER_PDRSFT(value) (GMAC_IER_PDRSFT_Msk & ((value) << GMAC_IER_PDRSFT_Pos)) +#define GMAC_IER_SRI_Pos _U_(26) /**< (GMAC_IER) TSU Seconds Register Increment Position */ +#define GMAC_IER_SRI_Msk (_U_(0x1) << GMAC_IER_SRI_Pos) /**< (GMAC_IER) TSU Seconds Register Increment Mask */ +#define GMAC_IER_SRI(value) (GMAC_IER_SRI_Msk & ((value) << GMAC_IER_SRI_Pos)) +#define GMAC_IER_RXLPISBC_Pos _U_(27) /**< (GMAC_IER) Enable RX LPI Indication Position */ +#define GMAC_IER_RXLPISBC_Msk (_U_(0x1) << GMAC_IER_RXLPISBC_Pos) /**< (GMAC_IER) Enable RX LPI Indication Mask */ +#define GMAC_IER_RXLPISBC(value) (GMAC_IER_RXLPISBC_Msk & ((value) << GMAC_IER_RXLPISBC_Pos)) +#define GMAC_IER_WOL_Pos _U_(28) /**< (GMAC_IER) Wake On LAN Position */ +#define GMAC_IER_WOL_Msk (_U_(0x1) << GMAC_IER_WOL_Pos) /**< (GMAC_IER) Wake On LAN Mask */ +#define GMAC_IER_WOL(value) (GMAC_IER_WOL_Msk & ((value) << GMAC_IER_WOL_Pos)) +#define GMAC_IER_TSUTIMCOMP_Pos _U_(29) /**< (GMAC_IER) TSU Timer Comparison Position */ +#define GMAC_IER_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IER_TSUTIMCOMP_Pos) /**< (GMAC_IER) TSU Timer Comparison Mask */ +#define GMAC_IER_TSUTIMCOMP(value) (GMAC_IER_TSUTIMCOMP_Msk & ((value) << GMAC_IER_TSUTIMCOMP_Pos)) +#define GMAC_IER_Msk _U_(0x3FFCFCFF) /**< (GMAC_IER) Register Mask */ + + +/* -------- GMAC_IDR : (GMAC Offset: 0x2C) ( /W 32) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS_Pos _U_(0) /**< (GMAC_IDR) Management Frame Sent Position */ +#define GMAC_IDR_MFS_Msk (_U_(0x1) << GMAC_IDR_MFS_Pos) /**< (GMAC_IDR) Management Frame Sent Mask */ +#define GMAC_IDR_MFS(value) (GMAC_IDR_MFS_Msk & ((value) << GMAC_IDR_MFS_Pos)) +#define GMAC_IDR_RCOMP_Pos _U_(1) /**< (GMAC_IDR) Receive Complete Position */ +#define GMAC_IDR_RCOMP_Msk (_U_(0x1) << GMAC_IDR_RCOMP_Pos) /**< (GMAC_IDR) Receive Complete Mask */ +#define GMAC_IDR_RCOMP(value) (GMAC_IDR_RCOMP_Msk & ((value) << GMAC_IDR_RCOMP_Pos)) +#define GMAC_IDR_RXUBR_Pos _U_(2) /**< (GMAC_IDR) RX Used Bit Read Position */ +#define GMAC_IDR_RXUBR_Msk (_U_(0x1) << GMAC_IDR_RXUBR_Pos) /**< (GMAC_IDR) RX Used Bit Read Mask */ +#define GMAC_IDR_RXUBR(value) (GMAC_IDR_RXUBR_Msk & ((value) << GMAC_IDR_RXUBR_Pos)) +#define GMAC_IDR_TXUBR_Pos _U_(3) /**< (GMAC_IDR) TX Used Bit Read Position */ +#define GMAC_IDR_TXUBR_Msk (_U_(0x1) << GMAC_IDR_TXUBR_Pos) /**< (GMAC_IDR) TX Used Bit Read Mask */ +#define GMAC_IDR_TXUBR(value) (GMAC_IDR_TXUBR_Msk & ((value) << GMAC_IDR_TXUBR_Pos)) +#define GMAC_IDR_TUR_Pos _U_(4) /**< (GMAC_IDR) Transmit Underrun Position */ +#define GMAC_IDR_TUR_Msk (_U_(0x1) << GMAC_IDR_TUR_Pos) /**< (GMAC_IDR) Transmit Underrun Mask */ +#define GMAC_IDR_TUR(value) (GMAC_IDR_TUR_Msk & ((value) << GMAC_IDR_TUR_Pos)) +#define GMAC_IDR_RLEX_Pos _U_(5) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDR_RLEX_Msk (_U_(0x1) << GMAC_IDR_RLEX_Pos) /**< (GMAC_IDR) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDR_RLEX(value) (GMAC_IDR_RLEX_Msk & ((value) << GMAC_IDR_RLEX_Pos)) +#define GMAC_IDR_TFC_Pos _U_(6) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDR_TFC_Msk (_U_(0x1) << GMAC_IDR_TFC_Pos) /**< (GMAC_IDR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDR_TFC(value) (GMAC_IDR_TFC_Msk & ((value) << GMAC_IDR_TFC_Pos)) +#define GMAC_IDR_TCOMP_Pos _U_(7) /**< (GMAC_IDR) Transmit Complete Position */ +#define GMAC_IDR_TCOMP_Msk (_U_(0x1) << GMAC_IDR_TCOMP_Pos) /**< (GMAC_IDR) Transmit Complete Mask */ +#define GMAC_IDR_TCOMP(value) (GMAC_IDR_TCOMP_Msk & ((value) << GMAC_IDR_TCOMP_Pos)) +#define GMAC_IDR_ROVR_Pos _U_(10) /**< (GMAC_IDR) Receive Overrun Position */ +#define GMAC_IDR_ROVR_Msk (_U_(0x1) << GMAC_IDR_ROVR_Pos) /**< (GMAC_IDR) Receive Overrun Mask */ +#define GMAC_IDR_ROVR(value) (GMAC_IDR_ROVR_Msk & ((value) << GMAC_IDR_ROVR_Pos)) +#define GMAC_IDR_HRESP_Pos _U_(11) /**< (GMAC_IDR) HRESP Not OK Position */ +#define GMAC_IDR_HRESP_Msk (_U_(0x1) << GMAC_IDR_HRESP_Pos) /**< (GMAC_IDR) HRESP Not OK Mask */ +#define GMAC_IDR_HRESP(value) (GMAC_IDR_HRESP_Msk & ((value) << GMAC_IDR_HRESP_Pos)) +#define GMAC_IDR_PFNZ_Pos _U_(12) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IDR_PFNZ_Msk (_U_(0x1) << GMAC_IDR_PFNZ_Pos) /**< (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IDR_PFNZ(value) (GMAC_IDR_PFNZ_Msk & ((value) << GMAC_IDR_PFNZ_Pos)) +#define GMAC_IDR_PTZ_Pos _U_(13) /**< (GMAC_IDR) Pause Time Zero Position */ +#define GMAC_IDR_PTZ_Msk (_U_(0x1) << GMAC_IDR_PTZ_Pos) /**< (GMAC_IDR) Pause Time Zero Mask */ +#define GMAC_IDR_PTZ(value) (GMAC_IDR_PTZ_Msk & ((value) << GMAC_IDR_PTZ_Pos)) +#define GMAC_IDR_PFTR_Pos _U_(14) /**< (GMAC_IDR) Pause Frame Transmitted Position */ +#define GMAC_IDR_PFTR_Msk (_U_(0x1) << GMAC_IDR_PFTR_Pos) /**< (GMAC_IDR) Pause Frame Transmitted Mask */ +#define GMAC_IDR_PFTR(value) (GMAC_IDR_PFTR_Msk & ((value) << GMAC_IDR_PFTR_Pos)) +#define GMAC_IDR_EXINT_Pos _U_(15) /**< (GMAC_IDR) External Interrupt Position */ +#define GMAC_IDR_EXINT_Msk (_U_(0x1) << GMAC_IDR_EXINT_Pos) /**< (GMAC_IDR) External Interrupt Mask */ +#define GMAC_IDR_EXINT(value) (GMAC_IDR_EXINT_Msk & ((value) << GMAC_IDR_EXINT_Pos)) +#define GMAC_IDR_DRQFR_Pos _U_(18) /**< (GMAC_IDR) PTP Delay Request Frame Received Position */ +#define GMAC_IDR_DRQFR_Msk (_U_(0x1) << GMAC_IDR_DRQFR_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Received Mask */ +#define GMAC_IDR_DRQFR(value) (GMAC_IDR_DRQFR_Msk & ((value) << GMAC_IDR_DRQFR_Pos)) +#define GMAC_IDR_SFR_Pos _U_(19) /**< (GMAC_IDR) PTP Sync Frame Received Position */ +#define GMAC_IDR_SFR_Msk (_U_(0x1) << GMAC_IDR_SFR_Pos) /**< (GMAC_IDR) PTP Sync Frame Received Mask */ +#define GMAC_IDR_SFR(value) (GMAC_IDR_SFR_Msk & ((value) << GMAC_IDR_SFR_Pos)) +#define GMAC_IDR_DRQFT_Pos _U_(20) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IDR_DRQFT_Msk (_U_(0x1) << GMAC_IDR_DRQFT_Pos) /**< (GMAC_IDR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IDR_DRQFT(value) (GMAC_IDR_DRQFT_Msk & ((value) << GMAC_IDR_DRQFT_Pos)) +#define GMAC_IDR_SFT_Pos _U_(21) /**< (GMAC_IDR) PTP Sync Frame Transmitted Position */ +#define GMAC_IDR_SFT_Msk (_U_(0x1) << GMAC_IDR_SFT_Pos) /**< (GMAC_IDR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IDR_SFT(value) (GMAC_IDR_SFT_Msk & ((value) << GMAC_IDR_SFT_Pos)) +#define GMAC_IDR_PDRQFR_Pos _U_(22) /**< (GMAC_IDR) PDelay Request Frame Received Position */ +#define GMAC_IDR_PDRQFR_Msk (_U_(0x1) << GMAC_IDR_PDRQFR_Pos) /**< (GMAC_IDR) PDelay Request Frame Received Mask */ +#define GMAC_IDR_PDRQFR(value) (GMAC_IDR_PDRQFR_Msk & ((value) << GMAC_IDR_PDRQFR_Pos)) +#define GMAC_IDR_PDRSFR_Pos _U_(23) /**< (GMAC_IDR) PDelay Response Frame Received Position */ +#define GMAC_IDR_PDRSFR_Msk (_U_(0x1) << GMAC_IDR_PDRSFR_Pos) /**< (GMAC_IDR) PDelay Response Frame Received Mask */ +#define GMAC_IDR_PDRSFR(value) (GMAC_IDR_PDRSFR_Msk & ((value) << GMAC_IDR_PDRSFR_Pos)) +#define GMAC_IDR_PDRQFT_Pos _U_(24) /**< (GMAC_IDR) PDelay Request Frame Transmitted Position */ +#define GMAC_IDR_PDRQFT_Msk (_U_(0x1) << GMAC_IDR_PDRQFT_Pos) /**< (GMAC_IDR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IDR_PDRQFT(value) (GMAC_IDR_PDRQFT_Msk & ((value) << GMAC_IDR_PDRQFT_Pos)) +#define GMAC_IDR_PDRSFT_Pos _U_(25) /**< (GMAC_IDR) PDelay Response Frame Transmitted Position */ +#define GMAC_IDR_PDRSFT_Msk (_U_(0x1) << GMAC_IDR_PDRSFT_Pos) /**< (GMAC_IDR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IDR_PDRSFT(value) (GMAC_IDR_PDRSFT_Msk & ((value) << GMAC_IDR_PDRSFT_Pos)) +#define GMAC_IDR_SRI_Pos _U_(26) /**< (GMAC_IDR) TSU Seconds Register Increment Position */ +#define GMAC_IDR_SRI_Msk (_U_(0x1) << GMAC_IDR_SRI_Pos) /**< (GMAC_IDR) TSU Seconds Register Increment Mask */ +#define GMAC_IDR_SRI(value) (GMAC_IDR_SRI_Msk & ((value) << GMAC_IDR_SRI_Pos)) +#define GMAC_IDR_RXLPISBC_Pos _U_(27) /**< (GMAC_IDR) Enable RX LPI Indication Position */ +#define GMAC_IDR_RXLPISBC_Msk (_U_(0x1) << GMAC_IDR_RXLPISBC_Pos) /**< (GMAC_IDR) Enable RX LPI Indication Mask */ +#define GMAC_IDR_RXLPISBC(value) (GMAC_IDR_RXLPISBC_Msk & ((value) << GMAC_IDR_RXLPISBC_Pos)) +#define GMAC_IDR_WOL_Pos _U_(28) /**< (GMAC_IDR) Wake On LAN Position */ +#define GMAC_IDR_WOL_Msk (_U_(0x1) << GMAC_IDR_WOL_Pos) /**< (GMAC_IDR) Wake On LAN Mask */ +#define GMAC_IDR_WOL(value) (GMAC_IDR_WOL_Msk & ((value) << GMAC_IDR_WOL_Pos)) +#define GMAC_IDR_TSUTIMCOMP_Pos _U_(29) /**< (GMAC_IDR) TSU Timer Comparison Position */ +#define GMAC_IDR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IDR_TSUTIMCOMP_Pos) /**< (GMAC_IDR) TSU Timer Comparison Mask */ +#define GMAC_IDR_TSUTIMCOMP(value) (GMAC_IDR_TSUTIMCOMP_Msk & ((value) << GMAC_IDR_TSUTIMCOMP_Pos)) +#define GMAC_IDR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IDR) Register Mask */ + + +/* -------- GMAC_IMR : (GMAC Offset: 0x30) (R/W 32) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS_Pos _U_(0) /**< (GMAC_IMR) Management Frame Sent Position */ +#define GMAC_IMR_MFS_Msk (_U_(0x1) << GMAC_IMR_MFS_Pos) /**< (GMAC_IMR) Management Frame Sent Mask */ +#define GMAC_IMR_MFS(value) (GMAC_IMR_MFS_Msk & ((value) << GMAC_IMR_MFS_Pos)) +#define GMAC_IMR_RCOMP_Pos _U_(1) /**< (GMAC_IMR) Receive Complete Position */ +#define GMAC_IMR_RCOMP_Msk (_U_(0x1) << GMAC_IMR_RCOMP_Pos) /**< (GMAC_IMR) Receive Complete Mask */ +#define GMAC_IMR_RCOMP(value) (GMAC_IMR_RCOMP_Msk & ((value) << GMAC_IMR_RCOMP_Pos)) +#define GMAC_IMR_RXUBR_Pos _U_(2) /**< (GMAC_IMR) RX Used Bit Read Position */ +#define GMAC_IMR_RXUBR_Msk (_U_(0x1) << GMAC_IMR_RXUBR_Pos) /**< (GMAC_IMR) RX Used Bit Read Mask */ +#define GMAC_IMR_RXUBR(value) (GMAC_IMR_RXUBR_Msk & ((value) << GMAC_IMR_RXUBR_Pos)) +#define GMAC_IMR_TXUBR_Pos _U_(3) /**< (GMAC_IMR) TX Used Bit Read Position */ +#define GMAC_IMR_TXUBR_Msk (_U_(0x1) << GMAC_IMR_TXUBR_Pos) /**< (GMAC_IMR) TX Used Bit Read Mask */ +#define GMAC_IMR_TXUBR(value) (GMAC_IMR_TXUBR_Msk & ((value) << GMAC_IMR_TXUBR_Pos)) +#define GMAC_IMR_TUR_Pos _U_(4) /**< (GMAC_IMR) Transmit Underrun Position */ +#define GMAC_IMR_TUR_Msk (_U_(0x1) << GMAC_IMR_TUR_Pos) /**< (GMAC_IMR) Transmit Underrun Mask */ +#define GMAC_IMR_TUR(value) (GMAC_IMR_TUR_Msk & ((value) << GMAC_IMR_TUR_Pos)) +#define GMAC_IMR_RLEX_Pos _U_(5) /**< (GMAC_IMR) Retry Limit Exceeded Position */ +#define GMAC_IMR_RLEX_Msk (_U_(0x1) << GMAC_IMR_RLEX_Pos) /**< (GMAC_IMR) Retry Limit Exceeded Mask */ +#define GMAC_IMR_RLEX(value) (GMAC_IMR_RLEX_Msk & ((value) << GMAC_IMR_RLEX_Pos)) +#define GMAC_IMR_TFC_Pos _U_(6) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IMR_TFC_Msk (_U_(0x1) << GMAC_IMR_TFC_Pos) /**< (GMAC_IMR) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IMR_TFC(value) (GMAC_IMR_TFC_Msk & ((value) << GMAC_IMR_TFC_Pos)) +#define GMAC_IMR_TCOMP_Pos _U_(7) /**< (GMAC_IMR) Transmit Complete Position */ +#define GMAC_IMR_TCOMP_Msk (_U_(0x1) << GMAC_IMR_TCOMP_Pos) /**< (GMAC_IMR) Transmit Complete Mask */ +#define GMAC_IMR_TCOMP(value) (GMAC_IMR_TCOMP_Msk & ((value) << GMAC_IMR_TCOMP_Pos)) +#define GMAC_IMR_ROVR_Pos _U_(10) /**< (GMAC_IMR) Receive Overrun Position */ +#define GMAC_IMR_ROVR_Msk (_U_(0x1) << GMAC_IMR_ROVR_Pos) /**< (GMAC_IMR) Receive Overrun Mask */ +#define GMAC_IMR_ROVR(value) (GMAC_IMR_ROVR_Msk & ((value) << GMAC_IMR_ROVR_Pos)) +#define GMAC_IMR_HRESP_Pos _U_(11) /**< (GMAC_IMR) HRESP Not OK Position */ +#define GMAC_IMR_HRESP_Msk (_U_(0x1) << GMAC_IMR_HRESP_Pos) /**< (GMAC_IMR) HRESP Not OK Mask */ +#define GMAC_IMR_HRESP(value) (GMAC_IMR_HRESP_Msk & ((value) << GMAC_IMR_HRESP_Pos)) +#define GMAC_IMR_PFNZ_Pos _U_(12) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Position */ +#define GMAC_IMR_PFNZ_Msk (_U_(0x1) << GMAC_IMR_PFNZ_Pos) /**< (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received Mask */ +#define GMAC_IMR_PFNZ(value) (GMAC_IMR_PFNZ_Msk & ((value) << GMAC_IMR_PFNZ_Pos)) +#define GMAC_IMR_PTZ_Pos _U_(13) /**< (GMAC_IMR) Pause Time Zero Position */ +#define GMAC_IMR_PTZ_Msk (_U_(0x1) << GMAC_IMR_PTZ_Pos) /**< (GMAC_IMR) Pause Time Zero Mask */ +#define GMAC_IMR_PTZ(value) (GMAC_IMR_PTZ_Msk & ((value) << GMAC_IMR_PTZ_Pos)) +#define GMAC_IMR_PFTR_Pos _U_(14) /**< (GMAC_IMR) Pause Frame Transmitted Position */ +#define GMAC_IMR_PFTR_Msk (_U_(0x1) << GMAC_IMR_PFTR_Pos) /**< (GMAC_IMR) Pause Frame Transmitted Mask */ +#define GMAC_IMR_PFTR(value) (GMAC_IMR_PFTR_Msk & ((value) << GMAC_IMR_PFTR_Pos)) +#define GMAC_IMR_EXINT_Pos _U_(15) /**< (GMAC_IMR) External Interrupt Position */ +#define GMAC_IMR_EXINT_Msk (_U_(0x1) << GMAC_IMR_EXINT_Pos) /**< (GMAC_IMR) External Interrupt Mask */ +#define GMAC_IMR_EXINT(value) (GMAC_IMR_EXINT_Msk & ((value) << GMAC_IMR_EXINT_Pos)) +#define GMAC_IMR_DRQFR_Pos _U_(18) /**< (GMAC_IMR) PTP Delay Request Frame Received Position */ +#define GMAC_IMR_DRQFR_Msk (_U_(0x1) << GMAC_IMR_DRQFR_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Received Mask */ +#define GMAC_IMR_DRQFR(value) (GMAC_IMR_DRQFR_Msk & ((value) << GMAC_IMR_DRQFR_Pos)) +#define GMAC_IMR_SFR_Pos _U_(19) /**< (GMAC_IMR) PTP Sync Frame Received Position */ +#define GMAC_IMR_SFR_Msk (_U_(0x1) << GMAC_IMR_SFR_Pos) /**< (GMAC_IMR) PTP Sync Frame Received Mask */ +#define GMAC_IMR_SFR(value) (GMAC_IMR_SFR_Msk & ((value) << GMAC_IMR_SFR_Pos)) +#define GMAC_IMR_DRQFT_Pos _U_(20) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Position */ +#define GMAC_IMR_DRQFT_Msk (_U_(0x1) << GMAC_IMR_DRQFT_Pos) /**< (GMAC_IMR) PTP Delay Request Frame Transmitted Mask */ +#define GMAC_IMR_DRQFT(value) (GMAC_IMR_DRQFT_Msk & ((value) << GMAC_IMR_DRQFT_Pos)) +#define GMAC_IMR_SFT_Pos _U_(21) /**< (GMAC_IMR) PTP Sync Frame Transmitted Position */ +#define GMAC_IMR_SFT_Msk (_U_(0x1) << GMAC_IMR_SFT_Pos) /**< (GMAC_IMR) PTP Sync Frame Transmitted Mask */ +#define GMAC_IMR_SFT(value) (GMAC_IMR_SFT_Msk & ((value) << GMAC_IMR_SFT_Pos)) +#define GMAC_IMR_PDRQFR_Pos _U_(22) /**< (GMAC_IMR) PDelay Request Frame Received Position */ +#define GMAC_IMR_PDRQFR_Msk (_U_(0x1) << GMAC_IMR_PDRQFR_Pos) /**< (GMAC_IMR) PDelay Request Frame Received Mask */ +#define GMAC_IMR_PDRQFR(value) (GMAC_IMR_PDRQFR_Msk & ((value) << GMAC_IMR_PDRQFR_Pos)) +#define GMAC_IMR_PDRSFR_Pos _U_(23) /**< (GMAC_IMR) PDelay Response Frame Received Position */ +#define GMAC_IMR_PDRSFR_Msk (_U_(0x1) << GMAC_IMR_PDRSFR_Pos) /**< (GMAC_IMR) PDelay Response Frame Received Mask */ +#define GMAC_IMR_PDRSFR(value) (GMAC_IMR_PDRSFR_Msk & ((value) << GMAC_IMR_PDRSFR_Pos)) +#define GMAC_IMR_PDRQFT_Pos _U_(24) /**< (GMAC_IMR) PDelay Request Frame Transmitted Position */ +#define GMAC_IMR_PDRQFT_Msk (_U_(0x1) << GMAC_IMR_PDRQFT_Pos) /**< (GMAC_IMR) PDelay Request Frame Transmitted Mask */ +#define GMAC_IMR_PDRQFT(value) (GMAC_IMR_PDRQFT_Msk & ((value) << GMAC_IMR_PDRQFT_Pos)) +#define GMAC_IMR_PDRSFT_Pos _U_(25) /**< (GMAC_IMR) PDelay Response Frame Transmitted Position */ +#define GMAC_IMR_PDRSFT_Msk (_U_(0x1) << GMAC_IMR_PDRSFT_Pos) /**< (GMAC_IMR) PDelay Response Frame Transmitted Mask */ +#define GMAC_IMR_PDRSFT(value) (GMAC_IMR_PDRSFT_Msk & ((value) << GMAC_IMR_PDRSFT_Pos)) +#define GMAC_IMR_SRI_Pos _U_(26) /**< (GMAC_IMR) TSU Seconds Register Increment Position */ +#define GMAC_IMR_SRI_Msk (_U_(0x1) << GMAC_IMR_SRI_Pos) /**< (GMAC_IMR) TSU Seconds Register Increment Mask */ +#define GMAC_IMR_SRI(value) (GMAC_IMR_SRI_Msk & ((value) << GMAC_IMR_SRI_Pos)) +#define GMAC_IMR_RXLPISBC_Pos _U_(27) /**< (GMAC_IMR) Enable RX LPI Indication Position */ +#define GMAC_IMR_RXLPISBC_Msk (_U_(0x1) << GMAC_IMR_RXLPISBC_Pos) /**< (GMAC_IMR) Enable RX LPI Indication Mask */ +#define GMAC_IMR_RXLPISBC(value) (GMAC_IMR_RXLPISBC_Msk & ((value) << GMAC_IMR_RXLPISBC_Pos)) +#define GMAC_IMR_WOL_Pos _U_(28) /**< (GMAC_IMR) Wake On LAN Position */ +#define GMAC_IMR_WOL_Msk (_U_(0x1) << GMAC_IMR_WOL_Pos) /**< (GMAC_IMR) Wake On LAN Mask */ +#define GMAC_IMR_WOL(value) (GMAC_IMR_WOL_Msk & ((value) << GMAC_IMR_WOL_Pos)) +#define GMAC_IMR_TSUTIMCOMP_Pos _U_(29) /**< (GMAC_IMR) TSU Timer Comparison Position */ +#define GMAC_IMR_TSUTIMCOMP_Msk (_U_(0x1) << GMAC_IMR_TSUTIMCOMP_Pos) /**< (GMAC_IMR) TSU Timer Comparison Mask */ +#define GMAC_IMR_TSUTIMCOMP(value) (GMAC_IMR_TSUTIMCOMP_Msk & ((value) << GMAC_IMR_TSUTIMCOMP_Pos)) +#define GMAC_IMR_Msk _U_(0x3FFCFCFF) /**< (GMAC_IMR) Register Mask */ + + +/* -------- GMAC_MAN : (GMAC Offset: 0x34) (R/W 32) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos _U_(0) /**< (GMAC_MAN) PHY Data Position */ +#define GMAC_MAN_DATA_Msk (_U_(0xFFFF) << GMAC_MAN_DATA_Pos) /**< (GMAC_MAN) PHY Data Mask */ +#define GMAC_MAN_DATA(value) (GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)) +#define GMAC_MAN_WTN_Pos _U_(16) /**< (GMAC_MAN) Write Ten Position */ +#define GMAC_MAN_WTN_Msk (_U_(0x3) << GMAC_MAN_WTN_Pos) /**< (GMAC_MAN) Write Ten Mask */ +#define GMAC_MAN_WTN(value) (GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)) +#define GMAC_MAN_REGA_Pos _U_(18) /**< (GMAC_MAN) Register Address Position */ +#define GMAC_MAN_REGA_Msk (_U_(0x1F) << GMAC_MAN_REGA_Pos) /**< (GMAC_MAN) Register Address Mask */ +#define GMAC_MAN_REGA(value) (GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)) +#define GMAC_MAN_PHYA_Pos _U_(23) /**< (GMAC_MAN) PHY Address Position */ +#define GMAC_MAN_PHYA_Msk (_U_(0x1F) << GMAC_MAN_PHYA_Pos) /**< (GMAC_MAN) PHY Address Mask */ +#define GMAC_MAN_PHYA(value) (GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)) +#define GMAC_MAN_OP_Pos _U_(28) /**< (GMAC_MAN) Operation Position */ +#define GMAC_MAN_OP_Msk (_U_(0x3) << GMAC_MAN_OP_Pos) /**< (GMAC_MAN) Operation Mask */ +#define GMAC_MAN_OP(value) (GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)) +#define GMAC_MAN_CLTTO_Pos _U_(30) /**< (GMAC_MAN) Clause 22 Operation Position */ +#define GMAC_MAN_CLTTO_Msk (_U_(0x1) << GMAC_MAN_CLTTO_Pos) /**< (GMAC_MAN) Clause 22 Operation Mask */ +#define GMAC_MAN_CLTTO(value) (GMAC_MAN_CLTTO_Msk & ((value) << GMAC_MAN_CLTTO_Pos)) +#define GMAC_MAN_WZO_Pos _U_(31) /**< (GMAC_MAN) Write ZERO Position */ +#define GMAC_MAN_WZO_Msk (_U_(0x1) << GMAC_MAN_WZO_Pos) /**< (GMAC_MAN) Write ZERO Mask */ +#define GMAC_MAN_WZO(value) (GMAC_MAN_WZO_Msk & ((value) << GMAC_MAN_WZO_Pos)) +#define GMAC_MAN_Msk _U_(0xFFFFFFFF) /**< (GMAC_MAN) Register Mask */ + + +/* -------- GMAC_RPQ : (GMAC Offset: 0x38) ( R/ 32) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos _U_(0) /**< (GMAC_RPQ) Received Pause Quantum Position */ +#define GMAC_RPQ_RPQ_Msk (_U_(0xFFFF) << GMAC_RPQ_RPQ_Pos) /**< (GMAC_RPQ) Received Pause Quantum Mask */ +#define GMAC_RPQ_RPQ(value) (GMAC_RPQ_RPQ_Msk & ((value) << GMAC_RPQ_RPQ_Pos)) +#define GMAC_RPQ_Msk _U_(0x0000FFFF) /**< (GMAC_RPQ) Register Mask */ + + +/* -------- GMAC_TPQ : (GMAC Offset: 0x3C) (R/W 32) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos _U_(0) /**< (GMAC_TPQ) Transmit Pause Quantum Position */ +#define GMAC_TPQ_TPQ_Msk (_U_(0xFFFF) << GMAC_TPQ_TPQ_Pos) /**< (GMAC_TPQ) Transmit Pause Quantum Mask */ +#define GMAC_TPQ_TPQ(value) (GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)) +#define GMAC_TPQ_Msk _U_(0x0000FFFF) /**< (GMAC_TPQ) Register Mask */ + + +/* -------- GMAC_TPSF : (GMAC Offset: 0x40) (R/W 32) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos _U_(0) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Position */ +#define GMAC_TPSF_TPB1ADR_Msk (_U_(0xFFF) << GMAC_TPSF_TPB1ADR_Pos) /**< (GMAC_TPSF) Transmit Partial Store and Forward Address Mask */ +#define GMAC_TPSF_TPB1ADR(value) (GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)) +#define GMAC_TPSF_ENTXP_Pos _U_(31) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Position */ +#define GMAC_TPSF_ENTXP_Msk (_U_(0x1) << GMAC_TPSF_ENTXP_Pos) /**< (GMAC_TPSF) Enable TX Partial Store and Forward Operation Mask */ +#define GMAC_TPSF_ENTXP(value) (GMAC_TPSF_ENTXP_Msk & ((value) << GMAC_TPSF_ENTXP_Pos)) +#define GMAC_TPSF_Msk _U_(0x80000FFF) /**< (GMAC_TPSF) Register Mask */ + + +/* -------- GMAC_RPSF : (GMAC Offset: 0x44) (R/W 32) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos _U_(0) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Position */ +#define GMAC_RPSF_RPB1ADR_Msk (_U_(0xFFF) << GMAC_RPSF_RPB1ADR_Pos) /**< (GMAC_RPSF) Receive Partial Store and Forward Address Mask */ +#define GMAC_RPSF_RPB1ADR(value) (GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)) +#define GMAC_RPSF_ENRXP_Pos _U_(31) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Position */ +#define GMAC_RPSF_ENRXP_Msk (_U_(0x1) << GMAC_RPSF_ENRXP_Pos) /**< (GMAC_RPSF) Enable RX Partial Store and Forward Operation Mask */ +#define GMAC_RPSF_ENRXP(value) (GMAC_RPSF_ENRXP_Msk & ((value) << GMAC_RPSF_ENRXP_Pos)) +#define GMAC_RPSF_Msk _U_(0x80000FFF) /**< (GMAC_RPSF) Register Mask */ + + +/* -------- GMAC_RJFML : (GMAC Offset: 0x48) (R/W 32) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos _U_(0) /**< (GMAC_RJFML) Frame Max Length Position */ +#define GMAC_RJFML_FML_Msk (_U_(0x3FFF) << GMAC_RJFML_FML_Pos) /**< (GMAC_RJFML) Frame Max Length Mask */ +#define GMAC_RJFML_FML(value) (GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)) +#define GMAC_RJFML_Msk _U_(0x00003FFF) /**< (GMAC_RJFML) Register Mask */ + + +/* -------- GMAC_HRB : (GMAC Offset: 0x80) (R/W 32) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos _U_(0) /**< (GMAC_HRB) Hash Address Position */ +#define GMAC_HRB_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRB_ADDR_Pos) /**< (GMAC_HRB) Hash Address Mask */ +#define GMAC_HRB_ADDR(value) (GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)) +#define GMAC_HRB_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRB) Register Mask */ + + +/* -------- GMAC_HRT : (GMAC Offset: 0x84) (R/W 32) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos _U_(0) /**< (GMAC_HRT) Hash Address Position */ +#define GMAC_HRT_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_HRT_ADDR_Pos) /**< (GMAC_HRT) Hash Address Mask */ +#define GMAC_HRT_ADDR(value) (GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)) +#define GMAC_HRT_Msk _U_(0xFFFFFFFF) /**< (GMAC_HRT) Register Mask */ + + +/* -------- GMAC_TIDM1 : (GMAC Offset: 0xA8) (R/W 32) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos _U_(0) /**< (GMAC_TIDM1) Type ID Match 1 Position */ +#define GMAC_TIDM1_TID_Msk (_U_(0xFFFF) << GMAC_TIDM1_TID_Pos) /**< (GMAC_TIDM1) Type ID Match 1 Mask */ +#define GMAC_TIDM1_TID(value) (GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)) +#define GMAC_TIDM1_ENID1_Pos _U_(31) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM1_ENID1_Msk (_U_(0x1) << GMAC_TIDM1_ENID1_Pos) /**< (GMAC_TIDM1) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM1_ENID1(value) (GMAC_TIDM1_ENID1_Msk & ((value) << GMAC_TIDM1_ENID1_Pos)) +#define GMAC_TIDM1_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM1) Register Mask */ + +#define GMAC_TIDM1_ENID_Pos _U_(31) /**< (GMAC_TIDM1 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM1_ENID_Msk (_U_(0x1) << GMAC_TIDM1_ENID_Pos) /**< (GMAC_TIDM1 Mask) ENID */ +#define GMAC_TIDM1_ENID(value) (GMAC_TIDM1_ENID_Msk & ((value) << GMAC_TIDM1_ENID_Pos)) + +/* -------- GMAC_TIDM2 : (GMAC Offset: 0xAC) (R/W 32) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos _U_(0) /**< (GMAC_TIDM2) Type ID Match 2 Position */ +#define GMAC_TIDM2_TID_Msk (_U_(0xFFFF) << GMAC_TIDM2_TID_Pos) /**< (GMAC_TIDM2) Type ID Match 2 Mask */ +#define GMAC_TIDM2_TID(value) (GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)) +#define GMAC_TIDM2_ENID2_Pos _U_(31) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM2_ENID2_Msk (_U_(0x1) << GMAC_TIDM2_ENID2_Pos) /**< (GMAC_TIDM2) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM2_ENID2(value) (GMAC_TIDM2_ENID2_Msk & ((value) << GMAC_TIDM2_ENID2_Pos)) +#define GMAC_TIDM2_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM2) Register Mask */ + +#define GMAC_TIDM2_ENID_Pos _U_(31) /**< (GMAC_TIDM2 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM2_ENID_Msk (_U_(0x1) << GMAC_TIDM2_ENID_Pos) /**< (GMAC_TIDM2 Mask) ENID */ +#define GMAC_TIDM2_ENID(value) (GMAC_TIDM2_ENID_Msk & ((value) << GMAC_TIDM2_ENID_Pos)) + +/* -------- GMAC_TIDM3 : (GMAC Offset: 0xB0) (R/W 32) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos _U_(0) /**< (GMAC_TIDM3) Type ID Match 3 Position */ +#define GMAC_TIDM3_TID_Msk (_U_(0xFFFF) << GMAC_TIDM3_TID_Pos) /**< (GMAC_TIDM3) Type ID Match 3 Mask */ +#define GMAC_TIDM3_TID(value) (GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)) +#define GMAC_TIDM3_ENID3_Pos _U_(31) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM3_ENID3_Msk (_U_(0x1) << GMAC_TIDM3_ENID3_Pos) /**< (GMAC_TIDM3) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM3_ENID3(value) (GMAC_TIDM3_ENID3_Msk & ((value) << GMAC_TIDM3_ENID3_Pos)) +#define GMAC_TIDM3_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM3) Register Mask */ + +#define GMAC_TIDM3_ENID_Pos _U_(31) /**< (GMAC_TIDM3 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM3_ENID_Msk (_U_(0x1) << GMAC_TIDM3_ENID_Pos) /**< (GMAC_TIDM3 Mask) ENID */ +#define GMAC_TIDM3_ENID(value) (GMAC_TIDM3_ENID_Msk & ((value) << GMAC_TIDM3_ENID_Pos)) + +/* -------- GMAC_TIDM4 : (GMAC Offset: 0xB4) (R/W 32) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos _U_(0) /**< (GMAC_TIDM4) Type ID Match 4 Position */ +#define GMAC_TIDM4_TID_Msk (_U_(0xFFFF) << GMAC_TIDM4_TID_Pos) /**< (GMAC_TIDM4) Type ID Match 4 Mask */ +#define GMAC_TIDM4_TID(value) (GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)) +#define GMAC_TIDM4_ENID4_Pos _U_(31) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Position */ +#define GMAC_TIDM4_ENID4_Msk (_U_(0x1) << GMAC_TIDM4_ENID4_Pos) /**< (GMAC_TIDM4) Enable Copying of TID Matched Frames Mask */ +#define GMAC_TIDM4_ENID4(value) (GMAC_TIDM4_ENID4_Msk & ((value) << GMAC_TIDM4_ENID4_Pos)) +#define GMAC_TIDM4_Msk _U_(0x8000FFFF) /**< (GMAC_TIDM4) Register Mask */ + +#define GMAC_TIDM4_ENID_Pos _U_(31) /**< (GMAC_TIDM4 Position) Enable Copying of TID Matched Frames */ +#define GMAC_TIDM4_ENID_Msk (_U_(0x1) << GMAC_TIDM4_ENID_Pos) /**< (GMAC_TIDM4 Mask) ENID */ +#define GMAC_TIDM4_ENID(value) (GMAC_TIDM4_ENID_Msk & ((value) << GMAC_TIDM4_ENID_Pos)) + +/* -------- GMAC_WOL : (GMAC Offset: 0xB8) (R/W 32) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos _U_(0) /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_IP_Msk (_U_(0xFFFF) << GMAC_WOL_IP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_IP(value) (GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)) +#define GMAC_WOL_MAG_Pos _U_(16) /**< (GMAC_WOL) Magic Packet Event Enable Position */ +#define GMAC_WOL_MAG_Msk (_U_(0x1) << GMAC_WOL_MAG_Pos) /**< (GMAC_WOL) Magic Packet Event Enable Mask */ +#define GMAC_WOL_MAG(value) (GMAC_WOL_MAG_Msk & ((value) << GMAC_WOL_MAG_Pos)) +#define GMAC_WOL_ARP_Pos _U_(17) /**< (GMAC_WOL) ARP Request IP Address Position */ +#define GMAC_WOL_ARP_Msk (_U_(0x1) << GMAC_WOL_ARP_Pos) /**< (GMAC_WOL) ARP Request IP Address Mask */ +#define GMAC_WOL_ARP(value) (GMAC_WOL_ARP_Msk & ((value) << GMAC_WOL_ARP_Pos)) +#define GMAC_WOL_SA1_Pos _U_(18) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Position */ +#define GMAC_WOL_SA1_Msk (_U_(0x1) << GMAC_WOL_SA1_Pos) /**< (GMAC_WOL) Specific Address Register 1 Event Enable Mask */ +#define GMAC_WOL_SA1(value) (GMAC_WOL_SA1_Msk & ((value) << GMAC_WOL_SA1_Pos)) +#define GMAC_WOL_MTI_Pos _U_(19) /**< (GMAC_WOL) Multicast Hash Event Enable Position */ +#define GMAC_WOL_MTI_Msk (_U_(0x1) << GMAC_WOL_MTI_Pos) /**< (GMAC_WOL) Multicast Hash Event Enable Mask */ +#define GMAC_WOL_MTI(value) (GMAC_WOL_MTI_Msk & ((value) << GMAC_WOL_MTI_Pos)) +#define GMAC_WOL_Msk _U_(0x000FFFFF) /**< (GMAC_WOL) Register Mask */ + +#define GMAC_WOL_SA_Pos _U_(18) /**< (GMAC_WOL Position) Specific Address Register x Event Enable */ +#define GMAC_WOL_SA_Msk (_U_(0x1) << GMAC_WOL_SA_Pos) /**< (GMAC_WOL Mask) SA */ +#define GMAC_WOL_SA(value) (GMAC_WOL_SA_Msk & ((value) << GMAC_WOL_SA_Pos)) + +/* -------- GMAC_IPGS : (GMAC Offset: 0xBC) (R/W 32) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos _U_(0) /**< (GMAC_IPGS) Frame Length Position */ +#define GMAC_IPGS_FL_Msk (_U_(0xFFFF) << GMAC_IPGS_FL_Pos) /**< (GMAC_IPGS) Frame Length Mask */ +#define GMAC_IPGS_FL(value) (GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)) +#define GMAC_IPGS_Msk _U_(0x0000FFFF) /**< (GMAC_IPGS) Register Mask */ + + +/* -------- GMAC_SVLAN : (GMAC Offset: 0xC0) (R/W 32) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos _U_(0) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Position */ +#define GMAC_SVLAN_VLAN_TYPE_Msk (_U_(0xFFFF) << GMAC_SVLAN_VLAN_TYPE_Pos) /**< (GMAC_SVLAN) User Defined VLAN_TYPE Field Mask */ +#define GMAC_SVLAN_VLAN_TYPE(value) (GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)) +#define GMAC_SVLAN_ESVLAN_Pos _U_(31) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Position */ +#define GMAC_SVLAN_ESVLAN_Msk (_U_(0x1) << GMAC_SVLAN_ESVLAN_Pos) /**< (GMAC_SVLAN) Enable Stacked VLAN Processing Mode Mask */ +#define GMAC_SVLAN_ESVLAN(value) (GMAC_SVLAN_ESVLAN_Msk & ((value) << GMAC_SVLAN_ESVLAN_Pos)) +#define GMAC_SVLAN_Msk _U_(0x8000FFFF) /**< (GMAC_SVLAN) Register Mask */ + + +/* -------- GMAC_TPFCP : (GMAC Offset: 0xC4) (R/W 32) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos _U_(0) /**< (GMAC_TPFCP) Priority Enable Vector Position */ +#define GMAC_TPFCP_PEV_Msk (_U_(0xFF) << GMAC_TPFCP_PEV_Pos) /**< (GMAC_TPFCP) Priority Enable Vector Mask */ +#define GMAC_TPFCP_PEV(value) (GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)) +#define GMAC_TPFCP_PQ_Pos _U_(8) /**< (GMAC_TPFCP) Pause Quantum Position */ +#define GMAC_TPFCP_PQ_Msk (_U_(0xFF) << GMAC_TPFCP_PQ_Pos) /**< (GMAC_TPFCP) Pause Quantum Mask */ +#define GMAC_TPFCP_PQ(value) (GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)) +#define GMAC_TPFCP_Msk _U_(0x0000FFFF) /**< (GMAC_TPFCP) Register Mask */ + + +/* -------- GMAC_SAMB1 : (GMAC Offset: 0xC8) (R/W 32) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos _U_(0) /**< (GMAC_SAMB1) Specific Address 1 Mask Position */ +#define GMAC_SAMB1_ADDR_Msk (_U_(0xFFFFFFFF) << GMAC_SAMB1_ADDR_Pos) /**< (GMAC_SAMB1) Specific Address 1 Mask Mask */ +#define GMAC_SAMB1_ADDR(value) (GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)) +#define GMAC_SAMB1_Msk _U_(0xFFFFFFFF) /**< (GMAC_SAMB1) Register Mask */ + + +/* -------- GMAC_SAMT1 : (GMAC Offset: 0xCC) (R/W 32) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos _U_(0) /**< (GMAC_SAMT1) Specific Address 1 Mask Position */ +#define GMAC_SAMT1_ADDR_Msk (_U_(0xFFFF) << GMAC_SAMT1_ADDR_Pos) /**< (GMAC_SAMT1) Specific Address 1 Mask Mask */ +#define GMAC_SAMT1_ADDR(value) (GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)) +#define GMAC_SAMT1_Msk _U_(0x0000FFFF) /**< (GMAC_SAMT1) Register Mask */ + + +/* -------- GMAC_NSC : (GMAC Offset: 0xDC) (R/W 32) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos _U_(0) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Position */ +#define GMAC_NSC_NANOSEC_Msk (_U_(0x3FFFFF) << GMAC_NSC_NANOSEC_Pos) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Value Mask */ +#define GMAC_NSC_NANOSEC(value) (GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)) +#define GMAC_NSC_Msk _U_(0x003FFFFF) /**< (GMAC_NSC) Register Mask */ + + +/* -------- GMAC_SCL : (GMAC Offset: 0xE0) (R/W 32) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos _U_(0) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCL_SEC_Msk (_U_(0xFFFFFFFF) << GMAC_SCL_SEC_Pos) /**< (GMAC_SCL) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCL_SEC(value) (GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)) +#define GMAC_SCL_Msk _U_(0xFFFFFFFF) /**< (GMAC_SCL) Register Mask */ + + +/* -------- GMAC_SCH : (GMAC Offset: 0xE4) (R/W 32) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos _U_(0) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Position */ +#define GMAC_SCH_SEC_Msk (_U_(0xFFFF) << GMAC_SCH_SEC_Pos) /**< (GMAC_SCH) 1588 Timer Second Comparison Value Mask */ +#define GMAC_SCH_SEC(value) (GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)) +#define GMAC_SCH_Msk _U_(0x0000FFFF) /**< (GMAC_SCH) Register Mask */ + + +/* -------- GMAC_EFTSH : (GMAC Offset: 0xE8) ( R/ 32) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos _U_(0) /**< (GMAC_EFTSH) Register Update Position */ +#define GMAC_EFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFTSH_RUD_Pos) /**< (GMAC_EFTSH) Register Update Mask */ +#define GMAC_EFTSH_RUD(value) (GMAC_EFTSH_RUD_Msk & ((value) << GMAC_EFTSH_RUD_Pos)) +#define GMAC_EFTSH_Msk _U_(0x0000FFFF) /**< (GMAC_EFTSH) Register Mask */ + + +/* -------- GMAC_EFRSH : (GMAC Offset: 0xEC) ( R/ 32) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos _U_(0) /**< (GMAC_EFRSH) Register Update Position */ +#define GMAC_EFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_EFRSH_RUD_Pos) /**< (GMAC_EFRSH) Register Update Mask */ +#define GMAC_EFRSH_RUD(value) (GMAC_EFRSH_RUD_Msk & ((value) << GMAC_EFRSH_RUD_Pos)) +#define GMAC_EFRSH_Msk _U_(0x0000FFFF) /**< (GMAC_EFRSH) Register Mask */ + + +/* -------- GMAC_PEFTSH : (GMAC Offset: 0xF0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos _U_(0) /**< (GMAC_PEFTSH) Register Update Position */ +#define GMAC_PEFTSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFTSH_RUD_Pos) /**< (GMAC_PEFTSH) Register Update Mask */ +#define GMAC_PEFTSH_RUD(value) (GMAC_PEFTSH_RUD_Msk & ((value) << GMAC_PEFTSH_RUD_Pos)) +#define GMAC_PEFTSH_Msk _U_(0x0000FFFF) /**< (GMAC_PEFTSH) Register Mask */ + + +/* -------- GMAC_PEFRSH : (GMAC Offset: 0xF4) ( R/ 32) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos _U_(0) /**< (GMAC_PEFRSH) Register Update Position */ +#define GMAC_PEFRSH_RUD_Msk (_U_(0xFFFF) << GMAC_PEFRSH_RUD_Pos) /**< (GMAC_PEFRSH) Register Update Mask */ +#define GMAC_PEFRSH_RUD(value) (GMAC_PEFRSH_RUD_Msk & ((value) << GMAC_PEFRSH_RUD_Pos)) +#define GMAC_PEFRSH_Msk _U_(0x0000FFFF) /**< (GMAC_PEFRSH) Register Mask */ + + +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) ( R/ 32) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos _U_(0) /**< (GMAC_OTLO) Transmitted Octets Position */ +#define GMAC_OTLO_TXO_Msk (_U_(0xFFFFFFFF) << GMAC_OTLO_TXO_Pos) /**< (GMAC_OTLO) Transmitted Octets Mask */ +#define GMAC_OTLO_TXO(value) (GMAC_OTLO_TXO_Msk & ((value) << GMAC_OTLO_TXO_Pos)) +#define GMAC_OTLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_OTLO) Register Mask */ + + +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) ( R/ 32) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos _U_(0) /**< (GMAC_OTHI) Transmitted Octets Position */ +#define GMAC_OTHI_TXO_Msk (_U_(0xFFFF) << GMAC_OTHI_TXO_Pos) /**< (GMAC_OTHI) Transmitted Octets Mask */ +#define GMAC_OTHI_TXO(value) (GMAC_OTHI_TXO_Msk & ((value) << GMAC_OTHI_TXO_Pos)) +#define GMAC_OTHI_Msk _U_(0x0000FFFF) /**< (GMAC_OTHI) Register Mask */ + + +/* -------- GMAC_FT : (GMAC Offset: 0x108) ( R/ 32) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos _U_(0) /**< (GMAC_FT) Frames Transmitted without Error Position */ +#define GMAC_FT_FTX_Msk (_U_(0xFFFFFFFF) << GMAC_FT_FTX_Pos) /**< (GMAC_FT) Frames Transmitted without Error Mask */ +#define GMAC_FT_FTX(value) (GMAC_FT_FTX_Msk & ((value) << GMAC_FT_FTX_Pos)) +#define GMAC_FT_Msk _U_(0xFFFFFFFF) /**< (GMAC_FT) Register Mask */ + + +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) ( R/ 32) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos _U_(0) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Position */ +#define GMAC_BCFT_BFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFT_BFTX_Pos) /**< (GMAC_BCFT) Broadcast Frames Transmitted without Error Mask */ +#define GMAC_BCFT_BFTX(value) (GMAC_BCFT_BFTX_Msk & ((value) << GMAC_BCFT_BFTX_Pos)) +#define GMAC_BCFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFT) Register Mask */ + + +/* -------- GMAC_MFT : (GMAC Offset: 0x110) ( R/ 32) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos _U_(0) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Position */ +#define GMAC_MFT_MFTX_Msk (_U_(0xFFFFFFFF) << GMAC_MFT_MFTX_Pos) /**< (GMAC_MFT) Multicast Frames Transmitted without Error Mask */ +#define GMAC_MFT_MFTX(value) (GMAC_MFT_MFTX_Msk & ((value) << GMAC_MFT_MFTX_Pos)) +#define GMAC_MFT_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFT) Register Mask */ + + +/* -------- GMAC_PFT : (GMAC Offset: 0x114) ( R/ 32) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos _U_(0) /**< (GMAC_PFT) Pause Frames Transmitted Register Position */ +#define GMAC_PFT_PFTX_Msk (_U_(0xFFFF) << GMAC_PFT_PFTX_Pos) /**< (GMAC_PFT) Pause Frames Transmitted Register Mask */ +#define GMAC_PFT_PFTX(value) (GMAC_PFT_PFTX_Msk & ((value) << GMAC_PFT_PFTX_Pos)) +#define GMAC_PFT_Msk _U_(0x0000FFFF) /**< (GMAC_PFT) Register Mask */ + + +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) ( R/ 32) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos _U_(0) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Position */ +#define GMAC_BFT64_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_BFT64_NFTX_Pos) /**< (GMAC_BFT64) 64 Byte Frames Transmitted without Error Mask */ +#define GMAC_BFT64_NFTX(value) (GMAC_BFT64_NFTX_Msk & ((value) << GMAC_BFT64_NFTX_Pos)) +#define GMAC_BFT64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFT64) Register Mask */ + + +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) ( R/ 32) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos _U_(0) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT127_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT127_NFTX_Pos) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT127_NFTX(value) (GMAC_TBFT127_NFTX_Msk & ((value) << GMAC_TBFT127_NFTX_Pos)) +#define GMAC_TBFT127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT127) Register Mask */ + + +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) ( R/ 32) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos _U_(0) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT255_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT255_NFTX_Pos) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT255_NFTX(value) (GMAC_TBFT255_NFTX_Msk & ((value) << GMAC_TBFT255_NFTX_Pos)) +#define GMAC_TBFT255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT255) Register Mask */ + + +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) ( R/ 32) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos _U_(0) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT511_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT511_NFTX_Pos) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT511_NFTX(value) (GMAC_TBFT511_NFTX_Msk & ((value) << GMAC_TBFT511_NFTX_Pos)) +#define GMAC_TBFT511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT511) Register Mask */ + + +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) ( R/ 32) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos _U_(0) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1023_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1023_NFTX_Pos) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1023_NFTX(value) (GMAC_TBFT1023_NFTX_Msk & ((value) << GMAC_TBFT1023_NFTX_Pos)) +#define GMAC_TBFT1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1023) Register Mask */ + + +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) ( R/ 32) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos _U_(0) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_TBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFT1518_NFTX_Pos) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_TBFT1518_NFTX(value) (GMAC_TBFT1518_NFTX_Msk & ((value) << GMAC_TBFT1518_NFTX_Pos)) +#define GMAC_TBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFT1518) Register Mask */ + + +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) ( R/ 32) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos _U_(0) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Position */ +#define GMAC_GTBFT1518_NFTX_Msk (_U_(0xFFFFFFFF) << GMAC_GTBFT1518_NFTX_Pos) /**< (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error Mask */ +#define GMAC_GTBFT1518_NFTX(value) (GMAC_GTBFT1518_NFTX_Msk & ((value) << GMAC_GTBFT1518_NFTX_Pos)) +#define GMAC_GTBFT1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_GTBFT1518) Register Mask */ + + +/* -------- GMAC_TUR : (GMAC Offset: 0x134) ( R/ 32) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos _U_(0) /**< (GMAC_TUR) Transmit Underruns Position */ +#define GMAC_TUR_TXUNR_Msk (_U_(0x3FF) << GMAC_TUR_TXUNR_Pos) /**< (GMAC_TUR) Transmit Underruns Mask */ +#define GMAC_TUR_TXUNR(value) (GMAC_TUR_TXUNR_Msk & ((value) << GMAC_TUR_TXUNR_Pos)) +#define GMAC_TUR_Msk _U_(0x000003FF) /**< (GMAC_TUR) Register Mask */ + + +/* -------- GMAC_SCF : (GMAC Offset: 0x138) ( R/ 32) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos _U_(0) /**< (GMAC_SCF) Single Collision Position */ +#define GMAC_SCF_SCOL_Msk (_U_(0x3FFFF) << GMAC_SCF_SCOL_Pos) /**< (GMAC_SCF) Single Collision Mask */ +#define GMAC_SCF_SCOL(value) (GMAC_SCF_SCOL_Msk & ((value) << GMAC_SCF_SCOL_Pos)) +#define GMAC_SCF_Msk _U_(0x0003FFFF) /**< (GMAC_SCF) Register Mask */ + + +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) ( R/ 32) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos _U_(0) /**< (GMAC_MCF) Multiple Collision Position */ +#define GMAC_MCF_MCOL_Msk (_U_(0x3FFFF) << GMAC_MCF_MCOL_Pos) /**< (GMAC_MCF) Multiple Collision Mask */ +#define GMAC_MCF_MCOL(value) (GMAC_MCF_MCOL_Msk & ((value) << GMAC_MCF_MCOL_Pos)) +#define GMAC_MCF_Msk _U_(0x0003FFFF) /**< (GMAC_MCF) Register Mask */ + + +/* -------- GMAC_EC : (GMAC Offset: 0x140) ( R/ 32) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos _U_(0) /**< (GMAC_EC) Excessive Collisions Position */ +#define GMAC_EC_XCOL_Msk (_U_(0x3FF) << GMAC_EC_XCOL_Pos) /**< (GMAC_EC) Excessive Collisions Mask */ +#define GMAC_EC_XCOL(value) (GMAC_EC_XCOL_Msk & ((value) << GMAC_EC_XCOL_Pos)) +#define GMAC_EC_Msk _U_(0x000003FF) /**< (GMAC_EC) Register Mask */ + + +/* -------- GMAC_LC : (GMAC Offset: 0x144) ( R/ 32) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos _U_(0) /**< (GMAC_LC) Late Collisions Position */ +#define GMAC_LC_LCOL_Msk (_U_(0x3FF) << GMAC_LC_LCOL_Pos) /**< (GMAC_LC) Late Collisions Mask */ +#define GMAC_LC_LCOL(value) (GMAC_LC_LCOL_Msk & ((value) << GMAC_LC_LCOL_Pos)) +#define GMAC_LC_Msk _U_(0x000003FF) /**< (GMAC_LC) Register Mask */ + + +/* -------- GMAC_DTF : (GMAC Offset: 0x148) ( R/ 32) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos _U_(0) /**< (GMAC_DTF) Deferred Transmission Position */ +#define GMAC_DTF_DEFT_Msk (_U_(0x3FFFF) << GMAC_DTF_DEFT_Pos) /**< (GMAC_DTF) Deferred Transmission Mask */ +#define GMAC_DTF_DEFT(value) (GMAC_DTF_DEFT_Msk & ((value) << GMAC_DTF_DEFT_Pos)) +#define GMAC_DTF_Msk _U_(0x0003FFFF) /**< (GMAC_DTF) Register Mask */ + + +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) ( R/ 32) Carrier Sense Errors Register -------- */ +#define GMAC_CSE_CSR_Pos _U_(0) /**< (GMAC_CSE) Carrier Sense Error Position */ +#define GMAC_CSE_CSR_Msk (_U_(0x3FF) << GMAC_CSE_CSR_Pos) /**< (GMAC_CSE) Carrier Sense Error Mask */ +#define GMAC_CSE_CSR(value) (GMAC_CSE_CSR_Msk & ((value) << GMAC_CSE_CSR_Pos)) +#define GMAC_CSE_Msk _U_(0x000003FF) /**< (GMAC_CSE) Register Mask */ + + +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) ( R/ 32) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos _U_(0) /**< (GMAC_ORLO) Received Octets Position */ +#define GMAC_ORLO_RXO_Msk (_U_(0xFFFFFFFF) << GMAC_ORLO_RXO_Pos) /**< (GMAC_ORLO) Received Octets Mask */ +#define GMAC_ORLO_RXO(value) (GMAC_ORLO_RXO_Msk & ((value) << GMAC_ORLO_RXO_Pos)) +#define GMAC_ORLO_Msk _U_(0xFFFFFFFF) /**< (GMAC_ORLO) Register Mask */ + + +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) ( R/ 32) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos _U_(0) /**< (GMAC_ORHI) Received Octets Position */ +#define GMAC_ORHI_RXO_Msk (_U_(0xFFFF) << GMAC_ORHI_RXO_Pos) /**< (GMAC_ORHI) Received Octets Mask */ +#define GMAC_ORHI_RXO(value) (GMAC_ORHI_RXO_Msk & ((value) << GMAC_ORHI_RXO_Pos)) +#define GMAC_ORHI_Msk _U_(0x0000FFFF) /**< (GMAC_ORHI) Register Mask */ + + +/* -------- GMAC_FR : (GMAC Offset: 0x158) ( R/ 32) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos _U_(0) /**< (GMAC_FR) Frames Received without Error Position */ +#define GMAC_FR_FRX_Msk (_U_(0xFFFFFFFF) << GMAC_FR_FRX_Pos) /**< (GMAC_FR) Frames Received without Error Mask */ +#define GMAC_FR_FRX(value) (GMAC_FR_FRX_Msk & ((value) << GMAC_FR_FRX_Pos)) +#define GMAC_FR_Msk _U_(0xFFFFFFFF) /**< (GMAC_FR) Register Mask */ + + +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) ( R/ 32) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos _U_(0) /**< (GMAC_BCFR) Broadcast Frames Received without Error Position */ +#define GMAC_BCFR_BFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BCFR_BFRX_Pos) /**< (GMAC_BCFR) Broadcast Frames Received without Error Mask */ +#define GMAC_BCFR_BFRX(value) (GMAC_BCFR_BFRX_Msk & ((value) << GMAC_BCFR_BFRX_Pos)) +#define GMAC_BCFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_BCFR) Register Mask */ + + +/* -------- GMAC_MFR : (GMAC Offset: 0x160) ( R/ 32) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos _U_(0) /**< (GMAC_MFR) Multicast Frames Received without Error Position */ +#define GMAC_MFR_MFRX_Msk (_U_(0xFFFFFFFF) << GMAC_MFR_MFRX_Pos) /**< (GMAC_MFR) Multicast Frames Received without Error Mask */ +#define GMAC_MFR_MFRX(value) (GMAC_MFR_MFRX_Msk & ((value) << GMAC_MFR_MFRX_Pos)) +#define GMAC_MFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_MFR) Register Mask */ + + +/* -------- GMAC_PFR : (GMAC Offset: 0x164) ( R/ 32) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos _U_(0) /**< (GMAC_PFR) Pause Frames Received Register Position */ +#define GMAC_PFR_PFRX_Msk (_U_(0xFFFF) << GMAC_PFR_PFRX_Pos) /**< (GMAC_PFR) Pause Frames Received Register Mask */ +#define GMAC_PFR_PFRX(value) (GMAC_PFR_PFRX_Msk & ((value) << GMAC_PFR_PFRX_Pos)) +#define GMAC_PFR_Msk _U_(0x0000FFFF) /**< (GMAC_PFR) Register Mask */ + + +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) ( R/ 32) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos _U_(0) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Position */ +#define GMAC_BFR64_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_BFR64_NFRX_Pos) /**< (GMAC_BFR64) 64 Byte Frames Received without Error Mask */ +#define GMAC_BFR64_NFRX(value) (GMAC_BFR64_NFRX_Msk & ((value) << GMAC_BFR64_NFRX_Pos)) +#define GMAC_BFR64_Msk _U_(0xFFFFFFFF) /**< (GMAC_BFR64) Register Mask */ + + +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) ( R/ 32) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos _U_(0) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Position */ +#define GMAC_TBFR127_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR127_NFRX_Pos) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error Mask */ +#define GMAC_TBFR127_NFRX(value) (GMAC_TBFR127_NFRX_Msk & ((value) << GMAC_TBFR127_NFRX_Pos)) +#define GMAC_TBFR127_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR127) Register Mask */ + + +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) ( R/ 32) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos _U_(0) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Position */ +#define GMAC_TBFR255_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR255_NFRX_Pos) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error Mask */ +#define GMAC_TBFR255_NFRX(value) (GMAC_TBFR255_NFRX_Msk & ((value) << GMAC_TBFR255_NFRX_Pos)) +#define GMAC_TBFR255_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR255) Register Mask */ + + +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) ( R/ 32) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos _U_(0) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Position */ +#define GMAC_TBFR511_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR511_NFRX_Pos) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error Mask */ +#define GMAC_TBFR511_NFRX(value) (GMAC_TBFR511_NFRX_Msk & ((value) << GMAC_TBFR511_NFRX_Pos)) +#define GMAC_TBFR511_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR511) Register Mask */ + + +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) ( R/ 32) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos _U_(0) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Position */ +#define GMAC_TBFR1023_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1023_NFRX_Pos) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1023_NFRX(value) (GMAC_TBFR1023_NFRX_Msk & ((value) << GMAC_TBFR1023_NFRX_Pos)) +#define GMAC_TBFR1023_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1023) Register Mask */ + + +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) ( R/ 32) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos _U_(0) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Position */ +#define GMAC_TBFR1518_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TBFR1518_NFRX_Pos) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error Mask */ +#define GMAC_TBFR1518_NFRX(value) (GMAC_TBFR1518_NFRX_Msk & ((value) << GMAC_TBFR1518_NFRX_Pos)) +#define GMAC_TBFR1518_Msk _U_(0xFFFFFFFF) /**< (GMAC_TBFR1518) Register Mask */ + + +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) ( R/ 32) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos _U_(0) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Position */ +#define GMAC_TMXBFR_NFRX_Msk (_U_(0xFFFFFFFF) << GMAC_TMXBFR_NFRX_Pos) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error Mask */ +#define GMAC_TMXBFR_NFRX(value) (GMAC_TMXBFR_NFRX_Msk & ((value) << GMAC_TMXBFR_NFRX_Pos)) +#define GMAC_TMXBFR_Msk _U_(0xFFFFFFFF) /**< (GMAC_TMXBFR) Register Mask */ + + +/* -------- GMAC_UFR : (GMAC Offset: 0x184) ( R/ 32) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos _U_(0) /**< (GMAC_UFR) Undersize Frames Received Position */ +#define GMAC_UFR_UFRX_Msk (_U_(0x3FF) << GMAC_UFR_UFRX_Pos) /**< (GMAC_UFR) Undersize Frames Received Mask */ +#define GMAC_UFR_UFRX(value) (GMAC_UFR_UFRX_Msk & ((value) << GMAC_UFR_UFRX_Pos)) +#define GMAC_UFR_Msk _U_(0x000003FF) /**< (GMAC_UFR) Register Mask */ + + +/* -------- GMAC_OFR : (GMAC Offset: 0x188) ( R/ 32) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos _U_(0) /**< (GMAC_OFR) Oversized Frames Received Position */ +#define GMAC_OFR_OFRX_Msk (_U_(0x3FF) << GMAC_OFR_OFRX_Pos) /**< (GMAC_OFR) Oversized Frames Received Mask */ +#define GMAC_OFR_OFRX(value) (GMAC_OFR_OFRX_Msk & ((value) << GMAC_OFR_OFRX_Pos)) +#define GMAC_OFR_Msk _U_(0x000003FF) /**< (GMAC_OFR) Register Mask */ + + +/* -------- GMAC_JR : (GMAC Offset: 0x18C) ( R/ 32) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos _U_(0) /**< (GMAC_JR) Jabbers Received Position */ +#define GMAC_JR_JRX_Msk (_U_(0x3FF) << GMAC_JR_JRX_Pos) /**< (GMAC_JR) Jabbers Received Mask */ +#define GMAC_JR_JRX(value) (GMAC_JR_JRX_Msk & ((value) << GMAC_JR_JRX_Pos)) +#define GMAC_JR_Msk _U_(0x000003FF) /**< (GMAC_JR) Register Mask */ + + +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) ( R/ 32) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos _U_(0) /**< (GMAC_FCSE) Frame Check Sequence Errors Position */ +#define GMAC_FCSE_FCKR_Msk (_U_(0x3FF) << GMAC_FCSE_FCKR_Pos) /**< (GMAC_FCSE) Frame Check Sequence Errors Mask */ +#define GMAC_FCSE_FCKR(value) (GMAC_FCSE_FCKR_Msk & ((value) << GMAC_FCSE_FCKR_Pos)) +#define GMAC_FCSE_Msk _U_(0x000003FF) /**< (GMAC_FCSE) Register Mask */ + + +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) ( R/ 32) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos _U_(0) /**< (GMAC_LFFE) Length Field Frame Errors Position */ +#define GMAC_LFFE_LFER_Msk (_U_(0x3FF) << GMAC_LFFE_LFER_Pos) /**< (GMAC_LFFE) Length Field Frame Errors Mask */ +#define GMAC_LFFE_LFER(value) (GMAC_LFFE_LFER_Msk & ((value) << GMAC_LFFE_LFER_Pos)) +#define GMAC_LFFE_Msk _U_(0x000003FF) /**< (GMAC_LFFE) Register Mask */ + + +/* -------- GMAC_RSE : (GMAC Offset: 0x198) ( R/ 32) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos _U_(0) /**< (GMAC_RSE) Receive Symbol Errors Position */ +#define GMAC_RSE_RXSE_Msk (_U_(0x3FF) << GMAC_RSE_RXSE_Pos) /**< (GMAC_RSE) Receive Symbol Errors Mask */ +#define GMAC_RSE_RXSE(value) (GMAC_RSE_RXSE_Msk & ((value) << GMAC_RSE_RXSE_Pos)) +#define GMAC_RSE_Msk _U_(0x000003FF) /**< (GMAC_RSE) Register Mask */ + + +/* -------- GMAC_AE : (GMAC Offset: 0x19C) ( R/ 32) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos _U_(0) /**< (GMAC_AE) Alignment Errors Position */ +#define GMAC_AE_AER_Msk (_U_(0x3FF) << GMAC_AE_AER_Pos) /**< (GMAC_AE) Alignment Errors Mask */ +#define GMAC_AE_AER(value) (GMAC_AE_AER_Msk & ((value) << GMAC_AE_AER_Pos)) +#define GMAC_AE_Msk _U_(0x000003FF) /**< (GMAC_AE) Register Mask */ + + +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) ( R/ 32) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos _U_(0) /**< (GMAC_RRE) Receive Resource Errors Position */ +#define GMAC_RRE_RXRER_Msk (_U_(0x3FFFF) << GMAC_RRE_RXRER_Pos) /**< (GMAC_RRE) Receive Resource Errors Mask */ +#define GMAC_RRE_RXRER(value) (GMAC_RRE_RXRER_Msk & ((value) << GMAC_RRE_RXRER_Pos)) +#define GMAC_RRE_Msk _U_(0x0003FFFF) /**< (GMAC_RRE) Register Mask */ + + +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) ( R/ 32) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos _U_(0) /**< (GMAC_ROE) Receive Overruns Position */ +#define GMAC_ROE_RXOVR_Msk (_U_(0x3FF) << GMAC_ROE_RXOVR_Pos) /**< (GMAC_ROE) Receive Overruns Mask */ +#define GMAC_ROE_RXOVR(value) (GMAC_ROE_RXOVR_Msk & ((value) << GMAC_ROE_RXOVR_Pos)) +#define GMAC_ROE_Msk _U_(0x000003FF) /**< (GMAC_ROE) Register Mask */ + + +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) ( R/ 32) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos _U_(0) /**< (GMAC_IHCE) IP Header Checksum Errors Position */ +#define GMAC_IHCE_HCKER_Msk (_U_(0xFF) << GMAC_IHCE_HCKER_Pos) /**< (GMAC_IHCE) IP Header Checksum Errors Mask */ +#define GMAC_IHCE_HCKER(value) (GMAC_IHCE_HCKER_Msk & ((value) << GMAC_IHCE_HCKER_Pos)) +#define GMAC_IHCE_Msk _U_(0x000000FF) /**< (GMAC_IHCE) Register Mask */ + + +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) ( R/ 32) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos _U_(0) /**< (GMAC_TCE) TCP Checksum Errors Position */ +#define GMAC_TCE_TCKER_Msk (_U_(0xFF) << GMAC_TCE_TCKER_Pos) /**< (GMAC_TCE) TCP Checksum Errors Mask */ +#define GMAC_TCE_TCKER(value) (GMAC_TCE_TCKER_Msk & ((value) << GMAC_TCE_TCKER_Pos)) +#define GMAC_TCE_Msk _U_(0x000000FF) /**< (GMAC_TCE) Register Mask */ + + +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) ( R/ 32) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos _U_(0) /**< (GMAC_UCE) UDP Checksum Errors Position */ +#define GMAC_UCE_UCKER_Msk (_U_(0xFF) << GMAC_UCE_UCKER_Pos) /**< (GMAC_UCE) UDP Checksum Errors Mask */ +#define GMAC_UCE_UCKER(value) (GMAC_UCE_UCKER_Msk & ((value) << GMAC_UCE_UCKER_Pos)) +#define GMAC_UCE_Msk _U_(0x000000FF) /**< (GMAC_UCE) Register Mask */ + + +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) (R/W 32) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos _U_(0) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Position */ +#define GMAC_TISUBN_LSBTIR_Msk (_U_(0xFFFF) << GMAC_TISUBN_LSBTIR_Pos) /**< (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register Mask */ +#define GMAC_TISUBN_LSBTIR(value) (GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)) +#define GMAC_TISUBN_Msk _U_(0x0000FFFF) /**< (GMAC_TISUBN) Register Mask */ + + +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) (R/W 32) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos _U_(0) /**< (GMAC_TSH) Timer Count in Seconds Position */ +#define GMAC_TSH_TCS_Msk (_U_(0xFFFF) << GMAC_TSH_TCS_Pos) /**< (GMAC_TSH) Timer Count in Seconds Mask */ +#define GMAC_TSH_TCS(value) (GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)) +#define GMAC_TSH_Msk _U_(0x0000FFFF) /**< (GMAC_TSH) Register Mask */ + + +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) (R/W 32) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos _U_(0) /**< (GMAC_TSL) Timer Count in Seconds Position */ +#define GMAC_TSL_TCS_Msk (_U_(0xFFFFFFFF) << GMAC_TSL_TCS_Pos) /**< (GMAC_TSL) Timer Count in Seconds Mask */ +#define GMAC_TSL_TCS(value) (GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)) +#define GMAC_TSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_TSL) Register Mask */ + + +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) (R/W 32) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos _U_(0) /**< (GMAC_TN) Timer Count in Nanoseconds Position */ +#define GMAC_TN_TNS_Msk (_U_(0x3FFFFFFF) << GMAC_TN_TNS_Pos) /**< (GMAC_TN) Timer Count in Nanoseconds Mask */ +#define GMAC_TN_TNS(value) (GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)) +#define GMAC_TN_Msk _U_(0x3FFFFFFF) /**< (GMAC_TN) Register Mask */ + + +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) ( /W 32) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos _U_(0) /**< (GMAC_TA) Increment/Decrement Position */ +#define GMAC_TA_ITDT_Msk (_U_(0x3FFFFFFF) << GMAC_TA_ITDT_Pos) /**< (GMAC_TA) Increment/Decrement Mask */ +#define GMAC_TA_ITDT(value) (GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)) +#define GMAC_TA_ADJ_Pos _U_(31) /**< (GMAC_TA) Adjust 1588 Timer Position */ +#define GMAC_TA_ADJ_Msk (_U_(0x1) << GMAC_TA_ADJ_Pos) /**< (GMAC_TA) Adjust 1588 Timer Mask */ +#define GMAC_TA_ADJ(value) (GMAC_TA_ADJ_Msk & ((value) << GMAC_TA_ADJ_Pos)) +#define GMAC_TA_Msk _U_(0xBFFFFFFF) /**< (GMAC_TA) Register Mask */ + + +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) (R/W 32) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos _U_(0) /**< (GMAC_TI) Count Nanoseconds Position */ +#define GMAC_TI_CNS_Msk (_U_(0xFF) << GMAC_TI_CNS_Pos) /**< (GMAC_TI) Count Nanoseconds Mask */ +#define GMAC_TI_CNS(value) (GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)) +#define GMAC_TI_ACNS_Pos _U_(8) /**< (GMAC_TI) Alternative Count Nanoseconds Position */ +#define GMAC_TI_ACNS_Msk (_U_(0xFF) << GMAC_TI_ACNS_Pos) /**< (GMAC_TI) Alternative Count Nanoseconds Mask */ +#define GMAC_TI_ACNS(value) (GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)) +#define GMAC_TI_NIT_Pos _U_(16) /**< (GMAC_TI) Number of Increments Position */ +#define GMAC_TI_NIT_Msk (_U_(0xFF) << GMAC_TI_NIT_Pos) /**< (GMAC_TI) Number of Increments Mask */ +#define GMAC_TI_NIT(value) (GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)) +#define GMAC_TI_Msk _U_(0x00FFFFFF) /**< (GMAC_TI) Register Mask */ + + +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) ( R/ 32) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos _U_(0) /**< (GMAC_EFTSL) Register Update Position */ +#define GMAC_EFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFTSL_RUD_Pos) /**< (GMAC_EFTSL) Register Update Mask */ +#define GMAC_EFTSL_RUD(value) (GMAC_EFTSL_RUD_Msk & ((value) << GMAC_EFTSL_RUD_Pos)) +#define GMAC_EFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFTSL) Register Mask */ + + +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) ( R/ 32) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos _U_(0) /**< (GMAC_EFTN) Register Update Position */ +#define GMAC_EFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFTN_RUD_Pos) /**< (GMAC_EFTN) Register Update Mask */ +#define GMAC_EFTN_RUD(value) (GMAC_EFTN_RUD_Msk & ((value) << GMAC_EFTN_RUD_Pos)) +#define GMAC_EFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFTN) Register Mask */ + + +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) ( R/ 32) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos _U_(0) /**< (GMAC_EFRSL) Register Update Position */ +#define GMAC_EFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_EFRSL_RUD_Pos) /**< (GMAC_EFRSL) Register Update Mask */ +#define GMAC_EFRSL_RUD(value) (GMAC_EFRSL_RUD_Msk & ((value) << GMAC_EFRSL_RUD_Pos)) +#define GMAC_EFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_EFRSL) Register Mask */ + + +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) ( R/ 32) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos _U_(0) /**< (GMAC_EFRN) Register Update Position */ +#define GMAC_EFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_EFRN_RUD_Pos) /**< (GMAC_EFRN) Register Update Mask */ +#define GMAC_EFRN_RUD(value) (GMAC_EFRN_RUD_Msk & ((value) << GMAC_EFRN_RUD_Pos)) +#define GMAC_EFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_EFRN) Register Mask */ + + +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) ( R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos _U_(0) /**< (GMAC_PEFTSL) Register Update Position */ +#define GMAC_PEFTSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFTSL_RUD_Pos) /**< (GMAC_PEFTSL) Register Update Mask */ +#define GMAC_PEFTSL_RUD(value) (GMAC_PEFTSL_RUD_Msk & ((value) << GMAC_PEFTSL_RUD_Pos)) +#define GMAC_PEFTSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFTSL) Register Mask */ + + +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) ( R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos _U_(0) /**< (GMAC_PEFTN) Register Update Position */ +#define GMAC_PEFTN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFTN_RUD_Pos) /**< (GMAC_PEFTN) Register Update Mask */ +#define GMAC_PEFTN_RUD(value) (GMAC_PEFTN_RUD_Msk & ((value) << GMAC_PEFTN_RUD_Pos)) +#define GMAC_PEFTN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFTN) Register Mask */ + + +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) ( R/ 32) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos _U_(0) /**< (GMAC_PEFRSL) Register Update Position */ +#define GMAC_PEFRSL_RUD_Msk (_U_(0xFFFFFFFF) << GMAC_PEFRSL_RUD_Pos) /**< (GMAC_PEFRSL) Register Update Mask */ +#define GMAC_PEFRSL_RUD(value) (GMAC_PEFRSL_RUD_Msk & ((value) << GMAC_PEFRSL_RUD_Pos)) +#define GMAC_PEFRSL_Msk _U_(0xFFFFFFFF) /**< (GMAC_PEFRSL) Register Mask */ + + +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) ( R/ 32) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos _U_(0) /**< (GMAC_PEFRN) Register Update Position */ +#define GMAC_PEFRN_RUD_Msk (_U_(0x3FFFFFFF) << GMAC_PEFRN_RUD_Pos) /**< (GMAC_PEFRN) Register Update Mask */ +#define GMAC_PEFRN_RUD(value) (GMAC_PEFRN_RUD_Msk & ((value) << GMAC_PEFRN_RUD_Pos)) +#define GMAC_PEFRN_Msk _U_(0x3FFFFFFF) /**< (GMAC_PEFRN) Register Mask */ + + +/* -------- GMAC_RXLPI : (GMAC Offset: 0x270) ( R/ 32) Received LPI Transitions -------- */ +#define GMAC_RXLPI_COUNT_Pos _U_(0) /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Position */ +#define GMAC_RXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_RXLPI_COUNT_Pos) /**< (GMAC_RXLPI) Count of RX LPI transitions (cleared on read) Mask */ +#define GMAC_RXLPI_COUNT(value) (GMAC_RXLPI_COUNT_Msk & ((value) << GMAC_RXLPI_COUNT_Pos)) +#define GMAC_RXLPI_Msk _U_(0x0000FFFF) /**< (GMAC_RXLPI) Register Mask */ + + +/* -------- GMAC_RXLPITIME : (GMAC Offset: 0x274) ( R/ 32) Received LPI Time -------- */ +#define GMAC_RXLPITIME_LPITIME_Pos _U_(0) /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Position */ +#define GMAC_RXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_RXLPITIME_LPITIME_Pos) /**< (GMAC_RXLPITIME) Time in LPI (cleared on read) Mask */ +#define GMAC_RXLPITIME_LPITIME(value) (GMAC_RXLPITIME_LPITIME_Msk & ((value) << GMAC_RXLPITIME_LPITIME_Pos)) +#define GMAC_RXLPITIME_Msk _U_(0x00FFFFFF) /**< (GMAC_RXLPITIME) Register Mask */ + + +/* -------- GMAC_TXLPI : (GMAC Offset: 0x278) ( R/ 32) Transmit LPI Transitions -------- */ +#define GMAC_TXLPI_COUNT_Pos _U_(0) /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Position */ +#define GMAC_TXLPI_COUNT_Msk (_U_(0xFFFF) << GMAC_TXLPI_COUNT_Pos) /**< (GMAC_TXLPI) Count of LPI transitions (cleared on read) Mask */ +#define GMAC_TXLPI_COUNT(value) (GMAC_TXLPI_COUNT_Msk & ((value) << GMAC_TXLPI_COUNT_Pos)) +#define GMAC_TXLPI_Msk _U_(0x0000FFFF) /**< (GMAC_TXLPI) Register Mask */ + + +/* -------- GMAC_TXLPITIME : (GMAC Offset: 0x27C) ( R/ 32) Transmit LPI Time -------- */ +#define GMAC_TXLPITIME_LPITIME_Pos _U_(0) /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Position */ +#define GMAC_TXLPITIME_LPITIME_Msk (_U_(0xFFFFFF) << GMAC_TXLPITIME_LPITIME_Pos) /**< (GMAC_TXLPITIME) Time in LPI (cleared on read) Mask */ +#define GMAC_TXLPITIME_LPITIME(value) (GMAC_TXLPITIME_LPITIME_Msk & ((value) << GMAC_TXLPITIME_LPITIME_Pos)) +#define GMAC_TXLPITIME_Msk _U_(0x00FFFFFF) /**< (GMAC_TXLPITIME) Register Mask */ + + +/* -------- GMAC_ISRPQ : (GMAC Offset: 0x400) ( R/ 32) Interrupt Status Register Priority Queue (1..5) -------- */ +#define GMAC_ISRPQ_RCOMP_Pos _U_(1) /**< (GMAC_ISRPQ) Receive Complete Position */ +#define GMAC_ISRPQ_RCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_RCOMP_Pos) /**< (GMAC_ISRPQ) Receive Complete Mask */ +#define GMAC_ISRPQ_RCOMP(value) (GMAC_ISRPQ_RCOMP_Msk & ((value) << GMAC_ISRPQ_RCOMP_Pos)) +#define GMAC_ISRPQ_RXUBR_Pos _U_(2) /**< (GMAC_ISRPQ) RX Used Bit Read Position */ +#define GMAC_ISRPQ_RXUBR_Msk (_U_(0x1) << GMAC_ISRPQ_RXUBR_Pos) /**< (GMAC_ISRPQ) RX Used Bit Read Mask */ +#define GMAC_ISRPQ_RXUBR(value) (GMAC_ISRPQ_RXUBR_Msk & ((value) << GMAC_ISRPQ_RXUBR_Pos)) +#define GMAC_ISRPQ_RLEX_Pos _U_(5) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_ISRPQ_RLEX_Msk (_U_(0x1) << GMAC_ISRPQ_RLEX_Pos) /**< (GMAC_ISRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_ISRPQ_RLEX(value) (GMAC_ISRPQ_RLEX_Msk & ((value) << GMAC_ISRPQ_RLEX_Pos)) +#define GMAC_ISRPQ_TFC_Pos _U_(6) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_ISRPQ_TFC_Msk (_U_(0x1) << GMAC_ISRPQ_TFC_Pos) /**< (GMAC_ISRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_ISRPQ_TFC(value) (GMAC_ISRPQ_TFC_Msk & ((value) << GMAC_ISRPQ_TFC_Pos)) +#define GMAC_ISRPQ_TCOMP_Pos _U_(7) /**< (GMAC_ISRPQ) Transmit Complete Position */ +#define GMAC_ISRPQ_TCOMP_Msk (_U_(0x1) << GMAC_ISRPQ_TCOMP_Pos) /**< (GMAC_ISRPQ) Transmit Complete Mask */ +#define GMAC_ISRPQ_TCOMP(value) (GMAC_ISRPQ_TCOMP_Msk & ((value) << GMAC_ISRPQ_TCOMP_Pos)) +#define GMAC_ISRPQ_ROVR_Pos _U_(10) /**< (GMAC_ISRPQ) Receive Overrun Position */ +#define GMAC_ISRPQ_ROVR_Msk (_U_(0x1) << GMAC_ISRPQ_ROVR_Pos) /**< (GMAC_ISRPQ) Receive Overrun Mask */ +#define GMAC_ISRPQ_ROVR(value) (GMAC_ISRPQ_ROVR_Msk & ((value) << GMAC_ISRPQ_ROVR_Pos)) +#define GMAC_ISRPQ_HRESP_Pos _U_(11) /**< (GMAC_ISRPQ) HRESP Not OK Position */ +#define GMAC_ISRPQ_HRESP_Msk (_U_(0x1) << GMAC_ISRPQ_HRESP_Pos) /**< (GMAC_ISRPQ) HRESP Not OK Mask */ +#define GMAC_ISRPQ_HRESP(value) (GMAC_ISRPQ_HRESP_Msk & ((value) << GMAC_ISRPQ_HRESP_Pos)) +#define GMAC_ISRPQ_Msk _U_(0x00000CE6) /**< (GMAC_ISRPQ) Register Mask */ + + +/* -------- GMAC_TBQBAPQ : (GMAC Offset: 0x440) (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos _U_(2) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Position */ +#define GMAC_TBQBAPQ_TXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_TBQBAPQ_TXBQBA_Pos) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Mask */ +#define GMAC_TBQBAPQ_TXBQBA(value) (GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)) +#define GMAC_TBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_TBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBQBAPQ : (GMAC Offset: 0x480) (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos _U_(2) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Position */ +#define GMAC_RBQBAPQ_RXBQBA_Msk (_U_(0x3FFFFFFF) << GMAC_RBQBAPQ_RXBQBA_Pos) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Mask */ +#define GMAC_RBQBAPQ_RXBQBA(value) (GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)) +#define GMAC_RBQBAPQ_Msk _U_(0xFFFFFFFC) /**< (GMAC_RBQBAPQ) Register Mask */ + + +/* -------- GMAC_RBSRPQ : (GMAC Offset: 0x4A0) (R/W 32) Receive Buffer Size Register Priority Queue (1..5) -------- */ +#define GMAC_RBSRPQ_RBS_Pos _U_(0) /**< (GMAC_RBSRPQ) Receive Buffer Size Position */ +#define GMAC_RBSRPQ_RBS_Msk (_U_(0xFFFF) << GMAC_RBSRPQ_RBS_Pos) /**< (GMAC_RBSRPQ) Receive Buffer Size Mask */ +#define GMAC_RBSRPQ_RBS(value) (GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)) +#define GMAC_RBSRPQ_Msk _U_(0x0000FFFF) /**< (GMAC_RBSRPQ) Register Mask */ + + +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) (R/W 32) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE_Pos _U_(0) /**< (GMAC_CBSCR) Queue B CBS Enable Position */ +#define GMAC_CBSCR_QBE_Msk (_U_(0x1) << GMAC_CBSCR_QBE_Pos) /**< (GMAC_CBSCR) Queue B CBS Enable Mask */ +#define GMAC_CBSCR_QBE(value) (GMAC_CBSCR_QBE_Msk & ((value) << GMAC_CBSCR_QBE_Pos)) +#define GMAC_CBSCR_QAE_Pos _U_(1) /**< (GMAC_CBSCR) Queue A CBS Enable Position */ +#define GMAC_CBSCR_QAE_Msk (_U_(0x1) << GMAC_CBSCR_QAE_Pos) /**< (GMAC_CBSCR) Queue A CBS Enable Mask */ +#define GMAC_CBSCR_QAE(value) (GMAC_CBSCR_QAE_Msk & ((value) << GMAC_CBSCR_QAE_Pos)) +#define GMAC_CBSCR_Msk _U_(0x00000003) /**< (GMAC_CBSCR) Register Mask */ + + +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos _U_(0) /**< (GMAC_CBSISQA) IdleSlope Position */ +#define GMAC_CBSISQA_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQA_IS_Pos) /**< (GMAC_CBSISQA) IdleSlope Mask */ +#define GMAC_CBSISQA_IS(value) (GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)) +#define GMAC_CBSISQA_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQA) Register Mask */ + + +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos _U_(0) /**< (GMAC_CBSISQB) IdleSlope Position */ +#define GMAC_CBSISQB_IS_Msk (_U_(0xFFFFFFFF) << GMAC_CBSISQB_IS_Pos) /**< (GMAC_CBSISQB) IdleSlope Mask */ +#define GMAC_CBSISQB_IS(value) (GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)) +#define GMAC_CBSISQB_Msk _U_(0xFFFFFFFF) /**< (GMAC_CBSISQB) Register Mask */ + + +/* -------- GMAC_ST1RPQ : (GMAC Offset: 0x500) (R/W 32) Screening Type 1 Register Priority Queue -------- */ +#define GMAC_ST1RPQ_QNB_Pos _U_(0) /**< (GMAC_ST1RPQ) Queue Number (0-5) Position */ +#define GMAC_ST1RPQ_QNB_Msk (_U_(0x7) << GMAC_ST1RPQ_QNB_Pos) /**< (GMAC_ST1RPQ) Queue Number (0-5) Mask */ +#define GMAC_ST1RPQ_QNB(value) (GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)) +#define GMAC_ST1RPQ_DSTCM_Pos _U_(4) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Position */ +#define GMAC_ST1RPQ_DSTCM_Msk (_U_(0xFF) << GMAC_ST1RPQ_DSTCM_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Mask */ +#define GMAC_ST1RPQ_DSTCM(value) (GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)) +#define GMAC_ST1RPQ_UDPM_Pos _U_(12) /**< (GMAC_ST1RPQ) UDP Port Match Position */ +#define GMAC_ST1RPQ_UDPM_Msk (_U_(0xFFFF) << GMAC_ST1RPQ_UDPM_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Mask */ +#define GMAC_ST1RPQ_UDPM(value) (GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)) +#define GMAC_ST1RPQ_DSTCE_Pos _U_(28) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Position */ +#define GMAC_ST1RPQ_DSTCE_Msk (_U_(0x1) << GMAC_ST1RPQ_DSTCE_Pos) /**< (GMAC_ST1RPQ) Differentiated Services or Traffic Class Match Enable Mask */ +#define GMAC_ST1RPQ_DSTCE(value) (GMAC_ST1RPQ_DSTCE_Msk & ((value) << GMAC_ST1RPQ_DSTCE_Pos)) +#define GMAC_ST1RPQ_UDPE_Pos _U_(29) /**< (GMAC_ST1RPQ) UDP Port Match Enable Position */ +#define GMAC_ST1RPQ_UDPE_Msk (_U_(0x1) << GMAC_ST1RPQ_UDPE_Pos) /**< (GMAC_ST1RPQ) UDP Port Match Enable Mask */ +#define GMAC_ST1RPQ_UDPE(value) (GMAC_ST1RPQ_UDPE_Msk & ((value) << GMAC_ST1RPQ_UDPE_Pos)) +#define GMAC_ST1RPQ_Msk _U_(0x3FFFFFF7) /**< (GMAC_ST1RPQ) Register Mask */ + + +/* -------- GMAC_ST2RPQ : (GMAC Offset: 0x540) (R/W 32) Screening Type 2 Register Priority Queue -------- */ +#define GMAC_ST2RPQ_QNB_Pos _U_(0) /**< (GMAC_ST2RPQ) Queue Number (0-5) Position */ +#define GMAC_ST2RPQ_QNB_Msk (_U_(0x7) << GMAC_ST2RPQ_QNB_Pos) /**< (GMAC_ST2RPQ) Queue Number (0-5) Mask */ +#define GMAC_ST2RPQ_QNB(value) (GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)) +#define GMAC_ST2RPQ_VLANP_Pos _U_(4) /**< (GMAC_ST2RPQ) VLAN Priority Position */ +#define GMAC_ST2RPQ_VLANP_Msk (_U_(0x7) << GMAC_ST2RPQ_VLANP_Pos) /**< (GMAC_ST2RPQ) VLAN Priority Mask */ +#define GMAC_ST2RPQ_VLANP(value) (GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)) +#define GMAC_ST2RPQ_VLANE_Pos _U_(8) /**< (GMAC_ST2RPQ) VLAN Enable Position */ +#define GMAC_ST2RPQ_VLANE_Msk (_U_(0x1) << GMAC_ST2RPQ_VLANE_Pos) /**< (GMAC_ST2RPQ) VLAN Enable Mask */ +#define GMAC_ST2RPQ_VLANE(value) (GMAC_ST2RPQ_VLANE_Msk & ((value) << GMAC_ST2RPQ_VLANE_Pos)) +#define GMAC_ST2RPQ_I2ETH_Pos _U_(9) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Position */ +#define GMAC_ST2RPQ_I2ETH_Msk (_U_(0x7) << GMAC_ST2RPQ_I2ETH_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 EtherType register x Mask */ +#define GMAC_ST2RPQ_I2ETH(value) (GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)) +#define GMAC_ST2RPQ_ETHE_Pos _U_(12) /**< (GMAC_ST2RPQ) EtherType Enable Position */ +#define GMAC_ST2RPQ_ETHE_Msk (_U_(0x1) << GMAC_ST2RPQ_ETHE_Pos) /**< (GMAC_ST2RPQ) EtherType Enable Mask */ +#define GMAC_ST2RPQ_ETHE(value) (GMAC_ST2RPQ_ETHE_Msk & ((value) << GMAC_ST2RPQ_ETHE_Pos)) +#define GMAC_ST2RPQ_COMPA_Pos _U_(13) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPA_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPA_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPA(value) (GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)) +#define GMAC_ST2RPQ_COMPAE_Pos _U_(18) /**< (GMAC_ST2RPQ) Compare A Enable Position */ +#define GMAC_ST2RPQ_COMPAE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPAE_Pos) /**< (GMAC_ST2RPQ) Compare A Enable Mask */ +#define GMAC_ST2RPQ_COMPAE(value) (GMAC_ST2RPQ_COMPAE_Msk & ((value) << GMAC_ST2RPQ_COMPAE_Pos)) +#define GMAC_ST2RPQ_COMPB_Pos _U_(19) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPB_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPB_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPB(value) (GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)) +#define GMAC_ST2RPQ_COMPBE_Pos _U_(24) /**< (GMAC_ST2RPQ) Compare B Enable Position */ +#define GMAC_ST2RPQ_COMPBE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPBE_Pos) /**< (GMAC_ST2RPQ) Compare B Enable Mask */ +#define GMAC_ST2RPQ_COMPBE(value) (GMAC_ST2RPQ_COMPBE_Msk & ((value) << GMAC_ST2RPQ_COMPBE_Pos)) +#define GMAC_ST2RPQ_COMPC_Pos _U_(25) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Position */ +#define GMAC_ST2RPQ_COMPC_Msk (_U_(0x1F) << GMAC_ST2RPQ_COMPC_Pos) /**< (GMAC_ST2RPQ) Index of Screening Type 2 Compare Word 0/Word 1 register x Mask */ +#define GMAC_ST2RPQ_COMPC(value) (GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)) +#define GMAC_ST2RPQ_COMPCE_Pos _U_(30) /**< (GMAC_ST2RPQ) Compare C Enable Position */ +#define GMAC_ST2RPQ_COMPCE_Msk (_U_(0x1) << GMAC_ST2RPQ_COMPCE_Pos) /**< (GMAC_ST2RPQ) Compare C Enable Mask */ +#define GMAC_ST2RPQ_COMPCE(value) (GMAC_ST2RPQ_COMPCE_Msk & ((value) << GMAC_ST2RPQ_COMPCE_Pos)) +#define GMAC_ST2RPQ_Msk _U_(0x7FFFFF77) /**< (GMAC_ST2RPQ) Register Mask */ + + +/* -------- GMAC_IERPQ : (GMAC Offset: 0x600) ( /W 32) Interrupt Enable Register Priority Queue (1..5) -------- */ +#define GMAC_IERPQ_RCOMP_Pos _U_(1) /**< (GMAC_IERPQ) Receive Complete Position */ +#define GMAC_IERPQ_RCOMP_Msk (_U_(0x1) << GMAC_IERPQ_RCOMP_Pos) /**< (GMAC_IERPQ) Receive Complete Mask */ +#define GMAC_IERPQ_RCOMP(value) (GMAC_IERPQ_RCOMP_Msk & ((value) << GMAC_IERPQ_RCOMP_Pos)) +#define GMAC_IERPQ_RXUBR_Pos _U_(2) /**< (GMAC_IERPQ) RX Used Bit Read Position */ +#define GMAC_IERPQ_RXUBR_Msk (_U_(0x1) << GMAC_IERPQ_RXUBR_Pos) /**< (GMAC_IERPQ) RX Used Bit Read Mask */ +#define GMAC_IERPQ_RXUBR(value) (GMAC_IERPQ_RXUBR_Msk & ((value) << GMAC_IERPQ_RXUBR_Pos)) +#define GMAC_IERPQ_RLEX_Pos _U_(5) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IERPQ_RLEX_Msk (_U_(0x1) << GMAC_IERPQ_RLEX_Pos) /**< (GMAC_IERPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IERPQ_RLEX(value) (GMAC_IERPQ_RLEX_Msk & ((value) << GMAC_IERPQ_RLEX_Pos)) +#define GMAC_IERPQ_TFC_Pos _U_(6) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IERPQ_TFC_Msk (_U_(0x1) << GMAC_IERPQ_TFC_Pos) /**< (GMAC_IERPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IERPQ_TFC(value) (GMAC_IERPQ_TFC_Msk & ((value) << GMAC_IERPQ_TFC_Pos)) +#define GMAC_IERPQ_TCOMP_Pos _U_(7) /**< (GMAC_IERPQ) Transmit Complete Position */ +#define GMAC_IERPQ_TCOMP_Msk (_U_(0x1) << GMAC_IERPQ_TCOMP_Pos) /**< (GMAC_IERPQ) Transmit Complete Mask */ +#define GMAC_IERPQ_TCOMP(value) (GMAC_IERPQ_TCOMP_Msk & ((value) << GMAC_IERPQ_TCOMP_Pos)) +#define GMAC_IERPQ_ROVR_Pos _U_(10) /**< (GMAC_IERPQ) Receive Overrun Position */ +#define GMAC_IERPQ_ROVR_Msk (_U_(0x1) << GMAC_IERPQ_ROVR_Pos) /**< (GMAC_IERPQ) Receive Overrun Mask */ +#define GMAC_IERPQ_ROVR(value) (GMAC_IERPQ_ROVR_Msk & ((value) << GMAC_IERPQ_ROVR_Pos)) +#define GMAC_IERPQ_HRESP_Pos _U_(11) /**< (GMAC_IERPQ) HRESP Not OK Position */ +#define GMAC_IERPQ_HRESP_Msk (_U_(0x1) << GMAC_IERPQ_HRESP_Pos) /**< (GMAC_IERPQ) HRESP Not OK Mask */ +#define GMAC_IERPQ_HRESP(value) (GMAC_IERPQ_HRESP_Msk & ((value) << GMAC_IERPQ_HRESP_Pos)) +#define GMAC_IERPQ_Msk _U_(0x00000CE6) /**< (GMAC_IERPQ) Register Mask */ + + +/* -------- GMAC_IDRPQ : (GMAC Offset: 0x620) ( /W 32) Interrupt Disable Register Priority Queue (1..5) -------- */ +#define GMAC_IDRPQ_RCOMP_Pos _U_(1) /**< (GMAC_IDRPQ) Receive Complete Position */ +#define GMAC_IDRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_RCOMP_Pos) /**< (GMAC_IDRPQ) Receive Complete Mask */ +#define GMAC_IDRPQ_RCOMP(value) (GMAC_IDRPQ_RCOMP_Msk & ((value) << GMAC_IDRPQ_RCOMP_Pos)) +#define GMAC_IDRPQ_RXUBR_Pos _U_(2) /**< (GMAC_IDRPQ) RX Used Bit Read Position */ +#define GMAC_IDRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IDRPQ_RXUBR_Pos) /**< (GMAC_IDRPQ) RX Used Bit Read Mask */ +#define GMAC_IDRPQ_RXUBR(value) (GMAC_IDRPQ_RXUBR_Msk & ((value) << GMAC_IDRPQ_RXUBR_Pos)) +#define GMAC_IDRPQ_RLEX_Pos _U_(5) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IDRPQ_RLEX_Msk (_U_(0x1) << GMAC_IDRPQ_RLEX_Pos) /**< (GMAC_IDRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IDRPQ_RLEX(value) (GMAC_IDRPQ_RLEX_Msk & ((value) << GMAC_IDRPQ_RLEX_Pos)) +#define GMAC_IDRPQ_TFC_Pos _U_(6) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Position */ +#define GMAC_IDRPQ_TFC_Msk (_U_(0x1) << GMAC_IDRPQ_TFC_Pos) /**< (GMAC_IDRPQ) Transmit Frame Corruption Due to AHB Error Mask */ +#define GMAC_IDRPQ_TFC(value) (GMAC_IDRPQ_TFC_Msk & ((value) << GMAC_IDRPQ_TFC_Pos)) +#define GMAC_IDRPQ_TCOMP_Pos _U_(7) /**< (GMAC_IDRPQ) Transmit Complete Position */ +#define GMAC_IDRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IDRPQ_TCOMP_Pos) /**< (GMAC_IDRPQ) Transmit Complete Mask */ +#define GMAC_IDRPQ_TCOMP(value) (GMAC_IDRPQ_TCOMP_Msk & ((value) << GMAC_IDRPQ_TCOMP_Pos)) +#define GMAC_IDRPQ_ROVR_Pos _U_(10) /**< (GMAC_IDRPQ) Receive Overrun Position */ +#define GMAC_IDRPQ_ROVR_Msk (_U_(0x1) << GMAC_IDRPQ_ROVR_Pos) /**< (GMAC_IDRPQ) Receive Overrun Mask */ +#define GMAC_IDRPQ_ROVR(value) (GMAC_IDRPQ_ROVR_Msk & ((value) << GMAC_IDRPQ_ROVR_Pos)) +#define GMAC_IDRPQ_HRESP_Pos _U_(11) /**< (GMAC_IDRPQ) HRESP Not OK Position */ +#define GMAC_IDRPQ_HRESP_Msk (_U_(0x1) << GMAC_IDRPQ_HRESP_Pos) /**< (GMAC_IDRPQ) HRESP Not OK Mask */ +#define GMAC_IDRPQ_HRESP(value) (GMAC_IDRPQ_HRESP_Msk & ((value) << GMAC_IDRPQ_HRESP_Pos)) +#define GMAC_IDRPQ_Msk _U_(0x00000CE6) /**< (GMAC_IDRPQ) Register Mask */ + + +/* -------- GMAC_IMRPQ : (GMAC Offset: 0x640) (R/W 32) Interrupt Mask Register Priority Queue (1..5) -------- */ +#define GMAC_IMRPQ_RCOMP_Pos _U_(1) /**< (GMAC_IMRPQ) Receive Complete Position */ +#define GMAC_IMRPQ_RCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_RCOMP_Pos) /**< (GMAC_IMRPQ) Receive Complete Mask */ +#define GMAC_IMRPQ_RCOMP(value) (GMAC_IMRPQ_RCOMP_Msk & ((value) << GMAC_IMRPQ_RCOMP_Pos)) +#define GMAC_IMRPQ_RXUBR_Pos _U_(2) /**< (GMAC_IMRPQ) RX Used Bit Read Position */ +#define GMAC_IMRPQ_RXUBR_Msk (_U_(0x1) << GMAC_IMRPQ_RXUBR_Pos) /**< (GMAC_IMRPQ) RX Used Bit Read Mask */ +#define GMAC_IMRPQ_RXUBR(value) (GMAC_IMRPQ_RXUBR_Msk & ((value) << GMAC_IMRPQ_RXUBR_Pos)) +#define GMAC_IMRPQ_RLEX_Pos _U_(5) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Position */ +#define GMAC_IMRPQ_RLEX_Msk (_U_(0x1) << GMAC_IMRPQ_RLEX_Pos) /**< (GMAC_IMRPQ) Retry Limit Exceeded or Late Collision Mask */ +#define GMAC_IMRPQ_RLEX(value) (GMAC_IMRPQ_RLEX_Msk & ((value) << GMAC_IMRPQ_RLEX_Pos)) +#define GMAC_IMRPQ_AHB_Pos _U_(6) /**< (GMAC_IMRPQ) AHB Error Position */ +#define GMAC_IMRPQ_AHB_Msk (_U_(0x1) << GMAC_IMRPQ_AHB_Pos) /**< (GMAC_IMRPQ) AHB Error Mask */ +#define GMAC_IMRPQ_AHB(value) (GMAC_IMRPQ_AHB_Msk & ((value) << GMAC_IMRPQ_AHB_Pos)) +#define GMAC_IMRPQ_TCOMP_Pos _U_(7) /**< (GMAC_IMRPQ) Transmit Complete Position */ +#define GMAC_IMRPQ_TCOMP_Msk (_U_(0x1) << GMAC_IMRPQ_TCOMP_Pos) /**< (GMAC_IMRPQ) Transmit Complete Mask */ +#define GMAC_IMRPQ_TCOMP(value) (GMAC_IMRPQ_TCOMP_Msk & ((value) << GMAC_IMRPQ_TCOMP_Pos)) +#define GMAC_IMRPQ_ROVR_Pos _U_(10) /**< (GMAC_IMRPQ) Receive Overrun Position */ +#define GMAC_IMRPQ_ROVR_Msk (_U_(0x1) << GMAC_IMRPQ_ROVR_Pos) /**< (GMAC_IMRPQ) Receive Overrun Mask */ +#define GMAC_IMRPQ_ROVR(value) (GMAC_IMRPQ_ROVR_Msk & ((value) << GMAC_IMRPQ_ROVR_Pos)) +#define GMAC_IMRPQ_HRESP_Pos _U_(11) /**< (GMAC_IMRPQ) HRESP Not OK Position */ +#define GMAC_IMRPQ_HRESP_Msk (_U_(0x1) << GMAC_IMRPQ_HRESP_Pos) /**< (GMAC_IMRPQ) HRESP Not OK Mask */ +#define GMAC_IMRPQ_HRESP(value) (GMAC_IMRPQ_HRESP_Msk & ((value) << GMAC_IMRPQ_HRESP_Pos)) +#define GMAC_IMRPQ_Msk _U_(0x00000CE6) /**< (GMAC_IMRPQ) Register Mask */ + + +/* -------- GMAC_ST2ER : (GMAC Offset: 0x6E0) (R/W 32) Screening Type 2 Ethertype Register -------- */ +#define GMAC_ST2ER_COMPVAL_Pos _U_(0) /**< (GMAC_ST2ER) Ethertype Compare Value Position */ +#define GMAC_ST2ER_COMPVAL_Msk (_U_(0xFFFF) << GMAC_ST2ER_COMPVAL_Pos) /**< (GMAC_ST2ER) Ethertype Compare Value Mask */ +#define GMAC_ST2ER_COMPVAL(value) (GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)) +#define GMAC_ST2ER_Msk _U_(0x0000FFFF) /**< (GMAC_ST2ER) Register Mask */ + + +/** \brief GMAC register offsets definitions */ +#define GMAC_SAB_REG_OFST (0x00) /**< (GMAC_SAB) Specific Address 1 Bottom Register Offset */ +#define GMAC_SAT_REG_OFST (0x04) /**< (GMAC_SAT) Specific Address 1 Top Register Offset */ +#define GMAC_ST2CW0_REG_OFST (0x00) /**< (GMAC_ST2CW0) Screening Type 2 Compare Word 0 Register Offset */ +#define GMAC_ST2CW1_REG_OFST (0x04) /**< (GMAC_ST2CW1) Screening Type 2 Compare Word 1 Register Offset */ +#define GMAC_NCR_REG_OFST (0x00) /**< (GMAC_NCR) Network Control Register Offset */ +#define GMAC_NCFGR_REG_OFST (0x04) /**< (GMAC_NCFGR) Network Configuration Register Offset */ +#define GMAC_NSR_REG_OFST (0x08) /**< (GMAC_NSR) Network Status Register Offset */ +#define GMAC_UR_REG_OFST (0x0C) /**< (GMAC_UR) User Register Offset */ +#define GMAC_DCFGR_REG_OFST (0x10) /**< (GMAC_DCFGR) DMA Configuration Register Offset */ +#define GMAC_TSR_REG_OFST (0x14) /**< (GMAC_TSR) Transmit Status Register Offset */ +#define GMAC_RBQB_REG_OFST (0x18) /**< (GMAC_RBQB) Receive Buffer Queue Base Address Register Offset */ +#define GMAC_TBQB_REG_OFST (0x1C) /**< (GMAC_TBQB) Transmit Buffer Queue Base Address Register Offset */ +#define GMAC_RSR_REG_OFST (0x20) /**< (GMAC_RSR) Receive Status Register Offset */ +#define GMAC_ISR_REG_OFST (0x24) /**< (GMAC_ISR) Interrupt Status Register Offset */ +#define GMAC_IER_REG_OFST (0x28) /**< (GMAC_IER) Interrupt Enable Register Offset */ +#define GMAC_IDR_REG_OFST (0x2C) /**< (GMAC_IDR) Interrupt Disable Register Offset */ +#define GMAC_IMR_REG_OFST (0x30) /**< (GMAC_IMR) Interrupt Mask Register Offset */ +#define GMAC_MAN_REG_OFST (0x34) /**< (GMAC_MAN) PHY Maintenance Register Offset */ +#define GMAC_RPQ_REG_OFST (0x38) /**< (GMAC_RPQ) Received Pause Quantum Register Offset */ +#define GMAC_TPQ_REG_OFST (0x3C) /**< (GMAC_TPQ) Transmit Pause Quantum Register Offset */ +#define GMAC_TPSF_REG_OFST (0x40) /**< (GMAC_TPSF) TX Partial Store and Forward Register Offset */ +#define GMAC_RPSF_REG_OFST (0x44) /**< (GMAC_RPSF) RX Partial Store and Forward Register Offset */ +#define GMAC_RJFML_REG_OFST (0x48) /**< (GMAC_RJFML) RX Jumbo Frame Max Length Register Offset */ +#define GMAC_HRB_REG_OFST (0x80) /**< (GMAC_HRB) Hash Register Bottom Offset */ +#define GMAC_HRT_REG_OFST (0x84) /**< (GMAC_HRT) Hash Register Top Offset */ +#define GMAC_TIDM1_REG_OFST (0xA8) /**< (GMAC_TIDM1) Type ID Match 1 Register Offset */ +#define GMAC_TIDM2_REG_OFST (0xAC) /**< (GMAC_TIDM2) Type ID Match 2 Register Offset */ +#define GMAC_TIDM3_REG_OFST (0xB0) /**< (GMAC_TIDM3) Type ID Match 3 Register Offset */ +#define GMAC_TIDM4_REG_OFST (0xB4) /**< (GMAC_TIDM4) Type ID Match 4 Register Offset */ +#define GMAC_WOL_REG_OFST (0xB8) /**< (GMAC_WOL) Wake on LAN Register Offset */ +#define GMAC_IPGS_REG_OFST (0xBC) /**< (GMAC_IPGS) IPG Stretch Register Offset */ +#define GMAC_SVLAN_REG_OFST (0xC0) /**< (GMAC_SVLAN) Stacked VLAN Register Offset */ +#define GMAC_TPFCP_REG_OFST (0xC4) /**< (GMAC_TPFCP) Transmit PFC Pause Register Offset */ +#define GMAC_SAMB1_REG_OFST (0xC8) /**< (GMAC_SAMB1) Specific Address 1 Mask Bottom Register Offset */ +#define GMAC_SAMT1_REG_OFST (0xCC) /**< (GMAC_SAMT1) Specific Address 1 Mask Top Register Offset */ +#define GMAC_NSC_REG_OFST (0xDC) /**< (GMAC_NSC) 1588 Timer Nanosecond Comparison Register Offset */ +#define GMAC_SCL_REG_OFST (0xE0) /**< (GMAC_SCL) 1588 Timer Second Comparison Low Register Offset */ +#define GMAC_SCH_REG_OFST (0xE4) /**< (GMAC_SCH) 1588 Timer Second Comparison High Register Offset */ +#define GMAC_EFTSH_REG_OFST (0xE8) /**< (GMAC_EFTSH) PTP Event Frame Transmitted Seconds High Register Offset */ +#define GMAC_EFRSH_REG_OFST (0xEC) /**< (GMAC_EFRSH) PTP Event Frame Received Seconds High Register Offset */ +#define GMAC_PEFTSH_REG_OFST (0xF0) /**< (GMAC_PEFTSH) PTP Peer Event Frame Transmitted Seconds High Register Offset */ +#define GMAC_PEFRSH_REG_OFST (0xF4) /**< (GMAC_PEFRSH) PTP Peer Event Frame Received Seconds High Register Offset */ +#define GMAC_OTLO_REG_OFST (0x100) /**< (GMAC_OTLO) Octets Transmitted Low Register Offset */ +#define GMAC_OTHI_REG_OFST (0x104) /**< (GMAC_OTHI) Octets Transmitted High Register Offset */ +#define GMAC_FT_REG_OFST (0x108) /**< (GMAC_FT) Frames Transmitted Register Offset */ +#define GMAC_BCFT_REG_OFST (0x10C) /**< (GMAC_BCFT) Broadcast Frames Transmitted Register Offset */ +#define GMAC_MFT_REG_OFST (0x110) /**< (GMAC_MFT) Multicast Frames Transmitted Register Offset */ +#define GMAC_PFT_REG_OFST (0x114) /**< (GMAC_PFT) Pause Frames Transmitted Register Offset */ +#define GMAC_BFT64_REG_OFST (0x118) /**< (GMAC_BFT64) 64 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT127_REG_OFST (0x11C) /**< (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT255_REG_OFST (0x120) /**< (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT511_REG_OFST (0x124) /**< (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT1023_REG_OFST (0x128) /**< (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted Register Offset */ +#define GMAC_TBFT1518_REG_OFST (0x12C) /**< (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted Register Offset */ +#define GMAC_GTBFT1518_REG_OFST (0x130) /**< (GMAC_GTBFT1518) Greater Than 1518 Byte Frames Transmitted Register Offset */ +#define GMAC_TUR_REG_OFST (0x134) /**< (GMAC_TUR) Transmit Underruns Register Offset */ +#define GMAC_SCF_REG_OFST (0x138) /**< (GMAC_SCF) Single Collision Frames Register Offset */ +#define GMAC_MCF_REG_OFST (0x13C) /**< (GMAC_MCF) Multiple Collision Frames Register Offset */ +#define GMAC_EC_REG_OFST (0x140) /**< (GMAC_EC) Excessive Collisions Register Offset */ +#define GMAC_LC_REG_OFST (0x144) /**< (GMAC_LC) Late Collisions Register Offset */ +#define GMAC_DTF_REG_OFST (0x148) /**< (GMAC_DTF) Deferred Transmission Frames Register Offset */ +#define GMAC_CSE_REG_OFST (0x14C) /**< (GMAC_CSE) Carrier Sense Errors Register Offset */ +#define GMAC_ORLO_REG_OFST (0x150) /**< (GMAC_ORLO) Octets Received Low Received Register Offset */ +#define GMAC_ORHI_REG_OFST (0x154) /**< (GMAC_ORHI) Octets Received High Received Register Offset */ +#define GMAC_FR_REG_OFST (0x158) /**< (GMAC_FR) Frames Received Register Offset */ +#define GMAC_BCFR_REG_OFST (0x15C) /**< (GMAC_BCFR) Broadcast Frames Received Register Offset */ +#define GMAC_MFR_REG_OFST (0x160) /**< (GMAC_MFR) Multicast Frames Received Register Offset */ +#define GMAC_PFR_REG_OFST (0x164) /**< (GMAC_PFR) Pause Frames Received Register Offset */ +#define GMAC_BFR64_REG_OFST (0x168) /**< (GMAC_BFR64) 64 Byte Frames Received Register Offset */ +#define GMAC_TBFR127_REG_OFST (0x16C) /**< (GMAC_TBFR127) 65 to 127 Byte Frames Received Register Offset */ +#define GMAC_TBFR255_REG_OFST (0x170) /**< (GMAC_TBFR255) 128 to 255 Byte Frames Received Register Offset */ +#define GMAC_TBFR511_REG_OFST (0x174) /**< (GMAC_TBFR511) 256 to 511 Byte Frames Received Register Offset */ +#define GMAC_TBFR1023_REG_OFST (0x178) /**< (GMAC_TBFR1023) 512 to 1023 Byte Frames Received Register Offset */ +#define GMAC_TBFR1518_REG_OFST (0x17C) /**< (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received Register Offset */ +#define GMAC_TMXBFR_REG_OFST (0x180) /**< (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received Register Offset */ +#define GMAC_UFR_REG_OFST (0x184) /**< (GMAC_UFR) Undersize Frames Received Register Offset */ +#define GMAC_OFR_REG_OFST (0x188) /**< (GMAC_OFR) Oversize Frames Received Register Offset */ +#define GMAC_JR_REG_OFST (0x18C) /**< (GMAC_JR) Jabbers Received Register Offset */ +#define GMAC_FCSE_REG_OFST (0x190) /**< (GMAC_FCSE) Frame Check Sequence Errors Register Offset */ +#define GMAC_LFFE_REG_OFST (0x194) /**< (GMAC_LFFE) Length Field Frame Errors Register Offset */ +#define GMAC_RSE_REG_OFST (0x198) /**< (GMAC_RSE) Receive Symbol Errors Register Offset */ +#define GMAC_AE_REG_OFST (0x19C) /**< (GMAC_AE) Alignment Errors Register Offset */ +#define GMAC_RRE_REG_OFST (0x1A0) /**< (GMAC_RRE) Receive Resource Errors Register Offset */ +#define GMAC_ROE_REG_OFST (0x1A4) /**< (GMAC_ROE) Receive Overrun Register Offset */ +#define GMAC_IHCE_REG_OFST (0x1A8) /**< (GMAC_IHCE) IP Header Checksum Errors Register Offset */ +#define GMAC_TCE_REG_OFST (0x1AC) /**< (GMAC_TCE) TCP Checksum Errors Register Offset */ +#define GMAC_UCE_REG_OFST (0x1B0) /**< (GMAC_UCE) UDP Checksum Errors Register Offset */ +#define GMAC_TISUBN_REG_OFST (0x1BC) /**< (GMAC_TISUBN) 1588 Timer Increment Sub-nanoseconds Register Offset */ +#define GMAC_TSH_REG_OFST (0x1C0) /**< (GMAC_TSH) 1588 Timer Seconds High Register Offset */ +#define GMAC_TSL_REG_OFST (0x1D0) /**< (GMAC_TSL) 1588 Timer Seconds Low Register Offset */ +#define GMAC_TN_REG_OFST (0x1D4) /**< (GMAC_TN) 1588 Timer Nanoseconds Register Offset */ +#define GMAC_TA_REG_OFST (0x1D8) /**< (GMAC_TA) 1588 Timer Adjust Register Offset */ +#define GMAC_TI_REG_OFST (0x1DC) /**< (GMAC_TI) 1588 Timer Increment Register Offset */ +#define GMAC_EFTSL_REG_OFST (0x1E0) /**< (GMAC_EFTSL) PTP Event Frame Transmitted Seconds Low Register Offset */ +#define GMAC_EFTN_REG_OFST (0x1E4) /**< (GMAC_EFTN) PTP Event Frame Transmitted Nanoseconds Register Offset */ +#define GMAC_EFRSL_REG_OFST (0x1E8) /**< (GMAC_EFRSL) PTP Event Frame Received Seconds Low Register Offset */ +#define GMAC_EFRN_REG_OFST (0x1EC) /**< (GMAC_EFRN) PTP Event Frame Received Nanoseconds Register Offset */ +#define GMAC_PEFTSL_REG_OFST (0x1F0) /**< (GMAC_PEFTSL) PTP Peer Event Frame Transmitted Seconds Low Register Offset */ +#define GMAC_PEFTN_REG_OFST (0x1F4) /**< (GMAC_PEFTN) PTP Peer Event Frame Transmitted Nanoseconds Register Offset */ +#define GMAC_PEFRSL_REG_OFST (0x1F8) /**< (GMAC_PEFRSL) PTP Peer Event Frame Received Seconds Low Register Offset */ +#define GMAC_PEFRN_REG_OFST (0x1FC) /**< (GMAC_PEFRN) PTP Peer Event Frame Received Nanoseconds Register Offset */ +#define GMAC_RXLPI_REG_OFST (0x270) /**< (GMAC_RXLPI) Received LPI Transitions Offset */ +#define GMAC_RXLPITIME_REG_OFST (0x274) /**< (GMAC_RXLPITIME) Received LPI Time Offset */ +#define GMAC_TXLPI_REG_OFST (0x278) /**< (GMAC_TXLPI) Transmit LPI Transitions Offset */ +#define GMAC_TXLPITIME_REG_OFST (0x27C) /**< (GMAC_TXLPITIME) Transmit LPI Time Offset */ +#define GMAC_ISRPQ_REG_OFST (0x400) /**< (GMAC_ISRPQ) Interrupt Status Register Priority Queue (1..5) Offset */ +#define GMAC_TBQBAPQ_REG_OFST (0x440) /**< (GMAC_TBQBAPQ) Transmit Buffer Queue Base Address Register Priority Queue (1..5) Offset */ +#define GMAC_RBQBAPQ_REG_OFST (0x480) /**< (GMAC_RBQBAPQ) Receive Buffer Queue Base Address Register Priority Queue (1..5) Offset */ +#define GMAC_RBSRPQ_REG_OFST (0x4A0) /**< (GMAC_RBSRPQ) Receive Buffer Size Register Priority Queue (1..5) Offset */ +#define GMAC_CBSCR_REG_OFST (0x4BC) /**< (GMAC_CBSCR) Credit-Based Shaping Control Register Offset */ +#define GMAC_CBSISQA_REG_OFST (0x4C0) /**< (GMAC_CBSISQA) Credit-Based Shaping IdleSlope Register for Queue A Offset */ +#define GMAC_CBSISQB_REG_OFST (0x4C4) /**< (GMAC_CBSISQB) Credit-Based Shaping IdleSlope Register for Queue B Offset */ +#define GMAC_ST1RPQ_REG_OFST (0x500) /**< (GMAC_ST1RPQ) Screening Type 1 Register Priority Queue Offset */ +#define GMAC_ST2RPQ_REG_OFST (0x540) /**< (GMAC_ST2RPQ) Screening Type 2 Register Priority Queue Offset */ +#define GMAC_IERPQ_REG_OFST (0x600) /**< (GMAC_IERPQ) Interrupt Enable Register Priority Queue (1..5) Offset */ +#define GMAC_IDRPQ_REG_OFST (0x620) /**< (GMAC_IDRPQ) Interrupt Disable Register Priority Queue (1..5) Offset */ +#define GMAC_IMRPQ_REG_OFST (0x640) /**< (GMAC_IMRPQ) Interrupt Mask Register Priority Queue (1..5) Offset */ +#define GMAC_ST2ER_REG_OFST (0x6E0) /**< (GMAC_ST2ER) Screening Type 2 Ethertype Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GMAC_SA register API structure */ +typedef struct +{ + __IO uint32_t GMAC_SAB; /**< Offset: 0x00 (R/W 32) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< Offset: 0x04 (R/W 32) Specific Address 1 Top Register */ +} gmac_sa_registers_t; + +/** \brief GMAC_ST2CW register API structure */ +typedef struct +{ + __IO uint32_t GMAC_ST2CW0; /**< Offset: 0x00 (R/W 32) Screening Type 2 Compare Word 0 Register */ + __IO uint32_t GMAC_ST2CW1; /**< Offset: 0x04 (R/W 32) Screening Type 2 Compare Word 1 Register */ +} gmac_st2cw_registers_t; + +#define GMAC_SA_NUMBER _U_(4) + +#define GMAC_ST2CW_NUMBER _U_(24) + +/** \brief GMAC register API structure */ +typedef struct +{ + __IO uint32_t GMAC_NCR; /**< Offset: 0x00 (R/W 32) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< Offset: 0x04 (R/W 32) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< Offset: 0x08 (R/ 32) Network Status Register */ + __IO uint32_t GMAC_UR; /**< Offset: 0x0C (R/W 32) User Register */ + __IO uint32_t GMAC_DCFGR; /**< Offset: 0x10 (R/W 32) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< Offset: 0x14 (R/W 32) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< Offset: 0x18 (R/W 32) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< Offset: 0x1C (R/W 32) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< Offset: 0x20 (R/W 32) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< Offset: 0x24 (R/ 32) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< Offset: 0x28 ( /W 32) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< Offset: 0x2C ( /W 32) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< Offset: 0x30 (R/W 32) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< Offset: 0x34 (R/W 32) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< Offset: 0x38 (R/ 32) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< Offset: 0x3C (R/W 32) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< Offset: 0x40 (R/W 32) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< Offset: 0x44 (R/W 32) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< Offset: 0x48 (R/W 32) RX Jumbo Frame Max Length Register */ + __I uint8_t Reserved1[0x34]; + __IO uint32_t GMAC_HRB; /**< Offset: 0x80 (R/W 32) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< Offset: 0x84 (R/W 32) Hash Register Top */ + gmac_sa_registers_t GMAC_SA[GMAC_SA_NUMBER]; /**< Offset: 0x88 Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_TIDM1; /**< Offset: 0xA8 (R/W 32) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< Offset: 0xAC (R/W 32) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< Offset: 0xB0 (R/W 32) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< Offset: 0xB4 (R/W 32) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< Offset: 0xB8 (R/W 32) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< Offset: 0xBC (R/W 32) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< Offset: 0xC0 (R/W 32) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< Offset: 0xC4 (R/W 32) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< Offset: 0xC8 (R/W 32) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< Offset: 0xCC (R/W 32) Specific Address 1 Mask Top Register */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t GMAC_NSC; /**< Offset: 0xDC (R/W 32) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< Offset: 0xE0 (R/W 32) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< Offset: 0xE4 (R/W 32) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< Offset: 0xE8 (R/ 32) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< Offset: 0xEC (R/ 32) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< Offset: 0xF0 (R/ 32) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< Offset: 0xF4 (R/ 32) PTP Peer Event Frame Received Seconds High Register */ + __I uint8_t Reserved3[0x08]; + __I uint32_t GMAC_OTLO; /**< Offset: 0x100 (R/ 32) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< Offset: 0x104 (R/ 32) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< Offset: 0x108 (R/ 32) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< Offset: 0x10C (R/ 32) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< Offset: 0x110 (R/ 32) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< Offset: 0x114 (R/ 32) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< Offset: 0x118 (R/ 32) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< Offset: 0x11C (R/ 32) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< Offset: 0x120 (R/ 32) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< Offset: 0x124 (R/ 32) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< Offset: 0x128 (R/ 32) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< Offset: 0x12C (R/ 32) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< Offset: 0x130 (R/ 32) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< Offset: 0x134 (R/ 32) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< Offset: 0x138 (R/ 32) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< Offset: 0x13C (R/ 32) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< Offset: 0x140 (R/ 32) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< Offset: 0x144 (R/ 32) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< Offset: 0x148 (R/ 32) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< Offset: 0x14C (R/ 32) Carrier Sense Errors Register */ + __I uint32_t GMAC_ORLO; /**< Offset: 0x150 (R/ 32) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< Offset: 0x154 (R/ 32) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< Offset: 0x158 (R/ 32) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< Offset: 0x15C (R/ 32) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< Offset: 0x160 (R/ 32) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< Offset: 0x164 (R/ 32) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< Offset: 0x168 (R/ 32) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< Offset: 0x16C (R/ 32) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< Offset: 0x170 (R/ 32) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< Offset: 0x174 (R/ 32) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< Offset: 0x178 (R/ 32) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< Offset: 0x17C (R/ 32) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< Offset: 0x180 (R/ 32) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< Offset: 0x184 (R/ 32) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< Offset: 0x188 (R/ 32) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< Offset: 0x18C (R/ 32) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< Offset: 0x190 (R/ 32) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< Offset: 0x194 (R/ 32) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< Offset: 0x198 (R/ 32) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< Offset: 0x19C (R/ 32) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< Offset: 0x1A0 (R/ 32) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< Offset: 0x1A4 (R/ 32) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< Offset: 0x1A8 (R/ 32) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< Offset: 0x1AC (R/ 32) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< Offset: 0x1B0 (R/ 32) UDP Checksum Errors Register */ + __I uint8_t Reserved4[0x08]; + __IO uint32_t GMAC_TISUBN; /**< Offset: 0x1BC (R/W 32) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< Offset: 0x1C0 (R/W 32) 1588 Timer Seconds High Register */ + __I uint8_t Reserved5[0x0C]; + __IO uint32_t GMAC_TSL; /**< Offset: 0x1D0 (R/W 32) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< Offset: 0x1D4 (R/W 32) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< Offset: 0x1D8 ( /W 32) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< Offset: 0x1DC (R/W 32) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< Offset: 0x1E0 (R/ 32) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< Offset: 0x1E4 (R/ 32) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< Offset: 0x1E8 (R/ 32) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< Offset: 0x1EC (R/ 32) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< Offset: 0x1F0 (R/ 32) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< Offset: 0x1F4 (R/ 32) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< Offset: 0x1F8 (R/ 32) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< Offset: 0x1FC (R/ 32) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint8_t Reserved6[0x70]; + __I uint32_t GMAC_RXLPI; /**< Offset: 0x270 (R/ 32) Received LPI Transitions */ + __I uint32_t GMAC_RXLPITIME; /**< Offset: 0x274 (R/ 32) Received LPI Time */ + __I uint32_t GMAC_TXLPI; /**< Offset: 0x278 (R/ 32) Transmit LPI Transitions */ + __I uint32_t GMAC_TXLPITIME; /**< Offset: 0x27C (R/ 32) Transmit LPI Time */ + __I uint8_t Reserved7[0x180]; + __I uint32_t GMAC_ISRPQ[5]; /**< Offset: 0x400 (R/ 32) Interrupt Status Register Priority Queue (1..5) */ + __I uint8_t Reserved8[0x2C]; + __IO uint32_t GMAC_TBQBAPQ[5]; /**< Offset: 0x440 (R/W 32) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved9[0x2C]; + __IO uint32_t GMAC_RBQBAPQ[5]; /**< Offset: 0x480 (R/W 32) Receive Buffer Queue Base Address Register Priority Queue (1..5) */ + __I uint8_t Reserved10[0x0C]; + __IO uint32_t GMAC_RBSRPQ[5]; /**< Offset: 0x4A0 (R/W 32) Receive Buffer Size Register Priority Queue (1..5) */ + __I uint8_t Reserved11[0x08]; + __IO uint32_t GMAC_CBSCR; /**< Offset: 0x4BC (R/W 32) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< Offset: 0x4C0 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< Offset: 0x4C4 (R/W 32) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint8_t Reserved12[0x38]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< Offset: 0x500 (R/W 32) Screening Type 1 Register Priority Queue */ + __I uint8_t Reserved13[0x30]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< Offset: 0x540 (R/W 32) Screening Type 2 Register Priority Queue */ + __I uint8_t Reserved14[0xA0]; + __O uint32_t GMAC_IERPQ[5]; /**< Offset: 0x600 ( /W 32) Interrupt Enable Register Priority Queue (1..5) */ + __I uint8_t Reserved15[0x0C]; + __O uint32_t GMAC_IDRPQ[5]; /**< Offset: 0x620 ( /W 32) Interrupt Disable Register Priority Queue (1..5) */ + __I uint8_t Reserved16[0x0C]; + __IO uint32_t GMAC_IMRPQ[5]; /**< Offset: 0x640 (R/W 32) Interrupt Mask Register Priority Queue (1..5) */ + __I uint8_t Reserved17[0x8C]; + __IO uint32_t GMAC_ST2ER[4]; /**< Offset: 0x6E0 (R/W 32) Screening Type 2 Ethertype Register */ + __I uint8_t Reserved18[0x10]; + gmac_st2cw_registers_t GMAC_ST2CW[GMAC_ST2CW_NUMBER]; /**< Offset: 0x700 Screening Type 2 Compare Word 0 Register */ +} gmac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_GMAC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/gpbr.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/gpbr.h new file mode 100644 index 00000000..f3b88a5a --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/gpbr.h @@ -0,0 +1,50 @@ +/** + * \brief Component description for GPBR + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_GPBR_COMPONENT_H_ +#define _SAME70_GPBR_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR GPBR */ +/* ************************************************************************** */ + +/* -------- SYS_GPBR : (GPBR Offset: 0x00) (R/W 32) General Purpose Backup Register 0 -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos _U_(0) /**< (SYS_GPBR) Value of GPBR x Position */ +#define SYS_GPBR_GPBR_VALUE_Msk (_U_(0xFFFFFFFF) << SYS_GPBR_GPBR_VALUE_Pos) /**< (SYS_GPBR) Value of GPBR x Mask */ +#define SYS_GPBR_GPBR_VALUE(value) (SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)) +#define SYS_GPBR_Msk _U_(0xFFFFFFFF) /**< (SYS_GPBR) Register Mask */ + + +/** \brief GPBR register offsets definitions */ +#define SYS_GPBR_REG_OFST (0x00) /**< (SYS_GPBR) General Purpose Backup Register 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GPBR register API structure */ +typedef struct +{ + __IO uint32_t SYS_GPBR[8]; /**< Offset: 0x00 (R/W 32) General Purpose Backup Register 0 */ +} gpbr_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_GPBR_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/hsmci.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/hsmci.h new file mode 100644 index 00000000..ad46a05e --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/hsmci.h @@ -0,0 +1,704 @@ +/** + * \brief Component description for HSMCI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_HSMCI_COMPONENT_H_ +#define _SAME70_HSMCI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR HSMCI */ +/* ************************************************************************** */ + +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) ( /W 32) Control Register -------- */ +#define HSMCI_CR_MCIEN_Pos _U_(0) /**< (HSMCI_CR) Multi-Media Interface Enable Position */ +#define HSMCI_CR_MCIEN_Msk (_U_(0x1) << HSMCI_CR_MCIEN_Pos) /**< (HSMCI_CR) Multi-Media Interface Enable Mask */ +#define HSMCI_CR_MCIEN(value) (HSMCI_CR_MCIEN_Msk & ((value) << HSMCI_CR_MCIEN_Pos)) +#define HSMCI_CR_MCIDIS_Pos _U_(1) /**< (HSMCI_CR) Multi-Media Interface Disable Position */ +#define HSMCI_CR_MCIDIS_Msk (_U_(0x1) << HSMCI_CR_MCIDIS_Pos) /**< (HSMCI_CR) Multi-Media Interface Disable Mask */ +#define HSMCI_CR_MCIDIS(value) (HSMCI_CR_MCIDIS_Msk & ((value) << HSMCI_CR_MCIDIS_Pos)) +#define HSMCI_CR_PWSEN_Pos _U_(2) /**< (HSMCI_CR) Power Save Mode Enable Position */ +#define HSMCI_CR_PWSEN_Msk (_U_(0x1) << HSMCI_CR_PWSEN_Pos) /**< (HSMCI_CR) Power Save Mode Enable Mask */ +#define HSMCI_CR_PWSEN(value) (HSMCI_CR_PWSEN_Msk & ((value) << HSMCI_CR_PWSEN_Pos)) +#define HSMCI_CR_PWSDIS_Pos _U_(3) /**< (HSMCI_CR) Power Save Mode Disable Position */ +#define HSMCI_CR_PWSDIS_Msk (_U_(0x1) << HSMCI_CR_PWSDIS_Pos) /**< (HSMCI_CR) Power Save Mode Disable Mask */ +#define HSMCI_CR_PWSDIS(value) (HSMCI_CR_PWSDIS_Msk & ((value) << HSMCI_CR_PWSDIS_Pos)) +#define HSMCI_CR_SWRST_Pos _U_(7) /**< (HSMCI_CR) Software Reset Position */ +#define HSMCI_CR_SWRST_Msk (_U_(0x1) << HSMCI_CR_SWRST_Pos) /**< (HSMCI_CR) Software Reset Mask */ +#define HSMCI_CR_SWRST(value) (HSMCI_CR_SWRST_Msk & ((value) << HSMCI_CR_SWRST_Pos)) +#define HSMCI_CR_Msk _U_(0x0000008F) /**< (HSMCI_CR) Register Mask */ + + +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos _U_(0) /**< (HSMCI_MR) Clock Divider Position */ +#define HSMCI_MR_CLKDIV_Msk (_U_(0xFF) << HSMCI_MR_CLKDIV_Pos) /**< (HSMCI_MR) Clock Divider Mask */ +#define HSMCI_MR_CLKDIV(value) (HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)) +#define HSMCI_MR_PWSDIV_Pos _U_(8) /**< (HSMCI_MR) Power Saving Divider Position */ +#define HSMCI_MR_PWSDIV_Msk (_U_(0x7) << HSMCI_MR_PWSDIV_Pos) /**< (HSMCI_MR) Power Saving Divider Mask */ +#define HSMCI_MR_PWSDIV(value) (HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)) +#define HSMCI_MR_RDPROOF_Pos _U_(11) /**< (HSMCI_MR) Read Proof Enable Position */ +#define HSMCI_MR_RDPROOF_Msk (_U_(0x1) << HSMCI_MR_RDPROOF_Pos) /**< (HSMCI_MR) Read Proof Enable Mask */ +#define HSMCI_MR_RDPROOF(value) (HSMCI_MR_RDPROOF_Msk & ((value) << HSMCI_MR_RDPROOF_Pos)) +#define HSMCI_MR_WRPROOF_Pos _U_(12) /**< (HSMCI_MR) Write Proof Enable Position */ +#define HSMCI_MR_WRPROOF_Msk (_U_(0x1) << HSMCI_MR_WRPROOF_Pos) /**< (HSMCI_MR) Write Proof Enable Mask */ +#define HSMCI_MR_WRPROOF(value) (HSMCI_MR_WRPROOF_Msk & ((value) << HSMCI_MR_WRPROOF_Pos)) +#define HSMCI_MR_FBYTE_Pos _U_(13) /**< (HSMCI_MR) Force Byte Transfer Position */ +#define HSMCI_MR_FBYTE_Msk (_U_(0x1) << HSMCI_MR_FBYTE_Pos) /**< (HSMCI_MR) Force Byte Transfer Mask */ +#define HSMCI_MR_FBYTE(value) (HSMCI_MR_FBYTE_Msk & ((value) << HSMCI_MR_FBYTE_Pos)) +#define HSMCI_MR_PADV_Pos _U_(14) /**< (HSMCI_MR) Padding Value Position */ +#define HSMCI_MR_PADV_Msk (_U_(0x1) << HSMCI_MR_PADV_Pos) /**< (HSMCI_MR) Padding Value Mask */ +#define HSMCI_MR_PADV(value) (HSMCI_MR_PADV_Msk & ((value) << HSMCI_MR_PADV_Pos)) +#define HSMCI_MR_CLKODD_Pos _U_(16) /**< (HSMCI_MR) Clock divider is odd Position */ +#define HSMCI_MR_CLKODD_Msk (_U_(0x1) << HSMCI_MR_CLKODD_Pos) /**< (HSMCI_MR) Clock divider is odd Mask */ +#define HSMCI_MR_CLKODD(value) (HSMCI_MR_CLKODD_Msk & ((value) << HSMCI_MR_CLKODD_Pos)) +#define HSMCI_MR_Msk _U_(0x00017FFF) /**< (HSMCI_MR) Register Mask */ + + +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) (R/W 32) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos _U_(0) /**< (HSMCI_DTOR) Data Timeout Cycle Number Position */ +#define HSMCI_DTOR_DTOCYC_Msk (_U_(0xF) << HSMCI_DTOR_DTOCYC_Pos) /**< (HSMCI_DTOR) Data Timeout Cycle Number Mask */ +#define HSMCI_DTOR_DTOCYC(value) (HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)) +#define HSMCI_DTOR_DTOMUL_Pos _U_(4) /**< (HSMCI_DTOR) Data Timeout Multiplier Position */ +#define HSMCI_DTOR_DTOMUL_Msk (_U_(0x7) << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) Data Timeout Multiplier Mask */ +#define HSMCI_DTOR_DTOMUL(value) (HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)) +#define HSMCI_DTOR_DTOMUL_1_Val _U_(0x0) /**< (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16_Val _U_(0x1) /**< (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128_Val _U_(0x2) /**< (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256_Val _U_(0x3) /**< (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024_Val _U_(0x4) /**< (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096_Val _U_(0x5) /**< (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536_Val _U_(0x6) /**< (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_DTOR) DTOCYC x 1048576 */ +#define HSMCI_DTOR_DTOMUL_1 (HSMCI_DTOR_DTOMUL_1_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC Position */ +#define HSMCI_DTOR_DTOMUL_16 (HSMCI_DTOR_DTOMUL_16_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 16 Position */ +#define HSMCI_DTOR_DTOMUL_128 (HSMCI_DTOR_DTOMUL_128_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 128 Position */ +#define HSMCI_DTOR_DTOMUL_256 (HSMCI_DTOR_DTOMUL_256_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 256 Position */ +#define HSMCI_DTOR_DTOMUL_1024 (HSMCI_DTOR_DTOMUL_1024_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1024 Position */ +#define HSMCI_DTOR_DTOMUL_4096 (HSMCI_DTOR_DTOMUL_4096_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 4096 Position */ +#define HSMCI_DTOR_DTOMUL_65536 (HSMCI_DTOR_DTOMUL_65536_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 65536 Position */ +#define HSMCI_DTOR_DTOMUL_1048576 (HSMCI_DTOR_DTOMUL_1048576_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1048576 Position */ +#define HSMCI_DTOR_Msk _U_(0x0000007F) /**< (HSMCI_DTOR) Register Mask */ + + +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) (R/W 32) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos _U_(0) /**< (HSMCI_SDCR) SDCard/SDIO Slot Position */ +#define HSMCI_SDCR_SDCSEL_Msk (_U_(0x3) << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Slot Mask */ +#define HSMCI_SDCR_SDCSEL(value) (HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)) +#define HSMCI_SDCR_SDCSEL_SLOTA_Val _U_(0x0) /**< (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTA (HSMCI_SDCR_SDCSEL_SLOTA_Val << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) Slot A is selected. Position */ +#define HSMCI_SDCR_SDCBUS_Pos _U_(6) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Position */ +#define HSMCI_SDCR_SDCBUS_Msk (_U_(0x3) << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Mask */ +#define HSMCI_SDCR_SDCBUS(value) (HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)) +#define HSMCI_SDCR_SDCBUS_1_Val _U_(0x0) /**< (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4_Val _U_(0x2) /**< (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8_Val _U_(0x3) /**< (HSMCI_SDCR) 8 bits */ +#define HSMCI_SDCR_SDCBUS_1 (HSMCI_SDCR_SDCBUS_1_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 1 bit Position */ +#define HSMCI_SDCR_SDCBUS_4 (HSMCI_SDCR_SDCBUS_4_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 4 bits Position */ +#define HSMCI_SDCR_SDCBUS_8 (HSMCI_SDCR_SDCBUS_8_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 8 bits Position */ +#define HSMCI_SDCR_Msk _U_(0x000000C3) /**< (HSMCI_SDCR) Register Mask */ + + +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) (R/W 32) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos _U_(0) /**< (HSMCI_ARGR) Command Argument Position */ +#define HSMCI_ARGR_ARG_Msk (_U_(0xFFFFFFFF) << HSMCI_ARGR_ARG_Pos) /**< (HSMCI_ARGR) Command Argument Mask */ +#define HSMCI_ARGR_ARG(value) (HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)) +#define HSMCI_ARGR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_ARGR) Register Mask */ + + +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) ( /W 32) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos _U_(0) /**< (HSMCI_CMDR) Command Number Position */ +#define HSMCI_CMDR_CMDNB_Msk (_U_(0x3F) << HSMCI_CMDR_CMDNB_Pos) /**< (HSMCI_CMDR) Command Number Mask */ +#define HSMCI_CMDR_CMDNB(value) (HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)) +#define HSMCI_CMDR_RSPTYP_Pos _U_(6) /**< (HSMCI_CMDR) Response Type Position */ +#define HSMCI_CMDR_RSPTYP_Msk (_U_(0x3) << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) Response Type Mask */ +#define HSMCI_CMDR_RSPTYP(value) (HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)) +#define HSMCI_CMDR_RSPTYP_NORESP_Val _U_(0x0) /**< (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT_Val _U_(0x1) /**< (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT_Val _U_(0x2) /**< (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B_Val _U_(0x3) /**< (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_RSPTYP_NORESP (HSMCI_CMDR_RSPTYP_NORESP_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) No response Position */ +#define HSMCI_CMDR_RSPTYP_48_BIT (HSMCI_CMDR_RSPTYP_48_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 48-bit response Position */ +#define HSMCI_CMDR_RSPTYP_136_BIT (HSMCI_CMDR_RSPTYP_136_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 136-bit response Position */ +#define HSMCI_CMDR_RSPTYP_R1B (HSMCI_CMDR_RSPTYP_R1B_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) R1b response type Position */ +#define HSMCI_CMDR_SPCMD_Pos _U_(8) /**< (HSMCI_CMDR) Special Command Position */ +#define HSMCI_CMDR_SPCMD_Msk (_U_(0x7) << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Special Command Mask */ +#define HSMCI_CMDR_SPCMD(value) (HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)) +#define HSMCI_CMDR_SPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT_Val _U_(0x1) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC_Val _U_(0x2) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA_Val _U_(0x3) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD_Val _U_(0x4) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP_Val _U_(0x5) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR_Val _U_(0x6) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO_Val _U_(0x7) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_SPCMD_STD (HSMCI_CMDR_SPCMD_STD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Not a special CMD. Position */ +#define HSMCI_CMDR_SPCMD_INIT (HSMCI_CMDR_SPCMD_INIT_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. Position */ +#define HSMCI_CMDR_SPCMD_SYNC (HSMCI_CMDR_SPCMD_SYNC_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Position */ +#define HSMCI_CMDR_SPCMD_CE_ATA (HSMCI_CMDR_SPCMD_CE_ATA_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Position */ +#define HSMCI_CMDR_SPCMD_IT_CMD (HSMCI_CMDR_SPCMD_IT_CMD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_IT_RESP (HSMCI_CMDR_SPCMD_IT_RESP_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). Position */ +#define HSMCI_CMDR_SPCMD_BOR (HSMCI_CMDR_SPCMD_BOR_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. Position */ +#define HSMCI_CMDR_SPCMD_EBO (HSMCI_CMDR_SPCMD_EBO_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. Position */ +#define HSMCI_CMDR_OPDCMD_Pos _U_(11) /**< (HSMCI_CMDR) Open Drain Command Position */ +#define HSMCI_CMDR_OPDCMD_Msk (_U_(0x1) << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open Drain Command Mask */ +#define HSMCI_CMDR_OPDCMD(value) (HSMCI_CMDR_OPDCMD_Msk & ((value) << HSMCI_CMDR_OPDCMD_Pos)) +#define HSMCI_CMDR_OPDCMD_PUSHPULL_Val _U_(0x0) /**< (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN_Val _U_(0x1) /**< (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (HSMCI_CMDR_OPDCMD_PUSHPULL_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Push pull command. Position */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (HSMCI_CMDR_OPDCMD_OPENDRAIN_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open drain command. Position */ +#define HSMCI_CMDR_MAXLAT_Pos _U_(12) /**< (HSMCI_CMDR) Max Latency for Command to Response Position */ +#define HSMCI_CMDR_MAXLAT_Msk (_U_(0x1) << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) Max Latency for Command to Response Mask */ +#define HSMCI_CMDR_MAXLAT(value) (HSMCI_CMDR_MAXLAT_Msk & ((value) << HSMCI_CMDR_MAXLAT_Pos)) +#define HSMCI_CMDR_MAXLAT_5_Val _U_(0x0) /**< (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64_Val _U_(0x1) /**< (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_5 (HSMCI_CMDR_MAXLAT_5_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 5-cycle max latency. Position */ +#define HSMCI_CMDR_MAXLAT_64 (HSMCI_CMDR_MAXLAT_64_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 64-cycle max latency. Position */ +#define HSMCI_CMDR_TRCMD_Pos _U_(16) /**< (HSMCI_CMDR) Transfer Command Position */ +#define HSMCI_CMDR_TRCMD_Msk (_U_(0x3) << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Transfer Command Mask */ +#define HSMCI_CMDR_TRCMD(value) (HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)) +#define HSMCI_CMDR_TRCMD_NO_DATA_Val _U_(0x0) /**< (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA_Val _U_(0x1) /**< (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA_Val _U_(0x2) /**< (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRCMD_NO_DATA (HSMCI_CMDR_TRCMD_NO_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) No data transfer Position */ +#define HSMCI_CMDR_TRCMD_START_DATA (HSMCI_CMDR_TRCMD_START_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Start data transfer Position */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (HSMCI_CMDR_TRCMD_STOP_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Stop data transfer Position */ +#define HSMCI_CMDR_TRDIR_Pos _U_(18) /**< (HSMCI_CMDR) Transfer Direction Position */ +#define HSMCI_CMDR_TRDIR_Msk (_U_(0x1) << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Transfer Direction Mask */ +#define HSMCI_CMDR_TRDIR(value) (HSMCI_CMDR_TRDIR_Msk & ((value) << HSMCI_CMDR_TRDIR_Pos)) +#define HSMCI_CMDR_TRDIR_WRITE_Val _U_(0x0) /**< (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ_Val _U_(0x1) /**< (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRDIR_WRITE (HSMCI_CMDR_TRDIR_WRITE_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Write. Position */ +#define HSMCI_CMDR_TRDIR_READ (HSMCI_CMDR_TRDIR_READ_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Read. Position */ +#define HSMCI_CMDR_TRTYP_Pos _U_(19) /**< (HSMCI_CMDR) Transfer Type Position */ +#define HSMCI_CMDR_TRTYP_Msk (_U_(0x7) << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) Transfer Type Mask */ +#define HSMCI_CMDR_TRTYP(value) (HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)) +#define HSMCI_CMDR_TRTYP_SINGLE_Val _U_(0x0) /**< (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE_Val _U_(0x1) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM_Val _U_(0x2) /**< (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE_Val _U_(0x4) /**< (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK_Val _U_(0x5) /**< (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_TRTYP_SINGLE (HSMCI_CMDR_TRTYP_SINGLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Single Block Position */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (HSMCI_CMDR_TRTYP_MULTIPLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block Position */ +#define HSMCI_CMDR_TRTYP_STREAM (HSMCI_CMDR_TRTYP_STREAM_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC Stream Position */ +#define HSMCI_CMDR_TRTYP_BYTE (HSMCI_CMDR_TRTYP_BYTE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Byte Position */ +#define HSMCI_CMDR_TRTYP_BLOCK (HSMCI_CMDR_TRTYP_BLOCK_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Block Position */ +#define HSMCI_CMDR_IOSPCMD_Pos _U_(24) /**< (HSMCI_CMDR) SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_Msk (_U_(0x3) << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Special Command Mask */ +#define HSMCI_CMDR_IOSPCMD(value) (HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)) +#define HSMCI_CMDR_IOSPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND_Val _U_(0x1) /**< (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME_Val _U_(0x2) /**< (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_IOSPCMD_STD (HSMCI_CMDR_IOSPCMD_STD_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) Not an SDIO Special Command Position */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (HSMCI_CMDR_IOSPCMD_SUSPEND_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Suspend Command Position */ +#define HSMCI_CMDR_IOSPCMD_RESUME (HSMCI_CMDR_IOSPCMD_RESUME_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Resume Command Position */ +#define HSMCI_CMDR_ATACS_Pos _U_(26) /**< (HSMCI_CMDR) ATA with Command Completion Signal Position */ +#define HSMCI_CMDR_ATACS_Msk (_U_(0x1) << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) ATA with Command Completion Signal Mask */ +#define HSMCI_CMDR_ATACS(value) (HSMCI_CMDR_ATACS_Msk & ((value) << HSMCI_CMDR_ATACS_Pos)) +#define HSMCI_CMDR_ATACS_NORMAL_Val _U_(0x0) /**< (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION_Val _U_(0x1) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_ATACS_NORMAL (HSMCI_CMDR_ATACS_NORMAL_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) Normal operation mode. Position */ +#define HSMCI_CMDR_ATACS_COMPLETION (HSMCI_CMDR_ATACS_COMPLETION_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). Position */ +#define HSMCI_CMDR_BOOT_ACK_Pos _U_(27) /**< (HSMCI_CMDR) Boot Operation Acknowledge Position */ +#define HSMCI_CMDR_BOOT_ACK_Msk (_U_(0x1) << HSMCI_CMDR_BOOT_ACK_Pos) /**< (HSMCI_CMDR) Boot Operation Acknowledge Mask */ +#define HSMCI_CMDR_BOOT_ACK(value) (HSMCI_CMDR_BOOT_ACK_Msk & ((value) << HSMCI_CMDR_BOOT_ACK_Pos)) +#define HSMCI_CMDR_Msk _U_(0x0F3F1FFF) /**< (HSMCI_CMDR) Register Mask */ + + +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) (R/W 32) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos _U_(0) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Position */ +#define HSMCI_BLKR_BCNT_Msk (_U_(0xFFFF) << HSMCI_BLKR_BCNT_Pos) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Mask */ +#define HSMCI_BLKR_BCNT(value) (HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)) +#define HSMCI_BLKR_BLKLEN_Pos _U_(16) /**< (HSMCI_BLKR) Data Block Length Position */ +#define HSMCI_BLKR_BLKLEN_Msk (_U_(0xFFFF) << HSMCI_BLKR_BLKLEN_Pos) /**< (HSMCI_BLKR) Data Block Length Mask */ +#define HSMCI_BLKR_BLKLEN(value) (HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)) +#define HSMCI_BLKR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_BLKR) Register Mask */ + + +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) (R/W 32) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos _U_(0) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Position */ +#define HSMCI_CSTOR_CSTOCYC_Msk (_U_(0xF) << HSMCI_CSTOR_CSTOCYC_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Mask */ +#define HSMCI_CSTOR_CSTOCYC(value) (HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)) +#define HSMCI_CSTOR_CSTOMUL_Pos _U_(4) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Position */ +#define HSMCI_CSTOR_CSTOMUL_Msk (_U_(0x7) << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Mask */ +#define HSMCI_CSTOR_CSTOMUL(value) (HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)) +#define HSMCI_CSTOR_CSTOMUL_1_Val _U_(0x0) /**< (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16_Val _U_(0x1) /**< (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128_Val _U_(0x2) /**< (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256_Val _U_(0x3) /**< (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024_Val _U_(0x4) /**< (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096_Val _U_(0x5) /**< (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536_Val _U_(0x6) /**< (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 */ +#define HSMCI_CSTOR_CSTOMUL_1 (HSMCI_CSTOR_CSTOMUL_1_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1 Position */ +#define HSMCI_CSTOR_CSTOMUL_16 (HSMCI_CSTOR_CSTOMUL_16_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 16 Position */ +#define HSMCI_CSTOR_CSTOMUL_128 (HSMCI_CSTOR_CSTOMUL_128_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 128 Position */ +#define HSMCI_CSTOR_CSTOMUL_256 (HSMCI_CSTOR_CSTOMUL_256_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 256 Position */ +#define HSMCI_CSTOR_CSTOMUL_1024 (HSMCI_CSTOR_CSTOMUL_1024_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1024 Position */ +#define HSMCI_CSTOR_CSTOMUL_4096 (HSMCI_CSTOR_CSTOMUL_4096_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 4096 Position */ +#define HSMCI_CSTOR_CSTOMUL_65536 (HSMCI_CSTOR_CSTOMUL_65536_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 65536 Position */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (HSMCI_CSTOR_CSTOMUL_1048576_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 Position */ +#define HSMCI_CSTOR_Msk _U_(0x0000007F) /**< (HSMCI_CSTOR) Register Mask */ + + +/* -------- HSMCI_RSPR : (HSMCI Offset: 0x20) ( R/ 32) Response Register 0 -------- */ +#define HSMCI_RSPR_RSP_Pos _U_(0) /**< (HSMCI_RSPR) Response Position */ +#define HSMCI_RSPR_RSP_Msk (_U_(0xFFFFFFFF) << HSMCI_RSPR_RSP_Pos) /**< (HSMCI_RSPR) Response Mask */ +#define HSMCI_RSPR_RSP(value) (HSMCI_RSPR_RSP_Msk & ((value) << HSMCI_RSPR_RSP_Pos)) +#define HSMCI_RSPR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RSPR) Register Mask */ + + +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) ( R/ 32) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos _U_(0) /**< (HSMCI_RDR) Data to Read Position */ +#define HSMCI_RDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_RDR_DATA_Pos) /**< (HSMCI_RDR) Data to Read Mask */ +#define HSMCI_RDR_DATA(value) (HSMCI_RDR_DATA_Msk & ((value) << HSMCI_RDR_DATA_Pos)) +#define HSMCI_RDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RDR) Register Mask */ + + +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) ( /W 32) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos _U_(0) /**< (HSMCI_TDR) Data to Write Position */ +#define HSMCI_TDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_TDR_DATA_Pos) /**< (HSMCI_TDR) Data to Write Mask */ +#define HSMCI_TDR_DATA(value) (HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)) +#define HSMCI_TDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_TDR) Register Mask */ + + +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) ( R/ 32) Status Register -------- */ +#define HSMCI_SR_CMDRDY_Pos _U_(0) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_CMDRDY_Msk (_U_(0x1) << HSMCI_SR_CMDRDY_Pos) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_CMDRDY(value) (HSMCI_SR_CMDRDY_Msk & ((value) << HSMCI_SR_CMDRDY_Pos)) +#define HSMCI_SR_RXRDY_Pos _U_(1) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Position */ +#define HSMCI_SR_RXRDY_Msk (_U_(0x1) << HSMCI_SR_RXRDY_Pos) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Mask */ +#define HSMCI_SR_RXRDY(value) (HSMCI_SR_RXRDY_Msk & ((value) << HSMCI_SR_RXRDY_Pos)) +#define HSMCI_SR_TXRDY_Pos _U_(2) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Position */ +#define HSMCI_SR_TXRDY_Msk (_U_(0x1) << HSMCI_SR_TXRDY_Pos) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Mask */ +#define HSMCI_SR_TXRDY(value) (HSMCI_SR_TXRDY_Msk & ((value) << HSMCI_SR_TXRDY_Pos)) +#define HSMCI_SR_BLKE_Pos _U_(3) /**< (HSMCI_SR) Data Block Ended (cleared on read) Position */ +#define HSMCI_SR_BLKE_Msk (_U_(0x1) << HSMCI_SR_BLKE_Pos) /**< (HSMCI_SR) Data Block Ended (cleared on read) Mask */ +#define HSMCI_SR_BLKE(value) (HSMCI_SR_BLKE_Msk & ((value) << HSMCI_SR_BLKE_Pos)) +#define HSMCI_SR_DTIP_Pos _U_(4) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Position */ +#define HSMCI_SR_DTIP_Msk (_U_(0x1) << HSMCI_SR_DTIP_Pos) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Mask */ +#define HSMCI_SR_DTIP(value) (HSMCI_SR_DTIP_Msk & ((value) << HSMCI_SR_DTIP_Pos)) +#define HSMCI_SR_NOTBUSY_Pos _U_(5) /**< (HSMCI_SR) HSMCI Not Busy Position */ +#define HSMCI_SR_NOTBUSY_Msk (_U_(0x1) << HSMCI_SR_NOTBUSY_Pos) /**< (HSMCI_SR) HSMCI Not Busy Mask */ +#define HSMCI_SR_NOTBUSY(value) (HSMCI_SR_NOTBUSY_Msk & ((value) << HSMCI_SR_NOTBUSY_Pos)) +#define HSMCI_SR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Position */ +#define HSMCI_SR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_SR_SDIOIRQA_Pos) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Mask */ +#define HSMCI_SR_SDIOIRQA(value) (HSMCI_SR_SDIOIRQA_Msk & ((value) << HSMCI_SR_SDIOIRQA_Pos)) +#define HSMCI_SR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_SR) SDIO Read Wait Operation Status Position */ +#define HSMCI_SR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_SR_SDIOWAIT_Pos) /**< (HSMCI_SR) SDIO Read Wait Operation Status Mask */ +#define HSMCI_SR_SDIOWAIT(value) (HSMCI_SR_SDIOWAIT_Msk & ((value) << HSMCI_SR_SDIOWAIT_Pos)) +#define HSMCI_SR_CSRCV_Pos _U_(13) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Position */ +#define HSMCI_SR_CSRCV_Msk (_U_(0x1) << HSMCI_SR_CSRCV_Pos) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Mask */ +#define HSMCI_SR_CSRCV(value) (HSMCI_SR_CSRCV_Msk & ((value) << HSMCI_SR_CSRCV_Pos)) +#define HSMCI_SR_RINDE_Pos _U_(16) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RINDE_Msk (_U_(0x1) << HSMCI_SR_RINDE_Pos) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RINDE(value) (HSMCI_SR_RINDE_Msk & ((value) << HSMCI_SR_RINDE_Pos)) +#define HSMCI_SR_RDIRE_Pos _U_(17) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RDIRE_Msk (_U_(0x1) << HSMCI_SR_RDIRE_Pos) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RDIRE(value) (HSMCI_SR_RDIRE_Msk & ((value) << HSMCI_SR_RDIRE_Pos)) +#define HSMCI_SR_RCRCE_Pos _U_(18) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RCRCE_Msk (_U_(0x1) << HSMCI_SR_RCRCE_Pos) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RCRCE(value) (HSMCI_SR_RCRCE_Msk & ((value) << HSMCI_SR_RCRCE_Pos)) +#define HSMCI_SR_RENDE_Pos _U_(19) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RENDE_Msk (_U_(0x1) << HSMCI_SR_RENDE_Pos) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RENDE(value) (HSMCI_SR_RENDE_Msk & ((value) << HSMCI_SR_RENDE_Pos)) +#define HSMCI_SR_RTOE_Pos _U_(20) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Position */ +#define HSMCI_SR_RTOE_Msk (_U_(0x1) << HSMCI_SR_RTOE_Pos) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Mask */ +#define HSMCI_SR_RTOE(value) (HSMCI_SR_RTOE_Msk & ((value) << HSMCI_SR_RTOE_Pos)) +#define HSMCI_SR_DCRCE_Pos _U_(21) /**< (HSMCI_SR) Data CRC Error (cleared on read) Position */ +#define HSMCI_SR_DCRCE_Msk (_U_(0x1) << HSMCI_SR_DCRCE_Pos) /**< (HSMCI_SR) Data CRC Error (cleared on read) Mask */ +#define HSMCI_SR_DCRCE(value) (HSMCI_SR_DCRCE_Msk & ((value) << HSMCI_SR_DCRCE_Pos)) +#define HSMCI_SR_DTOE_Pos _U_(22) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Position */ +#define HSMCI_SR_DTOE_Msk (_U_(0x1) << HSMCI_SR_DTOE_Pos) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_DTOE(value) (HSMCI_SR_DTOE_Msk & ((value) << HSMCI_SR_DTOE_Pos)) +#define HSMCI_SR_CSTOE_Pos _U_(23) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Position */ +#define HSMCI_SR_CSTOE_Msk (_U_(0x1) << HSMCI_SR_CSTOE_Pos) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Mask */ +#define HSMCI_SR_CSTOE(value) (HSMCI_SR_CSTOE_Msk & ((value) << HSMCI_SR_CSTOE_Pos)) +#define HSMCI_SR_BLKOVRE_Pos _U_(24) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Position */ +#define HSMCI_SR_BLKOVRE_Msk (_U_(0x1) << HSMCI_SR_BLKOVRE_Pos) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Mask */ +#define HSMCI_SR_BLKOVRE(value) (HSMCI_SR_BLKOVRE_Msk & ((value) << HSMCI_SR_BLKOVRE_Pos)) +#define HSMCI_SR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_SR) FIFO empty flag Position */ +#define HSMCI_SR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_SR_FIFOEMPTY_Pos) /**< (HSMCI_SR) FIFO empty flag Mask */ +#define HSMCI_SR_FIFOEMPTY(value) (HSMCI_SR_FIFOEMPTY_Msk & ((value) << HSMCI_SR_FIFOEMPTY_Pos)) +#define HSMCI_SR_XFRDONE_Pos _U_(27) /**< (HSMCI_SR) Transfer Done flag Position */ +#define HSMCI_SR_XFRDONE_Msk (_U_(0x1) << HSMCI_SR_XFRDONE_Pos) /**< (HSMCI_SR) Transfer Done flag Mask */ +#define HSMCI_SR_XFRDONE(value) (HSMCI_SR_XFRDONE_Msk & ((value) << HSMCI_SR_XFRDONE_Pos)) +#define HSMCI_SR_ACKRCV_Pos _U_(28) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Position */ +#define HSMCI_SR_ACKRCV_Msk (_U_(0x1) << HSMCI_SR_ACKRCV_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Mask */ +#define HSMCI_SR_ACKRCV(value) (HSMCI_SR_ACKRCV_Msk & ((value) << HSMCI_SR_ACKRCV_Pos)) +#define HSMCI_SR_ACKRCVE_Pos _U_(29) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Position */ +#define HSMCI_SR_ACKRCVE_Msk (_U_(0x1) << HSMCI_SR_ACKRCVE_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Mask */ +#define HSMCI_SR_ACKRCVE(value) (HSMCI_SR_ACKRCVE_Msk & ((value) << HSMCI_SR_ACKRCVE_Pos)) +#define HSMCI_SR_OVRE_Pos _U_(30) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_OVRE_Msk (_U_(0x1) << HSMCI_SR_OVRE_Pos) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_OVRE(value) (HSMCI_SR_OVRE_Msk & ((value) << HSMCI_SR_OVRE_Pos)) +#define HSMCI_SR_UNRE_Pos _U_(31) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ +#define HSMCI_SR_UNRE_Msk (_U_(0x1) << HSMCI_SR_UNRE_Pos) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ +#define HSMCI_SR_UNRE(value) (HSMCI_SR_UNRE_Msk & ((value) << HSMCI_SR_UNRE_Pos)) +#define HSMCI_SR_Msk _U_(0xFDFF313F) /**< (HSMCI_SR) Register Mask */ + + +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) ( /W 32) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY_Pos _U_(0) /**< (HSMCI_IER) Command Ready Interrupt Enable Position */ +#define HSMCI_IER_CMDRDY_Msk (_U_(0x1) << HSMCI_IER_CMDRDY_Pos) /**< (HSMCI_IER) Command Ready Interrupt Enable Mask */ +#define HSMCI_IER_CMDRDY(value) (HSMCI_IER_CMDRDY_Msk & ((value) << HSMCI_IER_CMDRDY_Pos)) +#define HSMCI_IER_RXRDY_Pos _U_(1) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Position */ +#define HSMCI_IER_RXRDY_Msk (_U_(0x1) << HSMCI_IER_RXRDY_Pos) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Mask */ +#define HSMCI_IER_RXRDY(value) (HSMCI_IER_RXRDY_Msk & ((value) << HSMCI_IER_RXRDY_Pos)) +#define HSMCI_IER_TXRDY_Pos _U_(2) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Position */ +#define HSMCI_IER_TXRDY_Msk (_U_(0x1) << HSMCI_IER_TXRDY_Pos) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Mask */ +#define HSMCI_IER_TXRDY(value) (HSMCI_IER_TXRDY_Msk & ((value) << HSMCI_IER_TXRDY_Pos)) +#define HSMCI_IER_BLKE_Pos _U_(3) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Position */ +#define HSMCI_IER_BLKE_Msk (_U_(0x1) << HSMCI_IER_BLKE_Pos) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Mask */ +#define HSMCI_IER_BLKE(value) (HSMCI_IER_BLKE_Msk & ((value) << HSMCI_IER_BLKE_Pos)) +#define HSMCI_IER_DTIP_Pos _U_(4) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Position */ +#define HSMCI_IER_DTIP_Msk (_U_(0x1) << HSMCI_IER_DTIP_Pos) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Mask */ +#define HSMCI_IER_DTIP(value) (HSMCI_IER_DTIP_Msk & ((value) << HSMCI_IER_DTIP_Pos)) +#define HSMCI_IER_NOTBUSY_Pos _U_(5) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Position */ +#define HSMCI_IER_NOTBUSY_Msk (_U_(0x1) << HSMCI_IER_NOTBUSY_Pos) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Mask */ +#define HSMCI_IER_NOTBUSY(value) (HSMCI_IER_NOTBUSY_Msk & ((value) << HSMCI_IER_NOTBUSY_Pos)) +#define HSMCI_IER_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Position */ +#define HSMCI_IER_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IER_SDIOIRQA_Pos) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Mask */ +#define HSMCI_IER_SDIOIRQA(value) (HSMCI_IER_SDIOIRQA_Msk & ((value) << HSMCI_IER_SDIOIRQA_Pos)) +#define HSMCI_IER_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Position */ +#define HSMCI_IER_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IER_SDIOWAIT_Pos) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Mask */ +#define HSMCI_IER_SDIOWAIT(value) (HSMCI_IER_SDIOWAIT_Msk & ((value) << HSMCI_IER_SDIOWAIT_Pos)) +#define HSMCI_IER_CSRCV_Pos _U_(13) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Position */ +#define HSMCI_IER_CSRCV_Msk (_U_(0x1) << HSMCI_IER_CSRCV_Pos) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Mask */ +#define HSMCI_IER_CSRCV(value) (HSMCI_IER_CSRCV_Msk & ((value) << HSMCI_IER_CSRCV_Pos)) +#define HSMCI_IER_RINDE_Pos _U_(16) /**< (HSMCI_IER) Response Index Error Interrupt Enable Position */ +#define HSMCI_IER_RINDE_Msk (_U_(0x1) << HSMCI_IER_RINDE_Pos) /**< (HSMCI_IER) Response Index Error Interrupt Enable Mask */ +#define HSMCI_IER_RINDE(value) (HSMCI_IER_RINDE_Msk & ((value) << HSMCI_IER_RINDE_Pos)) +#define HSMCI_IER_RDIRE_Pos _U_(17) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Position */ +#define HSMCI_IER_RDIRE_Msk (_U_(0x1) << HSMCI_IER_RDIRE_Pos) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Mask */ +#define HSMCI_IER_RDIRE(value) (HSMCI_IER_RDIRE_Msk & ((value) << HSMCI_IER_RDIRE_Pos)) +#define HSMCI_IER_RCRCE_Pos _U_(18) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Position */ +#define HSMCI_IER_RCRCE_Msk (_U_(0x1) << HSMCI_IER_RCRCE_Pos) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_RCRCE(value) (HSMCI_IER_RCRCE_Msk & ((value) << HSMCI_IER_RCRCE_Pos)) +#define HSMCI_IER_RENDE_Pos _U_(19) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Position */ +#define HSMCI_IER_RENDE_Msk (_U_(0x1) << HSMCI_IER_RENDE_Pos) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Mask */ +#define HSMCI_IER_RENDE(value) (HSMCI_IER_RENDE_Msk & ((value) << HSMCI_IER_RENDE_Pos)) +#define HSMCI_IER_RTOE_Pos _U_(20) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_RTOE_Msk (_U_(0x1) << HSMCI_IER_RTOE_Pos) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_RTOE(value) (HSMCI_IER_RTOE_Msk & ((value) << HSMCI_IER_RTOE_Pos)) +#define HSMCI_IER_DCRCE_Pos _U_(21) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Position */ +#define HSMCI_IER_DCRCE_Msk (_U_(0x1) << HSMCI_IER_DCRCE_Pos) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Mask */ +#define HSMCI_IER_DCRCE(value) (HSMCI_IER_DCRCE_Msk & ((value) << HSMCI_IER_DCRCE_Pos)) +#define HSMCI_IER_DTOE_Pos _U_(22) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Position */ +#define HSMCI_IER_DTOE_Msk (_U_(0x1) << HSMCI_IER_DTOE_Pos) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Mask */ +#define HSMCI_IER_DTOE(value) (HSMCI_IER_DTOE_Msk & ((value) << HSMCI_IER_DTOE_Pos)) +#define HSMCI_IER_CSTOE_Pos _U_(23) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Position */ +#define HSMCI_IER_CSTOE_Msk (_U_(0x1) << HSMCI_IER_CSTOE_Pos) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Mask */ +#define HSMCI_IER_CSTOE(value) (HSMCI_IER_CSTOE_Msk & ((value) << HSMCI_IER_CSTOE_Pos)) +#define HSMCI_IER_BLKOVRE_Pos _U_(24) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Position */ +#define HSMCI_IER_BLKOVRE_Msk (_U_(0x1) << HSMCI_IER_BLKOVRE_Pos) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Mask */ +#define HSMCI_IER_BLKOVRE(value) (HSMCI_IER_BLKOVRE_Msk & ((value) << HSMCI_IER_BLKOVRE_Pos)) +#define HSMCI_IER_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IER) FIFO empty Interrupt enable Position */ +#define HSMCI_IER_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IER_FIFOEMPTY_Pos) /**< (HSMCI_IER) FIFO empty Interrupt enable Mask */ +#define HSMCI_IER_FIFOEMPTY(value) (HSMCI_IER_FIFOEMPTY_Msk & ((value) << HSMCI_IER_FIFOEMPTY_Pos)) +#define HSMCI_IER_XFRDONE_Pos _U_(27) /**< (HSMCI_IER) Transfer Done Interrupt enable Position */ +#define HSMCI_IER_XFRDONE_Msk (_U_(0x1) << HSMCI_IER_XFRDONE_Pos) /**< (HSMCI_IER) Transfer Done Interrupt enable Mask */ +#define HSMCI_IER_XFRDONE(value) (HSMCI_IER_XFRDONE_Msk & ((value) << HSMCI_IER_XFRDONE_Pos)) +#define HSMCI_IER_ACKRCV_Pos _U_(28) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Position */ +#define HSMCI_IER_ACKRCV_Msk (_U_(0x1) << HSMCI_IER_ACKRCV_Pos) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCV(value) (HSMCI_IER_ACKRCV_Msk & ((value) << HSMCI_IER_ACKRCV_Pos)) +#define HSMCI_IER_ACKRCVE_Pos _U_(29) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Position */ +#define HSMCI_IER_ACKRCVE_Msk (_U_(0x1) << HSMCI_IER_ACKRCVE_Pos) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Mask */ +#define HSMCI_IER_ACKRCVE(value) (HSMCI_IER_ACKRCVE_Msk & ((value) << HSMCI_IER_ACKRCVE_Pos)) +#define HSMCI_IER_OVRE_Pos _U_(30) /**< (HSMCI_IER) Overrun Interrupt Enable Position */ +#define HSMCI_IER_OVRE_Msk (_U_(0x1) << HSMCI_IER_OVRE_Pos) /**< (HSMCI_IER) Overrun Interrupt Enable Mask */ +#define HSMCI_IER_OVRE(value) (HSMCI_IER_OVRE_Msk & ((value) << HSMCI_IER_OVRE_Pos)) +#define HSMCI_IER_UNRE_Pos _U_(31) /**< (HSMCI_IER) Underrun Interrupt Enable Position */ +#define HSMCI_IER_UNRE_Msk (_U_(0x1) << HSMCI_IER_UNRE_Pos) /**< (HSMCI_IER) Underrun Interrupt Enable Mask */ +#define HSMCI_IER_UNRE(value) (HSMCI_IER_UNRE_Msk & ((value) << HSMCI_IER_UNRE_Pos)) +#define HSMCI_IER_Msk _U_(0xFDFF313F) /**< (HSMCI_IER) Register Mask */ + + +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) ( /W 32) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY_Pos _U_(0) /**< (HSMCI_IDR) Command Ready Interrupt Disable Position */ +#define HSMCI_IDR_CMDRDY_Msk (_U_(0x1) << HSMCI_IDR_CMDRDY_Pos) /**< (HSMCI_IDR) Command Ready Interrupt Disable Mask */ +#define HSMCI_IDR_CMDRDY(value) (HSMCI_IDR_CMDRDY_Msk & ((value) << HSMCI_IDR_CMDRDY_Pos)) +#define HSMCI_IDR_RXRDY_Pos _U_(1) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Position */ +#define HSMCI_IDR_RXRDY_Msk (_U_(0x1) << HSMCI_IDR_RXRDY_Pos) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Mask */ +#define HSMCI_IDR_RXRDY(value) (HSMCI_IDR_RXRDY_Msk & ((value) << HSMCI_IDR_RXRDY_Pos)) +#define HSMCI_IDR_TXRDY_Pos _U_(2) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Position */ +#define HSMCI_IDR_TXRDY_Msk (_U_(0x1) << HSMCI_IDR_TXRDY_Pos) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Mask */ +#define HSMCI_IDR_TXRDY(value) (HSMCI_IDR_TXRDY_Msk & ((value) << HSMCI_IDR_TXRDY_Pos)) +#define HSMCI_IDR_BLKE_Pos _U_(3) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Position */ +#define HSMCI_IDR_BLKE_Msk (_U_(0x1) << HSMCI_IDR_BLKE_Pos) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Mask */ +#define HSMCI_IDR_BLKE(value) (HSMCI_IDR_BLKE_Msk & ((value) << HSMCI_IDR_BLKE_Pos)) +#define HSMCI_IDR_DTIP_Pos _U_(4) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Position */ +#define HSMCI_IDR_DTIP_Msk (_U_(0x1) << HSMCI_IDR_DTIP_Pos) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Mask */ +#define HSMCI_IDR_DTIP(value) (HSMCI_IDR_DTIP_Msk & ((value) << HSMCI_IDR_DTIP_Pos)) +#define HSMCI_IDR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Position */ +#define HSMCI_IDR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IDR_NOTBUSY_Pos) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Mask */ +#define HSMCI_IDR_NOTBUSY(value) (HSMCI_IDR_NOTBUSY_Msk & ((value) << HSMCI_IDR_NOTBUSY_Pos)) +#define HSMCI_IDR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Position */ +#define HSMCI_IDR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IDR_SDIOIRQA_Pos) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOIRQA(value) (HSMCI_IDR_SDIOIRQA_Msk & ((value) << HSMCI_IDR_SDIOIRQA_Pos)) +#define HSMCI_IDR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Position */ +#define HSMCI_IDR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IDR_SDIOWAIT_Pos) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Mask */ +#define HSMCI_IDR_SDIOWAIT(value) (HSMCI_IDR_SDIOWAIT_Msk & ((value) << HSMCI_IDR_SDIOWAIT_Pos)) +#define HSMCI_IDR_CSRCV_Pos _U_(13) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Position */ +#define HSMCI_IDR_CSRCV_Msk (_U_(0x1) << HSMCI_IDR_CSRCV_Pos) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Mask */ +#define HSMCI_IDR_CSRCV(value) (HSMCI_IDR_CSRCV_Msk & ((value) << HSMCI_IDR_CSRCV_Pos)) +#define HSMCI_IDR_RINDE_Pos _U_(16) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Position */ +#define HSMCI_IDR_RINDE_Msk (_U_(0x1) << HSMCI_IDR_RINDE_Pos) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Mask */ +#define HSMCI_IDR_RINDE(value) (HSMCI_IDR_RINDE_Msk & ((value) << HSMCI_IDR_RINDE_Pos)) +#define HSMCI_IDR_RDIRE_Pos _U_(17) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Position */ +#define HSMCI_IDR_RDIRE_Msk (_U_(0x1) << HSMCI_IDR_RDIRE_Pos) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Mask */ +#define HSMCI_IDR_RDIRE(value) (HSMCI_IDR_RDIRE_Msk & ((value) << HSMCI_IDR_RDIRE_Pos)) +#define HSMCI_IDR_RCRCE_Pos _U_(18) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_RCRCE_Msk (_U_(0x1) << HSMCI_IDR_RCRCE_Pos) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_RCRCE(value) (HSMCI_IDR_RCRCE_Msk & ((value) << HSMCI_IDR_RCRCE_Pos)) +#define HSMCI_IDR_RENDE_Pos _U_(19) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Position */ +#define HSMCI_IDR_RENDE_Msk (_U_(0x1) << HSMCI_IDR_RENDE_Pos) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Mask */ +#define HSMCI_IDR_RENDE(value) (HSMCI_IDR_RENDE_Msk & ((value) << HSMCI_IDR_RENDE_Pos)) +#define HSMCI_IDR_RTOE_Pos _U_(20) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_RTOE_Msk (_U_(0x1) << HSMCI_IDR_RTOE_Pos) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_RTOE(value) (HSMCI_IDR_RTOE_Msk & ((value) << HSMCI_IDR_RTOE_Pos)) +#define HSMCI_IDR_DCRCE_Pos _U_(21) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Position */ +#define HSMCI_IDR_DCRCE_Msk (_U_(0x1) << HSMCI_IDR_DCRCE_Pos) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Mask */ +#define HSMCI_IDR_DCRCE(value) (HSMCI_IDR_DCRCE_Msk & ((value) << HSMCI_IDR_DCRCE_Pos)) +#define HSMCI_IDR_DTOE_Pos _U_(22) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Position */ +#define HSMCI_IDR_DTOE_Msk (_U_(0x1) << HSMCI_IDR_DTOE_Pos) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Mask */ +#define HSMCI_IDR_DTOE(value) (HSMCI_IDR_DTOE_Msk & ((value) << HSMCI_IDR_DTOE_Pos)) +#define HSMCI_IDR_CSTOE_Pos _U_(23) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Position */ +#define HSMCI_IDR_CSTOE_Msk (_U_(0x1) << HSMCI_IDR_CSTOE_Pos) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Mask */ +#define HSMCI_IDR_CSTOE(value) (HSMCI_IDR_CSTOE_Msk & ((value) << HSMCI_IDR_CSTOE_Pos)) +#define HSMCI_IDR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Position */ +#define HSMCI_IDR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IDR_BLKOVRE_Pos) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Mask */ +#define HSMCI_IDR_BLKOVRE(value) (HSMCI_IDR_BLKOVRE_Msk & ((value) << HSMCI_IDR_BLKOVRE_Pos)) +#define HSMCI_IDR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Position */ +#define HSMCI_IDR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IDR_FIFOEMPTY_Pos) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Mask */ +#define HSMCI_IDR_FIFOEMPTY(value) (HSMCI_IDR_FIFOEMPTY_Msk & ((value) << HSMCI_IDR_FIFOEMPTY_Pos)) +#define HSMCI_IDR_XFRDONE_Pos _U_(27) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Position */ +#define HSMCI_IDR_XFRDONE_Msk (_U_(0x1) << HSMCI_IDR_XFRDONE_Pos) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Mask */ +#define HSMCI_IDR_XFRDONE(value) (HSMCI_IDR_XFRDONE_Msk & ((value) << HSMCI_IDR_XFRDONE_Pos)) +#define HSMCI_IDR_ACKRCV_Pos _U_(28) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCV_Msk (_U_(0x1) << HSMCI_IDR_ACKRCV_Pos) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCV(value) (HSMCI_IDR_ACKRCV_Msk & ((value) << HSMCI_IDR_ACKRCV_Pos)) +#define HSMCI_IDR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Position */ +#define HSMCI_IDR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IDR_ACKRCVE_Pos) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Mask */ +#define HSMCI_IDR_ACKRCVE(value) (HSMCI_IDR_ACKRCVE_Msk & ((value) << HSMCI_IDR_ACKRCVE_Pos)) +#define HSMCI_IDR_OVRE_Pos _U_(30) /**< (HSMCI_IDR) Overrun Interrupt Disable Position */ +#define HSMCI_IDR_OVRE_Msk (_U_(0x1) << HSMCI_IDR_OVRE_Pos) /**< (HSMCI_IDR) Overrun Interrupt Disable Mask */ +#define HSMCI_IDR_OVRE(value) (HSMCI_IDR_OVRE_Msk & ((value) << HSMCI_IDR_OVRE_Pos)) +#define HSMCI_IDR_UNRE_Pos _U_(31) /**< (HSMCI_IDR) Underrun Interrupt Disable Position */ +#define HSMCI_IDR_UNRE_Msk (_U_(0x1) << HSMCI_IDR_UNRE_Pos) /**< (HSMCI_IDR) Underrun Interrupt Disable Mask */ +#define HSMCI_IDR_UNRE(value) (HSMCI_IDR_UNRE_Msk & ((value) << HSMCI_IDR_UNRE_Pos)) +#define HSMCI_IDR_Msk _U_(0xFDFF313F) /**< (HSMCI_IDR) Register Mask */ + + +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) ( R/ 32) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY_Pos _U_(0) /**< (HSMCI_IMR) Command Ready Interrupt Mask Position */ +#define HSMCI_IMR_CMDRDY_Msk (_U_(0x1) << HSMCI_IMR_CMDRDY_Pos) /**< (HSMCI_IMR) Command Ready Interrupt Mask Mask */ +#define HSMCI_IMR_CMDRDY(value) (HSMCI_IMR_CMDRDY_Msk & ((value) << HSMCI_IMR_CMDRDY_Pos)) +#define HSMCI_IMR_RXRDY_Pos _U_(1) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Position */ +#define HSMCI_IMR_RXRDY_Msk (_U_(0x1) << HSMCI_IMR_RXRDY_Pos) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Mask */ +#define HSMCI_IMR_RXRDY(value) (HSMCI_IMR_RXRDY_Msk & ((value) << HSMCI_IMR_RXRDY_Pos)) +#define HSMCI_IMR_TXRDY_Pos _U_(2) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Position */ +#define HSMCI_IMR_TXRDY_Msk (_U_(0x1) << HSMCI_IMR_TXRDY_Pos) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Mask */ +#define HSMCI_IMR_TXRDY(value) (HSMCI_IMR_TXRDY_Msk & ((value) << HSMCI_IMR_TXRDY_Pos)) +#define HSMCI_IMR_BLKE_Pos _U_(3) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Position */ +#define HSMCI_IMR_BLKE_Msk (_U_(0x1) << HSMCI_IMR_BLKE_Pos) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Mask */ +#define HSMCI_IMR_BLKE(value) (HSMCI_IMR_BLKE_Msk & ((value) << HSMCI_IMR_BLKE_Pos)) +#define HSMCI_IMR_DTIP_Pos _U_(4) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Position */ +#define HSMCI_IMR_DTIP_Msk (_U_(0x1) << HSMCI_IMR_DTIP_Pos) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Mask */ +#define HSMCI_IMR_DTIP(value) (HSMCI_IMR_DTIP_Msk & ((value) << HSMCI_IMR_DTIP_Pos)) +#define HSMCI_IMR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Position */ +#define HSMCI_IMR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IMR_NOTBUSY_Pos) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Mask */ +#define HSMCI_IMR_NOTBUSY(value) (HSMCI_IMR_NOTBUSY_Msk & ((value) << HSMCI_IMR_NOTBUSY_Pos)) +#define HSMCI_IMR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Position */ +#define HSMCI_IMR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IMR_SDIOIRQA_Pos) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOIRQA(value) (HSMCI_IMR_SDIOIRQA_Msk & ((value) << HSMCI_IMR_SDIOIRQA_Pos)) +#define HSMCI_IMR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Position */ +#define HSMCI_IMR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IMR_SDIOWAIT_Pos) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Mask */ +#define HSMCI_IMR_SDIOWAIT(value) (HSMCI_IMR_SDIOWAIT_Msk & ((value) << HSMCI_IMR_SDIOWAIT_Pos)) +#define HSMCI_IMR_CSRCV_Pos _U_(13) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Position */ +#define HSMCI_IMR_CSRCV_Msk (_U_(0x1) << HSMCI_IMR_CSRCV_Pos) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Mask */ +#define HSMCI_IMR_CSRCV(value) (HSMCI_IMR_CSRCV_Msk & ((value) << HSMCI_IMR_CSRCV_Pos)) +#define HSMCI_IMR_RINDE_Pos _U_(16) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Position */ +#define HSMCI_IMR_RINDE_Msk (_U_(0x1) << HSMCI_IMR_RINDE_Pos) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Mask */ +#define HSMCI_IMR_RINDE(value) (HSMCI_IMR_RINDE_Msk & ((value) << HSMCI_IMR_RINDE_Pos)) +#define HSMCI_IMR_RDIRE_Pos _U_(17) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Position */ +#define HSMCI_IMR_RDIRE_Msk (_U_(0x1) << HSMCI_IMR_RDIRE_Pos) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Mask */ +#define HSMCI_IMR_RDIRE(value) (HSMCI_IMR_RDIRE_Msk & ((value) << HSMCI_IMR_RDIRE_Pos)) +#define HSMCI_IMR_RCRCE_Pos _U_(18) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_RCRCE_Msk (_U_(0x1) << HSMCI_IMR_RCRCE_Pos) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_RCRCE(value) (HSMCI_IMR_RCRCE_Msk & ((value) << HSMCI_IMR_RCRCE_Pos)) +#define HSMCI_IMR_RENDE_Pos _U_(19) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Position */ +#define HSMCI_IMR_RENDE_Msk (_U_(0x1) << HSMCI_IMR_RENDE_Pos) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Mask */ +#define HSMCI_IMR_RENDE(value) (HSMCI_IMR_RENDE_Msk & ((value) << HSMCI_IMR_RENDE_Pos)) +#define HSMCI_IMR_RTOE_Pos _U_(20) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_RTOE_Msk (_U_(0x1) << HSMCI_IMR_RTOE_Pos) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_RTOE(value) (HSMCI_IMR_RTOE_Msk & ((value) << HSMCI_IMR_RTOE_Pos)) +#define HSMCI_IMR_DCRCE_Pos _U_(21) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Position */ +#define HSMCI_IMR_DCRCE_Msk (_U_(0x1) << HSMCI_IMR_DCRCE_Pos) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Mask */ +#define HSMCI_IMR_DCRCE(value) (HSMCI_IMR_DCRCE_Msk & ((value) << HSMCI_IMR_DCRCE_Pos)) +#define HSMCI_IMR_DTOE_Pos _U_(22) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_DTOE_Msk (_U_(0x1) << HSMCI_IMR_DTOE_Pos) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_DTOE(value) (HSMCI_IMR_DTOE_Msk & ((value) << HSMCI_IMR_DTOE_Pos)) +#define HSMCI_IMR_CSTOE_Pos _U_(23) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Position */ +#define HSMCI_IMR_CSTOE_Msk (_U_(0x1) << HSMCI_IMR_CSTOE_Pos) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Mask */ +#define HSMCI_IMR_CSTOE(value) (HSMCI_IMR_CSTOE_Msk & ((value) << HSMCI_IMR_CSTOE_Pos)) +#define HSMCI_IMR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Position */ +#define HSMCI_IMR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IMR_BLKOVRE_Pos) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Mask */ +#define HSMCI_IMR_BLKOVRE(value) (HSMCI_IMR_BLKOVRE_Msk & ((value) << HSMCI_IMR_BLKOVRE_Pos)) +#define HSMCI_IMR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Position */ +#define HSMCI_IMR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IMR_FIFOEMPTY_Pos) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Mask */ +#define HSMCI_IMR_FIFOEMPTY(value) (HSMCI_IMR_FIFOEMPTY_Msk & ((value) << HSMCI_IMR_FIFOEMPTY_Pos)) +#define HSMCI_IMR_XFRDONE_Pos _U_(27) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Position */ +#define HSMCI_IMR_XFRDONE_Msk (_U_(0x1) << HSMCI_IMR_XFRDONE_Pos) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Mask */ +#define HSMCI_IMR_XFRDONE(value) (HSMCI_IMR_XFRDONE_Msk & ((value) << HSMCI_IMR_XFRDONE_Pos)) +#define HSMCI_IMR_ACKRCV_Pos _U_(28) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCV_Msk (_U_(0x1) << HSMCI_IMR_ACKRCV_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCV(value) (HSMCI_IMR_ACKRCV_Msk & ((value) << HSMCI_IMR_ACKRCV_Pos)) +#define HSMCI_IMR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Position */ +#define HSMCI_IMR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IMR_ACKRCVE_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Mask */ +#define HSMCI_IMR_ACKRCVE(value) (HSMCI_IMR_ACKRCVE_Msk & ((value) << HSMCI_IMR_ACKRCVE_Pos)) +#define HSMCI_IMR_OVRE_Pos _U_(30) /**< (HSMCI_IMR) Overrun Interrupt Mask Position */ +#define HSMCI_IMR_OVRE_Msk (_U_(0x1) << HSMCI_IMR_OVRE_Pos) /**< (HSMCI_IMR) Overrun Interrupt Mask Mask */ +#define HSMCI_IMR_OVRE(value) (HSMCI_IMR_OVRE_Msk & ((value) << HSMCI_IMR_OVRE_Pos)) +#define HSMCI_IMR_UNRE_Pos _U_(31) /**< (HSMCI_IMR) Underrun Interrupt Mask Position */ +#define HSMCI_IMR_UNRE_Msk (_U_(0x1) << HSMCI_IMR_UNRE_Pos) /**< (HSMCI_IMR) Underrun Interrupt Mask Mask */ +#define HSMCI_IMR_UNRE(value) (HSMCI_IMR_UNRE_Msk & ((value) << HSMCI_IMR_UNRE_Pos)) +#define HSMCI_IMR_Msk _U_(0xFDFF313F) /**< (HSMCI_IMR) Register Mask */ + + +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) (R/W 32) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos _U_(4) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Position */ +#define HSMCI_DMA_CHKSIZE_Msk (_U_(0x7) << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Mask */ +#define HSMCI_DMA_CHKSIZE(value) (HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)) +#define HSMCI_DMA_CHKSIZE_1_Val _U_(0x0) /**< (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2_Val _U_(0x1) /**< (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4_Val _U_(0x2) /**< (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8_Val _U_(0x3) /**< (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16_Val _U_(0x4) /**< (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_CHKSIZE_1 (HSMCI_DMA_CHKSIZE_1_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 1 data available Position */ +#define HSMCI_DMA_CHKSIZE_2 (HSMCI_DMA_CHKSIZE_2_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 2 data available Position */ +#define HSMCI_DMA_CHKSIZE_4 (HSMCI_DMA_CHKSIZE_4_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 4 data available Position */ +#define HSMCI_DMA_CHKSIZE_8 (HSMCI_DMA_CHKSIZE_8_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 8 data available Position */ +#define HSMCI_DMA_CHKSIZE_16 (HSMCI_DMA_CHKSIZE_16_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 16 data available Position */ +#define HSMCI_DMA_DMAEN_Pos _U_(8) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Position */ +#define HSMCI_DMA_DMAEN_Msk (_U_(0x1) << HSMCI_DMA_DMAEN_Pos) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Mask */ +#define HSMCI_DMA_DMAEN(value) (HSMCI_DMA_DMAEN_Msk & ((value) << HSMCI_DMA_DMAEN_Pos)) +#define HSMCI_DMA_Msk _U_(0x00000170) /**< (HSMCI_DMA) Register Mask */ + + +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) (R/W 32) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE_Pos _U_(0) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Position */ +#define HSMCI_CFG_FIFOMODE_Msk (_U_(0x1) << HSMCI_CFG_FIFOMODE_Pos) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Mask */ +#define HSMCI_CFG_FIFOMODE(value) (HSMCI_CFG_FIFOMODE_Msk & ((value) << HSMCI_CFG_FIFOMODE_Pos)) +#define HSMCI_CFG_FERRCTRL_Pos _U_(4) /**< (HSMCI_CFG) Flow Error flag reset control mode Position */ +#define HSMCI_CFG_FERRCTRL_Msk (_U_(0x1) << HSMCI_CFG_FERRCTRL_Pos) /**< (HSMCI_CFG) Flow Error flag reset control mode Mask */ +#define HSMCI_CFG_FERRCTRL(value) (HSMCI_CFG_FERRCTRL_Msk & ((value) << HSMCI_CFG_FERRCTRL_Pos)) +#define HSMCI_CFG_HSMODE_Pos _U_(8) /**< (HSMCI_CFG) High Speed Mode Position */ +#define HSMCI_CFG_HSMODE_Msk (_U_(0x1) << HSMCI_CFG_HSMODE_Pos) /**< (HSMCI_CFG) High Speed Mode Mask */ +#define HSMCI_CFG_HSMODE(value) (HSMCI_CFG_HSMODE_Msk & ((value) << HSMCI_CFG_HSMODE_Pos)) +#define HSMCI_CFG_LSYNC_Pos _U_(12) /**< (HSMCI_CFG) Synchronize on the last block Position */ +#define HSMCI_CFG_LSYNC_Msk (_U_(0x1) << HSMCI_CFG_LSYNC_Pos) /**< (HSMCI_CFG) Synchronize on the last block Mask */ +#define HSMCI_CFG_LSYNC(value) (HSMCI_CFG_LSYNC_Msk & ((value) << HSMCI_CFG_LSYNC_Pos)) +#define HSMCI_CFG_Msk _U_(0x00001111) /**< (HSMCI_CFG) Register Mask */ + + +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN_Pos _U_(0) /**< (HSMCI_WPMR) Write Protect Enable Position */ +#define HSMCI_WPMR_WPEN_Msk (_U_(0x1) << HSMCI_WPMR_WPEN_Pos) /**< (HSMCI_WPMR) Write Protect Enable Mask */ +#define HSMCI_WPMR_WPEN(value) (HSMCI_WPMR_WPEN_Msk & ((value) << HSMCI_WPMR_WPEN_Pos)) +#define HSMCI_WPMR_WPKEY_Pos _U_(8) /**< (HSMCI_WPMR) Write Protect Key Position */ +#define HSMCI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Write Protect Key Mask */ +#define HSMCI_WPMR_WPKEY(value) (HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)) +#define HSMCI_WPMR_WPKEY_PASSWD_Val _U_(0x4D4349) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define HSMCI_WPMR_WPKEY_PASSWD (HSMCI_WPMR_WPKEY_PASSWD_Val << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define HSMCI_WPMR_Msk _U_(0xFFFFFF01) /**< (HSMCI_WPMR) Register Mask */ + + +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS_Pos _U_(0) /**< (HSMCI_WPSR) Write Protection Violation Status Position */ +#define HSMCI_WPSR_WPVS_Msk (_U_(0x1) << HSMCI_WPSR_WPVS_Pos) /**< (HSMCI_WPSR) Write Protection Violation Status Mask */ +#define HSMCI_WPSR_WPVS(value) (HSMCI_WPSR_WPVS_Msk & ((value) << HSMCI_WPSR_WPVS_Pos)) +#define HSMCI_WPSR_WPVSRC_Pos _U_(8) /**< (HSMCI_WPSR) Write Protection Violation Source Position */ +#define HSMCI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << HSMCI_WPSR_WPVSRC_Pos) /**< (HSMCI_WPSR) Write Protection Violation Source Mask */ +#define HSMCI_WPSR_WPVSRC(value) (HSMCI_WPSR_WPVSRC_Msk & ((value) << HSMCI_WPSR_WPVSRC_Pos)) +#define HSMCI_WPSR_Msk _U_(0x00FFFF01) /**< (HSMCI_WPSR) Register Mask */ + + +/* -------- HSMCI_FIFO : (HSMCI Offset: 0x200) (R/W 32) FIFO Memory Aperture0 0 -------- */ +#define HSMCI_FIFO_DATA_Pos _U_(0) /**< (HSMCI_FIFO) Data to Read or Data to Write Position */ +#define HSMCI_FIFO_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_FIFO_DATA_Pos) /**< (HSMCI_FIFO) Data to Read or Data to Write Mask */ +#define HSMCI_FIFO_DATA(value) (HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)) +#define HSMCI_FIFO_Msk _U_(0xFFFFFFFF) /**< (HSMCI_FIFO) Register Mask */ + + +/** \brief HSMCI register offsets definitions */ +#define HSMCI_CR_REG_OFST (0x00) /**< (HSMCI_CR) Control Register Offset */ +#define HSMCI_MR_REG_OFST (0x04) /**< (HSMCI_MR) Mode Register Offset */ +#define HSMCI_DTOR_REG_OFST (0x08) /**< (HSMCI_DTOR) Data Timeout Register Offset */ +#define HSMCI_SDCR_REG_OFST (0x0C) /**< (HSMCI_SDCR) SD/SDIO Card Register Offset */ +#define HSMCI_ARGR_REG_OFST (0x10) /**< (HSMCI_ARGR) Argument Register Offset */ +#define HSMCI_CMDR_REG_OFST (0x14) /**< (HSMCI_CMDR) Command Register Offset */ +#define HSMCI_BLKR_REG_OFST (0x18) /**< (HSMCI_BLKR) Block Register Offset */ +#define HSMCI_CSTOR_REG_OFST (0x1C) /**< (HSMCI_CSTOR) Completion Signal Timeout Register Offset */ +#define HSMCI_RSPR_REG_OFST (0x20) /**< (HSMCI_RSPR) Response Register 0 Offset */ +#define HSMCI_RDR_REG_OFST (0x30) /**< (HSMCI_RDR) Receive Data Register Offset */ +#define HSMCI_TDR_REG_OFST (0x34) /**< (HSMCI_TDR) Transmit Data Register Offset */ +#define HSMCI_SR_REG_OFST (0x40) /**< (HSMCI_SR) Status Register Offset */ +#define HSMCI_IER_REG_OFST (0x44) /**< (HSMCI_IER) Interrupt Enable Register Offset */ +#define HSMCI_IDR_REG_OFST (0x48) /**< (HSMCI_IDR) Interrupt Disable Register Offset */ +#define HSMCI_IMR_REG_OFST (0x4C) /**< (HSMCI_IMR) Interrupt Mask Register Offset */ +#define HSMCI_DMA_REG_OFST (0x50) /**< (HSMCI_DMA) DMA Configuration Register Offset */ +#define HSMCI_CFG_REG_OFST (0x54) /**< (HSMCI_CFG) Configuration Register Offset */ +#define HSMCI_WPMR_REG_OFST (0xE4) /**< (HSMCI_WPMR) Write Protection Mode Register Offset */ +#define HSMCI_WPSR_REG_OFST (0xE8) /**< (HSMCI_WPSR) Write Protection Status Register Offset */ +#define HSMCI_FIFO_REG_OFST (0x200) /**< (HSMCI_FIFO) FIFO Memory Aperture0 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief HSMCI register API structure */ +typedef struct +{ + __O uint32_t HSMCI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t HSMCI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< Offset: 0x08 (R/W 32) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< Offset: 0x0C (R/W 32) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< Offset: 0x10 (R/W 32) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< Offset: 0x14 ( /W 32) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< Offset: 0x18 (R/W 32) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< Offset: 0x1C (R/W 32) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< Offset: 0x20 (R/ 32) Response Register 0 */ + __I uint32_t HSMCI_RDR; /**< Offset: 0x30 (R/ 32) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< Offset: 0x34 ( /W 32) Transmit Data Register */ + __I uint8_t Reserved1[0x08]; + __I uint32_t HSMCI_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O uint32_t HSMCI_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< Offset: 0x50 (R/W 32) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< Offset: 0x54 (R/W 32) Configuration Register */ + __I uint8_t Reserved2[0x8C]; + __IO uint32_t HSMCI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved3[0x114]; + __IO uint32_t HSMCI_FIFO[256]; /**< Offset: 0x200 (R/W 32) FIFO Memory Aperture0 0 */ +} hsmci_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_HSMCI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/i2sc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/i2sc.h new file mode 100644 index 00000000..adfab28d --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/i2sc.h @@ -0,0 +1,292 @@ +/** + * \brief Component description for I2SC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_I2SC_COMPONENT_H_ +#define _SAME70_I2SC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR I2SC */ +/* ************************************************************************** */ + +/* -------- I2SC_CR : (I2SC Offset: 0x00) ( /W 32) Control Register -------- */ +#define I2SC_CR_RXEN_Pos _U_(0) /**< (I2SC_CR) Receiver Enable Position */ +#define I2SC_CR_RXEN_Msk (_U_(0x1) << I2SC_CR_RXEN_Pos) /**< (I2SC_CR) Receiver Enable Mask */ +#define I2SC_CR_RXEN(value) (I2SC_CR_RXEN_Msk & ((value) << I2SC_CR_RXEN_Pos)) +#define I2SC_CR_RXDIS_Pos _U_(1) /**< (I2SC_CR) Receiver Disable Position */ +#define I2SC_CR_RXDIS_Msk (_U_(0x1) << I2SC_CR_RXDIS_Pos) /**< (I2SC_CR) Receiver Disable Mask */ +#define I2SC_CR_RXDIS(value) (I2SC_CR_RXDIS_Msk & ((value) << I2SC_CR_RXDIS_Pos)) +#define I2SC_CR_CKEN_Pos _U_(2) /**< (I2SC_CR) Clocks Enable Position */ +#define I2SC_CR_CKEN_Msk (_U_(0x1) << I2SC_CR_CKEN_Pos) /**< (I2SC_CR) Clocks Enable Mask */ +#define I2SC_CR_CKEN(value) (I2SC_CR_CKEN_Msk & ((value) << I2SC_CR_CKEN_Pos)) +#define I2SC_CR_CKDIS_Pos _U_(3) /**< (I2SC_CR) Clocks Disable Position */ +#define I2SC_CR_CKDIS_Msk (_U_(0x1) << I2SC_CR_CKDIS_Pos) /**< (I2SC_CR) Clocks Disable Mask */ +#define I2SC_CR_CKDIS(value) (I2SC_CR_CKDIS_Msk & ((value) << I2SC_CR_CKDIS_Pos)) +#define I2SC_CR_TXEN_Pos _U_(4) /**< (I2SC_CR) Transmitter Enable Position */ +#define I2SC_CR_TXEN_Msk (_U_(0x1) << I2SC_CR_TXEN_Pos) /**< (I2SC_CR) Transmitter Enable Mask */ +#define I2SC_CR_TXEN(value) (I2SC_CR_TXEN_Msk & ((value) << I2SC_CR_TXEN_Pos)) +#define I2SC_CR_TXDIS_Pos _U_(5) /**< (I2SC_CR) Transmitter Disable Position */ +#define I2SC_CR_TXDIS_Msk (_U_(0x1) << I2SC_CR_TXDIS_Pos) /**< (I2SC_CR) Transmitter Disable Mask */ +#define I2SC_CR_TXDIS(value) (I2SC_CR_TXDIS_Msk & ((value) << I2SC_CR_TXDIS_Pos)) +#define I2SC_CR_SWRST_Pos _U_(7) /**< (I2SC_CR) Software Reset Position */ +#define I2SC_CR_SWRST_Msk (_U_(0x1) << I2SC_CR_SWRST_Pos) /**< (I2SC_CR) Software Reset Mask */ +#define I2SC_CR_SWRST(value) (I2SC_CR_SWRST_Msk & ((value) << I2SC_CR_SWRST_Pos)) +#define I2SC_CR_Msk _U_(0x000000BF) /**< (I2SC_CR) Register Mask */ + + +/* -------- I2SC_MR : (I2SC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define I2SC_MR_MODE_Pos _U_(0) /**< (I2SC_MR) Inter-IC Sound Controller Mode Position */ +#define I2SC_MR_MODE_Msk (_U_(0x1) << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Inter-IC Sound Controller Mode Mask */ +#define I2SC_MR_MODE(value) (I2SC_MR_MODE_Msk & ((value) << I2SC_MR_MODE_Pos)) +#define I2SC_MR_MODE_SLAVE_Val _U_(0x0) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. */ +#define I2SC_MR_MODE_MASTER_Val _U_(0x1) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. */ +#define I2SC_MR_MODE_SLAVE (I2SC_MR_MODE_SLAVE_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization. Position */ +#define I2SC_MR_MODE_MASTER (I2SC_MR_MODE_MASTER_Val << I2SC_MR_MODE_Pos) /**< (I2SC_MR) Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set. Position */ +#define I2SC_MR_DATALENGTH_Pos _U_(2) /**< (I2SC_MR) Data Word Length Position */ +#define I2SC_MR_DATALENGTH_Msk (_U_(0x7) << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data Word Length Mask */ +#define I2SC_MR_DATALENGTH(value) (I2SC_MR_DATALENGTH_Msk & ((value) << I2SC_MR_DATALENGTH_Pos)) +#define I2SC_MR_DATALENGTH_32_BITS_Val _U_(0x0) /**< (I2SC_MR) Data length is set to 32 bits */ +#define I2SC_MR_DATALENGTH_24_BITS_Val _U_(0x1) /**< (I2SC_MR) Data length is set to 24 bits */ +#define I2SC_MR_DATALENGTH_20_BITS_Val _U_(0x2) /**< (I2SC_MR) Data length is set to 20 bits */ +#define I2SC_MR_DATALENGTH_18_BITS_Val _U_(0x3) /**< (I2SC_MR) Data length is set to 18 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_Val _U_(0x4) /**< (I2SC_MR) Data length is set to 16 bits */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val _U_(0x5) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. */ +#define I2SC_MR_DATALENGTH_8_BITS_Val _U_(0x6) /**< (I2SC_MR) Data length is set to 8 bits */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val _U_(0x7) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. */ +#define I2SC_MR_DATALENGTH_32_BITS (I2SC_MR_DATALENGTH_32_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 32 bits Position */ +#define I2SC_MR_DATALENGTH_24_BITS (I2SC_MR_DATALENGTH_24_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 24 bits Position */ +#define I2SC_MR_DATALENGTH_20_BITS (I2SC_MR_DATALENGTH_20_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 20 bits Position */ +#define I2SC_MR_DATALENGTH_18_BITS (I2SC_MR_DATALENGTH_18_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 18 bits Position */ +#define I2SC_MR_DATALENGTH_16_BITS (I2SC_MR_DATALENGTH_16_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16 bits Position */ +#define I2SC_MR_DATALENGTH_16_BITS_COMPACT (I2SC_MR_DATALENGTH_16_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word. Position */ +#define I2SC_MR_DATALENGTH_8_BITS (I2SC_MR_DATALENGTH_8_BITS_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8 bits Position */ +#define I2SC_MR_DATALENGTH_8_BITS_COMPACT (I2SC_MR_DATALENGTH_8_BITS_COMPACT_Val << I2SC_MR_DATALENGTH_Pos) /**< (I2SC_MR) Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word. Position */ +#define I2SC_MR_RXMONO_Pos _U_(8) /**< (I2SC_MR) Receive Mono Position */ +#define I2SC_MR_RXMONO_Msk (_U_(0x1) << I2SC_MR_RXMONO_Pos) /**< (I2SC_MR) Receive Mono Mask */ +#define I2SC_MR_RXMONO(value) (I2SC_MR_RXMONO_Msk & ((value) << I2SC_MR_RXMONO_Pos)) +#define I2SC_MR_RXDMA_Pos _U_(9) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Position */ +#define I2SC_MR_RXDMA_Msk (_U_(0x1) << I2SC_MR_RXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Receiver Mask */ +#define I2SC_MR_RXDMA(value) (I2SC_MR_RXDMA_Msk & ((value) << I2SC_MR_RXDMA_Pos)) +#define I2SC_MR_RXLOOP_Pos _U_(10) /**< (I2SC_MR) Loopback Test Mode Position */ +#define I2SC_MR_RXLOOP_Msk (_U_(0x1) << I2SC_MR_RXLOOP_Pos) /**< (I2SC_MR) Loopback Test Mode Mask */ +#define I2SC_MR_RXLOOP(value) (I2SC_MR_RXLOOP_Msk & ((value) << I2SC_MR_RXLOOP_Pos)) +#define I2SC_MR_TXMONO_Pos _U_(12) /**< (I2SC_MR) Transmit Mono Position */ +#define I2SC_MR_TXMONO_Msk (_U_(0x1) << I2SC_MR_TXMONO_Pos) /**< (I2SC_MR) Transmit Mono Mask */ +#define I2SC_MR_TXMONO(value) (I2SC_MR_TXMONO_Msk & ((value) << I2SC_MR_TXMONO_Pos)) +#define I2SC_MR_TXDMA_Pos _U_(13) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Position */ +#define I2SC_MR_TXDMA_Msk (_U_(0x1) << I2SC_MR_TXDMA_Pos) /**< (I2SC_MR) Single or Multiple DMA Controller Channels for Transmitter Mask */ +#define I2SC_MR_TXDMA(value) (I2SC_MR_TXDMA_Msk & ((value) << I2SC_MR_TXDMA_Pos)) +#define I2SC_MR_TXSAME_Pos _U_(14) /**< (I2SC_MR) Transmit Data when Underrun Position */ +#define I2SC_MR_TXSAME_Msk (_U_(0x1) << I2SC_MR_TXSAME_Pos) /**< (I2SC_MR) Transmit Data when Underrun Mask */ +#define I2SC_MR_TXSAME(value) (I2SC_MR_TXSAME_Msk & ((value) << I2SC_MR_TXSAME_Pos)) +#define I2SC_MR_IMCKDIV_Pos _U_(16) /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Position */ +#define I2SC_MR_IMCKDIV_Msk (_U_(0x3F) << I2SC_MR_IMCKDIV_Pos) /**< (I2SC_MR) Selected Clock to I2SC Master Clock Ratio Mask */ +#define I2SC_MR_IMCKDIV(value) (I2SC_MR_IMCKDIV_Msk & ((value) << I2SC_MR_IMCKDIV_Pos)) +#define I2SC_MR_IMCKFS_Pos _U_(24) /**< (I2SC_MR) Master Clock to fs Ratio Position */ +#define I2SC_MR_IMCKFS_Msk (_U_(0x3F) << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Master Clock to fs Ratio Mask */ +#define I2SC_MR_IMCKFS(value) (I2SC_MR_IMCKFS_Msk & ((value) << I2SC_MR_IMCKFS_Pos)) +#define I2SC_MR_IMCKFS_M2SF32_Val _U_(0x0) /**< (I2SC_MR) Sample frequency ratio set to 32 */ +#define I2SC_MR_IMCKFS_M2SF64_Val _U_(0x1) /**< (I2SC_MR) Sample frequency ratio set to 64 */ +#define I2SC_MR_IMCKFS_M2SF96_Val _U_(0x2) /**< (I2SC_MR) Sample frequency ratio set to 96 */ +#define I2SC_MR_IMCKFS_M2SF128_Val _U_(0x3) /**< (I2SC_MR) Sample frequency ratio set to 128 */ +#define I2SC_MR_IMCKFS_M2SF192_Val _U_(0x5) /**< (I2SC_MR) Sample frequency ratio set to 192 */ +#define I2SC_MR_IMCKFS_M2SF256_Val _U_(0x7) /**< (I2SC_MR) Sample frequency ratio set to 256 */ +#define I2SC_MR_IMCKFS_M2SF384_Val _U_(0xB) /**< (I2SC_MR) Sample frequency ratio set to 384 */ +#define I2SC_MR_IMCKFS_M2SF512_Val _U_(0xF) /**< (I2SC_MR) Sample frequency ratio set to 512 */ +#define I2SC_MR_IMCKFS_M2SF768_Val _U_(0x17) /**< (I2SC_MR) Sample frequency ratio set to 768 */ +#define I2SC_MR_IMCKFS_M2SF1024_Val _U_(0x1F) /**< (I2SC_MR) Sample frequency ratio set to 1024 */ +#define I2SC_MR_IMCKFS_M2SF1536_Val _U_(0x2F) /**< (I2SC_MR) Sample frequency ratio set to 1536 */ +#define I2SC_MR_IMCKFS_M2SF2048_Val _U_(0x3F) /**< (I2SC_MR) Sample frequency ratio set to 2048 */ +#define I2SC_MR_IMCKFS_M2SF32 (I2SC_MR_IMCKFS_M2SF32_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 32 Position */ +#define I2SC_MR_IMCKFS_M2SF64 (I2SC_MR_IMCKFS_M2SF64_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 64 Position */ +#define I2SC_MR_IMCKFS_M2SF96 (I2SC_MR_IMCKFS_M2SF96_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 96 Position */ +#define I2SC_MR_IMCKFS_M2SF128 (I2SC_MR_IMCKFS_M2SF128_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 128 Position */ +#define I2SC_MR_IMCKFS_M2SF192 (I2SC_MR_IMCKFS_M2SF192_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 192 Position */ +#define I2SC_MR_IMCKFS_M2SF256 (I2SC_MR_IMCKFS_M2SF256_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 256 Position */ +#define I2SC_MR_IMCKFS_M2SF384 (I2SC_MR_IMCKFS_M2SF384_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 384 Position */ +#define I2SC_MR_IMCKFS_M2SF512 (I2SC_MR_IMCKFS_M2SF512_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 512 Position */ +#define I2SC_MR_IMCKFS_M2SF768 (I2SC_MR_IMCKFS_M2SF768_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 768 Position */ +#define I2SC_MR_IMCKFS_M2SF1024 (I2SC_MR_IMCKFS_M2SF1024_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1024 Position */ +#define I2SC_MR_IMCKFS_M2SF1536 (I2SC_MR_IMCKFS_M2SF1536_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 1536 Position */ +#define I2SC_MR_IMCKFS_M2SF2048 (I2SC_MR_IMCKFS_M2SF2048_Val << I2SC_MR_IMCKFS_Pos) /**< (I2SC_MR) Sample frequency ratio set to 2048 Position */ +#define I2SC_MR_IMCKMODE_Pos _U_(30) /**< (I2SC_MR) Master Clock Mode Position */ +#define I2SC_MR_IMCKMODE_Msk (_U_(0x1) << I2SC_MR_IMCKMODE_Pos) /**< (I2SC_MR) Master Clock Mode Mask */ +#define I2SC_MR_IMCKMODE(value) (I2SC_MR_IMCKMODE_Msk & ((value) << I2SC_MR_IMCKMODE_Pos)) +#define I2SC_MR_IWS_Pos _U_(31) /**< (I2SC_MR) I2SC_WS Slot Width Position */ +#define I2SC_MR_IWS_Msk (_U_(0x1) << I2SC_MR_IWS_Pos) /**< (I2SC_MR) I2SC_WS Slot Width Mask */ +#define I2SC_MR_IWS(value) (I2SC_MR_IWS_Msk & ((value) << I2SC_MR_IWS_Pos)) +#define I2SC_MR_Msk _U_(0xFF3F771D) /**< (I2SC_MR) Register Mask */ + + +/* -------- I2SC_SR : (I2SC Offset: 0x08) ( R/ 32) Status Register -------- */ +#define I2SC_SR_RXEN_Pos _U_(0) /**< (I2SC_SR) Receiver Enabled Position */ +#define I2SC_SR_RXEN_Msk (_U_(0x1) << I2SC_SR_RXEN_Pos) /**< (I2SC_SR) Receiver Enabled Mask */ +#define I2SC_SR_RXEN(value) (I2SC_SR_RXEN_Msk & ((value) << I2SC_SR_RXEN_Pos)) +#define I2SC_SR_RXRDY_Pos _U_(1) /**< (I2SC_SR) Receive Ready Position */ +#define I2SC_SR_RXRDY_Msk (_U_(0x1) << I2SC_SR_RXRDY_Pos) /**< (I2SC_SR) Receive Ready Mask */ +#define I2SC_SR_RXRDY(value) (I2SC_SR_RXRDY_Msk & ((value) << I2SC_SR_RXRDY_Pos)) +#define I2SC_SR_RXOR_Pos _U_(2) /**< (I2SC_SR) Receive Overrun Position */ +#define I2SC_SR_RXOR_Msk (_U_(0x1) << I2SC_SR_RXOR_Pos) /**< (I2SC_SR) Receive Overrun Mask */ +#define I2SC_SR_RXOR(value) (I2SC_SR_RXOR_Msk & ((value) << I2SC_SR_RXOR_Pos)) +#define I2SC_SR_TXEN_Pos _U_(4) /**< (I2SC_SR) Transmitter Enabled Position */ +#define I2SC_SR_TXEN_Msk (_U_(0x1) << I2SC_SR_TXEN_Pos) /**< (I2SC_SR) Transmitter Enabled Mask */ +#define I2SC_SR_TXEN(value) (I2SC_SR_TXEN_Msk & ((value) << I2SC_SR_TXEN_Pos)) +#define I2SC_SR_TXRDY_Pos _U_(5) /**< (I2SC_SR) Transmit Ready Position */ +#define I2SC_SR_TXRDY_Msk (_U_(0x1) << I2SC_SR_TXRDY_Pos) /**< (I2SC_SR) Transmit Ready Mask */ +#define I2SC_SR_TXRDY(value) (I2SC_SR_TXRDY_Msk & ((value) << I2SC_SR_TXRDY_Pos)) +#define I2SC_SR_TXUR_Pos _U_(6) /**< (I2SC_SR) Transmit Underrun Position */ +#define I2SC_SR_TXUR_Msk (_U_(0x1) << I2SC_SR_TXUR_Pos) /**< (I2SC_SR) Transmit Underrun Mask */ +#define I2SC_SR_TXUR(value) (I2SC_SR_TXUR_Msk & ((value) << I2SC_SR_TXUR_Pos)) +#define I2SC_SR_RXORCH_Pos _U_(8) /**< (I2SC_SR) Receive Overrun Channel Position */ +#define I2SC_SR_RXORCH_Msk (_U_(0x3) << I2SC_SR_RXORCH_Pos) /**< (I2SC_SR) Receive Overrun Channel Mask */ +#define I2SC_SR_RXORCH(value) (I2SC_SR_RXORCH_Msk & ((value) << I2SC_SR_RXORCH_Pos)) +#define I2SC_SR_TXURCH_Pos _U_(20) /**< (I2SC_SR) Transmit Underrun Channel Position */ +#define I2SC_SR_TXURCH_Msk (_U_(0x3) << I2SC_SR_TXURCH_Pos) /**< (I2SC_SR) Transmit Underrun Channel Mask */ +#define I2SC_SR_TXURCH(value) (I2SC_SR_TXURCH_Msk & ((value) << I2SC_SR_TXURCH_Pos)) +#define I2SC_SR_Msk _U_(0x00300377) /**< (I2SC_SR) Register Mask */ + + +/* -------- I2SC_SCR : (I2SC Offset: 0x0C) ( /W 32) Status Clear Register -------- */ +#define I2SC_SCR_RXOR_Pos _U_(2) /**< (I2SC_SCR) Receive Overrun Status Clear Position */ +#define I2SC_SCR_RXOR_Msk (_U_(0x1) << I2SC_SCR_RXOR_Pos) /**< (I2SC_SCR) Receive Overrun Status Clear Mask */ +#define I2SC_SCR_RXOR(value) (I2SC_SCR_RXOR_Msk & ((value) << I2SC_SCR_RXOR_Pos)) +#define I2SC_SCR_TXUR_Pos _U_(6) /**< (I2SC_SCR) Transmit Underrun Status Clear Position */ +#define I2SC_SCR_TXUR_Msk (_U_(0x1) << I2SC_SCR_TXUR_Pos) /**< (I2SC_SCR) Transmit Underrun Status Clear Mask */ +#define I2SC_SCR_TXUR(value) (I2SC_SCR_TXUR_Msk & ((value) << I2SC_SCR_TXUR_Pos)) +#define I2SC_SCR_RXORCH_Pos _U_(8) /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Position */ +#define I2SC_SCR_RXORCH_Msk (_U_(0x3) << I2SC_SCR_RXORCH_Pos) /**< (I2SC_SCR) Receive Overrun Per Channel Status Clear Mask */ +#define I2SC_SCR_RXORCH(value) (I2SC_SCR_RXORCH_Msk & ((value) << I2SC_SCR_RXORCH_Pos)) +#define I2SC_SCR_TXURCH_Pos _U_(20) /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Position */ +#define I2SC_SCR_TXURCH_Msk (_U_(0x3) << I2SC_SCR_TXURCH_Pos) /**< (I2SC_SCR) Transmit Underrun Per Channel Status Clear Mask */ +#define I2SC_SCR_TXURCH(value) (I2SC_SCR_TXURCH_Msk & ((value) << I2SC_SCR_TXURCH_Pos)) +#define I2SC_SCR_Msk _U_(0x00300344) /**< (I2SC_SCR) Register Mask */ + + +/* -------- I2SC_SSR : (I2SC Offset: 0x10) ( /W 32) Status Set Register -------- */ +#define I2SC_SSR_RXOR_Pos _U_(2) /**< (I2SC_SSR) Receive Overrun Status Set Position */ +#define I2SC_SSR_RXOR_Msk (_U_(0x1) << I2SC_SSR_RXOR_Pos) /**< (I2SC_SSR) Receive Overrun Status Set Mask */ +#define I2SC_SSR_RXOR(value) (I2SC_SSR_RXOR_Msk & ((value) << I2SC_SSR_RXOR_Pos)) +#define I2SC_SSR_TXUR_Pos _U_(6) /**< (I2SC_SSR) Transmit Underrun Status Set Position */ +#define I2SC_SSR_TXUR_Msk (_U_(0x1) << I2SC_SSR_TXUR_Pos) /**< (I2SC_SSR) Transmit Underrun Status Set Mask */ +#define I2SC_SSR_TXUR(value) (I2SC_SSR_TXUR_Msk & ((value) << I2SC_SSR_TXUR_Pos)) +#define I2SC_SSR_RXORCH_Pos _U_(8) /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Position */ +#define I2SC_SSR_RXORCH_Msk (_U_(0x3) << I2SC_SSR_RXORCH_Pos) /**< (I2SC_SSR) Receive Overrun Per Channel Status Set Mask */ +#define I2SC_SSR_RXORCH(value) (I2SC_SSR_RXORCH_Msk & ((value) << I2SC_SSR_RXORCH_Pos)) +#define I2SC_SSR_TXURCH_Pos _U_(20) /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Position */ +#define I2SC_SSR_TXURCH_Msk (_U_(0x3) << I2SC_SSR_TXURCH_Pos) /**< (I2SC_SSR) Transmit Underrun Per Channel Status Set Mask */ +#define I2SC_SSR_TXURCH(value) (I2SC_SSR_TXURCH_Msk & ((value) << I2SC_SSR_TXURCH_Pos)) +#define I2SC_SSR_Msk _U_(0x00300344) /**< (I2SC_SSR) Register Mask */ + + +/* -------- I2SC_IER : (I2SC Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ +#define I2SC_IER_RXRDY_Pos _U_(1) /**< (I2SC_IER) Receiver Ready Interrupt Enable Position */ +#define I2SC_IER_RXRDY_Msk (_U_(0x1) << I2SC_IER_RXRDY_Pos) /**< (I2SC_IER) Receiver Ready Interrupt Enable Mask */ +#define I2SC_IER_RXRDY(value) (I2SC_IER_RXRDY_Msk & ((value) << I2SC_IER_RXRDY_Pos)) +#define I2SC_IER_RXOR_Pos _U_(2) /**< (I2SC_IER) Receiver Overrun Interrupt Enable Position */ +#define I2SC_IER_RXOR_Msk (_U_(0x1) << I2SC_IER_RXOR_Pos) /**< (I2SC_IER) Receiver Overrun Interrupt Enable Mask */ +#define I2SC_IER_RXOR(value) (I2SC_IER_RXOR_Msk & ((value) << I2SC_IER_RXOR_Pos)) +#define I2SC_IER_TXRDY_Pos _U_(5) /**< (I2SC_IER) Transmit Ready Interrupt Enable Position */ +#define I2SC_IER_TXRDY_Msk (_U_(0x1) << I2SC_IER_TXRDY_Pos) /**< (I2SC_IER) Transmit Ready Interrupt Enable Mask */ +#define I2SC_IER_TXRDY(value) (I2SC_IER_TXRDY_Msk & ((value) << I2SC_IER_TXRDY_Pos)) +#define I2SC_IER_TXUR_Pos _U_(6) /**< (I2SC_IER) Transmit Underflow Interrupt Enable Position */ +#define I2SC_IER_TXUR_Msk (_U_(0x1) << I2SC_IER_TXUR_Pos) /**< (I2SC_IER) Transmit Underflow Interrupt Enable Mask */ +#define I2SC_IER_TXUR(value) (I2SC_IER_TXUR_Msk & ((value) << I2SC_IER_TXUR_Pos)) +#define I2SC_IER_Msk _U_(0x00000066) /**< (I2SC_IER) Register Mask */ + + +/* -------- I2SC_IDR : (I2SC Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ +#define I2SC_IDR_RXRDY_Pos _U_(1) /**< (I2SC_IDR) Receiver Ready Interrupt Disable Position */ +#define I2SC_IDR_RXRDY_Msk (_U_(0x1) << I2SC_IDR_RXRDY_Pos) /**< (I2SC_IDR) Receiver Ready Interrupt Disable Mask */ +#define I2SC_IDR_RXRDY(value) (I2SC_IDR_RXRDY_Msk & ((value) << I2SC_IDR_RXRDY_Pos)) +#define I2SC_IDR_RXOR_Pos _U_(2) /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Position */ +#define I2SC_IDR_RXOR_Msk (_U_(0x1) << I2SC_IDR_RXOR_Pos) /**< (I2SC_IDR) Receiver Overrun Interrupt Disable Mask */ +#define I2SC_IDR_RXOR(value) (I2SC_IDR_RXOR_Msk & ((value) << I2SC_IDR_RXOR_Pos)) +#define I2SC_IDR_TXRDY_Pos _U_(5) /**< (I2SC_IDR) Transmit Ready Interrupt Disable Position */ +#define I2SC_IDR_TXRDY_Msk (_U_(0x1) << I2SC_IDR_TXRDY_Pos) /**< (I2SC_IDR) Transmit Ready Interrupt Disable Mask */ +#define I2SC_IDR_TXRDY(value) (I2SC_IDR_TXRDY_Msk & ((value) << I2SC_IDR_TXRDY_Pos)) +#define I2SC_IDR_TXUR_Pos _U_(6) /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Position */ +#define I2SC_IDR_TXUR_Msk (_U_(0x1) << I2SC_IDR_TXUR_Pos) /**< (I2SC_IDR) Transmit Underflow Interrupt Disable Mask */ +#define I2SC_IDR_TXUR(value) (I2SC_IDR_TXUR_Msk & ((value) << I2SC_IDR_TXUR_Pos)) +#define I2SC_IDR_Msk _U_(0x00000066) /**< (I2SC_IDR) Register Mask */ + + +/* -------- I2SC_IMR : (I2SC Offset: 0x1C) ( R/ 32) Interrupt Mask Register -------- */ +#define I2SC_IMR_RXRDY_Pos _U_(1) /**< (I2SC_IMR) Receiver Ready Interrupt Disable Position */ +#define I2SC_IMR_RXRDY_Msk (_U_(0x1) << I2SC_IMR_RXRDY_Pos) /**< (I2SC_IMR) Receiver Ready Interrupt Disable Mask */ +#define I2SC_IMR_RXRDY(value) (I2SC_IMR_RXRDY_Msk & ((value) << I2SC_IMR_RXRDY_Pos)) +#define I2SC_IMR_RXOR_Pos _U_(2) /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Position */ +#define I2SC_IMR_RXOR_Msk (_U_(0x1) << I2SC_IMR_RXOR_Pos) /**< (I2SC_IMR) Receiver Overrun Interrupt Disable Mask */ +#define I2SC_IMR_RXOR(value) (I2SC_IMR_RXOR_Msk & ((value) << I2SC_IMR_RXOR_Pos)) +#define I2SC_IMR_TXRDY_Pos _U_(5) /**< (I2SC_IMR) Transmit Ready Interrupt Disable Position */ +#define I2SC_IMR_TXRDY_Msk (_U_(0x1) << I2SC_IMR_TXRDY_Pos) /**< (I2SC_IMR) Transmit Ready Interrupt Disable Mask */ +#define I2SC_IMR_TXRDY(value) (I2SC_IMR_TXRDY_Msk & ((value) << I2SC_IMR_TXRDY_Pos)) +#define I2SC_IMR_TXUR_Pos _U_(6) /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Position */ +#define I2SC_IMR_TXUR_Msk (_U_(0x1) << I2SC_IMR_TXUR_Pos) /**< (I2SC_IMR) Transmit Underflow Interrupt Disable Mask */ +#define I2SC_IMR_TXUR(value) (I2SC_IMR_TXUR_Msk & ((value) << I2SC_IMR_TXUR_Pos)) +#define I2SC_IMR_Msk _U_(0x00000066) /**< (I2SC_IMR) Register Mask */ + + +/* -------- I2SC_RHR : (I2SC Offset: 0x20) ( R/ 32) Receiver Holding Register -------- */ +#define I2SC_RHR_RHR_Pos _U_(0) /**< (I2SC_RHR) Receiver Holding Register Position */ +#define I2SC_RHR_RHR_Msk (_U_(0xFFFFFFFF) << I2SC_RHR_RHR_Pos) /**< (I2SC_RHR) Receiver Holding Register Mask */ +#define I2SC_RHR_RHR(value) (I2SC_RHR_RHR_Msk & ((value) << I2SC_RHR_RHR_Pos)) +#define I2SC_RHR_Msk _U_(0xFFFFFFFF) /**< (I2SC_RHR) Register Mask */ + + +/* -------- I2SC_THR : (I2SC Offset: 0x24) ( /W 32) Transmitter Holding Register -------- */ +#define I2SC_THR_THR_Pos _U_(0) /**< (I2SC_THR) Transmitter Holding Register Position */ +#define I2SC_THR_THR_Msk (_U_(0xFFFFFFFF) << I2SC_THR_THR_Pos) /**< (I2SC_THR) Transmitter Holding Register Mask */ +#define I2SC_THR_THR(value) (I2SC_THR_THR_Msk & ((value) << I2SC_THR_THR_Pos)) +#define I2SC_THR_Msk _U_(0xFFFFFFFF) /**< (I2SC_THR) Register Mask */ + + +/** \brief I2SC register offsets definitions */ +#define I2SC_CR_REG_OFST (0x00) /**< (I2SC_CR) Control Register Offset */ +#define I2SC_MR_REG_OFST (0x04) /**< (I2SC_MR) Mode Register Offset */ +#define I2SC_SR_REG_OFST (0x08) /**< (I2SC_SR) Status Register Offset */ +#define I2SC_SCR_REG_OFST (0x0C) /**< (I2SC_SCR) Status Clear Register Offset */ +#define I2SC_SSR_REG_OFST (0x10) /**< (I2SC_SSR) Status Set Register Offset */ +#define I2SC_IER_REG_OFST (0x14) /**< (I2SC_IER) Interrupt Enable Register Offset */ +#define I2SC_IDR_REG_OFST (0x18) /**< (I2SC_IDR) Interrupt Disable Register Offset */ +#define I2SC_IMR_REG_OFST (0x1C) /**< (I2SC_IMR) Interrupt Mask Register Offset */ +#define I2SC_RHR_REG_OFST (0x20) /**< (I2SC_RHR) Receiver Holding Register Offset */ +#define I2SC_THR_REG_OFST (0x24) /**< (I2SC_THR) Transmitter Holding Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief I2SC register API structure */ +typedef struct +{ + __O uint32_t I2SC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t I2SC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t I2SC_SR; /**< Offset: 0x08 (R/ 32) Status Register */ + __O uint32_t I2SC_SCR; /**< Offset: 0x0C ( /W 32) Status Clear Register */ + __O uint32_t I2SC_SSR; /**< Offset: 0x10 ( /W 32) Status Set Register */ + __O uint32_t I2SC_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O uint32_t I2SC_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I uint32_t I2SC_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __I uint32_t I2SC_RHR; /**< Offset: 0x20 (R/ 32) Receiver Holding Register */ + __O uint32_t I2SC_THR; /**< Offset: 0x24 ( /W 32) Transmitter Holding Register */ +} i2sc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_I2SC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/icm.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/icm.h new file mode 100644 index 00000000..050d0893 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/icm.h @@ -0,0 +1,272 @@ +/** + * \brief Component description for ICM + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_ICM_COMPONENT_H_ +#define _SAME70_ICM_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ICM */ +/* ************************************************************************** */ + +/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */ +#define ICM_CFG_WBDIS_Pos _U_(0) /**< (ICM_CFG) Write Back Disable Position */ +#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */ +#define ICM_CFG_WBDIS(value) (ICM_CFG_WBDIS_Msk & ((value) << ICM_CFG_WBDIS_Pos)) +#define ICM_CFG_EOMDIS_Pos _U_(1) /**< (ICM_CFG) End of Monitoring Disable Position */ +#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */ +#define ICM_CFG_EOMDIS(value) (ICM_CFG_EOMDIS_Msk & ((value) << ICM_CFG_EOMDIS_Pos)) +#define ICM_CFG_SLBDIS_Pos _U_(2) /**< (ICM_CFG) Secondary List Branching Disable Position */ +#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */ +#define ICM_CFG_SLBDIS(value) (ICM_CFG_SLBDIS_Msk & ((value) << ICM_CFG_SLBDIS_Pos)) +#define ICM_CFG_BBC_Pos _U_(4) /**< (ICM_CFG) Bus Burden Control Position */ +#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */ +#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) +#define ICM_CFG_ASCD_Pos _U_(8) /**< (ICM_CFG) Automatic Switch To Compare Digest Position */ +#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */ +#define ICM_CFG_ASCD(value) (ICM_CFG_ASCD_Msk & ((value) << ICM_CFG_ASCD_Pos)) +#define ICM_CFG_DUALBUFF_Pos _U_(9) /**< (ICM_CFG) Dual Input Buffer Position */ +#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */ +#define ICM_CFG_DUALBUFF(value) (ICM_CFG_DUALBUFF_Msk & ((value) << ICM_CFG_DUALBUFF_Pos)) +#define ICM_CFG_UIHASH_Pos _U_(12) /**< (ICM_CFG) User Initial Hash Value Position */ +#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */ +#define ICM_CFG_UIHASH(value) (ICM_CFG_UIHASH_Msk & ((value) << ICM_CFG_UIHASH_Pos)) +#define ICM_CFG_UALGO_Pos _U_(13) /**< (ICM_CFG) User SHA Algorithm Position */ +#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */ +#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) +#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */ +#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */ +#define ICM_CFG_Msk _U_(0x0000F3F7) /**< (ICM_CFG) Register Mask */ + + +/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control Register -------- */ +#define ICM_CTRL_ENABLE_Pos _U_(0) /**< (ICM_CTRL) ICM Enable Position */ +#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */ +#define ICM_CTRL_ENABLE(value) (ICM_CTRL_ENABLE_Msk & ((value) << ICM_CTRL_ENABLE_Pos)) +#define ICM_CTRL_DISABLE_Pos _U_(1) /**< (ICM_CTRL) ICM Disable Register Position */ +#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */ +#define ICM_CTRL_DISABLE(value) (ICM_CTRL_DISABLE_Msk & ((value) << ICM_CTRL_DISABLE_Pos)) +#define ICM_CTRL_SWRST_Pos _U_(2) /**< (ICM_CTRL) Software Reset Position */ +#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */ +#define ICM_CTRL_SWRST(value) (ICM_CTRL_SWRST_Msk & ((value) << ICM_CTRL_SWRST_Pos)) +#define ICM_CTRL_REHASH_Pos _U_(4) /**< (ICM_CTRL) Recompute Internal Hash Position */ +#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */ +#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)) +#define ICM_CTRL_RMDIS_Pos _U_(8) /**< (ICM_CTRL) Region Monitoring Disable Position */ +#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */ +#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)) +#define ICM_CTRL_RMEN_Pos _U_(12) /**< (ICM_CTRL) Region Monitoring Enable Position */ +#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */ +#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)) +#define ICM_CTRL_Msk _U_(0x0000FFF7) /**< (ICM_CTRL) Register Mask */ + + +/* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status Register -------- */ +#define ICM_SR_ENABLE_Pos _U_(0) /**< (ICM_SR) ICM Controller Enable Register Position */ +#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */ +#define ICM_SR_ENABLE(value) (ICM_SR_ENABLE_Msk & ((value) << ICM_SR_ENABLE_Pos)) +#define ICM_SR_RAWRMDIS_Pos _U_(8) /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */ +#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */ +#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)) +#define ICM_SR_RMDIS_Pos _U_(12) /**< (ICM_SR) Region Monitoring Disabled Status Position */ +#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */ +#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)) +#define ICM_SR_Msk _U_(0x0000FF01) /**< (ICM_SR) Register Mask */ + + +/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos _U_(0) /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */ +#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */ +#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) +#define ICM_IER_RDM_Pos _U_(4) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */ +#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */ +#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) +#define ICM_IER_RBE_Pos _U_(8) /**< (ICM_IER) Region Bus Error Interrupt Enable Position */ +#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */ +#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) +#define ICM_IER_RWC_Pos _U_(12) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */ +#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */ +#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) +#define ICM_IER_REC_Pos _U_(16) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */ +#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */ +#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) +#define ICM_IER_RSU_Pos _U_(20) /**< (ICM_IER) Region Status Updated Interrupt Disable Position */ +#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */ +#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) +#define ICM_IER_URAD_Pos _U_(24) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */ +#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */ +#define ICM_IER_URAD(value) (ICM_IER_URAD_Msk & ((value) << ICM_IER_URAD_Pos)) +#define ICM_IER_Msk _U_(0x01FFFFFF) /**< (ICM_IER) Register Mask */ + + +/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos _U_(0) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */ +#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */ +#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) +#define ICM_IDR_RDM_Pos _U_(4) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */ +#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */ +#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) +#define ICM_IDR_RBE_Pos _U_(8) /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */ +#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */ +#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) +#define ICM_IDR_RWC_Pos _U_(12) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */ +#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */ +#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)) +#define ICM_IDR_REC_Pos _U_(16) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */ +#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */ +#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)) +#define ICM_IDR_RSU_Pos _U_(20) /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */ +#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */ +#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)) +#define ICM_IDR_URAD_Pos _U_(24) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */ +#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */ +#define ICM_IDR_URAD(value) (ICM_IDR_URAD_Msk & ((value) << ICM_IDR_URAD_Pos)) +#define ICM_IDR_Msk _U_(0x01FFFFFF) /**< (ICM_IDR) Register Mask */ + + +/* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos _U_(0) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */ +#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */ +#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos)) +#define ICM_IMR_RDM_Pos _U_(4) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */ +#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */ +#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos)) +#define ICM_IMR_RBE_Pos _U_(8) /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */ +#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */ +#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos)) +#define ICM_IMR_RWC_Pos _U_(12) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */ +#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos)) +#define ICM_IMR_REC_Pos _U_(16) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */ +#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */ +#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos)) +#define ICM_IMR_RSU_Pos _U_(20) /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */ +#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */ +#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos)) +#define ICM_IMR_URAD_Pos _U_(24) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */ +#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */ +#define ICM_IMR_URAD(value) (ICM_IMR_URAD_Msk & ((value) << ICM_IMR_URAD_Pos)) +#define ICM_IMR_Msk _U_(0x01FFFFFF) /**< (ICM_IMR) Register Mask */ + + +/* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos _U_(0) /**< (ICM_ISR) Region Hash Completed Position */ +#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */ +#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos)) +#define ICM_ISR_RDM_Pos _U_(4) /**< (ICM_ISR) Region Digest Mismatch Position */ +#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */ +#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos)) +#define ICM_ISR_RBE_Pos _U_(8) /**< (ICM_ISR) Region Bus Error Position */ +#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */ +#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos)) +#define ICM_ISR_RWC_Pos _U_(12) /**< (ICM_ISR) Region Wrap Condition Detected Position */ +#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */ +#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos)) +#define ICM_ISR_REC_Pos _U_(16) /**< (ICM_ISR) Region End bit Condition Detected Position */ +#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */ +#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos)) +#define ICM_ISR_RSU_Pos _U_(20) /**< (ICM_ISR) Region Status Updated Detected Position */ +#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */ +#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos)) +#define ICM_ISR_URAD_Pos _U_(24) /**< (ICM_ISR) Undefined Register Access Detection Status Position */ +#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */ +#define ICM_ISR_URAD(value) (ICM_ISR_URAD_Msk & ((value) << ICM_ISR_URAD_Pos)) +#define ICM_ISR_Msk _U_(0x01FFFFFF) /**< (ICM_ISR) Register Mask */ + + +/* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos _U_(0) /**< (ICM_UASR) Undefined Register Access Trace Position */ +#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */ +#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos)) +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */ +#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */ +#define ICM_UASR_Msk _U_(0x00000007) /**< (ICM_UASR) Register Mask */ + + +/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos _U_(6) /**< (ICM_DSCR) Descriptor Area Start Address Position */ +#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */ +#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)) +#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */ + + +/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos _U_(7) /**< (ICM_HASH) Hash Area Start Address Position */ +#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */ +#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)) +#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */ + + +/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value 0 Register 0 -------- */ +#define ICM_UIHVAL_VAL_Pos _U_(0) /**< (ICM_UIHVAL) Initial Hash Value Position */ +#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */ +#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)) +#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */ + + +/** \brief ICM register offsets definitions */ +#define ICM_CFG_REG_OFST (0x00) /**< (ICM_CFG) Configuration Register Offset */ +#define ICM_CTRL_REG_OFST (0x04) /**< (ICM_CTRL) Control Register Offset */ +#define ICM_SR_REG_OFST (0x08) /**< (ICM_SR) Status Register Offset */ +#define ICM_IER_REG_OFST (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */ +#define ICM_IDR_REG_OFST (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */ +#define ICM_IMR_REG_OFST (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */ +#define ICM_ISR_REG_OFST (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */ +#define ICM_UASR_REG_OFST (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */ +#define ICM_DSCR_REG_OFST (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */ +#define ICM_HASH_REG_OFST (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */ +#define ICM_UIHVAL_REG_OFST (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ICM register API structure */ +typedef struct +{ + __IO uint32_t ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */ + __O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */ + __I uint32_t ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */ + __I uint8_t Reserved2[0x0C]; + __IO uint32_t ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */ +} icm_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ICM_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/isi.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/isi.h new file mode 100644 index 00000000..a9eb8aed --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/isi.h @@ -0,0 +1,543 @@ +/** + * \brief Component description for ISI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_ISI_COMPONENT_H_ +#define _SAME70_ISI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR ISI */ +/* ************************************************************************** */ + +/* -------- ISI_CFG1 : (ISI Offset: 0x00) (R/W 32) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL_Pos _U_(2) /**< (ISI_CFG1) Horizontal Synchronization Polarity Position */ +#define ISI_CFG1_HSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_HSYNC_POL_Pos) /**< (ISI_CFG1) Horizontal Synchronization Polarity Mask */ +#define ISI_CFG1_HSYNC_POL(value) (ISI_CFG1_HSYNC_POL_Msk & ((value) << ISI_CFG1_HSYNC_POL_Pos)) +#define ISI_CFG1_VSYNC_POL_Pos _U_(3) /**< (ISI_CFG1) Vertical Synchronization Polarity Position */ +#define ISI_CFG1_VSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_VSYNC_POL_Pos) /**< (ISI_CFG1) Vertical Synchronization Polarity Mask */ +#define ISI_CFG1_VSYNC_POL(value) (ISI_CFG1_VSYNC_POL_Msk & ((value) << ISI_CFG1_VSYNC_POL_Pos)) +#define ISI_CFG1_PIXCLK_POL_Pos _U_(4) /**< (ISI_CFG1) Pixel Clock Polarity Position */ +#define ISI_CFG1_PIXCLK_POL_Msk (_U_(0x1) << ISI_CFG1_PIXCLK_POL_Pos) /**< (ISI_CFG1) Pixel Clock Polarity Mask */ +#define ISI_CFG1_PIXCLK_POL(value) (ISI_CFG1_PIXCLK_POL_Msk & ((value) << ISI_CFG1_PIXCLK_POL_Pos)) +#define ISI_CFG1_GRAYLE_Pos _U_(5) /**< (ISI_CFG1) Grayscale Little Endian Position */ +#define ISI_CFG1_GRAYLE_Msk (_U_(0x1) << ISI_CFG1_GRAYLE_Pos) /**< (ISI_CFG1) Grayscale Little Endian Mask */ +#define ISI_CFG1_GRAYLE(value) (ISI_CFG1_GRAYLE_Msk & ((value) << ISI_CFG1_GRAYLE_Pos)) +#define ISI_CFG1_EMB_SYNC_Pos _U_(6) /**< (ISI_CFG1) Embedded Synchronization Position */ +#define ISI_CFG1_EMB_SYNC_Msk (_U_(0x1) << ISI_CFG1_EMB_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Mask */ +#define ISI_CFG1_EMB_SYNC(value) (ISI_CFG1_EMB_SYNC_Msk & ((value) << ISI_CFG1_EMB_SYNC_Pos)) +#define ISI_CFG1_CRC_SYNC_Pos _U_(7) /**< (ISI_CFG1) Embedded Synchronization Correction Position */ +#define ISI_CFG1_CRC_SYNC_Msk (_U_(0x1) << ISI_CFG1_CRC_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Correction Mask */ +#define ISI_CFG1_CRC_SYNC(value) (ISI_CFG1_CRC_SYNC_Msk & ((value) << ISI_CFG1_CRC_SYNC_Pos)) +#define ISI_CFG1_FRATE_Pos _U_(8) /**< (ISI_CFG1) Frame Rate [0..7] Position */ +#define ISI_CFG1_FRATE_Msk (_U_(0x7) << ISI_CFG1_FRATE_Pos) /**< (ISI_CFG1) Frame Rate [0..7] Mask */ +#define ISI_CFG1_FRATE(value) (ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)) +#define ISI_CFG1_DISCR_Pos _U_(11) /**< (ISI_CFG1) Disable Codec Request Position */ +#define ISI_CFG1_DISCR_Msk (_U_(0x1) << ISI_CFG1_DISCR_Pos) /**< (ISI_CFG1) Disable Codec Request Mask */ +#define ISI_CFG1_DISCR(value) (ISI_CFG1_DISCR_Msk & ((value) << ISI_CFG1_DISCR_Pos)) +#define ISI_CFG1_FULL_Pos _U_(12) /**< (ISI_CFG1) Full Mode is Allowed Position */ +#define ISI_CFG1_FULL_Msk (_U_(0x1) << ISI_CFG1_FULL_Pos) /**< (ISI_CFG1) Full Mode is Allowed Mask */ +#define ISI_CFG1_FULL(value) (ISI_CFG1_FULL_Msk & ((value) << ISI_CFG1_FULL_Pos)) +#define ISI_CFG1_THMASK_Pos _U_(13) /**< (ISI_CFG1) Threshold Mask Position */ +#define ISI_CFG1_THMASK_Msk (_U_(0x3) << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Threshold Mask Mask */ +#define ISI_CFG1_THMASK(value) (ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)) +#define ISI_CFG1_THMASK_BEATS_4_Val _U_(0x0) /**< (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8_Val _U_(0x1) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16_Val _U_(0x2) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_4 (ISI_CFG1_THMASK_BEATS_4_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_8 (ISI_CFG1_THMASK_BEATS_8_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed Position */ +#define ISI_CFG1_THMASK_BEATS_16 (ISI_CFG1_THMASK_BEATS_16_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed Position */ +#define ISI_CFG1_SLD_Pos _U_(16) /**< (ISI_CFG1) Start of Line Delay Position */ +#define ISI_CFG1_SLD_Msk (_U_(0xFF) << ISI_CFG1_SLD_Pos) /**< (ISI_CFG1) Start of Line Delay Mask */ +#define ISI_CFG1_SLD(value) (ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)) +#define ISI_CFG1_SFD_Pos _U_(24) /**< (ISI_CFG1) Start of Frame Delay Position */ +#define ISI_CFG1_SFD_Msk (_U_(0xFF) << ISI_CFG1_SFD_Pos) /**< (ISI_CFG1) Start of Frame Delay Mask */ +#define ISI_CFG1_SFD(value) (ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)) +#define ISI_CFG1_Msk _U_(0xFFFF7FFC) /**< (ISI_CFG1) Register Mask */ + + +/* -------- ISI_CFG2 : (ISI Offset: 0x04) (R/W 32) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos _U_(0) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_VSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_VSIZE_Pos) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_VSIZE(value) (ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)) +#define ISI_CFG2_GS_MODE_Pos _U_(11) /**< (ISI_CFG2) Grayscale Pixel Format Mode Position */ +#define ISI_CFG2_GS_MODE_Msk (_U_(0x1) << ISI_CFG2_GS_MODE_Pos) /**< (ISI_CFG2) Grayscale Pixel Format Mode Mask */ +#define ISI_CFG2_GS_MODE(value) (ISI_CFG2_GS_MODE_Msk & ((value) << ISI_CFG2_GS_MODE_Pos)) +#define ISI_CFG2_RGB_MODE_Pos _U_(12) /**< (ISI_CFG2) RGB Input Mode Position */ +#define ISI_CFG2_RGB_MODE_Msk (_U_(0x1) << ISI_CFG2_RGB_MODE_Pos) /**< (ISI_CFG2) RGB Input Mode Mask */ +#define ISI_CFG2_RGB_MODE(value) (ISI_CFG2_RGB_MODE_Msk & ((value) << ISI_CFG2_RGB_MODE_Pos)) +#define ISI_CFG2_GRAYSCALE_Pos _U_(13) /**< (ISI_CFG2) Grayscale Mode Format Enable Position */ +#define ISI_CFG2_GRAYSCALE_Msk (_U_(0x1) << ISI_CFG2_GRAYSCALE_Pos) /**< (ISI_CFG2) Grayscale Mode Format Enable Mask */ +#define ISI_CFG2_GRAYSCALE(value) (ISI_CFG2_GRAYSCALE_Msk & ((value) << ISI_CFG2_GRAYSCALE_Pos)) +#define ISI_CFG2_RGB_SWAP_Pos _U_(14) /**< (ISI_CFG2) RGB Format Swap Mode Position */ +#define ISI_CFG2_RGB_SWAP_Msk (_U_(0x1) << ISI_CFG2_RGB_SWAP_Pos) /**< (ISI_CFG2) RGB Format Swap Mode Mask */ +#define ISI_CFG2_RGB_SWAP(value) (ISI_CFG2_RGB_SWAP_Msk & ((value) << ISI_CFG2_RGB_SWAP_Pos)) +#define ISI_CFG2_COL_SPACE_Pos _U_(15) /**< (ISI_CFG2) Color Space for the Image Data Position */ +#define ISI_CFG2_COL_SPACE_Msk (_U_(0x1) << ISI_CFG2_COL_SPACE_Pos) /**< (ISI_CFG2) Color Space for the Image Data Mask */ +#define ISI_CFG2_COL_SPACE(value) (ISI_CFG2_COL_SPACE_Msk & ((value) << ISI_CFG2_COL_SPACE_Pos)) +#define ISI_CFG2_IM_HSIZE_Pos _U_(16) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Position */ +#define ISI_CFG2_IM_HSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_HSIZE_Pos) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Mask */ +#define ISI_CFG2_IM_HSIZE(value) (ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)) +#define ISI_CFG2_YCC_SWAP_Pos _U_(28) /**< (ISI_CFG2) YCrCb Format Swap Mode Position */ +#define ISI_CFG2_YCC_SWAP_Msk (_U_(0x3) << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) YCrCb Format Swap Mode Mask */ +#define ISI_CFG2_YCC_SWAP(value) (ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)) +#define ISI_CFG2_YCC_SWAP_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_YCC_SWAP_DEFAULT (ISI_CFG2_YCC_SWAP_DEFAULT_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE1 (ISI_CFG2_YCC_SWAP_MODE1_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) Position */ +#define ISI_CFG2_YCC_SWAP_MODE2 (ISI_CFG2_YCC_SWAP_MODE2_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) Position */ +#define ISI_CFG2_YCC_SWAP_MODE3 (ISI_CFG2_YCC_SWAP_MODE3_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) Position */ +#define ISI_CFG2_RGB_CFG_Pos _U_(30) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Position */ +#define ISI_CFG2_RGB_CFG_Msk (_U_(0x3) << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Mask */ +#define ISI_CFG2_RGB_CFG(value) (ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)) +#define ISI_CFG2_RGB_CFG_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +#define ISI_CFG2_RGB_CFG_DEFAULT (ISI_CFG2_RGB_CFG_DEFAULT_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B Position */ +#define ISI_CFG2_RGB_CFG_MODE1 (ISI_CFG2_RGB_CFG_MODE1_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R Position */ +#define ISI_CFG2_RGB_CFG_MODE2 (ISI_CFG2_RGB_CFG_MODE2_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) Position */ +#define ISI_CFG2_RGB_CFG_MODE3 (ISI_CFG2_RGB_CFG_MODE3_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) Position */ +#define ISI_CFG2_Msk _U_(0xF7FFFFFF) /**< (ISI_CFG2) Register Mask */ + + +/* -------- ISI_PSIZE : (ISI Offset: 0x08) (R/W 32) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos _U_(0) /**< (ISI_PSIZE) Vertical Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_VSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_VSIZE_Pos) /**< (ISI_PSIZE) Vertical Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_VSIZE(value) (ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)) +#define ISI_PSIZE_PREV_HSIZE_Pos _U_(16) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Position */ +#define ISI_PSIZE_PREV_HSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_HSIZE_Pos) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Mask */ +#define ISI_PSIZE_PREV_HSIZE(value) (ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)) +#define ISI_PSIZE_Msk _U_(0x03FF03FF) /**< (ISI_PSIZE) Register Mask */ + + +/* -------- ISI_PDECF : (ISI Offset: 0x0C) (R/W 32) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos _U_(0) /**< (ISI_PDECF) Decimation Factor Position */ +#define ISI_PDECF_DEC_FACTOR_Msk (_U_(0xFF) << ISI_PDECF_DEC_FACTOR_Pos) /**< (ISI_PDECF) Decimation Factor Mask */ +#define ISI_PDECF_DEC_FACTOR(value) (ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)) +#define ISI_PDECF_Msk _U_(0x000000FF) /**< (ISI_PDECF) Register Mask */ + + +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos _U_(0) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_Y2R_SET0_C0_Msk (_U_(0xFF) << ISI_Y2R_SET0_C0_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_Y2R_SET0_C0(value) (ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)) +#define ISI_Y2R_SET0_C1_Pos _U_(8) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_Y2R_SET0_C1_Msk (_U_(0xFF) << ISI_Y2R_SET0_C1_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_Y2R_SET0_C1(value) (ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)) +#define ISI_Y2R_SET0_C2_Pos _U_(16) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_Y2R_SET0_C2_Msk (_U_(0xFF) << ISI_Y2R_SET0_C2_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_Y2R_SET0_C2(value) (ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)) +#define ISI_Y2R_SET0_C3_Pos _U_(24) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_Y2R_SET0_C3_Msk (_U_(0xFF) << ISI_Y2R_SET0_C3_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_Y2R_SET0_C3(value) (ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)) +#define ISI_Y2R_SET0_Msk _U_(0xFFFFFFFF) /**< (ISI_Y2R_SET0) Register Mask */ + + +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos _U_(0) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_Y2R_SET1_C4_Msk (_U_(0x1FF) << ISI_Y2R_SET1_C4_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_Y2R_SET1_C4(value) (ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)) +#define ISI_Y2R_SET1_Yoff_Pos _U_(12) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Position */ +#define ISI_Y2R_SET1_Yoff_Msk (_U_(0x1) << ISI_Y2R_SET1_Yoff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Mask */ +#define ISI_Y2R_SET1_Yoff(value) (ISI_Y2R_SET1_Yoff_Msk & ((value) << ISI_Y2R_SET1_Yoff_Pos)) +#define ISI_Y2R_SET1_Croff_Pos _U_(13) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Croff_Msk (_U_(0x1) << ISI_Y2R_SET1_Croff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Croff(value) (ISI_Y2R_SET1_Croff_Msk & ((value) << ISI_Y2R_SET1_Croff_Pos)) +#define ISI_Y2R_SET1_Cboff_Pos _U_(14) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Position */ +#define ISI_Y2R_SET1_Cboff_Msk (_U_(0x1) << ISI_Y2R_SET1_Cboff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Mask */ +#define ISI_Y2R_SET1_Cboff(value) (ISI_Y2R_SET1_Cboff_Msk & ((value) << ISI_Y2R_SET1_Cboff_Pos)) +#define ISI_Y2R_SET1_Msk _U_(0x000071FF) /**< (ISI_Y2R_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos _U_(0) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Position */ +#define ISI_R2Y_SET0_C0_Msk (_U_(0x7F) << ISI_R2Y_SET0_C0_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Mask */ +#define ISI_R2Y_SET0_C0(value) (ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)) +#define ISI_R2Y_SET0_C1_Pos _U_(8) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Position */ +#define ISI_R2Y_SET0_C1_Msk (_U_(0x7F) << ISI_R2Y_SET0_C1_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Mask */ +#define ISI_R2Y_SET0_C1(value) (ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)) +#define ISI_R2Y_SET0_C2_Pos _U_(16) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Position */ +#define ISI_R2Y_SET0_C2_Msk (_U_(0x7F) << ISI_R2Y_SET0_C2_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Mask */ +#define ISI_R2Y_SET0_C2(value) (ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)) +#define ISI_R2Y_SET0_Roff_Pos _U_(24) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Position */ +#define ISI_R2Y_SET0_Roff_Msk (_U_(0x1) << ISI_R2Y_SET0_Roff_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Mask */ +#define ISI_R2Y_SET0_Roff(value) (ISI_R2Y_SET0_Roff_Msk & ((value) << ISI_R2Y_SET0_Roff_Pos)) +#define ISI_R2Y_SET0_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET0) Register Mask */ + + +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos _U_(0) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Position */ +#define ISI_R2Y_SET1_C3_Msk (_U_(0x7F) << ISI_R2Y_SET1_C3_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Mask */ +#define ISI_R2Y_SET1_C3(value) (ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)) +#define ISI_R2Y_SET1_C4_Pos _U_(8) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Position */ +#define ISI_R2Y_SET1_C4_Msk (_U_(0x7F) << ISI_R2Y_SET1_C4_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Mask */ +#define ISI_R2Y_SET1_C4(value) (ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)) +#define ISI_R2Y_SET1_C5_Pos _U_(16) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Position */ +#define ISI_R2Y_SET1_C5_Msk (_U_(0x7F) << ISI_R2Y_SET1_C5_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Mask */ +#define ISI_R2Y_SET1_C5(value) (ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)) +#define ISI_R2Y_SET1_Goff_Pos _U_(24) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Position */ +#define ISI_R2Y_SET1_Goff_Msk (_U_(0x1) << ISI_R2Y_SET1_Goff_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Mask */ +#define ISI_R2Y_SET1_Goff(value) (ISI_R2Y_SET1_Goff_Msk & ((value) << ISI_R2Y_SET1_Goff_Pos)) +#define ISI_R2Y_SET1_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET1) Register Mask */ + + +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos _U_(0) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Position */ +#define ISI_R2Y_SET2_C6_Msk (_U_(0x7F) << ISI_R2Y_SET2_C6_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Mask */ +#define ISI_R2Y_SET2_C6(value) (ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)) +#define ISI_R2Y_SET2_C7_Pos _U_(8) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Position */ +#define ISI_R2Y_SET2_C7_Msk (_U_(0x7F) << ISI_R2Y_SET2_C7_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Mask */ +#define ISI_R2Y_SET2_C7(value) (ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)) +#define ISI_R2Y_SET2_C8_Pos _U_(16) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Position */ +#define ISI_R2Y_SET2_C8_Msk (_U_(0x7F) << ISI_R2Y_SET2_C8_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Mask */ +#define ISI_R2Y_SET2_C8(value) (ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)) +#define ISI_R2Y_SET2_Boff_Pos _U_(24) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Position */ +#define ISI_R2Y_SET2_Boff_Msk (_U_(0x1) << ISI_R2Y_SET2_Boff_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Mask */ +#define ISI_R2Y_SET2_Boff(value) (ISI_R2Y_SET2_Boff_Msk & ((value) << ISI_R2Y_SET2_Boff_Pos)) +#define ISI_R2Y_SET2_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET2) Register Mask */ + + +/* -------- ISI_CR : (ISI Offset: 0x24) ( /W 32) ISI Control Register -------- */ +#define ISI_CR_ISI_EN_Pos _U_(0) /**< (ISI_CR) ISI Module Enable Request Position */ +#define ISI_CR_ISI_EN_Msk (_U_(0x1) << ISI_CR_ISI_EN_Pos) /**< (ISI_CR) ISI Module Enable Request Mask */ +#define ISI_CR_ISI_EN(value) (ISI_CR_ISI_EN_Msk & ((value) << ISI_CR_ISI_EN_Pos)) +#define ISI_CR_ISI_DIS_Pos _U_(1) /**< (ISI_CR) ISI Module Disable Request Position */ +#define ISI_CR_ISI_DIS_Msk (_U_(0x1) << ISI_CR_ISI_DIS_Pos) /**< (ISI_CR) ISI Module Disable Request Mask */ +#define ISI_CR_ISI_DIS(value) (ISI_CR_ISI_DIS_Msk & ((value) << ISI_CR_ISI_DIS_Pos)) +#define ISI_CR_ISI_SRST_Pos _U_(2) /**< (ISI_CR) ISI Software Reset Request Position */ +#define ISI_CR_ISI_SRST_Msk (_U_(0x1) << ISI_CR_ISI_SRST_Pos) /**< (ISI_CR) ISI Software Reset Request Mask */ +#define ISI_CR_ISI_SRST(value) (ISI_CR_ISI_SRST_Msk & ((value) << ISI_CR_ISI_SRST_Pos)) +#define ISI_CR_ISI_CDC_Pos _U_(8) /**< (ISI_CR) ISI Codec Request Position */ +#define ISI_CR_ISI_CDC_Msk (_U_(0x1) << ISI_CR_ISI_CDC_Pos) /**< (ISI_CR) ISI Codec Request Mask */ +#define ISI_CR_ISI_CDC(value) (ISI_CR_ISI_CDC_Msk & ((value) << ISI_CR_ISI_CDC_Pos)) +#define ISI_CR_Msk _U_(0x00000107) /**< (ISI_CR) Register Mask */ + + +/* -------- ISI_SR : (ISI Offset: 0x28) ( R/ 32) ISI Status Register -------- */ +#define ISI_SR_ENABLE_Pos _U_(0) /**< (ISI_SR) Module Enable Position */ +#define ISI_SR_ENABLE_Msk (_U_(0x1) << ISI_SR_ENABLE_Pos) /**< (ISI_SR) Module Enable Mask */ +#define ISI_SR_ENABLE(value) (ISI_SR_ENABLE_Msk & ((value) << ISI_SR_ENABLE_Pos)) +#define ISI_SR_DIS_DONE_Pos _U_(1) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Position */ +#define ISI_SR_DIS_DONE_Msk (_U_(0x1) << ISI_SR_DIS_DONE_Pos) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Mask */ +#define ISI_SR_DIS_DONE(value) (ISI_SR_DIS_DONE_Msk & ((value) << ISI_SR_DIS_DONE_Pos)) +#define ISI_SR_SRST_Pos _U_(2) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Position */ +#define ISI_SR_SRST_Msk (_U_(0x1) << ISI_SR_SRST_Pos) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Mask */ +#define ISI_SR_SRST(value) (ISI_SR_SRST_Msk & ((value) << ISI_SR_SRST_Pos)) +#define ISI_SR_CDC_PND_Pos _U_(8) /**< (ISI_SR) Pending Codec Request Position */ +#define ISI_SR_CDC_PND_Msk (_U_(0x1) << ISI_SR_CDC_PND_Pos) /**< (ISI_SR) Pending Codec Request Mask */ +#define ISI_SR_CDC_PND(value) (ISI_SR_CDC_PND_Msk & ((value) << ISI_SR_CDC_PND_Pos)) +#define ISI_SR_VSYNC_Pos _U_(10) /**< (ISI_SR) Vertical Synchronization (cleared on read) Position */ +#define ISI_SR_VSYNC_Msk (_U_(0x1) << ISI_SR_VSYNC_Pos) /**< (ISI_SR) Vertical Synchronization (cleared on read) Mask */ +#define ISI_SR_VSYNC(value) (ISI_SR_VSYNC_Msk & ((value) << ISI_SR_VSYNC_Pos)) +#define ISI_SR_PXFR_DONE_Pos _U_(16) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_PXFR_DONE_Msk (_U_(0x1) << ISI_SR_PXFR_DONE_Pos) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_PXFR_DONE(value) (ISI_SR_PXFR_DONE_Msk & ((value) << ISI_SR_PXFR_DONE_Pos)) +#define ISI_SR_CXFR_DONE_Pos _U_(17) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Position */ +#define ISI_SR_CXFR_DONE_Msk (_U_(0x1) << ISI_SR_CXFR_DONE_Pos) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Mask */ +#define ISI_SR_CXFR_DONE(value) (ISI_SR_CXFR_DONE_Msk & ((value) << ISI_SR_CXFR_DONE_Pos)) +#define ISI_SR_SIP_Pos _U_(19) /**< (ISI_SR) Synchronization in Progress Position */ +#define ISI_SR_SIP_Msk (_U_(0x1) << ISI_SR_SIP_Pos) /**< (ISI_SR) Synchronization in Progress Mask */ +#define ISI_SR_SIP(value) (ISI_SR_SIP_Msk & ((value) << ISI_SR_SIP_Pos)) +#define ISI_SR_P_OVR_Pos _U_(24) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Position */ +#define ISI_SR_P_OVR_Msk (_U_(0x1) << ISI_SR_P_OVR_Pos) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_P_OVR(value) (ISI_SR_P_OVR_Msk & ((value) << ISI_SR_P_OVR_Pos)) +#define ISI_SR_C_OVR_Pos _U_(25) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Position */ +#define ISI_SR_C_OVR_Msk (_U_(0x1) << ISI_SR_C_OVR_Pos) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Mask */ +#define ISI_SR_C_OVR(value) (ISI_SR_C_OVR_Msk & ((value) << ISI_SR_C_OVR_Pos)) +#define ISI_SR_CRC_ERR_Pos _U_(26) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Position */ +#define ISI_SR_CRC_ERR_Msk (_U_(0x1) << ISI_SR_CRC_ERR_Pos) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Mask */ +#define ISI_SR_CRC_ERR(value) (ISI_SR_CRC_ERR_Msk & ((value) << ISI_SR_CRC_ERR_Pos)) +#define ISI_SR_FR_OVR_Pos _U_(27) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Position */ +#define ISI_SR_FR_OVR_Msk (_U_(0x1) << ISI_SR_FR_OVR_Pos) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Mask */ +#define ISI_SR_FR_OVR(value) (ISI_SR_FR_OVR_Msk & ((value) << ISI_SR_FR_OVR_Pos)) +#define ISI_SR_Msk _U_(0x0F0B0507) /**< (ISI_SR) Register Mask */ + + +/* -------- ISI_IER : (ISI Offset: 0x2C) ( /W 32) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE_Pos _U_(1) /**< (ISI_IER) Disable Done Interrupt Enable Position */ +#define ISI_IER_DIS_DONE_Msk (_U_(0x1) << ISI_IER_DIS_DONE_Pos) /**< (ISI_IER) Disable Done Interrupt Enable Mask */ +#define ISI_IER_DIS_DONE(value) (ISI_IER_DIS_DONE_Msk & ((value) << ISI_IER_DIS_DONE_Pos)) +#define ISI_IER_SRST_Pos _U_(2) /**< (ISI_IER) Software Reset Interrupt Enable Position */ +#define ISI_IER_SRST_Msk (_U_(0x1) << ISI_IER_SRST_Pos) /**< (ISI_IER) Software Reset Interrupt Enable Mask */ +#define ISI_IER_SRST(value) (ISI_IER_SRST_Msk & ((value) << ISI_IER_SRST_Pos)) +#define ISI_IER_VSYNC_Pos _U_(10) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Position */ +#define ISI_IER_VSYNC_Msk (_U_(0x1) << ISI_IER_VSYNC_Pos) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Mask */ +#define ISI_IER_VSYNC(value) (ISI_IER_VSYNC_Msk & ((value) << ISI_IER_VSYNC_Pos)) +#define ISI_IER_PXFR_DONE_Pos _U_(16) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_PXFR_DONE_Msk (_U_(0x1) << ISI_IER_PXFR_DONE_Pos) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_PXFR_DONE(value) (ISI_IER_PXFR_DONE_Msk & ((value) << ISI_IER_PXFR_DONE_Pos)) +#define ISI_IER_CXFR_DONE_Pos _U_(17) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Position */ +#define ISI_IER_CXFR_DONE_Msk (_U_(0x1) << ISI_IER_CXFR_DONE_Pos) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Mask */ +#define ISI_IER_CXFR_DONE(value) (ISI_IER_CXFR_DONE_Msk & ((value) << ISI_IER_CXFR_DONE_Pos)) +#define ISI_IER_P_OVR_Pos _U_(24) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_P_OVR_Msk (_U_(0x1) << ISI_IER_P_OVR_Pos) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_P_OVR(value) (ISI_IER_P_OVR_Msk & ((value) << ISI_IER_P_OVR_Pos)) +#define ISI_IER_C_OVR_Pos _U_(25) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Position */ +#define ISI_IER_C_OVR_Msk (_U_(0x1) << ISI_IER_C_OVR_Pos) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Mask */ +#define ISI_IER_C_OVR(value) (ISI_IER_C_OVR_Msk & ((value) << ISI_IER_C_OVR_Pos)) +#define ISI_IER_CRC_ERR_Pos _U_(26) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Position */ +#define ISI_IER_CRC_ERR_Msk (_U_(0x1) << ISI_IER_CRC_ERR_Pos) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Mask */ +#define ISI_IER_CRC_ERR(value) (ISI_IER_CRC_ERR_Msk & ((value) << ISI_IER_CRC_ERR_Pos)) +#define ISI_IER_FR_OVR_Pos _U_(27) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Position */ +#define ISI_IER_FR_OVR_Msk (_U_(0x1) << ISI_IER_FR_OVR_Pos) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Mask */ +#define ISI_IER_FR_OVR(value) (ISI_IER_FR_OVR_Msk & ((value) << ISI_IER_FR_OVR_Pos)) +#define ISI_IER_Msk _U_(0x0F030406) /**< (ISI_IER) Register Mask */ + + +/* -------- ISI_IDR : (ISI Offset: 0x30) ( /W 32) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE_Pos _U_(1) /**< (ISI_IDR) Disable Done Interrupt Disable Position */ +#define ISI_IDR_DIS_DONE_Msk (_U_(0x1) << ISI_IDR_DIS_DONE_Pos) /**< (ISI_IDR) Disable Done Interrupt Disable Mask */ +#define ISI_IDR_DIS_DONE(value) (ISI_IDR_DIS_DONE_Msk & ((value) << ISI_IDR_DIS_DONE_Pos)) +#define ISI_IDR_SRST_Pos _U_(2) /**< (ISI_IDR) Software Reset Interrupt Disable Position */ +#define ISI_IDR_SRST_Msk (_U_(0x1) << ISI_IDR_SRST_Pos) /**< (ISI_IDR) Software Reset Interrupt Disable Mask */ +#define ISI_IDR_SRST(value) (ISI_IDR_SRST_Msk & ((value) << ISI_IDR_SRST_Pos)) +#define ISI_IDR_VSYNC_Pos _U_(10) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Position */ +#define ISI_IDR_VSYNC_Msk (_U_(0x1) << ISI_IDR_VSYNC_Pos) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Mask */ +#define ISI_IDR_VSYNC(value) (ISI_IDR_VSYNC_Msk & ((value) << ISI_IDR_VSYNC_Pos)) +#define ISI_IDR_PXFR_DONE_Pos _U_(16) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_PXFR_DONE_Msk (_U_(0x1) << ISI_IDR_PXFR_DONE_Pos) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_PXFR_DONE(value) (ISI_IDR_PXFR_DONE_Msk & ((value) << ISI_IDR_PXFR_DONE_Pos)) +#define ISI_IDR_CXFR_DONE_Pos _U_(17) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Position */ +#define ISI_IDR_CXFR_DONE_Msk (_U_(0x1) << ISI_IDR_CXFR_DONE_Pos) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Mask */ +#define ISI_IDR_CXFR_DONE(value) (ISI_IDR_CXFR_DONE_Msk & ((value) << ISI_IDR_CXFR_DONE_Pos)) +#define ISI_IDR_P_OVR_Pos _U_(24) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_P_OVR_Msk (_U_(0x1) << ISI_IDR_P_OVR_Pos) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_P_OVR(value) (ISI_IDR_P_OVR_Msk & ((value) << ISI_IDR_P_OVR_Pos)) +#define ISI_IDR_C_OVR_Pos _U_(25) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Position */ +#define ISI_IDR_C_OVR_Msk (_U_(0x1) << ISI_IDR_C_OVR_Pos) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Mask */ +#define ISI_IDR_C_OVR(value) (ISI_IDR_C_OVR_Msk & ((value) << ISI_IDR_C_OVR_Pos)) +#define ISI_IDR_CRC_ERR_Pos _U_(26) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Position */ +#define ISI_IDR_CRC_ERR_Msk (_U_(0x1) << ISI_IDR_CRC_ERR_Pos) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Mask */ +#define ISI_IDR_CRC_ERR(value) (ISI_IDR_CRC_ERR_Msk & ((value) << ISI_IDR_CRC_ERR_Pos)) +#define ISI_IDR_FR_OVR_Pos _U_(27) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Position */ +#define ISI_IDR_FR_OVR_Msk (_U_(0x1) << ISI_IDR_FR_OVR_Pos) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Mask */ +#define ISI_IDR_FR_OVR(value) (ISI_IDR_FR_OVR_Msk & ((value) << ISI_IDR_FR_OVR_Pos)) +#define ISI_IDR_Msk _U_(0x0F030406) /**< (ISI_IDR) Register Mask */ + + +/* -------- ISI_IMR : (ISI Offset: 0x34) ( R/ 32) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE_Pos _U_(1) /**< (ISI_IMR) Module Disable Operation Completed Position */ +#define ISI_IMR_DIS_DONE_Msk (_U_(0x1) << ISI_IMR_DIS_DONE_Pos) /**< (ISI_IMR) Module Disable Operation Completed Mask */ +#define ISI_IMR_DIS_DONE(value) (ISI_IMR_DIS_DONE_Msk & ((value) << ISI_IMR_DIS_DONE_Pos)) +#define ISI_IMR_SRST_Pos _U_(2) /**< (ISI_IMR) Software Reset Completed Position */ +#define ISI_IMR_SRST_Msk (_U_(0x1) << ISI_IMR_SRST_Pos) /**< (ISI_IMR) Software Reset Completed Mask */ +#define ISI_IMR_SRST(value) (ISI_IMR_SRST_Msk & ((value) << ISI_IMR_SRST_Pos)) +#define ISI_IMR_VSYNC_Pos _U_(10) /**< (ISI_IMR) Vertical Synchronization Position */ +#define ISI_IMR_VSYNC_Msk (_U_(0x1) << ISI_IMR_VSYNC_Pos) /**< (ISI_IMR) Vertical Synchronization Mask */ +#define ISI_IMR_VSYNC(value) (ISI_IMR_VSYNC_Msk & ((value) << ISI_IMR_VSYNC_Pos)) +#define ISI_IMR_PXFR_DONE_Pos _U_(16) /**< (ISI_IMR) Preview DMA Transfer Completed Position */ +#define ISI_IMR_PXFR_DONE_Msk (_U_(0x1) << ISI_IMR_PXFR_DONE_Pos) /**< (ISI_IMR) Preview DMA Transfer Completed Mask */ +#define ISI_IMR_PXFR_DONE(value) (ISI_IMR_PXFR_DONE_Msk & ((value) << ISI_IMR_PXFR_DONE_Pos)) +#define ISI_IMR_CXFR_DONE_Pos _U_(17) /**< (ISI_IMR) Codec DMA Transfer Completed Position */ +#define ISI_IMR_CXFR_DONE_Msk (_U_(0x1) << ISI_IMR_CXFR_DONE_Pos) /**< (ISI_IMR) Codec DMA Transfer Completed Mask */ +#define ISI_IMR_CXFR_DONE(value) (ISI_IMR_CXFR_DONE_Msk & ((value) << ISI_IMR_CXFR_DONE_Pos)) +#define ISI_IMR_P_OVR_Pos _U_(24) /**< (ISI_IMR) Preview FIFO Overflow Position */ +#define ISI_IMR_P_OVR_Msk (_U_(0x1) << ISI_IMR_P_OVR_Pos) /**< (ISI_IMR) Preview FIFO Overflow Mask */ +#define ISI_IMR_P_OVR(value) (ISI_IMR_P_OVR_Msk & ((value) << ISI_IMR_P_OVR_Pos)) +#define ISI_IMR_C_OVR_Pos _U_(25) /**< (ISI_IMR) Codec FIFO Overflow Position */ +#define ISI_IMR_C_OVR_Msk (_U_(0x1) << ISI_IMR_C_OVR_Pos) /**< (ISI_IMR) Codec FIFO Overflow Mask */ +#define ISI_IMR_C_OVR(value) (ISI_IMR_C_OVR_Msk & ((value) << ISI_IMR_C_OVR_Pos)) +#define ISI_IMR_CRC_ERR_Pos _U_(26) /**< (ISI_IMR) CRC Synchronization Error Position */ +#define ISI_IMR_CRC_ERR_Msk (_U_(0x1) << ISI_IMR_CRC_ERR_Pos) /**< (ISI_IMR) CRC Synchronization Error Mask */ +#define ISI_IMR_CRC_ERR(value) (ISI_IMR_CRC_ERR_Msk & ((value) << ISI_IMR_CRC_ERR_Pos)) +#define ISI_IMR_FR_OVR_Pos _U_(27) /**< (ISI_IMR) Frame Rate Overrun Position */ +#define ISI_IMR_FR_OVR_Msk (_U_(0x1) << ISI_IMR_FR_OVR_Pos) /**< (ISI_IMR) Frame Rate Overrun Mask */ +#define ISI_IMR_FR_OVR(value) (ISI_IMR_FR_OVR_Msk & ((value) << ISI_IMR_FR_OVR_Pos)) +#define ISI_IMR_Msk _U_(0x0F030406) /**< (ISI_IMR) Register Mask */ + + +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) ( /W 32) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN_Pos _U_(0) /**< (ISI_DMA_CHER) Preview Channel Enable Position */ +#define ISI_DMA_CHER_P_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_P_CH_EN_Pos) /**< (ISI_DMA_CHER) Preview Channel Enable Mask */ +#define ISI_DMA_CHER_P_CH_EN(value) (ISI_DMA_CHER_P_CH_EN_Msk & ((value) << ISI_DMA_CHER_P_CH_EN_Pos)) +#define ISI_DMA_CHER_C_CH_EN_Pos _U_(1) /**< (ISI_DMA_CHER) Codec Channel Enable Position */ +#define ISI_DMA_CHER_C_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_C_CH_EN_Pos) /**< (ISI_DMA_CHER) Codec Channel Enable Mask */ +#define ISI_DMA_CHER_C_CH_EN(value) (ISI_DMA_CHER_C_CH_EN_Msk & ((value) << ISI_DMA_CHER_C_CH_EN_Pos)) +#define ISI_DMA_CHER_Msk _U_(0x00000003) /**< (ISI_DMA_CHER) Register Mask */ + + +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) ( /W 32) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS_Pos _U_(0) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Position */ +#define ISI_DMA_CHDR_P_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_P_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Mask */ +#define ISI_DMA_CHDR_P_CH_DIS(value) (ISI_DMA_CHDR_P_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_P_CH_DIS_Pos)) +#define ISI_DMA_CHDR_C_CH_DIS_Pos _U_(1) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Position */ +#define ISI_DMA_CHDR_C_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_C_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Mask */ +#define ISI_DMA_CHDR_C_CH_DIS(value) (ISI_DMA_CHDR_C_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_C_CH_DIS_Pos)) +#define ISI_DMA_CHDR_Msk _U_(0x00000003) /**< (ISI_DMA_CHDR) Register Mask */ + + +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) ( R/ 32) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S_Pos _U_(0) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Position */ +#define ISI_DMA_CHSR_P_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_P_CH_S_Pos) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Mask */ +#define ISI_DMA_CHSR_P_CH_S(value) (ISI_DMA_CHSR_P_CH_S_Msk & ((value) << ISI_DMA_CHSR_P_CH_S_Pos)) +#define ISI_DMA_CHSR_C_CH_S_Pos _U_(1) /**< (ISI_DMA_CHSR) Code DMA Channel Status Position */ +#define ISI_DMA_CHSR_C_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_C_CH_S_Pos) /**< (ISI_DMA_CHSR) Code DMA Channel Status Mask */ +#define ISI_DMA_CHSR_C_CH_S(value) (ISI_DMA_CHSR_C_CH_S_Msk & ((value) << ISI_DMA_CHSR_C_CH_S_Pos)) +#define ISI_DMA_CHSR_Msk _U_(0x00000003) /**< (ISI_DMA_CHSR) Register Mask */ + + +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) (R/W 32) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos _U_(2) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Position */ +#define ISI_DMA_P_ADDR_P_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Mask */ +#define ISI_DMA_P_ADDR_P_ADDR(value) (ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)) +#define ISI_DMA_P_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_ADDR) Register Mask */ + + +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) (R/W 32) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH_Pos _U_(0) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_P_CTRL_P_FETCH_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_FETCH_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_FETCH(value) (ISI_DMA_P_CTRL_P_FETCH_Msk & ((value) << ISI_DMA_P_CTRL_P_FETCH_Pos)) +#define ISI_DMA_P_CTRL_P_WB_Pos _U_(1) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_P_CTRL_P_WB_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_WB_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_P_CTRL_P_WB(value) (ISI_DMA_P_CTRL_P_WB_Msk & ((value) << ISI_DMA_P_CTRL_P_WB_Pos)) +#define ISI_DMA_P_CTRL_P_IEN_Pos _U_(2) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_P_CTRL_P_IEN_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_IEN_Pos) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_P_CTRL_P_IEN(value) (ISI_DMA_P_CTRL_P_IEN_Msk & ((value) << ISI_DMA_P_CTRL_P_IEN_Pos)) +#define ISI_DMA_P_CTRL_P_DONE_Pos _U_(3) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Position */ +#define ISI_DMA_P_CTRL_P_DONE_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_DONE_Pos) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Mask */ +#define ISI_DMA_P_CTRL_P_DONE(value) (ISI_DMA_P_CTRL_P_DONE_Msk & ((value) << ISI_DMA_P_CTRL_P_DONE_Pos)) +#define ISI_DMA_P_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_P_CTRL) Register Mask */ + + +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) (R/W 32) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos _U_(2) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Position */ +#define ISI_DMA_P_DSCR_P_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Mask */ +#define ISI_DMA_P_DSCR_P_DSCR(value) (ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)) +#define ISI_DMA_P_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_DSCR) Register Mask */ + + +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) (R/W 32) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos _U_(2) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Position */ +#define ISI_DMA_C_ADDR_C_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Mask */ +#define ISI_DMA_C_ADDR_C_ADDR(value) (ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)) +#define ISI_DMA_C_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_ADDR) Register Mask */ + + +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) (R/W 32) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH_Pos _U_(0) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Position */ +#define ISI_DMA_C_CTRL_C_FETCH_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_FETCH_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_FETCH(value) (ISI_DMA_C_CTRL_C_FETCH_Msk & ((value) << ISI_DMA_C_CTRL_C_FETCH_Pos)) +#define ISI_DMA_C_CTRL_C_WB_Pos _U_(1) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Position */ +#define ISI_DMA_C_CTRL_C_WB_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_WB_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Mask */ +#define ISI_DMA_C_CTRL_C_WB(value) (ISI_DMA_C_CTRL_C_WB_Msk & ((value) << ISI_DMA_C_CTRL_C_WB_Pos)) +#define ISI_DMA_C_CTRL_C_IEN_Pos _U_(2) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Position */ +#define ISI_DMA_C_CTRL_C_IEN_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_IEN_Pos) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Mask */ +#define ISI_DMA_C_CTRL_C_IEN(value) (ISI_DMA_C_CTRL_C_IEN_Msk & ((value) << ISI_DMA_C_CTRL_C_IEN_Pos)) +#define ISI_DMA_C_CTRL_C_DONE_Pos _U_(3) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Position */ +#define ISI_DMA_C_CTRL_C_DONE_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_DONE_Pos) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Mask */ +#define ISI_DMA_C_CTRL_C_DONE(value) (ISI_DMA_C_CTRL_C_DONE_Msk & ((value) << ISI_DMA_C_CTRL_C_DONE_Pos)) +#define ISI_DMA_C_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_C_CTRL) Register Mask */ + + +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) (R/W 32) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos _U_(2) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Position */ +#define ISI_DMA_C_DSCR_C_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Mask */ +#define ISI_DMA_C_DSCR_C_DSCR(value) (ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)) +#define ISI_DMA_C_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_DSCR) Register Mask */ + + +/* -------- ISI_WPMR : (ISI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN_Pos _U_(0) /**< (ISI_WPMR) Write Protection Enable Position */ +#define ISI_WPMR_WPEN_Msk (_U_(0x1) << ISI_WPMR_WPEN_Pos) /**< (ISI_WPMR) Write Protection Enable Mask */ +#define ISI_WPMR_WPEN(value) (ISI_WPMR_WPEN_Msk & ((value) << ISI_WPMR_WPEN_Pos)) +#define ISI_WPMR_WPKEY_Pos _U_(8) /**< (ISI_WPMR) Write Protection Key Password Position */ +#define ISI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Write Protection Key Password Mask */ +#define ISI_WPMR_WPKEY(value) (ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)) +#define ISI_WPMR_WPKEY_PASSWD_Val _U_(0x495349) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define ISI_WPMR_WPKEY_PASSWD (ISI_WPMR_WPKEY_PASSWD_Val << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define ISI_WPMR_Msk _U_(0xFFFFFF01) /**< (ISI_WPMR) Register Mask */ + + +/* -------- ISI_WPSR : (ISI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS_Pos _U_(0) /**< (ISI_WPSR) Write Protection Violation Status Position */ +#define ISI_WPSR_WPVS_Msk (_U_(0x1) << ISI_WPSR_WPVS_Pos) /**< (ISI_WPSR) Write Protection Violation Status Mask */ +#define ISI_WPSR_WPVS(value) (ISI_WPSR_WPVS_Msk & ((value) << ISI_WPSR_WPVS_Pos)) +#define ISI_WPSR_WPVSRC_Pos _U_(8) /**< (ISI_WPSR) Write Protection Violation Source Position */ +#define ISI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << ISI_WPSR_WPVSRC_Pos) /**< (ISI_WPSR) Write Protection Violation Source Mask */ +#define ISI_WPSR_WPVSRC(value) (ISI_WPSR_WPVSRC_Msk & ((value) << ISI_WPSR_WPVSRC_Pos)) +#define ISI_WPSR_Msk _U_(0x00FFFF01) /**< (ISI_WPSR) Register Mask */ + + +/** \brief ISI register offsets definitions */ +#define ISI_CFG1_REG_OFST (0x00) /**< (ISI_CFG1) ISI Configuration 1 Register Offset */ +#define ISI_CFG2_REG_OFST (0x04) /**< (ISI_CFG2) ISI Configuration 2 Register Offset */ +#define ISI_PSIZE_REG_OFST (0x08) /**< (ISI_PSIZE) ISI Preview Size Register Offset */ +#define ISI_PDECF_REG_OFST (0x0C) /**< (ISI_PDECF) ISI Preview Decimation Factor Register Offset */ +#define ISI_Y2R_SET0_REG_OFST (0x10) /**< (ISI_Y2R_SET0) ISI Color Space Conversion YCrCb To RGB Set 0 Register Offset */ +#define ISI_Y2R_SET1_REG_OFST (0x14) /**< (ISI_Y2R_SET1) ISI Color Space Conversion YCrCb To RGB Set 1 Register Offset */ +#define ISI_R2Y_SET0_REG_OFST (0x18) /**< (ISI_R2Y_SET0) ISI Color Space Conversion RGB To YCrCb Set 0 Register Offset */ +#define ISI_R2Y_SET1_REG_OFST (0x1C) /**< (ISI_R2Y_SET1) ISI Color Space Conversion RGB To YCrCb Set 1 Register Offset */ +#define ISI_R2Y_SET2_REG_OFST (0x20) /**< (ISI_R2Y_SET2) ISI Color Space Conversion RGB To YCrCb Set 2 Register Offset */ +#define ISI_CR_REG_OFST (0x24) /**< (ISI_CR) ISI Control Register Offset */ +#define ISI_SR_REG_OFST (0x28) /**< (ISI_SR) ISI Status Register Offset */ +#define ISI_IER_REG_OFST (0x2C) /**< (ISI_IER) ISI Interrupt Enable Register Offset */ +#define ISI_IDR_REG_OFST (0x30) /**< (ISI_IDR) ISI Interrupt Disable Register Offset */ +#define ISI_IMR_REG_OFST (0x34) /**< (ISI_IMR) ISI Interrupt Mask Register Offset */ +#define ISI_DMA_CHER_REG_OFST (0x38) /**< (ISI_DMA_CHER) DMA Channel Enable Register Offset */ +#define ISI_DMA_CHDR_REG_OFST (0x3C) /**< (ISI_DMA_CHDR) DMA Channel Disable Register Offset */ +#define ISI_DMA_CHSR_REG_OFST (0x40) /**< (ISI_DMA_CHSR) DMA Channel Status Register Offset */ +#define ISI_DMA_P_ADDR_REG_OFST (0x44) /**< (ISI_DMA_P_ADDR) DMA Preview Base Address Register Offset */ +#define ISI_DMA_P_CTRL_REG_OFST (0x48) /**< (ISI_DMA_P_CTRL) DMA Preview Control Register Offset */ +#define ISI_DMA_P_DSCR_REG_OFST (0x4C) /**< (ISI_DMA_P_DSCR) DMA Preview Descriptor Address Register Offset */ +#define ISI_DMA_C_ADDR_REG_OFST (0x50) /**< (ISI_DMA_C_ADDR) DMA Codec Base Address Register Offset */ +#define ISI_DMA_C_CTRL_REG_OFST (0x54) /**< (ISI_DMA_C_CTRL) DMA Codec Control Register Offset */ +#define ISI_DMA_C_DSCR_REG_OFST (0x58) /**< (ISI_DMA_C_DSCR) DMA Codec Descriptor Address Register Offset */ +#define ISI_WPMR_REG_OFST (0xE4) /**< (ISI_WPMR) Write Protection Mode Register Offset */ +#define ISI_WPSR_REG_OFST (0xE8) /**< (ISI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief ISI register API structure */ +typedef struct +{ + __IO uint32_t ISI_CFG1; /**< Offset: 0x00 (R/W 32) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< Offset: 0x04 (R/W 32) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< Offset: 0x08 (R/W 32) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< Offset: 0x0C (R/W 32) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< Offset: 0x10 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< Offset: 0x14 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< Offset: 0x18 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< Offset: 0x1C (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< Offset: 0x20 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< Offset: 0x24 ( /W 32) ISI Control Register */ + __I uint32_t ISI_SR; /**< Offset: 0x28 (R/ 32) ISI Status Register */ + __O uint32_t ISI_IER; /**< Offset: 0x2C ( /W 32) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< Offset: 0x30 ( /W 32) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< Offset: 0x34 (R/ 32) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< Offset: 0x38 ( /W 32) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< Offset: 0x3C ( /W 32) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< Offset: 0x40 (R/ 32) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< Offset: 0x44 (R/W 32) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< Offset: 0x48 (R/W 32) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< Offset: 0x4C (R/W 32) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< Offset: 0x50 (R/W 32) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< Offset: 0x54 (R/W 32) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< Offset: 0x58 (R/W 32) DMA Codec Descriptor Address Register */ + __I uint8_t Reserved1[0x88]; + __IO uint32_t ISI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} isi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_ISI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/matrix.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/matrix.h new file mode 100644 index 00000000..d99186cb --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/matrix.h @@ -0,0 +1,310 @@ +/** + * \brief Component description for MATRIX + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_MATRIX_COMPONENT_H_ +#define _SAME70_MATRIX_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR MATRIX */ +/* ************************************************************************** */ + +/* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos _U_(0) /**< (MATRIX_PRAS) Master 0 Priority Position */ +#define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */ +#define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)) +#define MATRIX_PRAS_M1PR_Pos _U_(4) /**< (MATRIX_PRAS) Master 1 Priority Position */ +#define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */ +#define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)) +#define MATRIX_PRAS_M2PR_Pos _U_(8) /**< (MATRIX_PRAS) Master 2 Priority Position */ +#define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */ +#define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)) +#define MATRIX_PRAS_M3PR_Pos _U_(12) /**< (MATRIX_PRAS) Master 3 Priority Position */ +#define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */ +#define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)) +#define MATRIX_PRAS_M4PR_Pos _U_(16) /**< (MATRIX_PRAS) Master 4 Priority Position */ +#define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */ +#define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)) +#define MATRIX_PRAS_M5PR_Pos _U_(20) /**< (MATRIX_PRAS) Master 5 Priority Position */ +#define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */ +#define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)) +#define MATRIX_PRAS_M6PR_Pos _U_(24) /**< (MATRIX_PRAS) Master 6 Priority Position */ +#define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */ +#define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)) +#define MATRIX_PRAS_Msk _U_(0x03333333) /**< (MATRIX_PRAS) Register Mask */ + + +/* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos _U_(0) /**< (MATRIX_PRBS) Master 8 Priority Position */ +#define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */ +#define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)) +#define MATRIX_PRBS_M9PR_Pos _U_(4) /**< (MATRIX_PRBS) Master 9 Priority Position */ +#define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */ +#define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)) +#define MATRIX_PRBS_M10PR_Pos _U_(8) /**< (MATRIX_PRBS) Master 10 Priority Position */ +#define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */ +#define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)) +#define MATRIX_PRBS_M11PR_Pos _U_(12) /**< (MATRIX_PRBS) Master 11 Priority Position */ +#define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */ +#define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)) +#define MATRIX_PRBS_M12PR_Pos _U_(16) /**< (MATRIX_PRBS) Master 12 Priority Position */ +#define MATRIX_PRBS_M12PR_Msk (_U_(0x3) << MATRIX_PRBS_M12PR_Pos) /**< (MATRIX_PRBS) Master 12 Priority Mask */ +#define MATRIX_PRBS_M12PR(value) (MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)) +#define MATRIX_PRBS_Msk _U_(0x00033333) /**< (MATRIX_PRBS) Register Mask */ + + +/* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */ +#define MATRIX_MCFG_ULBT_Pos _U_(0) /**< (MATRIX_MCFG) Undefined Length Burst Type Position */ +#define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */ +#define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */ +#define MATRIX_MCFG_Msk _U_(0x00000007) /**< (MATRIX_MCFG) Register Mask */ + + +/* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos _U_(0) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */ +#define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */ +#define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos _U_(16) /**< (MATRIX_SCFG) Default Master Type Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos _U_(18) /**< (MATRIX_SCFG) Fixed Default Master Position */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)) +#define MATRIX_SCFG_Msk _U_(0x003F01FF) /**< (MATRIX_SCFG) Register Mask */ + + +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0_Pos _U_(0) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */ +#define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */ +#define MATRIX_MRCR_RCB0(value) (MATRIX_MRCR_RCB0_Msk & ((value) << MATRIX_MRCR_RCB0_Pos)) +#define MATRIX_MRCR_RCB1_Pos _U_(1) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */ +#define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */ +#define MATRIX_MRCR_RCB1(value) (MATRIX_MRCR_RCB1_Msk & ((value) << MATRIX_MRCR_RCB1_Pos)) +#define MATRIX_MRCR_RCB2_Pos _U_(2) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */ +#define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */ +#define MATRIX_MRCR_RCB2(value) (MATRIX_MRCR_RCB2_Msk & ((value) << MATRIX_MRCR_RCB2_Pos)) +#define MATRIX_MRCR_RCB3_Pos _U_(3) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */ +#define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */ +#define MATRIX_MRCR_RCB3(value) (MATRIX_MRCR_RCB3_Msk & ((value) << MATRIX_MRCR_RCB3_Pos)) +#define MATRIX_MRCR_RCB4_Pos _U_(4) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */ +#define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */ +#define MATRIX_MRCR_RCB4(value) (MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos)) +#define MATRIX_MRCR_RCB5_Pos _U_(5) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */ +#define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */ +#define MATRIX_MRCR_RCB5(value) (MATRIX_MRCR_RCB5_Msk & ((value) << MATRIX_MRCR_RCB5_Pos)) +#define MATRIX_MRCR_RCB6_Pos _U_(6) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */ +#define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */ +#define MATRIX_MRCR_RCB6(value) (MATRIX_MRCR_RCB6_Msk & ((value) << MATRIX_MRCR_RCB6_Pos)) +#define MATRIX_MRCR_RCB8_Pos _U_(8) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */ +#define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */ +#define MATRIX_MRCR_RCB8(value) (MATRIX_MRCR_RCB8_Msk & ((value) << MATRIX_MRCR_RCB8_Pos)) +#define MATRIX_MRCR_RCB9_Pos _U_(9) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */ +#define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */ +#define MATRIX_MRCR_RCB9(value) (MATRIX_MRCR_RCB9_Msk & ((value) << MATRIX_MRCR_RCB9_Pos)) +#define MATRIX_MRCR_RCB10_Pos _U_(10) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */ +#define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */ +#define MATRIX_MRCR_RCB10(value) (MATRIX_MRCR_RCB10_Msk & ((value) << MATRIX_MRCR_RCB10_Pos)) +#define MATRIX_MRCR_RCB11_Pos _U_(11) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */ +#define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */ +#define MATRIX_MRCR_RCB11(value) (MATRIX_MRCR_RCB11_Msk & ((value) << MATRIX_MRCR_RCB11_Pos)) +#define MATRIX_MRCR_RCB12_Pos _U_(12) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Position */ +#define MATRIX_MRCR_RCB12_Msk (_U_(0x1) << MATRIX_MRCR_RCB12_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Mask */ +#define MATRIX_MRCR_RCB12(value) (MATRIX_MRCR_RCB12_Msk & ((value) << MATRIX_MRCR_RCB12_Pos)) +#define MATRIX_MRCR_Msk _U_(0x00001F7F) /**< (MATRIX_MRCR) Register Mask */ + +#define MATRIX_MRCR_RCB_Pos _U_(0) /**< (MATRIX_MRCR Position) Remap Command Bit for Master x2 */ +#define MATRIX_MRCR_RCB_Msk (_U_(0xFFF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */ +#define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos)) + +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos _U_(16) /**< (CCFG_CAN0) CAN0 DMA Base Address Position */ +#define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */ +#define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)) +#define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */ + + +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4_Pos _U_(4) /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */ +#define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */ +#define CCFG_SYSIO_SYSIO4(value) (CCFG_SYSIO_SYSIO4_Msk & ((value) << CCFG_SYSIO_SYSIO4_Pos)) +#define CCFG_SYSIO_SYSIO5_Pos _U_(5) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */ +#define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */ +#define CCFG_SYSIO_SYSIO5(value) (CCFG_SYSIO_SYSIO5_Msk & ((value) << CCFG_SYSIO_SYSIO5_Pos)) +#define CCFG_SYSIO_SYSIO6_Pos _U_(6) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */ +#define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */ +#define CCFG_SYSIO_SYSIO6(value) (CCFG_SYSIO_SYSIO6_Msk & ((value) << CCFG_SYSIO_SYSIO6_Pos)) +#define CCFG_SYSIO_SYSIO7_Pos _U_(7) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */ +#define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */ +#define CCFG_SYSIO_SYSIO7(value) (CCFG_SYSIO_SYSIO7_Msk & ((value) << CCFG_SYSIO_SYSIO7_Pos)) +#define CCFG_SYSIO_SYSIO12_Pos _U_(12) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */ +#define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */ +#define CCFG_SYSIO_SYSIO12(value) (CCFG_SYSIO_SYSIO12_Msk & ((value) << CCFG_SYSIO_SYSIO12_Pos)) +#define CCFG_SYSIO_CAN1DMABA_Pos _U_(16) /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */ +#define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */ +#define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)) +#define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */ + +#define CCFG_SYSIO_SYSIO_Pos _U_(4) /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */ +#define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos)) + +/* -------- CCFG_PCCR : (MATRIX Offset: 0x118) (R/W 32) Peripheral Clock Configuration Register -------- */ +#define CCFG_PCCR_TC0CC_Pos _U_(20) /**< (CCFG_PCCR) TC0 Clock Configuration Position */ +#define CCFG_PCCR_TC0CC_Msk (_U_(0x1) << CCFG_PCCR_TC0CC_Pos) /**< (CCFG_PCCR) TC0 Clock Configuration Mask */ +#define CCFG_PCCR_TC0CC(value) (CCFG_PCCR_TC0CC_Msk & ((value) << CCFG_PCCR_TC0CC_Pos)) +#define CCFG_PCCR_I2SC0CC_Pos _U_(21) /**< (CCFG_PCCR) I2SC0 Clock Configuration Position */ +#define CCFG_PCCR_I2SC0CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC0CC_Pos) /**< (CCFG_PCCR) I2SC0 Clock Configuration Mask */ +#define CCFG_PCCR_I2SC0CC(value) (CCFG_PCCR_I2SC0CC_Msk & ((value) << CCFG_PCCR_I2SC0CC_Pos)) +#define CCFG_PCCR_I2SC1CC_Pos _U_(22) /**< (CCFG_PCCR) I2SC1 Clock Configuration Position */ +#define CCFG_PCCR_I2SC1CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC1CC_Pos) /**< (CCFG_PCCR) I2SC1 Clock Configuration Mask */ +#define CCFG_PCCR_I2SC1CC(value) (CCFG_PCCR_I2SC1CC_Msk & ((value) << CCFG_PCCR_I2SC1CC_Pos)) +#define CCFG_PCCR_Msk _U_(0x00700000) /**< (CCFG_PCCR) Register Mask */ + + +/* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11C) (R/W 32) Dynamic Clock Gating Register -------- */ +#define CCFG_DYNCKG_MATCKG_Pos _U_(0) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Position */ +#define CCFG_DYNCKG_MATCKG_Msk (_U_(0x1) << CCFG_DYNCKG_MATCKG_Pos) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Mask */ +#define CCFG_DYNCKG_MATCKG(value) (CCFG_DYNCKG_MATCKG_Msk & ((value) << CCFG_DYNCKG_MATCKG_Pos)) +#define CCFG_DYNCKG_BRIDCKG_Pos _U_(1) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Position */ +#define CCFG_DYNCKG_BRIDCKG_Msk (_U_(0x1) << CCFG_DYNCKG_BRIDCKG_Pos) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Mask */ +#define CCFG_DYNCKG_BRIDCKG(value) (CCFG_DYNCKG_BRIDCKG_Msk & ((value) << CCFG_DYNCKG_BRIDCKG_Pos)) +#define CCFG_DYNCKG_EFCCKG_Pos _U_(2) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Position */ +#define CCFG_DYNCKG_EFCCKG_Msk (_U_(0x1) << CCFG_DYNCKG_EFCCKG_Pos) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Mask */ +#define CCFG_DYNCKG_EFCCKG(value) (CCFG_DYNCKG_EFCCKG_Msk & ((value) << CCFG_DYNCKG_EFCCKG_Pos)) +#define CCFG_DYNCKG_Msk _U_(0x00000007) /**< (CCFG_DYNCKG) Register Mask */ + + +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0_Pos _U_(0) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS0(value) (CCFG_SMCNFCS_SMC_NFCS0_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS0_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS1_Pos _U_(1) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS1(value) (CCFG_SMCNFCS_SMC_NFCS1_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS1_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS2_Pos _U_(2) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS2(value) (CCFG_SMCNFCS_SMC_NFCS2_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS2_Pos)) +#define CCFG_SMCNFCS_SMC_NFCS3_Pos _U_(3) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */ +#define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */ +#define CCFG_SMCNFCS_SMC_NFCS3(value) (CCFG_SMCNFCS_SMC_NFCS3_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS3_Pos)) +#define CCFG_SMCNFCS_SDRAMEN_Pos _U_(4) /**< (CCFG_SMCNFCS) SDRAM Enable Position */ +#define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */ +#define CCFG_SMCNFCS_SDRAMEN(value) (CCFG_SMCNFCS_SDRAMEN_Msk & ((value) << CCFG_SMCNFCS_SDRAMEN_Pos)) +#define CCFG_SMCNFCS_Msk _U_(0x0000001F) /**< (CCFG_SMCNFCS) Register Mask */ + +#define CCFG_SMCNFCS_SMC_NFCS_Pos _U_(0) /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */ +#define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos)) + +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) (R/W 32) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN_Pos _U_(0) /**< (MATRIX_WPMR) Write Protection Enable Position */ +#define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */ +#define MATRIX_WPMR_WPEN(value) (MATRIX_WPMR_WPEN_Msk & ((value) << MATRIX_WPMR_WPEN_Pos)) +#define MATRIX_WPMR_WPKEY_Pos _U_(8) /**< (MATRIX_WPMR) Write Protection Key Position */ +#define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */ +#define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)) +#define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */ + + +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) ( R/ 32) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS_Pos _U_(0) /**< (MATRIX_WPSR) Write Protection Violation Status Position */ +#define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */ +#define MATRIX_WPSR_WPVS(value) (MATRIX_WPSR_WPVS_Msk & ((value) << MATRIX_WPSR_WPVS_Pos)) +#define MATRIX_WPSR_WPVSRC_Pos _U_(8) /**< (MATRIX_WPSR) Write Protection Violation Source Position */ +#define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */ +#define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos)) +#define MATRIX_WPSR_Msk _U_(0x00FFFF01) /**< (MATRIX_WPSR) Register Mask */ + + +/** \brief MATRIX register offsets definitions */ +#define MATRIX_PRAS_REG_OFST (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */ +#define MATRIX_PRBS_REG_OFST (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */ +#define MATRIX_MCFG_REG_OFST (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */ +#define MATRIX_SCFG_REG_OFST (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */ +#define MATRIX_MRCR_REG_OFST (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */ +#define CCFG_CAN0_REG_OFST (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */ +#define CCFG_SYSIO_REG_OFST (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */ +#define CCFG_PCCR_REG_OFST (0x118) /**< (CCFG_PCCR) Peripheral Clock Configuration Register Offset */ +#define CCFG_DYNCKG_REG_OFST (0x11C) /**< (CCFG_DYNCKG) Dynamic Clock Gating Register Offset */ +#define CCFG_SMCNFCS_REG_OFST (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */ +#define MATRIX_WPMR_REG_OFST (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */ +#define MATRIX_WPSR_REG_OFST (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MATRIX_PR register API structure */ +typedef struct +{ + __IO uint32_t MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */ +} matrix_pr_registers_t; + +#define MATRIX_PR_NUMBER _U_(9) + +/** \brief MATRIX register API structure */ +typedef struct +{ + __IO uint32_t MATRIX_MCFG[13]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */ + __I uint8_t Reserved1[0x0C]; + __IO uint32_t MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */ + __I uint8_t Reserved2[0x1C]; + matrix_pr_registers_t MATRIX_PR[MATRIX_PR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */ + __I uint8_t Reserved3[0x38]; + __IO uint32_t MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */ + __I uint8_t Reserved4[0x0C]; + __IO uint32_t CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */ + __IO uint32_t CCFG_PCCR; /**< Offset: 0x118 (R/W 32) Peripheral Clock Configuration Register */ + __IO uint32_t CCFG_DYNCKG; /**< Offset: 0x11C (R/W 32) Dynamic Clock Gating Register */ + __I uint8_t Reserved5[0x04]; + __IO uint32_t CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */ + __I uint8_t Reserved6[0xBC]; + __IO uint32_t MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */ +} matrix_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_MATRIX_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/mcan.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/mcan.h new file mode 100644 index 00000000..1f988596 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/mcan.h @@ -0,0 +1,2452 @@ +/** + * \brief Component description for MCAN + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_MCAN_COMPONENT_H_ +#define _SAME70_MCAN_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR MCAN */ +/* ************************************************************************** */ + +/* -------- MCAN_RXBE_0 : (MCAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#define MCAN_RXBE_0_ID_Pos _U_(0) /**< (MCAN_RXBE_0) Identifier Position */ +#define MCAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXBE_0_ID_Pos) /**< (MCAN_RXBE_0) Identifier Mask */ +#define MCAN_RXBE_0_ID(value) (MCAN_RXBE_0_ID_Msk & ((value) << MCAN_RXBE_0_ID_Pos)) +#define MCAN_RXBE_0_RTR_Pos _U_(29) /**< (MCAN_RXBE_0) Remote Transmission Request Position */ +#define MCAN_RXBE_0_RTR_Msk (_U_(0x1) << MCAN_RXBE_0_RTR_Pos) /**< (MCAN_RXBE_0) Remote Transmission Request Mask */ +#define MCAN_RXBE_0_RTR(value) (MCAN_RXBE_0_RTR_Msk & ((value) << MCAN_RXBE_0_RTR_Pos)) +#define MCAN_RXBE_0_XTD_Pos _U_(30) /**< (MCAN_RXBE_0) Extended Identifier Position */ +#define MCAN_RXBE_0_XTD_Msk (_U_(0x1) << MCAN_RXBE_0_XTD_Pos) /**< (MCAN_RXBE_0) Extended Identifier Mask */ +#define MCAN_RXBE_0_XTD(value) (MCAN_RXBE_0_XTD_Msk & ((value) << MCAN_RXBE_0_XTD_Pos)) +#define MCAN_RXBE_0_ESI_Pos _U_(31) /**< (MCAN_RXBE_0) Error State Indicator Position */ +#define MCAN_RXBE_0_ESI_Msk (_U_(0x1) << MCAN_RXBE_0_ESI_Pos) /**< (MCAN_RXBE_0) Error State Indicator Mask */ +#define MCAN_RXBE_0_ESI(value) (MCAN_RXBE_0_ESI_Msk & ((value) << MCAN_RXBE_0_ESI_Pos)) +#define MCAN_RXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_0) Register Mask */ + + +/* -------- MCAN_RXBE_1 : (MCAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#define MCAN_RXBE_1_RXTS_Pos _U_(0) /**< (MCAN_RXBE_1) Rx Timestamp Position */ +#define MCAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXBE_1_RXTS_Pos) /**< (MCAN_RXBE_1) Rx Timestamp Mask */ +#define MCAN_RXBE_1_RXTS(value) (MCAN_RXBE_1_RXTS_Msk & ((value) << MCAN_RXBE_1_RXTS_Pos)) +#define MCAN_RXBE_1_DLC_Pos _U_(16) /**< (MCAN_RXBE_1) Data Length Code Position */ +#define MCAN_RXBE_1_DLC_Msk (_U_(0xF) << MCAN_RXBE_1_DLC_Pos) /**< (MCAN_RXBE_1) Data Length Code Mask */ +#define MCAN_RXBE_1_DLC(value) (MCAN_RXBE_1_DLC_Msk & ((value) << MCAN_RXBE_1_DLC_Pos)) +#define MCAN_RXBE_1_BRS_Pos _U_(20) /**< (MCAN_RXBE_1) Bit Rate Switch Position */ +#define MCAN_RXBE_1_BRS_Msk (_U_(0x1) << MCAN_RXBE_1_BRS_Pos) /**< (MCAN_RXBE_1) Bit Rate Switch Mask */ +#define MCAN_RXBE_1_BRS(value) (MCAN_RXBE_1_BRS_Msk & ((value) << MCAN_RXBE_1_BRS_Pos)) +#define MCAN_RXBE_1_FDF_Pos _U_(21) /**< (MCAN_RXBE_1) FD Format Position */ +#define MCAN_RXBE_1_FDF_Msk (_U_(0x1) << MCAN_RXBE_1_FDF_Pos) /**< (MCAN_RXBE_1) FD Format Mask */ +#define MCAN_RXBE_1_FDF(value) (MCAN_RXBE_1_FDF_Msk & ((value) << MCAN_RXBE_1_FDF_Pos)) +#define MCAN_RXBE_1_FIDX_Pos _U_(24) /**< (MCAN_RXBE_1) Filter Index Position */ +#define MCAN_RXBE_1_FIDX_Msk (_U_(0x7F) << MCAN_RXBE_1_FIDX_Pos) /**< (MCAN_RXBE_1) Filter Index Mask */ +#define MCAN_RXBE_1_FIDX(value) (MCAN_RXBE_1_FIDX_Msk & ((value) << MCAN_RXBE_1_FIDX_Pos)) +#define MCAN_RXBE_1_ANMF_Pos _U_(31) /**< (MCAN_RXBE_1) Accepted Non-matching Frame Position */ +#define MCAN_RXBE_1_ANMF_Msk (_U_(0x1) << MCAN_RXBE_1_ANMF_Pos) /**< (MCAN_RXBE_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXBE_1_ANMF(value) (MCAN_RXBE_1_ANMF_Msk & ((value) << MCAN_RXBE_1_ANMF_Pos)) +#define MCAN_RXBE_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXBE_1) Register Mask */ + + +/* -------- MCAN_RXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#define MCAN_RXBE_DATA_DB0_Pos _U_(0) /**< (MCAN_RXBE_DATA) Data Byte 0 Position */ +#define MCAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB0_Pos) /**< (MCAN_RXBE_DATA) Data Byte 0 Mask */ +#define MCAN_RXBE_DATA_DB0(value) (MCAN_RXBE_DATA_DB0_Msk & ((value) << MCAN_RXBE_DATA_DB0_Pos)) +#define MCAN_RXBE_DATA_DB1_Pos _U_(8) /**< (MCAN_RXBE_DATA) Data Byte 1 Position */ +#define MCAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB1_Pos) /**< (MCAN_RXBE_DATA) Data Byte 1 Mask */ +#define MCAN_RXBE_DATA_DB1(value) (MCAN_RXBE_DATA_DB1_Msk & ((value) << MCAN_RXBE_DATA_DB1_Pos)) +#define MCAN_RXBE_DATA_DB2_Pos _U_(16) /**< (MCAN_RXBE_DATA) Data Byte 2 Position */ +#define MCAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB2_Pos) /**< (MCAN_RXBE_DATA) Data Byte 2 Mask */ +#define MCAN_RXBE_DATA_DB2(value) (MCAN_RXBE_DATA_DB2_Msk & ((value) << MCAN_RXBE_DATA_DB2_Pos)) +#define MCAN_RXBE_DATA_DB3_Pos _U_(24) /**< (MCAN_RXBE_DATA) Data Byte 3 Position */ +#define MCAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB3_Pos) /**< (MCAN_RXBE_DATA) Data Byte 3 Mask */ +#define MCAN_RXBE_DATA_DB3(value) (MCAN_RXBE_DATA_DB3_Msk & ((value) << MCAN_RXBE_DATA_DB3_Pos)) +#define MCAN_RXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_DATA) Register Mask */ + + +/* -------- MCAN_RXF0E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#define MCAN_RXF0E_0_ID_Pos _U_(0) /**< (MCAN_RXF0E_0) Identifier Position */ +#define MCAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF0E_0_ID_Pos) /**< (MCAN_RXF0E_0) Identifier Mask */ +#define MCAN_RXF0E_0_ID(value) (MCAN_RXF0E_0_ID_Msk & ((value) << MCAN_RXF0E_0_ID_Pos)) +#define MCAN_RXF0E_0_RTR_Pos _U_(29) /**< (MCAN_RXF0E_0) Remote Transmission Request Position */ +#define MCAN_RXF0E_0_RTR_Msk (_U_(0x1) << MCAN_RXF0E_0_RTR_Pos) /**< (MCAN_RXF0E_0) Remote Transmission Request Mask */ +#define MCAN_RXF0E_0_RTR(value) (MCAN_RXF0E_0_RTR_Msk & ((value) << MCAN_RXF0E_0_RTR_Pos)) +#define MCAN_RXF0E_0_XTD_Pos _U_(30) /**< (MCAN_RXF0E_0) Extended Identifier Position */ +#define MCAN_RXF0E_0_XTD_Msk (_U_(0x1) << MCAN_RXF0E_0_XTD_Pos) /**< (MCAN_RXF0E_0) Extended Identifier Mask */ +#define MCAN_RXF0E_0_XTD(value) (MCAN_RXF0E_0_XTD_Msk & ((value) << MCAN_RXF0E_0_XTD_Pos)) +#define MCAN_RXF0E_0_ESI_Pos _U_(31) /**< (MCAN_RXF0E_0) Error State Indicator Position */ +#define MCAN_RXF0E_0_ESI_Msk (_U_(0x1) << MCAN_RXF0E_0_ESI_Pos) /**< (MCAN_RXF0E_0) Error State Indicator Mask */ +#define MCAN_RXF0E_0_ESI(value) (MCAN_RXF0E_0_ESI_Msk & ((value) << MCAN_RXF0E_0_ESI_Pos)) +#define MCAN_RXF0E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_0) Register Mask */ + + +/* -------- MCAN_RXF0E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#define MCAN_RXF0E_1_RXTS_Pos _U_(0) /**< (MCAN_RXF0E_1) Rx Timestamp Position */ +#define MCAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF0E_1_RXTS_Pos) /**< (MCAN_RXF0E_1) Rx Timestamp Mask */ +#define MCAN_RXF0E_1_RXTS(value) (MCAN_RXF0E_1_RXTS_Msk & ((value) << MCAN_RXF0E_1_RXTS_Pos)) +#define MCAN_RXF0E_1_DLC_Pos _U_(16) /**< (MCAN_RXF0E_1) Data Length Code Position */ +#define MCAN_RXF0E_1_DLC_Msk (_U_(0xF) << MCAN_RXF0E_1_DLC_Pos) /**< (MCAN_RXF0E_1) Data Length Code Mask */ +#define MCAN_RXF0E_1_DLC(value) (MCAN_RXF0E_1_DLC_Msk & ((value) << MCAN_RXF0E_1_DLC_Pos)) +#define MCAN_RXF0E_1_BRS_Pos _U_(20) /**< (MCAN_RXF0E_1) Bit Rate Switch Position */ +#define MCAN_RXF0E_1_BRS_Msk (_U_(0x1) << MCAN_RXF0E_1_BRS_Pos) /**< (MCAN_RXF0E_1) Bit Rate Switch Mask */ +#define MCAN_RXF0E_1_BRS(value) (MCAN_RXF0E_1_BRS_Msk & ((value) << MCAN_RXF0E_1_BRS_Pos)) +#define MCAN_RXF0E_1_FDF_Pos _U_(21) /**< (MCAN_RXF0E_1) FD Format Position */ +#define MCAN_RXF0E_1_FDF_Msk (_U_(0x1) << MCAN_RXF0E_1_FDF_Pos) /**< (MCAN_RXF0E_1) FD Format Mask */ +#define MCAN_RXF0E_1_FDF(value) (MCAN_RXF0E_1_FDF_Msk & ((value) << MCAN_RXF0E_1_FDF_Pos)) +#define MCAN_RXF0E_1_FIDX_Pos _U_(24) /**< (MCAN_RXF0E_1) Filter Index Position */ +#define MCAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF0E_1_FIDX_Pos) /**< (MCAN_RXF0E_1) Filter Index Mask */ +#define MCAN_RXF0E_1_FIDX(value) (MCAN_RXF0E_1_FIDX_Msk & ((value) << MCAN_RXF0E_1_FIDX_Pos)) +#define MCAN_RXF0E_1_ANMF_Pos _U_(31) /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Position */ +#define MCAN_RXF0E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF0E_1_ANMF_Pos) /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXF0E_1_ANMF(value) (MCAN_RXF0E_1_ANMF_Msk & ((value) << MCAN_RXF0E_1_ANMF_Pos)) +#define MCAN_RXF0E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF0E_1) Register Mask */ + + +/* -------- MCAN_RXF0E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#define MCAN_RXF0E_DATA_DB0_Pos _U_(0) /**< (MCAN_RXF0E_DATA) Data Byte 0 Position */ +#define MCAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB0_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 0 Mask */ +#define MCAN_RXF0E_DATA_DB0(value) (MCAN_RXF0E_DATA_DB0_Msk & ((value) << MCAN_RXF0E_DATA_DB0_Pos)) +#define MCAN_RXF0E_DATA_DB1_Pos _U_(8) /**< (MCAN_RXF0E_DATA) Data Byte 1 Position */ +#define MCAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB1_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 1 Mask */ +#define MCAN_RXF0E_DATA_DB1(value) (MCAN_RXF0E_DATA_DB1_Msk & ((value) << MCAN_RXF0E_DATA_DB1_Pos)) +#define MCAN_RXF0E_DATA_DB2_Pos _U_(16) /**< (MCAN_RXF0E_DATA) Data Byte 2 Position */ +#define MCAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB2_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 2 Mask */ +#define MCAN_RXF0E_DATA_DB2(value) (MCAN_RXF0E_DATA_DB2_Msk & ((value) << MCAN_RXF0E_DATA_DB2_Pos)) +#define MCAN_RXF0E_DATA_DB3_Pos _U_(24) /**< (MCAN_RXF0E_DATA) Data Byte 3 Position */ +#define MCAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB3_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 3 Mask */ +#define MCAN_RXF0E_DATA_DB3(value) (MCAN_RXF0E_DATA_DB3_Msk & ((value) << MCAN_RXF0E_DATA_DB3_Pos)) +#define MCAN_RXF0E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_DATA) Register Mask */ + + +/* -------- MCAN_RXF1E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#define MCAN_RXF1E_0_ID_Pos _U_(0) /**< (MCAN_RXF1E_0) Identifier Position */ +#define MCAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF1E_0_ID_Pos) /**< (MCAN_RXF1E_0) Identifier Mask */ +#define MCAN_RXF1E_0_ID(value) (MCAN_RXF1E_0_ID_Msk & ((value) << MCAN_RXF1E_0_ID_Pos)) +#define MCAN_RXF1E_0_RTR_Pos _U_(29) /**< (MCAN_RXF1E_0) Remote Transmission Request Position */ +#define MCAN_RXF1E_0_RTR_Msk (_U_(0x1) << MCAN_RXF1E_0_RTR_Pos) /**< (MCAN_RXF1E_0) Remote Transmission Request Mask */ +#define MCAN_RXF1E_0_RTR(value) (MCAN_RXF1E_0_RTR_Msk & ((value) << MCAN_RXF1E_0_RTR_Pos)) +#define MCAN_RXF1E_0_XTD_Pos _U_(30) /**< (MCAN_RXF1E_0) Extended Identifier Position */ +#define MCAN_RXF1E_0_XTD_Msk (_U_(0x1) << MCAN_RXF1E_0_XTD_Pos) /**< (MCAN_RXF1E_0) Extended Identifier Mask */ +#define MCAN_RXF1E_0_XTD(value) (MCAN_RXF1E_0_XTD_Msk & ((value) << MCAN_RXF1E_0_XTD_Pos)) +#define MCAN_RXF1E_0_ESI_Pos _U_(31) /**< (MCAN_RXF1E_0) Error State Indicator Position */ +#define MCAN_RXF1E_0_ESI_Msk (_U_(0x1) << MCAN_RXF1E_0_ESI_Pos) /**< (MCAN_RXF1E_0) Error State Indicator Mask */ +#define MCAN_RXF1E_0_ESI(value) (MCAN_RXF1E_0_ESI_Msk & ((value) << MCAN_RXF1E_0_ESI_Pos)) +#define MCAN_RXF1E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_0) Register Mask */ + + +/* -------- MCAN_RXF1E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#define MCAN_RXF1E_1_RXTS_Pos _U_(0) /**< (MCAN_RXF1E_1) Rx Timestamp Position */ +#define MCAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF1E_1_RXTS_Pos) /**< (MCAN_RXF1E_1) Rx Timestamp Mask */ +#define MCAN_RXF1E_1_RXTS(value) (MCAN_RXF1E_1_RXTS_Msk & ((value) << MCAN_RXF1E_1_RXTS_Pos)) +#define MCAN_RXF1E_1_DLC_Pos _U_(16) /**< (MCAN_RXF1E_1) Data Length Code Position */ +#define MCAN_RXF1E_1_DLC_Msk (_U_(0xF) << MCAN_RXF1E_1_DLC_Pos) /**< (MCAN_RXF1E_1) Data Length Code Mask */ +#define MCAN_RXF1E_1_DLC(value) (MCAN_RXF1E_1_DLC_Msk & ((value) << MCAN_RXF1E_1_DLC_Pos)) +#define MCAN_RXF1E_1_BRS_Pos _U_(20) /**< (MCAN_RXF1E_1) Bit Rate Switch Position */ +#define MCAN_RXF1E_1_BRS_Msk (_U_(0x1) << MCAN_RXF1E_1_BRS_Pos) /**< (MCAN_RXF1E_1) Bit Rate Switch Mask */ +#define MCAN_RXF1E_1_BRS(value) (MCAN_RXF1E_1_BRS_Msk & ((value) << MCAN_RXF1E_1_BRS_Pos)) +#define MCAN_RXF1E_1_FDF_Pos _U_(21) /**< (MCAN_RXF1E_1) FD Format Position */ +#define MCAN_RXF1E_1_FDF_Msk (_U_(0x1) << MCAN_RXF1E_1_FDF_Pos) /**< (MCAN_RXF1E_1) FD Format Mask */ +#define MCAN_RXF1E_1_FDF(value) (MCAN_RXF1E_1_FDF_Msk & ((value) << MCAN_RXF1E_1_FDF_Pos)) +#define MCAN_RXF1E_1_FIDX_Pos _U_(24) /**< (MCAN_RXF1E_1) Filter Index Position */ +#define MCAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF1E_1_FIDX_Pos) /**< (MCAN_RXF1E_1) Filter Index Mask */ +#define MCAN_RXF1E_1_FIDX(value) (MCAN_RXF1E_1_FIDX_Msk & ((value) << MCAN_RXF1E_1_FIDX_Pos)) +#define MCAN_RXF1E_1_ANMF_Pos _U_(31) /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Position */ +#define MCAN_RXF1E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF1E_1_ANMF_Pos) /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Mask */ +#define MCAN_RXF1E_1_ANMF(value) (MCAN_RXF1E_1_ANMF_Msk & ((value) << MCAN_RXF1E_1_ANMF_Pos)) +#define MCAN_RXF1E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF1E_1) Register Mask */ + + +/* -------- MCAN_RXF1E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#define MCAN_RXF1E_DATA_DB0_Pos _U_(0) /**< (MCAN_RXF1E_DATA) Data Byte 0 Position */ +#define MCAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB0_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 0 Mask */ +#define MCAN_RXF1E_DATA_DB0(value) (MCAN_RXF1E_DATA_DB0_Msk & ((value) << MCAN_RXF1E_DATA_DB0_Pos)) +#define MCAN_RXF1E_DATA_DB1_Pos _U_(8) /**< (MCAN_RXF1E_DATA) Data Byte 1 Position */ +#define MCAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB1_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 1 Mask */ +#define MCAN_RXF1E_DATA_DB1(value) (MCAN_RXF1E_DATA_DB1_Msk & ((value) << MCAN_RXF1E_DATA_DB1_Pos)) +#define MCAN_RXF1E_DATA_DB2_Pos _U_(16) /**< (MCAN_RXF1E_DATA) Data Byte 2 Position */ +#define MCAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB2_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 2 Mask */ +#define MCAN_RXF1E_DATA_DB2(value) (MCAN_RXF1E_DATA_DB2_Msk & ((value) << MCAN_RXF1E_DATA_DB2_Pos)) +#define MCAN_RXF1E_DATA_DB3_Pos _U_(24) /**< (MCAN_RXF1E_DATA) Data Byte 3 Position */ +#define MCAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB3_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 3 Mask */ +#define MCAN_RXF1E_DATA_DB3(value) (MCAN_RXF1E_DATA_DB3_Msk & ((value) << MCAN_RXF1E_DATA_DB3_Pos)) +#define MCAN_RXF1E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_DATA) Register Mask */ + + +/* -------- MCAN_TXBE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#define MCAN_TXBE_0_ID_Pos _U_(0) /**< (MCAN_TXBE_0) Identifier Position */ +#define MCAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXBE_0_ID_Pos) /**< (MCAN_TXBE_0) Identifier Mask */ +#define MCAN_TXBE_0_ID(value) (MCAN_TXBE_0_ID_Msk & ((value) << MCAN_TXBE_0_ID_Pos)) +#define MCAN_TXBE_0_RTR_Pos _U_(29) /**< (MCAN_TXBE_0) Remote Transmission Request Position */ +#define MCAN_TXBE_0_RTR_Msk (_U_(0x1) << MCAN_TXBE_0_RTR_Pos) /**< (MCAN_TXBE_0) Remote Transmission Request Mask */ +#define MCAN_TXBE_0_RTR(value) (MCAN_TXBE_0_RTR_Msk & ((value) << MCAN_TXBE_0_RTR_Pos)) +#define MCAN_TXBE_0_XTD_Pos _U_(30) /**< (MCAN_TXBE_0) Extended Identifier Position */ +#define MCAN_TXBE_0_XTD_Msk (_U_(0x1) << MCAN_TXBE_0_XTD_Pos) /**< (MCAN_TXBE_0) Extended Identifier Mask */ +#define MCAN_TXBE_0_XTD(value) (MCAN_TXBE_0_XTD_Msk & ((value) << MCAN_TXBE_0_XTD_Pos)) +#define MCAN_TXBE_0_ESI_Pos _U_(31) /**< (MCAN_TXBE_0) Error State Indicator Position */ +#define MCAN_TXBE_0_ESI_Msk (_U_(0x1) << MCAN_TXBE_0_ESI_Pos) /**< (MCAN_TXBE_0) Error State Indicator Mask */ +#define MCAN_TXBE_0_ESI(value) (MCAN_TXBE_0_ESI_Msk & ((value) << MCAN_TXBE_0_ESI_Pos)) +#define MCAN_TXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_0) Register Mask */ + + +/* -------- MCAN_TXBE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#define MCAN_TXBE_1_DLC_Pos _U_(16) /**< (MCAN_TXBE_1) Data Length Code Position */ +#define MCAN_TXBE_1_DLC_Msk (_U_(0xF) << MCAN_TXBE_1_DLC_Pos) /**< (MCAN_TXBE_1) Data Length Code Mask */ +#define MCAN_TXBE_1_DLC(value) (MCAN_TXBE_1_DLC_Msk & ((value) << MCAN_TXBE_1_DLC_Pos)) +#define MCAN_TXBE_1_BRS_Pos _U_(20) /**< (MCAN_TXBE_1) Bit Rate Switch Position */ +#define MCAN_TXBE_1_BRS_Msk (_U_(0x1) << MCAN_TXBE_1_BRS_Pos) /**< (MCAN_TXBE_1) Bit Rate Switch Mask */ +#define MCAN_TXBE_1_BRS(value) (MCAN_TXBE_1_BRS_Msk & ((value) << MCAN_TXBE_1_BRS_Pos)) +#define MCAN_TXBE_1_FDF_Pos _U_(21) /**< (MCAN_TXBE_1) FD Format Position */ +#define MCAN_TXBE_1_FDF_Msk (_U_(0x1) << MCAN_TXBE_1_FDF_Pos) /**< (MCAN_TXBE_1) FD Format Mask */ +#define MCAN_TXBE_1_FDF(value) (MCAN_TXBE_1_FDF_Msk & ((value) << MCAN_TXBE_1_FDF_Pos)) +#define MCAN_TXBE_1_EFC_Pos _U_(23) /**< (MCAN_TXBE_1) Event FIFO Control Position */ +#define MCAN_TXBE_1_EFC_Msk (_U_(0x1) << MCAN_TXBE_1_EFC_Pos) /**< (MCAN_TXBE_1) Event FIFO Control Mask */ +#define MCAN_TXBE_1_EFC(value) (MCAN_TXBE_1_EFC_Msk & ((value) << MCAN_TXBE_1_EFC_Pos)) +#define MCAN_TXBE_1_MM_Pos _U_(24) /**< (MCAN_TXBE_1) Message Marker Position */ +#define MCAN_TXBE_1_MM_Msk (_U_(0xFF) << MCAN_TXBE_1_MM_Pos) /**< (MCAN_TXBE_1) Message Marker Mask */ +#define MCAN_TXBE_1_MM(value) (MCAN_TXBE_1_MM_Msk & ((value) << MCAN_TXBE_1_MM_Pos)) +#define MCAN_TXBE_1_Msk _U_(0xFFBF0000) /**< (MCAN_TXBE_1) Register Mask */ + + +/* -------- MCAN_TXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#define MCAN_TXBE_DATA_DB0_Pos _U_(0) /**< (MCAN_TXBE_DATA) Data Byte 0 Position */ +#define MCAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB0_Pos) /**< (MCAN_TXBE_DATA) Data Byte 0 Mask */ +#define MCAN_TXBE_DATA_DB0(value) (MCAN_TXBE_DATA_DB0_Msk & ((value) << MCAN_TXBE_DATA_DB0_Pos)) +#define MCAN_TXBE_DATA_DB1_Pos _U_(8) /**< (MCAN_TXBE_DATA) Data Byte 1 Position */ +#define MCAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB1_Pos) /**< (MCAN_TXBE_DATA) Data Byte 1 Mask */ +#define MCAN_TXBE_DATA_DB1(value) (MCAN_TXBE_DATA_DB1_Msk & ((value) << MCAN_TXBE_DATA_DB1_Pos)) +#define MCAN_TXBE_DATA_DB2_Pos _U_(16) /**< (MCAN_TXBE_DATA) Data Byte 2 Position */ +#define MCAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB2_Pos) /**< (MCAN_TXBE_DATA) Data Byte 2 Mask */ +#define MCAN_TXBE_DATA_DB2(value) (MCAN_TXBE_DATA_DB2_Msk & ((value) << MCAN_TXBE_DATA_DB2_Pos)) +#define MCAN_TXBE_DATA_DB3_Pos _U_(24) /**< (MCAN_TXBE_DATA) Data Byte 3 Position */ +#define MCAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB3_Pos) /**< (MCAN_TXBE_DATA) Data Byte 3 Mask */ +#define MCAN_TXBE_DATA_DB3(value) (MCAN_TXBE_DATA_DB3_Msk & ((value) << MCAN_TXBE_DATA_DB3_Pos)) +#define MCAN_TXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_DATA) Register Mask */ + + +/* -------- MCAN_TXEFE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#define MCAN_TXEFE_0_ID_Pos _U_(0) /**< (MCAN_TXEFE_0) Identifier Position */ +#define MCAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXEFE_0_ID_Pos) /**< (MCAN_TXEFE_0) Identifier Mask */ +#define MCAN_TXEFE_0_ID(value) (MCAN_TXEFE_0_ID_Msk & ((value) << MCAN_TXEFE_0_ID_Pos)) +#define MCAN_TXEFE_0_RTR_Pos _U_(29) /**< (MCAN_TXEFE_0) Remote Transmission Request Position */ +#define MCAN_TXEFE_0_RTR_Msk (_U_(0x1) << MCAN_TXEFE_0_RTR_Pos) /**< (MCAN_TXEFE_0) Remote Transmission Request Mask */ +#define MCAN_TXEFE_0_RTR(value) (MCAN_TXEFE_0_RTR_Msk & ((value) << MCAN_TXEFE_0_RTR_Pos)) +#define MCAN_TXEFE_0_XTD_Pos _U_(30) /**< (MCAN_TXEFE_0) Extended Identifier Position */ +#define MCAN_TXEFE_0_XTD_Msk (_U_(0x1) << MCAN_TXEFE_0_XTD_Pos) /**< (MCAN_TXEFE_0) Extended Identifier Mask */ +#define MCAN_TXEFE_0_XTD(value) (MCAN_TXEFE_0_XTD_Msk & ((value) << MCAN_TXEFE_0_XTD_Pos)) +#define MCAN_TXEFE_0_ESI_Pos _U_(31) /**< (MCAN_TXEFE_0) Error State Indicator Position */ +#define MCAN_TXEFE_0_ESI_Msk (_U_(0x1) << MCAN_TXEFE_0_ESI_Pos) /**< (MCAN_TXEFE_0) Error State Indicator Mask */ +#define MCAN_TXEFE_0_ESI(value) (MCAN_TXEFE_0_ESI_Msk & ((value) << MCAN_TXEFE_0_ESI_Pos)) +#define MCAN_TXEFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_0) Register Mask */ + + +/* -------- MCAN_TXEFE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#define MCAN_TXEFE_1_TXTS_Pos _U_(0) /**< (MCAN_TXEFE_1) Tx Timestamp Position */ +#define MCAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << MCAN_TXEFE_1_TXTS_Pos) /**< (MCAN_TXEFE_1) Tx Timestamp Mask */ +#define MCAN_TXEFE_1_TXTS(value) (MCAN_TXEFE_1_TXTS_Msk & ((value) << MCAN_TXEFE_1_TXTS_Pos)) +#define MCAN_TXEFE_1_DLC_Pos _U_(16) /**< (MCAN_TXEFE_1) Data Length Code Position */ +#define MCAN_TXEFE_1_DLC_Msk (_U_(0xF) << MCAN_TXEFE_1_DLC_Pos) /**< (MCAN_TXEFE_1) Data Length Code Mask */ +#define MCAN_TXEFE_1_DLC(value) (MCAN_TXEFE_1_DLC_Msk & ((value) << MCAN_TXEFE_1_DLC_Pos)) +#define MCAN_TXEFE_1_BRS_Pos _U_(20) /**< (MCAN_TXEFE_1) Bit Rate Switch Position */ +#define MCAN_TXEFE_1_BRS_Msk (_U_(0x1) << MCAN_TXEFE_1_BRS_Pos) /**< (MCAN_TXEFE_1) Bit Rate Switch Mask */ +#define MCAN_TXEFE_1_BRS(value) (MCAN_TXEFE_1_BRS_Msk & ((value) << MCAN_TXEFE_1_BRS_Pos)) +#define MCAN_TXEFE_1_FDF_Pos _U_(21) /**< (MCAN_TXEFE_1) FD Format Position */ +#define MCAN_TXEFE_1_FDF_Msk (_U_(0x1) << MCAN_TXEFE_1_FDF_Pos) /**< (MCAN_TXEFE_1) FD Format Mask */ +#define MCAN_TXEFE_1_FDF(value) (MCAN_TXEFE_1_FDF_Msk & ((value) << MCAN_TXEFE_1_FDF_Pos)) +#define MCAN_TXEFE_1_ET_Pos _U_(22) /**< (MCAN_TXEFE_1) Event Type Position */ +#define MCAN_TXEFE_1_ET_Msk (_U_(0x3) << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Event Type Mask */ +#define MCAN_TXEFE_1_ET(value) (MCAN_TXEFE_1_ET_Msk & ((value) << MCAN_TXEFE_1_ET_Pos)) +#define MCAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< (MCAN_TXEFE_1) Tx event */ +#define MCAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation */ +#define MCAN_TXEFE_1_ET_TXE (MCAN_TXEFE_1_ET_TXE_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Tx event Position */ +#define MCAN_TXEFE_1_ET_TXC (MCAN_TXEFE_1_ET_TXC_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation Position */ +#define MCAN_TXEFE_1_MM_Pos _U_(24) /**< (MCAN_TXEFE_1) Message Marker Position */ +#define MCAN_TXEFE_1_MM_Msk (_U_(0xFF) << MCAN_TXEFE_1_MM_Pos) /**< (MCAN_TXEFE_1) Message Marker Mask */ +#define MCAN_TXEFE_1_MM(value) (MCAN_TXEFE_1_MM_Msk & ((value) << MCAN_TXEFE_1_MM_Pos)) +#define MCAN_TXEFE_1_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_1) Register Mask */ + + +/* -------- MCAN_SIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ +#define MCAN_SIDFE_0_SFID2_Pos _U_(0) /**< (MCAN_SIDFE_0) Standard Filter ID 2 Position */ +#define MCAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID2_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 2 Mask */ +#define MCAN_SIDFE_0_SFID2(value) (MCAN_SIDFE_0_SFID2_Msk & ((value) << MCAN_SIDFE_0_SFID2_Pos)) +#define MCAN_SIDFE_0_SFID1_Pos _U_(16) /**< (MCAN_SIDFE_0) Standard Filter ID 1 Position */ +#define MCAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID1_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 1 Mask */ +#define MCAN_SIDFE_0_SFID1(value) (MCAN_SIDFE_0_SFID1_Msk & ((value) << MCAN_SIDFE_0_SFID1_Pos)) +#define MCAN_SIDFE_0_SFEC_Pos _U_(27) /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Position */ +#define MCAN_SIDFE_0_SFEC_Msk (_U_(0x7) << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Mask */ +#define MCAN_SIDFE_0_SFEC(value) (MCAN_SIDFE_0_SFEC_Msk & ((value) << MCAN_SIDFE_0_SFEC_Pos)) +#define MCAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Disable filter element */ +#define MCAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches */ +#define MCAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches */ +#define MCAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< (MCAN_SIDFE_0) Reject ID if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_SIDFE_0) Set priority if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches */ +#define MCAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches */ +#define MCAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_SIDFE_0) Store into Rx Buffer */ +#define MCAN_SIDFE_0_SFEC_DISABLE (MCAN_SIDFE_0_SFEC_DISABLE_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Disable filter element Position */ +#define MCAN_SIDFE_0_SFEC_STF0M (MCAN_SIDFE_0_SFEC_STF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_STF1M (MCAN_SIDFE_0_SFEC_STF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_REJECT (MCAN_SIDFE_0_SFEC_REJECT_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Reject ID if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIORITY (MCAN_SIDFE_0_SFEC_PRIORITY_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIF0M (MCAN_SIDFE_0_SFEC_PRIF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_PRIF1M (MCAN_SIDFE_0_SFEC_PRIF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ +#define MCAN_SIDFE_0_SFEC_STRXBUF (MCAN_SIDFE_0_SFEC_STRXBUF_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store into Rx Buffer Position */ +#define MCAN_SIDFE_0_SFT_Pos _U_(30) /**< (MCAN_SIDFE_0) Standard Filter Type Position */ +#define MCAN_SIDFE_0_SFT_Msk (_U_(0x3) << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Standard Filter Type Mask */ +#define MCAN_SIDFE_0_SFT(value) (MCAN_SIDFE_0_SFT_Msk & ((value) << MCAN_SIDFE_0_SFT_Pos)) +#define MCAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define MCAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID */ +#define MCAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< (MCAN_SIDFE_0) Classic filter */ +#define MCAN_SIDFE_0_SFT_RANGE (MCAN_SIDFE_0_SFT_RANGE_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ +#define MCAN_SIDFE_0_SFT_DUAL (MCAN_SIDFE_0_SFT_DUAL_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID Position */ +#define MCAN_SIDFE_0_SFT_CLASSIC (MCAN_SIDFE_0_SFT_CLASSIC_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Classic filter Position */ +#define MCAN_SIDFE_0_Msk _U_(0xFFFF07FF) /**< (MCAN_SIDFE_0) Register Mask */ + + +/* -------- MCAN_XIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#define MCAN_XIDFE_0_EFID1_Pos _U_(0) /**< (MCAN_XIDFE_0) Extended Filter ID 1 Position */ +#define MCAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_0_EFID1_Pos) /**< (MCAN_XIDFE_0) Extended Filter ID 1 Mask */ +#define MCAN_XIDFE_0_EFID1(value) (MCAN_XIDFE_0_EFID1_Msk & ((value) << MCAN_XIDFE_0_EFID1_Pos)) +#define MCAN_XIDFE_0_EFEC_Pos _U_(29) /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Position */ +#define MCAN_XIDFE_0_EFEC_Msk (_U_(0x7) << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Mask */ +#define MCAN_XIDFE_0_EFEC(value) (MCAN_XIDFE_0_EFEC_Msk & ((value) << MCAN_XIDFE_0_EFEC_Pos)) +#define MCAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< (MCAN_XIDFE_0) Disable filter element */ +#define MCAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches */ +#define MCAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches */ +#define MCAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< (MCAN_XIDFE_0) Reject ID if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_XIDFE_0) Set priority if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches */ +#define MCAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches */ +#define MCAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_XIDFE_0) Store into Rx Buffer */ +#define MCAN_XIDFE_0_EFEC_DISABLE (MCAN_XIDFE_0_EFEC_DISABLE_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Disable filter element Position */ +#define MCAN_XIDFE_0_EFEC_STF0M (MCAN_XIDFE_0_EFEC_STF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_STF1M (MCAN_XIDFE_0_EFEC_STF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_REJECT (MCAN_XIDFE_0_EFEC_REJECT_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Reject ID if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIORITY (MCAN_XIDFE_0_EFEC_PRIORITY_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIF0M (MCAN_XIDFE_0_EFEC_PRIF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_PRIF1M (MCAN_XIDFE_0_EFEC_PRIF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ +#define MCAN_XIDFE_0_EFEC_STRXBUF (MCAN_XIDFE_0_EFEC_STRXBUF_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store into Rx Buffer Position */ +#define MCAN_XIDFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_XIDFE_0) Register Mask */ + + +/* -------- MCAN_XIDFE_1 : (MCAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#define MCAN_XIDFE_1_EFID2_Pos _U_(0) /**< (MCAN_XIDFE_1) Extended Filter ID 2 Position */ +#define MCAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_1_EFID2_Pos) /**< (MCAN_XIDFE_1) Extended Filter ID 2 Mask */ +#define MCAN_XIDFE_1_EFID2(value) (MCAN_XIDFE_1_EFID2_Msk & ((value) << MCAN_XIDFE_1_EFID2_Pos)) +#define MCAN_XIDFE_1_EFT_Pos _U_(30) /**< (MCAN_XIDFE_1) Extended Filter Type Position */ +#define MCAN_XIDFE_1_EFT_Msk (_U_(0x3) << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Extended Filter Type Mask */ +#define MCAN_XIDFE_1_EFT(value) (MCAN_XIDFE_1_EFT_Msk & ((value) << MCAN_XIDFE_1_EFT_Pos)) +#define MCAN_XIDFE_1_EFT_RANGE_Val _U_(0x0) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define MCAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define MCAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< (MCAN_XIDFE_1) Classic filter */ +#define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val _U_(0x3) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define MCAN_XIDFE_1_EFT_RANGE (MCAN_XIDFE_1_EFT_RANGE_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ +#define MCAN_XIDFE_1_EFT_DUAL (MCAN_XIDFE_1_EFT_DUAL_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ +#define MCAN_XIDFE_1_EFT_CLASSIC (MCAN_XIDFE_1_EFT_CLASSIC_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Classic filter Position */ +#define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM (MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ +#define MCAN_XIDFE_1_Msk _U_(0xDFFFFFFF) /**< (MCAN_XIDFE_1) Register Mask */ + + +/* -------- MCAN_CREL : (MCAN Offset: 0x00) ( R/ 32) Core Release Register -------- */ +#define MCAN_CREL_DAY_Pos _U_(0) /**< (MCAN_CREL) Timestamp Day Position */ +#define MCAN_CREL_DAY_Msk (_U_(0xFF) << MCAN_CREL_DAY_Pos) /**< (MCAN_CREL) Timestamp Day Mask */ +#define MCAN_CREL_DAY(value) (MCAN_CREL_DAY_Msk & ((value) << MCAN_CREL_DAY_Pos)) +#define MCAN_CREL_MON_Pos _U_(8) /**< (MCAN_CREL) Timestamp Month Position */ +#define MCAN_CREL_MON_Msk (_U_(0xFF) << MCAN_CREL_MON_Pos) /**< (MCAN_CREL) Timestamp Month Mask */ +#define MCAN_CREL_MON(value) (MCAN_CREL_MON_Msk & ((value) << MCAN_CREL_MON_Pos)) +#define MCAN_CREL_YEAR_Pos _U_(16) /**< (MCAN_CREL) Timestamp Year Position */ +#define MCAN_CREL_YEAR_Msk (_U_(0xF) << MCAN_CREL_YEAR_Pos) /**< (MCAN_CREL) Timestamp Year Mask */ +#define MCAN_CREL_YEAR(value) (MCAN_CREL_YEAR_Msk & ((value) << MCAN_CREL_YEAR_Pos)) +#define MCAN_CREL_SUBSTEP_Pos _U_(20) /**< (MCAN_CREL) Sub-step of Core Release Position */ +#define MCAN_CREL_SUBSTEP_Msk (_U_(0xF) << MCAN_CREL_SUBSTEP_Pos) /**< (MCAN_CREL) Sub-step of Core Release Mask */ +#define MCAN_CREL_SUBSTEP(value) (MCAN_CREL_SUBSTEP_Msk & ((value) << MCAN_CREL_SUBSTEP_Pos)) +#define MCAN_CREL_STEP_Pos _U_(24) /**< (MCAN_CREL) Step of Core Release Position */ +#define MCAN_CREL_STEP_Msk (_U_(0xF) << MCAN_CREL_STEP_Pos) /**< (MCAN_CREL) Step of Core Release Mask */ +#define MCAN_CREL_STEP(value) (MCAN_CREL_STEP_Msk & ((value) << MCAN_CREL_STEP_Pos)) +#define MCAN_CREL_REL_Pos _U_(28) /**< (MCAN_CREL) Core Release Position */ +#define MCAN_CREL_REL_Msk (_U_(0xF) << MCAN_CREL_REL_Pos) /**< (MCAN_CREL) Core Release Mask */ +#define MCAN_CREL_REL(value) (MCAN_CREL_REL_Msk & ((value) << MCAN_CREL_REL_Pos)) +#define MCAN_CREL_Msk _U_(0xFFFFFFFF) /**< (MCAN_CREL) Register Mask */ + + +/* -------- MCAN_ENDN : (MCAN Offset: 0x04) ( R/ 32) Endian Register -------- */ +#define MCAN_ENDN_ETV_Pos _U_(0) /**< (MCAN_ENDN) Endianness Test Value Position */ +#define MCAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << MCAN_ENDN_ETV_Pos) /**< (MCAN_ENDN) Endianness Test Value Mask */ +#define MCAN_ENDN_ETV(value) (MCAN_ENDN_ETV_Msk & ((value) << MCAN_ENDN_ETV_Pos)) +#define MCAN_ENDN_Msk _U_(0xFFFFFFFF) /**< (MCAN_ENDN) Register Mask */ + + +/* -------- MCAN_CUST : (MCAN Offset: 0x08) (R/W 32) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos _U_(0) /**< (MCAN_CUST) Customer-specific Value Position */ +#define MCAN_CUST_CSV_Msk (_U_(0xFFFFFFFF) << MCAN_CUST_CSV_Pos) /**< (MCAN_CUST) Customer-specific Value Mask */ +#define MCAN_CUST_CSV(value) (MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)) +#define MCAN_CUST_Msk _U_(0xFFFFFFFF) /**< (MCAN_CUST) Register Mask */ + + +/* -------- MCAN_DBTP : (MCAN Offset: 0x0C) (R/W 32) Data Bit Timing and Prescaler Register -------- */ +#define MCAN_DBTP_DSJW_Pos _U_(0) /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Position */ +#define MCAN_DBTP_DSJW_Msk (_U_(0x7) << MCAN_DBTP_DSJW_Pos) /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Mask */ +#define MCAN_DBTP_DSJW(value) (MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)) +#define MCAN_DBTP_DTSEG2_Pos _U_(4) /**< (MCAN_DBTP) Data Time Segment After Sample Point Position */ +#define MCAN_DBTP_DTSEG2_Msk (_U_(0xF) << MCAN_DBTP_DTSEG2_Pos) /**< (MCAN_DBTP) Data Time Segment After Sample Point Mask */ +#define MCAN_DBTP_DTSEG2(value) (MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)) +#define MCAN_DBTP_DTSEG1_Pos _U_(8) /**< (MCAN_DBTP) Data Time Segment Before Sample Point Position */ +#define MCAN_DBTP_DTSEG1_Msk (_U_(0x1F) << MCAN_DBTP_DTSEG1_Pos) /**< (MCAN_DBTP) Data Time Segment Before Sample Point Mask */ +#define MCAN_DBTP_DTSEG1(value) (MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)) +#define MCAN_DBTP_DBRP_Pos _U_(16) /**< (MCAN_DBTP) Data Bit Rate Prescaler Position */ +#define MCAN_DBTP_DBRP_Msk (_U_(0x1F) << MCAN_DBTP_DBRP_Pos) /**< (MCAN_DBTP) Data Bit Rate Prescaler Mask */ +#define MCAN_DBTP_DBRP(value) (MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos)) +#define MCAN_DBTP_TDC_Pos _U_(23) /**< (MCAN_DBTP) Transmitter Delay Compensation Position */ +#define MCAN_DBTP_TDC_Msk (_U_(0x1) << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation Mask */ +#define MCAN_DBTP_TDC(value) (MCAN_DBTP_TDC_Msk & ((value) << MCAN_DBTP_TDC_Pos)) +#define MCAN_DBTP_TDC_DISABLED_Val _U_(0x0) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. */ +#define MCAN_DBTP_TDC_ENABLED_Val _U_(0x1) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. */ +#define MCAN_DBTP_TDC_DISABLED (MCAN_DBTP_TDC_DISABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. Position */ +#define MCAN_DBTP_TDC_ENABLED (MCAN_DBTP_TDC_ENABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. Position */ +#define MCAN_DBTP_Msk _U_(0x009F1FF7) /**< (MCAN_DBTP) Register Mask */ + + +/* -------- MCAN_TEST : (MCAN Offset: 0x10) (R/W 32) Test Register -------- */ +#define MCAN_TEST_LBCK_Pos _U_(4) /**< (MCAN_TEST) Loop Back Mode (read/write) Position */ +#define MCAN_TEST_LBCK_Msk (_U_(0x1) << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back Mode (read/write) Mask */ +#define MCAN_TEST_LBCK(value) (MCAN_TEST_LBCK_Msk & ((value) << MCAN_TEST_LBCK_Pos)) +#define MCAN_TEST_LBCK_DISABLED_Val _U_(0x0) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED_Val _U_(0x1) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_LBCK_DISABLED (MCAN_TEST_LBCK_DISABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. Position */ +#define MCAN_TEST_LBCK_ENABLED (MCAN_TEST_LBCK_ENABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). Position */ +#define MCAN_TEST_TX_Pos _U_(5) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Position */ +#define MCAN_TEST_TX_Msk (_U_(0x3) << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Mask */ +#define MCAN_TEST_TX(value) (MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)) +#define MCAN_TEST_TX_RESET_Val _U_(0x0) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val _U_(0x1) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_TX_RESET (MCAN_TEST_TX_RESET_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. Position */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. Position */ +#define MCAN_TEST_TX_DOMINANT (MCAN_TEST_TX_DOMINANT_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. Position */ +#define MCAN_TEST_TX_RECESSIVE (MCAN_TEST_TX_RECESSIVE_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. Position */ +#define MCAN_TEST_RX_Pos _U_(7) /**< (MCAN_TEST) Receive Pin (read-only) Position */ +#define MCAN_TEST_RX_Msk (_U_(0x1) << MCAN_TEST_RX_Pos) /**< (MCAN_TEST) Receive Pin (read-only) Mask */ +#define MCAN_TEST_RX(value) (MCAN_TEST_RX_Msk & ((value) << MCAN_TEST_RX_Pos)) +#define MCAN_TEST_Msk _U_(0x000000F0) /**< (MCAN_TEST) Register Mask */ + + +/* -------- MCAN_RWD : (MCAN Offset: 0x14) (R/W 32) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos _U_(0) /**< (MCAN_RWD) Watchdog Configuration (read/write) Position */ +#define MCAN_RWD_WDC_Msk (_U_(0xFF) << MCAN_RWD_WDC_Pos) /**< (MCAN_RWD) Watchdog Configuration (read/write) Mask */ +#define MCAN_RWD_WDC(value) (MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)) +#define MCAN_RWD_WDV_Pos _U_(8) /**< (MCAN_RWD) Watchdog Value (read-only) Position */ +#define MCAN_RWD_WDV_Msk (_U_(0xFF) << MCAN_RWD_WDV_Pos) /**< (MCAN_RWD) Watchdog Value (read-only) Mask */ +#define MCAN_RWD_WDV(value) (MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)) +#define MCAN_RWD_Msk _U_(0x0000FFFF) /**< (MCAN_RWD) Register Mask */ + + +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) (R/W 32) CC Control Register -------- */ +#define MCAN_CCCR_INIT_Pos _U_(0) /**< (MCAN_CCCR) Initialization (read/write) Position */ +#define MCAN_CCCR_INIT_Msk (_U_(0x1) << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization (read/write) Mask */ +#define MCAN_CCCR_INIT(value) (MCAN_CCCR_INIT_Msk & ((value) << MCAN_CCCR_INIT_Pos)) +#define MCAN_CCCR_INIT_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_INIT_DISABLED (MCAN_CCCR_INIT_DISABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Normal operation. Position */ +#define MCAN_CCCR_INIT_ENABLED (MCAN_CCCR_INIT_ENABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization is started. Position */ +#define MCAN_CCCR_CCE_Pos _U_(1) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Position */ +#define MCAN_CCCR_CCE_Msk (_U_(0x1) << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_CCE(value) (MCAN_CCCR_CCE_Msk & ((value) << MCAN_CCCR_CCE_Pos)) +#define MCAN_CCCR_CCE_PROTECTED_Val _U_(0x0) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE_Val _U_(0x1) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_CCE_PROTECTED (MCAN_CCCR_CCE_PROTECTED_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. Position */ +#define MCAN_CCCR_CCE_CONFIGURABLE (MCAN_CCCR_CCE_CONFIGURABLE_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). Position */ +#define MCAN_CCCR_ASM_Pos _U_(2) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_ASM_Msk (_U_(0x1) << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_ASM(value) (MCAN_CCCR_ASM_Msk & ((value) << MCAN_CCCR_ASM_Pos)) +#define MCAN_CCCR_ASM_NORMAL_Val _U_(0x0) /**< (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED_Val _U_(0x1) /**< (MCAN_CCCR) Restricted Operation mode active. */ +#define MCAN_CCCR_ASM_NORMAL (MCAN_CCCR_ASM_NORMAL_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Normal CAN operation. Position */ +#define MCAN_CCCR_ASM_RESTRICTED (MCAN_CCCR_ASM_RESTRICTED_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation mode active. Position */ +#define MCAN_CCCR_CSA_Pos _U_(3) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Position */ +#define MCAN_CCCR_CSA_Msk (_U_(0x1) << MCAN_CCCR_CSA_Pos) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Mask */ +#define MCAN_CCCR_CSA(value) (MCAN_CCCR_CSA_Msk & ((value) << MCAN_CCCR_CSA_Pos)) +#define MCAN_CCCR_CSR_Pos _U_(4) /**< (MCAN_CCCR) Clock Stop Request (read/write) Position */ +#define MCAN_CCCR_CSR_Msk (_U_(0x1) << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock Stop Request (read/write) Mask */ +#define MCAN_CCCR_CSR(value) (MCAN_CCCR_CSR_Msk & ((value) << MCAN_CCCR_CSR_Pos)) +#define MCAN_CCCR_CSR_NO_CLOCK_STOP_Val _U_(0x0) /**< (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP_Val _U_(0x1) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (MCAN_CCCR_CSR_NO_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) No clock stop is requested. Position */ +#define MCAN_CCCR_CSR_CLOCK_STOP (MCAN_CCCR_CSR_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. Position */ +#define MCAN_CCCR_MON_Pos _U_(5) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Position */ +#define MCAN_CCCR_MON_Msk (_U_(0x1) << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_MON(value) (MCAN_CCCR_MON_Msk & ((value) << MCAN_CCCR_MON_Pos)) +#define MCAN_CCCR_MON_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_MON_DISABLED (MCAN_CCCR_MON_DISABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. Position */ +#define MCAN_CCCR_MON_ENABLED (MCAN_CCCR_MON_ENABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. Position */ +#define MCAN_CCCR_DAR_Pos _U_(6) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Position */ +#define MCAN_CCCR_DAR_Msk (_U_(0x1) << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Mask */ +#define MCAN_CCCR_DAR(value) (MCAN_CCCR_DAR_Msk & ((value) << MCAN_CCCR_DAR_Pos)) +#define MCAN_CCCR_DAR_AUTO_RETX_Val _U_(0x0) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX_Val _U_(0x1) /**< (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_DAR_AUTO_RETX (MCAN_CCCR_DAR_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. Position */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (MCAN_CCCR_DAR_NO_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission disabled. Position */ +#define MCAN_CCCR_TEST_Pos _U_(7) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Position */ +#define MCAN_CCCR_TEST_Msk (_U_(0x1) << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Mask */ +#define MCAN_CCCR_TEST(value) (MCAN_CCCR_TEST_Msk & ((value) << MCAN_CCCR_TEST_Pos)) +#define MCAN_CCCR_TEST_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_TEST_DISABLED (MCAN_CCCR_TEST_DISABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. Position */ +#define MCAN_CCCR_TEST_ENABLED (MCAN_CCCR_TEST_ENABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. Position */ +#define MCAN_CCCR_FDOE_Pos _U_(8) /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Position */ +#define MCAN_CCCR_FDOE_Msk (_U_(0x1) << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_FDOE(value) (MCAN_CCCR_FDOE_Msk & ((value) << MCAN_CCCR_FDOE_Pos)) +#define MCAN_CCCR_FDOE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) FD operation disabled. */ +#define MCAN_CCCR_FDOE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) FD operation enabled. */ +#define MCAN_CCCR_FDOE_DISABLED (MCAN_CCCR_FDOE_DISABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation disabled. Position */ +#define MCAN_CCCR_FDOE_ENABLED (MCAN_CCCR_FDOE_ENABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation enabled. Position */ +#define MCAN_CCCR_BRSE_Pos _U_(9) /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Position */ +#define MCAN_CCCR_BRSE_Msk (_U_(0x1) << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Mask */ +#define MCAN_CCCR_BRSE(value) (MCAN_CCCR_BRSE_Msk & ((value) << MCAN_CCCR_BRSE_Pos)) +#define MCAN_CCCR_BRSE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. */ +#define MCAN_CCCR_BRSE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. */ +#define MCAN_CCCR_BRSE_DISABLED (MCAN_CCCR_BRSE_DISABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. Position */ +#define MCAN_CCCR_BRSE_ENABLED (MCAN_CCCR_BRSE_ENABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. Position */ +#define MCAN_CCCR_PXHD_Pos _U_(12) /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Position */ +#define MCAN_CCCR_PXHD_Msk (_U_(0x1) << MCAN_CCCR_PXHD_Pos) /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Mask */ +#define MCAN_CCCR_PXHD(value) (MCAN_CCCR_PXHD_Msk & ((value) << MCAN_CCCR_PXHD_Pos)) +#define MCAN_CCCR_EFBI_Pos _U_(13) /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Position */ +#define MCAN_CCCR_EFBI_Msk (_U_(0x1) << MCAN_CCCR_EFBI_Pos) /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Mask */ +#define MCAN_CCCR_EFBI(value) (MCAN_CCCR_EFBI_Msk & ((value) << MCAN_CCCR_EFBI_Pos)) +#define MCAN_CCCR_TXP_Pos _U_(14) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Position */ +#define MCAN_CCCR_TXP_Msk (_U_(0x1) << MCAN_CCCR_TXP_Pos) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Mask */ +#define MCAN_CCCR_TXP(value) (MCAN_CCCR_TXP_Msk & ((value) << MCAN_CCCR_TXP_Pos)) +#define MCAN_CCCR_NISO_Pos _U_(15) /**< (MCAN_CCCR) Non-ISO Operation Position */ +#define MCAN_CCCR_NISO_Msk (_U_(0x1) << MCAN_CCCR_NISO_Pos) /**< (MCAN_CCCR) Non-ISO Operation Mask */ +#define MCAN_CCCR_NISO(value) (MCAN_CCCR_NISO_Msk & ((value) << MCAN_CCCR_NISO_Pos)) +#define MCAN_CCCR_Msk _U_(0x0000F3FF) /**< (MCAN_CCCR) Register Mask */ + + +/* -------- MCAN_NBTP : (MCAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler Register -------- */ +#define MCAN_NBTP_NTSEG2_Pos _U_(0) /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Position */ +#define MCAN_NBTP_NTSEG2_Msk (_U_(0x7F) << MCAN_NBTP_NTSEG2_Pos) /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Mask */ +#define MCAN_NBTP_NTSEG2(value) (MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)) +#define MCAN_NBTP_NTSEG1_Pos _U_(8) /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Position */ +#define MCAN_NBTP_NTSEG1_Msk (_U_(0xFF) << MCAN_NBTP_NTSEG1_Pos) /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Mask */ +#define MCAN_NBTP_NTSEG1(value) (MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)) +#define MCAN_NBTP_NBRP_Pos _U_(16) /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Position */ +#define MCAN_NBTP_NBRP_Msk (_U_(0x1FF) << MCAN_NBTP_NBRP_Pos) /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Mask */ +#define MCAN_NBTP_NBRP(value) (MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)) +#define MCAN_NBTP_NSJW_Pos _U_(25) /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Position */ +#define MCAN_NBTP_NSJW_Msk (_U_(0x7F) << MCAN_NBTP_NSJW_Pos) /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Mask */ +#define MCAN_NBTP_NSJW(value) (MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)) +#define MCAN_NBTP_Msk _U_(0xFFFFFF7F) /**< (MCAN_NBTP) Register Mask */ + + +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos _U_(0) /**< (MCAN_TSCC) Timestamp Select Position */ +#define MCAN_TSCC_TSS_Msk (_U_(0x3) << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp Select Mask */ +#define MCAN_TSCC_TSS(value) (MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)) +#define MCAN_TSCC_TSS_ALWAYS_0_Val _U_(0x0) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC_Val _U_(0x1) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP_Val _U_(0x2) /**< (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TSS_ALWAYS_0 (MCAN_TSCC_TSS_ALWAYS_0_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 Position */ +#define MCAN_TSCC_TSS_TCP_INC (MCAN_TSCC_TSS_TCP_INC_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP Position */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (MCAN_TSCC_TSS_EXT_TIMESTAMP_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) External timestamp counter value used Position */ +#define MCAN_TSCC_TCP_Pos _U_(16) /**< (MCAN_TSCC) Timestamp Counter Prescaler Position */ +#define MCAN_TSCC_TCP_Msk (_U_(0xF) << MCAN_TSCC_TCP_Pos) /**< (MCAN_TSCC) Timestamp Counter Prescaler Mask */ +#define MCAN_TSCC_TCP(value) (MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)) +#define MCAN_TSCC_Msk _U_(0x000F0003) /**< (MCAN_TSCC) Register Mask */ + + +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) (R/W 32) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos _U_(0) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Position */ +#define MCAN_TSCV_TSC_Msk (_U_(0xFFFF) << MCAN_TSCV_TSC_Pos) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Mask */ +#define MCAN_TSCV_TSC(value) (MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)) +#define MCAN_TSCV_Msk _U_(0x0000FFFF) /**< (MCAN_TSCV) Register Mask */ + + +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) (R/W 32) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC_Pos _U_(0) /**< (MCAN_TOCC) Enable Timeout Counter Position */ +#define MCAN_TOCC_ETOC_Msk (_U_(0x1) << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Enable Timeout Counter Mask */ +#define MCAN_TOCC_ETOC(value) (MCAN_TOCC_ETOC_Msk & ((value) << MCAN_TOCC_ETOC_Pos)) +#define MCAN_TOCC_ETOC_NO_TIMEOUT_Val _U_(0x0) /**< (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED_Val _U_(0x1) /**< (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (MCAN_TOCC_ETOC_NO_TIMEOUT_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter disabled. Position */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (MCAN_TOCC_ETOC_TOS_CONTROLLED_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter enabled. Position */ +#define MCAN_TOCC_TOS_Pos _U_(1) /**< (MCAN_TOCC) Timeout Select Position */ +#define MCAN_TOCC_TOS_Msk (_U_(0x3) << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout Select Mask */ +#define MCAN_TOCC_TOS(value) (MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)) +#define MCAN_TOCC_TOS_CONTINUOUS_Val _U_(0x0) /**< (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val _U_(0x1) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val _U_(0x2) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val _U_(0x3) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOS_CONTINUOUS (MCAN_TOCC_TOS_CONTINUOUS_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Continuous operation Position */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO Position */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 Position */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 Position */ +#define MCAN_TOCC_TOP_Pos _U_(16) /**< (MCAN_TOCC) Timeout Period Position */ +#define MCAN_TOCC_TOP_Msk (_U_(0xFFFF) << MCAN_TOCC_TOP_Pos) /**< (MCAN_TOCC) Timeout Period Mask */ +#define MCAN_TOCC_TOP(value) (MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)) +#define MCAN_TOCC_Msk _U_(0xFFFF0007) /**< (MCAN_TOCC) Register Mask */ + + +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) (R/W 32) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos _U_(0) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Position */ +#define MCAN_TOCV_TOC_Msk (_U_(0xFFFF) << MCAN_TOCV_TOC_Pos) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Mask */ +#define MCAN_TOCV_TOC(value) (MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)) +#define MCAN_TOCV_Msk _U_(0x0000FFFF) /**< (MCAN_TOCV) Register Mask */ + + +/* -------- MCAN_ECR : (MCAN Offset: 0x40) ( R/ 32) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos _U_(0) /**< (MCAN_ECR) Transmit Error Counter Position */ +#define MCAN_ECR_TEC_Msk (_U_(0xFF) << MCAN_ECR_TEC_Pos) /**< (MCAN_ECR) Transmit Error Counter Mask */ +#define MCAN_ECR_TEC(value) (MCAN_ECR_TEC_Msk & ((value) << MCAN_ECR_TEC_Pos)) +#define MCAN_ECR_REC_Pos _U_(8) /**< (MCAN_ECR) Receive Error Counter Position */ +#define MCAN_ECR_REC_Msk (_U_(0x7F) << MCAN_ECR_REC_Pos) /**< (MCAN_ECR) Receive Error Counter Mask */ +#define MCAN_ECR_REC(value) (MCAN_ECR_REC_Msk & ((value) << MCAN_ECR_REC_Pos)) +#define MCAN_ECR_RP_Pos _U_(15) /**< (MCAN_ECR) Receive Error Passive Position */ +#define MCAN_ECR_RP_Msk (_U_(0x1) << MCAN_ECR_RP_Pos) /**< (MCAN_ECR) Receive Error Passive Mask */ +#define MCAN_ECR_RP(value) (MCAN_ECR_RP_Msk & ((value) << MCAN_ECR_RP_Pos)) +#define MCAN_ECR_CEL_Pos _U_(16) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Position */ +#define MCAN_ECR_CEL_Msk (_U_(0xFF) << MCAN_ECR_CEL_Pos) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Mask */ +#define MCAN_ECR_CEL(value) (MCAN_ECR_CEL_Msk & ((value) << MCAN_ECR_CEL_Pos)) +#define MCAN_ECR_Msk _U_(0x00FFFFFF) /**< (MCAN_ECR) Register Mask */ + + +/* -------- MCAN_PSR : (MCAN Offset: 0x44) ( R/ 32) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos _U_(0) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_LEC_Msk (_U_(0x7) << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_LEC(value) (MCAN_PSR_LEC_Msk & ((value) << MCAN_PSR_LEC_Pos)) +#define MCAN_PSR_LEC_NO_ERROR_Val _U_(0x0) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR_Val _U_(0x1) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR_Val _U_(0x2) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR_Val _U_(0x3) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR_Val _U_(0x4) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR_Val _U_(0x5) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR_Val _U_(0x6) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE_Val _U_(0x7) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_LEC_NO_ERROR (MCAN_PSR_LEC_NO_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. Position */ +#define MCAN_PSR_LEC_STUFF_ERROR (MCAN_PSR_LEC_STUFF_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Position */ +#define MCAN_PSR_LEC_FORM_ERROR (MCAN_PSR_LEC_FORM_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. Position */ +#define MCAN_PSR_LEC_ACK_ERROR (MCAN_PSR_LEC_ACK_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. Position */ +#define MCAN_PSR_LEC_BIT1_ERROR (MCAN_PSR_LEC_BIT1_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. Position */ +#define MCAN_PSR_LEC_BIT0_ERROR (MCAN_PSR_LEC_BIT0_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). Position */ +#define MCAN_PSR_LEC_CRC_ERROR (MCAN_PSR_LEC_CRC_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. Position */ +#define MCAN_PSR_LEC_NO_CHANGE (MCAN_PSR_LEC_NO_CHANGE_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. Position */ +#define MCAN_PSR_ACT_Pos _U_(3) /**< (MCAN_PSR) Activity Position */ +#define MCAN_PSR_ACT_Msk (_U_(0x3) << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Activity Mask */ +#define MCAN_PSR_ACT(value) (MCAN_PSR_ACT_Msk & ((value) << MCAN_PSR_ACT_Pos)) +#define MCAN_PSR_ACT_SYNCHRONIZING_Val _U_(0x0) /**< (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER_Val _U_(0x2) /**< (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER_Val _U_(0x3) /**< (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_ACT_SYNCHRONIZING (MCAN_PSR_ACT_SYNCHRONIZING_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is synchronizing on CAN communication Position */ +#define MCAN_PSR_ACT_IDLE (MCAN_PSR_ACT_IDLE_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is neither receiver nor transmitter Position */ +#define MCAN_PSR_ACT_RECEIVER (MCAN_PSR_ACT_RECEIVER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as receiver Position */ +#define MCAN_PSR_ACT_TRANSMITTER (MCAN_PSR_ACT_TRANSMITTER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as transmitter Position */ +#define MCAN_PSR_EP_Pos _U_(5) /**< (MCAN_PSR) Error Passive Position */ +#define MCAN_PSR_EP_Msk (_U_(0x1) << MCAN_PSR_EP_Pos) /**< (MCAN_PSR) Error Passive Mask */ +#define MCAN_PSR_EP(value) (MCAN_PSR_EP_Msk & ((value) << MCAN_PSR_EP_Pos)) +#define MCAN_PSR_EW_Pos _U_(6) /**< (MCAN_PSR) Warning Status Position */ +#define MCAN_PSR_EW_Msk (_U_(0x1) << MCAN_PSR_EW_Pos) /**< (MCAN_PSR) Warning Status Mask */ +#define MCAN_PSR_EW(value) (MCAN_PSR_EW_Msk & ((value) << MCAN_PSR_EW_Pos)) +#define MCAN_PSR_BO_Pos _U_(7) /**< (MCAN_PSR) Bus_Off Status Position */ +#define MCAN_PSR_BO_Msk (_U_(0x1) << MCAN_PSR_BO_Pos) /**< (MCAN_PSR) Bus_Off Status Mask */ +#define MCAN_PSR_BO(value) (MCAN_PSR_BO_Msk & ((value) << MCAN_PSR_BO_Pos)) +#define MCAN_PSR_DLEC_Pos _U_(8) /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Position */ +#define MCAN_PSR_DLEC_Msk (_U_(0x7) << MCAN_PSR_DLEC_Pos) /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Mask */ +#define MCAN_PSR_DLEC(value) (MCAN_PSR_DLEC_Msk & ((value) << MCAN_PSR_DLEC_Pos)) +#define MCAN_PSR_RESI_Pos _U_(11) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RESI_Msk (_U_(0x1) << MCAN_PSR_RESI_Pos) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RESI(value) (MCAN_PSR_RESI_Msk & ((value) << MCAN_PSR_RESI_Pos)) +#define MCAN_PSR_RBRS_Pos _U_(12) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RBRS_Msk (_U_(0x1) << MCAN_PSR_RBRS_Pos) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RBRS(value) (MCAN_PSR_RBRS_Msk & ((value) << MCAN_PSR_RBRS_Pos)) +#define MCAN_PSR_RFDF_Pos _U_(13) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Position */ +#define MCAN_PSR_RFDF_Msk (_U_(0x1) << MCAN_PSR_RFDF_Pos) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Mask */ +#define MCAN_PSR_RFDF(value) (MCAN_PSR_RFDF_Msk & ((value) << MCAN_PSR_RFDF_Pos)) +#define MCAN_PSR_PXE_Pos _U_(14) /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Position */ +#define MCAN_PSR_PXE_Msk (_U_(0x1) << MCAN_PSR_PXE_Pos) /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Mask */ +#define MCAN_PSR_PXE(value) (MCAN_PSR_PXE_Msk & ((value) << MCAN_PSR_PXE_Pos)) +#define MCAN_PSR_TDCV_Pos _U_(16) /**< (MCAN_PSR) Transmitter Delay Compensation Value Position */ +#define MCAN_PSR_TDCV_Msk (_U_(0x7F) << MCAN_PSR_TDCV_Pos) /**< (MCAN_PSR) Transmitter Delay Compensation Value Mask */ +#define MCAN_PSR_TDCV(value) (MCAN_PSR_TDCV_Msk & ((value) << MCAN_PSR_TDCV_Pos)) +#define MCAN_PSR_Msk _U_(0x007F7FFF) /**< (MCAN_PSR) Register Mask */ + + +/* -------- MCAN_TDCR : (MCAN Offset: 0x48) (R/W 32) Transmit Delay Compensation Register -------- */ +#define MCAN_TDCR_TDCF_Pos _U_(0) /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Position */ +#define MCAN_TDCR_TDCF_Msk (_U_(0x7F) << MCAN_TDCR_TDCF_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Mask */ +#define MCAN_TDCR_TDCF(value) (MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)) +#define MCAN_TDCR_TDCO_Pos _U_(8) /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Position */ +#define MCAN_TDCR_TDCO_Msk (_U_(0x7F) << MCAN_TDCR_TDCO_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Mask */ +#define MCAN_TDCR_TDCO(value) (MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)) +#define MCAN_TDCR_Msk _U_(0x00007F7F) /**< (MCAN_TDCR) Register Mask */ + + +/* -------- MCAN_IR : (MCAN Offset: 0x50) (R/W 32) Interrupt Register -------- */ +#define MCAN_IR_RF0N_Pos _U_(0) /**< (MCAN_IR) Receive FIFO 0 New Message Position */ +#define MCAN_IR_RF0N_Msk (_U_(0x1) << MCAN_IR_RF0N_Pos) /**< (MCAN_IR) Receive FIFO 0 New Message Mask */ +#define MCAN_IR_RF0N(value) (MCAN_IR_RF0N_Msk & ((value) << MCAN_IR_RF0N_Pos)) +#define MCAN_IR_RF0W_Pos _U_(1) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Position */ +#define MCAN_IR_RF0W_Msk (_U_(0x1) << MCAN_IR_RF0W_Pos) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Mask */ +#define MCAN_IR_RF0W(value) (MCAN_IR_RF0W_Msk & ((value) << MCAN_IR_RF0W_Pos)) +#define MCAN_IR_RF0F_Pos _U_(2) /**< (MCAN_IR) Receive FIFO 0 Full Position */ +#define MCAN_IR_RF0F_Msk (_U_(0x1) << MCAN_IR_RF0F_Pos) /**< (MCAN_IR) Receive FIFO 0 Full Mask */ +#define MCAN_IR_RF0F(value) (MCAN_IR_RF0F_Msk & ((value) << MCAN_IR_RF0F_Pos)) +#define MCAN_IR_RF0L_Pos _U_(3) /**< (MCAN_IR) Receive FIFO 0 Message Lost Position */ +#define MCAN_IR_RF0L_Msk (_U_(0x1) << MCAN_IR_RF0L_Pos) /**< (MCAN_IR) Receive FIFO 0 Message Lost Mask */ +#define MCAN_IR_RF0L(value) (MCAN_IR_RF0L_Msk & ((value) << MCAN_IR_RF0L_Pos)) +#define MCAN_IR_RF1N_Pos _U_(4) /**< (MCAN_IR) Receive FIFO 1 New Message Position */ +#define MCAN_IR_RF1N_Msk (_U_(0x1) << MCAN_IR_RF1N_Pos) /**< (MCAN_IR) Receive FIFO 1 New Message Mask */ +#define MCAN_IR_RF1N(value) (MCAN_IR_RF1N_Msk & ((value) << MCAN_IR_RF1N_Pos)) +#define MCAN_IR_RF1W_Pos _U_(5) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Position */ +#define MCAN_IR_RF1W_Msk (_U_(0x1) << MCAN_IR_RF1W_Pos) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Mask */ +#define MCAN_IR_RF1W(value) (MCAN_IR_RF1W_Msk & ((value) << MCAN_IR_RF1W_Pos)) +#define MCAN_IR_RF1F_Pos _U_(6) /**< (MCAN_IR) Receive FIFO 1 Full Position */ +#define MCAN_IR_RF1F_Msk (_U_(0x1) << MCAN_IR_RF1F_Pos) /**< (MCAN_IR) Receive FIFO 1 Full Mask */ +#define MCAN_IR_RF1F(value) (MCAN_IR_RF1F_Msk & ((value) << MCAN_IR_RF1F_Pos)) +#define MCAN_IR_RF1L_Pos _U_(7) /**< (MCAN_IR) Receive FIFO 1 Message Lost Position */ +#define MCAN_IR_RF1L_Msk (_U_(0x1) << MCAN_IR_RF1L_Pos) /**< (MCAN_IR) Receive FIFO 1 Message Lost Mask */ +#define MCAN_IR_RF1L(value) (MCAN_IR_RF1L_Msk & ((value) << MCAN_IR_RF1L_Pos)) +#define MCAN_IR_HPM_Pos _U_(8) /**< (MCAN_IR) High Priority Message Position */ +#define MCAN_IR_HPM_Msk (_U_(0x1) << MCAN_IR_HPM_Pos) /**< (MCAN_IR) High Priority Message Mask */ +#define MCAN_IR_HPM(value) (MCAN_IR_HPM_Msk & ((value) << MCAN_IR_HPM_Pos)) +#define MCAN_IR_TC_Pos _U_(9) /**< (MCAN_IR) Transmission Completed Position */ +#define MCAN_IR_TC_Msk (_U_(0x1) << MCAN_IR_TC_Pos) /**< (MCAN_IR) Transmission Completed Mask */ +#define MCAN_IR_TC(value) (MCAN_IR_TC_Msk & ((value) << MCAN_IR_TC_Pos)) +#define MCAN_IR_TCF_Pos _U_(10) /**< (MCAN_IR) Transmission Cancellation Finished Position */ +#define MCAN_IR_TCF_Msk (_U_(0x1) << MCAN_IR_TCF_Pos) /**< (MCAN_IR) Transmission Cancellation Finished Mask */ +#define MCAN_IR_TCF(value) (MCAN_IR_TCF_Msk & ((value) << MCAN_IR_TCF_Pos)) +#define MCAN_IR_TFE_Pos _U_(11) /**< (MCAN_IR) Tx FIFO Empty Position */ +#define MCAN_IR_TFE_Msk (_U_(0x1) << MCAN_IR_TFE_Pos) /**< (MCAN_IR) Tx FIFO Empty Mask */ +#define MCAN_IR_TFE(value) (MCAN_IR_TFE_Msk & ((value) << MCAN_IR_TFE_Pos)) +#define MCAN_IR_TEFN_Pos _U_(12) /**< (MCAN_IR) Tx Event FIFO New Entry Position */ +#define MCAN_IR_TEFN_Msk (_U_(0x1) << MCAN_IR_TEFN_Pos) /**< (MCAN_IR) Tx Event FIFO New Entry Mask */ +#define MCAN_IR_TEFN(value) (MCAN_IR_TEFN_Msk & ((value) << MCAN_IR_TEFN_Pos)) +#define MCAN_IR_TEFW_Pos _U_(13) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Position */ +#define MCAN_IR_TEFW_Msk (_U_(0x1) << MCAN_IR_TEFW_Pos) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Mask */ +#define MCAN_IR_TEFW(value) (MCAN_IR_TEFW_Msk & ((value) << MCAN_IR_TEFW_Pos)) +#define MCAN_IR_TEFF_Pos _U_(14) /**< (MCAN_IR) Tx Event FIFO Full Position */ +#define MCAN_IR_TEFF_Msk (_U_(0x1) << MCAN_IR_TEFF_Pos) /**< (MCAN_IR) Tx Event FIFO Full Mask */ +#define MCAN_IR_TEFF(value) (MCAN_IR_TEFF_Msk & ((value) << MCAN_IR_TEFF_Pos)) +#define MCAN_IR_TEFL_Pos _U_(15) /**< (MCAN_IR) Tx Event FIFO Element Lost Position */ +#define MCAN_IR_TEFL_Msk (_U_(0x1) << MCAN_IR_TEFL_Pos) /**< (MCAN_IR) Tx Event FIFO Element Lost Mask */ +#define MCAN_IR_TEFL(value) (MCAN_IR_TEFL_Msk & ((value) << MCAN_IR_TEFL_Pos)) +#define MCAN_IR_TSW_Pos _U_(16) /**< (MCAN_IR) Timestamp Wraparound Position */ +#define MCAN_IR_TSW_Msk (_U_(0x1) << MCAN_IR_TSW_Pos) /**< (MCAN_IR) Timestamp Wraparound Mask */ +#define MCAN_IR_TSW(value) (MCAN_IR_TSW_Msk & ((value) << MCAN_IR_TSW_Pos)) +#define MCAN_IR_MRAF_Pos _U_(17) /**< (MCAN_IR) Message RAM Access Failure Position */ +#define MCAN_IR_MRAF_Msk (_U_(0x1) << MCAN_IR_MRAF_Pos) /**< (MCAN_IR) Message RAM Access Failure Mask */ +#define MCAN_IR_MRAF(value) (MCAN_IR_MRAF_Msk & ((value) << MCAN_IR_MRAF_Pos)) +#define MCAN_IR_TOO_Pos _U_(18) /**< (MCAN_IR) Timeout Occurred Position */ +#define MCAN_IR_TOO_Msk (_U_(0x1) << MCAN_IR_TOO_Pos) /**< (MCAN_IR) Timeout Occurred Mask */ +#define MCAN_IR_TOO(value) (MCAN_IR_TOO_Msk & ((value) << MCAN_IR_TOO_Pos)) +#define MCAN_IR_DRX_Pos _U_(19) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Position */ +#define MCAN_IR_DRX_Msk (_U_(0x1) << MCAN_IR_DRX_Pos) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Mask */ +#define MCAN_IR_DRX(value) (MCAN_IR_DRX_Msk & ((value) << MCAN_IR_DRX_Pos)) +#define MCAN_IR_ELO_Pos _U_(22) /**< (MCAN_IR) Error Logging Overflow Position */ +#define MCAN_IR_ELO_Msk (_U_(0x1) << MCAN_IR_ELO_Pos) /**< (MCAN_IR) Error Logging Overflow Mask */ +#define MCAN_IR_ELO(value) (MCAN_IR_ELO_Msk & ((value) << MCAN_IR_ELO_Pos)) +#define MCAN_IR_EP_Pos _U_(23) /**< (MCAN_IR) Error Passive Position */ +#define MCAN_IR_EP_Msk (_U_(0x1) << MCAN_IR_EP_Pos) /**< (MCAN_IR) Error Passive Mask */ +#define MCAN_IR_EP(value) (MCAN_IR_EP_Msk & ((value) << MCAN_IR_EP_Pos)) +#define MCAN_IR_EW_Pos _U_(24) /**< (MCAN_IR) Warning Status Position */ +#define MCAN_IR_EW_Msk (_U_(0x1) << MCAN_IR_EW_Pos) /**< (MCAN_IR) Warning Status Mask */ +#define MCAN_IR_EW(value) (MCAN_IR_EW_Msk & ((value) << MCAN_IR_EW_Pos)) +#define MCAN_IR_BO_Pos _U_(25) /**< (MCAN_IR) Bus_Off Status Position */ +#define MCAN_IR_BO_Msk (_U_(0x1) << MCAN_IR_BO_Pos) /**< (MCAN_IR) Bus_Off Status Mask */ +#define MCAN_IR_BO(value) (MCAN_IR_BO_Msk & ((value) << MCAN_IR_BO_Pos)) +#define MCAN_IR_WDI_Pos _U_(26) /**< (MCAN_IR) Watchdog Interrupt Position */ +#define MCAN_IR_WDI_Msk (_U_(0x1) << MCAN_IR_WDI_Pos) /**< (MCAN_IR) Watchdog Interrupt Mask */ +#define MCAN_IR_WDI(value) (MCAN_IR_WDI_Msk & ((value) << MCAN_IR_WDI_Pos)) +#define MCAN_IR_PEA_Pos _U_(27) /**< (MCAN_IR) Protocol Error in Arbitration Phase Position */ +#define MCAN_IR_PEA_Msk (_U_(0x1) << MCAN_IR_PEA_Pos) /**< (MCAN_IR) Protocol Error in Arbitration Phase Mask */ +#define MCAN_IR_PEA(value) (MCAN_IR_PEA_Msk & ((value) << MCAN_IR_PEA_Pos)) +#define MCAN_IR_PED_Pos _U_(28) /**< (MCAN_IR) Protocol Error in Data Phase Position */ +#define MCAN_IR_PED_Msk (_U_(0x1) << MCAN_IR_PED_Pos) /**< (MCAN_IR) Protocol Error in Data Phase Mask */ +#define MCAN_IR_PED(value) (MCAN_IR_PED_Msk & ((value) << MCAN_IR_PED_Pos)) +#define MCAN_IR_ARA_Pos _U_(29) /**< (MCAN_IR) Access to Reserved Address Position */ +#define MCAN_IR_ARA_Msk (_U_(0x1) << MCAN_IR_ARA_Pos) /**< (MCAN_IR) Access to Reserved Address Mask */ +#define MCAN_IR_ARA(value) (MCAN_IR_ARA_Msk & ((value) << MCAN_IR_ARA_Pos)) +#define MCAN_IR_Msk _U_(0x3FCFFFFF) /**< (MCAN_IR) Register Mask */ + + +/* -------- MCAN_IE : (MCAN Offset: 0x54) (R/W 32) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE_Pos _U_(0) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Position */ +#define MCAN_IE_RF0NE_Msk (_U_(0x1) << MCAN_IE_RF0NE_Pos) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF0NE(value) (MCAN_IE_RF0NE_Msk & ((value) << MCAN_IE_RF0NE_Pos)) +#define MCAN_IE_RF0WE_Pos _U_(1) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF0WE_Msk (_U_(0x1) << MCAN_IE_RF0WE_Pos) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF0WE(value) (MCAN_IE_RF0WE_Msk & ((value) << MCAN_IE_RF0WE_Pos)) +#define MCAN_IE_RF0FE_Pos _U_(2) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Position */ +#define MCAN_IE_RF0FE_Msk (_U_(0x1) << MCAN_IE_RF0FE_Pos) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Mask */ +#define MCAN_IE_RF0FE(value) (MCAN_IE_RF0FE_Msk & ((value) << MCAN_IE_RF0FE_Pos)) +#define MCAN_IE_RF0LE_Pos _U_(3) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF0LE_Msk (_U_(0x1) << MCAN_IE_RF0LE_Pos) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF0LE(value) (MCAN_IE_RF0LE_Msk & ((value) << MCAN_IE_RF0LE_Pos)) +#define MCAN_IE_RF1NE_Pos _U_(4) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Position */ +#define MCAN_IE_RF1NE_Msk (_U_(0x1) << MCAN_IE_RF1NE_Pos) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Mask */ +#define MCAN_IE_RF1NE(value) (MCAN_IE_RF1NE_Msk & ((value) << MCAN_IE_RF1NE_Pos)) +#define MCAN_IE_RF1WE_Pos _U_(5) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_RF1WE_Msk (_U_(0x1) << MCAN_IE_RF1WE_Pos) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_RF1WE(value) (MCAN_IE_RF1WE_Msk & ((value) << MCAN_IE_RF1WE_Pos)) +#define MCAN_IE_RF1FE_Pos _U_(6) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Position */ +#define MCAN_IE_RF1FE_Msk (_U_(0x1) << MCAN_IE_RF1FE_Pos) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Mask */ +#define MCAN_IE_RF1FE(value) (MCAN_IE_RF1FE_Msk & ((value) << MCAN_IE_RF1FE_Pos)) +#define MCAN_IE_RF1LE_Pos _U_(7) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Position */ +#define MCAN_IE_RF1LE_Msk (_U_(0x1) << MCAN_IE_RF1LE_Pos) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Mask */ +#define MCAN_IE_RF1LE(value) (MCAN_IE_RF1LE_Msk & ((value) << MCAN_IE_RF1LE_Pos)) +#define MCAN_IE_HPME_Pos _U_(8) /**< (MCAN_IE) High Priority Message Interrupt Enable Position */ +#define MCAN_IE_HPME_Msk (_U_(0x1) << MCAN_IE_HPME_Pos) /**< (MCAN_IE) High Priority Message Interrupt Enable Mask */ +#define MCAN_IE_HPME(value) (MCAN_IE_HPME_Msk & ((value) << MCAN_IE_HPME_Pos)) +#define MCAN_IE_TCE_Pos _U_(9) /**< (MCAN_IE) Transmission Completed Interrupt Enable Position */ +#define MCAN_IE_TCE_Msk (_U_(0x1) << MCAN_IE_TCE_Pos) /**< (MCAN_IE) Transmission Completed Interrupt Enable Mask */ +#define MCAN_IE_TCE(value) (MCAN_IE_TCE_Msk & ((value) << MCAN_IE_TCE_Pos)) +#define MCAN_IE_TCFE_Pos _U_(10) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ +#define MCAN_IE_TCFE_Msk (_U_(0x1) << MCAN_IE_TCFE_Pos) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ +#define MCAN_IE_TCFE(value) (MCAN_IE_TCFE_Msk & ((value) << MCAN_IE_TCFE_Pos)) +#define MCAN_IE_TFEE_Pos _U_(11) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Position */ +#define MCAN_IE_TFEE_Msk (_U_(0x1) << MCAN_IE_TFEE_Pos) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Mask */ +#define MCAN_IE_TFEE(value) (MCAN_IE_TFEE_Msk & ((value) << MCAN_IE_TFEE_Pos)) +#define MCAN_IE_TEFNE_Pos _U_(12) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ +#define MCAN_IE_TEFNE_Msk (_U_(0x1) << MCAN_IE_TEFNE_Pos) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ +#define MCAN_IE_TEFNE(value) (MCAN_IE_TEFNE_Msk & ((value) << MCAN_IE_TEFNE_Pos)) +#define MCAN_IE_TEFWE_Pos _U_(13) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ +#define MCAN_IE_TEFWE_Msk (_U_(0x1) << MCAN_IE_TEFWE_Pos) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ +#define MCAN_IE_TEFWE(value) (MCAN_IE_TEFWE_Msk & ((value) << MCAN_IE_TEFWE_Pos)) +#define MCAN_IE_TEFFE_Pos _U_(14) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Position */ +#define MCAN_IE_TEFFE_Msk (_U_(0x1) << MCAN_IE_TEFFE_Pos) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ +#define MCAN_IE_TEFFE(value) (MCAN_IE_TEFFE_Msk & ((value) << MCAN_IE_TEFFE_Pos)) +#define MCAN_IE_TEFLE_Pos _U_(15) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Position */ +#define MCAN_IE_TEFLE_Msk (_U_(0x1) << MCAN_IE_TEFLE_Pos) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Mask */ +#define MCAN_IE_TEFLE(value) (MCAN_IE_TEFLE_Msk & ((value) << MCAN_IE_TEFLE_Pos)) +#define MCAN_IE_TSWE_Pos _U_(16) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Position */ +#define MCAN_IE_TSWE_Msk (_U_(0x1) << MCAN_IE_TSWE_Pos) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Mask */ +#define MCAN_IE_TSWE(value) (MCAN_IE_TSWE_Msk & ((value) << MCAN_IE_TSWE_Pos)) +#define MCAN_IE_MRAFE_Pos _U_(17) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Position */ +#define MCAN_IE_MRAFE_Msk (_U_(0x1) << MCAN_IE_MRAFE_Pos) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Mask */ +#define MCAN_IE_MRAFE(value) (MCAN_IE_MRAFE_Msk & ((value) << MCAN_IE_MRAFE_Pos)) +#define MCAN_IE_TOOE_Pos _U_(18) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Position */ +#define MCAN_IE_TOOE_Msk (_U_(0x1) << MCAN_IE_TOOE_Pos) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Mask */ +#define MCAN_IE_TOOE(value) (MCAN_IE_TOOE_Msk & ((value) << MCAN_IE_TOOE_Pos)) +#define MCAN_IE_DRXE_Pos _U_(19) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Position */ +#define MCAN_IE_DRXE_Msk (_U_(0x1) << MCAN_IE_DRXE_Pos) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Mask */ +#define MCAN_IE_DRXE(value) (MCAN_IE_DRXE_Msk & ((value) << MCAN_IE_DRXE_Pos)) +#define MCAN_IE_ELOE_Pos _U_(22) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Position */ +#define MCAN_IE_ELOE_Msk (_U_(0x1) << MCAN_IE_ELOE_Pos) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Mask */ +#define MCAN_IE_ELOE(value) (MCAN_IE_ELOE_Msk & ((value) << MCAN_IE_ELOE_Pos)) +#define MCAN_IE_EPE_Pos _U_(23) /**< (MCAN_IE) Error Passive Interrupt Enable Position */ +#define MCAN_IE_EPE_Msk (_U_(0x1) << MCAN_IE_EPE_Pos) /**< (MCAN_IE) Error Passive Interrupt Enable Mask */ +#define MCAN_IE_EPE(value) (MCAN_IE_EPE_Msk & ((value) << MCAN_IE_EPE_Pos)) +#define MCAN_IE_EWE_Pos _U_(24) /**< (MCAN_IE) Warning Status Interrupt Enable Position */ +#define MCAN_IE_EWE_Msk (_U_(0x1) << MCAN_IE_EWE_Pos) /**< (MCAN_IE) Warning Status Interrupt Enable Mask */ +#define MCAN_IE_EWE(value) (MCAN_IE_EWE_Msk & ((value) << MCAN_IE_EWE_Pos)) +#define MCAN_IE_BOE_Pos _U_(25) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Position */ +#define MCAN_IE_BOE_Msk (_U_(0x1) << MCAN_IE_BOE_Pos) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Mask */ +#define MCAN_IE_BOE(value) (MCAN_IE_BOE_Msk & ((value) << MCAN_IE_BOE_Pos)) +#define MCAN_IE_WDIE_Pos _U_(26) /**< (MCAN_IE) Watchdog Interrupt Enable Position */ +#define MCAN_IE_WDIE_Msk (_U_(0x1) << MCAN_IE_WDIE_Pos) /**< (MCAN_IE) Watchdog Interrupt Enable Mask */ +#define MCAN_IE_WDIE(value) (MCAN_IE_WDIE_Msk & ((value) << MCAN_IE_WDIE_Pos)) +#define MCAN_IE_PEAE_Pos _U_(27) /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Position */ +#define MCAN_IE_PEAE_Msk (_U_(0x1) << MCAN_IE_PEAE_Pos) /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Mask */ +#define MCAN_IE_PEAE(value) (MCAN_IE_PEAE_Msk & ((value) << MCAN_IE_PEAE_Pos)) +#define MCAN_IE_PEDE_Pos _U_(28) /**< (MCAN_IE) Protocol Error in Data Phase Enable Position */ +#define MCAN_IE_PEDE_Msk (_U_(0x1) << MCAN_IE_PEDE_Pos) /**< (MCAN_IE) Protocol Error in Data Phase Enable Mask */ +#define MCAN_IE_PEDE(value) (MCAN_IE_PEDE_Msk & ((value) << MCAN_IE_PEDE_Pos)) +#define MCAN_IE_ARAE_Pos _U_(29) /**< (MCAN_IE) Access to Reserved Address Enable Position */ +#define MCAN_IE_ARAE_Msk (_U_(0x1) << MCAN_IE_ARAE_Pos) /**< (MCAN_IE) Access to Reserved Address Enable Mask */ +#define MCAN_IE_ARAE(value) (MCAN_IE_ARAE_Msk & ((value) << MCAN_IE_ARAE_Pos)) +#define MCAN_IE_Msk _U_(0x3FCFFFFF) /**< (MCAN_IE) Register Mask */ + + +/* -------- MCAN_ILS : (MCAN Offset: 0x58) (R/W 32) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL_Pos _U_(0) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Position */ +#define MCAN_ILS_RF0NL_Msk (_U_(0x1) << MCAN_ILS_RF0NL_Pos) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF0NL(value) (MCAN_ILS_RF0NL_Msk & ((value) << MCAN_ILS_RF0NL_Pos)) +#define MCAN_ILS_RF0WL_Pos _U_(1) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF0WL_Msk (_U_(0x1) << MCAN_ILS_RF0WL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF0WL(value) (MCAN_ILS_RF0WL_Msk & ((value) << MCAN_ILS_RF0WL_Pos)) +#define MCAN_ILS_RF0FL_Pos _U_(2) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Position */ +#define MCAN_ILS_RF0FL_Msk (_U_(0x1) << MCAN_ILS_RF0FL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Mask */ +#define MCAN_ILS_RF0FL(value) (MCAN_ILS_RF0FL_Msk & ((value) << MCAN_ILS_RF0FL_Pos)) +#define MCAN_ILS_RF0LL_Pos _U_(3) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF0LL_Msk (_U_(0x1) << MCAN_ILS_RF0LL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF0LL(value) (MCAN_ILS_RF0LL_Msk & ((value) << MCAN_ILS_RF0LL_Pos)) +#define MCAN_ILS_RF1NL_Pos _U_(4) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Position */ +#define MCAN_ILS_RF1NL_Msk (_U_(0x1) << MCAN_ILS_RF1NL_Pos) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Mask */ +#define MCAN_ILS_RF1NL(value) (MCAN_ILS_RF1NL_Msk & ((value) << MCAN_ILS_RF1NL_Pos)) +#define MCAN_ILS_RF1WL_Pos _U_(5) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_RF1WL_Msk (_U_(0x1) << MCAN_ILS_RF1WL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_RF1WL(value) (MCAN_ILS_RF1WL_Msk & ((value) << MCAN_ILS_RF1WL_Pos)) +#define MCAN_ILS_RF1FL_Pos _U_(6) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Position */ +#define MCAN_ILS_RF1FL_Msk (_U_(0x1) << MCAN_ILS_RF1FL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Mask */ +#define MCAN_ILS_RF1FL(value) (MCAN_ILS_RF1FL_Msk & ((value) << MCAN_ILS_RF1FL_Pos)) +#define MCAN_ILS_RF1LL_Pos _U_(7) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Position */ +#define MCAN_ILS_RF1LL_Msk (_U_(0x1) << MCAN_ILS_RF1LL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Mask */ +#define MCAN_ILS_RF1LL(value) (MCAN_ILS_RF1LL_Msk & ((value) << MCAN_ILS_RF1LL_Pos)) +#define MCAN_ILS_HPML_Pos _U_(8) /**< (MCAN_ILS) High Priority Message Interrupt Line Position */ +#define MCAN_ILS_HPML_Msk (_U_(0x1) << MCAN_ILS_HPML_Pos) /**< (MCAN_ILS) High Priority Message Interrupt Line Mask */ +#define MCAN_ILS_HPML(value) (MCAN_ILS_HPML_Msk & ((value) << MCAN_ILS_HPML_Pos)) +#define MCAN_ILS_TCL_Pos _U_(9) /**< (MCAN_ILS) Transmission Completed Interrupt Line Position */ +#define MCAN_ILS_TCL_Msk (_U_(0x1) << MCAN_ILS_TCL_Pos) /**< (MCAN_ILS) Transmission Completed Interrupt Line Mask */ +#define MCAN_ILS_TCL(value) (MCAN_ILS_TCL_Msk & ((value) << MCAN_ILS_TCL_Pos)) +#define MCAN_ILS_TCFL_Pos _U_(10) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ +#define MCAN_ILS_TCFL_Msk (_U_(0x1) << MCAN_ILS_TCFL_Pos) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ +#define MCAN_ILS_TCFL(value) (MCAN_ILS_TCFL_Msk & ((value) << MCAN_ILS_TCFL_Pos)) +#define MCAN_ILS_TFEL_Pos _U_(11) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Position */ +#define MCAN_ILS_TFEL_Msk (_U_(0x1) << MCAN_ILS_TFEL_Pos) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Mask */ +#define MCAN_ILS_TFEL(value) (MCAN_ILS_TFEL_Msk & ((value) << MCAN_ILS_TFEL_Pos)) +#define MCAN_ILS_TEFNL_Pos _U_(12) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ +#define MCAN_ILS_TEFNL_Msk (_U_(0x1) << MCAN_ILS_TEFNL_Pos) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ +#define MCAN_ILS_TEFNL(value) (MCAN_ILS_TEFNL_Msk & ((value) << MCAN_ILS_TEFNL_Pos)) +#define MCAN_ILS_TEFWL_Pos _U_(13) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ +#define MCAN_ILS_TEFWL_Msk (_U_(0x1) << MCAN_ILS_TEFWL_Pos) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ +#define MCAN_ILS_TEFWL(value) (MCAN_ILS_TEFWL_Msk & ((value) << MCAN_ILS_TEFWL_Pos)) +#define MCAN_ILS_TEFFL_Pos _U_(14) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Position */ +#define MCAN_ILS_TEFFL_Msk (_U_(0x1) << MCAN_ILS_TEFFL_Pos) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ +#define MCAN_ILS_TEFFL(value) (MCAN_ILS_TEFFL_Msk & ((value) << MCAN_ILS_TEFFL_Pos)) +#define MCAN_ILS_TEFLL_Pos _U_(15) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Position */ +#define MCAN_ILS_TEFLL_Msk (_U_(0x1) << MCAN_ILS_TEFLL_Pos) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Mask */ +#define MCAN_ILS_TEFLL(value) (MCAN_ILS_TEFLL_Msk & ((value) << MCAN_ILS_TEFLL_Pos)) +#define MCAN_ILS_TSWL_Pos _U_(16) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Position */ +#define MCAN_ILS_TSWL_Msk (_U_(0x1) << MCAN_ILS_TSWL_Pos) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Mask */ +#define MCAN_ILS_TSWL(value) (MCAN_ILS_TSWL_Msk & ((value) << MCAN_ILS_TSWL_Pos)) +#define MCAN_ILS_MRAFL_Pos _U_(17) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Position */ +#define MCAN_ILS_MRAFL_Msk (_U_(0x1) << MCAN_ILS_MRAFL_Pos) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Mask */ +#define MCAN_ILS_MRAFL(value) (MCAN_ILS_MRAFL_Msk & ((value) << MCAN_ILS_MRAFL_Pos)) +#define MCAN_ILS_TOOL_Pos _U_(18) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Position */ +#define MCAN_ILS_TOOL_Msk (_U_(0x1) << MCAN_ILS_TOOL_Pos) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Mask */ +#define MCAN_ILS_TOOL(value) (MCAN_ILS_TOOL_Msk & ((value) << MCAN_ILS_TOOL_Pos)) +#define MCAN_ILS_DRXL_Pos _U_(19) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Position */ +#define MCAN_ILS_DRXL_Msk (_U_(0x1) << MCAN_ILS_DRXL_Pos) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Mask */ +#define MCAN_ILS_DRXL(value) (MCAN_ILS_DRXL_Msk & ((value) << MCAN_ILS_DRXL_Pos)) +#define MCAN_ILS_ELOL_Pos _U_(22) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Position */ +#define MCAN_ILS_ELOL_Msk (_U_(0x1) << MCAN_ILS_ELOL_Pos) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Mask */ +#define MCAN_ILS_ELOL(value) (MCAN_ILS_ELOL_Msk & ((value) << MCAN_ILS_ELOL_Pos)) +#define MCAN_ILS_EPL_Pos _U_(23) /**< (MCAN_ILS) Error Passive Interrupt Line Position */ +#define MCAN_ILS_EPL_Msk (_U_(0x1) << MCAN_ILS_EPL_Pos) /**< (MCAN_ILS) Error Passive Interrupt Line Mask */ +#define MCAN_ILS_EPL(value) (MCAN_ILS_EPL_Msk & ((value) << MCAN_ILS_EPL_Pos)) +#define MCAN_ILS_EWL_Pos _U_(24) /**< (MCAN_ILS) Warning Status Interrupt Line Position */ +#define MCAN_ILS_EWL_Msk (_U_(0x1) << MCAN_ILS_EWL_Pos) /**< (MCAN_ILS) Warning Status Interrupt Line Mask */ +#define MCAN_ILS_EWL(value) (MCAN_ILS_EWL_Msk & ((value) << MCAN_ILS_EWL_Pos)) +#define MCAN_ILS_BOL_Pos _U_(25) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Position */ +#define MCAN_ILS_BOL_Msk (_U_(0x1) << MCAN_ILS_BOL_Pos) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Mask */ +#define MCAN_ILS_BOL(value) (MCAN_ILS_BOL_Msk & ((value) << MCAN_ILS_BOL_Pos)) +#define MCAN_ILS_WDIL_Pos _U_(26) /**< (MCAN_ILS) Watchdog Interrupt Line Position */ +#define MCAN_ILS_WDIL_Msk (_U_(0x1) << MCAN_ILS_WDIL_Pos) /**< (MCAN_ILS) Watchdog Interrupt Line Mask */ +#define MCAN_ILS_WDIL(value) (MCAN_ILS_WDIL_Msk & ((value) << MCAN_ILS_WDIL_Pos)) +#define MCAN_ILS_PEAL_Pos _U_(27) /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Position */ +#define MCAN_ILS_PEAL_Msk (_U_(0x1) << MCAN_ILS_PEAL_Pos) /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Mask */ +#define MCAN_ILS_PEAL(value) (MCAN_ILS_PEAL_Msk & ((value) << MCAN_ILS_PEAL_Pos)) +#define MCAN_ILS_PEDL_Pos _U_(28) /**< (MCAN_ILS) Protocol Error in Data Phase Line Position */ +#define MCAN_ILS_PEDL_Msk (_U_(0x1) << MCAN_ILS_PEDL_Pos) /**< (MCAN_ILS) Protocol Error in Data Phase Line Mask */ +#define MCAN_ILS_PEDL(value) (MCAN_ILS_PEDL_Msk & ((value) << MCAN_ILS_PEDL_Pos)) +#define MCAN_ILS_ARAL_Pos _U_(29) /**< (MCAN_ILS) Access to Reserved Address Line Position */ +#define MCAN_ILS_ARAL_Msk (_U_(0x1) << MCAN_ILS_ARAL_Pos) /**< (MCAN_ILS) Access to Reserved Address Line Mask */ +#define MCAN_ILS_ARAL(value) (MCAN_ILS_ARAL_Msk & ((value) << MCAN_ILS_ARAL_Pos)) +#define MCAN_ILS_Msk _U_(0x3FCFFFFF) /**< (MCAN_ILS) Register Mask */ + + +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) (R/W 32) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0_Pos _U_(0) /**< (MCAN_ILE) Enable Interrupt Line 0 Position */ +#define MCAN_ILE_EINT0_Msk (_U_(0x1) << MCAN_ILE_EINT0_Pos) /**< (MCAN_ILE) Enable Interrupt Line 0 Mask */ +#define MCAN_ILE_EINT0(value) (MCAN_ILE_EINT0_Msk & ((value) << MCAN_ILE_EINT0_Pos)) +#define MCAN_ILE_EINT1_Pos _U_(1) /**< (MCAN_ILE) Enable Interrupt Line 1 Position */ +#define MCAN_ILE_EINT1_Msk (_U_(0x1) << MCAN_ILE_EINT1_Pos) /**< (MCAN_ILE) Enable Interrupt Line 1 Mask */ +#define MCAN_ILE_EINT1(value) (MCAN_ILE_EINT1_Msk & ((value) << MCAN_ILE_EINT1_Pos)) +#define MCAN_ILE_Msk _U_(0x00000003) /**< (MCAN_ILE) Register Mask */ + +#define MCAN_ILE_EINT_Pos _U_(0) /**< (MCAN_ILE Position) Enable Interrupt Line x */ +#define MCAN_ILE_EINT_Msk (_U_(0x3) << MCAN_ILE_EINT_Pos) /**< (MCAN_ILE Mask) EINT */ +#define MCAN_ILE_EINT(value) (MCAN_ILE_EINT_Msk & ((value) << MCAN_ILE_EINT_Pos)) + +/* -------- MCAN_GFC : (MCAN Offset: 0x80) (R/W 32) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE_Pos _U_(0) /**< (MCAN_GFC) Reject Remote Frames Extended Position */ +#define MCAN_GFC_RRFE_Msk (_U_(0x1) << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject Remote Frames Extended Mask */ +#define MCAN_GFC_RRFE(value) (MCAN_GFC_RRFE_Msk & ((value) << MCAN_GFC_RRFE_Pos)) +#define MCAN_GFC_RRFE_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_FILTER (MCAN_GFC_RRFE_FILTER_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFE_REJECT (MCAN_GFC_RRFE_REJECT_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. Position */ +#define MCAN_GFC_RRFS_Pos _U_(1) /**< (MCAN_GFC) Reject Remote Frames Standard Position */ +#define MCAN_GFC_RRFS_Msk (_U_(0x1) << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject Remote Frames Standard Mask */ +#define MCAN_GFC_RRFS(value) (MCAN_GFC_RRFS_Msk & ((value) << MCAN_GFC_RRFS_Pos)) +#define MCAN_GFC_RRFS_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_FILTER (MCAN_GFC_RRFS_FILTER_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_RRFS_REJECT (MCAN_GFC_RRFS_REJECT_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. Position */ +#define MCAN_GFC_ANFE_Pos _U_(2) /**< (MCAN_GFC) Accept Non-matching Frames Extended Position */ +#define MCAN_GFC_ANFE_Msk (_U_(0x3) << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Extended Mask */ +#define MCAN_GFC_ANFE(value) (MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)) +#define MCAN_GFC_ANFE_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ +#define MCAN_GFC_ANFE_RX_FIFO_0 (MCAN_GFC_ANFE_RX_FIFO_0_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (MCAN_GFC_ANFE_RX_FIFO_1_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ +#define MCAN_GFC_ANFS_Pos _U_(4) /**< (MCAN_GFC) Accept Non-matching Frames Standard Position */ +#define MCAN_GFC_ANFS_Msk (_U_(0x3) << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Standard Mask */ +#define MCAN_GFC_ANFS(value) (MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)) +#define MCAN_GFC_ANFS_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ +#define MCAN_GFC_ANFS_RX_FIFO_0 (MCAN_GFC_ANFS_RX_FIFO_0_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (MCAN_GFC_ANFS_RX_FIFO_1_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ +#define MCAN_GFC_Msk _U_(0x0000003F) /**< (MCAN_GFC) Register Mask */ + + +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos _U_(2) /**< (MCAN_SIDFC) Filter List Standard Start Address Position */ +#define MCAN_SIDFC_FLSSA_Msk (_U_(0x3FFF) << MCAN_SIDFC_FLSSA_Pos) /**< (MCAN_SIDFC) Filter List Standard Start Address Mask */ +#define MCAN_SIDFC_FLSSA(value) (MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)) +#define MCAN_SIDFC_LSS_Pos _U_(16) /**< (MCAN_SIDFC) List Size Standard Position */ +#define MCAN_SIDFC_LSS_Msk (_U_(0xFF) << MCAN_SIDFC_LSS_Pos) /**< (MCAN_SIDFC) List Size Standard Mask */ +#define MCAN_SIDFC_LSS(value) (MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)) +#define MCAN_SIDFC_Msk _U_(0x00FFFFFC) /**< (MCAN_SIDFC) Register Mask */ + + +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos _U_(2) /**< (MCAN_XIDFC) Filter List Extended Start Address Position */ +#define MCAN_XIDFC_FLESA_Msk (_U_(0x3FFF) << MCAN_XIDFC_FLESA_Pos) /**< (MCAN_XIDFC) Filter List Extended Start Address Mask */ +#define MCAN_XIDFC_FLESA(value) (MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)) +#define MCAN_XIDFC_LSE_Pos _U_(16) /**< (MCAN_XIDFC) List Size Extended Position */ +#define MCAN_XIDFC_LSE_Msk (_U_(0x7F) << MCAN_XIDFC_LSE_Pos) /**< (MCAN_XIDFC) List Size Extended Mask */ +#define MCAN_XIDFC_LSE(value) (MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)) +#define MCAN_XIDFC_Msk _U_(0x007FFFFC) /**< (MCAN_XIDFC) Register Mask */ + + +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) (R/W 32) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos _U_(0) /**< (MCAN_XIDAM) Extended ID Mask Position */ +#define MCAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << MCAN_XIDAM_EIDM_Pos) /**< (MCAN_XIDAM) Extended ID Mask Mask */ +#define MCAN_XIDAM_EIDM(value) (MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)) +#define MCAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (MCAN_XIDAM) Register Mask */ + + +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) ( R/ 32) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos _U_(0) /**< (MCAN_HPMS) Buffer Index Position */ +#define MCAN_HPMS_BIDX_Msk (_U_(0x3F) << MCAN_HPMS_BIDX_Pos) /**< (MCAN_HPMS) Buffer Index Mask */ +#define MCAN_HPMS_BIDX(value) (MCAN_HPMS_BIDX_Msk & ((value) << MCAN_HPMS_BIDX_Pos)) +#define MCAN_HPMS_MSI_Pos _U_(6) /**< (MCAN_HPMS) Message Storage Indicator Position */ +#define MCAN_HPMS_MSI_Msk (_U_(0x3) << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message Storage Indicator Mask */ +#define MCAN_HPMS_MSI(value) (MCAN_HPMS_MSI_Msk & ((value) << MCAN_HPMS_MSI_Pos)) +#define MCAN_HPMS_MSI_NO_FIFO_SEL_Val _U_(0x0) /**< (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (MCAN_HPMS) FIFO message lost. */ +#define MCAN_HPMS_MSI_FIFO_0_Val _U_(0x2) /**< (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1_Val _U_(0x3) /**< (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (MCAN_HPMS_MSI_NO_FIFO_SEL_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) No FIFO selected. Position */ +#define MCAN_HPMS_MSI_LOST (MCAN_HPMS_MSI_LOST_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) FIFO message lost. Position */ +#define MCAN_HPMS_MSI_FIFO_0 (MCAN_HPMS_MSI_FIFO_0_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 0. Position */ +#define MCAN_HPMS_MSI_FIFO_1 (MCAN_HPMS_MSI_FIFO_1_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 1. Position */ +#define MCAN_HPMS_FIDX_Pos _U_(8) /**< (MCAN_HPMS) Filter Index Position */ +#define MCAN_HPMS_FIDX_Msk (_U_(0x7F) << MCAN_HPMS_FIDX_Pos) /**< (MCAN_HPMS) Filter Index Mask */ +#define MCAN_HPMS_FIDX(value) (MCAN_HPMS_FIDX_Msk & ((value) << MCAN_HPMS_FIDX_Pos)) +#define MCAN_HPMS_FLST_Pos _U_(15) /**< (MCAN_HPMS) Filter List Position */ +#define MCAN_HPMS_FLST_Msk (_U_(0x1) << MCAN_HPMS_FLST_Pos) /**< (MCAN_HPMS) Filter List Mask */ +#define MCAN_HPMS_FLST(value) (MCAN_HPMS_FLST_Msk & ((value) << MCAN_HPMS_FLST_Pos)) +#define MCAN_HPMS_Msk _U_(0x0000FFFF) /**< (MCAN_HPMS) Register Mask */ + + +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) (R/W 32) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0_Pos _U_(0) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND0_Msk (_U_(0x1) << MCAN_NDAT1_ND0_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND0(value) (MCAN_NDAT1_ND0_Msk & ((value) << MCAN_NDAT1_ND0_Pos)) +#define MCAN_NDAT1_ND1_Pos _U_(1) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND1_Msk (_U_(0x1) << MCAN_NDAT1_ND1_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND1(value) (MCAN_NDAT1_ND1_Msk & ((value) << MCAN_NDAT1_ND1_Pos)) +#define MCAN_NDAT1_ND2_Pos _U_(2) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND2_Msk (_U_(0x1) << MCAN_NDAT1_ND2_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND2(value) (MCAN_NDAT1_ND2_Msk & ((value) << MCAN_NDAT1_ND2_Pos)) +#define MCAN_NDAT1_ND3_Pos _U_(3) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND3_Msk (_U_(0x1) << MCAN_NDAT1_ND3_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND3(value) (MCAN_NDAT1_ND3_Msk & ((value) << MCAN_NDAT1_ND3_Pos)) +#define MCAN_NDAT1_ND4_Pos _U_(4) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND4_Msk (_U_(0x1) << MCAN_NDAT1_ND4_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND4(value) (MCAN_NDAT1_ND4_Msk & ((value) << MCAN_NDAT1_ND4_Pos)) +#define MCAN_NDAT1_ND5_Pos _U_(5) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND5_Msk (_U_(0x1) << MCAN_NDAT1_ND5_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND5(value) (MCAN_NDAT1_ND5_Msk & ((value) << MCAN_NDAT1_ND5_Pos)) +#define MCAN_NDAT1_ND6_Pos _U_(6) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND6_Msk (_U_(0x1) << MCAN_NDAT1_ND6_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND6(value) (MCAN_NDAT1_ND6_Msk & ((value) << MCAN_NDAT1_ND6_Pos)) +#define MCAN_NDAT1_ND7_Pos _U_(7) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND7_Msk (_U_(0x1) << MCAN_NDAT1_ND7_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND7(value) (MCAN_NDAT1_ND7_Msk & ((value) << MCAN_NDAT1_ND7_Pos)) +#define MCAN_NDAT1_ND8_Pos _U_(8) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND8_Msk (_U_(0x1) << MCAN_NDAT1_ND8_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND8(value) (MCAN_NDAT1_ND8_Msk & ((value) << MCAN_NDAT1_ND8_Pos)) +#define MCAN_NDAT1_ND9_Pos _U_(9) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND9_Msk (_U_(0x1) << MCAN_NDAT1_ND9_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND9(value) (MCAN_NDAT1_ND9_Msk & ((value) << MCAN_NDAT1_ND9_Pos)) +#define MCAN_NDAT1_ND10_Pos _U_(10) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND10_Msk (_U_(0x1) << MCAN_NDAT1_ND10_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND10(value) (MCAN_NDAT1_ND10_Msk & ((value) << MCAN_NDAT1_ND10_Pos)) +#define MCAN_NDAT1_ND11_Pos _U_(11) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND11_Msk (_U_(0x1) << MCAN_NDAT1_ND11_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND11(value) (MCAN_NDAT1_ND11_Msk & ((value) << MCAN_NDAT1_ND11_Pos)) +#define MCAN_NDAT1_ND12_Pos _U_(12) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND12_Msk (_U_(0x1) << MCAN_NDAT1_ND12_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND12(value) (MCAN_NDAT1_ND12_Msk & ((value) << MCAN_NDAT1_ND12_Pos)) +#define MCAN_NDAT1_ND13_Pos _U_(13) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND13_Msk (_U_(0x1) << MCAN_NDAT1_ND13_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND13(value) (MCAN_NDAT1_ND13_Msk & ((value) << MCAN_NDAT1_ND13_Pos)) +#define MCAN_NDAT1_ND14_Pos _U_(14) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND14_Msk (_U_(0x1) << MCAN_NDAT1_ND14_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND14(value) (MCAN_NDAT1_ND14_Msk & ((value) << MCAN_NDAT1_ND14_Pos)) +#define MCAN_NDAT1_ND15_Pos _U_(15) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND15_Msk (_U_(0x1) << MCAN_NDAT1_ND15_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND15(value) (MCAN_NDAT1_ND15_Msk & ((value) << MCAN_NDAT1_ND15_Pos)) +#define MCAN_NDAT1_ND16_Pos _U_(16) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND16_Msk (_U_(0x1) << MCAN_NDAT1_ND16_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND16(value) (MCAN_NDAT1_ND16_Msk & ((value) << MCAN_NDAT1_ND16_Pos)) +#define MCAN_NDAT1_ND17_Pos _U_(17) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND17_Msk (_U_(0x1) << MCAN_NDAT1_ND17_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND17(value) (MCAN_NDAT1_ND17_Msk & ((value) << MCAN_NDAT1_ND17_Pos)) +#define MCAN_NDAT1_ND18_Pos _U_(18) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND18_Msk (_U_(0x1) << MCAN_NDAT1_ND18_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND18(value) (MCAN_NDAT1_ND18_Msk & ((value) << MCAN_NDAT1_ND18_Pos)) +#define MCAN_NDAT1_ND19_Pos _U_(19) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND19_Msk (_U_(0x1) << MCAN_NDAT1_ND19_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND19(value) (MCAN_NDAT1_ND19_Msk & ((value) << MCAN_NDAT1_ND19_Pos)) +#define MCAN_NDAT1_ND20_Pos _U_(20) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND20_Msk (_U_(0x1) << MCAN_NDAT1_ND20_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND20(value) (MCAN_NDAT1_ND20_Msk & ((value) << MCAN_NDAT1_ND20_Pos)) +#define MCAN_NDAT1_ND21_Pos _U_(21) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND21_Msk (_U_(0x1) << MCAN_NDAT1_ND21_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND21(value) (MCAN_NDAT1_ND21_Msk & ((value) << MCAN_NDAT1_ND21_Pos)) +#define MCAN_NDAT1_ND22_Pos _U_(22) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND22_Msk (_U_(0x1) << MCAN_NDAT1_ND22_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND22(value) (MCAN_NDAT1_ND22_Msk & ((value) << MCAN_NDAT1_ND22_Pos)) +#define MCAN_NDAT1_ND23_Pos _U_(23) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND23_Msk (_U_(0x1) << MCAN_NDAT1_ND23_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND23(value) (MCAN_NDAT1_ND23_Msk & ((value) << MCAN_NDAT1_ND23_Pos)) +#define MCAN_NDAT1_ND24_Pos _U_(24) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND24_Msk (_U_(0x1) << MCAN_NDAT1_ND24_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND24(value) (MCAN_NDAT1_ND24_Msk & ((value) << MCAN_NDAT1_ND24_Pos)) +#define MCAN_NDAT1_ND25_Pos _U_(25) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND25_Msk (_U_(0x1) << MCAN_NDAT1_ND25_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND25(value) (MCAN_NDAT1_ND25_Msk & ((value) << MCAN_NDAT1_ND25_Pos)) +#define MCAN_NDAT1_ND26_Pos _U_(26) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND26_Msk (_U_(0x1) << MCAN_NDAT1_ND26_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND26(value) (MCAN_NDAT1_ND26_Msk & ((value) << MCAN_NDAT1_ND26_Pos)) +#define MCAN_NDAT1_ND27_Pos _U_(27) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND27_Msk (_U_(0x1) << MCAN_NDAT1_ND27_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND27(value) (MCAN_NDAT1_ND27_Msk & ((value) << MCAN_NDAT1_ND27_Pos)) +#define MCAN_NDAT1_ND28_Pos _U_(28) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND28_Msk (_U_(0x1) << MCAN_NDAT1_ND28_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND28(value) (MCAN_NDAT1_ND28_Msk & ((value) << MCAN_NDAT1_ND28_Pos)) +#define MCAN_NDAT1_ND29_Pos _U_(29) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND29_Msk (_U_(0x1) << MCAN_NDAT1_ND29_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND29(value) (MCAN_NDAT1_ND29_Msk & ((value) << MCAN_NDAT1_ND29_Pos)) +#define MCAN_NDAT1_ND30_Pos _U_(30) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND30_Msk (_U_(0x1) << MCAN_NDAT1_ND30_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND30(value) (MCAN_NDAT1_ND30_Msk & ((value) << MCAN_NDAT1_ND30_Pos)) +#define MCAN_NDAT1_ND31_Pos _U_(31) /**< (MCAN_NDAT1) New Data Position */ +#define MCAN_NDAT1_ND31_Msk (_U_(0x1) << MCAN_NDAT1_ND31_Pos) /**< (MCAN_NDAT1) New Data Mask */ +#define MCAN_NDAT1_ND31(value) (MCAN_NDAT1_ND31_Msk & ((value) << MCAN_NDAT1_ND31_Pos)) +#define MCAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT1) Register Mask */ + +#define MCAN_NDAT1_ND_Pos _U_(0) /**< (MCAN_NDAT1 Position) New Data */ +#define MCAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT1_ND_Pos) /**< (MCAN_NDAT1 Mask) ND */ +#define MCAN_NDAT1_ND(value) (MCAN_NDAT1_ND_Msk & ((value) << MCAN_NDAT1_ND_Pos)) + +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) (R/W 32) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32_Pos _U_(0) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND32_Msk (_U_(0x1) << MCAN_NDAT2_ND32_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND32(value) (MCAN_NDAT2_ND32_Msk & ((value) << MCAN_NDAT2_ND32_Pos)) +#define MCAN_NDAT2_ND33_Pos _U_(1) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND33_Msk (_U_(0x1) << MCAN_NDAT2_ND33_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND33(value) (MCAN_NDAT2_ND33_Msk & ((value) << MCAN_NDAT2_ND33_Pos)) +#define MCAN_NDAT2_ND34_Pos _U_(2) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND34_Msk (_U_(0x1) << MCAN_NDAT2_ND34_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND34(value) (MCAN_NDAT2_ND34_Msk & ((value) << MCAN_NDAT2_ND34_Pos)) +#define MCAN_NDAT2_ND35_Pos _U_(3) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND35_Msk (_U_(0x1) << MCAN_NDAT2_ND35_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND35(value) (MCAN_NDAT2_ND35_Msk & ((value) << MCAN_NDAT2_ND35_Pos)) +#define MCAN_NDAT2_ND36_Pos _U_(4) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND36_Msk (_U_(0x1) << MCAN_NDAT2_ND36_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND36(value) (MCAN_NDAT2_ND36_Msk & ((value) << MCAN_NDAT2_ND36_Pos)) +#define MCAN_NDAT2_ND37_Pos _U_(5) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND37_Msk (_U_(0x1) << MCAN_NDAT2_ND37_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND37(value) (MCAN_NDAT2_ND37_Msk & ((value) << MCAN_NDAT2_ND37_Pos)) +#define MCAN_NDAT2_ND38_Pos _U_(6) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND38_Msk (_U_(0x1) << MCAN_NDAT2_ND38_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND38(value) (MCAN_NDAT2_ND38_Msk & ((value) << MCAN_NDAT2_ND38_Pos)) +#define MCAN_NDAT2_ND39_Pos _U_(7) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND39_Msk (_U_(0x1) << MCAN_NDAT2_ND39_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND39(value) (MCAN_NDAT2_ND39_Msk & ((value) << MCAN_NDAT2_ND39_Pos)) +#define MCAN_NDAT2_ND40_Pos _U_(8) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND40_Msk (_U_(0x1) << MCAN_NDAT2_ND40_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND40(value) (MCAN_NDAT2_ND40_Msk & ((value) << MCAN_NDAT2_ND40_Pos)) +#define MCAN_NDAT2_ND41_Pos _U_(9) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND41_Msk (_U_(0x1) << MCAN_NDAT2_ND41_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND41(value) (MCAN_NDAT2_ND41_Msk & ((value) << MCAN_NDAT2_ND41_Pos)) +#define MCAN_NDAT2_ND42_Pos _U_(10) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND42_Msk (_U_(0x1) << MCAN_NDAT2_ND42_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND42(value) (MCAN_NDAT2_ND42_Msk & ((value) << MCAN_NDAT2_ND42_Pos)) +#define MCAN_NDAT2_ND43_Pos _U_(11) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND43_Msk (_U_(0x1) << MCAN_NDAT2_ND43_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND43(value) (MCAN_NDAT2_ND43_Msk & ((value) << MCAN_NDAT2_ND43_Pos)) +#define MCAN_NDAT2_ND44_Pos _U_(12) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND44_Msk (_U_(0x1) << MCAN_NDAT2_ND44_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND44(value) (MCAN_NDAT2_ND44_Msk & ((value) << MCAN_NDAT2_ND44_Pos)) +#define MCAN_NDAT2_ND45_Pos _U_(13) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND45_Msk (_U_(0x1) << MCAN_NDAT2_ND45_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND45(value) (MCAN_NDAT2_ND45_Msk & ((value) << MCAN_NDAT2_ND45_Pos)) +#define MCAN_NDAT2_ND46_Pos _U_(14) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND46_Msk (_U_(0x1) << MCAN_NDAT2_ND46_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND46(value) (MCAN_NDAT2_ND46_Msk & ((value) << MCAN_NDAT2_ND46_Pos)) +#define MCAN_NDAT2_ND47_Pos _U_(15) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND47_Msk (_U_(0x1) << MCAN_NDAT2_ND47_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND47(value) (MCAN_NDAT2_ND47_Msk & ((value) << MCAN_NDAT2_ND47_Pos)) +#define MCAN_NDAT2_ND48_Pos _U_(16) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND48_Msk (_U_(0x1) << MCAN_NDAT2_ND48_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND48(value) (MCAN_NDAT2_ND48_Msk & ((value) << MCAN_NDAT2_ND48_Pos)) +#define MCAN_NDAT2_ND49_Pos _U_(17) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND49_Msk (_U_(0x1) << MCAN_NDAT2_ND49_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND49(value) (MCAN_NDAT2_ND49_Msk & ((value) << MCAN_NDAT2_ND49_Pos)) +#define MCAN_NDAT2_ND50_Pos _U_(18) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND50_Msk (_U_(0x1) << MCAN_NDAT2_ND50_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND50(value) (MCAN_NDAT2_ND50_Msk & ((value) << MCAN_NDAT2_ND50_Pos)) +#define MCAN_NDAT2_ND51_Pos _U_(19) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND51_Msk (_U_(0x1) << MCAN_NDAT2_ND51_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND51(value) (MCAN_NDAT2_ND51_Msk & ((value) << MCAN_NDAT2_ND51_Pos)) +#define MCAN_NDAT2_ND52_Pos _U_(20) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND52_Msk (_U_(0x1) << MCAN_NDAT2_ND52_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND52(value) (MCAN_NDAT2_ND52_Msk & ((value) << MCAN_NDAT2_ND52_Pos)) +#define MCAN_NDAT2_ND53_Pos _U_(21) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND53_Msk (_U_(0x1) << MCAN_NDAT2_ND53_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND53(value) (MCAN_NDAT2_ND53_Msk & ((value) << MCAN_NDAT2_ND53_Pos)) +#define MCAN_NDAT2_ND54_Pos _U_(22) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND54_Msk (_U_(0x1) << MCAN_NDAT2_ND54_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND54(value) (MCAN_NDAT2_ND54_Msk & ((value) << MCAN_NDAT2_ND54_Pos)) +#define MCAN_NDAT2_ND55_Pos _U_(23) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND55_Msk (_U_(0x1) << MCAN_NDAT2_ND55_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND55(value) (MCAN_NDAT2_ND55_Msk & ((value) << MCAN_NDAT2_ND55_Pos)) +#define MCAN_NDAT2_ND56_Pos _U_(24) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND56_Msk (_U_(0x1) << MCAN_NDAT2_ND56_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND56(value) (MCAN_NDAT2_ND56_Msk & ((value) << MCAN_NDAT2_ND56_Pos)) +#define MCAN_NDAT2_ND57_Pos _U_(25) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND57_Msk (_U_(0x1) << MCAN_NDAT2_ND57_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND57(value) (MCAN_NDAT2_ND57_Msk & ((value) << MCAN_NDAT2_ND57_Pos)) +#define MCAN_NDAT2_ND58_Pos _U_(26) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND58_Msk (_U_(0x1) << MCAN_NDAT2_ND58_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND58(value) (MCAN_NDAT2_ND58_Msk & ((value) << MCAN_NDAT2_ND58_Pos)) +#define MCAN_NDAT2_ND59_Pos _U_(27) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND59_Msk (_U_(0x1) << MCAN_NDAT2_ND59_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND59(value) (MCAN_NDAT2_ND59_Msk & ((value) << MCAN_NDAT2_ND59_Pos)) +#define MCAN_NDAT2_ND60_Pos _U_(28) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND60_Msk (_U_(0x1) << MCAN_NDAT2_ND60_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND60(value) (MCAN_NDAT2_ND60_Msk & ((value) << MCAN_NDAT2_ND60_Pos)) +#define MCAN_NDAT2_ND61_Pos _U_(29) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND61_Msk (_U_(0x1) << MCAN_NDAT2_ND61_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND61(value) (MCAN_NDAT2_ND61_Msk & ((value) << MCAN_NDAT2_ND61_Pos)) +#define MCAN_NDAT2_ND62_Pos _U_(30) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND62_Msk (_U_(0x1) << MCAN_NDAT2_ND62_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND62(value) (MCAN_NDAT2_ND62_Msk & ((value) << MCAN_NDAT2_ND62_Pos)) +#define MCAN_NDAT2_ND63_Pos _U_(31) /**< (MCAN_NDAT2) New Data Position */ +#define MCAN_NDAT2_ND63_Msk (_U_(0x1) << MCAN_NDAT2_ND63_Pos) /**< (MCAN_NDAT2) New Data Mask */ +#define MCAN_NDAT2_ND63(value) (MCAN_NDAT2_ND63_Msk & ((value) << MCAN_NDAT2_ND63_Pos)) +#define MCAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT2) Register Mask */ + +#define MCAN_NDAT2_ND_Pos _U_(0) /**< (MCAN_NDAT2 Position) New Data */ +#define MCAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT2_ND_Pos) /**< (MCAN_NDAT2 Mask) ND */ +#define MCAN_NDAT2_ND(value) (MCAN_NDAT2_ND_Msk & ((value) << MCAN_NDAT2_ND_Pos)) + +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) (R/W 32) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos _U_(2) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0SA_Msk (_U_(0x3FFF) << MCAN_RXF0C_F0SA_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0SA(value) (MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)) +#define MCAN_RXF0C_F0S_Pos _U_(16) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ +#define MCAN_RXF0C_F0S_Msk (_U_(0x7F) << MCAN_RXF0C_F0S_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ +#define MCAN_RXF0C_F0S(value) (MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)) +#define MCAN_RXF0C_F0WM_Pos _U_(24) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Position */ +#define MCAN_RXF0C_F0WM_Msk (_U_(0x7F) << MCAN_RXF0C_F0WM_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Mask */ +#define MCAN_RXF0C_F0WM(value) (MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)) +#define MCAN_RXF0C_F0OM_Pos _U_(31) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Position */ +#define MCAN_RXF0C_F0OM_Msk (_U_(0x1) << MCAN_RXF0C_F0OM_Pos) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Mask */ +#define MCAN_RXF0C_F0OM(value) (MCAN_RXF0C_F0OM_Msk & ((value) << MCAN_RXF0C_F0OM_Pos)) +#define MCAN_RXF0C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF0C) Register Mask */ + + +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) ( R/ 32) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos _U_(0) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0FL_Msk (_U_(0x7F) << MCAN_RXF0S_F0FL_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0FL(value) (MCAN_RXF0S_F0FL_Msk & ((value) << MCAN_RXF0S_F0FL_Pos)) +#define MCAN_RXF0S_F0GI_Pos _U_(8) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Position */ +#define MCAN_RXF0S_F0GI_Msk (_U_(0x3F) << MCAN_RXF0S_F0GI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Mask */ +#define MCAN_RXF0S_F0GI(value) (MCAN_RXF0S_F0GI_Msk & ((value) << MCAN_RXF0S_F0GI_Pos)) +#define MCAN_RXF0S_F0PI_Pos _U_(16) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Position */ +#define MCAN_RXF0S_F0PI_Msk (_U_(0x3F) << MCAN_RXF0S_F0PI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Mask */ +#define MCAN_RXF0S_F0PI(value) (MCAN_RXF0S_F0PI_Msk & ((value) << MCAN_RXF0S_F0PI_Pos)) +#define MCAN_RXF0S_F0F_Pos _U_(24) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ +#define MCAN_RXF0S_F0F_Msk (_U_(0x1) << MCAN_RXF0S_F0F_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ +#define MCAN_RXF0S_F0F(value) (MCAN_RXF0S_F0F_Msk & ((value) << MCAN_RXF0S_F0F_Pos)) +#define MCAN_RXF0S_RF0L_Pos _U_(25) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Position */ +#define MCAN_RXF0S_RF0L_Msk (_U_(0x1) << MCAN_RXF0S_RF0L_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Mask */ +#define MCAN_RXF0S_RF0L(value) (MCAN_RXF0S_RF0L_Msk & ((value) << MCAN_RXF0S_RF0L_Pos)) +#define MCAN_RXF0S_Msk _U_(0x033F3F7F) /**< (MCAN_RXF0S) Register Mask */ + + +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) (R/W 32) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos _U_(0) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Position */ +#define MCAN_RXF0A_F0AI_Msk (_U_(0x3F) << MCAN_RXF0A_F0AI_Pos) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Mask */ +#define MCAN_RXF0A_F0AI(value) (MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)) +#define MCAN_RXF0A_Msk _U_(0x0000003F) /**< (MCAN_RXF0A) Register Mask */ + + +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) (R/W 32) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos _U_(2) /**< (MCAN_RXBC) Receive Buffer Start Address Position */ +#define MCAN_RXBC_RBSA_Msk (_U_(0x3FFF) << MCAN_RXBC_RBSA_Pos) /**< (MCAN_RXBC) Receive Buffer Start Address Mask */ +#define MCAN_RXBC_RBSA(value) (MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)) +#define MCAN_RXBC_Msk _U_(0x0000FFFC) /**< (MCAN_RXBC) Register Mask */ + + +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) (R/W 32) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos _U_(2) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1SA_Msk (_U_(0x3FFF) << MCAN_RXF1C_F1SA_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1SA(value) (MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)) +#define MCAN_RXF1C_F1S_Pos _U_(16) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ +#define MCAN_RXF1C_F1S_Msk (_U_(0x7F) << MCAN_RXF1C_F1S_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ +#define MCAN_RXF1C_F1S(value) (MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)) +#define MCAN_RXF1C_F1WM_Pos _U_(24) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Position */ +#define MCAN_RXF1C_F1WM_Msk (_U_(0x7F) << MCAN_RXF1C_F1WM_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Mask */ +#define MCAN_RXF1C_F1WM(value) (MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)) +#define MCAN_RXF1C_F1OM_Pos _U_(31) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Position */ +#define MCAN_RXF1C_F1OM_Msk (_U_(0x1) << MCAN_RXF1C_F1OM_Pos) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Mask */ +#define MCAN_RXF1C_F1OM(value) (MCAN_RXF1C_F1OM_Msk & ((value) << MCAN_RXF1C_F1OM_Pos)) +#define MCAN_RXF1C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF1C) Register Mask */ + + +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) ( R/ 32) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos _U_(0) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1FL_Msk (_U_(0x7F) << MCAN_RXF1S_F1FL_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1FL(value) (MCAN_RXF1S_F1FL_Msk & ((value) << MCAN_RXF1S_F1FL_Pos)) +#define MCAN_RXF1S_F1GI_Pos _U_(8) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Position */ +#define MCAN_RXF1S_F1GI_Msk (_U_(0x3F) << MCAN_RXF1S_F1GI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Mask */ +#define MCAN_RXF1S_F1GI(value) (MCAN_RXF1S_F1GI_Msk & ((value) << MCAN_RXF1S_F1GI_Pos)) +#define MCAN_RXF1S_F1PI_Pos _U_(16) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Position */ +#define MCAN_RXF1S_F1PI_Msk (_U_(0x3F) << MCAN_RXF1S_F1PI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Mask */ +#define MCAN_RXF1S_F1PI(value) (MCAN_RXF1S_F1PI_Msk & ((value) << MCAN_RXF1S_F1PI_Pos)) +#define MCAN_RXF1S_F1F_Pos _U_(24) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ +#define MCAN_RXF1S_F1F_Msk (_U_(0x1) << MCAN_RXF1S_F1F_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ +#define MCAN_RXF1S_F1F(value) (MCAN_RXF1S_F1F_Msk & ((value) << MCAN_RXF1S_F1F_Pos)) +#define MCAN_RXF1S_RF1L_Pos _U_(25) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Position */ +#define MCAN_RXF1S_RF1L_Msk (_U_(0x1) << MCAN_RXF1S_RF1L_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Mask */ +#define MCAN_RXF1S_RF1L(value) (MCAN_RXF1S_RF1L_Msk & ((value) << MCAN_RXF1S_RF1L_Pos)) +#define MCAN_RXF1S_DMS_Pos _U_(30) /**< (MCAN_RXF1S) Debug Message Status Position */ +#define MCAN_RXF1S_DMS_Msk (_U_(0x3) << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug Message Status Mask */ +#define MCAN_RXF1S_DMS(value) (MCAN_RXF1S_DMS_Msk & ((value) << MCAN_RXF1S_DMS_Pos)) +#define MCAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A_Val _U_(0x1) /**< (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB_Val _U_(0x2) /**< (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC_Val _U_(0x3) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +#define MCAN_RXF1S_DMS_IDLE (MCAN_RXF1S_DMS_IDLE_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. Position */ +#define MCAN_RXF1S_DMS_MSG_A (MCAN_RXF1S_DMS_MSG_A_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug message A received. Position */ +#define MCAN_RXF1S_DMS_MSG_AB (MCAN_RXF1S_DMS_MSG_AB_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B received. Position */ +#define MCAN_RXF1S_DMS_MSG_ABC (MCAN_RXF1S_DMS_MSG_ABC_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. Position */ +#define MCAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (MCAN_RXF1S) Register Mask */ + + +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) (R/W 32) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos _U_(0) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Position */ +#define MCAN_RXF1A_F1AI_Msk (_U_(0x3F) << MCAN_RXF1A_F1AI_Pos) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Mask */ +#define MCAN_RXF1A_F1AI(value) (MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)) +#define MCAN_RXF1A_Msk _U_(0x0000003F) /**< (MCAN_RXF1A) Register Mask */ + + +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) (R/W 32) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos _U_(0) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Position */ +#define MCAN_RXESC_F0DS_Msk (_U_(0x7) << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Mask */ +#define MCAN_RXESC_F0DS(value) (MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)) +#define MCAN_RXESC_F0DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F0DS_8_BYTE (MCAN_RXESC_F0DS_8_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F0DS_12_BYTE (MCAN_RXESC_F0DS_12_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F0DS_16_BYTE (MCAN_RXESC_F0DS_16_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F0DS_20_BYTE (MCAN_RXESC_F0DS_20_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F0DS_24_BYTE (MCAN_RXESC_F0DS_24_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F0DS_32_BYTE (MCAN_RXESC_F0DS_32_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F0DS_48_BYTE (MCAN_RXESC_F0DS_48_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F0DS_64_BYTE (MCAN_RXESC_F0DS_64_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_F1DS_Pos _U_(4) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Position */ +#define MCAN_RXESC_F1DS_Msk (_U_(0x7) << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Mask */ +#define MCAN_RXESC_F1DS(value) (MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)) +#define MCAN_RXESC_F1DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_F1DS_8_BYTE (MCAN_RXESC_F1DS_8_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_F1DS_12_BYTE (MCAN_RXESC_F1DS_12_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_F1DS_16_BYTE (MCAN_RXESC_F1DS_16_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_F1DS_20_BYTE (MCAN_RXESC_F1DS_20_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_F1DS_24_BYTE (MCAN_RXESC_F1DS_24_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_F1DS_32_BYTE (MCAN_RXESC_F1DS_32_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_F1DS_48_BYTE (MCAN_RXESC_F1DS_48_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_F1DS_64_BYTE (MCAN_RXESC_F1DS_64_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_RBDS_Pos _U_(8) /**< (MCAN_RXESC) Receive Buffer Data Field Size Position */ +#define MCAN_RXESC_RBDS_Msk (_U_(0x7) << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) Receive Buffer Data Field Size Mask */ +#define MCAN_RXESC_RBDS(value) (MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)) +#define MCAN_RXESC_RBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ +#define MCAN_RXESC_RBDS_8_BYTE (MCAN_RXESC_RBDS_8_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ +#define MCAN_RXESC_RBDS_12_BYTE (MCAN_RXESC_RBDS_12_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ +#define MCAN_RXESC_RBDS_16_BYTE (MCAN_RXESC_RBDS_16_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ +#define MCAN_RXESC_RBDS_20_BYTE (MCAN_RXESC_RBDS_20_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ +#define MCAN_RXESC_RBDS_24_BYTE (MCAN_RXESC_RBDS_24_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ +#define MCAN_RXESC_RBDS_32_BYTE (MCAN_RXESC_RBDS_32_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ +#define MCAN_RXESC_RBDS_48_BYTE (MCAN_RXESC_RBDS_48_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ +#define MCAN_RXESC_RBDS_64_BYTE (MCAN_RXESC_RBDS_64_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ +#define MCAN_RXESC_Msk _U_(0x00000777) /**< (MCAN_RXESC) Register Mask */ + + +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) (R/W 32) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos _U_(2) /**< (MCAN_TXBC) Tx Buffers Start Address Position */ +#define MCAN_TXBC_TBSA_Msk (_U_(0x3FFF) << MCAN_TXBC_TBSA_Pos) /**< (MCAN_TXBC) Tx Buffers Start Address Mask */ +#define MCAN_TXBC_TBSA(value) (MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)) +#define MCAN_TXBC_NDTB_Pos _U_(16) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Position */ +#define MCAN_TXBC_NDTB_Msk (_U_(0x3F) << MCAN_TXBC_NDTB_Pos) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Mask */ +#define MCAN_TXBC_NDTB(value) (MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)) +#define MCAN_TXBC_TFQS_Pos _U_(24) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Position */ +#define MCAN_TXBC_TFQS_Msk (_U_(0x3F) << MCAN_TXBC_TFQS_Pos) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Mask */ +#define MCAN_TXBC_TFQS(value) (MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)) +#define MCAN_TXBC_TFQM_Pos _U_(30) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Position */ +#define MCAN_TXBC_TFQM_Msk (_U_(0x1) << MCAN_TXBC_TFQM_Pos) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Mask */ +#define MCAN_TXBC_TFQM(value) (MCAN_TXBC_TFQM_Msk & ((value) << MCAN_TXBC_TFQM_Pos)) +#define MCAN_TXBC_Msk _U_(0x7F3FFFFC) /**< (MCAN_TXBC) Register Mask */ + + +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) ( R/ 32) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos _U_(0) /**< (MCAN_TXFQS) Tx FIFO Free Level Position */ +#define MCAN_TXFQS_TFFL_Msk (_U_(0x3F) << MCAN_TXFQS_TFFL_Pos) /**< (MCAN_TXFQS) Tx FIFO Free Level Mask */ +#define MCAN_TXFQS_TFFL(value) (MCAN_TXFQS_TFFL_Msk & ((value) << MCAN_TXFQS_TFFL_Pos)) +#define MCAN_TXFQS_TFGI_Pos _U_(8) /**< (MCAN_TXFQS) Tx FIFO Get Index Position */ +#define MCAN_TXFQS_TFGI_Msk (_U_(0x1F) << MCAN_TXFQS_TFGI_Pos) /**< (MCAN_TXFQS) Tx FIFO Get Index Mask */ +#define MCAN_TXFQS_TFGI(value) (MCAN_TXFQS_TFGI_Msk & ((value) << MCAN_TXFQS_TFGI_Pos)) +#define MCAN_TXFQS_TFQPI_Pos _U_(16) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Position */ +#define MCAN_TXFQS_TFQPI_Msk (_U_(0x1F) << MCAN_TXFQS_TFQPI_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Mask */ +#define MCAN_TXFQS_TFQPI(value) (MCAN_TXFQS_TFQPI_Msk & ((value) << MCAN_TXFQS_TFQPI_Pos)) +#define MCAN_TXFQS_TFQF_Pos _U_(21) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Position */ +#define MCAN_TXFQS_TFQF_Msk (_U_(0x1) << MCAN_TXFQS_TFQF_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Mask */ +#define MCAN_TXFQS_TFQF(value) (MCAN_TXFQS_TFQF_Msk & ((value) << MCAN_TXFQS_TFQF_Pos)) +#define MCAN_TXFQS_Msk _U_(0x003F1F3F) /**< (MCAN_TXFQS) Register Mask */ + + +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) (R/W 32) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos _U_(0) /**< (MCAN_TXESC) Tx Buffer Data Field Size Position */ +#define MCAN_TXESC_TBDS_Msk (_U_(0x7) << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) Tx Buffer Data Field Size Mask */ +#define MCAN_TXESC_TBDS(value) (MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)) +#define MCAN_TXESC_TBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_TXESC) 8-byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_TXESC) 12-byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_TXESC) 16-byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_TXESC) 20-byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_TXESC) 24-byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_TXESC) 32-byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_TXESC) 48-byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_TXESC) 64-byte data field */ +#define MCAN_TXESC_TBDS_8_BYTE (MCAN_TXESC_TBDS_8_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 8-byte data field Position */ +#define MCAN_TXESC_TBDS_12_BYTE (MCAN_TXESC_TBDS_12_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 12-byte data field Position */ +#define MCAN_TXESC_TBDS_16_BYTE (MCAN_TXESC_TBDS_16_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 16-byte data field Position */ +#define MCAN_TXESC_TBDS_20_BYTE (MCAN_TXESC_TBDS_20_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 20-byte data field Position */ +#define MCAN_TXESC_TBDS_24_BYTE (MCAN_TXESC_TBDS_24_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 24-byte data field Position */ +#define MCAN_TXESC_TBDS_32_BYTE (MCAN_TXESC_TBDS_32_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 32-byte data field Position */ +#define MCAN_TXESC_TBDS_48_BYTE (MCAN_TXESC_TBDS_48_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 48-byte data field Position */ +#define MCAN_TXESC_TBDS_64_BYTE (MCAN_TXESC_TBDS_64_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 64-byte data field Position */ +#define MCAN_TXESC_Msk _U_(0x00000007) /**< (MCAN_TXESC) Register Mask */ + + +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) ( R/ 32) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0_Pos _U_(0) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Position */ +#define MCAN_TXBRP_TRP0_Msk (_U_(0x1) << MCAN_TXBRP_TRP0_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Mask */ +#define MCAN_TXBRP_TRP0(value) (MCAN_TXBRP_TRP0_Msk & ((value) << MCAN_TXBRP_TRP0_Pos)) +#define MCAN_TXBRP_TRP1_Pos _U_(1) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Position */ +#define MCAN_TXBRP_TRP1_Msk (_U_(0x1) << MCAN_TXBRP_TRP1_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Mask */ +#define MCAN_TXBRP_TRP1(value) (MCAN_TXBRP_TRP1_Msk & ((value) << MCAN_TXBRP_TRP1_Pos)) +#define MCAN_TXBRP_TRP2_Pos _U_(2) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Position */ +#define MCAN_TXBRP_TRP2_Msk (_U_(0x1) << MCAN_TXBRP_TRP2_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Mask */ +#define MCAN_TXBRP_TRP2(value) (MCAN_TXBRP_TRP2_Msk & ((value) << MCAN_TXBRP_TRP2_Pos)) +#define MCAN_TXBRP_TRP3_Pos _U_(3) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Position */ +#define MCAN_TXBRP_TRP3_Msk (_U_(0x1) << MCAN_TXBRP_TRP3_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Mask */ +#define MCAN_TXBRP_TRP3(value) (MCAN_TXBRP_TRP3_Msk & ((value) << MCAN_TXBRP_TRP3_Pos)) +#define MCAN_TXBRP_TRP4_Pos _U_(4) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Position */ +#define MCAN_TXBRP_TRP4_Msk (_U_(0x1) << MCAN_TXBRP_TRP4_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Mask */ +#define MCAN_TXBRP_TRP4(value) (MCAN_TXBRP_TRP4_Msk & ((value) << MCAN_TXBRP_TRP4_Pos)) +#define MCAN_TXBRP_TRP5_Pos _U_(5) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Position */ +#define MCAN_TXBRP_TRP5_Msk (_U_(0x1) << MCAN_TXBRP_TRP5_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Mask */ +#define MCAN_TXBRP_TRP5(value) (MCAN_TXBRP_TRP5_Msk & ((value) << MCAN_TXBRP_TRP5_Pos)) +#define MCAN_TXBRP_TRP6_Pos _U_(6) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Position */ +#define MCAN_TXBRP_TRP6_Msk (_U_(0x1) << MCAN_TXBRP_TRP6_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Mask */ +#define MCAN_TXBRP_TRP6(value) (MCAN_TXBRP_TRP6_Msk & ((value) << MCAN_TXBRP_TRP6_Pos)) +#define MCAN_TXBRP_TRP7_Pos _U_(7) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Position */ +#define MCAN_TXBRP_TRP7_Msk (_U_(0x1) << MCAN_TXBRP_TRP7_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Mask */ +#define MCAN_TXBRP_TRP7(value) (MCAN_TXBRP_TRP7_Msk & ((value) << MCAN_TXBRP_TRP7_Pos)) +#define MCAN_TXBRP_TRP8_Pos _U_(8) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Position */ +#define MCAN_TXBRP_TRP8_Msk (_U_(0x1) << MCAN_TXBRP_TRP8_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Mask */ +#define MCAN_TXBRP_TRP8(value) (MCAN_TXBRP_TRP8_Msk & ((value) << MCAN_TXBRP_TRP8_Pos)) +#define MCAN_TXBRP_TRP9_Pos _U_(9) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Position */ +#define MCAN_TXBRP_TRP9_Msk (_U_(0x1) << MCAN_TXBRP_TRP9_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Mask */ +#define MCAN_TXBRP_TRP9(value) (MCAN_TXBRP_TRP9_Msk & ((value) << MCAN_TXBRP_TRP9_Pos)) +#define MCAN_TXBRP_TRP10_Pos _U_(10) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Position */ +#define MCAN_TXBRP_TRP10_Msk (_U_(0x1) << MCAN_TXBRP_TRP10_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Mask */ +#define MCAN_TXBRP_TRP10(value) (MCAN_TXBRP_TRP10_Msk & ((value) << MCAN_TXBRP_TRP10_Pos)) +#define MCAN_TXBRP_TRP11_Pos _U_(11) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Position */ +#define MCAN_TXBRP_TRP11_Msk (_U_(0x1) << MCAN_TXBRP_TRP11_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Mask */ +#define MCAN_TXBRP_TRP11(value) (MCAN_TXBRP_TRP11_Msk & ((value) << MCAN_TXBRP_TRP11_Pos)) +#define MCAN_TXBRP_TRP12_Pos _U_(12) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Position */ +#define MCAN_TXBRP_TRP12_Msk (_U_(0x1) << MCAN_TXBRP_TRP12_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Mask */ +#define MCAN_TXBRP_TRP12(value) (MCAN_TXBRP_TRP12_Msk & ((value) << MCAN_TXBRP_TRP12_Pos)) +#define MCAN_TXBRP_TRP13_Pos _U_(13) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Position */ +#define MCAN_TXBRP_TRP13_Msk (_U_(0x1) << MCAN_TXBRP_TRP13_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Mask */ +#define MCAN_TXBRP_TRP13(value) (MCAN_TXBRP_TRP13_Msk & ((value) << MCAN_TXBRP_TRP13_Pos)) +#define MCAN_TXBRP_TRP14_Pos _U_(14) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Position */ +#define MCAN_TXBRP_TRP14_Msk (_U_(0x1) << MCAN_TXBRP_TRP14_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Mask */ +#define MCAN_TXBRP_TRP14(value) (MCAN_TXBRP_TRP14_Msk & ((value) << MCAN_TXBRP_TRP14_Pos)) +#define MCAN_TXBRP_TRP15_Pos _U_(15) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Position */ +#define MCAN_TXBRP_TRP15_Msk (_U_(0x1) << MCAN_TXBRP_TRP15_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Mask */ +#define MCAN_TXBRP_TRP15(value) (MCAN_TXBRP_TRP15_Msk & ((value) << MCAN_TXBRP_TRP15_Pos)) +#define MCAN_TXBRP_TRP16_Pos _U_(16) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Position */ +#define MCAN_TXBRP_TRP16_Msk (_U_(0x1) << MCAN_TXBRP_TRP16_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Mask */ +#define MCAN_TXBRP_TRP16(value) (MCAN_TXBRP_TRP16_Msk & ((value) << MCAN_TXBRP_TRP16_Pos)) +#define MCAN_TXBRP_TRP17_Pos _U_(17) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Position */ +#define MCAN_TXBRP_TRP17_Msk (_U_(0x1) << MCAN_TXBRP_TRP17_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Mask */ +#define MCAN_TXBRP_TRP17(value) (MCAN_TXBRP_TRP17_Msk & ((value) << MCAN_TXBRP_TRP17_Pos)) +#define MCAN_TXBRP_TRP18_Pos _U_(18) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Position */ +#define MCAN_TXBRP_TRP18_Msk (_U_(0x1) << MCAN_TXBRP_TRP18_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Mask */ +#define MCAN_TXBRP_TRP18(value) (MCAN_TXBRP_TRP18_Msk & ((value) << MCAN_TXBRP_TRP18_Pos)) +#define MCAN_TXBRP_TRP19_Pos _U_(19) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Position */ +#define MCAN_TXBRP_TRP19_Msk (_U_(0x1) << MCAN_TXBRP_TRP19_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Mask */ +#define MCAN_TXBRP_TRP19(value) (MCAN_TXBRP_TRP19_Msk & ((value) << MCAN_TXBRP_TRP19_Pos)) +#define MCAN_TXBRP_TRP20_Pos _U_(20) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Position */ +#define MCAN_TXBRP_TRP20_Msk (_U_(0x1) << MCAN_TXBRP_TRP20_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Mask */ +#define MCAN_TXBRP_TRP20(value) (MCAN_TXBRP_TRP20_Msk & ((value) << MCAN_TXBRP_TRP20_Pos)) +#define MCAN_TXBRP_TRP21_Pos _U_(21) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Position */ +#define MCAN_TXBRP_TRP21_Msk (_U_(0x1) << MCAN_TXBRP_TRP21_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Mask */ +#define MCAN_TXBRP_TRP21(value) (MCAN_TXBRP_TRP21_Msk & ((value) << MCAN_TXBRP_TRP21_Pos)) +#define MCAN_TXBRP_TRP22_Pos _U_(22) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Position */ +#define MCAN_TXBRP_TRP22_Msk (_U_(0x1) << MCAN_TXBRP_TRP22_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Mask */ +#define MCAN_TXBRP_TRP22(value) (MCAN_TXBRP_TRP22_Msk & ((value) << MCAN_TXBRP_TRP22_Pos)) +#define MCAN_TXBRP_TRP23_Pos _U_(23) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Position */ +#define MCAN_TXBRP_TRP23_Msk (_U_(0x1) << MCAN_TXBRP_TRP23_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Mask */ +#define MCAN_TXBRP_TRP23(value) (MCAN_TXBRP_TRP23_Msk & ((value) << MCAN_TXBRP_TRP23_Pos)) +#define MCAN_TXBRP_TRP24_Pos _U_(24) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Position */ +#define MCAN_TXBRP_TRP24_Msk (_U_(0x1) << MCAN_TXBRP_TRP24_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Mask */ +#define MCAN_TXBRP_TRP24(value) (MCAN_TXBRP_TRP24_Msk & ((value) << MCAN_TXBRP_TRP24_Pos)) +#define MCAN_TXBRP_TRP25_Pos _U_(25) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Position */ +#define MCAN_TXBRP_TRP25_Msk (_U_(0x1) << MCAN_TXBRP_TRP25_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Mask */ +#define MCAN_TXBRP_TRP25(value) (MCAN_TXBRP_TRP25_Msk & ((value) << MCAN_TXBRP_TRP25_Pos)) +#define MCAN_TXBRP_TRP26_Pos _U_(26) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Position */ +#define MCAN_TXBRP_TRP26_Msk (_U_(0x1) << MCAN_TXBRP_TRP26_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Mask */ +#define MCAN_TXBRP_TRP26(value) (MCAN_TXBRP_TRP26_Msk & ((value) << MCAN_TXBRP_TRP26_Pos)) +#define MCAN_TXBRP_TRP27_Pos _U_(27) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Position */ +#define MCAN_TXBRP_TRP27_Msk (_U_(0x1) << MCAN_TXBRP_TRP27_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Mask */ +#define MCAN_TXBRP_TRP27(value) (MCAN_TXBRP_TRP27_Msk & ((value) << MCAN_TXBRP_TRP27_Pos)) +#define MCAN_TXBRP_TRP28_Pos _U_(28) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Position */ +#define MCAN_TXBRP_TRP28_Msk (_U_(0x1) << MCAN_TXBRP_TRP28_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Mask */ +#define MCAN_TXBRP_TRP28(value) (MCAN_TXBRP_TRP28_Msk & ((value) << MCAN_TXBRP_TRP28_Pos)) +#define MCAN_TXBRP_TRP29_Pos _U_(29) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Position */ +#define MCAN_TXBRP_TRP29_Msk (_U_(0x1) << MCAN_TXBRP_TRP29_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Mask */ +#define MCAN_TXBRP_TRP29(value) (MCAN_TXBRP_TRP29_Msk & ((value) << MCAN_TXBRP_TRP29_Pos)) +#define MCAN_TXBRP_TRP30_Pos _U_(30) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Position */ +#define MCAN_TXBRP_TRP30_Msk (_U_(0x1) << MCAN_TXBRP_TRP30_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Mask */ +#define MCAN_TXBRP_TRP30(value) (MCAN_TXBRP_TRP30_Msk & ((value) << MCAN_TXBRP_TRP30_Pos)) +#define MCAN_TXBRP_TRP31_Pos _U_(31) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Position */ +#define MCAN_TXBRP_TRP31_Msk (_U_(0x1) << MCAN_TXBRP_TRP31_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Mask */ +#define MCAN_TXBRP_TRP31(value) (MCAN_TXBRP_TRP31_Msk & ((value) << MCAN_TXBRP_TRP31_Pos)) +#define MCAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBRP) Register Mask */ + +#define MCAN_TXBRP_TRP_Pos _U_(0) /**< (MCAN_TXBRP Position) Transmission Request Pending for Buffer 3x */ +#define MCAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << MCAN_TXBRP_TRP_Pos) /**< (MCAN_TXBRP Mask) TRP */ +#define MCAN_TXBRP_TRP(value) (MCAN_TXBRP_TRP_Msk & ((value) << MCAN_TXBRP_TRP_Pos)) + +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) (R/W 32) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0_Pos _U_(0) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Position */ +#define MCAN_TXBAR_AR0_Msk (_U_(0x1) << MCAN_TXBAR_AR0_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBAR_AR0(value) (MCAN_TXBAR_AR0_Msk & ((value) << MCAN_TXBAR_AR0_Pos)) +#define MCAN_TXBAR_AR1_Pos _U_(1) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Position */ +#define MCAN_TXBAR_AR1_Msk (_U_(0x1) << MCAN_TXBAR_AR1_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBAR_AR1(value) (MCAN_TXBAR_AR1_Msk & ((value) << MCAN_TXBAR_AR1_Pos)) +#define MCAN_TXBAR_AR2_Pos _U_(2) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Position */ +#define MCAN_TXBAR_AR2_Msk (_U_(0x1) << MCAN_TXBAR_AR2_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBAR_AR2(value) (MCAN_TXBAR_AR2_Msk & ((value) << MCAN_TXBAR_AR2_Pos)) +#define MCAN_TXBAR_AR3_Pos _U_(3) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Position */ +#define MCAN_TXBAR_AR3_Msk (_U_(0x1) << MCAN_TXBAR_AR3_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBAR_AR3(value) (MCAN_TXBAR_AR3_Msk & ((value) << MCAN_TXBAR_AR3_Pos)) +#define MCAN_TXBAR_AR4_Pos _U_(4) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Position */ +#define MCAN_TXBAR_AR4_Msk (_U_(0x1) << MCAN_TXBAR_AR4_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBAR_AR4(value) (MCAN_TXBAR_AR4_Msk & ((value) << MCAN_TXBAR_AR4_Pos)) +#define MCAN_TXBAR_AR5_Pos _U_(5) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Position */ +#define MCAN_TXBAR_AR5_Msk (_U_(0x1) << MCAN_TXBAR_AR5_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBAR_AR5(value) (MCAN_TXBAR_AR5_Msk & ((value) << MCAN_TXBAR_AR5_Pos)) +#define MCAN_TXBAR_AR6_Pos _U_(6) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Position */ +#define MCAN_TXBAR_AR6_Msk (_U_(0x1) << MCAN_TXBAR_AR6_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBAR_AR6(value) (MCAN_TXBAR_AR6_Msk & ((value) << MCAN_TXBAR_AR6_Pos)) +#define MCAN_TXBAR_AR7_Pos _U_(7) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Position */ +#define MCAN_TXBAR_AR7_Msk (_U_(0x1) << MCAN_TXBAR_AR7_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBAR_AR7(value) (MCAN_TXBAR_AR7_Msk & ((value) << MCAN_TXBAR_AR7_Pos)) +#define MCAN_TXBAR_AR8_Pos _U_(8) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Position */ +#define MCAN_TXBAR_AR8_Msk (_U_(0x1) << MCAN_TXBAR_AR8_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBAR_AR8(value) (MCAN_TXBAR_AR8_Msk & ((value) << MCAN_TXBAR_AR8_Pos)) +#define MCAN_TXBAR_AR9_Pos _U_(9) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Position */ +#define MCAN_TXBAR_AR9_Msk (_U_(0x1) << MCAN_TXBAR_AR9_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBAR_AR9(value) (MCAN_TXBAR_AR9_Msk & ((value) << MCAN_TXBAR_AR9_Pos)) +#define MCAN_TXBAR_AR10_Pos _U_(10) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Position */ +#define MCAN_TXBAR_AR10_Msk (_U_(0x1) << MCAN_TXBAR_AR10_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBAR_AR10(value) (MCAN_TXBAR_AR10_Msk & ((value) << MCAN_TXBAR_AR10_Pos)) +#define MCAN_TXBAR_AR11_Pos _U_(11) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Position */ +#define MCAN_TXBAR_AR11_Msk (_U_(0x1) << MCAN_TXBAR_AR11_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBAR_AR11(value) (MCAN_TXBAR_AR11_Msk & ((value) << MCAN_TXBAR_AR11_Pos)) +#define MCAN_TXBAR_AR12_Pos _U_(12) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Position */ +#define MCAN_TXBAR_AR12_Msk (_U_(0x1) << MCAN_TXBAR_AR12_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBAR_AR12(value) (MCAN_TXBAR_AR12_Msk & ((value) << MCAN_TXBAR_AR12_Pos)) +#define MCAN_TXBAR_AR13_Pos _U_(13) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Position */ +#define MCAN_TXBAR_AR13_Msk (_U_(0x1) << MCAN_TXBAR_AR13_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBAR_AR13(value) (MCAN_TXBAR_AR13_Msk & ((value) << MCAN_TXBAR_AR13_Pos)) +#define MCAN_TXBAR_AR14_Pos _U_(14) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Position */ +#define MCAN_TXBAR_AR14_Msk (_U_(0x1) << MCAN_TXBAR_AR14_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBAR_AR14(value) (MCAN_TXBAR_AR14_Msk & ((value) << MCAN_TXBAR_AR14_Pos)) +#define MCAN_TXBAR_AR15_Pos _U_(15) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Position */ +#define MCAN_TXBAR_AR15_Msk (_U_(0x1) << MCAN_TXBAR_AR15_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBAR_AR15(value) (MCAN_TXBAR_AR15_Msk & ((value) << MCAN_TXBAR_AR15_Pos)) +#define MCAN_TXBAR_AR16_Pos _U_(16) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Position */ +#define MCAN_TXBAR_AR16_Msk (_U_(0x1) << MCAN_TXBAR_AR16_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBAR_AR16(value) (MCAN_TXBAR_AR16_Msk & ((value) << MCAN_TXBAR_AR16_Pos)) +#define MCAN_TXBAR_AR17_Pos _U_(17) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Position */ +#define MCAN_TXBAR_AR17_Msk (_U_(0x1) << MCAN_TXBAR_AR17_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBAR_AR17(value) (MCAN_TXBAR_AR17_Msk & ((value) << MCAN_TXBAR_AR17_Pos)) +#define MCAN_TXBAR_AR18_Pos _U_(18) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Position */ +#define MCAN_TXBAR_AR18_Msk (_U_(0x1) << MCAN_TXBAR_AR18_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBAR_AR18(value) (MCAN_TXBAR_AR18_Msk & ((value) << MCAN_TXBAR_AR18_Pos)) +#define MCAN_TXBAR_AR19_Pos _U_(19) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Position */ +#define MCAN_TXBAR_AR19_Msk (_U_(0x1) << MCAN_TXBAR_AR19_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBAR_AR19(value) (MCAN_TXBAR_AR19_Msk & ((value) << MCAN_TXBAR_AR19_Pos)) +#define MCAN_TXBAR_AR20_Pos _U_(20) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Position */ +#define MCAN_TXBAR_AR20_Msk (_U_(0x1) << MCAN_TXBAR_AR20_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBAR_AR20(value) (MCAN_TXBAR_AR20_Msk & ((value) << MCAN_TXBAR_AR20_Pos)) +#define MCAN_TXBAR_AR21_Pos _U_(21) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Position */ +#define MCAN_TXBAR_AR21_Msk (_U_(0x1) << MCAN_TXBAR_AR21_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBAR_AR21(value) (MCAN_TXBAR_AR21_Msk & ((value) << MCAN_TXBAR_AR21_Pos)) +#define MCAN_TXBAR_AR22_Pos _U_(22) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Position */ +#define MCAN_TXBAR_AR22_Msk (_U_(0x1) << MCAN_TXBAR_AR22_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBAR_AR22(value) (MCAN_TXBAR_AR22_Msk & ((value) << MCAN_TXBAR_AR22_Pos)) +#define MCAN_TXBAR_AR23_Pos _U_(23) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Position */ +#define MCAN_TXBAR_AR23_Msk (_U_(0x1) << MCAN_TXBAR_AR23_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBAR_AR23(value) (MCAN_TXBAR_AR23_Msk & ((value) << MCAN_TXBAR_AR23_Pos)) +#define MCAN_TXBAR_AR24_Pos _U_(24) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Position */ +#define MCAN_TXBAR_AR24_Msk (_U_(0x1) << MCAN_TXBAR_AR24_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBAR_AR24(value) (MCAN_TXBAR_AR24_Msk & ((value) << MCAN_TXBAR_AR24_Pos)) +#define MCAN_TXBAR_AR25_Pos _U_(25) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Position */ +#define MCAN_TXBAR_AR25_Msk (_U_(0x1) << MCAN_TXBAR_AR25_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBAR_AR25(value) (MCAN_TXBAR_AR25_Msk & ((value) << MCAN_TXBAR_AR25_Pos)) +#define MCAN_TXBAR_AR26_Pos _U_(26) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Position */ +#define MCAN_TXBAR_AR26_Msk (_U_(0x1) << MCAN_TXBAR_AR26_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBAR_AR26(value) (MCAN_TXBAR_AR26_Msk & ((value) << MCAN_TXBAR_AR26_Pos)) +#define MCAN_TXBAR_AR27_Pos _U_(27) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Position */ +#define MCAN_TXBAR_AR27_Msk (_U_(0x1) << MCAN_TXBAR_AR27_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBAR_AR27(value) (MCAN_TXBAR_AR27_Msk & ((value) << MCAN_TXBAR_AR27_Pos)) +#define MCAN_TXBAR_AR28_Pos _U_(28) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Position */ +#define MCAN_TXBAR_AR28_Msk (_U_(0x1) << MCAN_TXBAR_AR28_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBAR_AR28(value) (MCAN_TXBAR_AR28_Msk & ((value) << MCAN_TXBAR_AR28_Pos)) +#define MCAN_TXBAR_AR29_Pos _U_(29) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Position */ +#define MCAN_TXBAR_AR29_Msk (_U_(0x1) << MCAN_TXBAR_AR29_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBAR_AR29(value) (MCAN_TXBAR_AR29_Msk & ((value) << MCAN_TXBAR_AR29_Pos)) +#define MCAN_TXBAR_AR30_Pos _U_(30) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Position */ +#define MCAN_TXBAR_AR30_Msk (_U_(0x1) << MCAN_TXBAR_AR30_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBAR_AR30(value) (MCAN_TXBAR_AR30_Msk & ((value) << MCAN_TXBAR_AR30_Pos)) +#define MCAN_TXBAR_AR31_Pos _U_(31) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Position */ +#define MCAN_TXBAR_AR31_Msk (_U_(0x1) << MCAN_TXBAR_AR31_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBAR_AR31(value) (MCAN_TXBAR_AR31_Msk & ((value) << MCAN_TXBAR_AR31_Pos)) +#define MCAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBAR) Register Mask */ + +#define MCAN_TXBAR_AR_Pos _U_(0) /**< (MCAN_TXBAR Position) Add Request for Transmit Buffer 3x */ +#define MCAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBAR_AR_Pos) /**< (MCAN_TXBAR Mask) AR */ +#define MCAN_TXBAR_AR(value) (MCAN_TXBAR_AR_Msk & ((value) << MCAN_TXBAR_AR_Pos)) + +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) (R/W 32) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0_Pos _U_(0) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Position */ +#define MCAN_TXBCR_CR0_Msk (_U_(0x1) << MCAN_TXBCR_CR0_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Mask */ +#define MCAN_TXBCR_CR0(value) (MCAN_TXBCR_CR0_Msk & ((value) << MCAN_TXBCR_CR0_Pos)) +#define MCAN_TXBCR_CR1_Pos _U_(1) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Position */ +#define MCAN_TXBCR_CR1_Msk (_U_(0x1) << MCAN_TXBCR_CR1_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Mask */ +#define MCAN_TXBCR_CR1(value) (MCAN_TXBCR_CR1_Msk & ((value) << MCAN_TXBCR_CR1_Pos)) +#define MCAN_TXBCR_CR2_Pos _U_(2) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Position */ +#define MCAN_TXBCR_CR2_Msk (_U_(0x1) << MCAN_TXBCR_CR2_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Mask */ +#define MCAN_TXBCR_CR2(value) (MCAN_TXBCR_CR2_Msk & ((value) << MCAN_TXBCR_CR2_Pos)) +#define MCAN_TXBCR_CR3_Pos _U_(3) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Position */ +#define MCAN_TXBCR_CR3_Msk (_U_(0x1) << MCAN_TXBCR_CR3_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Mask */ +#define MCAN_TXBCR_CR3(value) (MCAN_TXBCR_CR3_Msk & ((value) << MCAN_TXBCR_CR3_Pos)) +#define MCAN_TXBCR_CR4_Pos _U_(4) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Position */ +#define MCAN_TXBCR_CR4_Msk (_U_(0x1) << MCAN_TXBCR_CR4_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Mask */ +#define MCAN_TXBCR_CR4(value) (MCAN_TXBCR_CR4_Msk & ((value) << MCAN_TXBCR_CR4_Pos)) +#define MCAN_TXBCR_CR5_Pos _U_(5) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Position */ +#define MCAN_TXBCR_CR5_Msk (_U_(0x1) << MCAN_TXBCR_CR5_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Mask */ +#define MCAN_TXBCR_CR5(value) (MCAN_TXBCR_CR5_Msk & ((value) << MCAN_TXBCR_CR5_Pos)) +#define MCAN_TXBCR_CR6_Pos _U_(6) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Position */ +#define MCAN_TXBCR_CR6_Msk (_U_(0x1) << MCAN_TXBCR_CR6_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Mask */ +#define MCAN_TXBCR_CR6(value) (MCAN_TXBCR_CR6_Msk & ((value) << MCAN_TXBCR_CR6_Pos)) +#define MCAN_TXBCR_CR7_Pos _U_(7) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Position */ +#define MCAN_TXBCR_CR7_Msk (_U_(0x1) << MCAN_TXBCR_CR7_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Mask */ +#define MCAN_TXBCR_CR7(value) (MCAN_TXBCR_CR7_Msk & ((value) << MCAN_TXBCR_CR7_Pos)) +#define MCAN_TXBCR_CR8_Pos _U_(8) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Position */ +#define MCAN_TXBCR_CR8_Msk (_U_(0x1) << MCAN_TXBCR_CR8_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Mask */ +#define MCAN_TXBCR_CR8(value) (MCAN_TXBCR_CR8_Msk & ((value) << MCAN_TXBCR_CR8_Pos)) +#define MCAN_TXBCR_CR9_Pos _U_(9) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Position */ +#define MCAN_TXBCR_CR9_Msk (_U_(0x1) << MCAN_TXBCR_CR9_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Mask */ +#define MCAN_TXBCR_CR9(value) (MCAN_TXBCR_CR9_Msk & ((value) << MCAN_TXBCR_CR9_Pos)) +#define MCAN_TXBCR_CR10_Pos _U_(10) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Position */ +#define MCAN_TXBCR_CR10_Msk (_U_(0x1) << MCAN_TXBCR_CR10_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Mask */ +#define MCAN_TXBCR_CR10(value) (MCAN_TXBCR_CR10_Msk & ((value) << MCAN_TXBCR_CR10_Pos)) +#define MCAN_TXBCR_CR11_Pos _U_(11) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Position */ +#define MCAN_TXBCR_CR11_Msk (_U_(0x1) << MCAN_TXBCR_CR11_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Mask */ +#define MCAN_TXBCR_CR11(value) (MCAN_TXBCR_CR11_Msk & ((value) << MCAN_TXBCR_CR11_Pos)) +#define MCAN_TXBCR_CR12_Pos _U_(12) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Position */ +#define MCAN_TXBCR_CR12_Msk (_U_(0x1) << MCAN_TXBCR_CR12_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Mask */ +#define MCAN_TXBCR_CR12(value) (MCAN_TXBCR_CR12_Msk & ((value) << MCAN_TXBCR_CR12_Pos)) +#define MCAN_TXBCR_CR13_Pos _U_(13) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Position */ +#define MCAN_TXBCR_CR13_Msk (_U_(0x1) << MCAN_TXBCR_CR13_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Mask */ +#define MCAN_TXBCR_CR13(value) (MCAN_TXBCR_CR13_Msk & ((value) << MCAN_TXBCR_CR13_Pos)) +#define MCAN_TXBCR_CR14_Pos _U_(14) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Position */ +#define MCAN_TXBCR_CR14_Msk (_U_(0x1) << MCAN_TXBCR_CR14_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Mask */ +#define MCAN_TXBCR_CR14(value) (MCAN_TXBCR_CR14_Msk & ((value) << MCAN_TXBCR_CR14_Pos)) +#define MCAN_TXBCR_CR15_Pos _U_(15) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Position */ +#define MCAN_TXBCR_CR15_Msk (_U_(0x1) << MCAN_TXBCR_CR15_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Mask */ +#define MCAN_TXBCR_CR15(value) (MCAN_TXBCR_CR15_Msk & ((value) << MCAN_TXBCR_CR15_Pos)) +#define MCAN_TXBCR_CR16_Pos _U_(16) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Position */ +#define MCAN_TXBCR_CR16_Msk (_U_(0x1) << MCAN_TXBCR_CR16_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Mask */ +#define MCAN_TXBCR_CR16(value) (MCAN_TXBCR_CR16_Msk & ((value) << MCAN_TXBCR_CR16_Pos)) +#define MCAN_TXBCR_CR17_Pos _U_(17) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Position */ +#define MCAN_TXBCR_CR17_Msk (_U_(0x1) << MCAN_TXBCR_CR17_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Mask */ +#define MCAN_TXBCR_CR17(value) (MCAN_TXBCR_CR17_Msk & ((value) << MCAN_TXBCR_CR17_Pos)) +#define MCAN_TXBCR_CR18_Pos _U_(18) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Position */ +#define MCAN_TXBCR_CR18_Msk (_U_(0x1) << MCAN_TXBCR_CR18_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Mask */ +#define MCAN_TXBCR_CR18(value) (MCAN_TXBCR_CR18_Msk & ((value) << MCAN_TXBCR_CR18_Pos)) +#define MCAN_TXBCR_CR19_Pos _U_(19) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Position */ +#define MCAN_TXBCR_CR19_Msk (_U_(0x1) << MCAN_TXBCR_CR19_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Mask */ +#define MCAN_TXBCR_CR19(value) (MCAN_TXBCR_CR19_Msk & ((value) << MCAN_TXBCR_CR19_Pos)) +#define MCAN_TXBCR_CR20_Pos _U_(20) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Position */ +#define MCAN_TXBCR_CR20_Msk (_U_(0x1) << MCAN_TXBCR_CR20_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Mask */ +#define MCAN_TXBCR_CR20(value) (MCAN_TXBCR_CR20_Msk & ((value) << MCAN_TXBCR_CR20_Pos)) +#define MCAN_TXBCR_CR21_Pos _U_(21) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Position */ +#define MCAN_TXBCR_CR21_Msk (_U_(0x1) << MCAN_TXBCR_CR21_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Mask */ +#define MCAN_TXBCR_CR21(value) (MCAN_TXBCR_CR21_Msk & ((value) << MCAN_TXBCR_CR21_Pos)) +#define MCAN_TXBCR_CR22_Pos _U_(22) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Position */ +#define MCAN_TXBCR_CR22_Msk (_U_(0x1) << MCAN_TXBCR_CR22_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Mask */ +#define MCAN_TXBCR_CR22(value) (MCAN_TXBCR_CR22_Msk & ((value) << MCAN_TXBCR_CR22_Pos)) +#define MCAN_TXBCR_CR23_Pos _U_(23) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Position */ +#define MCAN_TXBCR_CR23_Msk (_U_(0x1) << MCAN_TXBCR_CR23_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Mask */ +#define MCAN_TXBCR_CR23(value) (MCAN_TXBCR_CR23_Msk & ((value) << MCAN_TXBCR_CR23_Pos)) +#define MCAN_TXBCR_CR24_Pos _U_(24) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Position */ +#define MCAN_TXBCR_CR24_Msk (_U_(0x1) << MCAN_TXBCR_CR24_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Mask */ +#define MCAN_TXBCR_CR24(value) (MCAN_TXBCR_CR24_Msk & ((value) << MCAN_TXBCR_CR24_Pos)) +#define MCAN_TXBCR_CR25_Pos _U_(25) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Position */ +#define MCAN_TXBCR_CR25_Msk (_U_(0x1) << MCAN_TXBCR_CR25_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Mask */ +#define MCAN_TXBCR_CR25(value) (MCAN_TXBCR_CR25_Msk & ((value) << MCAN_TXBCR_CR25_Pos)) +#define MCAN_TXBCR_CR26_Pos _U_(26) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Position */ +#define MCAN_TXBCR_CR26_Msk (_U_(0x1) << MCAN_TXBCR_CR26_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Mask */ +#define MCAN_TXBCR_CR26(value) (MCAN_TXBCR_CR26_Msk & ((value) << MCAN_TXBCR_CR26_Pos)) +#define MCAN_TXBCR_CR27_Pos _U_(27) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Position */ +#define MCAN_TXBCR_CR27_Msk (_U_(0x1) << MCAN_TXBCR_CR27_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Mask */ +#define MCAN_TXBCR_CR27(value) (MCAN_TXBCR_CR27_Msk & ((value) << MCAN_TXBCR_CR27_Pos)) +#define MCAN_TXBCR_CR28_Pos _U_(28) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Position */ +#define MCAN_TXBCR_CR28_Msk (_U_(0x1) << MCAN_TXBCR_CR28_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Mask */ +#define MCAN_TXBCR_CR28(value) (MCAN_TXBCR_CR28_Msk & ((value) << MCAN_TXBCR_CR28_Pos)) +#define MCAN_TXBCR_CR29_Pos _U_(29) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Position */ +#define MCAN_TXBCR_CR29_Msk (_U_(0x1) << MCAN_TXBCR_CR29_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Mask */ +#define MCAN_TXBCR_CR29(value) (MCAN_TXBCR_CR29_Msk & ((value) << MCAN_TXBCR_CR29_Pos)) +#define MCAN_TXBCR_CR30_Pos _U_(30) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Position */ +#define MCAN_TXBCR_CR30_Msk (_U_(0x1) << MCAN_TXBCR_CR30_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Mask */ +#define MCAN_TXBCR_CR30(value) (MCAN_TXBCR_CR30_Msk & ((value) << MCAN_TXBCR_CR30_Pos)) +#define MCAN_TXBCR_CR31_Pos _U_(31) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Position */ +#define MCAN_TXBCR_CR31_Msk (_U_(0x1) << MCAN_TXBCR_CR31_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Mask */ +#define MCAN_TXBCR_CR31(value) (MCAN_TXBCR_CR31_Msk & ((value) << MCAN_TXBCR_CR31_Pos)) +#define MCAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCR) Register Mask */ + +#define MCAN_TXBCR_CR_Pos _U_(0) /**< (MCAN_TXBCR Position) Cancellation Request for Transmit Buffer 3x */ +#define MCAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCR_CR_Pos) /**< (MCAN_TXBCR Mask) CR */ +#define MCAN_TXBCR_CR(value) (MCAN_TXBCR_CR_Msk & ((value) << MCAN_TXBCR_CR_Pos)) + +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) ( R/ 32) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0_Pos _U_(0) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Position */ +#define MCAN_TXBTO_TO0_Msk (_U_(0x1) << MCAN_TXBTO_TO0_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Mask */ +#define MCAN_TXBTO_TO0(value) (MCAN_TXBTO_TO0_Msk & ((value) << MCAN_TXBTO_TO0_Pos)) +#define MCAN_TXBTO_TO1_Pos _U_(1) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Position */ +#define MCAN_TXBTO_TO1_Msk (_U_(0x1) << MCAN_TXBTO_TO1_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Mask */ +#define MCAN_TXBTO_TO1(value) (MCAN_TXBTO_TO1_Msk & ((value) << MCAN_TXBTO_TO1_Pos)) +#define MCAN_TXBTO_TO2_Pos _U_(2) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Position */ +#define MCAN_TXBTO_TO2_Msk (_U_(0x1) << MCAN_TXBTO_TO2_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Mask */ +#define MCAN_TXBTO_TO2(value) (MCAN_TXBTO_TO2_Msk & ((value) << MCAN_TXBTO_TO2_Pos)) +#define MCAN_TXBTO_TO3_Pos _U_(3) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Position */ +#define MCAN_TXBTO_TO3_Msk (_U_(0x1) << MCAN_TXBTO_TO3_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Mask */ +#define MCAN_TXBTO_TO3(value) (MCAN_TXBTO_TO3_Msk & ((value) << MCAN_TXBTO_TO3_Pos)) +#define MCAN_TXBTO_TO4_Pos _U_(4) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Position */ +#define MCAN_TXBTO_TO4_Msk (_U_(0x1) << MCAN_TXBTO_TO4_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Mask */ +#define MCAN_TXBTO_TO4(value) (MCAN_TXBTO_TO4_Msk & ((value) << MCAN_TXBTO_TO4_Pos)) +#define MCAN_TXBTO_TO5_Pos _U_(5) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Position */ +#define MCAN_TXBTO_TO5_Msk (_U_(0x1) << MCAN_TXBTO_TO5_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Mask */ +#define MCAN_TXBTO_TO5(value) (MCAN_TXBTO_TO5_Msk & ((value) << MCAN_TXBTO_TO5_Pos)) +#define MCAN_TXBTO_TO6_Pos _U_(6) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Position */ +#define MCAN_TXBTO_TO6_Msk (_U_(0x1) << MCAN_TXBTO_TO6_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Mask */ +#define MCAN_TXBTO_TO6(value) (MCAN_TXBTO_TO6_Msk & ((value) << MCAN_TXBTO_TO6_Pos)) +#define MCAN_TXBTO_TO7_Pos _U_(7) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Position */ +#define MCAN_TXBTO_TO7_Msk (_U_(0x1) << MCAN_TXBTO_TO7_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Mask */ +#define MCAN_TXBTO_TO7(value) (MCAN_TXBTO_TO7_Msk & ((value) << MCAN_TXBTO_TO7_Pos)) +#define MCAN_TXBTO_TO8_Pos _U_(8) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Position */ +#define MCAN_TXBTO_TO8_Msk (_U_(0x1) << MCAN_TXBTO_TO8_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Mask */ +#define MCAN_TXBTO_TO8(value) (MCAN_TXBTO_TO8_Msk & ((value) << MCAN_TXBTO_TO8_Pos)) +#define MCAN_TXBTO_TO9_Pos _U_(9) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Position */ +#define MCAN_TXBTO_TO9_Msk (_U_(0x1) << MCAN_TXBTO_TO9_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Mask */ +#define MCAN_TXBTO_TO9(value) (MCAN_TXBTO_TO9_Msk & ((value) << MCAN_TXBTO_TO9_Pos)) +#define MCAN_TXBTO_TO10_Pos _U_(10) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Position */ +#define MCAN_TXBTO_TO10_Msk (_U_(0x1) << MCAN_TXBTO_TO10_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Mask */ +#define MCAN_TXBTO_TO10(value) (MCAN_TXBTO_TO10_Msk & ((value) << MCAN_TXBTO_TO10_Pos)) +#define MCAN_TXBTO_TO11_Pos _U_(11) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Position */ +#define MCAN_TXBTO_TO11_Msk (_U_(0x1) << MCAN_TXBTO_TO11_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Mask */ +#define MCAN_TXBTO_TO11(value) (MCAN_TXBTO_TO11_Msk & ((value) << MCAN_TXBTO_TO11_Pos)) +#define MCAN_TXBTO_TO12_Pos _U_(12) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Position */ +#define MCAN_TXBTO_TO12_Msk (_U_(0x1) << MCAN_TXBTO_TO12_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Mask */ +#define MCAN_TXBTO_TO12(value) (MCAN_TXBTO_TO12_Msk & ((value) << MCAN_TXBTO_TO12_Pos)) +#define MCAN_TXBTO_TO13_Pos _U_(13) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Position */ +#define MCAN_TXBTO_TO13_Msk (_U_(0x1) << MCAN_TXBTO_TO13_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Mask */ +#define MCAN_TXBTO_TO13(value) (MCAN_TXBTO_TO13_Msk & ((value) << MCAN_TXBTO_TO13_Pos)) +#define MCAN_TXBTO_TO14_Pos _U_(14) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Position */ +#define MCAN_TXBTO_TO14_Msk (_U_(0x1) << MCAN_TXBTO_TO14_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Mask */ +#define MCAN_TXBTO_TO14(value) (MCAN_TXBTO_TO14_Msk & ((value) << MCAN_TXBTO_TO14_Pos)) +#define MCAN_TXBTO_TO15_Pos _U_(15) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Position */ +#define MCAN_TXBTO_TO15_Msk (_U_(0x1) << MCAN_TXBTO_TO15_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Mask */ +#define MCAN_TXBTO_TO15(value) (MCAN_TXBTO_TO15_Msk & ((value) << MCAN_TXBTO_TO15_Pos)) +#define MCAN_TXBTO_TO16_Pos _U_(16) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Position */ +#define MCAN_TXBTO_TO16_Msk (_U_(0x1) << MCAN_TXBTO_TO16_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Mask */ +#define MCAN_TXBTO_TO16(value) (MCAN_TXBTO_TO16_Msk & ((value) << MCAN_TXBTO_TO16_Pos)) +#define MCAN_TXBTO_TO17_Pos _U_(17) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Position */ +#define MCAN_TXBTO_TO17_Msk (_U_(0x1) << MCAN_TXBTO_TO17_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Mask */ +#define MCAN_TXBTO_TO17(value) (MCAN_TXBTO_TO17_Msk & ((value) << MCAN_TXBTO_TO17_Pos)) +#define MCAN_TXBTO_TO18_Pos _U_(18) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Position */ +#define MCAN_TXBTO_TO18_Msk (_U_(0x1) << MCAN_TXBTO_TO18_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Mask */ +#define MCAN_TXBTO_TO18(value) (MCAN_TXBTO_TO18_Msk & ((value) << MCAN_TXBTO_TO18_Pos)) +#define MCAN_TXBTO_TO19_Pos _U_(19) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Position */ +#define MCAN_TXBTO_TO19_Msk (_U_(0x1) << MCAN_TXBTO_TO19_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Mask */ +#define MCAN_TXBTO_TO19(value) (MCAN_TXBTO_TO19_Msk & ((value) << MCAN_TXBTO_TO19_Pos)) +#define MCAN_TXBTO_TO20_Pos _U_(20) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Position */ +#define MCAN_TXBTO_TO20_Msk (_U_(0x1) << MCAN_TXBTO_TO20_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Mask */ +#define MCAN_TXBTO_TO20(value) (MCAN_TXBTO_TO20_Msk & ((value) << MCAN_TXBTO_TO20_Pos)) +#define MCAN_TXBTO_TO21_Pos _U_(21) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Position */ +#define MCAN_TXBTO_TO21_Msk (_U_(0x1) << MCAN_TXBTO_TO21_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Mask */ +#define MCAN_TXBTO_TO21(value) (MCAN_TXBTO_TO21_Msk & ((value) << MCAN_TXBTO_TO21_Pos)) +#define MCAN_TXBTO_TO22_Pos _U_(22) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Position */ +#define MCAN_TXBTO_TO22_Msk (_U_(0x1) << MCAN_TXBTO_TO22_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Mask */ +#define MCAN_TXBTO_TO22(value) (MCAN_TXBTO_TO22_Msk & ((value) << MCAN_TXBTO_TO22_Pos)) +#define MCAN_TXBTO_TO23_Pos _U_(23) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Position */ +#define MCAN_TXBTO_TO23_Msk (_U_(0x1) << MCAN_TXBTO_TO23_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Mask */ +#define MCAN_TXBTO_TO23(value) (MCAN_TXBTO_TO23_Msk & ((value) << MCAN_TXBTO_TO23_Pos)) +#define MCAN_TXBTO_TO24_Pos _U_(24) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Position */ +#define MCAN_TXBTO_TO24_Msk (_U_(0x1) << MCAN_TXBTO_TO24_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Mask */ +#define MCAN_TXBTO_TO24(value) (MCAN_TXBTO_TO24_Msk & ((value) << MCAN_TXBTO_TO24_Pos)) +#define MCAN_TXBTO_TO25_Pos _U_(25) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Position */ +#define MCAN_TXBTO_TO25_Msk (_U_(0x1) << MCAN_TXBTO_TO25_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Mask */ +#define MCAN_TXBTO_TO25(value) (MCAN_TXBTO_TO25_Msk & ((value) << MCAN_TXBTO_TO25_Pos)) +#define MCAN_TXBTO_TO26_Pos _U_(26) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Position */ +#define MCAN_TXBTO_TO26_Msk (_U_(0x1) << MCAN_TXBTO_TO26_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Mask */ +#define MCAN_TXBTO_TO26(value) (MCAN_TXBTO_TO26_Msk & ((value) << MCAN_TXBTO_TO26_Pos)) +#define MCAN_TXBTO_TO27_Pos _U_(27) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Position */ +#define MCAN_TXBTO_TO27_Msk (_U_(0x1) << MCAN_TXBTO_TO27_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Mask */ +#define MCAN_TXBTO_TO27(value) (MCAN_TXBTO_TO27_Msk & ((value) << MCAN_TXBTO_TO27_Pos)) +#define MCAN_TXBTO_TO28_Pos _U_(28) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Position */ +#define MCAN_TXBTO_TO28_Msk (_U_(0x1) << MCAN_TXBTO_TO28_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Mask */ +#define MCAN_TXBTO_TO28(value) (MCAN_TXBTO_TO28_Msk & ((value) << MCAN_TXBTO_TO28_Pos)) +#define MCAN_TXBTO_TO29_Pos _U_(29) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Position */ +#define MCAN_TXBTO_TO29_Msk (_U_(0x1) << MCAN_TXBTO_TO29_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Mask */ +#define MCAN_TXBTO_TO29(value) (MCAN_TXBTO_TO29_Msk & ((value) << MCAN_TXBTO_TO29_Pos)) +#define MCAN_TXBTO_TO30_Pos _U_(30) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Position */ +#define MCAN_TXBTO_TO30_Msk (_U_(0x1) << MCAN_TXBTO_TO30_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Mask */ +#define MCAN_TXBTO_TO30(value) (MCAN_TXBTO_TO30_Msk & ((value) << MCAN_TXBTO_TO30_Pos)) +#define MCAN_TXBTO_TO31_Pos _U_(31) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Position */ +#define MCAN_TXBTO_TO31_Msk (_U_(0x1) << MCAN_TXBTO_TO31_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Mask */ +#define MCAN_TXBTO_TO31(value) (MCAN_TXBTO_TO31_Msk & ((value) << MCAN_TXBTO_TO31_Pos)) +#define MCAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTO) Register Mask */ + +#define MCAN_TXBTO_TO_Pos _U_(0) /**< (MCAN_TXBTO Position) Transmission Occurred for Buffer 3x */ +#define MCAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTO_TO_Pos) /**< (MCAN_TXBTO Mask) TO */ +#define MCAN_TXBTO_TO(value) (MCAN_TXBTO_TO_Msk & ((value) << MCAN_TXBTO_TO_Pos)) + +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) ( R/ 32) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0_Pos _U_(0) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Position */ +#define MCAN_TXBCF_CF0_Msk (_U_(0x1) << MCAN_TXBCF_CF0_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Mask */ +#define MCAN_TXBCF_CF0(value) (MCAN_TXBCF_CF0_Msk & ((value) << MCAN_TXBCF_CF0_Pos)) +#define MCAN_TXBCF_CF1_Pos _U_(1) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Position */ +#define MCAN_TXBCF_CF1_Msk (_U_(0x1) << MCAN_TXBCF_CF1_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Mask */ +#define MCAN_TXBCF_CF1(value) (MCAN_TXBCF_CF1_Msk & ((value) << MCAN_TXBCF_CF1_Pos)) +#define MCAN_TXBCF_CF2_Pos _U_(2) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Position */ +#define MCAN_TXBCF_CF2_Msk (_U_(0x1) << MCAN_TXBCF_CF2_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Mask */ +#define MCAN_TXBCF_CF2(value) (MCAN_TXBCF_CF2_Msk & ((value) << MCAN_TXBCF_CF2_Pos)) +#define MCAN_TXBCF_CF3_Pos _U_(3) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Position */ +#define MCAN_TXBCF_CF3_Msk (_U_(0x1) << MCAN_TXBCF_CF3_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Mask */ +#define MCAN_TXBCF_CF3(value) (MCAN_TXBCF_CF3_Msk & ((value) << MCAN_TXBCF_CF3_Pos)) +#define MCAN_TXBCF_CF4_Pos _U_(4) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Position */ +#define MCAN_TXBCF_CF4_Msk (_U_(0x1) << MCAN_TXBCF_CF4_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Mask */ +#define MCAN_TXBCF_CF4(value) (MCAN_TXBCF_CF4_Msk & ((value) << MCAN_TXBCF_CF4_Pos)) +#define MCAN_TXBCF_CF5_Pos _U_(5) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Position */ +#define MCAN_TXBCF_CF5_Msk (_U_(0x1) << MCAN_TXBCF_CF5_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Mask */ +#define MCAN_TXBCF_CF5(value) (MCAN_TXBCF_CF5_Msk & ((value) << MCAN_TXBCF_CF5_Pos)) +#define MCAN_TXBCF_CF6_Pos _U_(6) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Position */ +#define MCAN_TXBCF_CF6_Msk (_U_(0x1) << MCAN_TXBCF_CF6_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Mask */ +#define MCAN_TXBCF_CF6(value) (MCAN_TXBCF_CF6_Msk & ((value) << MCAN_TXBCF_CF6_Pos)) +#define MCAN_TXBCF_CF7_Pos _U_(7) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Position */ +#define MCAN_TXBCF_CF7_Msk (_U_(0x1) << MCAN_TXBCF_CF7_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Mask */ +#define MCAN_TXBCF_CF7(value) (MCAN_TXBCF_CF7_Msk & ((value) << MCAN_TXBCF_CF7_Pos)) +#define MCAN_TXBCF_CF8_Pos _U_(8) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Position */ +#define MCAN_TXBCF_CF8_Msk (_U_(0x1) << MCAN_TXBCF_CF8_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Mask */ +#define MCAN_TXBCF_CF8(value) (MCAN_TXBCF_CF8_Msk & ((value) << MCAN_TXBCF_CF8_Pos)) +#define MCAN_TXBCF_CF9_Pos _U_(9) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Position */ +#define MCAN_TXBCF_CF9_Msk (_U_(0x1) << MCAN_TXBCF_CF9_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Mask */ +#define MCAN_TXBCF_CF9(value) (MCAN_TXBCF_CF9_Msk & ((value) << MCAN_TXBCF_CF9_Pos)) +#define MCAN_TXBCF_CF10_Pos _U_(10) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Position */ +#define MCAN_TXBCF_CF10_Msk (_U_(0x1) << MCAN_TXBCF_CF10_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Mask */ +#define MCAN_TXBCF_CF10(value) (MCAN_TXBCF_CF10_Msk & ((value) << MCAN_TXBCF_CF10_Pos)) +#define MCAN_TXBCF_CF11_Pos _U_(11) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Position */ +#define MCAN_TXBCF_CF11_Msk (_U_(0x1) << MCAN_TXBCF_CF11_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Mask */ +#define MCAN_TXBCF_CF11(value) (MCAN_TXBCF_CF11_Msk & ((value) << MCAN_TXBCF_CF11_Pos)) +#define MCAN_TXBCF_CF12_Pos _U_(12) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Position */ +#define MCAN_TXBCF_CF12_Msk (_U_(0x1) << MCAN_TXBCF_CF12_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Mask */ +#define MCAN_TXBCF_CF12(value) (MCAN_TXBCF_CF12_Msk & ((value) << MCAN_TXBCF_CF12_Pos)) +#define MCAN_TXBCF_CF13_Pos _U_(13) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Position */ +#define MCAN_TXBCF_CF13_Msk (_U_(0x1) << MCAN_TXBCF_CF13_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Mask */ +#define MCAN_TXBCF_CF13(value) (MCAN_TXBCF_CF13_Msk & ((value) << MCAN_TXBCF_CF13_Pos)) +#define MCAN_TXBCF_CF14_Pos _U_(14) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Position */ +#define MCAN_TXBCF_CF14_Msk (_U_(0x1) << MCAN_TXBCF_CF14_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Mask */ +#define MCAN_TXBCF_CF14(value) (MCAN_TXBCF_CF14_Msk & ((value) << MCAN_TXBCF_CF14_Pos)) +#define MCAN_TXBCF_CF15_Pos _U_(15) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Position */ +#define MCAN_TXBCF_CF15_Msk (_U_(0x1) << MCAN_TXBCF_CF15_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Mask */ +#define MCAN_TXBCF_CF15(value) (MCAN_TXBCF_CF15_Msk & ((value) << MCAN_TXBCF_CF15_Pos)) +#define MCAN_TXBCF_CF16_Pos _U_(16) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Position */ +#define MCAN_TXBCF_CF16_Msk (_U_(0x1) << MCAN_TXBCF_CF16_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Mask */ +#define MCAN_TXBCF_CF16(value) (MCAN_TXBCF_CF16_Msk & ((value) << MCAN_TXBCF_CF16_Pos)) +#define MCAN_TXBCF_CF17_Pos _U_(17) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Position */ +#define MCAN_TXBCF_CF17_Msk (_U_(0x1) << MCAN_TXBCF_CF17_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Mask */ +#define MCAN_TXBCF_CF17(value) (MCAN_TXBCF_CF17_Msk & ((value) << MCAN_TXBCF_CF17_Pos)) +#define MCAN_TXBCF_CF18_Pos _U_(18) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Position */ +#define MCAN_TXBCF_CF18_Msk (_U_(0x1) << MCAN_TXBCF_CF18_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Mask */ +#define MCAN_TXBCF_CF18(value) (MCAN_TXBCF_CF18_Msk & ((value) << MCAN_TXBCF_CF18_Pos)) +#define MCAN_TXBCF_CF19_Pos _U_(19) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Position */ +#define MCAN_TXBCF_CF19_Msk (_U_(0x1) << MCAN_TXBCF_CF19_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Mask */ +#define MCAN_TXBCF_CF19(value) (MCAN_TXBCF_CF19_Msk & ((value) << MCAN_TXBCF_CF19_Pos)) +#define MCAN_TXBCF_CF20_Pos _U_(20) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Position */ +#define MCAN_TXBCF_CF20_Msk (_U_(0x1) << MCAN_TXBCF_CF20_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Mask */ +#define MCAN_TXBCF_CF20(value) (MCAN_TXBCF_CF20_Msk & ((value) << MCAN_TXBCF_CF20_Pos)) +#define MCAN_TXBCF_CF21_Pos _U_(21) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Position */ +#define MCAN_TXBCF_CF21_Msk (_U_(0x1) << MCAN_TXBCF_CF21_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Mask */ +#define MCAN_TXBCF_CF21(value) (MCAN_TXBCF_CF21_Msk & ((value) << MCAN_TXBCF_CF21_Pos)) +#define MCAN_TXBCF_CF22_Pos _U_(22) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Position */ +#define MCAN_TXBCF_CF22_Msk (_U_(0x1) << MCAN_TXBCF_CF22_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Mask */ +#define MCAN_TXBCF_CF22(value) (MCAN_TXBCF_CF22_Msk & ((value) << MCAN_TXBCF_CF22_Pos)) +#define MCAN_TXBCF_CF23_Pos _U_(23) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Position */ +#define MCAN_TXBCF_CF23_Msk (_U_(0x1) << MCAN_TXBCF_CF23_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Mask */ +#define MCAN_TXBCF_CF23(value) (MCAN_TXBCF_CF23_Msk & ((value) << MCAN_TXBCF_CF23_Pos)) +#define MCAN_TXBCF_CF24_Pos _U_(24) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Position */ +#define MCAN_TXBCF_CF24_Msk (_U_(0x1) << MCAN_TXBCF_CF24_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Mask */ +#define MCAN_TXBCF_CF24(value) (MCAN_TXBCF_CF24_Msk & ((value) << MCAN_TXBCF_CF24_Pos)) +#define MCAN_TXBCF_CF25_Pos _U_(25) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Position */ +#define MCAN_TXBCF_CF25_Msk (_U_(0x1) << MCAN_TXBCF_CF25_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Mask */ +#define MCAN_TXBCF_CF25(value) (MCAN_TXBCF_CF25_Msk & ((value) << MCAN_TXBCF_CF25_Pos)) +#define MCAN_TXBCF_CF26_Pos _U_(26) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Position */ +#define MCAN_TXBCF_CF26_Msk (_U_(0x1) << MCAN_TXBCF_CF26_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Mask */ +#define MCAN_TXBCF_CF26(value) (MCAN_TXBCF_CF26_Msk & ((value) << MCAN_TXBCF_CF26_Pos)) +#define MCAN_TXBCF_CF27_Pos _U_(27) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Position */ +#define MCAN_TXBCF_CF27_Msk (_U_(0x1) << MCAN_TXBCF_CF27_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Mask */ +#define MCAN_TXBCF_CF27(value) (MCAN_TXBCF_CF27_Msk & ((value) << MCAN_TXBCF_CF27_Pos)) +#define MCAN_TXBCF_CF28_Pos _U_(28) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Position */ +#define MCAN_TXBCF_CF28_Msk (_U_(0x1) << MCAN_TXBCF_CF28_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Mask */ +#define MCAN_TXBCF_CF28(value) (MCAN_TXBCF_CF28_Msk & ((value) << MCAN_TXBCF_CF28_Pos)) +#define MCAN_TXBCF_CF29_Pos _U_(29) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Position */ +#define MCAN_TXBCF_CF29_Msk (_U_(0x1) << MCAN_TXBCF_CF29_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Mask */ +#define MCAN_TXBCF_CF29(value) (MCAN_TXBCF_CF29_Msk & ((value) << MCAN_TXBCF_CF29_Pos)) +#define MCAN_TXBCF_CF30_Pos _U_(30) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Position */ +#define MCAN_TXBCF_CF30_Msk (_U_(0x1) << MCAN_TXBCF_CF30_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Mask */ +#define MCAN_TXBCF_CF30(value) (MCAN_TXBCF_CF30_Msk & ((value) << MCAN_TXBCF_CF30_Pos)) +#define MCAN_TXBCF_CF31_Pos _U_(31) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Position */ +#define MCAN_TXBCF_CF31_Msk (_U_(0x1) << MCAN_TXBCF_CF31_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Mask */ +#define MCAN_TXBCF_CF31(value) (MCAN_TXBCF_CF31_Msk & ((value) << MCAN_TXBCF_CF31_Pos)) +#define MCAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCF) Register Mask */ + +#define MCAN_TXBCF_CF_Pos _U_(0) /**< (MCAN_TXBCF Position) Cancellation Finished for Transmit Buffer 3x */ +#define MCAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCF_CF_Pos) /**< (MCAN_TXBCF Mask) CF */ +#define MCAN_TXBCF_CF(value) (MCAN_TXBCF_CF_Msk & ((value) << MCAN_TXBCF_CF_Pos)) + +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) (R/W 32) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0_Pos _U_(0) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Position */ +#define MCAN_TXBTIE_TIE0_Msk (_U_(0x1) << MCAN_TXBTIE_TIE0_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Mask */ +#define MCAN_TXBTIE_TIE0(value) (MCAN_TXBTIE_TIE0_Msk & ((value) << MCAN_TXBTIE_TIE0_Pos)) +#define MCAN_TXBTIE_TIE1_Pos _U_(1) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Position */ +#define MCAN_TXBTIE_TIE1_Msk (_U_(0x1) << MCAN_TXBTIE_TIE1_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Mask */ +#define MCAN_TXBTIE_TIE1(value) (MCAN_TXBTIE_TIE1_Msk & ((value) << MCAN_TXBTIE_TIE1_Pos)) +#define MCAN_TXBTIE_TIE2_Pos _U_(2) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Position */ +#define MCAN_TXBTIE_TIE2_Msk (_U_(0x1) << MCAN_TXBTIE_TIE2_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Mask */ +#define MCAN_TXBTIE_TIE2(value) (MCAN_TXBTIE_TIE2_Msk & ((value) << MCAN_TXBTIE_TIE2_Pos)) +#define MCAN_TXBTIE_TIE3_Pos _U_(3) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Position */ +#define MCAN_TXBTIE_TIE3_Msk (_U_(0x1) << MCAN_TXBTIE_TIE3_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Mask */ +#define MCAN_TXBTIE_TIE3(value) (MCAN_TXBTIE_TIE3_Msk & ((value) << MCAN_TXBTIE_TIE3_Pos)) +#define MCAN_TXBTIE_TIE4_Pos _U_(4) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Position */ +#define MCAN_TXBTIE_TIE4_Msk (_U_(0x1) << MCAN_TXBTIE_TIE4_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Mask */ +#define MCAN_TXBTIE_TIE4(value) (MCAN_TXBTIE_TIE4_Msk & ((value) << MCAN_TXBTIE_TIE4_Pos)) +#define MCAN_TXBTIE_TIE5_Pos _U_(5) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Position */ +#define MCAN_TXBTIE_TIE5_Msk (_U_(0x1) << MCAN_TXBTIE_TIE5_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Mask */ +#define MCAN_TXBTIE_TIE5(value) (MCAN_TXBTIE_TIE5_Msk & ((value) << MCAN_TXBTIE_TIE5_Pos)) +#define MCAN_TXBTIE_TIE6_Pos _U_(6) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Position */ +#define MCAN_TXBTIE_TIE6_Msk (_U_(0x1) << MCAN_TXBTIE_TIE6_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Mask */ +#define MCAN_TXBTIE_TIE6(value) (MCAN_TXBTIE_TIE6_Msk & ((value) << MCAN_TXBTIE_TIE6_Pos)) +#define MCAN_TXBTIE_TIE7_Pos _U_(7) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Position */ +#define MCAN_TXBTIE_TIE7_Msk (_U_(0x1) << MCAN_TXBTIE_TIE7_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Mask */ +#define MCAN_TXBTIE_TIE7(value) (MCAN_TXBTIE_TIE7_Msk & ((value) << MCAN_TXBTIE_TIE7_Pos)) +#define MCAN_TXBTIE_TIE8_Pos _U_(8) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Position */ +#define MCAN_TXBTIE_TIE8_Msk (_U_(0x1) << MCAN_TXBTIE_TIE8_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Mask */ +#define MCAN_TXBTIE_TIE8(value) (MCAN_TXBTIE_TIE8_Msk & ((value) << MCAN_TXBTIE_TIE8_Pos)) +#define MCAN_TXBTIE_TIE9_Pos _U_(9) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Position */ +#define MCAN_TXBTIE_TIE9_Msk (_U_(0x1) << MCAN_TXBTIE_TIE9_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Mask */ +#define MCAN_TXBTIE_TIE9(value) (MCAN_TXBTIE_TIE9_Msk & ((value) << MCAN_TXBTIE_TIE9_Pos)) +#define MCAN_TXBTIE_TIE10_Pos _U_(10) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Position */ +#define MCAN_TXBTIE_TIE10_Msk (_U_(0x1) << MCAN_TXBTIE_TIE10_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Mask */ +#define MCAN_TXBTIE_TIE10(value) (MCAN_TXBTIE_TIE10_Msk & ((value) << MCAN_TXBTIE_TIE10_Pos)) +#define MCAN_TXBTIE_TIE11_Pos _U_(11) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Position */ +#define MCAN_TXBTIE_TIE11_Msk (_U_(0x1) << MCAN_TXBTIE_TIE11_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Mask */ +#define MCAN_TXBTIE_TIE11(value) (MCAN_TXBTIE_TIE11_Msk & ((value) << MCAN_TXBTIE_TIE11_Pos)) +#define MCAN_TXBTIE_TIE12_Pos _U_(12) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Position */ +#define MCAN_TXBTIE_TIE12_Msk (_U_(0x1) << MCAN_TXBTIE_TIE12_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Mask */ +#define MCAN_TXBTIE_TIE12(value) (MCAN_TXBTIE_TIE12_Msk & ((value) << MCAN_TXBTIE_TIE12_Pos)) +#define MCAN_TXBTIE_TIE13_Pos _U_(13) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Position */ +#define MCAN_TXBTIE_TIE13_Msk (_U_(0x1) << MCAN_TXBTIE_TIE13_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Mask */ +#define MCAN_TXBTIE_TIE13(value) (MCAN_TXBTIE_TIE13_Msk & ((value) << MCAN_TXBTIE_TIE13_Pos)) +#define MCAN_TXBTIE_TIE14_Pos _U_(14) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Position */ +#define MCAN_TXBTIE_TIE14_Msk (_U_(0x1) << MCAN_TXBTIE_TIE14_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Mask */ +#define MCAN_TXBTIE_TIE14(value) (MCAN_TXBTIE_TIE14_Msk & ((value) << MCAN_TXBTIE_TIE14_Pos)) +#define MCAN_TXBTIE_TIE15_Pos _U_(15) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Position */ +#define MCAN_TXBTIE_TIE15_Msk (_U_(0x1) << MCAN_TXBTIE_TIE15_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Mask */ +#define MCAN_TXBTIE_TIE15(value) (MCAN_TXBTIE_TIE15_Msk & ((value) << MCAN_TXBTIE_TIE15_Pos)) +#define MCAN_TXBTIE_TIE16_Pos _U_(16) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Position */ +#define MCAN_TXBTIE_TIE16_Msk (_U_(0x1) << MCAN_TXBTIE_TIE16_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Mask */ +#define MCAN_TXBTIE_TIE16(value) (MCAN_TXBTIE_TIE16_Msk & ((value) << MCAN_TXBTIE_TIE16_Pos)) +#define MCAN_TXBTIE_TIE17_Pos _U_(17) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Position */ +#define MCAN_TXBTIE_TIE17_Msk (_U_(0x1) << MCAN_TXBTIE_TIE17_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Mask */ +#define MCAN_TXBTIE_TIE17(value) (MCAN_TXBTIE_TIE17_Msk & ((value) << MCAN_TXBTIE_TIE17_Pos)) +#define MCAN_TXBTIE_TIE18_Pos _U_(18) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Position */ +#define MCAN_TXBTIE_TIE18_Msk (_U_(0x1) << MCAN_TXBTIE_TIE18_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Mask */ +#define MCAN_TXBTIE_TIE18(value) (MCAN_TXBTIE_TIE18_Msk & ((value) << MCAN_TXBTIE_TIE18_Pos)) +#define MCAN_TXBTIE_TIE19_Pos _U_(19) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Position */ +#define MCAN_TXBTIE_TIE19_Msk (_U_(0x1) << MCAN_TXBTIE_TIE19_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Mask */ +#define MCAN_TXBTIE_TIE19(value) (MCAN_TXBTIE_TIE19_Msk & ((value) << MCAN_TXBTIE_TIE19_Pos)) +#define MCAN_TXBTIE_TIE20_Pos _U_(20) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Position */ +#define MCAN_TXBTIE_TIE20_Msk (_U_(0x1) << MCAN_TXBTIE_TIE20_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Mask */ +#define MCAN_TXBTIE_TIE20(value) (MCAN_TXBTIE_TIE20_Msk & ((value) << MCAN_TXBTIE_TIE20_Pos)) +#define MCAN_TXBTIE_TIE21_Pos _U_(21) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Position */ +#define MCAN_TXBTIE_TIE21_Msk (_U_(0x1) << MCAN_TXBTIE_TIE21_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Mask */ +#define MCAN_TXBTIE_TIE21(value) (MCAN_TXBTIE_TIE21_Msk & ((value) << MCAN_TXBTIE_TIE21_Pos)) +#define MCAN_TXBTIE_TIE22_Pos _U_(22) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Position */ +#define MCAN_TXBTIE_TIE22_Msk (_U_(0x1) << MCAN_TXBTIE_TIE22_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Mask */ +#define MCAN_TXBTIE_TIE22(value) (MCAN_TXBTIE_TIE22_Msk & ((value) << MCAN_TXBTIE_TIE22_Pos)) +#define MCAN_TXBTIE_TIE23_Pos _U_(23) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Position */ +#define MCAN_TXBTIE_TIE23_Msk (_U_(0x1) << MCAN_TXBTIE_TIE23_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Mask */ +#define MCAN_TXBTIE_TIE23(value) (MCAN_TXBTIE_TIE23_Msk & ((value) << MCAN_TXBTIE_TIE23_Pos)) +#define MCAN_TXBTIE_TIE24_Pos _U_(24) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Position */ +#define MCAN_TXBTIE_TIE24_Msk (_U_(0x1) << MCAN_TXBTIE_TIE24_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Mask */ +#define MCAN_TXBTIE_TIE24(value) (MCAN_TXBTIE_TIE24_Msk & ((value) << MCAN_TXBTIE_TIE24_Pos)) +#define MCAN_TXBTIE_TIE25_Pos _U_(25) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Position */ +#define MCAN_TXBTIE_TIE25_Msk (_U_(0x1) << MCAN_TXBTIE_TIE25_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Mask */ +#define MCAN_TXBTIE_TIE25(value) (MCAN_TXBTIE_TIE25_Msk & ((value) << MCAN_TXBTIE_TIE25_Pos)) +#define MCAN_TXBTIE_TIE26_Pos _U_(26) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Position */ +#define MCAN_TXBTIE_TIE26_Msk (_U_(0x1) << MCAN_TXBTIE_TIE26_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Mask */ +#define MCAN_TXBTIE_TIE26(value) (MCAN_TXBTIE_TIE26_Msk & ((value) << MCAN_TXBTIE_TIE26_Pos)) +#define MCAN_TXBTIE_TIE27_Pos _U_(27) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Position */ +#define MCAN_TXBTIE_TIE27_Msk (_U_(0x1) << MCAN_TXBTIE_TIE27_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Mask */ +#define MCAN_TXBTIE_TIE27(value) (MCAN_TXBTIE_TIE27_Msk & ((value) << MCAN_TXBTIE_TIE27_Pos)) +#define MCAN_TXBTIE_TIE28_Pos _U_(28) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Position */ +#define MCAN_TXBTIE_TIE28_Msk (_U_(0x1) << MCAN_TXBTIE_TIE28_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Mask */ +#define MCAN_TXBTIE_TIE28(value) (MCAN_TXBTIE_TIE28_Msk & ((value) << MCAN_TXBTIE_TIE28_Pos)) +#define MCAN_TXBTIE_TIE29_Pos _U_(29) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Position */ +#define MCAN_TXBTIE_TIE29_Msk (_U_(0x1) << MCAN_TXBTIE_TIE29_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Mask */ +#define MCAN_TXBTIE_TIE29(value) (MCAN_TXBTIE_TIE29_Msk & ((value) << MCAN_TXBTIE_TIE29_Pos)) +#define MCAN_TXBTIE_TIE30_Pos _U_(30) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Position */ +#define MCAN_TXBTIE_TIE30_Msk (_U_(0x1) << MCAN_TXBTIE_TIE30_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Mask */ +#define MCAN_TXBTIE_TIE30(value) (MCAN_TXBTIE_TIE30_Msk & ((value) << MCAN_TXBTIE_TIE30_Pos)) +#define MCAN_TXBTIE_TIE31_Pos _U_(31) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Position */ +#define MCAN_TXBTIE_TIE31_Msk (_U_(0x1) << MCAN_TXBTIE_TIE31_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Mask */ +#define MCAN_TXBTIE_TIE31(value) (MCAN_TXBTIE_TIE31_Msk & ((value) << MCAN_TXBTIE_TIE31_Pos)) +#define MCAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTIE) Register Mask */ + +#define MCAN_TXBTIE_TIE_Pos _U_(0) /**< (MCAN_TXBTIE Position) Transmission Interrupt Enable for Buffer 3x */ +#define MCAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTIE_TIE_Pos) /**< (MCAN_TXBTIE Mask) TIE */ +#define MCAN_TXBTIE_TIE(value) (MCAN_TXBTIE_TIE_Msk & ((value) << MCAN_TXBTIE_TIE_Pos)) + +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0_Pos _U_(0) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Position */ +#define MCAN_TXBCIE_CFIE0_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE0_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Mask */ +#define MCAN_TXBCIE_CFIE0(value) (MCAN_TXBCIE_CFIE0_Msk & ((value) << MCAN_TXBCIE_CFIE0_Pos)) +#define MCAN_TXBCIE_CFIE1_Pos _U_(1) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Position */ +#define MCAN_TXBCIE_CFIE1_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE1_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Mask */ +#define MCAN_TXBCIE_CFIE1(value) (MCAN_TXBCIE_CFIE1_Msk & ((value) << MCAN_TXBCIE_CFIE1_Pos)) +#define MCAN_TXBCIE_CFIE2_Pos _U_(2) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Position */ +#define MCAN_TXBCIE_CFIE2_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE2_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Mask */ +#define MCAN_TXBCIE_CFIE2(value) (MCAN_TXBCIE_CFIE2_Msk & ((value) << MCAN_TXBCIE_CFIE2_Pos)) +#define MCAN_TXBCIE_CFIE3_Pos _U_(3) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Position */ +#define MCAN_TXBCIE_CFIE3_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE3_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Mask */ +#define MCAN_TXBCIE_CFIE3(value) (MCAN_TXBCIE_CFIE3_Msk & ((value) << MCAN_TXBCIE_CFIE3_Pos)) +#define MCAN_TXBCIE_CFIE4_Pos _U_(4) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Position */ +#define MCAN_TXBCIE_CFIE4_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE4_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Mask */ +#define MCAN_TXBCIE_CFIE4(value) (MCAN_TXBCIE_CFIE4_Msk & ((value) << MCAN_TXBCIE_CFIE4_Pos)) +#define MCAN_TXBCIE_CFIE5_Pos _U_(5) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Position */ +#define MCAN_TXBCIE_CFIE5_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE5_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Mask */ +#define MCAN_TXBCIE_CFIE5(value) (MCAN_TXBCIE_CFIE5_Msk & ((value) << MCAN_TXBCIE_CFIE5_Pos)) +#define MCAN_TXBCIE_CFIE6_Pos _U_(6) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Position */ +#define MCAN_TXBCIE_CFIE6_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE6_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Mask */ +#define MCAN_TXBCIE_CFIE6(value) (MCAN_TXBCIE_CFIE6_Msk & ((value) << MCAN_TXBCIE_CFIE6_Pos)) +#define MCAN_TXBCIE_CFIE7_Pos _U_(7) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Position */ +#define MCAN_TXBCIE_CFIE7_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE7_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Mask */ +#define MCAN_TXBCIE_CFIE7(value) (MCAN_TXBCIE_CFIE7_Msk & ((value) << MCAN_TXBCIE_CFIE7_Pos)) +#define MCAN_TXBCIE_CFIE8_Pos _U_(8) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Position */ +#define MCAN_TXBCIE_CFIE8_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE8_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Mask */ +#define MCAN_TXBCIE_CFIE8(value) (MCAN_TXBCIE_CFIE8_Msk & ((value) << MCAN_TXBCIE_CFIE8_Pos)) +#define MCAN_TXBCIE_CFIE9_Pos _U_(9) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Position */ +#define MCAN_TXBCIE_CFIE9_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE9_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Mask */ +#define MCAN_TXBCIE_CFIE9(value) (MCAN_TXBCIE_CFIE9_Msk & ((value) << MCAN_TXBCIE_CFIE9_Pos)) +#define MCAN_TXBCIE_CFIE10_Pos _U_(10) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Position */ +#define MCAN_TXBCIE_CFIE10_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE10_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Mask */ +#define MCAN_TXBCIE_CFIE10(value) (MCAN_TXBCIE_CFIE10_Msk & ((value) << MCAN_TXBCIE_CFIE10_Pos)) +#define MCAN_TXBCIE_CFIE11_Pos _U_(11) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Position */ +#define MCAN_TXBCIE_CFIE11_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE11_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Mask */ +#define MCAN_TXBCIE_CFIE11(value) (MCAN_TXBCIE_CFIE11_Msk & ((value) << MCAN_TXBCIE_CFIE11_Pos)) +#define MCAN_TXBCIE_CFIE12_Pos _U_(12) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Position */ +#define MCAN_TXBCIE_CFIE12_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE12_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Mask */ +#define MCAN_TXBCIE_CFIE12(value) (MCAN_TXBCIE_CFIE12_Msk & ((value) << MCAN_TXBCIE_CFIE12_Pos)) +#define MCAN_TXBCIE_CFIE13_Pos _U_(13) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Position */ +#define MCAN_TXBCIE_CFIE13_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE13_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Mask */ +#define MCAN_TXBCIE_CFIE13(value) (MCAN_TXBCIE_CFIE13_Msk & ((value) << MCAN_TXBCIE_CFIE13_Pos)) +#define MCAN_TXBCIE_CFIE14_Pos _U_(14) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Position */ +#define MCAN_TXBCIE_CFIE14_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE14_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Mask */ +#define MCAN_TXBCIE_CFIE14(value) (MCAN_TXBCIE_CFIE14_Msk & ((value) << MCAN_TXBCIE_CFIE14_Pos)) +#define MCAN_TXBCIE_CFIE15_Pos _U_(15) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Position */ +#define MCAN_TXBCIE_CFIE15_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE15_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Mask */ +#define MCAN_TXBCIE_CFIE15(value) (MCAN_TXBCIE_CFIE15_Msk & ((value) << MCAN_TXBCIE_CFIE15_Pos)) +#define MCAN_TXBCIE_CFIE16_Pos _U_(16) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Position */ +#define MCAN_TXBCIE_CFIE16_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE16_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Mask */ +#define MCAN_TXBCIE_CFIE16(value) (MCAN_TXBCIE_CFIE16_Msk & ((value) << MCAN_TXBCIE_CFIE16_Pos)) +#define MCAN_TXBCIE_CFIE17_Pos _U_(17) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Position */ +#define MCAN_TXBCIE_CFIE17_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE17_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Mask */ +#define MCAN_TXBCIE_CFIE17(value) (MCAN_TXBCIE_CFIE17_Msk & ((value) << MCAN_TXBCIE_CFIE17_Pos)) +#define MCAN_TXBCIE_CFIE18_Pos _U_(18) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Position */ +#define MCAN_TXBCIE_CFIE18_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE18_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Mask */ +#define MCAN_TXBCIE_CFIE18(value) (MCAN_TXBCIE_CFIE18_Msk & ((value) << MCAN_TXBCIE_CFIE18_Pos)) +#define MCAN_TXBCIE_CFIE19_Pos _U_(19) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Position */ +#define MCAN_TXBCIE_CFIE19_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE19_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Mask */ +#define MCAN_TXBCIE_CFIE19(value) (MCAN_TXBCIE_CFIE19_Msk & ((value) << MCAN_TXBCIE_CFIE19_Pos)) +#define MCAN_TXBCIE_CFIE20_Pos _U_(20) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Position */ +#define MCAN_TXBCIE_CFIE20_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE20_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Mask */ +#define MCAN_TXBCIE_CFIE20(value) (MCAN_TXBCIE_CFIE20_Msk & ((value) << MCAN_TXBCIE_CFIE20_Pos)) +#define MCAN_TXBCIE_CFIE21_Pos _U_(21) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Position */ +#define MCAN_TXBCIE_CFIE21_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE21_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Mask */ +#define MCAN_TXBCIE_CFIE21(value) (MCAN_TXBCIE_CFIE21_Msk & ((value) << MCAN_TXBCIE_CFIE21_Pos)) +#define MCAN_TXBCIE_CFIE22_Pos _U_(22) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Position */ +#define MCAN_TXBCIE_CFIE22_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE22_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Mask */ +#define MCAN_TXBCIE_CFIE22(value) (MCAN_TXBCIE_CFIE22_Msk & ((value) << MCAN_TXBCIE_CFIE22_Pos)) +#define MCAN_TXBCIE_CFIE23_Pos _U_(23) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Position */ +#define MCAN_TXBCIE_CFIE23_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE23_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Mask */ +#define MCAN_TXBCIE_CFIE23(value) (MCAN_TXBCIE_CFIE23_Msk & ((value) << MCAN_TXBCIE_CFIE23_Pos)) +#define MCAN_TXBCIE_CFIE24_Pos _U_(24) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Position */ +#define MCAN_TXBCIE_CFIE24_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE24_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Mask */ +#define MCAN_TXBCIE_CFIE24(value) (MCAN_TXBCIE_CFIE24_Msk & ((value) << MCAN_TXBCIE_CFIE24_Pos)) +#define MCAN_TXBCIE_CFIE25_Pos _U_(25) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Position */ +#define MCAN_TXBCIE_CFIE25_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE25_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Mask */ +#define MCAN_TXBCIE_CFIE25(value) (MCAN_TXBCIE_CFIE25_Msk & ((value) << MCAN_TXBCIE_CFIE25_Pos)) +#define MCAN_TXBCIE_CFIE26_Pos _U_(26) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Position */ +#define MCAN_TXBCIE_CFIE26_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE26_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Mask */ +#define MCAN_TXBCIE_CFIE26(value) (MCAN_TXBCIE_CFIE26_Msk & ((value) << MCAN_TXBCIE_CFIE26_Pos)) +#define MCAN_TXBCIE_CFIE27_Pos _U_(27) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Position */ +#define MCAN_TXBCIE_CFIE27_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE27_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Mask */ +#define MCAN_TXBCIE_CFIE27(value) (MCAN_TXBCIE_CFIE27_Msk & ((value) << MCAN_TXBCIE_CFIE27_Pos)) +#define MCAN_TXBCIE_CFIE28_Pos _U_(28) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Position */ +#define MCAN_TXBCIE_CFIE28_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE28_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Mask */ +#define MCAN_TXBCIE_CFIE28(value) (MCAN_TXBCIE_CFIE28_Msk & ((value) << MCAN_TXBCIE_CFIE28_Pos)) +#define MCAN_TXBCIE_CFIE29_Pos _U_(29) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Position */ +#define MCAN_TXBCIE_CFIE29_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE29_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Mask */ +#define MCAN_TXBCIE_CFIE29(value) (MCAN_TXBCIE_CFIE29_Msk & ((value) << MCAN_TXBCIE_CFIE29_Pos)) +#define MCAN_TXBCIE_CFIE30_Pos _U_(30) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Position */ +#define MCAN_TXBCIE_CFIE30_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE30_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Mask */ +#define MCAN_TXBCIE_CFIE30(value) (MCAN_TXBCIE_CFIE30_Msk & ((value) << MCAN_TXBCIE_CFIE30_Pos)) +#define MCAN_TXBCIE_CFIE31_Pos _U_(31) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Position */ +#define MCAN_TXBCIE_CFIE31_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE31_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Mask */ +#define MCAN_TXBCIE_CFIE31(value) (MCAN_TXBCIE_CFIE31_Msk & ((value) << MCAN_TXBCIE_CFIE31_Pos)) +#define MCAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCIE) Register Mask */ + +#define MCAN_TXBCIE_CFIE_Pos _U_(0) /**< (MCAN_TXBCIE Position) Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ +#define MCAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCIE_CFIE_Pos) /**< (MCAN_TXBCIE Mask) CFIE */ +#define MCAN_TXBCIE_CFIE(value) (MCAN_TXBCIE_CFIE_Msk & ((value) << MCAN_TXBCIE_CFIE_Pos)) + +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) (R/W 32) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos _U_(2) /**< (MCAN_TXEFC) Event FIFO Start Address Position */ +#define MCAN_TXEFC_EFSA_Msk (_U_(0x3FFF) << MCAN_TXEFC_EFSA_Pos) /**< (MCAN_TXEFC) Event FIFO Start Address Mask */ +#define MCAN_TXEFC_EFSA(value) (MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)) +#define MCAN_TXEFC_EFS_Pos _U_(16) /**< (MCAN_TXEFC) Event FIFO Size Position */ +#define MCAN_TXEFC_EFS_Msk (_U_(0x3F) << MCAN_TXEFC_EFS_Pos) /**< (MCAN_TXEFC) Event FIFO Size Mask */ +#define MCAN_TXEFC_EFS(value) (MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)) +#define MCAN_TXEFC_EFWM_Pos _U_(24) /**< (MCAN_TXEFC) Event FIFO Watermark Position */ +#define MCAN_TXEFC_EFWM_Msk (_U_(0x3F) << MCAN_TXEFC_EFWM_Pos) /**< (MCAN_TXEFC) Event FIFO Watermark Mask */ +#define MCAN_TXEFC_EFWM(value) (MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)) +#define MCAN_TXEFC_Msk _U_(0x3F3FFFFC) /**< (MCAN_TXEFC) Register Mask */ + + +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) ( R/ 32) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos _U_(0) /**< (MCAN_TXEFS) Event FIFO Fill Level Position */ +#define MCAN_TXEFS_EFFL_Msk (_U_(0x3F) << MCAN_TXEFS_EFFL_Pos) /**< (MCAN_TXEFS) Event FIFO Fill Level Mask */ +#define MCAN_TXEFS_EFFL(value) (MCAN_TXEFS_EFFL_Msk & ((value) << MCAN_TXEFS_EFFL_Pos)) +#define MCAN_TXEFS_EFGI_Pos _U_(8) /**< (MCAN_TXEFS) Event FIFO Get Index Position */ +#define MCAN_TXEFS_EFGI_Msk (_U_(0x1F) << MCAN_TXEFS_EFGI_Pos) /**< (MCAN_TXEFS) Event FIFO Get Index Mask */ +#define MCAN_TXEFS_EFGI(value) (MCAN_TXEFS_EFGI_Msk & ((value) << MCAN_TXEFS_EFGI_Pos)) +#define MCAN_TXEFS_EFPI_Pos _U_(16) /**< (MCAN_TXEFS) Event FIFO Put Index Position */ +#define MCAN_TXEFS_EFPI_Msk (_U_(0x1F) << MCAN_TXEFS_EFPI_Pos) /**< (MCAN_TXEFS) Event FIFO Put Index Mask */ +#define MCAN_TXEFS_EFPI(value) (MCAN_TXEFS_EFPI_Msk & ((value) << MCAN_TXEFS_EFPI_Pos)) +#define MCAN_TXEFS_EFF_Pos _U_(24) /**< (MCAN_TXEFS) Event FIFO Full Position */ +#define MCAN_TXEFS_EFF_Msk (_U_(0x1) << MCAN_TXEFS_EFF_Pos) /**< (MCAN_TXEFS) Event FIFO Full Mask */ +#define MCAN_TXEFS_EFF(value) (MCAN_TXEFS_EFF_Msk & ((value) << MCAN_TXEFS_EFF_Pos)) +#define MCAN_TXEFS_TEFL_Pos _U_(25) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Position */ +#define MCAN_TXEFS_TEFL_Msk (_U_(0x1) << MCAN_TXEFS_TEFL_Pos) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Mask */ +#define MCAN_TXEFS_TEFL(value) (MCAN_TXEFS_TEFL_Msk & ((value) << MCAN_TXEFS_TEFL_Pos)) +#define MCAN_TXEFS_Msk _U_(0x031F1F3F) /**< (MCAN_TXEFS) Register Mask */ + + +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) (R/W 32) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos _U_(0) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Position */ +#define MCAN_TXEFA_EFAI_Msk (_U_(0x1F) << MCAN_TXEFA_EFAI_Pos) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Mask */ +#define MCAN_TXEFA_EFAI(value) (MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)) +#define MCAN_TXEFA_Msk _U_(0x0000001F) /**< (MCAN_TXEFA) Register Mask */ + + +/** \brief MCAN register offsets definitions */ +#define MCAN_RXBE_0_REG_OFST (0x00) /**< (MCAN_RXBE_0) Rx Buffer Element 0 Offset */ +#define MCAN_RXBE_1_REG_OFST (0x04) /**< (MCAN_RXBE_1) Rx Buffer Element 1 Offset */ +#define MCAN_RXBE_DATA_REG_OFST (0x08) /**< (MCAN_RXBE_DATA) Rx Buffer Element Data Offset */ +#define MCAN_RXF0E_0_REG_OFST (0x00) /**< (MCAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ +#define MCAN_RXF0E_1_REG_OFST (0x04) /**< (MCAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ +#define MCAN_RXF0E_DATA_REG_OFST (0x08) /**< (MCAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ +#define MCAN_RXF1E_0_REG_OFST (0x00) /**< (MCAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ +#define MCAN_RXF1E_1_REG_OFST (0x04) /**< (MCAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ +#define MCAN_RXF1E_DATA_REG_OFST (0x08) /**< (MCAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ +#define MCAN_TXBE_0_REG_OFST (0x00) /**< (MCAN_TXBE_0) Tx Buffer Element 0 Offset */ +#define MCAN_TXBE_1_REG_OFST (0x04) /**< (MCAN_TXBE_1) Tx Buffer Element 1 Offset */ +#define MCAN_TXBE_DATA_REG_OFST (0x08) /**< (MCAN_TXBE_DATA) Tx Buffer Element Data Offset */ +#define MCAN_TXEFE_0_REG_OFST (0x00) /**< (MCAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ +#define MCAN_TXEFE_1_REG_OFST (0x04) /**< (MCAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ +#define MCAN_SIDFE_0_REG_OFST (0x00) /**< (MCAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ +#define MCAN_XIDFE_0_REG_OFST (0x00) /**< (MCAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ +#define MCAN_XIDFE_1_REG_OFST (0x04) /**< (MCAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ +#define MCAN_CREL_REG_OFST (0x00) /**< (MCAN_CREL) Core Release Register Offset */ +#define MCAN_ENDN_REG_OFST (0x04) /**< (MCAN_ENDN) Endian Register Offset */ +#define MCAN_CUST_REG_OFST (0x08) /**< (MCAN_CUST) Customer Register Offset */ +#define MCAN_DBTP_REG_OFST (0x0C) /**< (MCAN_DBTP) Data Bit Timing and Prescaler Register Offset */ +#define MCAN_TEST_REG_OFST (0x10) /**< (MCAN_TEST) Test Register Offset */ +#define MCAN_RWD_REG_OFST (0x14) /**< (MCAN_RWD) RAM Watchdog Register Offset */ +#define MCAN_CCCR_REG_OFST (0x18) /**< (MCAN_CCCR) CC Control Register Offset */ +#define MCAN_NBTP_REG_OFST (0x1C) /**< (MCAN_NBTP) Nominal Bit Timing and Prescaler Register Offset */ +#define MCAN_TSCC_REG_OFST (0x20) /**< (MCAN_TSCC) Timestamp Counter Configuration Register Offset */ +#define MCAN_TSCV_REG_OFST (0x24) /**< (MCAN_TSCV) Timestamp Counter Value Register Offset */ +#define MCAN_TOCC_REG_OFST (0x28) /**< (MCAN_TOCC) Timeout Counter Configuration Register Offset */ +#define MCAN_TOCV_REG_OFST (0x2C) /**< (MCAN_TOCV) Timeout Counter Value Register Offset */ +#define MCAN_ECR_REG_OFST (0x40) /**< (MCAN_ECR) Error Counter Register Offset */ +#define MCAN_PSR_REG_OFST (0x44) /**< (MCAN_PSR) Protocol Status Register Offset */ +#define MCAN_TDCR_REG_OFST (0x48) /**< (MCAN_TDCR) Transmit Delay Compensation Register Offset */ +#define MCAN_IR_REG_OFST (0x50) /**< (MCAN_IR) Interrupt Register Offset */ +#define MCAN_IE_REG_OFST (0x54) /**< (MCAN_IE) Interrupt Enable Register Offset */ +#define MCAN_ILS_REG_OFST (0x58) /**< (MCAN_ILS) Interrupt Line Select Register Offset */ +#define MCAN_ILE_REG_OFST (0x5C) /**< (MCAN_ILE) Interrupt Line Enable Register Offset */ +#define MCAN_GFC_REG_OFST (0x80) /**< (MCAN_GFC) Global Filter Configuration Register Offset */ +#define MCAN_SIDFC_REG_OFST (0x84) /**< (MCAN_SIDFC) Standard ID Filter Configuration Register Offset */ +#define MCAN_XIDFC_REG_OFST (0x88) /**< (MCAN_XIDFC) Extended ID Filter Configuration Register Offset */ +#define MCAN_XIDAM_REG_OFST (0x90) /**< (MCAN_XIDAM) Extended ID AND Mask Register Offset */ +#define MCAN_HPMS_REG_OFST (0x94) /**< (MCAN_HPMS) High Priority Message Status Register Offset */ +#define MCAN_NDAT1_REG_OFST (0x98) /**< (MCAN_NDAT1) New Data 1 Register Offset */ +#define MCAN_NDAT2_REG_OFST (0x9C) /**< (MCAN_NDAT2) New Data 2 Register Offset */ +#define MCAN_RXF0C_REG_OFST (0xA0) /**< (MCAN_RXF0C) Receive FIFO 0 Configuration Register Offset */ +#define MCAN_RXF0S_REG_OFST (0xA4) /**< (MCAN_RXF0S) Receive FIFO 0 Status Register Offset */ +#define MCAN_RXF0A_REG_OFST (0xA8) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Register Offset */ +#define MCAN_RXBC_REG_OFST (0xAC) /**< (MCAN_RXBC) Receive Rx Buffer Configuration Register Offset */ +#define MCAN_RXF1C_REG_OFST (0xB0) /**< (MCAN_RXF1C) Receive FIFO 1 Configuration Register Offset */ +#define MCAN_RXF1S_REG_OFST (0xB4) /**< (MCAN_RXF1S) Receive FIFO 1 Status Register Offset */ +#define MCAN_RXF1A_REG_OFST (0xB8) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Register Offset */ +#define MCAN_RXESC_REG_OFST (0xBC) /**< (MCAN_RXESC) Receive Buffer / FIFO Element Size Configuration Register Offset */ +#define MCAN_TXBC_REG_OFST (0xC0) /**< (MCAN_TXBC) Transmit Buffer Configuration Register Offset */ +#define MCAN_TXFQS_REG_OFST (0xC4) /**< (MCAN_TXFQS) Transmit FIFO/Queue Status Register Offset */ +#define MCAN_TXESC_REG_OFST (0xC8) /**< (MCAN_TXESC) Transmit Buffer Element Size Configuration Register Offset */ +#define MCAN_TXBRP_REG_OFST (0xCC) /**< (MCAN_TXBRP) Transmit Buffer Request Pending Register Offset */ +#define MCAN_TXBAR_REG_OFST (0xD0) /**< (MCAN_TXBAR) Transmit Buffer Add Request Register Offset */ +#define MCAN_TXBCR_REG_OFST (0xD4) /**< (MCAN_TXBCR) Transmit Buffer Cancellation Request Register Offset */ +#define MCAN_TXBTO_REG_OFST (0xD8) /**< (MCAN_TXBTO) Transmit Buffer Transmission Occurred Register Offset */ +#define MCAN_TXBCF_REG_OFST (0xDC) /**< (MCAN_TXBCF) Transmit Buffer Cancellation Finished Register Offset */ +#define MCAN_TXBTIE_REG_OFST (0xE0) /**< (MCAN_TXBTIE) Transmit Buffer Transmission Interrupt Enable Register Offset */ +#define MCAN_TXBCIE_REG_OFST (0xE4) /**< (MCAN_TXBCIE) Transmit Buffer Cancellation Finished Interrupt Enable Register Offset */ +#define MCAN_TXEFC_REG_OFST (0xF0) /**< (MCAN_TXEFC) Transmit Event FIFO Configuration Register Offset */ +#define MCAN_TXEFS_REG_OFST (0xF4) /**< (MCAN_TXEFS) Transmit Event FIFO Status Register Offset */ +#define MCAN_TXEFA_REG_OFST (0xF8) /**< (MCAN_TXEFA) Transmit Event FIFO Acknowledge Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MCAN_RXBE register API structure */ +typedef struct +{ /* Rx Buffer Element */ + __IO uint32_t MCAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO uint32_t MCAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO uint32_t MCAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} mcan_rxbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF0E register API structure */ +typedef struct +{ /* Rx FIFO 0 Element */ + __IO uint32_t MCAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO uint32_t MCAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO uint32_t MCAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} mcan_rxf0e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_RXF1E register API structure */ +typedef struct +{ /* Rx FIFO 1 Element */ + __IO uint32_t MCAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO uint32_t MCAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO uint32_t MCAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} mcan_rxf1e_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXBE register API structure */ +typedef struct +{ /* Tx Buffer Element */ + __IO uint32_t MCAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO uint32_t MCAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO uint32_t MCAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} mcan_txbe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_TXEFE register API structure */ +typedef struct +{ /* Tx Event FIFO Element */ + __IO uint32_t MCAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO uint32_t MCAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} mcan_txefe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_SIDFE register API structure */ +typedef struct +{ /* Standard Message ID Filter Element */ + __IO uint32_t MCAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ +} mcan_sidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN_XIDFE register API structure */ +typedef struct +{ /* Extended Message ID Filter Element */ + __IO uint32_t MCAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO uint32_t MCAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} mcan_xidfe_registers_t +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; + +/** \brief MCAN register API structure */ +typedef struct +{ + __I uint32_t MCAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release Register */ + __I uint32_t MCAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian Register */ + __IO uint32_t MCAN_CUST; /**< Offset: 0x08 (R/W 32) Customer Register */ + __IO uint32_t MCAN_DBTP; /**< Offset: 0x0C (R/W 32) Data Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< Offset: 0x10 (R/W 32) Test Register */ + __IO uint32_t MCAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control Register */ + __IO uint32_t MCAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< Offset: 0x24 (R/W 32) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value Register */ + __I uint8_t Reserved1[0x10]; + __I uint32_t MCAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status Register */ + __IO uint32_t MCAN_TDCR; /**< Offset: 0x48 (R/W 32) Transmit Delay Compensation Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t MCAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable Register */ + __I uint8_t Reserved3[0x20]; + __IO uint32_t MCAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration Register */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t MCAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< Offset: 0xAC (R/W 32) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< Offset: 0xBC (R/W 32) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< Offset: 0xC0 (R/W 32) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< Offset: 0xC8 (R/W 32) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< Offset: 0xCC (R/ 32) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< Offset: 0xDC (R/ 32) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint8_t Reserved5[0x08]; + __IO uint32_t MCAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Transmit Event FIFO Acknowledge Register */ +} mcan_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_MCAN_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/pio.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/pio.h new file mode 100644 index 00000000..a87eeab7 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/pio.h @@ -0,0 +1,5045 @@ +/** + * \brief Component description for PIO + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_PIO_COMPONENT_H_ +#define _SAME70_PIO_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PIO */ +/* ************************************************************************** */ + +/* -------- PIO_PER : (PIO Offset: 0x00) ( /W 32) PIO Enable Register -------- */ +#define PIO_PER_P0_Pos _U_(0) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P0_Msk (_U_(0x1) << PIO_PER_P0_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P0(value) (PIO_PER_P0_Msk & ((value) << PIO_PER_P0_Pos)) +#define PIO_PER_P1_Pos _U_(1) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P1_Msk (_U_(0x1) << PIO_PER_P1_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P1(value) (PIO_PER_P1_Msk & ((value) << PIO_PER_P1_Pos)) +#define PIO_PER_P2_Pos _U_(2) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P2_Msk (_U_(0x1) << PIO_PER_P2_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P2(value) (PIO_PER_P2_Msk & ((value) << PIO_PER_P2_Pos)) +#define PIO_PER_P3_Pos _U_(3) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P3_Msk (_U_(0x1) << PIO_PER_P3_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P3(value) (PIO_PER_P3_Msk & ((value) << PIO_PER_P3_Pos)) +#define PIO_PER_P4_Pos _U_(4) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P4_Msk (_U_(0x1) << PIO_PER_P4_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P4(value) (PIO_PER_P4_Msk & ((value) << PIO_PER_P4_Pos)) +#define PIO_PER_P5_Pos _U_(5) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P5_Msk (_U_(0x1) << PIO_PER_P5_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P5(value) (PIO_PER_P5_Msk & ((value) << PIO_PER_P5_Pos)) +#define PIO_PER_P6_Pos _U_(6) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P6_Msk (_U_(0x1) << PIO_PER_P6_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P6(value) (PIO_PER_P6_Msk & ((value) << PIO_PER_P6_Pos)) +#define PIO_PER_P7_Pos _U_(7) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P7_Msk (_U_(0x1) << PIO_PER_P7_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P7(value) (PIO_PER_P7_Msk & ((value) << PIO_PER_P7_Pos)) +#define PIO_PER_P8_Pos _U_(8) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P8_Msk (_U_(0x1) << PIO_PER_P8_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P8(value) (PIO_PER_P8_Msk & ((value) << PIO_PER_P8_Pos)) +#define PIO_PER_P9_Pos _U_(9) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P9_Msk (_U_(0x1) << PIO_PER_P9_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P9(value) (PIO_PER_P9_Msk & ((value) << PIO_PER_P9_Pos)) +#define PIO_PER_P10_Pos _U_(10) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P10_Msk (_U_(0x1) << PIO_PER_P10_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P10(value) (PIO_PER_P10_Msk & ((value) << PIO_PER_P10_Pos)) +#define PIO_PER_P11_Pos _U_(11) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P11_Msk (_U_(0x1) << PIO_PER_P11_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P11(value) (PIO_PER_P11_Msk & ((value) << PIO_PER_P11_Pos)) +#define PIO_PER_P12_Pos _U_(12) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P12_Msk (_U_(0x1) << PIO_PER_P12_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P12(value) (PIO_PER_P12_Msk & ((value) << PIO_PER_P12_Pos)) +#define PIO_PER_P13_Pos _U_(13) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P13_Msk (_U_(0x1) << PIO_PER_P13_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P13(value) (PIO_PER_P13_Msk & ((value) << PIO_PER_P13_Pos)) +#define PIO_PER_P14_Pos _U_(14) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P14_Msk (_U_(0x1) << PIO_PER_P14_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P14(value) (PIO_PER_P14_Msk & ((value) << PIO_PER_P14_Pos)) +#define PIO_PER_P15_Pos _U_(15) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P15_Msk (_U_(0x1) << PIO_PER_P15_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P15(value) (PIO_PER_P15_Msk & ((value) << PIO_PER_P15_Pos)) +#define PIO_PER_P16_Pos _U_(16) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P16_Msk (_U_(0x1) << PIO_PER_P16_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P16(value) (PIO_PER_P16_Msk & ((value) << PIO_PER_P16_Pos)) +#define PIO_PER_P17_Pos _U_(17) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P17_Msk (_U_(0x1) << PIO_PER_P17_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P17(value) (PIO_PER_P17_Msk & ((value) << PIO_PER_P17_Pos)) +#define PIO_PER_P18_Pos _U_(18) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P18_Msk (_U_(0x1) << PIO_PER_P18_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P18(value) (PIO_PER_P18_Msk & ((value) << PIO_PER_P18_Pos)) +#define PIO_PER_P19_Pos _U_(19) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P19_Msk (_U_(0x1) << PIO_PER_P19_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P19(value) (PIO_PER_P19_Msk & ((value) << PIO_PER_P19_Pos)) +#define PIO_PER_P20_Pos _U_(20) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P20_Msk (_U_(0x1) << PIO_PER_P20_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P20(value) (PIO_PER_P20_Msk & ((value) << PIO_PER_P20_Pos)) +#define PIO_PER_P21_Pos _U_(21) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P21_Msk (_U_(0x1) << PIO_PER_P21_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P21(value) (PIO_PER_P21_Msk & ((value) << PIO_PER_P21_Pos)) +#define PIO_PER_P22_Pos _U_(22) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P22_Msk (_U_(0x1) << PIO_PER_P22_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P22(value) (PIO_PER_P22_Msk & ((value) << PIO_PER_P22_Pos)) +#define PIO_PER_P23_Pos _U_(23) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P23_Msk (_U_(0x1) << PIO_PER_P23_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P23(value) (PIO_PER_P23_Msk & ((value) << PIO_PER_P23_Pos)) +#define PIO_PER_P24_Pos _U_(24) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P24_Msk (_U_(0x1) << PIO_PER_P24_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P24(value) (PIO_PER_P24_Msk & ((value) << PIO_PER_P24_Pos)) +#define PIO_PER_P25_Pos _U_(25) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P25_Msk (_U_(0x1) << PIO_PER_P25_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P25(value) (PIO_PER_P25_Msk & ((value) << PIO_PER_P25_Pos)) +#define PIO_PER_P26_Pos _U_(26) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P26_Msk (_U_(0x1) << PIO_PER_P26_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P26(value) (PIO_PER_P26_Msk & ((value) << PIO_PER_P26_Pos)) +#define PIO_PER_P27_Pos _U_(27) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P27_Msk (_U_(0x1) << PIO_PER_P27_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P27(value) (PIO_PER_P27_Msk & ((value) << PIO_PER_P27_Pos)) +#define PIO_PER_P28_Pos _U_(28) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P28_Msk (_U_(0x1) << PIO_PER_P28_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P28(value) (PIO_PER_P28_Msk & ((value) << PIO_PER_P28_Pos)) +#define PIO_PER_P29_Pos _U_(29) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P29_Msk (_U_(0x1) << PIO_PER_P29_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P29(value) (PIO_PER_P29_Msk & ((value) << PIO_PER_P29_Pos)) +#define PIO_PER_P30_Pos _U_(30) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P30_Msk (_U_(0x1) << PIO_PER_P30_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P30(value) (PIO_PER_P30_Msk & ((value) << PIO_PER_P30_Pos)) +#define PIO_PER_P31_Pos _U_(31) /**< (PIO_PER) PIO Enable Position */ +#define PIO_PER_P31_Msk (_U_(0x1) << PIO_PER_P31_Pos) /**< (PIO_PER) PIO Enable Mask */ +#define PIO_PER_P31(value) (PIO_PER_P31_Msk & ((value) << PIO_PER_P31_Pos)) +#define PIO_PER_Msk _U_(0xFFFFFFFF) /**< (PIO_PER) Register Mask */ + +#define PIO_PER_P_Pos _U_(0) /**< (PIO_PER Position) PIO Enable */ +#define PIO_PER_P_Msk (_U_(0xFFFFFFFF) << PIO_PER_P_Pos) /**< (PIO_PER Mask) P */ +#define PIO_PER_P(value) (PIO_PER_P_Msk & ((value) << PIO_PER_P_Pos)) + +/* -------- PIO_PDR : (PIO Offset: 0x04) ( /W 32) PIO Disable Register -------- */ +#define PIO_PDR_P0_Pos _U_(0) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P0_Msk (_U_(0x1) << PIO_PDR_P0_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P0(value) (PIO_PDR_P0_Msk & ((value) << PIO_PDR_P0_Pos)) +#define PIO_PDR_P1_Pos _U_(1) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P1_Msk (_U_(0x1) << PIO_PDR_P1_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P1(value) (PIO_PDR_P1_Msk & ((value) << PIO_PDR_P1_Pos)) +#define PIO_PDR_P2_Pos _U_(2) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P2_Msk (_U_(0x1) << PIO_PDR_P2_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P2(value) (PIO_PDR_P2_Msk & ((value) << PIO_PDR_P2_Pos)) +#define PIO_PDR_P3_Pos _U_(3) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P3_Msk (_U_(0x1) << PIO_PDR_P3_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P3(value) (PIO_PDR_P3_Msk & ((value) << PIO_PDR_P3_Pos)) +#define PIO_PDR_P4_Pos _U_(4) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P4_Msk (_U_(0x1) << PIO_PDR_P4_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P4(value) (PIO_PDR_P4_Msk & ((value) << PIO_PDR_P4_Pos)) +#define PIO_PDR_P5_Pos _U_(5) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P5_Msk (_U_(0x1) << PIO_PDR_P5_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P5(value) (PIO_PDR_P5_Msk & ((value) << PIO_PDR_P5_Pos)) +#define PIO_PDR_P6_Pos _U_(6) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P6_Msk (_U_(0x1) << PIO_PDR_P6_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P6(value) (PIO_PDR_P6_Msk & ((value) << PIO_PDR_P6_Pos)) +#define PIO_PDR_P7_Pos _U_(7) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P7_Msk (_U_(0x1) << PIO_PDR_P7_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P7(value) (PIO_PDR_P7_Msk & ((value) << PIO_PDR_P7_Pos)) +#define PIO_PDR_P8_Pos _U_(8) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P8_Msk (_U_(0x1) << PIO_PDR_P8_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P8(value) (PIO_PDR_P8_Msk & ((value) << PIO_PDR_P8_Pos)) +#define PIO_PDR_P9_Pos _U_(9) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P9_Msk (_U_(0x1) << PIO_PDR_P9_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P9(value) (PIO_PDR_P9_Msk & ((value) << PIO_PDR_P9_Pos)) +#define PIO_PDR_P10_Pos _U_(10) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P10_Msk (_U_(0x1) << PIO_PDR_P10_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P10(value) (PIO_PDR_P10_Msk & ((value) << PIO_PDR_P10_Pos)) +#define PIO_PDR_P11_Pos _U_(11) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P11_Msk (_U_(0x1) << PIO_PDR_P11_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P11(value) (PIO_PDR_P11_Msk & ((value) << PIO_PDR_P11_Pos)) +#define PIO_PDR_P12_Pos _U_(12) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P12_Msk (_U_(0x1) << PIO_PDR_P12_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P12(value) (PIO_PDR_P12_Msk & ((value) << PIO_PDR_P12_Pos)) +#define PIO_PDR_P13_Pos _U_(13) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P13_Msk (_U_(0x1) << PIO_PDR_P13_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P13(value) (PIO_PDR_P13_Msk & ((value) << PIO_PDR_P13_Pos)) +#define PIO_PDR_P14_Pos _U_(14) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P14_Msk (_U_(0x1) << PIO_PDR_P14_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P14(value) (PIO_PDR_P14_Msk & ((value) << PIO_PDR_P14_Pos)) +#define PIO_PDR_P15_Pos _U_(15) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P15_Msk (_U_(0x1) << PIO_PDR_P15_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P15(value) (PIO_PDR_P15_Msk & ((value) << PIO_PDR_P15_Pos)) +#define PIO_PDR_P16_Pos _U_(16) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P16_Msk (_U_(0x1) << PIO_PDR_P16_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P16(value) (PIO_PDR_P16_Msk & ((value) << PIO_PDR_P16_Pos)) +#define PIO_PDR_P17_Pos _U_(17) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P17_Msk (_U_(0x1) << PIO_PDR_P17_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P17(value) (PIO_PDR_P17_Msk & ((value) << PIO_PDR_P17_Pos)) +#define PIO_PDR_P18_Pos _U_(18) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P18_Msk (_U_(0x1) << PIO_PDR_P18_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P18(value) (PIO_PDR_P18_Msk & ((value) << PIO_PDR_P18_Pos)) +#define PIO_PDR_P19_Pos _U_(19) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P19_Msk (_U_(0x1) << PIO_PDR_P19_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P19(value) (PIO_PDR_P19_Msk & ((value) << PIO_PDR_P19_Pos)) +#define PIO_PDR_P20_Pos _U_(20) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P20_Msk (_U_(0x1) << PIO_PDR_P20_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P20(value) (PIO_PDR_P20_Msk & ((value) << PIO_PDR_P20_Pos)) +#define PIO_PDR_P21_Pos _U_(21) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P21_Msk (_U_(0x1) << PIO_PDR_P21_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P21(value) (PIO_PDR_P21_Msk & ((value) << PIO_PDR_P21_Pos)) +#define PIO_PDR_P22_Pos _U_(22) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P22_Msk (_U_(0x1) << PIO_PDR_P22_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P22(value) (PIO_PDR_P22_Msk & ((value) << PIO_PDR_P22_Pos)) +#define PIO_PDR_P23_Pos _U_(23) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P23_Msk (_U_(0x1) << PIO_PDR_P23_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P23(value) (PIO_PDR_P23_Msk & ((value) << PIO_PDR_P23_Pos)) +#define PIO_PDR_P24_Pos _U_(24) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P24_Msk (_U_(0x1) << PIO_PDR_P24_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P24(value) (PIO_PDR_P24_Msk & ((value) << PIO_PDR_P24_Pos)) +#define PIO_PDR_P25_Pos _U_(25) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P25_Msk (_U_(0x1) << PIO_PDR_P25_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P25(value) (PIO_PDR_P25_Msk & ((value) << PIO_PDR_P25_Pos)) +#define PIO_PDR_P26_Pos _U_(26) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P26_Msk (_U_(0x1) << PIO_PDR_P26_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P26(value) (PIO_PDR_P26_Msk & ((value) << PIO_PDR_P26_Pos)) +#define PIO_PDR_P27_Pos _U_(27) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P27_Msk (_U_(0x1) << PIO_PDR_P27_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P27(value) (PIO_PDR_P27_Msk & ((value) << PIO_PDR_P27_Pos)) +#define PIO_PDR_P28_Pos _U_(28) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P28_Msk (_U_(0x1) << PIO_PDR_P28_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P28(value) (PIO_PDR_P28_Msk & ((value) << PIO_PDR_P28_Pos)) +#define PIO_PDR_P29_Pos _U_(29) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P29_Msk (_U_(0x1) << PIO_PDR_P29_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P29(value) (PIO_PDR_P29_Msk & ((value) << PIO_PDR_P29_Pos)) +#define PIO_PDR_P30_Pos _U_(30) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P30_Msk (_U_(0x1) << PIO_PDR_P30_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P30(value) (PIO_PDR_P30_Msk & ((value) << PIO_PDR_P30_Pos)) +#define PIO_PDR_P31_Pos _U_(31) /**< (PIO_PDR) PIO Disable Position */ +#define PIO_PDR_P31_Msk (_U_(0x1) << PIO_PDR_P31_Pos) /**< (PIO_PDR) PIO Disable Mask */ +#define PIO_PDR_P31(value) (PIO_PDR_P31_Msk & ((value) << PIO_PDR_P31_Pos)) +#define PIO_PDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDR) Register Mask */ + +#define PIO_PDR_P_Pos _U_(0) /**< (PIO_PDR Position) PIO Disable */ +#define PIO_PDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDR_P_Pos) /**< (PIO_PDR Mask) P */ +#define PIO_PDR_P(value) (PIO_PDR_P_Msk & ((value) << PIO_PDR_P_Pos)) + +/* -------- PIO_PSR : (PIO Offset: 0x08) ( R/ 32) PIO Status Register -------- */ +#define PIO_PSR_P0_Pos _U_(0) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P0_Msk (_U_(0x1) << PIO_PSR_P0_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P0(value) (PIO_PSR_P0_Msk & ((value) << PIO_PSR_P0_Pos)) +#define PIO_PSR_P1_Pos _U_(1) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P1_Msk (_U_(0x1) << PIO_PSR_P1_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P1(value) (PIO_PSR_P1_Msk & ((value) << PIO_PSR_P1_Pos)) +#define PIO_PSR_P2_Pos _U_(2) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P2_Msk (_U_(0x1) << PIO_PSR_P2_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P2(value) (PIO_PSR_P2_Msk & ((value) << PIO_PSR_P2_Pos)) +#define PIO_PSR_P3_Pos _U_(3) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P3_Msk (_U_(0x1) << PIO_PSR_P3_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P3(value) (PIO_PSR_P3_Msk & ((value) << PIO_PSR_P3_Pos)) +#define PIO_PSR_P4_Pos _U_(4) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P4_Msk (_U_(0x1) << PIO_PSR_P4_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P4(value) (PIO_PSR_P4_Msk & ((value) << PIO_PSR_P4_Pos)) +#define PIO_PSR_P5_Pos _U_(5) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P5_Msk (_U_(0x1) << PIO_PSR_P5_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P5(value) (PIO_PSR_P5_Msk & ((value) << PIO_PSR_P5_Pos)) +#define PIO_PSR_P6_Pos _U_(6) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P6_Msk (_U_(0x1) << PIO_PSR_P6_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P6(value) (PIO_PSR_P6_Msk & ((value) << PIO_PSR_P6_Pos)) +#define PIO_PSR_P7_Pos _U_(7) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P7_Msk (_U_(0x1) << PIO_PSR_P7_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P7(value) (PIO_PSR_P7_Msk & ((value) << PIO_PSR_P7_Pos)) +#define PIO_PSR_P8_Pos _U_(8) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P8_Msk (_U_(0x1) << PIO_PSR_P8_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P8(value) (PIO_PSR_P8_Msk & ((value) << PIO_PSR_P8_Pos)) +#define PIO_PSR_P9_Pos _U_(9) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P9_Msk (_U_(0x1) << PIO_PSR_P9_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P9(value) (PIO_PSR_P9_Msk & ((value) << PIO_PSR_P9_Pos)) +#define PIO_PSR_P10_Pos _U_(10) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P10_Msk (_U_(0x1) << PIO_PSR_P10_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P10(value) (PIO_PSR_P10_Msk & ((value) << PIO_PSR_P10_Pos)) +#define PIO_PSR_P11_Pos _U_(11) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P11_Msk (_U_(0x1) << PIO_PSR_P11_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P11(value) (PIO_PSR_P11_Msk & ((value) << PIO_PSR_P11_Pos)) +#define PIO_PSR_P12_Pos _U_(12) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P12_Msk (_U_(0x1) << PIO_PSR_P12_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P12(value) (PIO_PSR_P12_Msk & ((value) << PIO_PSR_P12_Pos)) +#define PIO_PSR_P13_Pos _U_(13) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P13_Msk (_U_(0x1) << PIO_PSR_P13_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P13(value) (PIO_PSR_P13_Msk & ((value) << PIO_PSR_P13_Pos)) +#define PIO_PSR_P14_Pos _U_(14) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P14_Msk (_U_(0x1) << PIO_PSR_P14_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P14(value) (PIO_PSR_P14_Msk & ((value) << PIO_PSR_P14_Pos)) +#define PIO_PSR_P15_Pos _U_(15) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P15_Msk (_U_(0x1) << PIO_PSR_P15_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P15(value) (PIO_PSR_P15_Msk & ((value) << PIO_PSR_P15_Pos)) +#define PIO_PSR_P16_Pos _U_(16) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P16_Msk (_U_(0x1) << PIO_PSR_P16_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P16(value) (PIO_PSR_P16_Msk & ((value) << PIO_PSR_P16_Pos)) +#define PIO_PSR_P17_Pos _U_(17) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P17_Msk (_U_(0x1) << PIO_PSR_P17_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P17(value) (PIO_PSR_P17_Msk & ((value) << PIO_PSR_P17_Pos)) +#define PIO_PSR_P18_Pos _U_(18) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P18_Msk (_U_(0x1) << PIO_PSR_P18_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P18(value) (PIO_PSR_P18_Msk & ((value) << PIO_PSR_P18_Pos)) +#define PIO_PSR_P19_Pos _U_(19) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P19_Msk (_U_(0x1) << PIO_PSR_P19_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P19(value) (PIO_PSR_P19_Msk & ((value) << PIO_PSR_P19_Pos)) +#define PIO_PSR_P20_Pos _U_(20) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P20_Msk (_U_(0x1) << PIO_PSR_P20_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P20(value) (PIO_PSR_P20_Msk & ((value) << PIO_PSR_P20_Pos)) +#define PIO_PSR_P21_Pos _U_(21) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P21_Msk (_U_(0x1) << PIO_PSR_P21_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P21(value) (PIO_PSR_P21_Msk & ((value) << PIO_PSR_P21_Pos)) +#define PIO_PSR_P22_Pos _U_(22) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P22_Msk (_U_(0x1) << PIO_PSR_P22_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P22(value) (PIO_PSR_P22_Msk & ((value) << PIO_PSR_P22_Pos)) +#define PIO_PSR_P23_Pos _U_(23) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P23_Msk (_U_(0x1) << PIO_PSR_P23_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P23(value) (PIO_PSR_P23_Msk & ((value) << PIO_PSR_P23_Pos)) +#define PIO_PSR_P24_Pos _U_(24) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P24_Msk (_U_(0x1) << PIO_PSR_P24_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P24(value) (PIO_PSR_P24_Msk & ((value) << PIO_PSR_P24_Pos)) +#define PIO_PSR_P25_Pos _U_(25) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P25_Msk (_U_(0x1) << PIO_PSR_P25_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P25(value) (PIO_PSR_P25_Msk & ((value) << PIO_PSR_P25_Pos)) +#define PIO_PSR_P26_Pos _U_(26) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P26_Msk (_U_(0x1) << PIO_PSR_P26_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P26(value) (PIO_PSR_P26_Msk & ((value) << PIO_PSR_P26_Pos)) +#define PIO_PSR_P27_Pos _U_(27) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P27_Msk (_U_(0x1) << PIO_PSR_P27_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P27(value) (PIO_PSR_P27_Msk & ((value) << PIO_PSR_P27_Pos)) +#define PIO_PSR_P28_Pos _U_(28) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P28_Msk (_U_(0x1) << PIO_PSR_P28_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P28(value) (PIO_PSR_P28_Msk & ((value) << PIO_PSR_P28_Pos)) +#define PIO_PSR_P29_Pos _U_(29) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P29_Msk (_U_(0x1) << PIO_PSR_P29_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P29(value) (PIO_PSR_P29_Msk & ((value) << PIO_PSR_P29_Pos)) +#define PIO_PSR_P30_Pos _U_(30) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P30_Msk (_U_(0x1) << PIO_PSR_P30_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P30(value) (PIO_PSR_P30_Msk & ((value) << PIO_PSR_P30_Pos)) +#define PIO_PSR_P31_Pos _U_(31) /**< (PIO_PSR) PIO Status Position */ +#define PIO_PSR_P31_Msk (_U_(0x1) << PIO_PSR_P31_Pos) /**< (PIO_PSR) PIO Status Mask */ +#define PIO_PSR_P31(value) (PIO_PSR_P31_Msk & ((value) << PIO_PSR_P31_Pos)) +#define PIO_PSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PSR) Register Mask */ + +#define PIO_PSR_P_Pos _U_(0) /**< (PIO_PSR Position) PIO Status */ +#define PIO_PSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PSR_P_Pos) /**< (PIO_PSR Mask) P */ +#define PIO_PSR_P(value) (PIO_PSR_P_Msk & ((value) << PIO_PSR_P_Pos)) + +/* -------- PIO_OER : (PIO Offset: 0x10) ( /W 32) Output Enable Register -------- */ +#define PIO_OER_P0_Pos _U_(0) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P0_Msk (_U_(0x1) << PIO_OER_P0_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P0(value) (PIO_OER_P0_Msk & ((value) << PIO_OER_P0_Pos)) +#define PIO_OER_P1_Pos _U_(1) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P1_Msk (_U_(0x1) << PIO_OER_P1_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P1(value) (PIO_OER_P1_Msk & ((value) << PIO_OER_P1_Pos)) +#define PIO_OER_P2_Pos _U_(2) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P2_Msk (_U_(0x1) << PIO_OER_P2_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P2(value) (PIO_OER_P2_Msk & ((value) << PIO_OER_P2_Pos)) +#define PIO_OER_P3_Pos _U_(3) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P3_Msk (_U_(0x1) << PIO_OER_P3_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P3(value) (PIO_OER_P3_Msk & ((value) << PIO_OER_P3_Pos)) +#define PIO_OER_P4_Pos _U_(4) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P4_Msk (_U_(0x1) << PIO_OER_P4_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P4(value) (PIO_OER_P4_Msk & ((value) << PIO_OER_P4_Pos)) +#define PIO_OER_P5_Pos _U_(5) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P5_Msk (_U_(0x1) << PIO_OER_P5_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P5(value) (PIO_OER_P5_Msk & ((value) << PIO_OER_P5_Pos)) +#define PIO_OER_P6_Pos _U_(6) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P6_Msk (_U_(0x1) << PIO_OER_P6_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P6(value) (PIO_OER_P6_Msk & ((value) << PIO_OER_P6_Pos)) +#define PIO_OER_P7_Pos _U_(7) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P7_Msk (_U_(0x1) << PIO_OER_P7_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P7(value) (PIO_OER_P7_Msk & ((value) << PIO_OER_P7_Pos)) +#define PIO_OER_P8_Pos _U_(8) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P8_Msk (_U_(0x1) << PIO_OER_P8_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P8(value) (PIO_OER_P8_Msk & ((value) << PIO_OER_P8_Pos)) +#define PIO_OER_P9_Pos _U_(9) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P9_Msk (_U_(0x1) << PIO_OER_P9_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P9(value) (PIO_OER_P9_Msk & ((value) << PIO_OER_P9_Pos)) +#define PIO_OER_P10_Pos _U_(10) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P10_Msk (_U_(0x1) << PIO_OER_P10_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P10(value) (PIO_OER_P10_Msk & ((value) << PIO_OER_P10_Pos)) +#define PIO_OER_P11_Pos _U_(11) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P11_Msk (_U_(0x1) << PIO_OER_P11_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P11(value) (PIO_OER_P11_Msk & ((value) << PIO_OER_P11_Pos)) +#define PIO_OER_P12_Pos _U_(12) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P12_Msk (_U_(0x1) << PIO_OER_P12_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P12(value) (PIO_OER_P12_Msk & ((value) << PIO_OER_P12_Pos)) +#define PIO_OER_P13_Pos _U_(13) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P13_Msk (_U_(0x1) << PIO_OER_P13_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P13(value) (PIO_OER_P13_Msk & ((value) << PIO_OER_P13_Pos)) +#define PIO_OER_P14_Pos _U_(14) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P14_Msk (_U_(0x1) << PIO_OER_P14_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P14(value) (PIO_OER_P14_Msk & ((value) << PIO_OER_P14_Pos)) +#define PIO_OER_P15_Pos _U_(15) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P15_Msk (_U_(0x1) << PIO_OER_P15_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P15(value) (PIO_OER_P15_Msk & ((value) << PIO_OER_P15_Pos)) +#define PIO_OER_P16_Pos _U_(16) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P16_Msk (_U_(0x1) << PIO_OER_P16_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P16(value) (PIO_OER_P16_Msk & ((value) << PIO_OER_P16_Pos)) +#define PIO_OER_P17_Pos _U_(17) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P17_Msk (_U_(0x1) << PIO_OER_P17_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P17(value) (PIO_OER_P17_Msk & ((value) << PIO_OER_P17_Pos)) +#define PIO_OER_P18_Pos _U_(18) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P18_Msk (_U_(0x1) << PIO_OER_P18_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P18(value) (PIO_OER_P18_Msk & ((value) << PIO_OER_P18_Pos)) +#define PIO_OER_P19_Pos _U_(19) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P19_Msk (_U_(0x1) << PIO_OER_P19_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P19(value) (PIO_OER_P19_Msk & ((value) << PIO_OER_P19_Pos)) +#define PIO_OER_P20_Pos _U_(20) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P20_Msk (_U_(0x1) << PIO_OER_P20_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P20(value) (PIO_OER_P20_Msk & ((value) << PIO_OER_P20_Pos)) +#define PIO_OER_P21_Pos _U_(21) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P21_Msk (_U_(0x1) << PIO_OER_P21_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P21(value) (PIO_OER_P21_Msk & ((value) << PIO_OER_P21_Pos)) +#define PIO_OER_P22_Pos _U_(22) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P22_Msk (_U_(0x1) << PIO_OER_P22_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P22(value) (PIO_OER_P22_Msk & ((value) << PIO_OER_P22_Pos)) +#define PIO_OER_P23_Pos _U_(23) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P23_Msk (_U_(0x1) << PIO_OER_P23_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P23(value) (PIO_OER_P23_Msk & ((value) << PIO_OER_P23_Pos)) +#define PIO_OER_P24_Pos _U_(24) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P24_Msk (_U_(0x1) << PIO_OER_P24_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P24(value) (PIO_OER_P24_Msk & ((value) << PIO_OER_P24_Pos)) +#define PIO_OER_P25_Pos _U_(25) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P25_Msk (_U_(0x1) << PIO_OER_P25_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P25(value) (PIO_OER_P25_Msk & ((value) << PIO_OER_P25_Pos)) +#define PIO_OER_P26_Pos _U_(26) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P26_Msk (_U_(0x1) << PIO_OER_P26_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P26(value) (PIO_OER_P26_Msk & ((value) << PIO_OER_P26_Pos)) +#define PIO_OER_P27_Pos _U_(27) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P27_Msk (_U_(0x1) << PIO_OER_P27_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P27(value) (PIO_OER_P27_Msk & ((value) << PIO_OER_P27_Pos)) +#define PIO_OER_P28_Pos _U_(28) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P28_Msk (_U_(0x1) << PIO_OER_P28_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P28(value) (PIO_OER_P28_Msk & ((value) << PIO_OER_P28_Pos)) +#define PIO_OER_P29_Pos _U_(29) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P29_Msk (_U_(0x1) << PIO_OER_P29_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P29(value) (PIO_OER_P29_Msk & ((value) << PIO_OER_P29_Pos)) +#define PIO_OER_P30_Pos _U_(30) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P30_Msk (_U_(0x1) << PIO_OER_P30_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P30(value) (PIO_OER_P30_Msk & ((value) << PIO_OER_P30_Pos)) +#define PIO_OER_P31_Pos _U_(31) /**< (PIO_OER) Output Enable Position */ +#define PIO_OER_P31_Msk (_U_(0x1) << PIO_OER_P31_Pos) /**< (PIO_OER) Output Enable Mask */ +#define PIO_OER_P31(value) (PIO_OER_P31_Msk & ((value) << PIO_OER_P31_Pos)) +#define PIO_OER_Msk _U_(0xFFFFFFFF) /**< (PIO_OER) Register Mask */ + +#define PIO_OER_P_Pos _U_(0) /**< (PIO_OER Position) Output Enable */ +#define PIO_OER_P_Msk (_U_(0xFFFFFFFF) << PIO_OER_P_Pos) /**< (PIO_OER Mask) P */ +#define PIO_OER_P(value) (PIO_OER_P_Msk & ((value) << PIO_OER_P_Pos)) + +/* -------- PIO_ODR : (PIO Offset: 0x14) ( /W 32) Output Disable Register -------- */ +#define PIO_ODR_P0_Pos _U_(0) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P0_Msk (_U_(0x1) << PIO_ODR_P0_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P0(value) (PIO_ODR_P0_Msk & ((value) << PIO_ODR_P0_Pos)) +#define PIO_ODR_P1_Pos _U_(1) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P1_Msk (_U_(0x1) << PIO_ODR_P1_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P1(value) (PIO_ODR_P1_Msk & ((value) << PIO_ODR_P1_Pos)) +#define PIO_ODR_P2_Pos _U_(2) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P2_Msk (_U_(0x1) << PIO_ODR_P2_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P2(value) (PIO_ODR_P2_Msk & ((value) << PIO_ODR_P2_Pos)) +#define PIO_ODR_P3_Pos _U_(3) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P3_Msk (_U_(0x1) << PIO_ODR_P3_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P3(value) (PIO_ODR_P3_Msk & ((value) << PIO_ODR_P3_Pos)) +#define PIO_ODR_P4_Pos _U_(4) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P4_Msk (_U_(0x1) << PIO_ODR_P4_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P4(value) (PIO_ODR_P4_Msk & ((value) << PIO_ODR_P4_Pos)) +#define PIO_ODR_P5_Pos _U_(5) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P5_Msk (_U_(0x1) << PIO_ODR_P5_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P5(value) (PIO_ODR_P5_Msk & ((value) << PIO_ODR_P5_Pos)) +#define PIO_ODR_P6_Pos _U_(6) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P6_Msk (_U_(0x1) << PIO_ODR_P6_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P6(value) (PIO_ODR_P6_Msk & ((value) << PIO_ODR_P6_Pos)) +#define PIO_ODR_P7_Pos _U_(7) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P7_Msk (_U_(0x1) << PIO_ODR_P7_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P7(value) (PIO_ODR_P7_Msk & ((value) << PIO_ODR_P7_Pos)) +#define PIO_ODR_P8_Pos _U_(8) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P8_Msk (_U_(0x1) << PIO_ODR_P8_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P8(value) (PIO_ODR_P8_Msk & ((value) << PIO_ODR_P8_Pos)) +#define PIO_ODR_P9_Pos _U_(9) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P9_Msk (_U_(0x1) << PIO_ODR_P9_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P9(value) (PIO_ODR_P9_Msk & ((value) << PIO_ODR_P9_Pos)) +#define PIO_ODR_P10_Pos _U_(10) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P10_Msk (_U_(0x1) << PIO_ODR_P10_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P10(value) (PIO_ODR_P10_Msk & ((value) << PIO_ODR_P10_Pos)) +#define PIO_ODR_P11_Pos _U_(11) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P11_Msk (_U_(0x1) << PIO_ODR_P11_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P11(value) (PIO_ODR_P11_Msk & ((value) << PIO_ODR_P11_Pos)) +#define PIO_ODR_P12_Pos _U_(12) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P12_Msk (_U_(0x1) << PIO_ODR_P12_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P12(value) (PIO_ODR_P12_Msk & ((value) << PIO_ODR_P12_Pos)) +#define PIO_ODR_P13_Pos _U_(13) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P13_Msk (_U_(0x1) << PIO_ODR_P13_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P13(value) (PIO_ODR_P13_Msk & ((value) << PIO_ODR_P13_Pos)) +#define PIO_ODR_P14_Pos _U_(14) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P14_Msk (_U_(0x1) << PIO_ODR_P14_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P14(value) (PIO_ODR_P14_Msk & ((value) << PIO_ODR_P14_Pos)) +#define PIO_ODR_P15_Pos _U_(15) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P15_Msk (_U_(0x1) << PIO_ODR_P15_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P15(value) (PIO_ODR_P15_Msk & ((value) << PIO_ODR_P15_Pos)) +#define PIO_ODR_P16_Pos _U_(16) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P16_Msk (_U_(0x1) << PIO_ODR_P16_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P16(value) (PIO_ODR_P16_Msk & ((value) << PIO_ODR_P16_Pos)) +#define PIO_ODR_P17_Pos _U_(17) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P17_Msk (_U_(0x1) << PIO_ODR_P17_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P17(value) (PIO_ODR_P17_Msk & ((value) << PIO_ODR_P17_Pos)) +#define PIO_ODR_P18_Pos _U_(18) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P18_Msk (_U_(0x1) << PIO_ODR_P18_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P18(value) (PIO_ODR_P18_Msk & ((value) << PIO_ODR_P18_Pos)) +#define PIO_ODR_P19_Pos _U_(19) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P19_Msk (_U_(0x1) << PIO_ODR_P19_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P19(value) (PIO_ODR_P19_Msk & ((value) << PIO_ODR_P19_Pos)) +#define PIO_ODR_P20_Pos _U_(20) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P20_Msk (_U_(0x1) << PIO_ODR_P20_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P20(value) (PIO_ODR_P20_Msk & ((value) << PIO_ODR_P20_Pos)) +#define PIO_ODR_P21_Pos _U_(21) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P21_Msk (_U_(0x1) << PIO_ODR_P21_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P21(value) (PIO_ODR_P21_Msk & ((value) << PIO_ODR_P21_Pos)) +#define PIO_ODR_P22_Pos _U_(22) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P22_Msk (_U_(0x1) << PIO_ODR_P22_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P22(value) (PIO_ODR_P22_Msk & ((value) << PIO_ODR_P22_Pos)) +#define PIO_ODR_P23_Pos _U_(23) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P23_Msk (_U_(0x1) << PIO_ODR_P23_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P23(value) (PIO_ODR_P23_Msk & ((value) << PIO_ODR_P23_Pos)) +#define PIO_ODR_P24_Pos _U_(24) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P24_Msk (_U_(0x1) << PIO_ODR_P24_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P24(value) (PIO_ODR_P24_Msk & ((value) << PIO_ODR_P24_Pos)) +#define PIO_ODR_P25_Pos _U_(25) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P25_Msk (_U_(0x1) << PIO_ODR_P25_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P25(value) (PIO_ODR_P25_Msk & ((value) << PIO_ODR_P25_Pos)) +#define PIO_ODR_P26_Pos _U_(26) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P26_Msk (_U_(0x1) << PIO_ODR_P26_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P26(value) (PIO_ODR_P26_Msk & ((value) << PIO_ODR_P26_Pos)) +#define PIO_ODR_P27_Pos _U_(27) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P27_Msk (_U_(0x1) << PIO_ODR_P27_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P27(value) (PIO_ODR_P27_Msk & ((value) << PIO_ODR_P27_Pos)) +#define PIO_ODR_P28_Pos _U_(28) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P28_Msk (_U_(0x1) << PIO_ODR_P28_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P28(value) (PIO_ODR_P28_Msk & ((value) << PIO_ODR_P28_Pos)) +#define PIO_ODR_P29_Pos _U_(29) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P29_Msk (_U_(0x1) << PIO_ODR_P29_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P29(value) (PIO_ODR_P29_Msk & ((value) << PIO_ODR_P29_Pos)) +#define PIO_ODR_P30_Pos _U_(30) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P30_Msk (_U_(0x1) << PIO_ODR_P30_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P30(value) (PIO_ODR_P30_Msk & ((value) << PIO_ODR_P30_Pos)) +#define PIO_ODR_P31_Pos _U_(31) /**< (PIO_ODR) Output Disable Position */ +#define PIO_ODR_P31_Msk (_U_(0x1) << PIO_ODR_P31_Pos) /**< (PIO_ODR) Output Disable Mask */ +#define PIO_ODR_P31(value) (PIO_ODR_P31_Msk & ((value) << PIO_ODR_P31_Pos)) +#define PIO_ODR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODR) Register Mask */ + +#define PIO_ODR_P_Pos _U_(0) /**< (PIO_ODR Position) Output Disable */ +#define PIO_ODR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODR_P_Pos) /**< (PIO_ODR Mask) P */ +#define PIO_ODR_P(value) (PIO_ODR_P_Msk & ((value) << PIO_ODR_P_Pos)) + +/* -------- PIO_OSR : (PIO Offset: 0x18) ( R/ 32) Output Status Register -------- */ +#define PIO_OSR_P0_Pos _U_(0) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P0_Msk (_U_(0x1) << PIO_OSR_P0_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P0(value) (PIO_OSR_P0_Msk & ((value) << PIO_OSR_P0_Pos)) +#define PIO_OSR_P1_Pos _U_(1) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P1_Msk (_U_(0x1) << PIO_OSR_P1_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P1(value) (PIO_OSR_P1_Msk & ((value) << PIO_OSR_P1_Pos)) +#define PIO_OSR_P2_Pos _U_(2) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P2_Msk (_U_(0x1) << PIO_OSR_P2_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P2(value) (PIO_OSR_P2_Msk & ((value) << PIO_OSR_P2_Pos)) +#define PIO_OSR_P3_Pos _U_(3) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P3_Msk (_U_(0x1) << PIO_OSR_P3_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P3(value) (PIO_OSR_P3_Msk & ((value) << PIO_OSR_P3_Pos)) +#define PIO_OSR_P4_Pos _U_(4) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P4_Msk (_U_(0x1) << PIO_OSR_P4_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P4(value) (PIO_OSR_P4_Msk & ((value) << PIO_OSR_P4_Pos)) +#define PIO_OSR_P5_Pos _U_(5) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P5_Msk (_U_(0x1) << PIO_OSR_P5_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P5(value) (PIO_OSR_P5_Msk & ((value) << PIO_OSR_P5_Pos)) +#define PIO_OSR_P6_Pos _U_(6) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P6_Msk (_U_(0x1) << PIO_OSR_P6_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P6(value) (PIO_OSR_P6_Msk & ((value) << PIO_OSR_P6_Pos)) +#define PIO_OSR_P7_Pos _U_(7) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P7_Msk (_U_(0x1) << PIO_OSR_P7_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P7(value) (PIO_OSR_P7_Msk & ((value) << PIO_OSR_P7_Pos)) +#define PIO_OSR_P8_Pos _U_(8) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P8_Msk (_U_(0x1) << PIO_OSR_P8_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P8(value) (PIO_OSR_P8_Msk & ((value) << PIO_OSR_P8_Pos)) +#define PIO_OSR_P9_Pos _U_(9) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P9_Msk (_U_(0x1) << PIO_OSR_P9_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P9(value) (PIO_OSR_P9_Msk & ((value) << PIO_OSR_P9_Pos)) +#define PIO_OSR_P10_Pos _U_(10) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P10_Msk (_U_(0x1) << PIO_OSR_P10_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P10(value) (PIO_OSR_P10_Msk & ((value) << PIO_OSR_P10_Pos)) +#define PIO_OSR_P11_Pos _U_(11) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P11_Msk (_U_(0x1) << PIO_OSR_P11_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P11(value) (PIO_OSR_P11_Msk & ((value) << PIO_OSR_P11_Pos)) +#define PIO_OSR_P12_Pos _U_(12) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P12_Msk (_U_(0x1) << PIO_OSR_P12_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P12(value) (PIO_OSR_P12_Msk & ((value) << PIO_OSR_P12_Pos)) +#define PIO_OSR_P13_Pos _U_(13) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P13_Msk (_U_(0x1) << PIO_OSR_P13_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P13(value) (PIO_OSR_P13_Msk & ((value) << PIO_OSR_P13_Pos)) +#define PIO_OSR_P14_Pos _U_(14) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P14_Msk (_U_(0x1) << PIO_OSR_P14_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P14(value) (PIO_OSR_P14_Msk & ((value) << PIO_OSR_P14_Pos)) +#define PIO_OSR_P15_Pos _U_(15) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P15_Msk (_U_(0x1) << PIO_OSR_P15_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P15(value) (PIO_OSR_P15_Msk & ((value) << PIO_OSR_P15_Pos)) +#define PIO_OSR_P16_Pos _U_(16) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P16_Msk (_U_(0x1) << PIO_OSR_P16_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P16(value) (PIO_OSR_P16_Msk & ((value) << PIO_OSR_P16_Pos)) +#define PIO_OSR_P17_Pos _U_(17) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P17_Msk (_U_(0x1) << PIO_OSR_P17_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P17(value) (PIO_OSR_P17_Msk & ((value) << PIO_OSR_P17_Pos)) +#define PIO_OSR_P18_Pos _U_(18) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P18_Msk (_U_(0x1) << PIO_OSR_P18_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P18(value) (PIO_OSR_P18_Msk & ((value) << PIO_OSR_P18_Pos)) +#define PIO_OSR_P19_Pos _U_(19) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P19_Msk (_U_(0x1) << PIO_OSR_P19_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P19(value) (PIO_OSR_P19_Msk & ((value) << PIO_OSR_P19_Pos)) +#define PIO_OSR_P20_Pos _U_(20) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P20_Msk (_U_(0x1) << PIO_OSR_P20_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P20(value) (PIO_OSR_P20_Msk & ((value) << PIO_OSR_P20_Pos)) +#define PIO_OSR_P21_Pos _U_(21) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P21_Msk (_U_(0x1) << PIO_OSR_P21_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P21(value) (PIO_OSR_P21_Msk & ((value) << PIO_OSR_P21_Pos)) +#define PIO_OSR_P22_Pos _U_(22) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P22_Msk (_U_(0x1) << PIO_OSR_P22_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P22(value) (PIO_OSR_P22_Msk & ((value) << PIO_OSR_P22_Pos)) +#define PIO_OSR_P23_Pos _U_(23) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P23_Msk (_U_(0x1) << PIO_OSR_P23_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P23(value) (PIO_OSR_P23_Msk & ((value) << PIO_OSR_P23_Pos)) +#define PIO_OSR_P24_Pos _U_(24) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P24_Msk (_U_(0x1) << PIO_OSR_P24_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P24(value) (PIO_OSR_P24_Msk & ((value) << PIO_OSR_P24_Pos)) +#define PIO_OSR_P25_Pos _U_(25) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P25_Msk (_U_(0x1) << PIO_OSR_P25_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P25(value) (PIO_OSR_P25_Msk & ((value) << PIO_OSR_P25_Pos)) +#define PIO_OSR_P26_Pos _U_(26) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P26_Msk (_U_(0x1) << PIO_OSR_P26_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P26(value) (PIO_OSR_P26_Msk & ((value) << PIO_OSR_P26_Pos)) +#define PIO_OSR_P27_Pos _U_(27) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P27_Msk (_U_(0x1) << PIO_OSR_P27_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P27(value) (PIO_OSR_P27_Msk & ((value) << PIO_OSR_P27_Pos)) +#define PIO_OSR_P28_Pos _U_(28) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P28_Msk (_U_(0x1) << PIO_OSR_P28_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P28(value) (PIO_OSR_P28_Msk & ((value) << PIO_OSR_P28_Pos)) +#define PIO_OSR_P29_Pos _U_(29) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P29_Msk (_U_(0x1) << PIO_OSR_P29_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P29(value) (PIO_OSR_P29_Msk & ((value) << PIO_OSR_P29_Pos)) +#define PIO_OSR_P30_Pos _U_(30) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P30_Msk (_U_(0x1) << PIO_OSR_P30_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P30(value) (PIO_OSR_P30_Msk & ((value) << PIO_OSR_P30_Pos)) +#define PIO_OSR_P31_Pos _U_(31) /**< (PIO_OSR) Output Status Position */ +#define PIO_OSR_P31_Msk (_U_(0x1) << PIO_OSR_P31_Pos) /**< (PIO_OSR) Output Status Mask */ +#define PIO_OSR_P31(value) (PIO_OSR_P31_Msk & ((value) << PIO_OSR_P31_Pos)) +#define PIO_OSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OSR) Register Mask */ + +#define PIO_OSR_P_Pos _U_(0) /**< (PIO_OSR Position) Output Status */ +#define PIO_OSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OSR_P_Pos) /**< (PIO_OSR Mask) P */ +#define PIO_OSR_P(value) (PIO_OSR_P_Msk & ((value) << PIO_OSR_P_Pos)) + +/* -------- PIO_IFER : (PIO Offset: 0x20) ( /W 32) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0_Pos _U_(0) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P0_Msk (_U_(0x1) << PIO_IFER_P0_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P0(value) (PIO_IFER_P0_Msk & ((value) << PIO_IFER_P0_Pos)) +#define PIO_IFER_P1_Pos _U_(1) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P1_Msk (_U_(0x1) << PIO_IFER_P1_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P1(value) (PIO_IFER_P1_Msk & ((value) << PIO_IFER_P1_Pos)) +#define PIO_IFER_P2_Pos _U_(2) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P2_Msk (_U_(0x1) << PIO_IFER_P2_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P2(value) (PIO_IFER_P2_Msk & ((value) << PIO_IFER_P2_Pos)) +#define PIO_IFER_P3_Pos _U_(3) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P3_Msk (_U_(0x1) << PIO_IFER_P3_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P3(value) (PIO_IFER_P3_Msk & ((value) << PIO_IFER_P3_Pos)) +#define PIO_IFER_P4_Pos _U_(4) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P4_Msk (_U_(0x1) << PIO_IFER_P4_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P4(value) (PIO_IFER_P4_Msk & ((value) << PIO_IFER_P4_Pos)) +#define PIO_IFER_P5_Pos _U_(5) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P5_Msk (_U_(0x1) << PIO_IFER_P5_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P5(value) (PIO_IFER_P5_Msk & ((value) << PIO_IFER_P5_Pos)) +#define PIO_IFER_P6_Pos _U_(6) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P6_Msk (_U_(0x1) << PIO_IFER_P6_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P6(value) (PIO_IFER_P6_Msk & ((value) << PIO_IFER_P6_Pos)) +#define PIO_IFER_P7_Pos _U_(7) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P7_Msk (_U_(0x1) << PIO_IFER_P7_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P7(value) (PIO_IFER_P7_Msk & ((value) << PIO_IFER_P7_Pos)) +#define PIO_IFER_P8_Pos _U_(8) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P8_Msk (_U_(0x1) << PIO_IFER_P8_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P8(value) (PIO_IFER_P8_Msk & ((value) << PIO_IFER_P8_Pos)) +#define PIO_IFER_P9_Pos _U_(9) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P9_Msk (_U_(0x1) << PIO_IFER_P9_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P9(value) (PIO_IFER_P9_Msk & ((value) << PIO_IFER_P9_Pos)) +#define PIO_IFER_P10_Pos _U_(10) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P10_Msk (_U_(0x1) << PIO_IFER_P10_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P10(value) (PIO_IFER_P10_Msk & ((value) << PIO_IFER_P10_Pos)) +#define PIO_IFER_P11_Pos _U_(11) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P11_Msk (_U_(0x1) << PIO_IFER_P11_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P11(value) (PIO_IFER_P11_Msk & ((value) << PIO_IFER_P11_Pos)) +#define PIO_IFER_P12_Pos _U_(12) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P12_Msk (_U_(0x1) << PIO_IFER_P12_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P12(value) (PIO_IFER_P12_Msk & ((value) << PIO_IFER_P12_Pos)) +#define PIO_IFER_P13_Pos _U_(13) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P13_Msk (_U_(0x1) << PIO_IFER_P13_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P13(value) (PIO_IFER_P13_Msk & ((value) << PIO_IFER_P13_Pos)) +#define PIO_IFER_P14_Pos _U_(14) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P14_Msk (_U_(0x1) << PIO_IFER_P14_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P14(value) (PIO_IFER_P14_Msk & ((value) << PIO_IFER_P14_Pos)) +#define PIO_IFER_P15_Pos _U_(15) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P15_Msk (_U_(0x1) << PIO_IFER_P15_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P15(value) (PIO_IFER_P15_Msk & ((value) << PIO_IFER_P15_Pos)) +#define PIO_IFER_P16_Pos _U_(16) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P16_Msk (_U_(0x1) << PIO_IFER_P16_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P16(value) (PIO_IFER_P16_Msk & ((value) << PIO_IFER_P16_Pos)) +#define PIO_IFER_P17_Pos _U_(17) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P17_Msk (_U_(0x1) << PIO_IFER_P17_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P17(value) (PIO_IFER_P17_Msk & ((value) << PIO_IFER_P17_Pos)) +#define PIO_IFER_P18_Pos _U_(18) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P18_Msk (_U_(0x1) << PIO_IFER_P18_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P18(value) (PIO_IFER_P18_Msk & ((value) << PIO_IFER_P18_Pos)) +#define PIO_IFER_P19_Pos _U_(19) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P19_Msk (_U_(0x1) << PIO_IFER_P19_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P19(value) (PIO_IFER_P19_Msk & ((value) << PIO_IFER_P19_Pos)) +#define PIO_IFER_P20_Pos _U_(20) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P20_Msk (_U_(0x1) << PIO_IFER_P20_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P20(value) (PIO_IFER_P20_Msk & ((value) << PIO_IFER_P20_Pos)) +#define PIO_IFER_P21_Pos _U_(21) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P21_Msk (_U_(0x1) << PIO_IFER_P21_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P21(value) (PIO_IFER_P21_Msk & ((value) << PIO_IFER_P21_Pos)) +#define PIO_IFER_P22_Pos _U_(22) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P22_Msk (_U_(0x1) << PIO_IFER_P22_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P22(value) (PIO_IFER_P22_Msk & ((value) << PIO_IFER_P22_Pos)) +#define PIO_IFER_P23_Pos _U_(23) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P23_Msk (_U_(0x1) << PIO_IFER_P23_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P23(value) (PIO_IFER_P23_Msk & ((value) << PIO_IFER_P23_Pos)) +#define PIO_IFER_P24_Pos _U_(24) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P24_Msk (_U_(0x1) << PIO_IFER_P24_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P24(value) (PIO_IFER_P24_Msk & ((value) << PIO_IFER_P24_Pos)) +#define PIO_IFER_P25_Pos _U_(25) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P25_Msk (_U_(0x1) << PIO_IFER_P25_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P25(value) (PIO_IFER_P25_Msk & ((value) << PIO_IFER_P25_Pos)) +#define PIO_IFER_P26_Pos _U_(26) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P26_Msk (_U_(0x1) << PIO_IFER_P26_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P26(value) (PIO_IFER_P26_Msk & ((value) << PIO_IFER_P26_Pos)) +#define PIO_IFER_P27_Pos _U_(27) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P27_Msk (_U_(0x1) << PIO_IFER_P27_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P27(value) (PIO_IFER_P27_Msk & ((value) << PIO_IFER_P27_Pos)) +#define PIO_IFER_P28_Pos _U_(28) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P28_Msk (_U_(0x1) << PIO_IFER_P28_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P28(value) (PIO_IFER_P28_Msk & ((value) << PIO_IFER_P28_Pos)) +#define PIO_IFER_P29_Pos _U_(29) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P29_Msk (_U_(0x1) << PIO_IFER_P29_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P29(value) (PIO_IFER_P29_Msk & ((value) << PIO_IFER_P29_Pos)) +#define PIO_IFER_P30_Pos _U_(30) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P30_Msk (_U_(0x1) << PIO_IFER_P30_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P30(value) (PIO_IFER_P30_Msk & ((value) << PIO_IFER_P30_Pos)) +#define PIO_IFER_P31_Pos _U_(31) /**< (PIO_IFER) Input Filter Enable Position */ +#define PIO_IFER_P31_Msk (_U_(0x1) << PIO_IFER_P31_Pos) /**< (PIO_IFER) Input Filter Enable Mask */ +#define PIO_IFER_P31(value) (PIO_IFER_P31_Msk & ((value) << PIO_IFER_P31_Pos)) +#define PIO_IFER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFER) Register Mask */ + +#define PIO_IFER_P_Pos _U_(0) /**< (PIO_IFER Position) Input Filter Enable */ +#define PIO_IFER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFER_P_Pos) /**< (PIO_IFER Mask) P */ +#define PIO_IFER_P(value) (PIO_IFER_P_Msk & ((value) << PIO_IFER_P_Pos)) + +/* -------- PIO_IFDR : (PIO Offset: 0x24) ( /W 32) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0_Pos _U_(0) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P0_Msk (_U_(0x1) << PIO_IFDR_P0_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P0(value) (PIO_IFDR_P0_Msk & ((value) << PIO_IFDR_P0_Pos)) +#define PIO_IFDR_P1_Pos _U_(1) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P1_Msk (_U_(0x1) << PIO_IFDR_P1_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P1(value) (PIO_IFDR_P1_Msk & ((value) << PIO_IFDR_P1_Pos)) +#define PIO_IFDR_P2_Pos _U_(2) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P2_Msk (_U_(0x1) << PIO_IFDR_P2_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P2(value) (PIO_IFDR_P2_Msk & ((value) << PIO_IFDR_P2_Pos)) +#define PIO_IFDR_P3_Pos _U_(3) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P3_Msk (_U_(0x1) << PIO_IFDR_P3_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P3(value) (PIO_IFDR_P3_Msk & ((value) << PIO_IFDR_P3_Pos)) +#define PIO_IFDR_P4_Pos _U_(4) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P4_Msk (_U_(0x1) << PIO_IFDR_P4_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P4(value) (PIO_IFDR_P4_Msk & ((value) << PIO_IFDR_P4_Pos)) +#define PIO_IFDR_P5_Pos _U_(5) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P5_Msk (_U_(0x1) << PIO_IFDR_P5_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P5(value) (PIO_IFDR_P5_Msk & ((value) << PIO_IFDR_P5_Pos)) +#define PIO_IFDR_P6_Pos _U_(6) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P6_Msk (_U_(0x1) << PIO_IFDR_P6_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P6(value) (PIO_IFDR_P6_Msk & ((value) << PIO_IFDR_P6_Pos)) +#define PIO_IFDR_P7_Pos _U_(7) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P7_Msk (_U_(0x1) << PIO_IFDR_P7_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P7(value) (PIO_IFDR_P7_Msk & ((value) << PIO_IFDR_P7_Pos)) +#define PIO_IFDR_P8_Pos _U_(8) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P8_Msk (_U_(0x1) << PIO_IFDR_P8_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P8(value) (PIO_IFDR_P8_Msk & ((value) << PIO_IFDR_P8_Pos)) +#define PIO_IFDR_P9_Pos _U_(9) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P9_Msk (_U_(0x1) << PIO_IFDR_P9_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P9(value) (PIO_IFDR_P9_Msk & ((value) << PIO_IFDR_P9_Pos)) +#define PIO_IFDR_P10_Pos _U_(10) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P10_Msk (_U_(0x1) << PIO_IFDR_P10_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P10(value) (PIO_IFDR_P10_Msk & ((value) << PIO_IFDR_P10_Pos)) +#define PIO_IFDR_P11_Pos _U_(11) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P11_Msk (_U_(0x1) << PIO_IFDR_P11_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P11(value) (PIO_IFDR_P11_Msk & ((value) << PIO_IFDR_P11_Pos)) +#define PIO_IFDR_P12_Pos _U_(12) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P12_Msk (_U_(0x1) << PIO_IFDR_P12_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P12(value) (PIO_IFDR_P12_Msk & ((value) << PIO_IFDR_P12_Pos)) +#define PIO_IFDR_P13_Pos _U_(13) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P13_Msk (_U_(0x1) << PIO_IFDR_P13_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P13(value) (PIO_IFDR_P13_Msk & ((value) << PIO_IFDR_P13_Pos)) +#define PIO_IFDR_P14_Pos _U_(14) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P14_Msk (_U_(0x1) << PIO_IFDR_P14_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P14(value) (PIO_IFDR_P14_Msk & ((value) << PIO_IFDR_P14_Pos)) +#define PIO_IFDR_P15_Pos _U_(15) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P15_Msk (_U_(0x1) << PIO_IFDR_P15_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P15(value) (PIO_IFDR_P15_Msk & ((value) << PIO_IFDR_P15_Pos)) +#define PIO_IFDR_P16_Pos _U_(16) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P16_Msk (_U_(0x1) << PIO_IFDR_P16_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P16(value) (PIO_IFDR_P16_Msk & ((value) << PIO_IFDR_P16_Pos)) +#define PIO_IFDR_P17_Pos _U_(17) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P17_Msk (_U_(0x1) << PIO_IFDR_P17_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P17(value) (PIO_IFDR_P17_Msk & ((value) << PIO_IFDR_P17_Pos)) +#define PIO_IFDR_P18_Pos _U_(18) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P18_Msk (_U_(0x1) << PIO_IFDR_P18_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P18(value) (PIO_IFDR_P18_Msk & ((value) << PIO_IFDR_P18_Pos)) +#define PIO_IFDR_P19_Pos _U_(19) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P19_Msk (_U_(0x1) << PIO_IFDR_P19_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P19(value) (PIO_IFDR_P19_Msk & ((value) << PIO_IFDR_P19_Pos)) +#define PIO_IFDR_P20_Pos _U_(20) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P20_Msk (_U_(0x1) << PIO_IFDR_P20_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P20(value) (PIO_IFDR_P20_Msk & ((value) << PIO_IFDR_P20_Pos)) +#define PIO_IFDR_P21_Pos _U_(21) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P21_Msk (_U_(0x1) << PIO_IFDR_P21_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P21(value) (PIO_IFDR_P21_Msk & ((value) << PIO_IFDR_P21_Pos)) +#define PIO_IFDR_P22_Pos _U_(22) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P22_Msk (_U_(0x1) << PIO_IFDR_P22_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P22(value) (PIO_IFDR_P22_Msk & ((value) << PIO_IFDR_P22_Pos)) +#define PIO_IFDR_P23_Pos _U_(23) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P23_Msk (_U_(0x1) << PIO_IFDR_P23_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P23(value) (PIO_IFDR_P23_Msk & ((value) << PIO_IFDR_P23_Pos)) +#define PIO_IFDR_P24_Pos _U_(24) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P24_Msk (_U_(0x1) << PIO_IFDR_P24_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P24(value) (PIO_IFDR_P24_Msk & ((value) << PIO_IFDR_P24_Pos)) +#define PIO_IFDR_P25_Pos _U_(25) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P25_Msk (_U_(0x1) << PIO_IFDR_P25_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P25(value) (PIO_IFDR_P25_Msk & ((value) << PIO_IFDR_P25_Pos)) +#define PIO_IFDR_P26_Pos _U_(26) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P26_Msk (_U_(0x1) << PIO_IFDR_P26_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P26(value) (PIO_IFDR_P26_Msk & ((value) << PIO_IFDR_P26_Pos)) +#define PIO_IFDR_P27_Pos _U_(27) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P27_Msk (_U_(0x1) << PIO_IFDR_P27_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P27(value) (PIO_IFDR_P27_Msk & ((value) << PIO_IFDR_P27_Pos)) +#define PIO_IFDR_P28_Pos _U_(28) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P28_Msk (_U_(0x1) << PIO_IFDR_P28_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P28(value) (PIO_IFDR_P28_Msk & ((value) << PIO_IFDR_P28_Pos)) +#define PIO_IFDR_P29_Pos _U_(29) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P29_Msk (_U_(0x1) << PIO_IFDR_P29_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P29(value) (PIO_IFDR_P29_Msk & ((value) << PIO_IFDR_P29_Pos)) +#define PIO_IFDR_P30_Pos _U_(30) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P30_Msk (_U_(0x1) << PIO_IFDR_P30_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P30(value) (PIO_IFDR_P30_Msk & ((value) << PIO_IFDR_P30_Pos)) +#define PIO_IFDR_P31_Pos _U_(31) /**< (PIO_IFDR) Input Filter Disable Position */ +#define PIO_IFDR_P31_Msk (_U_(0x1) << PIO_IFDR_P31_Pos) /**< (PIO_IFDR) Input Filter Disable Mask */ +#define PIO_IFDR_P31(value) (PIO_IFDR_P31_Msk & ((value) << PIO_IFDR_P31_Pos)) +#define PIO_IFDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFDR) Register Mask */ + +#define PIO_IFDR_P_Pos _U_(0) /**< (PIO_IFDR Position) Input Filter Disable */ +#define PIO_IFDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFDR_P_Pos) /**< (PIO_IFDR Mask) P */ +#define PIO_IFDR_P(value) (PIO_IFDR_P_Msk & ((value) << PIO_IFDR_P_Pos)) + +/* -------- PIO_IFSR : (PIO Offset: 0x28) ( R/ 32) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0_Pos _U_(0) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P0_Msk (_U_(0x1) << PIO_IFSR_P0_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P0(value) (PIO_IFSR_P0_Msk & ((value) << PIO_IFSR_P0_Pos)) +#define PIO_IFSR_P1_Pos _U_(1) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P1_Msk (_U_(0x1) << PIO_IFSR_P1_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P1(value) (PIO_IFSR_P1_Msk & ((value) << PIO_IFSR_P1_Pos)) +#define PIO_IFSR_P2_Pos _U_(2) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P2_Msk (_U_(0x1) << PIO_IFSR_P2_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P2(value) (PIO_IFSR_P2_Msk & ((value) << PIO_IFSR_P2_Pos)) +#define PIO_IFSR_P3_Pos _U_(3) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P3_Msk (_U_(0x1) << PIO_IFSR_P3_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P3(value) (PIO_IFSR_P3_Msk & ((value) << PIO_IFSR_P3_Pos)) +#define PIO_IFSR_P4_Pos _U_(4) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P4_Msk (_U_(0x1) << PIO_IFSR_P4_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P4(value) (PIO_IFSR_P4_Msk & ((value) << PIO_IFSR_P4_Pos)) +#define PIO_IFSR_P5_Pos _U_(5) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P5_Msk (_U_(0x1) << PIO_IFSR_P5_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P5(value) (PIO_IFSR_P5_Msk & ((value) << PIO_IFSR_P5_Pos)) +#define PIO_IFSR_P6_Pos _U_(6) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P6_Msk (_U_(0x1) << PIO_IFSR_P6_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P6(value) (PIO_IFSR_P6_Msk & ((value) << PIO_IFSR_P6_Pos)) +#define PIO_IFSR_P7_Pos _U_(7) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P7_Msk (_U_(0x1) << PIO_IFSR_P7_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P7(value) (PIO_IFSR_P7_Msk & ((value) << PIO_IFSR_P7_Pos)) +#define PIO_IFSR_P8_Pos _U_(8) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P8_Msk (_U_(0x1) << PIO_IFSR_P8_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P8(value) (PIO_IFSR_P8_Msk & ((value) << PIO_IFSR_P8_Pos)) +#define PIO_IFSR_P9_Pos _U_(9) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P9_Msk (_U_(0x1) << PIO_IFSR_P9_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P9(value) (PIO_IFSR_P9_Msk & ((value) << PIO_IFSR_P9_Pos)) +#define PIO_IFSR_P10_Pos _U_(10) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P10_Msk (_U_(0x1) << PIO_IFSR_P10_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P10(value) (PIO_IFSR_P10_Msk & ((value) << PIO_IFSR_P10_Pos)) +#define PIO_IFSR_P11_Pos _U_(11) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P11_Msk (_U_(0x1) << PIO_IFSR_P11_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P11(value) (PIO_IFSR_P11_Msk & ((value) << PIO_IFSR_P11_Pos)) +#define PIO_IFSR_P12_Pos _U_(12) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P12_Msk (_U_(0x1) << PIO_IFSR_P12_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P12(value) (PIO_IFSR_P12_Msk & ((value) << PIO_IFSR_P12_Pos)) +#define PIO_IFSR_P13_Pos _U_(13) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P13_Msk (_U_(0x1) << PIO_IFSR_P13_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P13(value) (PIO_IFSR_P13_Msk & ((value) << PIO_IFSR_P13_Pos)) +#define PIO_IFSR_P14_Pos _U_(14) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P14_Msk (_U_(0x1) << PIO_IFSR_P14_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P14(value) (PIO_IFSR_P14_Msk & ((value) << PIO_IFSR_P14_Pos)) +#define PIO_IFSR_P15_Pos _U_(15) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P15_Msk (_U_(0x1) << PIO_IFSR_P15_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P15(value) (PIO_IFSR_P15_Msk & ((value) << PIO_IFSR_P15_Pos)) +#define PIO_IFSR_P16_Pos _U_(16) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P16_Msk (_U_(0x1) << PIO_IFSR_P16_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P16(value) (PIO_IFSR_P16_Msk & ((value) << PIO_IFSR_P16_Pos)) +#define PIO_IFSR_P17_Pos _U_(17) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P17_Msk (_U_(0x1) << PIO_IFSR_P17_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P17(value) (PIO_IFSR_P17_Msk & ((value) << PIO_IFSR_P17_Pos)) +#define PIO_IFSR_P18_Pos _U_(18) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P18_Msk (_U_(0x1) << PIO_IFSR_P18_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P18(value) (PIO_IFSR_P18_Msk & ((value) << PIO_IFSR_P18_Pos)) +#define PIO_IFSR_P19_Pos _U_(19) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P19_Msk (_U_(0x1) << PIO_IFSR_P19_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P19(value) (PIO_IFSR_P19_Msk & ((value) << PIO_IFSR_P19_Pos)) +#define PIO_IFSR_P20_Pos _U_(20) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P20_Msk (_U_(0x1) << PIO_IFSR_P20_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P20(value) (PIO_IFSR_P20_Msk & ((value) << PIO_IFSR_P20_Pos)) +#define PIO_IFSR_P21_Pos _U_(21) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P21_Msk (_U_(0x1) << PIO_IFSR_P21_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P21(value) (PIO_IFSR_P21_Msk & ((value) << PIO_IFSR_P21_Pos)) +#define PIO_IFSR_P22_Pos _U_(22) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P22_Msk (_U_(0x1) << PIO_IFSR_P22_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P22(value) (PIO_IFSR_P22_Msk & ((value) << PIO_IFSR_P22_Pos)) +#define PIO_IFSR_P23_Pos _U_(23) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P23_Msk (_U_(0x1) << PIO_IFSR_P23_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P23(value) (PIO_IFSR_P23_Msk & ((value) << PIO_IFSR_P23_Pos)) +#define PIO_IFSR_P24_Pos _U_(24) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P24_Msk (_U_(0x1) << PIO_IFSR_P24_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P24(value) (PIO_IFSR_P24_Msk & ((value) << PIO_IFSR_P24_Pos)) +#define PIO_IFSR_P25_Pos _U_(25) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P25_Msk (_U_(0x1) << PIO_IFSR_P25_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P25(value) (PIO_IFSR_P25_Msk & ((value) << PIO_IFSR_P25_Pos)) +#define PIO_IFSR_P26_Pos _U_(26) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P26_Msk (_U_(0x1) << PIO_IFSR_P26_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P26(value) (PIO_IFSR_P26_Msk & ((value) << PIO_IFSR_P26_Pos)) +#define PIO_IFSR_P27_Pos _U_(27) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P27_Msk (_U_(0x1) << PIO_IFSR_P27_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P27(value) (PIO_IFSR_P27_Msk & ((value) << PIO_IFSR_P27_Pos)) +#define PIO_IFSR_P28_Pos _U_(28) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P28_Msk (_U_(0x1) << PIO_IFSR_P28_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P28(value) (PIO_IFSR_P28_Msk & ((value) << PIO_IFSR_P28_Pos)) +#define PIO_IFSR_P29_Pos _U_(29) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P29_Msk (_U_(0x1) << PIO_IFSR_P29_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P29(value) (PIO_IFSR_P29_Msk & ((value) << PIO_IFSR_P29_Pos)) +#define PIO_IFSR_P30_Pos _U_(30) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P30_Msk (_U_(0x1) << PIO_IFSR_P30_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P30(value) (PIO_IFSR_P30_Msk & ((value) << PIO_IFSR_P30_Pos)) +#define PIO_IFSR_P31_Pos _U_(31) /**< (PIO_IFSR) Input Filter Status Position */ +#define PIO_IFSR_P31_Msk (_U_(0x1) << PIO_IFSR_P31_Pos) /**< (PIO_IFSR) Input Filter Status Mask */ +#define PIO_IFSR_P31(value) (PIO_IFSR_P31_Msk & ((value) << PIO_IFSR_P31_Pos)) +#define PIO_IFSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSR) Register Mask */ + +#define PIO_IFSR_P_Pos _U_(0) /**< (PIO_IFSR Position) Input Filter Status */ +#define PIO_IFSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSR_P_Pos) /**< (PIO_IFSR Mask) P */ +#define PIO_IFSR_P(value) (PIO_IFSR_P_Msk & ((value) << PIO_IFSR_P_Pos)) + +/* -------- PIO_SODR : (PIO Offset: 0x30) ( /W 32) Set Output Data Register -------- */ +#define PIO_SODR_P0_Pos _U_(0) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P0_Msk (_U_(0x1) << PIO_SODR_P0_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P0(value) (PIO_SODR_P0_Msk & ((value) << PIO_SODR_P0_Pos)) +#define PIO_SODR_P1_Pos _U_(1) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P1_Msk (_U_(0x1) << PIO_SODR_P1_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P1(value) (PIO_SODR_P1_Msk & ((value) << PIO_SODR_P1_Pos)) +#define PIO_SODR_P2_Pos _U_(2) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P2_Msk (_U_(0x1) << PIO_SODR_P2_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P2(value) (PIO_SODR_P2_Msk & ((value) << PIO_SODR_P2_Pos)) +#define PIO_SODR_P3_Pos _U_(3) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P3_Msk (_U_(0x1) << PIO_SODR_P3_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P3(value) (PIO_SODR_P3_Msk & ((value) << PIO_SODR_P3_Pos)) +#define PIO_SODR_P4_Pos _U_(4) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P4_Msk (_U_(0x1) << PIO_SODR_P4_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P4(value) (PIO_SODR_P4_Msk & ((value) << PIO_SODR_P4_Pos)) +#define PIO_SODR_P5_Pos _U_(5) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P5_Msk (_U_(0x1) << PIO_SODR_P5_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P5(value) (PIO_SODR_P5_Msk & ((value) << PIO_SODR_P5_Pos)) +#define PIO_SODR_P6_Pos _U_(6) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P6_Msk (_U_(0x1) << PIO_SODR_P6_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P6(value) (PIO_SODR_P6_Msk & ((value) << PIO_SODR_P6_Pos)) +#define PIO_SODR_P7_Pos _U_(7) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P7_Msk (_U_(0x1) << PIO_SODR_P7_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P7(value) (PIO_SODR_P7_Msk & ((value) << PIO_SODR_P7_Pos)) +#define PIO_SODR_P8_Pos _U_(8) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P8_Msk (_U_(0x1) << PIO_SODR_P8_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P8(value) (PIO_SODR_P8_Msk & ((value) << PIO_SODR_P8_Pos)) +#define PIO_SODR_P9_Pos _U_(9) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P9_Msk (_U_(0x1) << PIO_SODR_P9_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P9(value) (PIO_SODR_P9_Msk & ((value) << PIO_SODR_P9_Pos)) +#define PIO_SODR_P10_Pos _U_(10) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P10_Msk (_U_(0x1) << PIO_SODR_P10_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P10(value) (PIO_SODR_P10_Msk & ((value) << PIO_SODR_P10_Pos)) +#define PIO_SODR_P11_Pos _U_(11) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P11_Msk (_U_(0x1) << PIO_SODR_P11_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P11(value) (PIO_SODR_P11_Msk & ((value) << PIO_SODR_P11_Pos)) +#define PIO_SODR_P12_Pos _U_(12) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P12_Msk (_U_(0x1) << PIO_SODR_P12_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P12(value) (PIO_SODR_P12_Msk & ((value) << PIO_SODR_P12_Pos)) +#define PIO_SODR_P13_Pos _U_(13) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P13_Msk (_U_(0x1) << PIO_SODR_P13_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P13(value) (PIO_SODR_P13_Msk & ((value) << PIO_SODR_P13_Pos)) +#define PIO_SODR_P14_Pos _U_(14) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P14_Msk (_U_(0x1) << PIO_SODR_P14_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P14(value) (PIO_SODR_P14_Msk & ((value) << PIO_SODR_P14_Pos)) +#define PIO_SODR_P15_Pos _U_(15) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P15_Msk (_U_(0x1) << PIO_SODR_P15_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P15(value) (PIO_SODR_P15_Msk & ((value) << PIO_SODR_P15_Pos)) +#define PIO_SODR_P16_Pos _U_(16) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P16_Msk (_U_(0x1) << PIO_SODR_P16_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P16(value) (PIO_SODR_P16_Msk & ((value) << PIO_SODR_P16_Pos)) +#define PIO_SODR_P17_Pos _U_(17) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P17_Msk (_U_(0x1) << PIO_SODR_P17_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P17(value) (PIO_SODR_P17_Msk & ((value) << PIO_SODR_P17_Pos)) +#define PIO_SODR_P18_Pos _U_(18) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P18_Msk (_U_(0x1) << PIO_SODR_P18_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P18(value) (PIO_SODR_P18_Msk & ((value) << PIO_SODR_P18_Pos)) +#define PIO_SODR_P19_Pos _U_(19) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P19_Msk (_U_(0x1) << PIO_SODR_P19_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P19(value) (PIO_SODR_P19_Msk & ((value) << PIO_SODR_P19_Pos)) +#define PIO_SODR_P20_Pos _U_(20) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P20_Msk (_U_(0x1) << PIO_SODR_P20_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P20(value) (PIO_SODR_P20_Msk & ((value) << PIO_SODR_P20_Pos)) +#define PIO_SODR_P21_Pos _U_(21) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P21_Msk (_U_(0x1) << PIO_SODR_P21_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P21(value) (PIO_SODR_P21_Msk & ((value) << PIO_SODR_P21_Pos)) +#define PIO_SODR_P22_Pos _U_(22) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P22_Msk (_U_(0x1) << PIO_SODR_P22_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P22(value) (PIO_SODR_P22_Msk & ((value) << PIO_SODR_P22_Pos)) +#define PIO_SODR_P23_Pos _U_(23) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P23_Msk (_U_(0x1) << PIO_SODR_P23_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P23(value) (PIO_SODR_P23_Msk & ((value) << PIO_SODR_P23_Pos)) +#define PIO_SODR_P24_Pos _U_(24) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P24_Msk (_U_(0x1) << PIO_SODR_P24_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P24(value) (PIO_SODR_P24_Msk & ((value) << PIO_SODR_P24_Pos)) +#define PIO_SODR_P25_Pos _U_(25) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P25_Msk (_U_(0x1) << PIO_SODR_P25_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P25(value) (PIO_SODR_P25_Msk & ((value) << PIO_SODR_P25_Pos)) +#define PIO_SODR_P26_Pos _U_(26) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P26_Msk (_U_(0x1) << PIO_SODR_P26_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P26(value) (PIO_SODR_P26_Msk & ((value) << PIO_SODR_P26_Pos)) +#define PIO_SODR_P27_Pos _U_(27) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P27_Msk (_U_(0x1) << PIO_SODR_P27_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P27(value) (PIO_SODR_P27_Msk & ((value) << PIO_SODR_P27_Pos)) +#define PIO_SODR_P28_Pos _U_(28) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P28_Msk (_U_(0x1) << PIO_SODR_P28_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P28(value) (PIO_SODR_P28_Msk & ((value) << PIO_SODR_P28_Pos)) +#define PIO_SODR_P29_Pos _U_(29) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P29_Msk (_U_(0x1) << PIO_SODR_P29_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P29(value) (PIO_SODR_P29_Msk & ((value) << PIO_SODR_P29_Pos)) +#define PIO_SODR_P30_Pos _U_(30) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P30_Msk (_U_(0x1) << PIO_SODR_P30_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P30(value) (PIO_SODR_P30_Msk & ((value) << PIO_SODR_P30_Pos)) +#define PIO_SODR_P31_Pos _U_(31) /**< (PIO_SODR) Set Output Data Position */ +#define PIO_SODR_P31_Msk (_U_(0x1) << PIO_SODR_P31_Pos) /**< (PIO_SODR) Set Output Data Mask */ +#define PIO_SODR_P31(value) (PIO_SODR_P31_Msk & ((value) << PIO_SODR_P31_Pos)) +#define PIO_SODR_Msk _U_(0xFFFFFFFF) /**< (PIO_SODR) Register Mask */ + +#define PIO_SODR_P_Pos _U_(0) /**< (PIO_SODR Position) Set Output Data */ +#define PIO_SODR_P_Msk (_U_(0xFFFFFFFF) << PIO_SODR_P_Pos) /**< (PIO_SODR Mask) P */ +#define PIO_SODR_P(value) (PIO_SODR_P_Msk & ((value) << PIO_SODR_P_Pos)) + +/* -------- PIO_CODR : (PIO Offset: 0x34) ( /W 32) Clear Output Data Register -------- */ +#define PIO_CODR_P0_Pos _U_(0) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P0_Msk (_U_(0x1) << PIO_CODR_P0_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P0(value) (PIO_CODR_P0_Msk & ((value) << PIO_CODR_P0_Pos)) +#define PIO_CODR_P1_Pos _U_(1) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P1_Msk (_U_(0x1) << PIO_CODR_P1_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P1(value) (PIO_CODR_P1_Msk & ((value) << PIO_CODR_P1_Pos)) +#define PIO_CODR_P2_Pos _U_(2) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P2_Msk (_U_(0x1) << PIO_CODR_P2_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P2(value) (PIO_CODR_P2_Msk & ((value) << PIO_CODR_P2_Pos)) +#define PIO_CODR_P3_Pos _U_(3) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P3_Msk (_U_(0x1) << PIO_CODR_P3_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P3(value) (PIO_CODR_P3_Msk & ((value) << PIO_CODR_P3_Pos)) +#define PIO_CODR_P4_Pos _U_(4) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P4_Msk (_U_(0x1) << PIO_CODR_P4_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P4(value) (PIO_CODR_P4_Msk & ((value) << PIO_CODR_P4_Pos)) +#define PIO_CODR_P5_Pos _U_(5) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P5_Msk (_U_(0x1) << PIO_CODR_P5_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P5(value) (PIO_CODR_P5_Msk & ((value) << PIO_CODR_P5_Pos)) +#define PIO_CODR_P6_Pos _U_(6) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P6_Msk (_U_(0x1) << PIO_CODR_P6_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P6(value) (PIO_CODR_P6_Msk & ((value) << PIO_CODR_P6_Pos)) +#define PIO_CODR_P7_Pos _U_(7) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P7_Msk (_U_(0x1) << PIO_CODR_P7_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P7(value) (PIO_CODR_P7_Msk & ((value) << PIO_CODR_P7_Pos)) +#define PIO_CODR_P8_Pos _U_(8) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P8_Msk (_U_(0x1) << PIO_CODR_P8_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P8(value) (PIO_CODR_P8_Msk & ((value) << PIO_CODR_P8_Pos)) +#define PIO_CODR_P9_Pos _U_(9) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P9_Msk (_U_(0x1) << PIO_CODR_P9_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P9(value) (PIO_CODR_P9_Msk & ((value) << PIO_CODR_P9_Pos)) +#define PIO_CODR_P10_Pos _U_(10) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P10_Msk (_U_(0x1) << PIO_CODR_P10_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P10(value) (PIO_CODR_P10_Msk & ((value) << PIO_CODR_P10_Pos)) +#define PIO_CODR_P11_Pos _U_(11) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P11_Msk (_U_(0x1) << PIO_CODR_P11_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P11(value) (PIO_CODR_P11_Msk & ((value) << PIO_CODR_P11_Pos)) +#define PIO_CODR_P12_Pos _U_(12) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P12_Msk (_U_(0x1) << PIO_CODR_P12_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P12(value) (PIO_CODR_P12_Msk & ((value) << PIO_CODR_P12_Pos)) +#define PIO_CODR_P13_Pos _U_(13) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P13_Msk (_U_(0x1) << PIO_CODR_P13_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P13(value) (PIO_CODR_P13_Msk & ((value) << PIO_CODR_P13_Pos)) +#define PIO_CODR_P14_Pos _U_(14) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P14_Msk (_U_(0x1) << PIO_CODR_P14_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P14(value) (PIO_CODR_P14_Msk & ((value) << PIO_CODR_P14_Pos)) +#define PIO_CODR_P15_Pos _U_(15) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P15_Msk (_U_(0x1) << PIO_CODR_P15_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P15(value) (PIO_CODR_P15_Msk & ((value) << PIO_CODR_P15_Pos)) +#define PIO_CODR_P16_Pos _U_(16) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P16_Msk (_U_(0x1) << PIO_CODR_P16_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P16(value) (PIO_CODR_P16_Msk & ((value) << PIO_CODR_P16_Pos)) +#define PIO_CODR_P17_Pos _U_(17) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P17_Msk (_U_(0x1) << PIO_CODR_P17_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P17(value) (PIO_CODR_P17_Msk & ((value) << PIO_CODR_P17_Pos)) +#define PIO_CODR_P18_Pos _U_(18) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P18_Msk (_U_(0x1) << PIO_CODR_P18_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P18(value) (PIO_CODR_P18_Msk & ((value) << PIO_CODR_P18_Pos)) +#define PIO_CODR_P19_Pos _U_(19) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P19_Msk (_U_(0x1) << PIO_CODR_P19_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P19(value) (PIO_CODR_P19_Msk & ((value) << PIO_CODR_P19_Pos)) +#define PIO_CODR_P20_Pos _U_(20) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P20_Msk (_U_(0x1) << PIO_CODR_P20_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P20(value) (PIO_CODR_P20_Msk & ((value) << PIO_CODR_P20_Pos)) +#define PIO_CODR_P21_Pos _U_(21) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P21_Msk (_U_(0x1) << PIO_CODR_P21_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P21(value) (PIO_CODR_P21_Msk & ((value) << PIO_CODR_P21_Pos)) +#define PIO_CODR_P22_Pos _U_(22) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P22_Msk (_U_(0x1) << PIO_CODR_P22_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P22(value) (PIO_CODR_P22_Msk & ((value) << PIO_CODR_P22_Pos)) +#define PIO_CODR_P23_Pos _U_(23) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P23_Msk (_U_(0x1) << PIO_CODR_P23_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P23(value) (PIO_CODR_P23_Msk & ((value) << PIO_CODR_P23_Pos)) +#define PIO_CODR_P24_Pos _U_(24) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P24_Msk (_U_(0x1) << PIO_CODR_P24_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P24(value) (PIO_CODR_P24_Msk & ((value) << PIO_CODR_P24_Pos)) +#define PIO_CODR_P25_Pos _U_(25) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P25_Msk (_U_(0x1) << PIO_CODR_P25_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P25(value) (PIO_CODR_P25_Msk & ((value) << PIO_CODR_P25_Pos)) +#define PIO_CODR_P26_Pos _U_(26) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P26_Msk (_U_(0x1) << PIO_CODR_P26_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P26(value) (PIO_CODR_P26_Msk & ((value) << PIO_CODR_P26_Pos)) +#define PIO_CODR_P27_Pos _U_(27) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P27_Msk (_U_(0x1) << PIO_CODR_P27_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P27(value) (PIO_CODR_P27_Msk & ((value) << PIO_CODR_P27_Pos)) +#define PIO_CODR_P28_Pos _U_(28) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P28_Msk (_U_(0x1) << PIO_CODR_P28_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P28(value) (PIO_CODR_P28_Msk & ((value) << PIO_CODR_P28_Pos)) +#define PIO_CODR_P29_Pos _U_(29) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P29_Msk (_U_(0x1) << PIO_CODR_P29_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P29(value) (PIO_CODR_P29_Msk & ((value) << PIO_CODR_P29_Pos)) +#define PIO_CODR_P30_Pos _U_(30) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P30_Msk (_U_(0x1) << PIO_CODR_P30_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P30(value) (PIO_CODR_P30_Msk & ((value) << PIO_CODR_P30_Pos)) +#define PIO_CODR_P31_Pos _U_(31) /**< (PIO_CODR) Clear Output Data Position */ +#define PIO_CODR_P31_Msk (_U_(0x1) << PIO_CODR_P31_Pos) /**< (PIO_CODR) Clear Output Data Mask */ +#define PIO_CODR_P31(value) (PIO_CODR_P31_Msk & ((value) << PIO_CODR_P31_Pos)) +#define PIO_CODR_Msk _U_(0xFFFFFFFF) /**< (PIO_CODR) Register Mask */ + +#define PIO_CODR_P_Pos _U_(0) /**< (PIO_CODR Position) Clear Output Data */ +#define PIO_CODR_P_Msk (_U_(0xFFFFFFFF) << PIO_CODR_P_Pos) /**< (PIO_CODR Mask) P */ +#define PIO_CODR_P(value) (PIO_CODR_P_Msk & ((value) << PIO_CODR_P_Pos)) + +/* -------- PIO_ODSR : (PIO Offset: 0x38) (R/W 32) Output Data Status Register -------- */ +#define PIO_ODSR_P0_Pos _U_(0) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P0_Msk (_U_(0x1) << PIO_ODSR_P0_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P0(value) (PIO_ODSR_P0_Msk & ((value) << PIO_ODSR_P0_Pos)) +#define PIO_ODSR_P1_Pos _U_(1) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P1_Msk (_U_(0x1) << PIO_ODSR_P1_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P1(value) (PIO_ODSR_P1_Msk & ((value) << PIO_ODSR_P1_Pos)) +#define PIO_ODSR_P2_Pos _U_(2) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P2_Msk (_U_(0x1) << PIO_ODSR_P2_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P2(value) (PIO_ODSR_P2_Msk & ((value) << PIO_ODSR_P2_Pos)) +#define PIO_ODSR_P3_Pos _U_(3) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P3_Msk (_U_(0x1) << PIO_ODSR_P3_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P3(value) (PIO_ODSR_P3_Msk & ((value) << PIO_ODSR_P3_Pos)) +#define PIO_ODSR_P4_Pos _U_(4) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P4_Msk (_U_(0x1) << PIO_ODSR_P4_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P4(value) (PIO_ODSR_P4_Msk & ((value) << PIO_ODSR_P4_Pos)) +#define PIO_ODSR_P5_Pos _U_(5) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P5_Msk (_U_(0x1) << PIO_ODSR_P5_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P5(value) (PIO_ODSR_P5_Msk & ((value) << PIO_ODSR_P5_Pos)) +#define PIO_ODSR_P6_Pos _U_(6) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P6_Msk (_U_(0x1) << PIO_ODSR_P6_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P6(value) (PIO_ODSR_P6_Msk & ((value) << PIO_ODSR_P6_Pos)) +#define PIO_ODSR_P7_Pos _U_(7) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P7_Msk (_U_(0x1) << PIO_ODSR_P7_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P7(value) (PIO_ODSR_P7_Msk & ((value) << PIO_ODSR_P7_Pos)) +#define PIO_ODSR_P8_Pos _U_(8) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P8_Msk (_U_(0x1) << PIO_ODSR_P8_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P8(value) (PIO_ODSR_P8_Msk & ((value) << PIO_ODSR_P8_Pos)) +#define PIO_ODSR_P9_Pos _U_(9) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P9_Msk (_U_(0x1) << PIO_ODSR_P9_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P9(value) (PIO_ODSR_P9_Msk & ((value) << PIO_ODSR_P9_Pos)) +#define PIO_ODSR_P10_Pos _U_(10) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P10_Msk (_U_(0x1) << PIO_ODSR_P10_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P10(value) (PIO_ODSR_P10_Msk & ((value) << PIO_ODSR_P10_Pos)) +#define PIO_ODSR_P11_Pos _U_(11) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P11_Msk (_U_(0x1) << PIO_ODSR_P11_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P11(value) (PIO_ODSR_P11_Msk & ((value) << PIO_ODSR_P11_Pos)) +#define PIO_ODSR_P12_Pos _U_(12) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P12_Msk (_U_(0x1) << PIO_ODSR_P12_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P12(value) (PIO_ODSR_P12_Msk & ((value) << PIO_ODSR_P12_Pos)) +#define PIO_ODSR_P13_Pos _U_(13) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P13_Msk (_U_(0x1) << PIO_ODSR_P13_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P13(value) (PIO_ODSR_P13_Msk & ((value) << PIO_ODSR_P13_Pos)) +#define PIO_ODSR_P14_Pos _U_(14) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P14_Msk (_U_(0x1) << PIO_ODSR_P14_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P14(value) (PIO_ODSR_P14_Msk & ((value) << PIO_ODSR_P14_Pos)) +#define PIO_ODSR_P15_Pos _U_(15) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P15_Msk (_U_(0x1) << PIO_ODSR_P15_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P15(value) (PIO_ODSR_P15_Msk & ((value) << PIO_ODSR_P15_Pos)) +#define PIO_ODSR_P16_Pos _U_(16) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P16_Msk (_U_(0x1) << PIO_ODSR_P16_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P16(value) (PIO_ODSR_P16_Msk & ((value) << PIO_ODSR_P16_Pos)) +#define PIO_ODSR_P17_Pos _U_(17) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P17_Msk (_U_(0x1) << PIO_ODSR_P17_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P17(value) (PIO_ODSR_P17_Msk & ((value) << PIO_ODSR_P17_Pos)) +#define PIO_ODSR_P18_Pos _U_(18) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P18_Msk (_U_(0x1) << PIO_ODSR_P18_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P18(value) (PIO_ODSR_P18_Msk & ((value) << PIO_ODSR_P18_Pos)) +#define PIO_ODSR_P19_Pos _U_(19) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P19_Msk (_U_(0x1) << PIO_ODSR_P19_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P19(value) (PIO_ODSR_P19_Msk & ((value) << PIO_ODSR_P19_Pos)) +#define PIO_ODSR_P20_Pos _U_(20) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P20_Msk (_U_(0x1) << PIO_ODSR_P20_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P20(value) (PIO_ODSR_P20_Msk & ((value) << PIO_ODSR_P20_Pos)) +#define PIO_ODSR_P21_Pos _U_(21) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P21_Msk (_U_(0x1) << PIO_ODSR_P21_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P21(value) (PIO_ODSR_P21_Msk & ((value) << PIO_ODSR_P21_Pos)) +#define PIO_ODSR_P22_Pos _U_(22) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P22_Msk (_U_(0x1) << PIO_ODSR_P22_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P22(value) (PIO_ODSR_P22_Msk & ((value) << PIO_ODSR_P22_Pos)) +#define PIO_ODSR_P23_Pos _U_(23) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P23_Msk (_U_(0x1) << PIO_ODSR_P23_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P23(value) (PIO_ODSR_P23_Msk & ((value) << PIO_ODSR_P23_Pos)) +#define PIO_ODSR_P24_Pos _U_(24) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P24_Msk (_U_(0x1) << PIO_ODSR_P24_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P24(value) (PIO_ODSR_P24_Msk & ((value) << PIO_ODSR_P24_Pos)) +#define PIO_ODSR_P25_Pos _U_(25) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P25_Msk (_U_(0x1) << PIO_ODSR_P25_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P25(value) (PIO_ODSR_P25_Msk & ((value) << PIO_ODSR_P25_Pos)) +#define PIO_ODSR_P26_Pos _U_(26) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P26_Msk (_U_(0x1) << PIO_ODSR_P26_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P26(value) (PIO_ODSR_P26_Msk & ((value) << PIO_ODSR_P26_Pos)) +#define PIO_ODSR_P27_Pos _U_(27) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P27_Msk (_U_(0x1) << PIO_ODSR_P27_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P27(value) (PIO_ODSR_P27_Msk & ((value) << PIO_ODSR_P27_Pos)) +#define PIO_ODSR_P28_Pos _U_(28) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P28_Msk (_U_(0x1) << PIO_ODSR_P28_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P28(value) (PIO_ODSR_P28_Msk & ((value) << PIO_ODSR_P28_Pos)) +#define PIO_ODSR_P29_Pos _U_(29) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P29_Msk (_U_(0x1) << PIO_ODSR_P29_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P29(value) (PIO_ODSR_P29_Msk & ((value) << PIO_ODSR_P29_Pos)) +#define PIO_ODSR_P30_Pos _U_(30) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P30_Msk (_U_(0x1) << PIO_ODSR_P30_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P30(value) (PIO_ODSR_P30_Msk & ((value) << PIO_ODSR_P30_Pos)) +#define PIO_ODSR_P31_Pos _U_(31) /**< (PIO_ODSR) Output Data Status Position */ +#define PIO_ODSR_P31_Msk (_U_(0x1) << PIO_ODSR_P31_Pos) /**< (PIO_ODSR) Output Data Status Mask */ +#define PIO_ODSR_P31(value) (PIO_ODSR_P31_Msk & ((value) << PIO_ODSR_P31_Pos)) +#define PIO_ODSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ODSR) Register Mask */ + +#define PIO_ODSR_P_Pos _U_(0) /**< (PIO_ODSR Position) Output Data Status */ +#define PIO_ODSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ODSR_P_Pos) /**< (PIO_ODSR Mask) P */ +#define PIO_ODSR_P(value) (PIO_ODSR_P_Msk & ((value) << PIO_ODSR_P_Pos)) + +/* -------- PIO_PDSR : (PIO Offset: 0x3C) ( R/ 32) Pin Data Status Register -------- */ +#define PIO_PDSR_P0_Pos _U_(0) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P0_Msk (_U_(0x1) << PIO_PDSR_P0_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P0(value) (PIO_PDSR_P0_Msk & ((value) << PIO_PDSR_P0_Pos)) +#define PIO_PDSR_P1_Pos _U_(1) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P1_Msk (_U_(0x1) << PIO_PDSR_P1_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P1(value) (PIO_PDSR_P1_Msk & ((value) << PIO_PDSR_P1_Pos)) +#define PIO_PDSR_P2_Pos _U_(2) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P2_Msk (_U_(0x1) << PIO_PDSR_P2_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P2(value) (PIO_PDSR_P2_Msk & ((value) << PIO_PDSR_P2_Pos)) +#define PIO_PDSR_P3_Pos _U_(3) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P3_Msk (_U_(0x1) << PIO_PDSR_P3_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P3(value) (PIO_PDSR_P3_Msk & ((value) << PIO_PDSR_P3_Pos)) +#define PIO_PDSR_P4_Pos _U_(4) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P4_Msk (_U_(0x1) << PIO_PDSR_P4_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P4(value) (PIO_PDSR_P4_Msk & ((value) << PIO_PDSR_P4_Pos)) +#define PIO_PDSR_P5_Pos _U_(5) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P5_Msk (_U_(0x1) << PIO_PDSR_P5_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P5(value) (PIO_PDSR_P5_Msk & ((value) << PIO_PDSR_P5_Pos)) +#define PIO_PDSR_P6_Pos _U_(6) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P6_Msk (_U_(0x1) << PIO_PDSR_P6_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P6(value) (PIO_PDSR_P6_Msk & ((value) << PIO_PDSR_P6_Pos)) +#define PIO_PDSR_P7_Pos _U_(7) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P7_Msk (_U_(0x1) << PIO_PDSR_P7_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P7(value) (PIO_PDSR_P7_Msk & ((value) << PIO_PDSR_P7_Pos)) +#define PIO_PDSR_P8_Pos _U_(8) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P8_Msk (_U_(0x1) << PIO_PDSR_P8_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P8(value) (PIO_PDSR_P8_Msk & ((value) << PIO_PDSR_P8_Pos)) +#define PIO_PDSR_P9_Pos _U_(9) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P9_Msk (_U_(0x1) << PIO_PDSR_P9_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P9(value) (PIO_PDSR_P9_Msk & ((value) << PIO_PDSR_P9_Pos)) +#define PIO_PDSR_P10_Pos _U_(10) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P10_Msk (_U_(0x1) << PIO_PDSR_P10_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P10(value) (PIO_PDSR_P10_Msk & ((value) << PIO_PDSR_P10_Pos)) +#define PIO_PDSR_P11_Pos _U_(11) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P11_Msk (_U_(0x1) << PIO_PDSR_P11_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P11(value) (PIO_PDSR_P11_Msk & ((value) << PIO_PDSR_P11_Pos)) +#define PIO_PDSR_P12_Pos _U_(12) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P12_Msk (_U_(0x1) << PIO_PDSR_P12_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P12(value) (PIO_PDSR_P12_Msk & ((value) << PIO_PDSR_P12_Pos)) +#define PIO_PDSR_P13_Pos _U_(13) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P13_Msk (_U_(0x1) << PIO_PDSR_P13_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P13(value) (PIO_PDSR_P13_Msk & ((value) << PIO_PDSR_P13_Pos)) +#define PIO_PDSR_P14_Pos _U_(14) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P14_Msk (_U_(0x1) << PIO_PDSR_P14_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P14(value) (PIO_PDSR_P14_Msk & ((value) << PIO_PDSR_P14_Pos)) +#define PIO_PDSR_P15_Pos _U_(15) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P15_Msk (_U_(0x1) << PIO_PDSR_P15_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P15(value) (PIO_PDSR_P15_Msk & ((value) << PIO_PDSR_P15_Pos)) +#define PIO_PDSR_P16_Pos _U_(16) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P16_Msk (_U_(0x1) << PIO_PDSR_P16_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P16(value) (PIO_PDSR_P16_Msk & ((value) << PIO_PDSR_P16_Pos)) +#define PIO_PDSR_P17_Pos _U_(17) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P17_Msk (_U_(0x1) << PIO_PDSR_P17_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P17(value) (PIO_PDSR_P17_Msk & ((value) << PIO_PDSR_P17_Pos)) +#define PIO_PDSR_P18_Pos _U_(18) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P18_Msk (_U_(0x1) << PIO_PDSR_P18_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P18(value) (PIO_PDSR_P18_Msk & ((value) << PIO_PDSR_P18_Pos)) +#define PIO_PDSR_P19_Pos _U_(19) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P19_Msk (_U_(0x1) << PIO_PDSR_P19_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P19(value) (PIO_PDSR_P19_Msk & ((value) << PIO_PDSR_P19_Pos)) +#define PIO_PDSR_P20_Pos _U_(20) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P20_Msk (_U_(0x1) << PIO_PDSR_P20_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P20(value) (PIO_PDSR_P20_Msk & ((value) << PIO_PDSR_P20_Pos)) +#define PIO_PDSR_P21_Pos _U_(21) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P21_Msk (_U_(0x1) << PIO_PDSR_P21_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P21(value) (PIO_PDSR_P21_Msk & ((value) << PIO_PDSR_P21_Pos)) +#define PIO_PDSR_P22_Pos _U_(22) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P22_Msk (_U_(0x1) << PIO_PDSR_P22_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P22(value) (PIO_PDSR_P22_Msk & ((value) << PIO_PDSR_P22_Pos)) +#define PIO_PDSR_P23_Pos _U_(23) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P23_Msk (_U_(0x1) << PIO_PDSR_P23_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P23(value) (PIO_PDSR_P23_Msk & ((value) << PIO_PDSR_P23_Pos)) +#define PIO_PDSR_P24_Pos _U_(24) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P24_Msk (_U_(0x1) << PIO_PDSR_P24_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P24(value) (PIO_PDSR_P24_Msk & ((value) << PIO_PDSR_P24_Pos)) +#define PIO_PDSR_P25_Pos _U_(25) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P25_Msk (_U_(0x1) << PIO_PDSR_P25_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P25(value) (PIO_PDSR_P25_Msk & ((value) << PIO_PDSR_P25_Pos)) +#define PIO_PDSR_P26_Pos _U_(26) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P26_Msk (_U_(0x1) << PIO_PDSR_P26_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P26(value) (PIO_PDSR_P26_Msk & ((value) << PIO_PDSR_P26_Pos)) +#define PIO_PDSR_P27_Pos _U_(27) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P27_Msk (_U_(0x1) << PIO_PDSR_P27_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P27(value) (PIO_PDSR_P27_Msk & ((value) << PIO_PDSR_P27_Pos)) +#define PIO_PDSR_P28_Pos _U_(28) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P28_Msk (_U_(0x1) << PIO_PDSR_P28_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P28(value) (PIO_PDSR_P28_Msk & ((value) << PIO_PDSR_P28_Pos)) +#define PIO_PDSR_P29_Pos _U_(29) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P29_Msk (_U_(0x1) << PIO_PDSR_P29_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P29(value) (PIO_PDSR_P29_Msk & ((value) << PIO_PDSR_P29_Pos)) +#define PIO_PDSR_P30_Pos _U_(30) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P30_Msk (_U_(0x1) << PIO_PDSR_P30_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P30(value) (PIO_PDSR_P30_Msk & ((value) << PIO_PDSR_P30_Pos)) +#define PIO_PDSR_P31_Pos _U_(31) /**< (PIO_PDSR) Output Data Status Position */ +#define PIO_PDSR_P31_Msk (_U_(0x1) << PIO_PDSR_P31_Pos) /**< (PIO_PDSR) Output Data Status Mask */ +#define PIO_PDSR_P31(value) (PIO_PDSR_P31_Msk & ((value) << PIO_PDSR_P31_Pos)) +#define PIO_PDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PDSR) Register Mask */ + +#define PIO_PDSR_P_Pos _U_(0) /**< (PIO_PDSR Position) Output Data Status */ +#define PIO_PDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PDSR_P_Pos) /**< (PIO_PDSR Mask) P */ +#define PIO_PDSR_P(value) (PIO_PDSR_P_Msk & ((value) << PIO_PDSR_P_Pos)) + +/* -------- PIO_IER : (PIO Offset: 0x40) ( /W 32) Interrupt Enable Register -------- */ +#define PIO_IER_P0_Pos _U_(0) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P0_Msk (_U_(0x1) << PIO_IER_P0_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P0(value) (PIO_IER_P0_Msk & ((value) << PIO_IER_P0_Pos)) +#define PIO_IER_P1_Pos _U_(1) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P1_Msk (_U_(0x1) << PIO_IER_P1_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P1(value) (PIO_IER_P1_Msk & ((value) << PIO_IER_P1_Pos)) +#define PIO_IER_P2_Pos _U_(2) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P2_Msk (_U_(0x1) << PIO_IER_P2_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P2(value) (PIO_IER_P2_Msk & ((value) << PIO_IER_P2_Pos)) +#define PIO_IER_P3_Pos _U_(3) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P3_Msk (_U_(0x1) << PIO_IER_P3_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P3(value) (PIO_IER_P3_Msk & ((value) << PIO_IER_P3_Pos)) +#define PIO_IER_P4_Pos _U_(4) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P4_Msk (_U_(0x1) << PIO_IER_P4_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P4(value) (PIO_IER_P4_Msk & ((value) << PIO_IER_P4_Pos)) +#define PIO_IER_P5_Pos _U_(5) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P5_Msk (_U_(0x1) << PIO_IER_P5_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P5(value) (PIO_IER_P5_Msk & ((value) << PIO_IER_P5_Pos)) +#define PIO_IER_P6_Pos _U_(6) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P6_Msk (_U_(0x1) << PIO_IER_P6_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P6(value) (PIO_IER_P6_Msk & ((value) << PIO_IER_P6_Pos)) +#define PIO_IER_P7_Pos _U_(7) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P7_Msk (_U_(0x1) << PIO_IER_P7_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P7(value) (PIO_IER_P7_Msk & ((value) << PIO_IER_P7_Pos)) +#define PIO_IER_P8_Pos _U_(8) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P8_Msk (_U_(0x1) << PIO_IER_P8_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P8(value) (PIO_IER_P8_Msk & ((value) << PIO_IER_P8_Pos)) +#define PIO_IER_P9_Pos _U_(9) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P9_Msk (_U_(0x1) << PIO_IER_P9_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P9(value) (PIO_IER_P9_Msk & ((value) << PIO_IER_P9_Pos)) +#define PIO_IER_P10_Pos _U_(10) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P10_Msk (_U_(0x1) << PIO_IER_P10_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P10(value) (PIO_IER_P10_Msk & ((value) << PIO_IER_P10_Pos)) +#define PIO_IER_P11_Pos _U_(11) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P11_Msk (_U_(0x1) << PIO_IER_P11_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P11(value) (PIO_IER_P11_Msk & ((value) << PIO_IER_P11_Pos)) +#define PIO_IER_P12_Pos _U_(12) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P12_Msk (_U_(0x1) << PIO_IER_P12_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P12(value) (PIO_IER_P12_Msk & ((value) << PIO_IER_P12_Pos)) +#define PIO_IER_P13_Pos _U_(13) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P13_Msk (_U_(0x1) << PIO_IER_P13_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P13(value) (PIO_IER_P13_Msk & ((value) << PIO_IER_P13_Pos)) +#define PIO_IER_P14_Pos _U_(14) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P14_Msk (_U_(0x1) << PIO_IER_P14_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P14(value) (PIO_IER_P14_Msk & ((value) << PIO_IER_P14_Pos)) +#define PIO_IER_P15_Pos _U_(15) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P15_Msk (_U_(0x1) << PIO_IER_P15_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P15(value) (PIO_IER_P15_Msk & ((value) << PIO_IER_P15_Pos)) +#define PIO_IER_P16_Pos _U_(16) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P16_Msk (_U_(0x1) << PIO_IER_P16_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P16(value) (PIO_IER_P16_Msk & ((value) << PIO_IER_P16_Pos)) +#define PIO_IER_P17_Pos _U_(17) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P17_Msk (_U_(0x1) << PIO_IER_P17_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P17(value) (PIO_IER_P17_Msk & ((value) << PIO_IER_P17_Pos)) +#define PIO_IER_P18_Pos _U_(18) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P18_Msk (_U_(0x1) << PIO_IER_P18_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P18(value) (PIO_IER_P18_Msk & ((value) << PIO_IER_P18_Pos)) +#define PIO_IER_P19_Pos _U_(19) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P19_Msk (_U_(0x1) << PIO_IER_P19_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P19(value) (PIO_IER_P19_Msk & ((value) << PIO_IER_P19_Pos)) +#define PIO_IER_P20_Pos _U_(20) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P20_Msk (_U_(0x1) << PIO_IER_P20_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P20(value) (PIO_IER_P20_Msk & ((value) << PIO_IER_P20_Pos)) +#define PIO_IER_P21_Pos _U_(21) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P21_Msk (_U_(0x1) << PIO_IER_P21_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P21(value) (PIO_IER_P21_Msk & ((value) << PIO_IER_P21_Pos)) +#define PIO_IER_P22_Pos _U_(22) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P22_Msk (_U_(0x1) << PIO_IER_P22_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P22(value) (PIO_IER_P22_Msk & ((value) << PIO_IER_P22_Pos)) +#define PIO_IER_P23_Pos _U_(23) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P23_Msk (_U_(0x1) << PIO_IER_P23_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P23(value) (PIO_IER_P23_Msk & ((value) << PIO_IER_P23_Pos)) +#define PIO_IER_P24_Pos _U_(24) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P24_Msk (_U_(0x1) << PIO_IER_P24_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P24(value) (PIO_IER_P24_Msk & ((value) << PIO_IER_P24_Pos)) +#define PIO_IER_P25_Pos _U_(25) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P25_Msk (_U_(0x1) << PIO_IER_P25_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P25(value) (PIO_IER_P25_Msk & ((value) << PIO_IER_P25_Pos)) +#define PIO_IER_P26_Pos _U_(26) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P26_Msk (_U_(0x1) << PIO_IER_P26_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P26(value) (PIO_IER_P26_Msk & ((value) << PIO_IER_P26_Pos)) +#define PIO_IER_P27_Pos _U_(27) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P27_Msk (_U_(0x1) << PIO_IER_P27_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P27(value) (PIO_IER_P27_Msk & ((value) << PIO_IER_P27_Pos)) +#define PIO_IER_P28_Pos _U_(28) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P28_Msk (_U_(0x1) << PIO_IER_P28_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P28(value) (PIO_IER_P28_Msk & ((value) << PIO_IER_P28_Pos)) +#define PIO_IER_P29_Pos _U_(29) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P29_Msk (_U_(0x1) << PIO_IER_P29_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P29(value) (PIO_IER_P29_Msk & ((value) << PIO_IER_P29_Pos)) +#define PIO_IER_P30_Pos _U_(30) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P30_Msk (_U_(0x1) << PIO_IER_P30_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P30(value) (PIO_IER_P30_Msk & ((value) << PIO_IER_P30_Pos)) +#define PIO_IER_P31_Pos _U_(31) /**< (PIO_IER) Input Change Interrupt Enable Position */ +#define PIO_IER_P31_Msk (_U_(0x1) << PIO_IER_P31_Pos) /**< (PIO_IER) Input Change Interrupt Enable Mask */ +#define PIO_IER_P31(value) (PIO_IER_P31_Msk & ((value) << PIO_IER_P31_Pos)) +#define PIO_IER_Msk _U_(0xFFFFFFFF) /**< (PIO_IER) Register Mask */ + +#define PIO_IER_P_Pos _U_(0) /**< (PIO_IER Position) Input Change Interrupt Enable */ +#define PIO_IER_P_Msk (_U_(0xFFFFFFFF) << PIO_IER_P_Pos) /**< (PIO_IER Mask) P */ +#define PIO_IER_P(value) (PIO_IER_P_Msk & ((value) << PIO_IER_P_Pos)) + +/* -------- PIO_IDR : (PIO Offset: 0x44) ( /W 32) Interrupt Disable Register -------- */ +#define PIO_IDR_P0_Pos _U_(0) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P0_Msk (_U_(0x1) << PIO_IDR_P0_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P0(value) (PIO_IDR_P0_Msk & ((value) << PIO_IDR_P0_Pos)) +#define PIO_IDR_P1_Pos _U_(1) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P1_Msk (_U_(0x1) << PIO_IDR_P1_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P1(value) (PIO_IDR_P1_Msk & ((value) << PIO_IDR_P1_Pos)) +#define PIO_IDR_P2_Pos _U_(2) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P2_Msk (_U_(0x1) << PIO_IDR_P2_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P2(value) (PIO_IDR_P2_Msk & ((value) << PIO_IDR_P2_Pos)) +#define PIO_IDR_P3_Pos _U_(3) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P3_Msk (_U_(0x1) << PIO_IDR_P3_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P3(value) (PIO_IDR_P3_Msk & ((value) << PIO_IDR_P3_Pos)) +#define PIO_IDR_P4_Pos _U_(4) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P4_Msk (_U_(0x1) << PIO_IDR_P4_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P4(value) (PIO_IDR_P4_Msk & ((value) << PIO_IDR_P4_Pos)) +#define PIO_IDR_P5_Pos _U_(5) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P5_Msk (_U_(0x1) << PIO_IDR_P5_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P5(value) (PIO_IDR_P5_Msk & ((value) << PIO_IDR_P5_Pos)) +#define PIO_IDR_P6_Pos _U_(6) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P6_Msk (_U_(0x1) << PIO_IDR_P6_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P6(value) (PIO_IDR_P6_Msk & ((value) << PIO_IDR_P6_Pos)) +#define PIO_IDR_P7_Pos _U_(7) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P7_Msk (_U_(0x1) << PIO_IDR_P7_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P7(value) (PIO_IDR_P7_Msk & ((value) << PIO_IDR_P7_Pos)) +#define PIO_IDR_P8_Pos _U_(8) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P8_Msk (_U_(0x1) << PIO_IDR_P8_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P8(value) (PIO_IDR_P8_Msk & ((value) << PIO_IDR_P8_Pos)) +#define PIO_IDR_P9_Pos _U_(9) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P9_Msk (_U_(0x1) << PIO_IDR_P9_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P9(value) (PIO_IDR_P9_Msk & ((value) << PIO_IDR_P9_Pos)) +#define PIO_IDR_P10_Pos _U_(10) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P10_Msk (_U_(0x1) << PIO_IDR_P10_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P10(value) (PIO_IDR_P10_Msk & ((value) << PIO_IDR_P10_Pos)) +#define PIO_IDR_P11_Pos _U_(11) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P11_Msk (_U_(0x1) << PIO_IDR_P11_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P11(value) (PIO_IDR_P11_Msk & ((value) << PIO_IDR_P11_Pos)) +#define PIO_IDR_P12_Pos _U_(12) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P12_Msk (_U_(0x1) << PIO_IDR_P12_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P12(value) (PIO_IDR_P12_Msk & ((value) << PIO_IDR_P12_Pos)) +#define PIO_IDR_P13_Pos _U_(13) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P13_Msk (_U_(0x1) << PIO_IDR_P13_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P13(value) (PIO_IDR_P13_Msk & ((value) << PIO_IDR_P13_Pos)) +#define PIO_IDR_P14_Pos _U_(14) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P14_Msk (_U_(0x1) << PIO_IDR_P14_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P14(value) (PIO_IDR_P14_Msk & ((value) << PIO_IDR_P14_Pos)) +#define PIO_IDR_P15_Pos _U_(15) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P15_Msk (_U_(0x1) << PIO_IDR_P15_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P15(value) (PIO_IDR_P15_Msk & ((value) << PIO_IDR_P15_Pos)) +#define PIO_IDR_P16_Pos _U_(16) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P16_Msk (_U_(0x1) << PIO_IDR_P16_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P16(value) (PIO_IDR_P16_Msk & ((value) << PIO_IDR_P16_Pos)) +#define PIO_IDR_P17_Pos _U_(17) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P17_Msk (_U_(0x1) << PIO_IDR_P17_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P17(value) (PIO_IDR_P17_Msk & ((value) << PIO_IDR_P17_Pos)) +#define PIO_IDR_P18_Pos _U_(18) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P18_Msk (_U_(0x1) << PIO_IDR_P18_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P18(value) (PIO_IDR_P18_Msk & ((value) << PIO_IDR_P18_Pos)) +#define PIO_IDR_P19_Pos _U_(19) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P19_Msk (_U_(0x1) << PIO_IDR_P19_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P19(value) (PIO_IDR_P19_Msk & ((value) << PIO_IDR_P19_Pos)) +#define PIO_IDR_P20_Pos _U_(20) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P20_Msk (_U_(0x1) << PIO_IDR_P20_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P20(value) (PIO_IDR_P20_Msk & ((value) << PIO_IDR_P20_Pos)) +#define PIO_IDR_P21_Pos _U_(21) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P21_Msk (_U_(0x1) << PIO_IDR_P21_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P21(value) (PIO_IDR_P21_Msk & ((value) << PIO_IDR_P21_Pos)) +#define PIO_IDR_P22_Pos _U_(22) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P22_Msk (_U_(0x1) << PIO_IDR_P22_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P22(value) (PIO_IDR_P22_Msk & ((value) << PIO_IDR_P22_Pos)) +#define PIO_IDR_P23_Pos _U_(23) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P23_Msk (_U_(0x1) << PIO_IDR_P23_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P23(value) (PIO_IDR_P23_Msk & ((value) << PIO_IDR_P23_Pos)) +#define PIO_IDR_P24_Pos _U_(24) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P24_Msk (_U_(0x1) << PIO_IDR_P24_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P24(value) (PIO_IDR_P24_Msk & ((value) << PIO_IDR_P24_Pos)) +#define PIO_IDR_P25_Pos _U_(25) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P25_Msk (_U_(0x1) << PIO_IDR_P25_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P25(value) (PIO_IDR_P25_Msk & ((value) << PIO_IDR_P25_Pos)) +#define PIO_IDR_P26_Pos _U_(26) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P26_Msk (_U_(0x1) << PIO_IDR_P26_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P26(value) (PIO_IDR_P26_Msk & ((value) << PIO_IDR_P26_Pos)) +#define PIO_IDR_P27_Pos _U_(27) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P27_Msk (_U_(0x1) << PIO_IDR_P27_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P27(value) (PIO_IDR_P27_Msk & ((value) << PIO_IDR_P27_Pos)) +#define PIO_IDR_P28_Pos _U_(28) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P28_Msk (_U_(0x1) << PIO_IDR_P28_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P28(value) (PIO_IDR_P28_Msk & ((value) << PIO_IDR_P28_Pos)) +#define PIO_IDR_P29_Pos _U_(29) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P29_Msk (_U_(0x1) << PIO_IDR_P29_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P29(value) (PIO_IDR_P29_Msk & ((value) << PIO_IDR_P29_Pos)) +#define PIO_IDR_P30_Pos _U_(30) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P30_Msk (_U_(0x1) << PIO_IDR_P30_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P30(value) (PIO_IDR_P30_Msk & ((value) << PIO_IDR_P30_Pos)) +#define PIO_IDR_P31_Pos _U_(31) /**< (PIO_IDR) Input Change Interrupt Disable Position */ +#define PIO_IDR_P31_Msk (_U_(0x1) << PIO_IDR_P31_Pos) /**< (PIO_IDR) Input Change Interrupt Disable Mask */ +#define PIO_IDR_P31(value) (PIO_IDR_P31_Msk & ((value) << PIO_IDR_P31_Pos)) +#define PIO_IDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IDR) Register Mask */ + +#define PIO_IDR_P_Pos _U_(0) /**< (PIO_IDR Position) Input Change Interrupt Disable */ +#define PIO_IDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IDR_P_Pos) /**< (PIO_IDR Mask) P */ +#define PIO_IDR_P(value) (PIO_IDR_P_Msk & ((value) << PIO_IDR_P_Pos)) + +/* -------- PIO_IMR : (PIO Offset: 0x48) ( R/ 32) Interrupt Mask Register -------- */ +#define PIO_IMR_P0_Pos _U_(0) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P0_Msk (_U_(0x1) << PIO_IMR_P0_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P0(value) (PIO_IMR_P0_Msk & ((value) << PIO_IMR_P0_Pos)) +#define PIO_IMR_P1_Pos _U_(1) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P1_Msk (_U_(0x1) << PIO_IMR_P1_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P1(value) (PIO_IMR_P1_Msk & ((value) << PIO_IMR_P1_Pos)) +#define PIO_IMR_P2_Pos _U_(2) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P2_Msk (_U_(0x1) << PIO_IMR_P2_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P2(value) (PIO_IMR_P2_Msk & ((value) << PIO_IMR_P2_Pos)) +#define PIO_IMR_P3_Pos _U_(3) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P3_Msk (_U_(0x1) << PIO_IMR_P3_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P3(value) (PIO_IMR_P3_Msk & ((value) << PIO_IMR_P3_Pos)) +#define PIO_IMR_P4_Pos _U_(4) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P4_Msk (_U_(0x1) << PIO_IMR_P4_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P4(value) (PIO_IMR_P4_Msk & ((value) << PIO_IMR_P4_Pos)) +#define PIO_IMR_P5_Pos _U_(5) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P5_Msk (_U_(0x1) << PIO_IMR_P5_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P5(value) (PIO_IMR_P5_Msk & ((value) << PIO_IMR_P5_Pos)) +#define PIO_IMR_P6_Pos _U_(6) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P6_Msk (_U_(0x1) << PIO_IMR_P6_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P6(value) (PIO_IMR_P6_Msk & ((value) << PIO_IMR_P6_Pos)) +#define PIO_IMR_P7_Pos _U_(7) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P7_Msk (_U_(0x1) << PIO_IMR_P7_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P7(value) (PIO_IMR_P7_Msk & ((value) << PIO_IMR_P7_Pos)) +#define PIO_IMR_P8_Pos _U_(8) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P8_Msk (_U_(0x1) << PIO_IMR_P8_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P8(value) (PIO_IMR_P8_Msk & ((value) << PIO_IMR_P8_Pos)) +#define PIO_IMR_P9_Pos _U_(9) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P9_Msk (_U_(0x1) << PIO_IMR_P9_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P9(value) (PIO_IMR_P9_Msk & ((value) << PIO_IMR_P9_Pos)) +#define PIO_IMR_P10_Pos _U_(10) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P10_Msk (_U_(0x1) << PIO_IMR_P10_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P10(value) (PIO_IMR_P10_Msk & ((value) << PIO_IMR_P10_Pos)) +#define PIO_IMR_P11_Pos _U_(11) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P11_Msk (_U_(0x1) << PIO_IMR_P11_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P11(value) (PIO_IMR_P11_Msk & ((value) << PIO_IMR_P11_Pos)) +#define PIO_IMR_P12_Pos _U_(12) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P12_Msk (_U_(0x1) << PIO_IMR_P12_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P12(value) (PIO_IMR_P12_Msk & ((value) << PIO_IMR_P12_Pos)) +#define PIO_IMR_P13_Pos _U_(13) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P13_Msk (_U_(0x1) << PIO_IMR_P13_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P13(value) (PIO_IMR_P13_Msk & ((value) << PIO_IMR_P13_Pos)) +#define PIO_IMR_P14_Pos _U_(14) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P14_Msk (_U_(0x1) << PIO_IMR_P14_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P14(value) (PIO_IMR_P14_Msk & ((value) << PIO_IMR_P14_Pos)) +#define PIO_IMR_P15_Pos _U_(15) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P15_Msk (_U_(0x1) << PIO_IMR_P15_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P15(value) (PIO_IMR_P15_Msk & ((value) << PIO_IMR_P15_Pos)) +#define PIO_IMR_P16_Pos _U_(16) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P16_Msk (_U_(0x1) << PIO_IMR_P16_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P16(value) (PIO_IMR_P16_Msk & ((value) << PIO_IMR_P16_Pos)) +#define PIO_IMR_P17_Pos _U_(17) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P17_Msk (_U_(0x1) << PIO_IMR_P17_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P17(value) (PIO_IMR_P17_Msk & ((value) << PIO_IMR_P17_Pos)) +#define PIO_IMR_P18_Pos _U_(18) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P18_Msk (_U_(0x1) << PIO_IMR_P18_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P18(value) (PIO_IMR_P18_Msk & ((value) << PIO_IMR_P18_Pos)) +#define PIO_IMR_P19_Pos _U_(19) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P19_Msk (_U_(0x1) << PIO_IMR_P19_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P19(value) (PIO_IMR_P19_Msk & ((value) << PIO_IMR_P19_Pos)) +#define PIO_IMR_P20_Pos _U_(20) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P20_Msk (_U_(0x1) << PIO_IMR_P20_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P20(value) (PIO_IMR_P20_Msk & ((value) << PIO_IMR_P20_Pos)) +#define PIO_IMR_P21_Pos _U_(21) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P21_Msk (_U_(0x1) << PIO_IMR_P21_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P21(value) (PIO_IMR_P21_Msk & ((value) << PIO_IMR_P21_Pos)) +#define PIO_IMR_P22_Pos _U_(22) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P22_Msk (_U_(0x1) << PIO_IMR_P22_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P22(value) (PIO_IMR_P22_Msk & ((value) << PIO_IMR_P22_Pos)) +#define PIO_IMR_P23_Pos _U_(23) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P23_Msk (_U_(0x1) << PIO_IMR_P23_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P23(value) (PIO_IMR_P23_Msk & ((value) << PIO_IMR_P23_Pos)) +#define PIO_IMR_P24_Pos _U_(24) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P24_Msk (_U_(0x1) << PIO_IMR_P24_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P24(value) (PIO_IMR_P24_Msk & ((value) << PIO_IMR_P24_Pos)) +#define PIO_IMR_P25_Pos _U_(25) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P25_Msk (_U_(0x1) << PIO_IMR_P25_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P25(value) (PIO_IMR_P25_Msk & ((value) << PIO_IMR_P25_Pos)) +#define PIO_IMR_P26_Pos _U_(26) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P26_Msk (_U_(0x1) << PIO_IMR_P26_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P26(value) (PIO_IMR_P26_Msk & ((value) << PIO_IMR_P26_Pos)) +#define PIO_IMR_P27_Pos _U_(27) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P27_Msk (_U_(0x1) << PIO_IMR_P27_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P27(value) (PIO_IMR_P27_Msk & ((value) << PIO_IMR_P27_Pos)) +#define PIO_IMR_P28_Pos _U_(28) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P28_Msk (_U_(0x1) << PIO_IMR_P28_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P28(value) (PIO_IMR_P28_Msk & ((value) << PIO_IMR_P28_Pos)) +#define PIO_IMR_P29_Pos _U_(29) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P29_Msk (_U_(0x1) << PIO_IMR_P29_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P29(value) (PIO_IMR_P29_Msk & ((value) << PIO_IMR_P29_Pos)) +#define PIO_IMR_P30_Pos _U_(30) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P30_Msk (_U_(0x1) << PIO_IMR_P30_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P30(value) (PIO_IMR_P30_Msk & ((value) << PIO_IMR_P30_Pos)) +#define PIO_IMR_P31_Pos _U_(31) /**< (PIO_IMR) Input Change Interrupt Mask Position */ +#define PIO_IMR_P31_Msk (_U_(0x1) << PIO_IMR_P31_Pos) /**< (PIO_IMR) Input Change Interrupt Mask Mask */ +#define PIO_IMR_P31(value) (PIO_IMR_P31_Msk & ((value) << PIO_IMR_P31_Pos)) +#define PIO_IMR_Msk _U_(0xFFFFFFFF) /**< (PIO_IMR) Register Mask */ + +#define PIO_IMR_P_Pos _U_(0) /**< (PIO_IMR Position) Input Change Interrupt Mask */ +#define PIO_IMR_P_Msk (_U_(0xFFFFFFFF) << PIO_IMR_P_Pos) /**< (PIO_IMR Mask) P */ +#define PIO_IMR_P(value) (PIO_IMR_P_Msk & ((value) << PIO_IMR_P_Pos)) + +/* -------- PIO_ISR : (PIO Offset: 0x4C) ( R/ 32) Interrupt Status Register -------- */ +#define PIO_ISR_P0_Pos _U_(0) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P0_Msk (_U_(0x1) << PIO_ISR_P0_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P0(value) (PIO_ISR_P0_Msk & ((value) << PIO_ISR_P0_Pos)) +#define PIO_ISR_P1_Pos _U_(1) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P1_Msk (_U_(0x1) << PIO_ISR_P1_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P1(value) (PIO_ISR_P1_Msk & ((value) << PIO_ISR_P1_Pos)) +#define PIO_ISR_P2_Pos _U_(2) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P2_Msk (_U_(0x1) << PIO_ISR_P2_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P2(value) (PIO_ISR_P2_Msk & ((value) << PIO_ISR_P2_Pos)) +#define PIO_ISR_P3_Pos _U_(3) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P3_Msk (_U_(0x1) << PIO_ISR_P3_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P3(value) (PIO_ISR_P3_Msk & ((value) << PIO_ISR_P3_Pos)) +#define PIO_ISR_P4_Pos _U_(4) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P4_Msk (_U_(0x1) << PIO_ISR_P4_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P4(value) (PIO_ISR_P4_Msk & ((value) << PIO_ISR_P4_Pos)) +#define PIO_ISR_P5_Pos _U_(5) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P5_Msk (_U_(0x1) << PIO_ISR_P5_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P5(value) (PIO_ISR_P5_Msk & ((value) << PIO_ISR_P5_Pos)) +#define PIO_ISR_P6_Pos _U_(6) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P6_Msk (_U_(0x1) << PIO_ISR_P6_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P6(value) (PIO_ISR_P6_Msk & ((value) << PIO_ISR_P6_Pos)) +#define PIO_ISR_P7_Pos _U_(7) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P7_Msk (_U_(0x1) << PIO_ISR_P7_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P7(value) (PIO_ISR_P7_Msk & ((value) << PIO_ISR_P7_Pos)) +#define PIO_ISR_P8_Pos _U_(8) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P8_Msk (_U_(0x1) << PIO_ISR_P8_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P8(value) (PIO_ISR_P8_Msk & ((value) << PIO_ISR_P8_Pos)) +#define PIO_ISR_P9_Pos _U_(9) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P9_Msk (_U_(0x1) << PIO_ISR_P9_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P9(value) (PIO_ISR_P9_Msk & ((value) << PIO_ISR_P9_Pos)) +#define PIO_ISR_P10_Pos _U_(10) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P10_Msk (_U_(0x1) << PIO_ISR_P10_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P10(value) (PIO_ISR_P10_Msk & ((value) << PIO_ISR_P10_Pos)) +#define PIO_ISR_P11_Pos _U_(11) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P11_Msk (_U_(0x1) << PIO_ISR_P11_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P11(value) (PIO_ISR_P11_Msk & ((value) << PIO_ISR_P11_Pos)) +#define PIO_ISR_P12_Pos _U_(12) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P12_Msk (_U_(0x1) << PIO_ISR_P12_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P12(value) (PIO_ISR_P12_Msk & ((value) << PIO_ISR_P12_Pos)) +#define PIO_ISR_P13_Pos _U_(13) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P13_Msk (_U_(0x1) << PIO_ISR_P13_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P13(value) (PIO_ISR_P13_Msk & ((value) << PIO_ISR_P13_Pos)) +#define PIO_ISR_P14_Pos _U_(14) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P14_Msk (_U_(0x1) << PIO_ISR_P14_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P14(value) (PIO_ISR_P14_Msk & ((value) << PIO_ISR_P14_Pos)) +#define PIO_ISR_P15_Pos _U_(15) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P15_Msk (_U_(0x1) << PIO_ISR_P15_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P15(value) (PIO_ISR_P15_Msk & ((value) << PIO_ISR_P15_Pos)) +#define PIO_ISR_P16_Pos _U_(16) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P16_Msk (_U_(0x1) << PIO_ISR_P16_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P16(value) (PIO_ISR_P16_Msk & ((value) << PIO_ISR_P16_Pos)) +#define PIO_ISR_P17_Pos _U_(17) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P17_Msk (_U_(0x1) << PIO_ISR_P17_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P17(value) (PIO_ISR_P17_Msk & ((value) << PIO_ISR_P17_Pos)) +#define PIO_ISR_P18_Pos _U_(18) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P18_Msk (_U_(0x1) << PIO_ISR_P18_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P18(value) (PIO_ISR_P18_Msk & ((value) << PIO_ISR_P18_Pos)) +#define PIO_ISR_P19_Pos _U_(19) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P19_Msk (_U_(0x1) << PIO_ISR_P19_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P19(value) (PIO_ISR_P19_Msk & ((value) << PIO_ISR_P19_Pos)) +#define PIO_ISR_P20_Pos _U_(20) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P20_Msk (_U_(0x1) << PIO_ISR_P20_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P20(value) (PIO_ISR_P20_Msk & ((value) << PIO_ISR_P20_Pos)) +#define PIO_ISR_P21_Pos _U_(21) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P21_Msk (_U_(0x1) << PIO_ISR_P21_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P21(value) (PIO_ISR_P21_Msk & ((value) << PIO_ISR_P21_Pos)) +#define PIO_ISR_P22_Pos _U_(22) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P22_Msk (_U_(0x1) << PIO_ISR_P22_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P22(value) (PIO_ISR_P22_Msk & ((value) << PIO_ISR_P22_Pos)) +#define PIO_ISR_P23_Pos _U_(23) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P23_Msk (_U_(0x1) << PIO_ISR_P23_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P23(value) (PIO_ISR_P23_Msk & ((value) << PIO_ISR_P23_Pos)) +#define PIO_ISR_P24_Pos _U_(24) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P24_Msk (_U_(0x1) << PIO_ISR_P24_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P24(value) (PIO_ISR_P24_Msk & ((value) << PIO_ISR_P24_Pos)) +#define PIO_ISR_P25_Pos _U_(25) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P25_Msk (_U_(0x1) << PIO_ISR_P25_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P25(value) (PIO_ISR_P25_Msk & ((value) << PIO_ISR_P25_Pos)) +#define PIO_ISR_P26_Pos _U_(26) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P26_Msk (_U_(0x1) << PIO_ISR_P26_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P26(value) (PIO_ISR_P26_Msk & ((value) << PIO_ISR_P26_Pos)) +#define PIO_ISR_P27_Pos _U_(27) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P27_Msk (_U_(0x1) << PIO_ISR_P27_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P27(value) (PIO_ISR_P27_Msk & ((value) << PIO_ISR_P27_Pos)) +#define PIO_ISR_P28_Pos _U_(28) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P28_Msk (_U_(0x1) << PIO_ISR_P28_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P28(value) (PIO_ISR_P28_Msk & ((value) << PIO_ISR_P28_Pos)) +#define PIO_ISR_P29_Pos _U_(29) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P29_Msk (_U_(0x1) << PIO_ISR_P29_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P29(value) (PIO_ISR_P29_Msk & ((value) << PIO_ISR_P29_Pos)) +#define PIO_ISR_P30_Pos _U_(30) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P30_Msk (_U_(0x1) << PIO_ISR_P30_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P30(value) (PIO_ISR_P30_Msk & ((value) << PIO_ISR_P30_Pos)) +#define PIO_ISR_P31_Pos _U_(31) /**< (PIO_ISR) Input Change Interrupt Status Position */ +#define PIO_ISR_P31_Msk (_U_(0x1) << PIO_ISR_P31_Pos) /**< (PIO_ISR) Input Change Interrupt Status Mask */ +#define PIO_ISR_P31(value) (PIO_ISR_P31_Msk & ((value) << PIO_ISR_P31_Pos)) +#define PIO_ISR_Msk _U_(0xFFFFFFFF) /**< (PIO_ISR) Register Mask */ + +#define PIO_ISR_P_Pos _U_(0) /**< (PIO_ISR Position) Input Change Interrupt Status */ +#define PIO_ISR_P_Msk (_U_(0xFFFFFFFF) << PIO_ISR_P_Pos) /**< (PIO_ISR Mask) P */ +#define PIO_ISR_P(value) (PIO_ISR_P_Msk & ((value) << PIO_ISR_P_Pos)) + +/* -------- PIO_MDER : (PIO Offset: 0x50) ( /W 32) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0_Pos _U_(0) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P0_Msk (_U_(0x1) << PIO_MDER_P0_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P0(value) (PIO_MDER_P0_Msk & ((value) << PIO_MDER_P0_Pos)) +#define PIO_MDER_P1_Pos _U_(1) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P1_Msk (_U_(0x1) << PIO_MDER_P1_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P1(value) (PIO_MDER_P1_Msk & ((value) << PIO_MDER_P1_Pos)) +#define PIO_MDER_P2_Pos _U_(2) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P2_Msk (_U_(0x1) << PIO_MDER_P2_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P2(value) (PIO_MDER_P2_Msk & ((value) << PIO_MDER_P2_Pos)) +#define PIO_MDER_P3_Pos _U_(3) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P3_Msk (_U_(0x1) << PIO_MDER_P3_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P3(value) (PIO_MDER_P3_Msk & ((value) << PIO_MDER_P3_Pos)) +#define PIO_MDER_P4_Pos _U_(4) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P4_Msk (_U_(0x1) << PIO_MDER_P4_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P4(value) (PIO_MDER_P4_Msk & ((value) << PIO_MDER_P4_Pos)) +#define PIO_MDER_P5_Pos _U_(5) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P5_Msk (_U_(0x1) << PIO_MDER_P5_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P5(value) (PIO_MDER_P5_Msk & ((value) << PIO_MDER_P5_Pos)) +#define PIO_MDER_P6_Pos _U_(6) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P6_Msk (_U_(0x1) << PIO_MDER_P6_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P6(value) (PIO_MDER_P6_Msk & ((value) << PIO_MDER_P6_Pos)) +#define PIO_MDER_P7_Pos _U_(7) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P7_Msk (_U_(0x1) << PIO_MDER_P7_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P7(value) (PIO_MDER_P7_Msk & ((value) << PIO_MDER_P7_Pos)) +#define PIO_MDER_P8_Pos _U_(8) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P8_Msk (_U_(0x1) << PIO_MDER_P8_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P8(value) (PIO_MDER_P8_Msk & ((value) << PIO_MDER_P8_Pos)) +#define PIO_MDER_P9_Pos _U_(9) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P9_Msk (_U_(0x1) << PIO_MDER_P9_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P9(value) (PIO_MDER_P9_Msk & ((value) << PIO_MDER_P9_Pos)) +#define PIO_MDER_P10_Pos _U_(10) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P10_Msk (_U_(0x1) << PIO_MDER_P10_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P10(value) (PIO_MDER_P10_Msk & ((value) << PIO_MDER_P10_Pos)) +#define PIO_MDER_P11_Pos _U_(11) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P11_Msk (_U_(0x1) << PIO_MDER_P11_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P11(value) (PIO_MDER_P11_Msk & ((value) << PIO_MDER_P11_Pos)) +#define PIO_MDER_P12_Pos _U_(12) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P12_Msk (_U_(0x1) << PIO_MDER_P12_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P12(value) (PIO_MDER_P12_Msk & ((value) << PIO_MDER_P12_Pos)) +#define PIO_MDER_P13_Pos _U_(13) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P13_Msk (_U_(0x1) << PIO_MDER_P13_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P13(value) (PIO_MDER_P13_Msk & ((value) << PIO_MDER_P13_Pos)) +#define PIO_MDER_P14_Pos _U_(14) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P14_Msk (_U_(0x1) << PIO_MDER_P14_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P14(value) (PIO_MDER_P14_Msk & ((value) << PIO_MDER_P14_Pos)) +#define PIO_MDER_P15_Pos _U_(15) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P15_Msk (_U_(0x1) << PIO_MDER_P15_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P15(value) (PIO_MDER_P15_Msk & ((value) << PIO_MDER_P15_Pos)) +#define PIO_MDER_P16_Pos _U_(16) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P16_Msk (_U_(0x1) << PIO_MDER_P16_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P16(value) (PIO_MDER_P16_Msk & ((value) << PIO_MDER_P16_Pos)) +#define PIO_MDER_P17_Pos _U_(17) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P17_Msk (_U_(0x1) << PIO_MDER_P17_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P17(value) (PIO_MDER_P17_Msk & ((value) << PIO_MDER_P17_Pos)) +#define PIO_MDER_P18_Pos _U_(18) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P18_Msk (_U_(0x1) << PIO_MDER_P18_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P18(value) (PIO_MDER_P18_Msk & ((value) << PIO_MDER_P18_Pos)) +#define PIO_MDER_P19_Pos _U_(19) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P19_Msk (_U_(0x1) << PIO_MDER_P19_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P19(value) (PIO_MDER_P19_Msk & ((value) << PIO_MDER_P19_Pos)) +#define PIO_MDER_P20_Pos _U_(20) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P20_Msk (_U_(0x1) << PIO_MDER_P20_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P20(value) (PIO_MDER_P20_Msk & ((value) << PIO_MDER_P20_Pos)) +#define PIO_MDER_P21_Pos _U_(21) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P21_Msk (_U_(0x1) << PIO_MDER_P21_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P21(value) (PIO_MDER_P21_Msk & ((value) << PIO_MDER_P21_Pos)) +#define PIO_MDER_P22_Pos _U_(22) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P22_Msk (_U_(0x1) << PIO_MDER_P22_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P22(value) (PIO_MDER_P22_Msk & ((value) << PIO_MDER_P22_Pos)) +#define PIO_MDER_P23_Pos _U_(23) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P23_Msk (_U_(0x1) << PIO_MDER_P23_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P23(value) (PIO_MDER_P23_Msk & ((value) << PIO_MDER_P23_Pos)) +#define PIO_MDER_P24_Pos _U_(24) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P24_Msk (_U_(0x1) << PIO_MDER_P24_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P24(value) (PIO_MDER_P24_Msk & ((value) << PIO_MDER_P24_Pos)) +#define PIO_MDER_P25_Pos _U_(25) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P25_Msk (_U_(0x1) << PIO_MDER_P25_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P25(value) (PIO_MDER_P25_Msk & ((value) << PIO_MDER_P25_Pos)) +#define PIO_MDER_P26_Pos _U_(26) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P26_Msk (_U_(0x1) << PIO_MDER_P26_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P26(value) (PIO_MDER_P26_Msk & ((value) << PIO_MDER_P26_Pos)) +#define PIO_MDER_P27_Pos _U_(27) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P27_Msk (_U_(0x1) << PIO_MDER_P27_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P27(value) (PIO_MDER_P27_Msk & ((value) << PIO_MDER_P27_Pos)) +#define PIO_MDER_P28_Pos _U_(28) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P28_Msk (_U_(0x1) << PIO_MDER_P28_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P28(value) (PIO_MDER_P28_Msk & ((value) << PIO_MDER_P28_Pos)) +#define PIO_MDER_P29_Pos _U_(29) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P29_Msk (_U_(0x1) << PIO_MDER_P29_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P29(value) (PIO_MDER_P29_Msk & ((value) << PIO_MDER_P29_Pos)) +#define PIO_MDER_P30_Pos _U_(30) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P30_Msk (_U_(0x1) << PIO_MDER_P30_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P30(value) (PIO_MDER_P30_Msk & ((value) << PIO_MDER_P30_Pos)) +#define PIO_MDER_P31_Pos _U_(31) /**< (PIO_MDER) Multi-drive Enable Position */ +#define PIO_MDER_P31_Msk (_U_(0x1) << PIO_MDER_P31_Pos) /**< (PIO_MDER) Multi-drive Enable Mask */ +#define PIO_MDER_P31(value) (PIO_MDER_P31_Msk & ((value) << PIO_MDER_P31_Pos)) +#define PIO_MDER_Msk _U_(0xFFFFFFFF) /**< (PIO_MDER) Register Mask */ + +#define PIO_MDER_P_Pos _U_(0) /**< (PIO_MDER Position) Multi-drive Enable */ +#define PIO_MDER_P_Msk (_U_(0xFFFFFFFF) << PIO_MDER_P_Pos) /**< (PIO_MDER Mask) P */ +#define PIO_MDER_P(value) (PIO_MDER_P_Msk & ((value) << PIO_MDER_P_Pos)) + +/* -------- PIO_MDDR : (PIO Offset: 0x54) ( /W 32) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0_Pos _U_(0) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P0_Msk (_U_(0x1) << PIO_MDDR_P0_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P0(value) (PIO_MDDR_P0_Msk & ((value) << PIO_MDDR_P0_Pos)) +#define PIO_MDDR_P1_Pos _U_(1) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P1_Msk (_U_(0x1) << PIO_MDDR_P1_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P1(value) (PIO_MDDR_P1_Msk & ((value) << PIO_MDDR_P1_Pos)) +#define PIO_MDDR_P2_Pos _U_(2) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P2_Msk (_U_(0x1) << PIO_MDDR_P2_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P2(value) (PIO_MDDR_P2_Msk & ((value) << PIO_MDDR_P2_Pos)) +#define PIO_MDDR_P3_Pos _U_(3) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P3_Msk (_U_(0x1) << PIO_MDDR_P3_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P3(value) (PIO_MDDR_P3_Msk & ((value) << PIO_MDDR_P3_Pos)) +#define PIO_MDDR_P4_Pos _U_(4) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P4_Msk (_U_(0x1) << PIO_MDDR_P4_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P4(value) (PIO_MDDR_P4_Msk & ((value) << PIO_MDDR_P4_Pos)) +#define PIO_MDDR_P5_Pos _U_(5) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P5_Msk (_U_(0x1) << PIO_MDDR_P5_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P5(value) (PIO_MDDR_P5_Msk & ((value) << PIO_MDDR_P5_Pos)) +#define PIO_MDDR_P6_Pos _U_(6) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P6_Msk (_U_(0x1) << PIO_MDDR_P6_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P6(value) (PIO_MDDR_P6_Msk & ((value) << PIO_MDDR_P6_Pos)) +#define PIO_MDDR_P7_Pos _U_(7) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P7_Msk (_U_(0x1) << PIO_MDDR_P7_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P7(value) (PIO_MDDR_P7_Msk & ((value) << PIO_MDDR_P7_Pos)) +#define PIO_MDDR_P8_Pos _U_(8) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P8_Msk (_U_(0x1) << PIO_MDDR_P8_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P8(value) (PIO_MDDR_P8_Msk & ((value) << PIO_MDDR_P8_Pos)) +#define PIO_MDDR_P9_Pos _U_(9) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P9_Msk (_U_(0x1) << PIO_MDDR_P9_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P9(value) (PIO_MDDR_P9_Msk & ((value) << PIO_MDDR_P9_Pos)) +#define PIO_MDDR_P10_Pos _U_(10) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P10_Msk (_U_(0x1) << PIO_MDDR_P10_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P10(value) (PIO_MDDR_P10_Msk & ((value) << PIO_MDDR_P10_Pos)) +#define PIO_MDDR_P11_Pos _U_(11) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P11_Msk (_U_(0x1) << PIO_MDDR_P11_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P11(value) (PIO_MDDR_P11_Msk & ((value) << PIO_MDDR_P11_Pos)) +#define PIO_MDDR_P12_Pos _U_(12) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P12_Msk (_U_(0x1) << PIO_MDDR_P12_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P12(value) (PIO_MDDR_P12_Msk & ((value) << PIO_MDDR_P12_Pos)) +#define PIO_MDDR_P13_Pos _U_(13) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P13_Msk (_U_(0x1) << PIO_MDDR_P13_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P13(value) (PIO_MDDR_P13_Msk & ((value) << PIO_MDDR_P13_Pos)) +#define PIO_MDDR_P14_Pos _U_(14) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P14_Msk (_U_(0x1) << PIO_MDDR_P14_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P14(value) (PIO_MDDR_P14_Msk & ((value) << PIO_MDDR_P14_Pos)) +#define PIO_MDDR_P15_Pos _U_(15) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P15_Msk (_U_(0x1) << PIO_MDDR_P15_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P15(value) (PIO_MDDR_P15_Msk & ((value) << PIO_MDDR_P15_Pos)) +#define PIO_MDDR_P16_Pos _U_(16) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P16_Msk (_U_(0x1) << PIO_MDDR_P16_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P16(value) (PIO_MDDR_P16_Msk & ((value) << PIO_MDDR_P16_Pos)) +#define PIO_MDDR_P17_Pos _U_(17) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P17_Msk (_U_(0x1) << PIO_MDDR_P17_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P17(value) (PIO_MDDR_P17_Msk & ((value) << PIO_MDDR_P17_Pos)) +#define PIO_MDDR_P18_Pos _U_(18) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P18_Msk (_U_(0x1) << PIO_MDDR_P18_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P18(value) (PIO_MDDR_P18_Msk & ((value) << PIO_MDDR_P18_Pos)) +#define PIO_MDDR_P19_Pos _U_(19) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P19_Msk (_U_(0x1) << PIO_MDDR_P19_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P19(value) (PIO_MDDR_P19_Msk & ((value) << PIO_MDDR_P19_Pos)) +#define PIO_MDDR_P20_Pos _U_(20) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P20_Msk (_U_(0x1) << PIO_MDDR_P20_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P20(value) (PIO_MDDR_P20_Msk & ((value) << PIO_MDDR_P20_Pos)) +#define PIO_MDDR_P21_Pos _U_(21) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P21_Msk (_U_(0x1) << PIO_MDDR_P21_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P21(value) (PIO_MDDR_P21_Msk & ((value) << PIO_MDDR_P21_Pos)) +#define PIO_MDDR_P22_Pos _U_(22) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P22_Msk (_U_(0x1) << PIO_MDDR_P22_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P22(value) (PIO_MDDR_P22_Msk & ((value) << PIO_MDDR_P22_Pos)) +#define PIO_MDDR_P23_Pos _U_(23) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P23_Msk (_U_(0x1) << PIO_MDDR_P23_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P23(value) (PIO_MDDR_P23_Msk & ((value) << PIO_MDDR_P23_Pos)) +#define PIO_MDDR_P24_Pos _U_(24) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P24_Msk (_U_(0x1) << PIO_MDDR_P24_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P24(value) (PIO_MDDR_P24_Msk & ((value) << PIO_MDDR_P24_Pos)) +#define PIO_MDDR_P25_Pos _U_(25) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P25_Msk (_U_(0x1) << PIO_MDDR_P25_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P25(value) (PIO_MDDR_P25_Msk & ((value) << PIO_MDDR_P25_Pos)) +#define PIO_MDDR_P26_Pos _U_(26) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P26_Msk (_U_(0x1) << PIO_MDDR_P26_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P26(value) (PIO_MDDR_P26_Msk & ((value) << PIO_MDDR_P26_Pos)) +#define PIO_MDDR_P27_Pos _U_(27) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P27_Msk (_U_(0x1) << PIO_MDDR_P27_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P27(value) (PIO_MDDR_P27_Msk & ((value) << PIO_MDDR_P27_Pos)) +#define PIO_MDDR_P28_Pos _U_(28) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P28_Msk (_U_(0x1) << PIO_MDDR_P28_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P28(value) (PIO_MDDR_P28_Msk & ((value) << PIO_MDDR_P28_Pos)) +#define PIO_MDDR_P29_Pos _U_(29) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P29_Msk (_U_(0x1) << PIO_MDDR_P29_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P29(value) (PIO_MDDR_P29_Msk & ((value) << PIO_MDDR_P29_Pos)) +#define PIO_MDDR_P30_Pos _U_(30) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P30_Msk (_U_(0x1) << PIO_MDDR_P30_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P30(value) (PIO_MDDR_P30_Msk & ((value) << PIO_MDDR_P30_Pos)) +#define PIO_MDDR_P31_Pos _U_(31) /**< (PIO_MDDR) Multi-drive Disable Position */ +#define PIO_MDDR_P31_Msk (_U_(0x1) << PIO_MDDR_P31_Pos) /**< (PIO_MDDR) Multi-drive Disable Mask */ +#define PIO_MDDR_P31(value) (PIO_MDDR_P31_Msk & ((value) << PIO_MDDR_P31_Pos)) +#define PIO_MDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDDR) Register Mask */ + +#define PIO_MDDR_P_Pos _U_(0) /**< (PIO_MDDR Position) Multi-drive Disable */ +#define PIO_MDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDDR_P_Pos) /**< (PIO_MDDR Mask) P */ +#define PIO_MDDR_P(value) (PIO_MDDR_P_Msk & ((value) << PIO_MDDR_P_Pos)) + +/* -------- PIO_MDSR : (PIO Offset: 0x58) ( R/ 32) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0_Pos _U_(0) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P0_Msk (_U_(0x1) << PIO_MDSR_P0_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P0(value) (PIO_MDSR_P0_Msk & ((value) << PIO_MDSR_P0_Pos)) +#define PIO_MDSR_P1_Pos _U_(1) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P1_Msk (_U_(0x1) << PIO_MDSR_P1_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P1(value) (PIO_MDSR_P1_Msk & ((value) << PIO_MDSR_P1_Pos)) +#define PIO_MDSR_P2_Pos _U_(2) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P2_Msk (_U_(0x1) << PIO_MDSR_P2_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P2(value) (PIO_MDSR_P2_Msk & ((value) << PIO_MDSR_P2_Pos)) +#define PIO_MDSR_P3_Pos _U_(3) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P3_Msk (_U_(0x1) << PIO_MDSR_P3_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P3(value) (PIO_MDSR_P3_Msk & ((value) << PIO_MDSR_P3_Pos)) +#define PIO_MDSR_P4_Pos _U_(4) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P4_Msk (_U_(0x1) << PIO_MDSR_P4_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P4(value) (PIO_MDSR_P4_Msk & ((value) << PIO_MDSR_P4_Pos)) +#define PIO_MDSR_P5_Pos _U_(5) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P5_Msk (_U_(0x1) << PIO_MDSR_P5_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P5(value) (PIO_MDSR_P5_Msk & ((value) << PIO_MDSR_P5_Pos)) +#define PIO_MDSR_P6_Pos _U_(6) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P6_Msk (_U_(0x1) << PIO_MDSR_P6_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P6(value) (PIO_MDSR_P6_Msk & ((value) << PIO_MDSR_P6_Pos)) +#define PIO_MDSR_P7_Pos _U_(7) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P7_Msk (_U_(0x1) << PIO_MDSR_P7_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P7(value) (PIO_MDSR_P7_Msk & ((value) << PIO_MDSR_P7_Pos)) +#define PIO_MDSR_P8_Pos _U_(8) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P8_Msk (_U_(0x1) << PIO_MDSR_P8_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P8(value) (PIO_MDSR_P8_Msk & ((value) << PIO_MDSR_P8_Pos)) +#define PIO_MDSR_P9_Pos _U_(9) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P9_Msk (_U_(0x1) << PIO_MDSR_P9_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P9(value) (PIO_MDSR_P9_Msk & ((value) << PIO_MDSR_P9_Pos)) +#define PIO_MDSR_P10_Pos _U_(10) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P10_Msk (_U_(0x1) << PIO_MDSR_P10_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P10(value) (PIO_MDSR_P10_Msk & ((value) << PIO_MDSR_P10_Pos)) +#define PIO_MDSR_P11_Pos _U_(11) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P11_Msk (_U_(0x1) << PIO_MDSR_P11_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P11(value) (PIO_MDSR_P11_Msk & ((value) << PIO_MDSR_P11_Pos)) +#define PIO_MDSR_P12_Pos _U_(12) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P12_Msk (_U_(0x1) << PIO_MDSR_P12_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P12(value) (PIO_MDSR_P12_Msk & ((value) << PIO_MDSR_P12_Pos)) +#define PIO_MDSR_P13_Pos _U_(13) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P13_Msk (_U_(0x1) << PIO_MDSR_P13_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P13(value) (PIO_MDSR_P13_Msk & ((value) << PIO_MDSR_P13_Pos)) +#define PIO_MDSR_P14_Pos _U_(14) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P14_Msk (_U_(0x1) << PIO_MDSR_P14_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P14(value) (PIO_MDSR_P14_Msk & ((value) << PIO_MDSR_P14_Pos)) +#define PIO_MDSR_P15_Pos _U_(15) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P15_Msk (_U_(0x1) << PIO_MDSR_P15_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P15(value) (PIO_MDSR_P15_Msk & ((value) << PIO_MDSR_P15_Pos)) +#define PIO_MDSR_P16_Pos _U_(16) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P16_Msk (_U_(0x1) << PIO_MDSR_P16_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P16(value) (PIO_MDSR_P16_Msk & ((value) << PIO_MDSR_P16_Pos)) +#define PIO_MDSR_P17_Pos _U_(17) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P17_Msk (_U_(0x1) << PIO_MDSR_P17_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P17(value) (PIO_MDSR_P17_Msk & ((value) << PIO_MDSR_P17_Pos)) +#define PIO_MDSR_P18_Pos _U_(18) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P18_Msk (_U_(0x1) << PIO_MDSR_P18_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P18(value) (PIO_MDSR_P18_Msk & ((value) << PIO_MDSR_P18_Pos)) +#define PIO_MDSR_P19_Pos _U_(19) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P19_Msk (_U_(0x1) << PIO_MDSR_P19_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P19(value) (PIO_MDSR_P19_Msk & ((value) << PIO_MDSR_P19_Pos)) +#define PIO_MDSR_P20_Pos _U_(20) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P20_Msk (_U_(0x1) << PIO_MDSR_P20_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P20(value) (PIO_MDSR_P20_Msk & ((value) << PIO_MDSR_P20_Pos)) +#define PIO_MDSR_P21_Pos _U_(21) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P21_Msk (_U_(0x1) << PIO_MDSR_P21_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P21(value) (PIO_MDSR_P21_Msk & ((value) << PIO_MDSR_P21_Pos)) +#define PIO_MDSR_P22_Pos _U_(22) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P22_Msk (_U_(0x1) << PIO_MDSR_P22_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P22(value) (PIO_MDSR_P22_Msk & ((value) << PIO_MDSR_P22_Pos)) +#define PIO_MDSR_P23_Pos _U_(23) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P23_Msk (_U_(0x1) << PIO_MDSR_P23_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P23(value) (PIO_MDSR_P23_Msk & ((value) << PIO_MDSR_P23_Pos)) +#define PIO_MDSR_P24_Pos _U_(24) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P24_Msk (_U_(0x1) << PIO_MDSR_P24_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P24(value) (PIO_MDSR_P24_Msk & ((value) << PIO_MDSR_P24_Pos)) +#define PIO_MDSR_P25_Pos _U_(25) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P25_Msk (_U_(0x1) << PIO_MDSR_P25_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P25(value) (PIO_MDSR_P25_Msk & ((value) << PIO_MDSR_P25_Pos)) +#define PIO_MDSR_P26_Pos _U_(26) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P26_Msk (_U_(0x1) << PIO_MDSR_P26_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P26(value) (PIO_MDSR_P26_Msk & ((value) << PIO_MDSR_P26_Pos)) +#define PIO_MDSR_P27_Pos _U_(27) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P27_Msk (_U_(0x1) << PIO_MDSR_P27_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P27(value) (PIO_MDSR_P27_Msk & ((value) << PIO_MDSR_P27_Pos)) +#define PIO_MDSR_P28_Pos _U_(28) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P28_Msk (_U_(0x1) << PIO_MDSR_P28_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P28(value) (PIO_MDSR_P28_Msk & ((value) << PIO_MDSR_P28_Pos)) +#define PIO_MDSR_P29_Pos _U_(29) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P29_Msk (_U_(0x1) << PIO_MDSR_P29_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P29(value) (PIO_MDSR_P29_Msk & ((value) << PIO_MDSR_P29_Pos)) +#define PIO_MDSR_P30_Pos _U_(30) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P30_Msk (_U_(0x1) << PIO_MDSR_P30_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P30(value) (PIO_MDSR_P30_Msk & ((value) << PIO_MDSR_P30_Pos)) +#define PIO_MDSR_P31_Pos _U_(31) /**< (PIO_MDSR) Multi-drive Status Position */ +#define PIO_MDSR_P31_Msk (_U_(0x1) << PIO_MDSR_P31_Pos) /**< (PIO_MDSR) Multi-drive Status Mask */ +#define PIO_MDSR_P31(value) (PIO_MDSR_P31_Msk & ((value) << PIO_MDSR_P31_Pos)) +#define PIO_MDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_MDSR) Register Mask */ + +#define PIO_MDSR_P_Pos _U_(0) /**< (PIO_MDSR Position) Multi-drive Status */ +#define PIO_MDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_MDSR_P_Pos) /**< (PIO_MDSR Mask) P */ +#define PIO_MDSR_P(value) (PIO_MDSR_P_Msk & ((value) << PIO_MDSR_P_Pos)) + +/* -------- PIO_PUDR : (PIO Offset: 0x60) ( /W 32) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0_Pos _U_(0) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P0_Msk (_U_(0x1) << PIO_PUDR_P0_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P0(value) (PIO_PUDR_P0_Msk & ((value) << PIO_PUDR_P0_Pos)) +#define PIO_PUDR_P1_Pos _U_(1) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P1_Msk (_U_(0x1) << PIO_PUDR_P1_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P1(value) (PIO_PUDR_P1_Msk & ((value) << PIO_PUDR_P1_Pos)) +#define PIO_PUDR_P2_Pos _U_(2) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P2_Msk (_U_(0x1) << PIO_PUDR_P2_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P2(value) (PIO_PUDR_P2_Msk & ((value) << PIO_PUDR_P2_Pos)) +#define PIO_PUDR_P3_Pos _U_(3) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P3_Msk (_U_(0x1) << PIO_PUDR_P3_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P3(value) (PIO_PUDR_P3_Msk & ((value) << PIO_PUDR_P3_Pos)) +#define PIO_PUDR_P4_Pos _U_(4) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P4_Msk (_U_(0x1) << PIO_PUDR_P4_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P4(value) (PIO_PUDR_P4_Msk & ((value) << PIO_PUDR_P4_Pos)) +#define PIO_PUDR_P5_Pos _U_(5) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P5_Msk (_U_(0x1) << PIO_PUDR_P5_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P5(value) (PIO_PUDR_P5_Msk & ((value) << PIO_PUDR_P5_Pos)) +#define PIO_PUDR_P6_Pos _U_(6) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P6_Msk (_U_(0x1) << PIO_PUDR_P6_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P6(value) (PIO_PUDR_P6_Msk & ((value) << PIO_PUDR_P6_Pos)) +#define PIO_PUDR_P7_Pos _U_(7) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P7_Msk (_U_(0x1) << PIO_PUDR_P7_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P7(value) (PIO_PUDR_P7_Msk & ((value) << PIO_PUDR_P7_Pos)) +#define PIO_PUDR_P8_Pos _U_(8) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P8_Msk (_U_(0x1) << PIO_PUDR_P8_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P8(value) (PIO_PUDR_P8_Msk & ((value) << PIO_PUDR_P8_Pos)) +#define PIO_PUDR_P9_Pos _U_(9) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P9_Msk (_U_(0x1) << PIO_PUDR_P9_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P9(value) (PIO_PUDR_P9_Msk & ((value) << PIO_PUDR_P9_Pos)) +#define PIO_PUDR_P10_Pos _U_(10) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P10_Msk (_U_(0x1) << PIO_PUDR_P10_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P10(value) (PIO_PUDR_P10_Msk & ((value) << PIO_PUDR_P10_Pos)) +#define PIO_PUDR_P11_Pos _U_(11) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P11_Msk (_U_(0x1) << PIO_PUDR_P11_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P11(value) (PIO_PUDR_P11_Msk & ((value) << PIO_PUDR_P11_Pos)) +#define PIO_PUDR_P12_Pos _U_(12) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P12_Msk (_U_(0x1) << PIO_PUDR_P12_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P12(value) (PIO_PUDR_P12_Msk & ((value) << PIO_PUDR_P12_Pos)) +#define PIO_PUDR_P13_Pos _U_(13) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P13_Msk (_U_(0x1) << PIO_PUDR_P13_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P13(value) (PIO_PUDR_P13_Msk & ((value) << PIO_PUDR_P13_Pos)) +#define PIO_PUDR_P14_Pos _U_(14) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P14_Msk (_U_(0x1) << PIO_PUDR_P14_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P14(value) (PIO_PUDR_P14_Msk & ((value) << PIO_PUDR_P14_Pos)) +#define PIO_PUDR_P15_Pos _U_(15) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P15_Msk (_U_(0x1) << PIO_PUDR_P15_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P15(value) (PIO_PUDR_P15_Msk & ((value) << PIO_PUDR_P15_Pos)) +#define PIO_PUDR_P16_Pos _U_(16) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P16_Msk (_U_(0x1) << PIO_PUDR_P16_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P16(value) (PIO_PUDR_P16_Msk & ((value) << PIO_PUDR_P16_Pos)) +#define PIO_PUDR_P17_Pos _U_(17) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P17_Msk (_U_(0x1) << PIO_PUDR_P17_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P17(value) (PIO_PUDR_P17_Msk & ((value) << PIO_PUDR_P17_Pos)) +#define PIO_PUDR_P18_Pos _U_(18) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P18_Msk (_U_(0x1) << PIO_PUDR_P18_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P18(value) (PIO_PUDR_P18_Msk & ((value) << PIO_PUDR_P18_Pos)) +#define PIO_PUDR_P19_Pos _U_(19) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P19_Msk (_U_(0x1) << PIO_PUDR_P19_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P19(value) (PIO_PUDR_P19_Msk & ((value) << PIO_PUDR_P19_Pos)) +#define PIO_PUDR_P20_Pos _U_(20) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P20_Msk (_U_(0x1) << PIO_PUDR_P20_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P20(value) (PIO_PUDR_P20_Msk & ((value) << PIO_PUDR_P20_Pos)) +#define PIO_PUDR_P21_Pos _U_(21) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P21_Msk (_U_(0x1) << PIO_PUDR_P21_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P21(value) (PIO_PUDR_P21_Msk & ((value) << PIO_PUDR_P21_Pos)) +#define PIO_PUDR_P22_Pos _U_(22) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P22_Msk (_U_(0x1) << PIO_PUDR_P22_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P22(value) (PIO_PUDR_P22_Msk & ((value) << PIO_PUDR_P22_Pos)) +#define PIO_PUDR_P23_Pos _U_(23) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P23_Msk (_U_(0x1) << PIO_PUDR_P23_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P23(value) (PIO_PUDR_P23_Msk & ((value) << PIO_PUDR_P23_Pos)) +#define PIO_PUDR_P24_Pos _U_(24) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P24_Msk (_U_(0x1) << PIO_PUDR_P24_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P24(value) (PIO_PUDR_P24_Msk & ((value) << PIO_PUDR_P24_Pos)) +#define PIO_PUDR_P25_Pos _U_(25) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P25_Msk (_U_(0x1) << PIO_PUDR_P25_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P25(value) (PIO_PUDR_P25_Msk & ((value) << PIO_PUDR_P25_Pos)) +#define PIO_PUDR_P26_Pos _U_(26) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P26_Msk (_U_(0x1) << PIO_PUDR_P26_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P26(value) (PIO_PUDR_P26_Msk & ((value) << PIO_PUDR_P26_Pos)) +#define PIO_PUDR_P27_Pos _U_(27) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P27_Msk (_U_(0x1) << PIO_PUDR_P27_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P27(value) (PIO_PUDR_P27_Msk & ((value) << PIO_PUDR_P27_Pos)) +#define PIO_PUDR_P28_Pos _U_(28) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P28_Msk (_U_(0x1) << PIO_PUDR_P28_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P28(value) (PIO_PUDR_P28_Msk & ((value) << PIO_PUDR_P28_Pos)) +#define PIO_PUDR_P29_Pos _U_(29) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P29_Msk (_U_(0x1) << PIO_PUDR_P29_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P29(value) (PIO_PUDR_P29_Msk & ((value) << PIO_PUDR_P29_Pos)) +#define PIO_PUDR_P30_Pos _U_(30) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P30_Msk (_U_(0x1) << PIO_PUDR_P30_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P30(value) (PIO_PUDR_P30_Msk & ((value) << PIO_PUDR_P30_Pos)) +#define PIO_PUDR_P31_Pos _U_(31) /**< (PIO_PUDR) Pull-Up Disable Position */ +#define PIO_PUDR_P31_Msk (_U_(0x1) << PIO_PUDR_P31_Pos) /**< (PIO_PUDR) Pull-Up Disable Mask */ +#define PIO_PUDR_P31(value) (PIO_PUDR_P31_Msk & ((value) << PIO_PUDR_P31_Pos)) +#define PIO_PUDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUDR) Register Mask */ + +#define PIO_PUDR_P_Pos _U_(0) /**< (PIO_PUDR Position) Pull-Up Disable */ +#define PIO_PUDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUDR_P_Pos) /**< (PIO_PUDR Mask) P */ +#define PIO_PUDR_P(value) (PIO_PUDR_P_Msk & ((value) << PIO_PUDR_P_Pos)) + +/* -------- PIO_PUER : (PIO Offset: 0x64) ( /W 32) Pull-up Enable Register -------- */ +#define PIO_PUER_P0_Pos _U_(0) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P0_Msk (_U_(0x1) << PIO_PUER_P0_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P0(value) (PIO_PUER_P0_Msk & ((value) << PIO_PUER_P0_Pos)) +#define PIO_PUER_P1_Pos _U_(1) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P1_Msk (_U_(0x1) << PIO_PUER_P1_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P1(value) (PIO_PUER_P1_Msk & ((value) << PIO_PUER_P1_Pos)) +#define PIO_PUER_P2_Pos _U_(2) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P2_Msk (_U_(0x1) << PIO_PUER_P2_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P2(value) (PIO_PUER_P2_Msk & ((value) << PIO_PUER_P2_Pos)) +#define PIO_PUER_P3_Pos _U_(3) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P3_Msk (_U_(0x1) << PIO_PUER_P3_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P3(value) (PIO_PUER_P3_Msk & ((value) << PIO_PUER_P3_Pos)) +#define PIO_PUER_P4_Pos _U_(4) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P4_Msk (_U_(0x1) << PIO_PUER_P4_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P4(value) (PIO_PUER_P4_Msk & ((value) << PIO_PUER_P4_Pos)) +#define PIO_PUER_P5_Pos _U_(5) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P5_Msk (_U_(0x1) << PIO_PUER_P5_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P5(value) (PIO_PUER_P5_Msk & ((value) << PIO_PUER_P5_Pos)) +#define PIO_PUER_P6_Pos _U_(6) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P6_Msk (_U_(0x1) << PIO_PUER_P6_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P6(value) (PIO_PUER_P6_Msk & ((value) << PIO_PUER_P6_Pos)) +#define PIO_PUER_P7_Pos _U_(7) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P7_Msk (_U_(0x1) << PIO_PUER_P7_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P7(value) (PIO_PUER_P7_Msk & ((value) << PIO_PUER_P7_Pos)) +#define PIO_PUER_P8_Pos _U_(8) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P8_Msk (_U_(0x1) << PIO_PUER_P8_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P8(value) (PIO_PUER_P8_Msk & ((value) << PIO_PUER_P8_Pos)) +#define PIO_PUER_P9_Pos _U_(9) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P9_Msk (_U_(0x1) << PIO_PUER_P9_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P9(value) (PIO_PUER_P9_Msk & ((value) << PIO_PUER_P9_Pos)) +#define PIO_PUER_P10_Pos _U_(10) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P10_Msk (_U_(0x1) << PIO_PUER_P10_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P10(value) (PIO_PUER_P10_Msk & ((value) << PIO_PUER_P10_Pos)) +#define PIO_PUER_P11_Pos _U_(11) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P11_Msk (_U_(0x1) << PIO_PUER_P11_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P11(value) (PIO_PUER_P11_Msk & ((value) << PIO_PUER_P11_Pos)) +#define PIO_PUER_P12_Pos _U_(12) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P12_Msk (_U_(0x1) << PIO_PUER_P12_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P12(value) (PIO_PUER_P12_Msk & ((value) << PIO_PUER_P12_Pos)) +#define PIO_PUER_P13_Pos _U_(13) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P13_Msk (_U_(0x1) << PIO_PUER_P13_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P13(value) (PIO_PUER_P13_Msk & ((value) << PIO_PUER_P13_Pos)) +#define PIO_PUER_P14_Pos _U_(14) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P14_Msk (_U_(0x1) << PIO_PUER_P14_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P14(value) (PIO_PUER_P14_Msk & ((value) << PIO_PUER_P14_Pos)) +#define PIO_PUER_P15_Pos _U_(15) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P15_Msk (_U_(0x1) << PIO_PUER_P15_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P15(value) (PIO_PUER_P15_Msk & ((value) << PIO_PUER_P15_Pos)) +#define PIO_PUER_P16_Pos _U_(16) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P16_Msk (_U_(0x1) << PIO_PUER_P16_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P16(value) (PIO_PUER_P16_Msk & ((value) << PIO_PUER_P16_Pos)) +#define PIO_PUER_P17_Pos _U_(17) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P17_Msk (_U_(0x1) << PIO_PUER_P17_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P17(value) (PIO_PUER_P17_Msk & ((value) << PIO_PUER_P17_Pos)) +#define PIO_PUER_P18_Pos _U_(18) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P18_Msk (_U_(0x1) << PIO_PUER_P18_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P18(value) (PIO_PUER_P18_Msk & ((value) << PIO_PUER_P18_Pos)) +#define PIO_PUER_P19_Pos _U_(19) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P19_Msk (_U_(0x1) << PIO_PUER_P19_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P19(value) (PIO_PUER_P19_Msk & ((value) << PIO_PUER_P19_Pos)) +#define PIO_PUER_P20_Pos _U_(20) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P20_Msk (_U_(0x1) << PIO_PUER_P20_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P20(value) (PIO_PUER_P20_Msk & ((value) << PIO_PUER_P20_Pos)) +#define PIO_PUER_P21_Pos _U_(21) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P21_Msk (_U_(0x1) << PIO_PUER_P21_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P21(value) (PIO_PUER_P21_Msk & ((value) << PIO_PUER_P21_Pos)) +#define PIO_PUER_P22_Pos _U_(22) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P22_Msk (_U_(0x1) << PIO_PUER_P22_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P22(value) (PIO_PUER_P22_Msk & ((value) << PIO_PUER_P22_Pos)) +#define PIO_PUER_P23_Pos _U_(23) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P23_Msk (_U_(0x1) << PIO_PUER_P23_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P23(value) (PIO_PUER_P23_Msk & ((value) << PIO_PUER_P23_Pos)) +#define PIO_PUER_P24_Pos _U_(24) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P24_Msk (_U_(0x1) << PIO_PUER_P24_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P24(value) (PIO_PUER_P24_Msk & ((value) << PIO_PUER_P24_Pos)) +#define PIO_PUER_P25_Pos _U_(25) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P25_Msk (_U_(0x1) << PIO_PUER_P25_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P25(value) (PIO_PUER_P25_Msk & ((value) << PIO_PUER_P25_Pos)) +#define PIO_PUER_P26_Pos _U_(26) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P26_Msk (_U_(0x1) << PIO_PUER_P26_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P26(value) (PIO_PUER_P26_Msk & ((value) << PIO_PUER_P26_Pos)) +#define PIO_PUER_P27_Pos _U_(27) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P27_Msk (_U_(0x1) << PIO_PUER_P27_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P27(value) (PIO_PUER_P27_Msk & ((value) << PIO_PUER_P27_Pos)) +#define PIO_PUER_P28_Pos _U_(28) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P28_Msk (_U_(0x1) << PIO_PUER_P28_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P28(value) (PIO_PUER_P28_Msk & ((value) << PIO_PUER_P28_Pos)) +#define PIO_PUER_P29_Pos _U_(29) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P29_Msk (_U_(0x1) << PIO_PUER_P29_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P29(value) (PIO_PUER_P29_Msk & ((value) << PIO_PUER_P29_Pos)) +#define PIO_PUER_P30_Pos _U_(30) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P30_Msk (_U_(0x1) << PIO_PUER_P30_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P30(value) (PIO_PUER_P30_Msk & ((value) << PIO_PUER_P30_Pos)) +#define PIO_PUER_P31_Pos _U_(31) /**< (PIO_PUER) Pull-Up Enable Position */ +#define PIO_PUER_P31_Msk (_U_(0x1) << PIO_PUER_P31_Pos) /**< (PIO_PUER) Pull-Up Enable Mask */ +#define PIO_PUER_P31(value) (PIO_PUER_P31_Msk & ((value) << PIO_PUER_P31_Pos)) +#define PIO_PUER_Msk _U_(0xFFFFFFFF) /**< (PIO_PUER) Register Mask */ + +#define PIO_PUER_P_Pos _U_(0) /**< (PIO_PUER Position) Pull-Up Enable */ +#define PIO_PUER_P_Msk (_U_(0xFFFFFFFF) << PIO_PUER_P_Pos) /**< (PIO_PUER Mask) P */ +#define PIO_PUER_P(value) (PIO_PUER_P_Msk & ((value) << PIO_PUER_P_Pos)) + +/* -------- PIO_PUSR : (PIO Offset: 0x68) ( R/ 32) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0_Pos _U_(0) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P0_Msk (_U_(0x1) << PIO_PUSR_P0_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P0(value) (PIO_PUSR_P0_Msk & ((value) << PIO_PUSR_P0_Pos)) +#define PIO_PUSR_P1_Pos _U_(1) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P1_Msk (_U_(0x1) << PIO_PUSR_P1_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P1(value) (PIO_PUSR_P1_Msk & ((value) << PIO_PUSR_P1_Pos)) +#define PIO_PUSR_P2_Pos _U_(2) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P2_Msk (_U_(0x1) << PIO_PUSR_P2_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P2(value) (PIO_PUSR_P2_Msk & ((value) << PIO_PUSR_P2_Pos)) +#define PIO_PUSR_P3_Pos _U_(3) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P3_Msk (_U_(0x1) << PIO_PUSR_P3_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P3(value) (PIO_PUSR_P3_Msk & ((value) << PIO_PUSR_P3_Pos)) +#define PIO_PUSR_P4_Pos _U_(4) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P4_Msk (_U_(0x1) << PIO_PUSR_P4_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P4(value) (PIO_PUSR_P4_Msk & ((value) << PIO_PUSR_P4_Pos)) +#define PIO_PUSR_P5_Pos _U_(5) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P5_Msk (_U_(0x1) << PIO_PUSR_P5_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P5(value) (PIO_PUSR_P5_Msk & ((value) << PIO_PUSR_P5_Pos)) +#define PIO_PUSR_P6_Pos _U_(6) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P6_Msk (_U_(0x1) << PIO_PUSR_P6_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P6(value) (PIO_PUSR_P6_Msk & ((value) << PIO_PUSR_P6_Pos)) +#define PIO_PUSR_P7_Pos _U_(7) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P7_Msk (_U_(0x1) << PIO_PUSR_P7_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P7(value) (PIO_PUSR_P7_Msk & ((value) << PIO_PUSR_P7_Pos)) +#define PIO_PUSR_P8_Pos _U_(8) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P8_Msk (_U_(0x1) << PIO_PUSR_P8_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P8(value) (PIO_PUSR_P8_Msk & ((value) << PIO_PUSR_P8_Pos)) +#define PIO_PUSR_P9_Pos _U_(9) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P9_Msk (_U_(0x1) << PIO_PUSR_P9_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P9(value) (PIO_PUSR_P9_Msk & ((value) << PIO_PUSR_P9_Pos)) +#define PIO_PUSR_P10_Pos _U_(10) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P10_Msk (_U_(0x1) << PIO_PUSR_P10_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P10(value) (PIO_PUSR_P10_Msk & ((value) << PIO_PUSR_P10_Pos)) +#define PIO_PUSR_P11_Pos _U_(11) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P11_Msk (_U_(0x1) << PIO_PUSR_P11_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P11(value) (PIO_PUSR_P11_Msk & ((value) << PIO_PUSR_P11_Pos)) +#define PIO_PUSR_P12_Pos _U_(12) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P12_Msk (_U_(0x1) << PIO_PUSR_P12_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P12(value) (PIO_PUSR_P12_Msk & ((value) << PIO_PUSR_P12_Pos)) +#define PIO_PUSR_P13_Pos _U_(13) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P13_Msk (_U_(0x1) << PIO_PUSR_P13_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P13(value) (PIO_PUSR_P13_Msk & ((value) << PIO_PUSR_P13_Pos)) +#define PIO_PUSR_P14_Pos _U_(14) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P14_Msk (_U_(0x1) << PIO_PUSR_P14_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P14(value) (PIO_PUSR_P14_Msk & ((value) << PIO_PUSR_P14_Pos)) +#define PIO_PUSR_P15_Pos _U_(15) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P15_Msk (_U_(0x1) << PIO_PUSR_P15_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P15(value) (PIO_PUSR_P15_Msk & ((value) << PIO_PUSR_P15_Pos)) +#define PIO_PUSR_P16_Pos _U_(16) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P16_Msk (_U_(0x1) << PIO_PUSR_P16_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P16(value) (PIO_PUSR_P16_Msk & ((value) << PIO_PUSR_P16_Pos)) +#define PIO_PUSR_P17_Pos _U_(17) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P17_Msk (_U_(0x1) << PIO_PUSR_P17_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P17(value) (PIO_PUSR_P17_Msk & ((value) << PIO_PUSR_P17_Pos)) +#define PIO_PUSR_P18_Pos _U_(18) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P18_Msk (_U_(0x1) << PIO_PUSR_P18_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P18(value) (PIO_PUSR_P18_Msk & ((value) << PIO_PUSR_P18_Pos)) +#define PIO_PUSR_P19_Pos _U_(19) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P19_Msk (_U_(0x1) << PIO_PUSR_P19_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P19(value) (PIO_PUSR_P19_Msk & ((value) << PIO_PUSR_P19_Pos)) +#define PIO_PUSR_P20_Pos _U_(20) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P20_Msk (_U_(0x1) << PIO_PUSR_P20_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P20(value) (PIO_PUSR_P20_Msk & ((value) << PIO_PUSR_P20_Pos)) +#define PIO_PUSR_P21_Pos _U_(21) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P21_Msk (_U_(0x1) << PIO_PUSR_P21_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P21(value) (PIO_PUSR_P21_Msk & ((value) << PIO_PUSR_P21_Pos)) +#define PIO_PUSR_P22_Pos _U_(22) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P22_Msk (_U_(0x1) << PIO_PUSR_P22_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P22(value) (PIO_PUSR_P22_Msk & ((value) << PIO_PUSR_P22_Pos)) +#define PIO_PUSR_P23_Pos _U_(23) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P23_Msk (_U_(0x1) << PIO_PUSR_P23_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P23(value) (PIO_PUSR_P23_Msk & ((value) << PIO_PUSR_P23_Pos)) +#define PIO_PUSR_P24_Pos _U_(24) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P24_Msk (_U_(0x1) << PIO_PUSR_P24_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P24(value) (PIO_PUSR_P24_Msk & ((value) << PIO_PUSR_P24_Pos)) +#define PIO_PUSR_P25_Pos _U_(25) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P25_Msk (_U_(0x1) << PIO_PUSR_P25_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P25(value) (PIO_PUSR_P25_Msk & ((value) << PIO_PUSR_P25_Pos)) +#define PIO_PUSR_P26_Pos _U_(26) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P26_Msk (_U_(0x1) << PIO_PUSR_P26_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P26(value) (PIO_PUSR_P26_Msk & ((value) << PIO_PUSR_P26_Pos)) +#define PIO_PUSR_P27_Pos _U_(27) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P27_Msk (_U_(0x1) << PIO_PUSR_P27_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P27(value) (PIO_PUSR_P27_Msk & ((value) << PIO_PUSR_P27_Pos)) +#define PIO_PUSR_P28_Pos _U_(28) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P28_Msk (_U_(0x1) << PIO_PUSR_P28_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P28(value) (PIO_PUSR_P28_Msk & ((value) << PIO_PUSR_P28_Pos)) +#define PIO_PUSR_P29_Pos _U_(29) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P29_Msk (_U_(0x1) << PIO_PUSR_P29_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P29(value) (PIO_PUSR_P29_Msk & ((value) << PIO_PUSR_P29_Pos)) +#define PIO_PUSR_P30_Pos _U_(30) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P30_Msk (_U_(0x1) << PIO_PUSR_P30_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P30(value) (PIO_PUSR_P30_Msk & ((value) << PIO_PUSR_P30_Pos)) +#define PIO_PUSR_P31_Pos _U_(31) /**< (PIO_PUSR) Pull-Up Status Position */ +#define PIO_PUSR_P31_Msk (_U_(0x1) << PIO_PUSR_P31_Pos) /**< (PIO_PUSR) Pull-Up Status Mask */ +#define PIO_PUSR_P31(value) (PIO_PUSR_P31_Msk & ((value) << PIO_PUSR_P31_Pos)) +#define PIO_PUSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PUSR) Register Mask */ + +#define PIO_PUSR_P_Pos _U_(0) /**< (PIO_PUSR Position) Pull-Up Status */ +#define PIO_PUSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PUSR_P_Pos) /**< (PIO_PUSR Mask) P */ +#define PIO_PUSR_P(value) (PIO_PUSR_P_Msk & ((value) << PIO_PUSR_P_Pos)) + +/* -------- PIO_ABCDSR : (PIO Offset: 0x70) (R/W 32) Peripheral ABCD Select Register 0 -------- */ +#define PIO_ABCDSR_P0_Pos _U_(0) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P0_Msk (_U_(0x1) << PIO_ABCDSR_P0_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P0(value) (PIO_ABCDSR_P0_Msk & ((value) << PIO_ABCDSR_P0_Pos)) +#define PIO_ABCDSR_P1_Pos _U_(1) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P1_Msk (_U_(0x1) << PIO_ABCDSR_P1_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P1(value) (PIO_ABCDSR_P1_Msk & ((value) << PIO_ABCDSR_P1_Pos)) +#define PIO_ABCDSR_P2_Pos _U_(2) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P2_Msk (_U_(0x1) << PIO_ABCDSR_P2_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P2(value) (PIO_ABCDSR_P2_Msk & ((value) << PIO_ABCDSR_P2_Pos)) +#define PIO_ABCDSR_P3_Pos _U_(3) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P3_Msk (_U_(0x1) << PIO_ABCDSR_P3_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P3(value) (PIO_ABCDSR_P3_Msk & ((value) << PIO_ABCDSR_P3_Pos)) +#define PIO_ABCDSR_P4_Pos _U_(4) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P4_Msk (_U_(0x1) << PIO_ABCDSR_P4_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P4(value) (PIO_ABCDSR_P4_Msk & ((value) << PIO_ABCDSR_P4_Pos)) +#define PIO_ABCDSR_P5_Pos _U_(5) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P5_Msk (_U_(0x1) << PIO_ABCDSR_P5_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P5(value) (PIO_ABCDSR_P5_Msk & ((value) << PIO_ABCDSR_P5_Pos)) +#define PIO_ABCDSR_P6_Pos _U_(6) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P6_Msk (_U_(0x1) << PIO_ABCDSR_P6_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P6(value) (PIO_ABCDSR_P6_Msk & ((value) << PIO_ABCDSR_P6_Pos)) +#define PIO_ABCDSR_P7_Pos _U_(7) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P7_Msk (_U_(0x1) << PIO_ABCDSR_P7_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P7(value) (PIO_ABCDSR_P7_Msk & ((value) << PIO_ABCDSR_P7_Pos)) +#define PIO_ABCDSR_P8_Pos _U_(8) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P8_Msk (_U_(0x1) << PIO_ABCDSR_P8_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P8(value) (PIO_ABCDSR_P8_Msk & ((value) << PIO_ABCDSR_P8_Pos)) +#define PIO_ABCDSR_P9_Pos _U_(9) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P9_Msk (_U_(0x1) << PIO_ABCDSR_P9_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P9(value) (PIO_ABCDSR_P9_Msk & ((value) << PIO_ABCDSR_P9_Pos)) +#define PIO_ABCDSR_P10_Pos _U_(10) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P10_Msk (_U_(0x1) << PIO_ABCDSR_P10_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P10(value) (PIO_ABCDSR_P10_Msk & ((value) << PIO_ABCDSR_P10_Pos)) +#define PIO_ABCDSR_P11_Pos _U_(11) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P11_Msk (_U_(0x1) << PIO_ABCDSR_P11_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P11(value) (PIO_ABCDSR_P11_Msk & ((value) << PIO_ABCDSR_P11_Pos)) +#define PIO_ABCDSR_P12_Pos _U_(12) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P12_Msk (_U_(0x1) << PIO_ABCDSR_P12_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P12(value) (PIO_ABCDSR_P12_Msk & ((value) << PIO_ABCDSR_P12_Pos)) +#define PIO_ABCDSR_P13_Pos _U_(13) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P13_Msk (_U_(0x1) << PIO_ABCDSR_P13_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P13(value) (PIO_ABCDSR_P13_Msk & ((value) << PIO_ABCDSR_P13_Pos)) +#define PIO_ABCDSR_P14_Pos _U_(14) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P14_Msk (_U_(0x1) << PIO_ABCDSR_P14_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P14(value) (PIO_ABCDSR_P14_Msk & ((value) << PIO_ABCDSR_P14_Pos)) +#define PIO_ABCDSR_P15_Pos _U_(15) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P15_Msk (_U_(0x1) << PIO_ABCDSR_P15_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P15(value) (PIO_ABCDSR_P15_Msk & ((value) << PIO_ABCDSR_P15_Pos)) +#define PIO_ABCDSR_P16_Pos _U_(16) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P16_Msk (_U_(0x1) << PIO_ABCDSR_P16_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P16(value) (PIO_ABCDSR_P16_Msk & ((value) << PIO_ABCDSR_P16_Pos)) +#define PIO_ABCDSR_P17_Pos _U_(17) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P17_Msk (_U_(0x1) << PIO_ABCDSR_P17_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P17(value) (PIO_ABCDSR_P17_Msk & ((value) << PIO_ABCDSR_P17_Pos)) +#define PIO_ABCDSR_P18_Pos _U_(18) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P18_Msk (_U_(0x1) << PIO_ABCDSR_P18_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P18(value) (PIO_ABCDSR_P18_Msk & ((value) << PIO_ABCDSR_P18_Pos)) +#define PIO_ABCDSR_P19_Pos _U_(19) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P19_Msk (_U_(0x1) << PIO_ABCDSR_P19_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P19(value) (PIO_ABCDSR_P19_Msk & ((value) << PIO_ABCDSR_P19_Pos)) +#define PIO_ABCDSR_P20_Pos _U_(20) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P20_Msk (_U_(0x1) << PIO_ABCDSR_P20_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P20(value) (PIO_ABCDSR_P20_Msk & ((value) << PIO_ABCDSR_P20_Pos)) +#define PIO_ABCDSR_P21_Pos _U_(21) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P21_Msk (_U_(0x1) << PIO_ABCDSR_P21_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P21(value) (PIO_ABCDSR_P21_Msk & ((value) << PIO_ABCDSR_P21_Pos)) +#define PIO_ABCDSR_P22_Pos _U_(22) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P22_Msk (_U_(0x1) << PIO_ABCDSR_P22_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P22(value) (PIO_ABCDSR_P22_Msk & ((value) << PIO_ABCDSR_P22_Pos)) +#define PIO_ABCDSR_P23_Pos _U_(23) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P23_Msk (_U_(0x1) << PIO_ABCDSR_P23_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P23(value) (PIO_ABCDSR_P23_Msk & ((value) << PIO_ABCDSR_P23_Pos)) +#define PIO_ABCDSR_P24_Pos _U_(24) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P24_Msk (_U_(0x1) << PIO_ABCDSR_P24_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P24(value) (PIO_ABCDSR_P24_Msk & ((value) << PIO_ABCDSR_P24_Pos)) +#define PIO_ABCDSR_P25_Pos _U_(25) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P25_Msk (_U_(0x1) << PIO_ABCDSR_P25_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P25(value) (PIO_ABCDSR_P25_Msk & ((value) << PIO_ABCDSR_P25_Pos)) +#define PIO_ABCDSR_P26_Pos _U_(26) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P26_Msk (_U_(0x1) << PIO_ABCDSR_P26_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P26(value) (PIO_ABCDSR_P26_Msk & ((value) << PIO_ABCDSR_P26_Pos)) +#define PIO_ABCDSR_P27_Pos _U_(27) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P27_Msk (_U_(0x1) << PIO_ABCDSR_P27_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P27(value) (PIO_ABCDSR_P27_Msk & ((value) << PIO_ABCDSR_P27_Pos)) +#define PIO_ABCDSR_P28_Pos _U_(28) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P28_Msk (_U_(0x1) << PIO_ABCDSR_P28_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P28(value) (PIO_ABCDSR_P28_Msk & ((value) << PIO_ABCDSR_P28_Pos)) +#define PIO_ABCDSR_P29_Pos _U_(29) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P29_Msk (_U_(0x1) << PIO_ABCDSR_P29_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P29(value) (PIO_ABCDSR_P29_Msk & ((value) << PIO_ABCDSR_P29_Pos)) +#define PIO_ABCDSR_P30_Pos _U_(30) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P30_Msk (_U_(0x1) << PIO_ABCDSR_P30_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P30(value) (PIO_ABCDSR_P30_Msk & ((value) << PIO_ABCDSR_P30_Pos)) +#define PIO_ABCDSR_P31_Pos _U_(31) /**< (PIO_ABCDSR) Peripheral Select Position */ +#define PIO_ABCDSR_P31_Msk (_U_(0x1) << PIO_ABCDSR_P31_Pos) /**< (PIO_ABCDSR) Peripheral Select Mask */ +#define PIO_ABCDSR_P31(value) (PIO_ABCDSR_P31_Msk & ((value) << PIO_ABCDSR_P31_Pos)) +#define PIO_ABCDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ABCDSR) Register Mask */ + +#define PIO_ABCDSR_P_Pos _U_(0) /**< (PIO_ABCDSR Position) Peripheral Select */ +#define PIO_ABCDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ABCDSR_P_Pos) /**< (PIO_ABCDSR Mask) P */ +#define PIO_ABCDSR_P(value) (PIO_ABCDSR_P_Msk & ((value) << PIO_ABCDSR_P_Pos)) + +/* -------- PIO_IFSCDR : (PIO Offset: 0x80) ( /W 32) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0_Pos _U_(0) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P0_Msk (_U_(0x1) << PIO_IFSCDR_P0_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P0(value) (PIO_IFSCDR_P0_Msk & ((value) << PIO_IFSCDR_P0_Pos)) +#define PIO_IFSCDR_P1_Pos _U_(1) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P1_Msk (_U_(0x1) << PIO_IFSCDR_P1_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P1(value) (PIO_IFSCDR_P1_Msk & ((value) << PIO_IFSCDR_P1_Pos)) +#define PIO_IFSCDR_P2_Pos _U_(2) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P2_Msk (_U_(0x1) << PIO_IFSCDR_P2_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P2(value) (PIO_IFSCDR_P2_Msk & ((value) << PIO_IFSCDR_P2_Pos)) +#define PIO_IFSCDR_P3_Pos _U_(3) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P3_Msk (_U_(0x1) << PIO_IFSCDR_P3_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P3(value) (PIO_IFSCDR_P3_Msk & ((value) << PIO_IFSCDR_P3_Pos)) +#define PIO_IFSCDR_P4_Pos _U_(4) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P4_Msk (_U_(0x1) << PIO_IFSCDR_P4_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P4(value) (PIO_IFSCDR_P4_Msk & ((value) << PIO_IFSCDR_P4_Pos)) +#define PIO_IFSCDR_P5_Pos _U_(5) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P5_Msk (_U_(0x1) << PIO_IFSCDR_P5_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P5(value) (PIO_IFSCDR_P5_Msk & ((value) << PIO_IFSCDR_P5_Pos)) +#define PIO_IFSCDR_P6_Pos _U_(6) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P6_Msk (_U_(0x1) << PIO_IFSCDR_P6_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P6(value) (PIO_IFSCDR_P6_Msk & ((value) << PIO_IFSCDR_P6_Pos)) +#define PIO_IFSCDR_P7_Pos _U_(7) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P7_Msk (_U_(0x1) << PIO_IFSCDR_P7_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P7(value) (PIO_IFSCDR_P7_Msk & ((value) << PIO_IFSCDR_P7_Pos)) +#define PIO_IFSCDR_P8_Pos _U_(8) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P8_Msk (_U_(0x1) << PIO_IFSCDR_P8_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P8(value) (PIO_IFSCDR_P8_Msk & ((value) << PIO_IFSCDR_P8_Pos)) +#define PIO_IFSCDR_P9_Pos _U_(9) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P9_Msk (_U_(0x1) << PIO_IFSCDR_P9_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P9(value) (PIO_IFSCDR_P9_Msk & ((value) << PIO_IFSCDR_P9_Pos)) +#define PIO_IFSCDR_P10_Pos _U_(10) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P10_Msk (_U_(0x1) << PIO_IFSCDR_P10_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P10(value) (PIO_IFSCDR_P10_Msk & ((value) << PIO_IFSCDR_P10_Pos)) +#define PIO_IFSCDR_P11_Pos _U_(11) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P11_Msk (_U_(0x1) << PIO_IFSCDR_P11_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P11(value) (PIO_IFSCDR_P11_Msk & ((value) << PIO_IFSCDR_P11_Pos)) +#define PIO_IFSCDR_P12_Pos _U_(12) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P12_Msk (_U_(0x1) << PIO_IFSCDR_P12_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P12(value) (PIO_IFSCDR_P12_Msk & ((value) << PIO_IFSCDR_P12_Pos)) +#define PIO_IFSCDR_P13_Pos _U_(13) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P13_Msk (_U_(0x1) << PIO_IFSCDR_P13_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P13(value) (PIO_IFSCDR_P13_Msk & ((value) << PIO_IFSCDR_P13_Pos)) +#define PIO_IFSCDR_P14_Pos _U_(14) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P14_Msk (_U_(0x1) << PIO_IFSCDR_P14_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P14(value) (PIO_IFSCDR_P14_Msk & ((value) << PIO_IFSCDR_P14_Pos)) +#define PIO_IFSCDR_P15_Pos _U_(15) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P15_Msk (_U_(0x1) << PIO_IFSCDR_P15_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P15(value) (PIO_IFSCDR_P15_Msk & ((value) << PIO_IFSCDR_P15_Pos)) +#define PIO_IFSCDR_P16_Pos _U_(16) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P16_Msk (_U_(0x1) << PIO_IFSCDR_P16_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P16(value) (PIO_IFSCDR_P16_Msk & ((value) << PIO_IFSCDR_P16_Pos)) +#define PIO_IFSCDR_P17_Pos _U_(17) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P17_Msk (_U_(0x1) << PIO_IFSCDR_P17_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P17(value) (PIO_IFSCDR_P17_Msk & ((value) << PIO_IFSCDR_P17_Pos)) +#define PIO_IFSCDR_P18_Pos _U_(18) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P18_Msk (_U_(0x1) << PIO_IFSCDR_P18_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P18(value) (PIO_IFSCDR_P18_Msk & ((value) << PIO_IFSCDR_P18_Pos)) +#define PIO_IFSCDR_P19_Pos _U_(19) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P19_Msk (_U_(0x1) << PIO_IFSCDR_P19_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P19(value) (PIO_IFSCDR_P19_Msk & ((value) << PIO_IFSCDR_P19_Pos)) +#define PIO_IFSCDR_P20_Pos _U_(20) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P20_Msk (_U_(0x1) << PIO_IFSCDR_P20_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P20(value) (PIO_IFSCDR_P20_Msk & ((value) << PIO_IFSCDR_P20_Pos)) +#define PIO_IFSCDR_P21_Pos _U_(21) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P21_Msk (_U_(0x1) << PIO_IFSCDR_P21_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P21(value) (PIO_IFSCDR_P21_Msk & ((value) << PIO_IFSCDR_P21_Pos)) +#define PIO_IFSCDR_P22_Pos _U_(22) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P22_Msk (_U_(0x1) << PIO_IFSCDR_P22_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P22(value) (PIO_IFSCDR_P22_Msk & ((value) << PIO_IFSCDR_P22_Pos)) +#define PIO_IFSCDR_P23_Pos _U_(23) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P23_Msk (_U_(0x1) << PIO_IFSCDR_P23_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P23(value) (PIO_IFSCDR_P23_Msk & ((value) << PIO_IFSCDR_P23_Pos)) +#define PIO_IFSCDR_P24_Pos _U_(24) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P24_Msk (_U_(0x1) << PIO_IFSCDR_P24_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P24(value) (PIO_IFSCDR_P24_Msk & ((value) << PIO_IFSCDR_P24_Pos)) +#define PIO_IFSCDR_P25_Pos _U_(25) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P25_Msk (_U_(0x1) << PIO_IFSCDR_P25_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P25(value) (PIO_IFSCDR_P25_Msk & ((value) << PIO_IFSCDR_P25_Pos)) +#define PIO_IFSCDR_P26_Pos _U_(26) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P26_Msk (_U_(0x1) << PIO_IFSCDR_P26_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P26(value) (PIO_IFSCDR_P26_Msk & ((value) << PIO_IFSCDR_P26_Pos)) +#define PIO_IFSCDR_P27_Pos _U_(27) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P27_Msk (_U_(0x1) << PIO_IFSCDR_P27_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P27(value) (PIO_IFSCDR_P27_Msk & ((value) << PIO_IFSCDR_P27_Pos)) +#define PIO_IFSCDR_P28_Pos _U_(28) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P28_Msk (_U_(0x1) << PIO_IFSCDR_P28_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P28(value) (PIO_IFSCDR_P28_Msk & ((value) << PIO_IFSCDR_P28_Pos)) +#define PIO_IFSCDR_P29_Pos _U_(29) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P29_Msk (_U_(0x1) << PIO_IFSCDR_P29_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P29(value) (PIO_IFSCDR_P29_Msk & ((value) << PIO_IFSCDR_P29_Pos)) +#define PIO_IFSCDR_P30_Pos _U_(30) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P30_Msk (_U_(0x1) << PIO_IFSCDR_P30_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P30(value) (PIO_IFSCDR_P30_Msk & ((value) << PIO_IFSCDR_P30_Pos)) +#define PIO_IFSCDR_P31_Pos _U_(31) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Position */ +#define PIO_IFSCDR_P31_Msk (_U_(0x1) << PIO_IFSCDR_P31_Pos) /**< (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select Mask */ +#define PIO_IFSCDR_P31(value) (PIO_IFSCDR_P31_Msk & ((value) << PIO_IFSCDR_P31_Pos)) +#define PIO_IFSCDR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCDR) Register Mask */ + +#define PIO_IFSCDR_P_Pos _U_(0) /**< (PIO_IFSCDR Position) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCDR_P_Pos) /**< (PIO_IFSCDR Mask) P */ +#define PIO_IFSCDR_P(value) (PIO_IFSCDR_P_Msk & ((value) << PIO_IFSCDR_P_Pos)) + +/* -------- PIO_IFSCER : (PIO Offset: 0x84) ( /W 32) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0_Pos _U_(0) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P0_Msk (_U_(0x1) << PIO_IFSCER_P0_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P0(value) (PIO_IFSCER_P0_Msk & ((value) << PIO_IFSCER_P0_Pos)) +#define PIO_IFSCER_P1_Pos _U_(1) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P1_Msk (_U_(0x1) << PIO_IFSCER_P1_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P1(value) (PIO_IFSCER_P1_Msk & ((value) << PIO_IFSCER_P1_Pos)) +#define PIO_IFSCER_P2_Pos _U_(2) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P2_Msk (_U_(0x1) << PIO_IFSCER_P2_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P2(value) (PIO_IFSCER_P2_Msk & ((value) << PIO_IFSCER_P2_Pos)) +#define PIO_IFSCER_P3_Pos _U_(3) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P3_Msk (_U_(0x1) << PIO_IFSCER_P3_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P3(value) (PIO_IFSCER_P3_Msk & ((value) << PIO_IFSCER_P3_Pos)) +#define PIO_IFSCER_P4_Pos _U_(4) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P4_Msk (_U_(0x1) << PIO_IFSCER_P4_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P4(value) (PIO_IFSCER_P4_Msk & ((value) << PIO_IFSCER_P4_Pos)) +#define PIO_IFSCER_P5_Pos _U_(5) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P5_Msk (_U_(0x1) << PIO_IFSCER_P5_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P5(value) (PIO_IFSCER_P5_Msk & ((value) << PIO_IFSCER_P5_Pos)) +#define PIO_IFSCER_P6_Pos _U_(6) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P6_Msk (_U_(0x1) << PIO_IFSCER_P6_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P6(value) (PIO_IFSCER_P6_Msk & ((value) << PIO_IFSCER_P6_Pos)) +#define PIO_IFSCER_P7_Pos _U_(7) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P7_Msk (_U_(0x1) << PIO_IFSCER_P7_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P7(value) (PIO_IFSCER_P7_Msk & ((value) << PIO_IFSCER_P7_Pos)) +#define PIO_IFSCER_P8_Pos _U_(8) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P8_Msk (_U_(0x1) << PIO_IFSCER_P8_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P8(value) (PIO_IFSCER_P8_Msk & ((value) << PIO_IFSCER_P8_Pos)) +#define PIO_IFSCER_P9_Pos _U_(9) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P9_Msk (_U_(0x1) << PIO_IFSCER_P9_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P9(value) (PIO_IFSCER_P9_Msk & ((value) << PIO_IFSCER_P9_Pos)) +#define PIO_IFSCER_P10_Pos _U_(10) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P10_Msk (_U_(0x1) << PIO_IFSCER_P10_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P10(value) (PIO_IFSCER_P10_Msk & ((value) << PIO_IFSCER_P10_Pos)) +#define PIO_IFSCER_P11_Pos _U_(11) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P11_Msk (_U_(0x1) << PIO_IFSCER_P11_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P11(value) (PIO_IFSCER_P11_Msk & ((value) << PIO_IFSCER_P11_Pos)) +#define PIO_IFSCER_P12_Pos _U_(12) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P12_Msk (_U_(0x1) << PIO_IFSCER_P12_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P12(value) (PIO_IFSCER_P12_Msk & ((value) << PIO_IFSCER_P12_Pos)) +#define PIO_IFSCER_P13_Pos _U_(13) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P13_Msk (_U_(0x1) << PIO_IFSCER_P13_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P13(value) (PIO_IFSCER_P13_Msk & ((value) << PIO_IFSCER_P13_Pos)) +#define PIO_IFSCER_P14_Pos _U_(14) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P14_Msk (_U_(0x1) << PIO_IFSCER_P14_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P14(value) (PIO_IFSCER_P14_Msk & ((value) << PIO_IFSCER_P14_Pos)) +#define PIO_IFSCER_P15_Pos _U_(15) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P15_Msk (_U_(0x1) << PIO_IFSCER_P15_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P15(value) (PIO_IFSCER_P15_Msk & ((value) << PIO_IFSCER_P15_Pos)) +#define PIO_IFSCER_P16_Pos _U_(16) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P16_Msk (_U_(0x1) << PIO_IFSCER_P16_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P16(value) (PIO_IFSCER_P16_Msk & ((value) << PIO_IFSCER_P16_Pos)) +#define PIO_IFSCER_P17_Pos _U_(17) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P17_Msk (_U_(0x1) << PIO_IFSCER_P17_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P17(value) (PIO_IFSCER_P17_Msk & ((value) << PIO_IFSCER_P17_Pos)) +#define PIO_IFSCER_P18_Pos _U_(18) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P18_Msk (_U_(0x1) << PIO_IFSCER_P18_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P18(value) (PIO_IFSCER_P18_Msk & ((value) << PIO_IFSCER_P18_Pos)) +#define PIO_IFSCER_P19_Pos _U_(19) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P19_Msk (_U_(0x1) << PIO_IFSCER_P19_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P19(value) (PIO_IFSCER_P19_Msk & ((value) << PIO_IFSCER_P19_Pos)) +#define PIO_IFSCER_P20_Pos _U_(20) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P20_Msk (_U_(0x1) << PIO_IFSCER_P20_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P20(value) (PIO_IFSCER_P20_Msk & ((value) << PIO_IFSCER_P20_Pos)) +#define PIO_IFSCER_P21_Pos _U_(21) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P21_Msk (_U_(0x1) << PIO_IFSCER_P21_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P21(value) (PIO_IFSCER_P21_Msk & ((value) << PIO_IFSCER_P21_Pos)) +#define PIO_IFSCER_P22_Pos _U_(22) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P22_Msk (_U_(0x1) << PIO_IFSCER_P22_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P22(value) (PIO_IFSCER_P22_Msk & ((value) << PIO_IFSCER_P22_Pos)) +#define PIO_IFSCER_P23_Pos _U_(23) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P23_Msk (_U_(0x1) << PIO_IFSCER_P23_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P23(value) (PIO_IFSCER_P23_Msk & ((value) << PIO_IFSCER_P23_Pos)) +#define PIO_IFSCER_P24_Pos _U_(24) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P24_Msk (_U_(0x1) << PIO_IFSCER_P24_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P24(value) (PIO_IFSCER_P24_Msk & ((value) << PIO_IFSCER_P24_Pos)) +#define PIO_IFSCER_P25_Pos _U_(25) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P25_Msk (_U_(0x1) << PIO_IFSCER_P25_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P25(value) (PIO_IFSCER_P25_Msk & ((value) << PIO_IFSCER_P25_Pos)) +#define PIO_IFSCER_P26_Pos _U_(26) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P26_Msk (_U_(0x1) << PIO_IFSCER_P26_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P26(value) (PIO_IFSCER_P26_Msk & ((value) << PIO_IFSCER_P26_Pos)) +#define PIO_IFSCER_P27_Pos _U_(27) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P27_Msk (_U_(0x1) << PIO_IFSCER_P27_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P27(value) (PIO_IFSCER_P27_Msk & ((value) << PIO_IFSCER_P27_Pos)) +#define PIO_IFSCER_P28_Pos _U_(28) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P28_Msk (_U_(0x1) << PIO_IFSCER_P28_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P28(value) (PIO_IFSCER_P28_Msk & ((value) << PIO_IFSCER_P28_Pos)) +#define PIO_IFSCER_P29_Pos _U_(29) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P29_Msk (_U_(0x1) << PIO_IFSCER_P29_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P29(value) (PIO_IFSCER_P29_Msk & ((value) << PIO_IFSCER_P29_Pos)) +#define PIO_IFSCER_P30_Pos _U_(30) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P30_Msk (_U_(0x1) << PIO_IFSCER_P30_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P30(value) (PIO_IFSCER_P30_Msk & ((value) << PIO_IFSCER_P30_Pos)) +#define PIO_IFSCER_P31_Pos _U_(31) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Position */ +#define PIO_IFSCER_P31_Msk (_U_(0x1) << PIO_IFSCER_P31_Pos) /**< (PIO_IFSCER) Slow Clock Debouncing Filtering Select Mask */ +#define PIO_IFSCER_P31(value) (PIO_IFSCER_P31_Msk & ((value) << PIO_IFSCER_P31_Pos)) +#define PIO_IFSCER_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCER) Register Mask */ + +#define PIO_IFSCER_P_Pos _U_(0) /**< (PIO_IFSCER Position) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCER_P_Pos) /**< (PIO_IFSCER Mask) P */ +#define PIO_IFSCER_P(value) (PIO_IFSCER_P_Msk & ((value) << PIO_IFSCER_P_Pos)) + +/* -------- PIO_IFSCSR : (PIO Offset: 0x88) ( R/ 32) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0_Pos _U_(0) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P0_Msk (_U_(0x1) << PIO_IFSCSR_P0_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P0(value) (PIO_IFSCSR_P0_Msk & ((value) << PIO_IFSCSR_P0_Pos)) +#define PIO_IFSCSR_P1_Pos _U_(1) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P1_Msk (_U_(0x1) << PIO_IFSCSR_P1_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P1(value) (PIO_IFSCSR_P1_Msk & ((value) << PIO_IFSCSR_P1_Pos)) +#define PIO_IFSCSR_P2_Pos _U_(2) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P2_Msk (_U_(0x1) << PIO_IFSCSR_P2_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P2(value) (PIO_IFSCSR_P2_Msk & ((value) << PIO_IFSCSR_P2_Pos)) +#define PIO_IFSCSR_P3_Pos _U_(3) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P3_Msk (_U_(0x1) << PIO_IFSCSR_P3_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P3(value) (PIO_IFSCSR_P3_Msk & ((value) << PIO_IFSCSR_P3_Pos)) +#define PIO_IFSCSR_P4_Pos _U_(4) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P4_Msk (_U_(0x1) << PIO_IFSCSR_P4_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P4(value) (PIO_IFSCSR_P4_Msk & ((value) << PIO_IFSCSR_P4_Pos)) +#define PIO_IFSCSR_P5_Pos _U_(5) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P5_Msk (_U_(0x1) << PIO_IFSCSR_P5_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P5(value) (PIO_IFSCSR_P5_Msk & ((value) << PIO_IFSCSR_P5_Pos)) +#define PIO_IFSCSR_P6_Pos _U_(6) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P6_Msk (_U_(0x1) << PIO_IFSCSR_P6_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P6(value) (PIO_IFSCSR_P6_Msk & ((value) << PIO_IFSCSR_P6_Pos)) +#define PIO_IFSCSR_P7_Pos _U_(7) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P7_Msk (_U_(0x1) << PIO_IFSCSR_P7_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P7(value) (PIO_IFSCSR_P7_Msk & ((value) << PIO_IFSCSR_P7_Pos)) +#define PIO_IFSCSR_P8_Pos _U_(8) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P8_Msk (_U_(0x1) << PIO_IFSCSR_P8_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P8(value) (PIO_IFSCSR_P8_Msk & ((value) << PIO_IFSCSR_P8_Pos)) +#define PIO_IFSCSR_P9_Pos _U_(9) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P9_Msk (_U_(0x1) << PIO_IFSCSR_P9_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P9(value) (PIO_IFSCSR_P9_Msk & ((value) << PIO_IFSCSR_P9_Pos)) +#define PIO_IFSCSR_P10_Pos _U_(10) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P10_Msk (_U_(0x1) << PIO_IFSCSR_P10_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P10(value) (PIO_IFSCSR_P10_Msk & ((value) << PIO_IFSCSR_P10_Pos)) +#define PIO_IFSCSR_P11_Pos _U_(11) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P11_Msk (_U_(0x1) << PIO_IFSCSR_P11_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P11(value) (PIO_IFSCSR_P11_Msk & ((value) << PIO_IFSCSR_P11_Pos)) +#define PIO_IFSCSR_P12_Pos _U_(12) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P12_Msk (_U_(0x1) << PIO_IFSCSR_P12_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P12(value) (PIO_IFSCSR_P12_Msk & ((value) << PIO_IFSCSR_P12_Pos)) +#define PIO_IFSCSR_P13_Pos _U_(13) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P13_Msk (_U_(0x1) << PIO_IFSCSR_P13_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P13(value) (PIO_IFSCSR_P13_Msk & ((value) << PIO_IFSCSR_P13_Pos)) +#define PIO_IFSCSR_P14_Pos _U_(14) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P14_Msk (_U_(0x1) << PIO_IFSCSR_P14_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P14(value) (PIO_IFSCSR_P14_Msk & ((value) << PIO_IFSCSR_P14_Pos)) +#define PIO_IFSCSR_P15_Pos _U_(15) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P15_Msk (_U_(0x1) << PIO_IFSCSR_P15_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P15(value) (PIO_IFSCSR_P15_Msk & ((value) << PIO_IFSCSR_P15_Pos)) +#define PIO_IFSCSR_P16_Pos _U_(16) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P16_Msk (_U_(0x1) << PIO_IFSCSR_P16_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P16(value) (PIO_IFSCSR_P16_Msk & ((value) << PIO_IFSCSR_P16_Pos)) +#define PIO_IFSCSR_P17_Pos _U_(17) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P17_Msk (_U_(0x1) << PIO_IFSCSR_P17_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P17(value) (PIO_IFSCSR_P17_Msk & ((value) << PIO_IFSCSR_P17_Pos)) +#define PIO_IFSCSR_P18_Pos _U_(18) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P18_Msk (_U_(0x1) << PIO_IFSCSR_P18_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P18(value) (PIO_IFSCSR_P18_Msk & ((value) << PIO_IFSCSR_P18_Pos)) +#define PIO_IFSCSR_P19_Pos _U_(19) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P19_Msk (_U_(0x1) << PIO_IFSCSR_P19_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P19(value) (PIO_IFSCSR_P19_Msk & ((value) << PIO_IFSCSR_P19_Pos)) +#define PIO_IFSCSR_P20_Pos _U_(20) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P20_Msk (_U_(0x1) << PIO_IFSCSR_P20_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P20(value) (PIO_IFSCSR_P20_Msk & ((value) << PIO_IFSCSR_P20_Pos)) +#define PIO_IFSCSR_P21_Pos _U_(21) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P21_Msk (_U_(0x1) << PIO_IFSCSR_P21_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P21(value) (PIO_IFSCSR_P21_Msk & ((value) << PIO_IFSCSR_P21_Pos)) +#define PIO_IFSCSR_P22_Pos _U_(22) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P22_Msk (_U_(0x1) << PIO_IFSCSR_P22_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P22(value) (PIO_IFSCSR_P22_Msk & ((value) << PIO_IFSCSR_P22_Pos)) +#define PIO_IFSCSR_P23_Pos _U_(23) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P23_Msk (_U_(0x1) << PIO_IFSCSR_P23_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P23(value) (PIO_IFSCSR_P23_Msk & ((value) << PIO_IFSCSR_P23_Pos)) +#define PIO_IFSCSR_P24_Pos _U_(24) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P24_Msk (_U_(0x1) << PIO_IFSCSR_P24_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P24(value) (PIO_IFSCSR_P24_Msk & ((value) << PIO_IFSCSR_P24_Pos)) +#define PIO_IFSCSR_P25_Pos _U_(25) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P25_Msk (_U_(0x1) << PIO_IFSCSR_P25_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P25(value) (PIO_IFSCSR_P25_Msk & ((value) << PIO_IFSCSR_P25_Pos)) +#define PIO_IFSCSR_P26_Pos _U_(26) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P26_Msk (_U_(0x1) << PIO_IFSCSR_P26_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P26(value) (PIO_IFSCSR_P26_Msk & ((value) << PIO_IFSCSR_P26_Pos)) +#define PIO_IFSCSR_P27_Pos _U_(27) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P27_Msk (_U_(0x1) << PIO_IFSCSR_P27_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P27(value) (PIO_IFSCSR_P27_Msk & ((value) << PIO_IFSCSR_P27_Pos)) +#define PIO_IFSCSR_P28_Pos _U_(28) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P28_Msk (_U_(0x1) << PIO_IFSCSR_P28_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P28(value) (PIO_IFSCSR_P28_Msk & ((value) << PIO_IFSCSR_P28_Pos)) +#define PIO_IFSCSR_P29_Pos _U_(29) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P29_Msk (_U_(0x1) << PIO_IFSCSR_P29_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P29(value) (PIO_IFSCSR_P29_Msk & ((value) << PIO_IFSCSR_P29_Pos)) +#define PIO_IFSCSR_P30_Pos _U_(30) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P30_Msk (_U_(0x1) << PIO_IFSCSR_P30_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P30(value) (PIO_IFSCSR_P30_Msk & ((value) << PIO_IFSCSR_P30_Pos)) +#define PIO_IFSCSR_P31_Pos _U_(31) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Position */ +#define PIO_IFSCSR_P31_Msk (_U_(0x1) << PIO_IFSCSR_P31_Pos) /**< (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status Mask */ +#define PIO_IFSCSR_P31(value) (PIO_IFSCSR_P31_Msk & ((value) << PIO_IFSCSR_P31_Pos)) +#define PIO_IFSCSR_Msk _U_(0xFFFFFFFF) /**< (PIO_IFSCSR) Register Mask */ + +#define PIO_IFSCSR_P_Pos _U_(0) /**< (PIO_IFSCSR Position) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P_Msk (_U_(0xFFFFFFFF) << PIO_IFSCSR_P_Pos) /**< (PIO_IFSCSR Mask) P */ +#define PIO_IFSCSR_P(value) (PIO_IFSCSR_P_Msk & ((value) << PIO_IFSCSR_P_Pos)) + +/* -------- PIO_SCDR : (PIO Offset: 0x8C) (R/W 32) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos _U_(0) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Position */ +#define PIO_SCDR_DIV_Msk (_U_(0x3FFF) << PIO_SCDR_DIV_Pos) /**< (PIO_SCDR) Slow Clock Divider Selection for Debouncing Mask */ +#define PIO_SCDR_DIV(value) (PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)) +#define PIO_SCDR_Msk _U_(0x00003FFF) /**< (PIO_SCDR) Register Mask */ + + +/* -------- PIO_PPDDR : (PIO Offset: 0x90) ( /W 32) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0_Pos _U_(0) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P0_Msk (_U_(0x1) << PIO_PPDDR_P0_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P0(value) (PIO_PPDDR_P0_Msk & ((value) << PIO_PPDDR_P0_Pos)) +#define PIO_PPDDR_P1_Pos _U_(1) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P1_Msk (_U_(0x1) << PIO_PPDDR_P1_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P1(value) (PIO_PPDDR_P1_Msk & ((value) << PIO_PPDDR_P1_Pos)) +#define PIO_PPDDR_P2_Pos _U_(2) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P2_Msk (_U_(0x1) << PIO_PPDDR_P2_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P2(value) (PIO_PPDDR_P2_Msk & ((value) << PIO_PPDDR_P2_Pos)) +#define PIO_PPDDR_P3_Pos _U_(3) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P3_Msk (_U_(0x1) << PIO_PPDDR_P3_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P3(value) (PIO_PPDDR_P3_Msk & ((value) << PIO_PPDDR_P3_Pos)) +#define PIO_PPDDR_P4_Pos _U_(4) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P4_Msk (_U_(0x1) << PIO_PPDDR_P4_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P4(value) (PIO_PPDDR_P4_Msk & ((value) << PIO_PPDDR_P4_Pos)) +#define PIO_PPDDR_P5_Pos _U_(5) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P5_Msk (_U_(0x1) << PIO_PPDDR_P5_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P5(value) (PIO_PPDDR_P5_Msk & ((value) << PIO_PPDDR_P5_Pos)) +#define PIO_PPDDR_P6_Pos _U_(6) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P6_Msk (_U_(0x1) << PIO_PPDDR_P6_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P6(value) (PIO_PPDDR_P6_Msk & ((value) << PIO_PPDDR_P6_Pos)) +#define PIO_PPDDR_P7_Pos _U_(7) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P7_Msk (_U_(0x1) << PIO_PPDDR_P7_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P7(value) (PIO_PPDDR_P7_Msk & ((value) << PIO_PPDDR_P7_Pos)) +#define PIO_PPDDR_P8_Pos _U_(8) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P8_Msk (_U_(0x1) << PIO_PPDDR_P8_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P8(value) (PIO_PPDDR_P8_Msk & ((value) << PIO_PPDDR_P8_Pos)) +#define PIO_PPDDR_P9_Pos _U_(9) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P9_Msk (_U_(0x1) << PIO_PPDDR_P9_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P9(value) (PIO_PPDDR_P9_Msk & ((value) << PIO_PPDDR_P9_Pos)) +#define PIO_PPDDR_P10_Pos _U_(10) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P10_Msk (_U_(0x1) << PIO_PPDDR_P10_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P10(value) (PIO_PPDDR_P10_Msk & ((value) << PIO_PPDDR_P10_Pos)) +#define PIO_PPDDR_P11_Pos _U_(11) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P11_Msk (_U_(0x1) << PIO_PPDDR_P11_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P11(value) (PIO_PPDDR_P11_Msk & ((value) << PIO_PPDDR_P11_Pos)) +#define PIO_PPDDR_P12_Pos _U_(12) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P12_Msk (_U_(0x1) << PIO_PPDDR_P12_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P12(value) (PIO_PPDDR_P12_Msk & ((value) << PIO_PPDDR_P12_Pos)) +#define PIO_PPDDR_P13_Pos _U_(13) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P13_Msk (_U_(0x1) << PIO_PPDDR_P13_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P13(value) (PIO_PPDDR_P13_Msk & ((value) << PIO_PPDDR_P13_Pos)) +#define PIO_PPDDR_P14_Pos _U_(14) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P14_Msk (_U_(0x1) << PIO_PPDDR_P14_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P14(value) (PIO_PPDDR_P14_Msk & ((value) << PIO_PPDDR_P14_Pos)) +#define PIO_PPDDR_P15_Pos _U_(15) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P15_Msk (_U_(0x1) << PIO_PPDDR_P15_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P15(value) (PIO_PPDDR_P15_Msk & ((value) << PIO_PPDDR_P15_Pos)) +#define PIO_PPDDR_P16_Pos _U_(16) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P16_Msk (_U_(0x1) << PIO_PPDDR_P16_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P16(value) (PIO_PPDDR_P16_Msk & ((value) << PIO_PPDDR_P16_Pos)) +#define PIO_PPDDR_P17_Pos _U_(17) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P17_Msk (_U_(0x1) << PIO_PPDDR_P17_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P17(value) (PIO_PPDDR_P17_Msk & ((value) << PIO_PPDDR_P17_Pos)) +#define PIO_PPDDR_P18_Pos _U_(18) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P18_Msk (_U_(0x1) << PIO_PPDDR_P18_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P18(value) (PIO_PPDDR_P18_Msk & ((value) << PIO_PPDDR_P18_Pos)) +#define PIO_PPDDR_P19_Pos _U_(19) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P19_Msk (_U_(0x1) << PIO_PPDDR_P19_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P19(value) (PIO_PPDDR_P19_Msk & ((value) << PIO_PPDDR_P19_Pos)) +#define PIO_PPDDR_P20_Pos _U_(20) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P20_Msk (_U_(0x1) << PIO_PPDDR_P20_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P20(value) (PIO_PPDDR_P20_Msk & ((value) << PIO_PPDDR_P20_Pos)) +#define PIO_PPDDR_P21_Pos _U_(21) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P21_Msk (_U_(0x1) << PIO_PPDDR_P21_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P21(value) (PIO_PPDDR_P21_Msk & ((value) << PIO_PPDDR_P21_Pos)) +#define PIO_PPDDR_P22_Pos _U_(22) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P22_Msk (_U_(0x1) << PIO_PPDDR_P22_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P22(value) (PIO_PPDDR_P22_Msk & ((value) << PIO_PPDDR_P22_Pos)) +#define PIO_PPDDR_P23_Pos _U_(23) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P23_Msk (_U_(0x1) << PIO_PPDDR_P23_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P23(value) (PIO_PPDDR_P23_Msk & ((value) << PIO_PPDDR_P23_Pos)) +#define PIO_PPDDR_P24_Pos _U_(24) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P24_Msk (_U_(0x1) << PIO_PPDDR_P24_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P24(value) (PIO_PPDDR_P24_Msk & ((value) << PIO_PPDDR_P24_Pos)) +#define PIO_PPDDR_P25_Pos _U_(25) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P25_Msk (_U_(0x1) << PIO_PPDDR_P25_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P25(value) (PIO_PPDDR_P25_Msk & ((value) << PIO_PPDDR_P25_Pos)) +#define PIO_PPDDR_P26_Pos _U_(26) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P26_Msk (_U_(0x1) << PIO_PPDDR_P26_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P26(value) (PIO_PPDDR_P26_Msk & ((value) << PIO_PPDDR_P26_Pos)) +#define PIO_PPDDR_P27_Pos _U_(27) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P27_Msk (_U_(0x1) << PIO_PPDDR_P27_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P27(value) (PIO_PPDDR_P27_Msk & ((value) << PIO_PPDDR_P27_Pos)) +#define PIO_PPDDR_P28_Pos _U_(28) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P28_Msk (_U_(0x1) << PIO_PPDDR_P28_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P28(value) (PIO_PPDDR_P28_Msk & ((value) << PIO_PPDDR_P28_Pos)) +#define PIO_PPDDR_P29_Pos _U_(29) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P29_Msk (_U_(0x1) << PIO_PPDDR_P29_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P29(value) (PIO_PPDDR_P29_Msk & ((value) << PIO_PPDDR_P29_Pos)) +#define PIO_PPDDR_P30_Pos _U_(30) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P30_Msk (_U_(0x1) << PIO_PPDDR_P30_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P30(value) (PIO_PPDDR_P30_Msk & ((value) << PIO_PPDDR_P30_Pos)) +#define PIO_PPDDR_P31_Pos _U_(31) /**< (PIO_PPDDR) Pull-Down Disable Position */ +#define PIO_PPDDR_P31_Msk (_U_(0x1) << PIO_PPDDR_P31_Pos) /**< (PIO_PPDDR) Pull-Down Disable Mask */ +#define PIO_PPDDR_P31(value) (PIO_PPDDR_P31_Msk & ((value) << PIO_PPDDR_P31_Pos)) +#define PIO_PPDDR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDDR) Register Mask */ + +#define PIO_PPDDR_P_Pos _U_(0) /**< (PIO_PPDDR Position) Pull-Down Disable */ +#define PIO_PPDDR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDDR_P_Pos) /**< (PIO_PPDDR Mask) P */ +#define PIO_PPDDR_P(value) (PIO_PPDDR_P_Msk & ((value) << PIO_PPDDR_P_Pos)) + +/* -------- PIO_PPDER : (PIO Offset: 0x94) ( /W 32) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0_Pos _U_(0) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P0_Msk (_U_(0x1) << PIO_PPDER_P0_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P0(value) (PIO_PPDER_P0_Msk & ((value) << PIO_PPDER_P0_Pos)) +#define PIO_PPDER_P1_Pos _U_(1) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P1_Msk (_U_(0x1) << PIO_PPDER_P1_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P1(value) (PIO_PPDER_P1_Msk & ((value) << PIO_PPDER_P1_Pos)) +#define PIO_PPDER_P2_Pos _U_(2) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P2_Msk (_U_(0x1) << PIO_PPDER_P2_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P2(value) (PIO_PPDER_P2_Msk & ((value) << PIO_PPDER_P2_Pos)) +#define PIO_PPDER_P3_Pos _U_(3) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P3_Msk (_U_(0x1) << PIO_PPDER_P3_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P3(value) (PIO_PPDER_P3_Msk & ((value) << PIO_PPDER_P3_Pos)) +#define PIO_PPDER_P4_Pos _U_(4) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P4_Msk (_U_(0x1) << PIO_PPDER_P4_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P4(value) (PIO_PPDER_P4_Msk & ((value) << PIO_PPDER_P4_Pos)) +#define PIO_PPDER_P5_Pos _U_(5) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P5_Msk (_U_(0x1) << PIO_PPDER_P5_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P5(value) (PIO_PPDER_P5_Msk & ((value) << PIO_PPDER_P5_Pos)) +#define PIO_PPDER_P6_Pos _U_(6) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P6_Msk (_U_(0x1) << PIO_PPDER_P6_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P6(value) (PIO_PPDER_P6_Msk & ((value) << PIO_PPDER_P6_Pos)) +#define PIO_PPDER_P7_Pos _U_(7) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P7_Msk (_U_(0x1) << PIO_PPDER_P7_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P7(value) (PIO_PPDER_P7_Msk & ((value) << PIO_PPDER_P7_Pos)) +#define PIO_PPDER_P8_Pos _U_(8) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P8_Msk (_U_(0x1) << PIO_PPDER_P8_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P8(value) (PIO_PPDER_P8_Msk & ((value) << PIO_PPDER_P8_Pos)) +#define PIO_PPDER_P9_Pos _U_(9) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P9_Msk (_U_(0x1) << PIO_PPDER_P9_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P9(value) (PIO_PPDER_P9_Msk & ((value) << PIO_PPDER_P9_Pos)) +#define PIO_PPDER_P10_Pos _U_(10) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P10_Msk (_U_(0x1) << PIO_PPDER_P10_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P10(value) (PIO_PPDER_P10_Msk & ((value) << PIO_PPDER_P10_Pos)) +#define PIO_PPDER_P11_Pos _U_(11) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P11_Msk (_U_(0x1) << PIO_PPDER_P11_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P11(value) (PIO_PPDER_P11_Msk & ((value) << PIO_PPDER_P11_Pos)) +#define PIO_PPDER_P12_Pos _U_(12) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P12_Msk (_U_(0x1) << PIO_PPDER_P12_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P12(value) (PIO_PPDER_P12_Msk & ((value) << PIO_PPDER_P12_Pos)) +#define PIO_PPDER_P13_Pos _U_(13) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P13_Msk (_U_(0x1) << PIO_PPDER_P13_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P13(value) (PIO_PPDER_P13_Msk & ((value) << PIO_PPDER_P13_Pos)) +#define PIO_PPDER_P14_Pos _U_(14) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P14_Msk (_U_(0x1) << PIO_PPDER_P14_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P14(value) (PIO_PPDER_P14_Msk & ((value) << PIO_PPDER_P14_Pos)) +#define PIO_PPDER_P15_Pos _U_(15) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P15_Msk (_U_(0x1) << PIO_PPDER_P15_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P15(value) (PIO_PPDER_P15_Msk & ((value) << PIO_PPDER_P15_Pos)) +#define PIO_PPDER_P16_Pos _U_(16) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P16_Msk (_U_(0x1) << PIO_PPDER_P16_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P16(value) (PIO_PPDER_P16_Msk & ((value) << PIO_PPDER_P16_Pos)) +#define PIO_PPDER_P17_Pos _U_(17) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P17_Msk (_U_(0x1) << PIO_PPDER_P17_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P17(value) (PIO_PPDER_P17_Msk & ((value) << PIO_PPDER_P17_Pos)) +#define PIO_PPDER_P18_Pos _U_(18) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P18_Msk (_U_(0x1) << PIO_PPDER_P18_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P18(value) (PIO_PPDER_P18_Msk & ((value) << PIO_PPDER_P18_Pos)) +#define PIO_PPDER_P19_Pos _U_(19) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P19_Msk (_U_(0x1) << PIO_PPDER_P19_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P19(value) (PIO_PPDER_P19_Msk & ((value) << PIO_PPDER_P19_Pos)) +#define PIO_PPDER_P20_Pos _U_(20) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P20_Msk (_U_(0x1) << PIO_PPDER_P20_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P20(value) (PIO_PPDER_P20_Msk & ((value) << PIO_PPDER_P20_Pos)) +#define PIO_PPDER_P21_Pos _U_(21) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P21_Msk (_U_(0x1) << PIO_PPDER_P21_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P21(value) (PIO_PPDER_P21_Msk & ((value) << PIO_PPDER_P21_Pos)) +#define PIO_PPDER_P22_Pos _U_(22) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P22_Msk (_U_(0x1) << PIO_PPDER_P22_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P22(value) (PIO_PPDER_P22_Msk & ((value) << PIO_PPDER_P22_Pos)) +#define PIO_PPDER_P23_Pos _U_(23) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P23_Msk (_U_(0x1) << PIO_PPDER_P23_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P23(value) (PIO_PPDER_P23_Msk & ((value) << PIO_PPDER_P23_Pos)) +#define PIO_PPDER_P24_Pos _U_(24) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P24_Msk (_U_(0x1) << PIO_PPDER_P24_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P24(value) (PIO_PPDER_P24_Msk & ((value) << PIO_PPDER_P24_Pos)) +#define PIO_PPDER_P25_Pos _U_(25) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P25_Msk (_U_(0x1) << PIO_PPDER_P25_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P25(value) (PIO_PPDER_P25_Msk & ((value) << PIO_PPDER_P25_Pos)) +#define PIO_PPDER_P26_Pos _U_(26) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P26_Msk (_U_(0x1) << PIO_PPDER_P26_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P26(value) (PIO_PPDER_P26_Msk & ((value) << PIO_PPDER_P26_Pos)) +#define PIO_PPDER_P27_Pos _U_(27) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P27_Msk (_U_(0x1) << PIO_PPDER_P27_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P27(value) (PIO_PPDER_P27_Msk & ((value) << PIO_PPDER_P27_Pos)) +#define PIO_PPDER_P28_Pos _U_(28) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P28_Msk (_U_(0x1) << PIO_PPDER_P28_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P28(value) (PIO_PPDER_P28_Msk & ((value) << PIO_PPDER_P28_Pos)) +#define PIO_PPDER_P29_Pos _U_(29) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P29_Msk (_U_(0x1) << PIO_PPDER_P29_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P29(value) (PIO_PPDER_P29_Msk & ((value) << PIO_PPDER_P29_Pos)) +#define PIO_PPDER_P30_Pos _U_(30) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P30_Msk (_U_(0x1) << PIO_PPDER_P30_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P30(value) (PIO_PPDER_P30_Msk & ((value) << PIO_PPDER_P30_Pos)) +#define PIO_PPDER_P31_Pos _U_(31) /**< (PIO_PPDER) Pull-Down Enable Position */ +#define PIO_PPDER_P31_Msk (_U_(0x1) << PIO_PPDER_P31_Pos) /**< (PIO_PPDER) Pull-Down Enable Mask */ +#define PIO_PPDER_P31(value) (PIO_PPDER_P31_Msk & ((value) << PIO_PPDER_P31_Pos)) +#define PIO_PPDER_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDER) Register Mask */ + +#define PIO_PPDER_P_Pos _U_(0) /**< (PIO_PPDER Position) Pull-Down Enable */ +#define PIO_PPDER_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDER_P_Pos) /**< (PIO_PPDER Mask) P */ +#define PIO_PPDER_P(value) (PIO_PPDER_P_Msk & ((value) << PIO_PPDER_P_Pos)) + +/* -------- PIO_PPDSR : (PIO Offset: 0x98) ( R/ 32) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0_Pos _U_(0) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P0_Msk (_U_(0x1) << PIO_PPDSR_P0_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P0(value) (PIO_PPDSR_P0_Msk & ((value) << PIO_PPDSR_P0_Pos)) +#define PIO_PPDSR_P1_Pos _U_(1) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P1_Msk (_U_(0x1) << PIO_PPDSR_P1_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P1(value) (PIO_PPDSR_P1_Msk & ((value) << PIO_PPDSR_P1_Pos)) +#define PIO_PPDSR_P2_Pos _U_(2) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P2_Msk (_U_(0x1) << PIO_PPDSR_P2_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P2(value) (PIO_PPDSR_P2_Msk & ((value) << PIO_PPDSR_P2_Pos)) +#define PIO_PPDSR_P3_Pos _U_(3) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P3_Msk (_U_(0x1) << PIO_PPDSR_P3_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P3(value) (PIO_PPDSR_P3_Msk & ((value) << PIO_PPDSR_P3_Pos)) +#define PIO_PPDSR_P4_Pos _U_(4) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P4_Msk (_U_(0x1) << PIO_PPDSR_P4_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P4(value) (PIO_PPDSR_P4_Msk & ((value) << PIO_PPDSR_P4_Pos)) +#define PIO_PPDSR_P5_Pos _U_(5) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P5_Msk (_U_(0x1) << PIO_PPDSR_P5_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P5(value) (PIO_PPDSR_P5_Msk & ((value) << PIO_PPDSR_P5_Pos)) +#define PIO_PPDSR_P6_Pos _U_(6) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P6_Msk (_U_(0x1) << PIO_PPDSR_P6_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P6(value) (PIO_PPDSR_P6_Msk & ((value) << PIO_PPDSR_P6_Pos)) +#define PIO_PPDSR_P7_Pos _U_(7) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P7_Msk (_U_(0x1) << PIO_PPDSR_P7_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P7(value) (PIO_PPDSR_P7_Msk & ((value) << PIO_PPDSR_P7_Pos)) +#define PIO_PPDSR_P8_Pos _U_(8) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P8_Msk (_U_(0x1) << PIO_PPDSR_P8_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P8(value) (PIO_PPDSR_P8_Msk & ((value) << PIO_PPDSR_P8_Pos)) +#define PIO_PPDSR_P9_Pos _U_(9) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P9_Msk (_U_(0x1) << PIO_PPDSR_P9_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P9(value) (PIO_PPDSR_P9_Msk & ((value) << PIO_PPDSR_P9_Pos)) +#define PIO_PPDSR_P10_Pos _U_(10) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P10_Msk (_U_(0x1) << PIO_PPDSR_P10_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P10(value) (PIO_PPDSR_P10_Msk & ((value) << PIO_PPDSR_P10_Pos)) +#define PIO_PPDSR_P11_Pos _U_(11) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P11_Msk (_U_(0x1) << PIO_PPDSR_P11_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P11(value) (PIO_PPDSR_P11_Msk & ((value) << PIO_PPDSR_P11_Pos)) +#define PIO_PPDSR_P12_Pos _U_(12) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P12_Msk (_U_(0x1) << PIO_PPDSR_P12_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P12(value) (PIO_PPDSR_P12_Msk & ((value) << PIO_PPDSR_P12_Pos)) +#define PIO_PPDSR_P13_Pos _U_(13) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P13_Msk (_U_(0x1) << PIO_PPDSR_P13_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P13(value) (PIO_PPDSR_P13_Msk & ((value) << PIO_PPDSR_P13_Pos)) +#define PIO_PPDSR_P14_Pos _U_(14) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P14_Msk (_U_(0x1) << PIO_PPDSR_P14_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P14(value) (PIO_PPDSR_P14_Msk & ((value) << PIO_PPDSR_P14_Pos)) +#define PIO_PPDSR_P15_Pos _U_(15) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P15_Msk (_U_(0x1) << PIO_PPDSR_P15_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P15(value) (PIO_PPDSR_P15_Msk & ((value) << PIO_PPDSR_P15_Pos)) +#define PIO_PPDSR_P16_Pos _U_(16) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P16_Msk (_U_(0x1) << PIO_PPDSR_P16_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P16(value) (PIO_PPDSR_P16_Msk & ((value) << PIO_PPDSR_P16_Pos)) +#define PIO_PPDSR_P17_Pos _U_(17) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P17_Msk (_U_(0x1) << PIO_PPDSR_P17_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P17(value) (PIO_PPDSR_P17_Msk & ((value) << PIO_PPDSR_P17_Pos)) +#define PIO_PPDSR_P18_Pos _U_(18) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P18_Msk (_U_(0x1) << PIO_PPDSR_P18_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P18(value) (PIO_PPDSR_P18_Msk & ((value) << PIO_PPDSR_P18_Pos)) +#define PIO_PPDSR_P19_Pos _U_(19) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P19_Msk (_U_(0x1) << PIO_PPDSR_P19_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P19(value) (PIO_PPDSR_P19_Msk & ((value) << PIO_PPDSR_P19_Pos)) +#define PIO_PPDSR_P20_Pos _U_(20) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P20_Msk (_U_(0x1) << PIO_PPDSR_P20_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P20(value) (PIO_PPDSR_P20_Msk & ((value) << PIO_PPDSR_P20_Pos)) +#define PIO_PPDSR_P21_Pos _U_(21) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P21_Msk (_U_(0x1) << PIO_PPDSR_P21_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P21(value) (PIO_PPDSR_P21_Msk & ((value) << PIO_PPDSR_P21_Pos)) +#define PIO_PPDSR_P22_Pos _U_(22) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P22_Msk (_U_(0x1) << PIO_PPDSR_P22_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P22(value) (PIO_PPDSR_P22_Msk & ((value) << PIO_PPDSR_P22_Pos)) +#define PIO_PPDSR_P23_Pos _U_(23) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P23_Msk (_U_(0x1) << PIO_PPDSR_P23_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P23(value) (PIO_PPDSR_P23_Msk & ((value) << PIO_PPDSR_P23_Pos)) +#define PIO_PPDSR_P24_Pos _U_(24) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P24_Msk (_U_(0x1) << PIO_PPDSR_P24_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P24(value) (PIO_PPDSR_P24_Msk & ((value) << PIO_PPDSR_P24_Pos)) +#define PIO_PPDSR_P25_Pos _U_(25) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P25_Msk (_U_(0x1) << PIO_PPDSR_P25_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P25(value) (PIO_PPDSR_P25_Msk & ((value) << PIO_PPDSR_P25_Pos)) +#define PIO_PPDSR_P26_Pos _U_(26) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P26_Msk (_U_(0x1) << PIO_PPDSR_P26_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P26(value) (PIO_PPDSR_P26_Msk & ((value) << PIO_PPDSR_P26_Pos)) +#define PIO_PPDSR_P27_Pos _U_(27) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P27_Msk (_U_(0x1) << PIO_PPDSR_P27_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P27(value) (PIO_PPDSR_P27_Msk & ((value) << PIO_PPDSR_P27_Pos)) +#define PIO_PPDSR_P28_Pos _U_(28) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P28_Msk (_U_(0x1) << PIO_PPDSR_P28_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P28(value) (PIO_PPDSR_P28_Msk & ((value) << PIO_PPDSR_P28_Pos)) +#define PIO_PPDSR_P29_Pos _U_(29) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P29_Msk (_U_(0x1) << PIO_PPDSR_P29_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P29(value) (PIO_PPDSR_P29_Msk & ((value) << PIO_PPDSR_P29_Pos)) +#define PIO_PPDSR_P30_Pos _U_(30) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P30_Msk (_U_(0x1) << PIO_PPDSR_P30_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P30(value) (PIO_PPDSR_P30_Msk & ((value) << PIO_PPDSR_P30_Pos)) +#define PIO_PPDSR_P31_Pos _U_(31) /**< (PIO_PPDSR) Pull-Down Status Position */ +#define PIO_PPDSR_P31_Msk (_U_(0x1) << PIO_PPDSR_P31_Pos) /**< (PIO_PPDSR) Pull-Down Status Mask */ +#define PIO_PPDSR_P31(value) (PIO_PPDSR_P31_Msk & ((value) << PIO_PPDSR_P31_Pos)) +#define PIO_PPDSR_Msk _U_(0xFFFFFFFF) /**< (PIO_PPDSR) Register Mask */ + +#define PIO_PPDSR_P_Pos _U_(0) /**< (PIO_PPDSR Position) Pull-Down Status */ +#define PIO_PPDSR_P_Msk (_U_(0xFFFFFFFF) << PIO_PPDSR_P_Pos) /**< (PIO_PPDSR Mask) P */ +#define PIO_PPDSR_P(value) (PIO_PPDSR_P_Msk & ((value) << PIO_PPDSR_P_Pos)) + +/* -------- PIO_OWER : (PIO Offset: 0xA0) ( /W 32) Output Write Enable -------- */ +#define PIO_OWER_P0_Pos _U_(0) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P0_Msk (_U_(0x1) << PIO_OWER_P0_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P0(value) (PIO_OWER_P0_Msk & ((value) << PIO_OWER_P0_Pos)) +#define PIO_OWER_P1_Pos _U_(1) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P1_Msk (_U_(0x1) << PIO_OWER_P1_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P1(value) (PIO_OWER_P1_Msk & ((value) << PIO_OWER_P1_Pos)) +#define PIO_OWER_P2_Pos _U_(2) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P2_Msk (_U_(0x1) << PIO_OWER_P2_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P2(value) (PIO_OWER_P2_Msk & ((value) << PIO_OWER_P2_Pos)) +#define PIO_OWER_P3_Pos _U_(3) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P3_Msk (_U_(0x1) << PIO_OWER_P3_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P3(value) (PIO_OWER_P3_Msk & ((value) << PIO_OWER_P3_Pos)) +#define PIO_OWER_P4_Pos _U_(4) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P4_Msk (_U_(0x1) << PIO_OWER_P4_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P4(value) (PIO_OWER_P4_Msk & ((value) << PIO_OWER_P4_Pos)) +#define PIO_OWER_P5_Pos _U_(5) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P5_Msk (_U_(0x1) << PIO_OWER_P5_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P5(value) (PIO_OWER_P5_Msk & ((value) << PIO_OWER_P5_Pos)) +#define PIO_OWER_P6_Pos _U_(6) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P6_Msk (_U_(0x1) << PIO_OWER_P6_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P6(value) (PIO_OWER_P6_Msk & ((value) << PIO_OWER_P6_Pos)) +#define PIO_OWER_P7_Pos _U_(7) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P7_Msk (_U_(0x1) << PIO_OWER_P7_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P7(value) (PIO_OWER_P7_Msk & ((value) << PIO_OWER_P7_Pos)) +#define PIO_OWER_P8_Pos _U_(8) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P8_Msk (_U_(0x1) << PIO_OWER_P8_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P8(value) (PIO_OWER_P8_Msk & ((value) << PIO_OWER_P8_Pos)) +#define PIO_OWER_P9_Pos _U_(9) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P9_Msk (_U_(0x1) << PIO_OWER_P9_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P9(value) (PIO_OWER_P9_Msk & ((value) << PIO_OWER_P9_Pos)) +#define PIO_OWER_P10_Pos _U_(10) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P10_Msk (_U_(0x1) << PIO_OWER_P10_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P10(value) (PIO_OWER_P10_Msk & ((value) << PIO_OWER_P10_Pos)) +#define PIO_OWER_P11_Pos _U_(11) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P11_Msk (_U_(0x1) << PIO_OWER_P11_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P11(value) (PIO_OWER_P11_Msk & ((value) << PIO_OWER_P11_Pos)) +#define PIO_OWER_P12_Pos _U_(12) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P12_Msk (_U_(0x1) << PIO_OWER_P12_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P12(value) (PIO_OWER_P12_Msk & ((value) << PIO_OWER_P12_Pos)) +#define PIO_OWER_P13_Pos _U_(13) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P13_Msk (_U_(0x1) << PIO_OWER_P13_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P13(value) (PIO_OWER_P13_Msk & ((value) << PIO_OWER_P13_Pos)) +#define PIO_OWER_P14_Pos _U_(14) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P14_Msk (_U_(0x1) << PIO_OWER_P14_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P14(value) (PIO_OWER_P14_Msk & ((value) << PIO_OWER_P14_Pos)) +#define PIO_OWER_P15_Pos _U_(15) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P15_Msk (_U_(0x1) << PIO_OWER_P15_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P15(value) (PIO_OWER_P15_Msk & ((value) << PIO_OWER_P15_Pos)) +#define PIO_OWER_P16_Pos _U_(16) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P16_Msk (_U_(0x1) << PIO_OWER_P16_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P16(value) (PIO_OWER_P16_Msk & ((value) << PIO_OWER_P16_Pos)) +#define PIO_OWER_P17_Pos _U_(17) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P17_Msk (_U_(0x1) << PIO_OWER_P17_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P17(value) (PIO_OWER_P17_Msk & ((value) << PIO_OWER_P17_Pos)) +#define PIO_OWER_P18_Pos _U_(18) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P18_Msk (_U_(0x1) << PIO_OWER_P18_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P18(value) (PIO_OWER_P18_Msk & ((value) << PIO_OWER_P18_Pos)) +#define PIO_OWER_P19_Pos _U_(19) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P19_Msk (_U_(0x1) << PIO_OWER_P19_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P19(value) (PIO_OWER_P19_Msk & ((value) << PIO_OWER_P19_Pos)) +#define PIO_OWER_P20_Pos _U_(20) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P20_Msk (_U_(0x1) << PIO_OWER_P20_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P20(value) (PIO_OWER_P20_Msk & ((value) << PIO_OWER_P20_Pos)) +#define PIO_OWER_P21_Pos _U_(21) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P21_Msk (_U_(0x1) << PIO_OWER_P21_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P21(value) (PIO_OWER_P21_Msk & ((value) << PIO_OWER_P21_Pos)) +#define PIO_OWER_P22_Pos _U_(22) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P22_Msk (_U_(0x1) << PIO_OWER_P22_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P22(value) (PIO_OWER_P22_Msk & ((value) << PIO_OWER_P22_Pos)) +#define PIO_OWER_P23_Pos _U_(23) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P23_Msk (_U_(0x1) << PIO_OWER_P23_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P23(value) (PIO_OWER_P23_Msk & ((value) << PIO_OWER_P23_Pos)) +#define PIO_OWER_P24_Pos _U_(24) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P24_Msk (_U_(0x1) << PIO_OWER_P24_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P24(value) (PIO_OWER_P24_Msk & ((value) << PIO_OWER_P24_Pos)) +#define PIO_OWER_P25_Pos _U_(25) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P25_Msk (_U_(0x1) << PIO_OWER_P25_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P25(value) (PIO_OWER_P25_Msk & ((value) << PIO_OWER_P25_Pos)) +#define PIO_OWER_P26_Pos _U_(26) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P26_Msk (_U_(0x1) << PIO_OWER_P26_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P26(value) (PIO_OWER_P26_Msk & ((value) << PIO_OWER_P26_Pos)) +#define PIO_OWER_P27_Pos _U_(27) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P27_Msk (_U_(0x1) << PIO_OWER_P27_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P27(value) (PIO_OWER_P27_Msk & ((value) << PIO_OWER_P27_Pos)) +#define PIO_OWER_P28_Pos _U_(28) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P28_Msk (_U_(0x1) << PIO_OWER_P28_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P28(value) (PIO_OWER_P28_Msk & ((value) << PIO_OWER_P28_Pos)) +#define PIO_OWER_P29_Pos _U_(29) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P29_Msk (_U_(0x1) << PIO_OWER_P29_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P29(value) (PIO_OWER_P29_Msk & ((value) << PIO_OWER_P29_Pos)) +#define PIO_OWER_P30_Pos _U_(30) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P30_Msk (_U_(0x1) << PIO_OWER_P30_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P30(value) (PIO_OWER_P30_Msk & ((value) << PIO_OWER_P30_Pos)) +#define PIO_OWER_P31_Pos _U_(31) /**< (PIO_OWER) Output Write Enable Position */ +#define PIO_OWER_P31_Msk (_U_(0x1) << PIO_OWER_P31_Pos) /**< (PIO_OWER) Output Write Enable Mask */ +#define PIO_OWER_P31(value) (PIO_OWER_P31_Msk & ((value) << PIO_OWER_P31_Pos)) +#define PIO_OWER_Msk _U_(0xFFFFFFFF) /**< (PIO_OWER) Register Mask */ + +#define PIO_OWER_P_Pos _U_(0) /**< (PIO_OWER Position) Output Write Enable */ +#define PIO_OWER_P_Msk (_U_(0xFFFFFFFF) << PIO_OWER_P_Pos) /**< (PIO_OWER Mask) P */ +#define PIO_OWER_P(value) (PIO_OWER_P_Msk & ((value) << PIO_OWER_P_Pos)) + +/* -------- PIO_OWDR : (PIO Offset: 0xA4) ( /W 32) Output Write Disable -------- */ +#define PIO_OWDR_P0_Pos _U_(0) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P0_Msk (_U_(0x1) << PIO_OWDR_P0_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P0(value) (PIO_OWDR_P0_Msk & ((value) << PIO_OWDR_P0_Pos)) +#define PIO_OWDR_P1_Pos _U_(1) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P1_Msk (_U_(0x1) << PIO_OWDR_P1_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P1(value) (PIO_OWDR_P1_Msk & ((value) << PIO_OWDR_P1_Pos)) +#define PIO_OWDR_P2_Pos _U_(2) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P2_Msk (_U_(0x1) << PIO_OWDR_P2_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P2(value) (PIO_OWDR_P2_Msk & ((value) << PIO_OWDR_P2_Pos)) +#define PIO_OWDR_P3_Pos _U_(3) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P3_Msk (_U_(0x1) << PIO_OWDR_P3_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P3(value) (PIO_OWDR_P3_Msk & ((value) << PIO_OWDR_P3_Pos)) +#define PIO_OWDR_P4_Pos _U_(4) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P4_Msk (_U_(0x1) << PIO_OWDR_P4_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P4(value) (PIO_OWDR_P4_Msk & ((value) << PIO_OWDR_P4_Pos)) +#define PIO_OWDR_P5_Pos _U_(5) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P5_Msk (_U_(0x1) << PIO_OWDR_P5_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P5(value) (PIO_OWDR_P5_Msk & ((value) << PIO_OWDR_P5_Pos)) +#define PIO_OWDR_P6_Pos _U_(6) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P6_Msk (_U_(0x1) << PIO_OWDR_P6_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P6(value) (PIO_OWDR_P6_Msk & ((value) << PIO_OWDR_P6_Pos)) +#define PIO_OWDR_P7_Pos _U_(7) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P7_Msk (_U_(0x1) << PIO_OWDR_P7_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P7(value) (PIO_OWDR_P7_Msk & ((value) << PIO_OWDR_P7_Pos)) +#define PIO_OWDR_P8_Pos _U_(8) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P8_Msk (_U_(0x1) << PIO_OWDR_P8_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P8(value) (PIO_OWDR_P8_Msk & ((value) << PIO_OWDR_P8_Pos)) +#define PIO_OWDR_P9_Pos _U_(9) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P9_Msk (_U_(0x1) << PIO_OWDR_P9_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P9(value) (PIO_OWDR_P9_Msk & ((value) << PIO_OWDR_P9_Pos)) +#define PIO_OWDR_P10_Pos _U_(10) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P10_Msk (_U_(0x1) << PIO_OWDR_P10_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P10(value) (PIO_OWDR_P10_Msk & ((value) << PIO_OWDR_P10_Pos)) +#define PIO_OWDR_P11_Pos _U_(11) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P11_Msk (_U_(0x1) << PIO_OWDR_P11_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P11(value) (PIO_OWDR_P11_Msk & ((value) << PIO_OWDR_P11_Pos)) +#define PIO_OWDR_P12_Pos _U_(12) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P12_Msk (_U_(0x1) << PIO_OWDR_P12_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P12(value) (PIO_OWDR_P12_Msk & ((value) << PIO_OWDR_P12_Pos)) +#define PIO_OWDR_P13_Pos _U_(13) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P13_Msk (_U_(0x1) << PIO_OWDR_P13_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P13(value) (PIO_OWDR_P13_Msk & ((value) << PIO_OWDR_P13_Pos)) +#define PIO_OWDR_P14_Pos _U_(14) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P14_Msk (_U_(0x1) << PIO_OWDR_P14_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P14(value) (PIO_OWDR_P14_Msk & ((value) << PIO_OWDR_P14_Pos)) +#define PIO_OWDR_P15_Pos _U_(15) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P15_Msk (_U_(0x1) << PIO_OWDR_P15_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P15(value) (PIO_OWDR_P15_Msk & ((value) << PIO_OWDR_P15_Pos)) +#define PIO_OWDR_P16_Pos _U_(16) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P16_Msk (_U_(0x1) << PIO_OWDR_P16_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P16(value) (PIO_OWDR_P16_Msk & ((value) << PIO_OWDR_P16_Pos)) +#define PIO_OWDR_P17_Pos _U_(17) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P17_Msk (_U_(0x1) << PIO_OWDR_P17_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P17(value) (PIO_OWDR_P17_Msk & ((value) << PIO_OWDR_P17_Pos)) +#define PIO_OWDR_P18_Pos _U_(18) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P18_Msk (_U_(0x1) << PIO_OWDR_P18_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P18(value) (PIO_OWDR_P18_Msk & ((value) << PIO_OWDR_P18_Pos)) +#define PIO_OWDR_P19_Pos _U_(19) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P19_Msk (_U_(0x1) << PIO_OWDR_P19_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P19(value) (PIO_OWDR_P19_Msk & ((value) << PIO_OWDR_P19_Pos)) +#define PIO_OWDR_P20_Pos _U_(20) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P20_Msk (_U_(0x1) << PIO_OWDR_P20_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P20(value) (PIO_OWDR_P20_Msk & ((value) << PIO_OWDR_P20_Pos)) +#define PIO_OWDR_P21_Pos _U_(21) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P21_Msk (_U_(0x1) << PIO_OWDR_P21_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P21(value) (PIO_OWDR_P21_Msk & ((value) << PIO_OWDR_P21_Pos)) +#define PIO_OWDR_P22_Pos _U_(22) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P22_Msk (_U_(0x1) << PIO_OWDR_P22_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P22(value) (PIO_OWDR_P22_Msk & ((value) << PIO_OWDR_P22_Pos)) +#define PIO_OWDR_P23_Pos _U_(23) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P23_Msk (_U_(0x1) << PIO_OWDR_P23_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P23(value) (PIO_OWDR_P23_Msk & ((value) << PIO_OWDR_P23_Pos)) +#define PIO_OWDR_P24_Pos _U_(24) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P24_Msk (_U_(0x1) << PIO_OWDR_P24_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P24(value) (PIO_OWDR_P24_Msk & ((value) << PIO_OWDR_P24_Pos)) +#define PIO_OWDR_P25_Pos _U_(25) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P25_Msk (_U_(0x1) << PIO_OWDR_P25_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P25(value) (PIO_OWDR_P25_Msk & ((value) << PIO_OWDR_P25_Pos)) +#define PIO_OWDR_P26_Pos _U_(26) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P26_Msk (_U_(0x1) << PIO_OWDR_P26_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P26(value) (PIO_OWDR_P26_Msk & ((value) << PIO_OWDR_P26_Pos)) +#define PIO_OWDR_P27_Pos _U_(27) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P27_Msk (_U_(0x1) << PIO_OWDR_P27_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P27(value) (PIO_OWDR_P27_Msk & ((value) << PIO_OWDR_P27_Pos)) +#define PIO_OWDR_P28_Pos _U_(28) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P28_Msk (_U_(0x1) << PIO_OWDR_P28_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P28(value) (PIO_OWDR_P28_Msk & ((value) << PIO_OWDR_P28_Pos)) +#define PIO_OWDR_P29_Pos _U_(29) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P29_Msk (_U_(0x1) << PIO_OWDR_P29_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P29(value) (PIO_OWDR_P29_Msk & ((value) << PIO_OWDR_P29_Pos)) +#define PIO_OWDR_P30_Pos _U_(30) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P30_Msk (_U_(0x1) << PIO_OWDR_P30_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P30(value) (PIO_OWDR_P30_Msk & ((value) << PIO_OWDR_P30_Pos)) +#define PIO_OWDR_P31_Pos _U_(31) /**< (PIO_OWDR) Output Write Disable Position */ +#define PIO_OWDR_P31_Msk (_U_(0x1) << PIO_OWDR_P31_Pos) /**< (PIO_OWDR) Output Write Disable Mask */ +#define PIO_OWDR_P31(value) (PIO_OWDR_P31_Msk & ((value) << PIO_OWDR_P31_Pos)) +#define PIO_OWDR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWDR) Register Mask */ + +#define PIO_OWDR_P_Pos _U_(0) /**< (PIO_OWDR Position) Output Write Disable */ +#define PIO_OWDR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWDR_P_Pos) /**< (PIO_OWDR Mask) P */ +#define PIO_OWDR_P(value) (PIO_OWDR_P_Msk & ((value) << PIO_OWDR_P_Pos)) + +/* -------- PIO_OWSR : (PIO Offset: 0xA8) ( R/ 32) Output Write Status Register -------- */ +#define PIO_OWSR_P0_Pos _U_(0) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P0_Msk (_U_(0x1) << PIO_OWSR_P0_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P0(value) (PIO_OWSR_P0_Msk & ((value) << PIO_OWSR_P0_Pos)) +#define PIO_OWSR_P1_Pos _U_(1) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P1_Msk (_U_(0x1) << PIO_OWSR_P1_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P1(value) (PIO_OWSR_P1_Msk & ((value) << PIO_OWSR_P1_Pos)) +#define PIO_OWSR_P2_Pos _U_(2) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P2_Msk (_U_(0x1) << PIO_OWSR_P2_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P2(value) (PIO_OWSR_P2_Msk & ((value) << PIO_OWSR_P2_Pos)) +#define PIO_OWSR_P3_Pos _U_(3) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P3_Msk (_U_(0x1) << PIO_OWSR_P3_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P3(value) (PIO_OWSR_P3_Msk & ((value) << PIO_OWSR_P3_Pos)) +#define PIO_OWSR_P4_Pos _U_(4) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P4_Msk (_U_(0x1) << PIO_OWSR_P4_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P4(value) (PIO_OWSR_P4_Msk & ((value) << PIO_OWSR_P4_Pos)) +#define PIO_OWSR_P5_Pos _U_(5) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P5_Msk (_U_(0x1) << PIO_OWSR_P5_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P5(value) (PIO_OWSR_P5_Msk & ((value) << PIO_OWSR_P5_Pos)) +#define PIO_OWSR_P6_Pos _U_(6) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P6_Msk (_U_(0x1) << PIO_OWSR_P6_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P6(value) (PIO_OWSR_P6_Msk & ((value) << PIO_OWSR_P6_Pos)) +#define PIO_OWSR_P7_Pos _U_(7) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P7_Msk (_U_(0x1) << PIO_OWSR_P7_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P7(value) (PIO_OWSR_P7_Msk & ((value) << PIO_OWSR_P7_Pos)) +#define PIO_OWSR_P8_Pos _U_(8) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P8_Msk (_U_(0x1) << PIO_OWSR_P8_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P8(value) (PIO_OWSR_P8_Msk & ((value) << PIO_OWSR_P8_Pos)) +#define PIO_OWSR_P9_Pos _U_(9) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P9_Msk (_U_(0x1) << PIO_OWSR_P9_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P9(value) (PIO_OWSR_P9_Msk & ((value) << PIO_OWSR_P9_Pos)) +#define PIO_OWSR_P10_Pos _U_(10) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P10_Msk (_U_(0x1) << PIO_OWSR_P10_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P10(value) (PIO_OWSR_P10_Msk & ((value) << PIO_OWSR_P10_Pos)) +#define PIO_OWSR_P11_Pos _U_(11) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P11_Msk (_U_(0x1) << PIO_OWSR_P11_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P11(value) (PIO_OWSR_P11_Msk & ((value) << PIO_OWSR_P11_Pos)) +#define PIO_OWSR_P12_Pos _U_(12) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P12_Msk (_U_(0x1) << PIO_OWSR_P12_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P12(value) (PIO_OWSR_P12_Msk & ((value) << PIO_OWSR_P12_Pos)) +#define PIO_OWSR_P13_Pos _U_(13) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P13_Msk (_U_(0x1) << PIO_OWSR_P13_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P13(value) (PIO_OWSR_P13_Msk & ((value) << PIO_OWSR_P13_Pos)) +#define PIO_OWSR_P14_Pos _U_(14) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P14_Msk (_U_(0x1) << PIO_OWSR_P14_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P14(value) (PIO_OWSR_P14_Msk & ((value) << PIO_OWSR_P14_Pos)) +#define PIO_OWSR_P15_Pos _U_(15) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P15_Msk (_U_(0x1) << PIO_OWSR_P15_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P15(value) (PIO_OWSR_P15_Msk & ((value) << PIO_OWSR_P15_Pos)) +#define PIO_OWSR_P16_Pos _U_(16) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P16_Msk (_U_(0x1) << PIO_OWSR_P16_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P16(value) (PIO_OWSR_P16_Msk & ((value) << PIO_OWSR_P16_Pos)) +#define PIO_OWSR_P17_Pos _U_(17) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P17_Msk (_U_(0x1) << PIO_OWSR_P17_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P17(value) (PIO_OWSR_P17_Msk & ((value) << PIO_OWSR_P17_Pos)) +#define PIO_OWSR_P18_Pos _U_(18) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P18_Msk (_U_(0x1) << PIO_OWSR_P18_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P18(value) (PIO_OWSR_P18_Msk & ((value) << PIO_OWSR_P18_Pos)) +#define PIO_OWSR_P19_Pos _U_(19) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P19_Msk (_U_(0x1) << PIO_OWSR_P19_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P19(value) (PIO_OWSR_P19_Msk & ((value) << PIO_OWSR_P19_Pos)) +#define PIO_OWSR_P20_Pos _U_(20) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P20_Msk (_U_(0x1) << PIO_OWSR_P20_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P20(value) (PIO_OWSR_P20_Msk & ((value) << PIO_OWSR_P20_Pos)) +#define PIO_OWSR_P21_Pos _U_(21) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P21_Msk (_U_(0x1) << PIO_OWSR_P21_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P21(value) (PIO_OWSR_P21_Msk & ((value) << PIO_OWSR_P21_Pos)) +#define PIO_OWSR_P22_Pos _U_(22) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P22_Msk (_U_(0x1) << PIO_OWSR_P22_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P22(value) (PIO_OWSR_P22_Msk & ((value) << PIO_OWSR_P22_Pos)) +#define PIO_OWSR_P23_Pos _U_(23) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P23_Msk (_U_(0x1) << PIO_OWSR_P23_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P23(value) (PIO_OWSR_P23_Msk & ((value) << PIO_OWSR_P23_Pos)) +#define PIO_OWSR_P24_Pos _U_(24) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P24_Msk (_U_(0x1) << PIO_OWSR_P24_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P24(value) (PIO_OWSR_P24_Msk & ((value) << PIO_OWSR_P24_Pos)) +#define PIO_OWSR_P25_Pos _U_(25) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P25_Msk (_U_(0x1) << PIO_OWSR_P25_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P25(value) (PIO_OWSR_P25_Msk & ((value) << PIO_OWSR_P25_Pos)) +#define PIO_OWSR_P26_Pos _U_(26) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P26_Msk (_U_(0x1) << PIO_OWSR_P26_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P26(value) (PIO_OWSR_P26_Msk & ((value) << PIO_OWSR_P26_Pos)) +#define PIO_OWSR_P27_Pos _U_(27) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P27_Msk (_U_(0x1) << PIO_OWSR_P27_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P27(value) (PIO_OWSR_P27_Msk & ((value) << PIO_OWSR_P27_Pos)) +#define PIO_OWSR_P28_Pos _U_(28) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P28_Msk (_U_(0x1) << PIO_OWSR_P28_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P28(value) (PIO_OWSR_P28_Msk & ((value) << PIO_OWSR_P28_Pos)) +#define PIO_OWSR_P29_Pos _U_(29) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P29_Msk (_U_(0x1) << PIO_OWSR_P29_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P29(value) (PIO_OWSR_P29_Msk & ((value) << PIO_OWSR_P29_Pos)) +#define PIO_OWSR_P30_Pos _U_(30) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P30_Msk (_U_(0x1) << PIO_OWSR_P30_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P30(value) (PIO_OWSR_P30_Msk & ((value) << PIO_OWSR_P30_Pos)) +#define PIO_OWSR_P31_Pos _U_(31) /**< (PIO_OWSR) Output Write Status Position */ +#define PIO_OWSR_P31_Msk (_U_(0x1) << PIO_OWSR_P31_Pos) /**< (PIO_OWSR) Output Write Status Mask */ +#define PIO_OWSR_P31(value) (PIO_OWSR_P31_Msk & ((value) << PIO_OWSR_P31_Pos)) +#define PIO_OWSR_Msk _U_(0xFFFFFFFF) /**< (PIO_OWSR) Register Mask */ + +#define PIO_OWSR_P_Pos _U_(0) /**< (PIO_OWSR Position) Output Write Status */ +#define PIO_OWSR_P_Msk (_U_(0xFFFFFFFF) << PIO_OWSR_P_Pos) /**< (PIO_OWSR Mask) P */ +#define PIO_OWSR_P(value) (PIO_OWSR_P_Msk & ((value) << PIO_OWSR_P_Pos)) + +/* -------- PIO_AIMER : (PIO Offset: 0xB0) ( /W 32) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0_Pos _U_(0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P0_Msk (_U_(0x1) << PIO_AIMER_P0_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P0(value) (PIO_AIMER_P0_Msk & ((value) << PIO_AIMER_P0_Pos)) +#define PIO_AIMER_P1_Pos _U_(1) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P1_Msk (_U_(0x1) << PIO_AIMER_P1_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P1(value) (PIO_AIMER_P1_Msk & ((value) << PIO_AIMER_P1_Pos)) +#define PIO_AIMER_P2_Pos _U_(2) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P2_Msk (_U_(0x1) << PIO_AIMER_P2_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P2(value) (PIO_AIMER_P2_Msk & ((value) << PIO_AIMER_P2_Pos)) +#define PIO_AIMER_P3_Pos _U_(3) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P3_Msk (_U_(0x1) << PIO_AIMER_P3_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P3(value) (PIO_AIMER_P3_Msk & ((value) << PIO_AIMER_P3_Pos)) +#define PIO_AIMER_P4_Pos _U_(4) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P4_Msk (_U_(0x1) << PIO_AIMER_P4_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P4(value) (PIO_AIMER_P4_Msk & ((value) << PIO_AIMER_P4_Pos)) +#define PIO_AIMER_P5_Pos _U_(5) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P5_Msk (_U_(0x1) << PIO_AIMER_P5_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P5(value) (PIO_AIMER_P5_Msk & ((value) << PIO_AIMER_P5_Pos)) +#define PIO_AIMER_P6_Pos _U_(6) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P6_Msk (_U_(0x1) << PIO_AIMER_P6_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P6(value) (PIO_AIMER_P6_Msk & ((value) << PIO_AIMER_P6_Pos)) +#define PIO_AIMER_P7_Pos _U_(7) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P7_Msk (_U_(0x1) << PIO_AIMER_P7_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P7(value) (PIO_AIMER_P7_Msk & ((value) << PIO_AIMER_P7_Pos)) +#define PIO_AIMER_P8_Pos _U_(8) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P8_Msk (_U_(0x1) << PIO_AIMER_P8_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P8(value) (PIO_AIMER_P8_Msk & ((value) << PIO_AIMER_P8_Pos)) +#define PIO_AIMER_P9_Pos _U_(9) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P9_Msk (_U_(0x1) << PIO_AIMER_P9_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P9(value) (PIO_AIMER_P9_Msk & ((value) << PIO_AIMER_P9_Pos)) +#define PIO_AIMER_P10_Pos _U_(10) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P10_Msk (_U_(0x1) << PIO_AIMER_P10_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P10(value) (PIO_AIMER_P10_Msk & ((value) << PIO_AIMER_P10_Pos)) +#define PIO_AIMER_P11_Pos _U_(11) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P11_Msk (_U_(0x1) << PIO_AIMER_P11_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P11(value) (PIO_AIMER_P11_Msk & ((value) << PIO_AIMER_P11_Pos)) +#define PIO_AIMER_P12_Pos _U_(12) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P12_Msk (_U_(0x1) << PIO_AIMER_P12_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P12(value) (PIO_AIMER_P12_Msk & ((value) << PIO_AIMER_P12_Pos)) +#define PIO_AIMER_P13_Pos _U_(13) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P13_Msk (_U_(0x1) << PIO_AIMER_P13_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P13(value) (PIO_AIMER_P13_Msk & ((value) << PIO_AIMER_P13_Pos)) +#define PIO_AIMER_P14_Pos _U_(14) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P14_Msk (_U_(0x1) << PIO_AIMER_P14_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P14(value) (PIO_AIMER_P14_Msk & ((value) << PIO_AIMER_P14_Pos)) +#define PIO_AIMER_P15_Pos _U_(15) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P15_Msk (_U_(0x1) << PIO_AIMER_P15_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P15(value) (PIO_AIMER_P15_Msk & ((value) << PIO_AIMER_P15_Pos)) +#define PIO_AIMER_P16_Pos _U_(16) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P16_Msk (_U_(0x1) << PIO_AIMER_P16_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P16(value) (PIO_AIMER_P16_Msk & ((value) << PIO_AIMER_P16_Pos)) +#define PIO_AIMER_P17_Pos _U_(17) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P17_Msk (_U_(0x1) << PIO_AIMER_P17_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P17(value) (PIO_AIMER_P17_Msk & ((value) << PIO_AIMER_P17_Pos)) +#define PIO_AIMER_P18_Pos _U_(18) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P18_Msk (_U_(0x1) << PIO_AIMER_P18_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P18(value) (PIO_AIMER_P18_Msk & ((value) << PIO_AIMER_P18_Pos)) +#define PIO_AIMER_P19_Pos _U_(19) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P19_Msk (_U_(0x1) << PIO_AIMER_P19_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P19(value) (PIO_AIMER_P19_Msk & ((value) << PIO_AIMER_P19_Pos)) +#define PIO_AIMER_P20_Pos _U_(20) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P20_Msk (_U_(0x1) << PIO_AIMER_P20_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P20(value) (PIO_AIMER_P20_Msk & ((value) << PIO_AIMER_P20_Pos)) +#define PIO_AIMER_P21_Pos _U_(21) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P21_Msk (_U_(0x1) << PIO_AIMER_P21_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P21(value) (PIO_AIMER_P21_Msk & ((value) << PIO_AIMER_P21_Pos)) +#define PIO_AIMER_P22_Pos _U_(22) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P22_Msk (_U_(0x1) << PIO_AIMER_P22_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P22(value) (PIO_AIMER_P22_Msk & ((value) << PIO_AIMER_P22_Pos)) +#define PIO_AIMER_P23_Pos _U_(23) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P23_Msk (_U_(0x1) << PIO_AIMER_P23_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P23(value) (PIO_AIMER_P23_Msk & ((value) << PIO_AIMER_P23_Pos)) +#define PIO_AIMER_P24_Pos _U_(24) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P24_Msk (_U_(0x1) << PIO_AIMER_P24_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P24(value) (PIO_AIMER_P24_Msk & ((value) << PIO_AIMER_P24_Pos)) +#define PIO_AIMER_P25_Pos _U_(25) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P25_Msk (_U_(0x1) << PIO_AIMER_P25_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P25(value) (PIO_AIMER_P25_Msk & ((value) << PIO_AIMER_P25_Pos)) +#define PIO_AIMER_P26_Pos _U_(26) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P26_Msk (_U_(0x1) << PIO_AIMER_P26_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P26(value) (PIO_AIMER_P26_Msk & ((value) << PIO_AIMER_P26_Pos)) +#define PIO_AIMER_P27_Pos _U_(27) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P27_Msk (_U_(0x1) << PIO_AIMER_P27_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P27(value) (PIO_AIMER_P27_Msk & ((value) << PIO_AIMER_P27_Pos)) +#define PIO_AIMER_P28_Pos _U_(28) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P28_Msk (_U_(0x1) << PIO_AIMER_P28_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P28(value) (PIO_AIMER_P28_Msk & ((value) << PIO_AIMER_P28_Pos)) +#define PIO_AIMER_P29_Pos _U_(29) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P29_Msk (_U_(0x1) << PIO_AIMER_P29_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P29(value) (PIO_AIMER_P29_Msk & ((value) << PIO_AIMER_P29_Pos)) +#define PIO_AIMER_P30_Pos _U_(30) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P30_Msk (_U_(0x1) << PIO_AIMER_P30_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P30(value) (PIO_AIMER_P30_Msk & ((value) << PIO_AIMER_P30_Pos)) +#define PIO_AIMER_P31_Pos _U_(31) /**< (PIO_AIMER) Additional Interrupt Modes Enable Position */ +#define PIO_AIMER_P31_Msk (_U_(0x1) << PIO_AIMER_P31_Pos) /**< (PIO_AIMER) Additional Interrupt Modes Enable Mask */ +#define PIO_AIMER_P31(value) (PIO_AIMER_P31_Msk & ((value) << PIO_AIMER_P31_Pos)) +#define PIO_AIMER_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMER) Register Mask */ + +#define PIO_AIMER_P_Pos _U_(0) /**< (PIO_AIMER Position) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMER_P_Pos) /**< (PIO_AIMER Mask) P */ +#define PIO_AIMER_P(value) (PIO_AIMER_P_Msk & ((value) << PIO_AIMER_P_Pos)) + +/* -------- PIO_AIMDR : (PIO Offset: 0xB4) ( /W 32) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0_Pos _U_(0) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P0_Msk (_U_(0x1) << PIO_AIMDR_P0_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P0(value) (PIO_AIMDR_P0_Msk & ((value) << PIO_AIMDR_P0_Pos)) +#define PIO_AIMDR_P1_Pos _U_(1) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P1_Msk (_U_(0x1) << PIO_AIMDR_P1_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P1(value) (PIO_AIMDR_P1_Msk & ((value) << PIO_AIMDR_P1_Pos)) +#define PIO_AIMDR_P2_Pos _U_(2) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P2_Msk (_U_(0x1) << PIO_AIMDR_P2_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P2(value) (PIO_AIMDR_P2_Msk & ((value) << PIO_AIMDR_P2_Pos)) +#define PIO_AIMDR_P3_Pos _U_(3) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P3_Msk (_U_(0x1) << PIO_AIMDR_P3_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P3(value) (PIO_AIMDR_P3_Msk & ((value) << PIO_AIMDR_P3_Pos)) +#define PIO_AIMDR_P4_Pos _U_(4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P4_Msk (_U_(0x1) << PIO_AIMDR_P4_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P4(value) (PIO_AIMDR_P4_Msk & ((value) << PIO_AIMDR_P4_Pos)) +#define PIO_AIMDR_P5_Pos _U_(5) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P5_Msk (_U_(0x1) << PIO_AIMDR_P5_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P5(value) (PIO_AIMDR_P5_Msk & ((value) << PIO_AIMDR_P5_Pos)) +#define PIO_AIMDR_P6_Pos _U_(6) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P6_Msk (_U_(0x1) << PIO_AIMDR_P6_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P6(value) (PIO_AIMDR_P6_Msk & ((value) << PIO_AIMDR_P6_Pos)) +#define PIO_AIMDR_P7_Pos _U_(7) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P7_Msk (_U_(0x1) << PIO_AIMDR_P7_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P7(value) (PIO_AIMDR_P7_Msk & ((value) << PIO_AIMDR_P7_Pos)) +#define PIO_AIMDR_P8_Pos _U_(8) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P8_Msk (_U_(0x1) << PIO_AIMDR_P8_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P8(value) (PIO_AIMDR_P8_Msk & ((value) << PIO_AIMDR_P8_Pos)) +#define PIO_AIMDR_P9_Pos _U_(9) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P9_Msk (_U_(0x1) << PIO_AIMDR_P9_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P9(value) (PIO_AIMDR_P9_Msk & ((value) << PIO_AIMDR_P9_Pos)) +#define PIO_AIMDR_P10_Pos _U_(10) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P10_Msk (_U_(0x1) << PIO_AIMDR_P10_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P10(value) (PIO_AIMDR_P10_Msk & ((value) << PIO_AIMDR_P10_Pos)) +#define PIO_AIMDR_P11_Pos _U_(11) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P11_Msk (_U_(0x1) << PIO_AIMDR_P11_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P11(value) (PIO_AIMDR_P11_Msk & ((value) << PIO_AIMDR_P11_Pos)) +#define PIO_AIMDR_P12_Pos _U_(12) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P12_Msk (_U_(0x1) << PIO_AIMDR_P12_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P12(value) (PIO_AIMDR_P12_Msk & ((value) << PIO_AIMDR_P12_Pos)) +#define PIO_AIMDR_P13_Pos _U_(13) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P13_Msk (_U_(0x1) << PIO_AIMDR_P13_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P13(value) (PIO_AIMDR_P13_Msk & ((value) << PIO_AIMDR_P13_Pos)) +#define PIO_AIMDR_P14_Pos _U_(14) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P14_Msk (_U_(0x1) << PIO_AIMDR_P14_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P14(value) (PIO_AIMDR_P14_Msk & ((value) << PIO_AIMDR_P14_Pos)) +#define PIO_AIMDR_P15_Pos _U_(15) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P15_Msk (_U_(0x1) << PIO_AIMDR_P15_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P15(value) (PIO_AIMDR_P15_Msk & ((value) << PIO_AIMDR_P15_Pos)) +#define PIO_AIMDR_P16_Pos _U_(16) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P16_Msk (_U_(0x1) << PIO_AIMDR_P16_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P16(value) (PIO_AIMDR_P16_Msk & ((value) << PIO_AIMDR_P16_Pos)) +#define PIO_AIMDR_P17_Pos _U_(17) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P17_Msk (_U_(0x1) << PIO_AIMDR_P17_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P17(value) (PIO_AIMDR_P17_Msk & ((value) << PIO_AIMDR_P17_Pos)) +#define PIO_AIMDR_P18_Pos _U_(18) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P18_Msk (_U_(0x1) << PIO_AIMDR_P18_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P18(value) (PIO_AIMDR_P18_Msk & ((value) << PIO_AIMDR_P18_Pos)) +#define PIO_AIMDR_P19_Pos _U_(19) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P19_Msk (_U_(0x1) << PIO_AIMDR_P19_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P19(value) (PIO_AIMDR_P19_Msk & ((value) << PIO_AIMDR_P19_Pos)) +#define PIO_AIMDR_P20_Pos _U_(20) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P20_Msk (_U_(0x1) << PIO_AIMDR_P20_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P20(value) (PIO_AIMDR_P20_Msk & ((value) << PIO_AIMDR_P20_Pos)) +#define PIO_AIMDR_P21_Pos _U_(21) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P21_Msk (_U_(0x1) << PIO_AIMDR_P21_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P21(value) (PIO_AIMDR_P21_Msk & ((value) << PIO_AIMDR_P21_Pos)) +#define PIO_AIMDR_P22_Pos _U_(22) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P22_Msk (_U_(0x1) << PIO_AIMDR_P22_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P22(value) (PIO_AIMDR_P22_Msk & ((value) << PIO_AIMDR_P22_Pos)) +#define PIO_AIMDR_P23_Pos _U_(23) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P23_Msk (_U_(0x1) << PIO_AIMDR_P23_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P23(value) (PIO_AIMDR_P23_Msk & ((value) << PIO_AIMDR_P23_Pos)) +#define PIO_AIMDR_P24_Pos _U_(24) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P24_Msk (_U_(0x1) << PIO_AIMDR_P24_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P24(value) (PIO_AIMDR_P24_Msk & ((value) << PIO_AIMDR_P24_Pos)) +#define PIO_AIMDR_P25_Pos _U_(25) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P25_Msk (_U_(0x1) << PIO_AIMDR_P25_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P25(value) (PIO_AIMDR_P25_Msk & ((value) << PIO_AIMDR_P25_Pos)) +#define PIO_AIMDR_P26_Pos _U_(26) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P26_Msk (_U_(0x1) << PIO_AIMDR_P26_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P26(value) (PIO_AIMDR_P26_Msk & ((value) << PIO_AIMDR_P26_Pos)) +#define PIO_AIMDR_P27_Pos _U_(27) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P27_Msk (_U_(0x1) << PIO_AIMDR_P27_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P27(value) (PIO_AIMDR_P27_Msk & ((value) << PIO_AIMDR_P27_Pos)) +#define PIO_AIMDR_P28_Pos _U_(28) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P28_Msk (_U_(0x1) << PIO_AIMDR_P28_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P28(value) (PIO_AIMDR_P28_Msk & ((value) << PIO_AIMDR_P28_Pos)) +#define PIO_AIMDR_P29_Pos _U_(29) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P29_Msk (_U_(0x1) << PIO_AIMDR_P29_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P29(value) (PIO_AIMDR_P29_Msk & ((value) << PIO_AIMDR_P29_Pos)) +#define PIO_AIMDR_P30_Pos _U_(30) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P30_Msk (_U_(0x1) << PIO_AIMDR_P30_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P30(value) (PIO_AIMDR_P30_Msk & ((value) << PIO_AIMDR_P30_Pos)) +#define PIO_AIMDR_P31_Pos _U_(31) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Position */ +#define PIO_AIMDR_P31_Msk (_U_(0x1) << PIO_AIMDR_P31_Pos) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Mask */ +#define PIO_AIMDR_P31(value) (PIO_AIMDR_P31_Msk & ((value) << PIO_AIMDR_P31_Pos)) +#define PIO_AIMDR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMDR) Register Mask */ + +#define PIO_AIMDR_P_Pos _U_(0) /**< (PIO_AIMDR Position) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMDR_P_Pos) /**< (PIO_AIMDR Mask) P */ +#define PIO_AIMDR_P(value) (PIO_AIMDR_P_Msk & ((value) << PIO_AIMDR_P_Pos)) + +/* -------- PIO_AIMMR : (PIO Offset: 0xB8) ( R/ 32) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0_Pos _U_(0) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P0_Msk (_U_(0x1) << PIO_AIMMR_P0_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P0(value) (PIO_AIMMR_P0_Msk & ((value) << PIO_AIMMR_P0_Pos)) +#define PIO_AIMMR_P1_Pos _U_(1) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P1_Msk (_U_(0x1) << PIO_AIMMR_P1_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P1(value) (PIO_AIMMR_P1_Msk & ((value) << PIO_AIMMR_P1_Pos)) +#define PIO_AIMMR_P2_Pos _U_(2) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P2_Msk (_U_(0x1) << PIO_AIMMR_P2_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P2(value) (PIO_AIMMR_P2_Msk & ((value) << PIO_AIMMR_P2_Pos)) +#define PIO_AIMMR_P3_Pos _U_(3) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P3_Msk (_U_(0x1) << PIO_AIMMR_P3_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P3(value) (PIO_AIMMR_P3_Msk & ((value) << PIO_AIMMR_P3_Pos)) +#define PIO_AIMMR_P4_Pos _U_(4) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P4_Msk (_U_(0x1) << PIO_AIMMR_P4_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P4(value) (PIO_AIMMR_P4_Msk & ((value) << PIO_AIMMR_P4_Pos)) +#define PIO_AIMMR_P5_Pos _U_(5) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P5_Msk (_U_(0x1) << PIO_AIMMR_P5_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P5(value) (PIO_AIMMR_P5_Msk & ((value) << PIO_AIMMR_P5_Pos)) +#define PIO_AIMMR_P6_Pos _U_(6) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P6_Msk (_U_(0x1) << PIO_AIMMR_P6_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P6(value) (PIO_AIMMR_P6_Msk & ((value) << PIO_AIMMR_P6_Pos)) +#define PIO_AIMMR_P7_Pos _U_(7) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P7_Msk (_U_(0x1) << PIO_AIMMR_P7_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P7(value) (PIO_AIMMR_P7_Msk & ((value) << PIO_AIMMR_P7_Pos)) +#define PIO_AIMMR_P8_Pos _U_(8) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P8_Msk (_U_(0x1) << PIO_AIMMR_P8_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P8(value) (PIO_AIMMR_P8_Msk & ((value) << PIO_AIMMR_P8_Pos)) +#define PIO_AIMMR_P9_Pos _U_(9) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P9_Msk (_U_(0x1) << PIO_AIMMR_P9_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P9(value) (PIO_AIMMR_P9_Msk & ((value) << PIO_AIMMR_P9_Pos)) +#define PIO_AIMMR_P10_Pos _U_(10) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P10_Msk (_U_(0x1) << PIO_AIMMR_P10_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P10(value) (PIO_AIMMR_P10_Msk & ((value) << PIO_AIMMR_P10_Pos)) +#define PIO_AIMMR_P11_Pos _U_(11) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P11_Msk (_U_(0x1) << PIO_AIMMR_P11_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P11(value) (PIO_AIMMR_P11_Msk & ((value) << PIO_AIMMR_P11_Pos)) +#define PIO_AIMMR_P12_Pos _U_(12) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P12_Msk (_U_(0x1) << PIO_AIMMR_P12_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P12(value) (PIO_AIMMR_P12_Msk & ((value) << PIO_AIMMR_P12_Pos)) +#define PIO_AIMMR_P13_Pos _U_(13) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P13_Msk (_U_(0x1) << PIO_AIMMR_P13_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P13(value) (PIO_AIMMR_P13_Msk & ((value) << PIO_AIMMR_P13_Pos)) +#define PIO_AIMMR_P14_Pos _U_(14) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P14_Msk (_U_(0x1) << PIO_AIMMR_P14_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P14(value) (PIO_AIMMR_P14_Msk & ((value) << PIO_AIMMR_P14_Pos)) +#define PIO_AIMMR_P15_Pos _U_(15) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P15_Msk (_U_(0x1) << PIO_AIMMR_P15_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P15(value) (PIO_AIMMR_P15_Msk & ((value) << PIO_AIMMR_P15_Pos)) +#define PIO_AIMMR_P16_Pos _U_(16) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P16_Msk (_U_(0x1) << PIO_AIMMR_P16_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P16(value) (PIO_AIMMR_P16_Msk & ((value) << PIO_AIMMR_P16_Pos)) +#define PIO_AIMMR_P17_Pos _U_(17) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P17_Msk (_U_(0x1) << PIO_AIMMR_P17_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P17(value) (PIO_AIMMR_P17_Msk & ((value) << PIO_AIMMR_P17_Pos)) +#define PIO_AIMMR_P18_Pos _U_(18) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P18_Msk (_U_(0x1) << PIO_AIMMR_P18_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P18(value) (PIO_AIMMR_P18_Msk & ((value) << PIO_AIMMR_P18_Pos)) +#define PIO_AIMMR_P19_Pos _U_(19) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P19_Msk (_U_(0x1) << PIO_AIMMR_P19_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P19(value) (PIO_AIMMR_P19_Msk & ((value) << PIO_AIMMR_P19_Pos)) +#define PIO_AIMMR_P20_Pos _U_(20) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P20_Msk (_U_(0x1) << PIO_AIMMR_P20_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P20(value) (PIO_AIMMR_P20_Msk & ((value) << PIO_AIMMR_P20_Pos)) +#define PIO_AIMMR_P21_Pos _U_(21) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P21_Msk (_U_(0x1) << PIO_AIMMR_P21_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P21(value) (PIO_AIMMR_P21_Msk & ((value) << PIO_AIMMR_P21_Pos)) +#define PIO_AIMMR_P22_Pos _U_(22) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P22_Msk (_U_(0x1) << PIO_AIMMR_P22_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P22(value) (PIO_AIMMR_P22_Msk & ((value) << PIO_AIMMR_P22_Pos)) +#define PIO_AIMMR_P23_Pos _U_(23) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P23_Msk (_U_(0x1) << PIO_AIMMR_P23_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P23(value) (PIO_AIMMR_P23_Msk & ((value) << PIO_AIMMR_P23_Pos)) +#define PIO_AIMMR_P24_Pos _U_(24) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P24_Msk (_U_(0x1) << PIO_AIMMR_P24_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P24(value) (PIO_AIMMR_P24_Msk & ((value) << PIO_AIMMR_P24_Pos)) +#define PIO_AIMMR_P25_Pos _U_(25) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P25_Msk (_U_(0x1) << PIO_AIMMR_P25_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P25(value) (PIO_AIMMR_P25_Msk & ((value) << PIO_AIMMR_P25_Pos)) +#define PIO_AIMMR_P26_Pos _U_(26) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P26_Msk (_U_(0x1) << PIO_AIMMR_P26_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P26(value) (PIO_AIMMR_P26_Msk & ((value) << PIO_AIMMR_P26_Pos)) +#define PIO_AIMMR_P27_Pos _U_(27) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P27_Msk (_U_(0x1) << PIO_AIMMR_P27_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P27(value) (PIO_AIMMR_P27_Msk & ((value) << PIO_AIMMR_P27_Pos)) +#define PIO_AIMMR_P28_Pos _U_(28) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P28_Msk (_U_(0x1) << PIO_AIMMR_P28_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P28(value) (PIO_AIMMR_P28_Msk & ((value) << PIO_AIMMR_P28_Pos)) +#define PIO_AIMMR_P29_Pos _U_(29) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P29_Msk (_U_(0x1) << PIO_AIMMR_P29_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P29(value) (PIO_AIMMR_P29_Msk & ((value) << PIO_AIMMR_P29_Pos)) +#define PIO_AIMMR_P30_Pos _U_(30) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P30_Msk (_U_(0x1) << PIO_AIMMR_P30_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P30(value) (PIO_AIMMR_P30_Msk & ((value) << PIO_AIMMR_P30_Pos)) +#define PIO_AIMMR_P31_Pos _U_(31) /**< (PIO_AIMMR) IO Line Index Position */ +#define PIO_AIMMR_P31_Msk (_U_(0x1) << PIO_AIMMR_P31_Pos) /**< (PIO_AIMMR) IO Line Index Mask */ +#define PIO_AIMMR_P31(value) (PIO_AIMMR_P31_Msk & ((value) << PIO_AIMMR_P31_Pos)) +#define PIO_AIMMR_Msk _U_(0xFFFFFFFF) /**< (PIO_AIMMR) Register Mask */ + +#define PIO_AIMMR_P_Pos _U_(0) /**< (PIO_AIMMR Position) IO Line Index */ +#define PIO_AIMMR_P_Msk (_U_(0xFFFFFFFF) << PIO_AIMMR_P_Pos) /**< (PIO_AIMMR Mask) P */ +#define PIO_AIMMR_P(value) (PIO_AIMMR_P_Msk & ((value) << PIO_AIMMR_P_Pos)) + +/* -------- PIO_ESR : (PIO Offset: 0xC0) ( /W 32) Edge Select Register -------- */ +#define PIO_ESR_P0_Pos _U_(0) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P0_Msk (_U_(0x1) << PIO_ESR_P0_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P0(value) (PIO_ESR_P0_Msk & ((value) << PIO_ESR_P0_Pos)) +#define PIO_ESR_P1_Pos _U_(1) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P1_Msk (_U_(0x1) << PIO_ESR_P1_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P1(value) (PIO_ESR_P1_Msk & ((value) << PIO_ESR_P1_Pos)) +#define PIO_ESR_P2_Pos _U_(2) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P2_Msk (_U_(0x1) << PIO_ESR_P2_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P2(value) (PIO_ESR_P2_Msk & ((value) << PIO_ESR_P2_Pos)) +#define PIO_ESR_P3_Pos _U_(3) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P3_Msk (_U_(0x1) << PIO_ESR_P3_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P3(value) (PIO_ESR_P3_Msk & ((value) << PIO_ESR_P3_Pos)) +#define PIO_ESR_P4_Pos _U_(4) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P4_Msk (_U_(0x1) << PIO_ESR_P4_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P4(value) (PIO_ESR_P4_Msk & ((value) << PIO_ESR_P4_Pos)) +#define PIO_ESR_P5_Pos _U_(5) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P5_Msk (_U_(0x1) << PIO_ESR_P5_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P5(value) (PIO_ESR_P5_Msk & ((value) << PIO_ESR_P5_Pos)) +#define PIO_ESR_P6_Pos _U_(6) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P6_Msk (_U_(0x1) << PIO_ESR_P6_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P6(value) (PIO_ESR_P6_Msk & ((value) << PIO_ESR_P6_Pos)) +#define PIO_ESR_P7_Pos _U_(7) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P7_Msk (_U_(0x1) << PIO_ESR_P7_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P7(value) (PIO_ESR_P7_Msk & ((value) << PIO_ESR_P7_Pos)) +#define PIO_ESR_P8_Pos _U_(8) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P8_Msk (_U_(0x1) << PIO_ESR_P8_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P8(value) (PIO_ESR_P8_Msk & ((value) << PIO_ESR_P8_Pos)) +#define PIO_ESR_P9_Pos _U_(9) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P9_Msk (_U_(0x1) << PIO_ESR_P9_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P9(value) (PIO_ESR_P9_Msk & ((value) << PIO_ESR_P9_Pos)) +#define PIO_ESR_P10_Pos _U_(10) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P10_Msk (_U_(0x1) << PIO_ESR_P10_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P10(value) (PIO_ESR_P10_Msk & ((value) << PIO_ESR_P10_Pos)) +#define PIO_ESR_P11_Pos _U_(11) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P11_Msk (_U_(0x1) << PIO_ESR_P11_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P11(value) (PIO_ESR_P11_Msk & ((value) << PIO_ESR_P11_Pos)) +#define PIO_ESR_P12_Pos _U_(12) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P12_Msk (_U_(0x1) << PIO_ESR_P12_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P12(value) (PIO_ESR_P12_Msk & ((value) << PIO_ESR_P12_Pos)) +#define PIO_ESR_P13_Pos _U_(13) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P13_Msk (_U_(0x1) << PIO_ESR_P13_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P13(value) (PIO_ESR_P13_Msk & ((value) << PIO_ESR_P13_Pos)) +#define PIO_ESR_P14_Pos _U_(14) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P14_Msk (_U_(0x1) << PIO_ESR_P14_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P14(value) (PIO_ESR_P14_Msk & ((value) << PIO_ESR_P14_Pos)) +#define PIO_ESR_P15_Pos _U_(15) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P15_Msk (_U_(0x1) << PIO_ESR_P15_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P15(value) (PIO_ESR_P15_Msk & ((value) << PIO_ESR_P15_Pos)) +#define PIO_ESR_P16_Pos _U_(16) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P16_Msk (_U_(0x1) << PIO_ESR_P16_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P16(value) (PIO_ESR_P16_Msk & ((value) << PIO_ESR_P16_Pos)) +#define PIO_ESR_P17_Pos _U_(17) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P17_Msk (_U_(0x1) << PIO_ESR_P17_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P17(value) (PIO_ESR_P17_Msk & ((value) << PIO_ESR_P17_Pos)) +#define PIO_ESR_P18_Pos _U_(18) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P18_Msk (_U_(0x1) << PIO_ESR_P18_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P18(value) (PIO_ESR_P18_Msk & ((value) << PIO_ESR_P18_Pos)) +#define PIO_ESR_P19_Pos _U_(19) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P19_Msk (_U_(0x1) << PIO_ESR_P19_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P19(value) (PIO_ESR_P19_Msk & ((value) << PIO_ESR_P19_Pos)) +#define PIO_ESR_P20_Pos _U_(20) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P20_Msk (_U_(0x1) << PIO_ESR_P20_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P20(value) (PIO_ESR_P20_Msk & ((value) << PIO_ESR_P20_Pos)) +#define PIO_ESR_P21_Pos _U_(21) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P21_Msk (_U_(0x1) << PIO_ESR_P21_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P21(value) (PIO_ESR_P21_Msk & ((value) << PIO_ESR_P21_Pos)) +#define PIO_ESR_P22_Pos _U_(22) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P22_Msk (_U_(0x1) << PIO_ESR_P22_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P22(value) (PIO_ESR_P22_Msk & ((value) << PIO_ESR_P22_Pos)) +#define PIO_ESR_P23_Pos _U_(23) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P23_Msk (_U_(0x1) << PIO_ESR_P23_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P23(value) (PIO_ESR_P23_Msk & ((value) << PIO_ESR_P23_Pos)) +#define PIO_ESR_P24_Pos _U_(24) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P24_Msk (_U_(0x1) << PIO_ESR_P24_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P24(value) (PIO_ESR_P24_Msk & ((value) << PIO_ESR_P24_Pos)) +#define PIO_ESR_P25_Pos _U_(25) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P25_Msk (_U_(0x1) << PIO_ESR_P25_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P25(value) (PIO_ESR_P25_Msk & ((value) << PIO_ESR_P25_Pos)) +#define PIO_ESR_P26_Pos _U_(26) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P26_Msk (_U_(0x1) << PIO_ESR_P26_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P26(value) (PIO_ESR_P26_Msk & ((value) << PIO_ESR_P26_Pos)) +#define PIO_ESR_P27_Pos _U_(27) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P27_Msk (_U_(0x1) << PIO_ESR_P27_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P27(value) (PIO_ESR_P27_Msk & ((value) << PIO_ESR_P27_Pos)) +#define PIO_ESR_P28_Pos _U_(28) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P28_Msk (_U_(0x1) << PIO_ESR_P28_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P28(value) (PIO_ESR_P28_Msk & ((value) << PIO_ESR_P28_Pos)) +#define PIO_ESR_P29_Pos _U_(29) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P29_Msk (_U_(0x1) << PIO_ESR_P29_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P29(value) (PIO_ESR_P29_Msk & ((value) << PIO_ESR_P29_Pos)) +#define PIO_ESR_P30_Pos _U_(30) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P30_Msk (_U_(0x1) << PIO_ESR_P30_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P30(value) (PIO_ESR_P30_Msk & ((value) << PIO_ESR_P30_Pos)) +#define PIO_ESR_P31_Pos _U_(31) /**< (PIO_ESR) Edge Interrupt Selection Position */ +#define PIO_ESR_P31_Msk (_U_(0x1) << PIO_ESR_P31_Pos) /**< (PIO_ESR) Edge Interrupt Selection Mask */ +#define PIO_ESR_P31(value) (PIO_ESR_P31_Msk & ((value) << PIO_ESR_P31_Pos)) +#define PIO_ESR_Msk _U_(0xFFFFFFFF) /**< (PIO_ESR) Register Mask */ + +#define PIO_ESR_P_Pos _U_(0) /**< (PIO_ESR Position) Edge Interrupt Selection */ +#define PIO_ESR_P_Msk (_U_(0xFFFFFFFF) << PIO_ESR_P_Pos) /**< (PIO_ESR Mask) P */ +#define PIO_ESR_P(value) (PIO_ESR_P_Msk & ((value) << PIO_ESR_P_Pos)) + +/* -------- PIO_LSR : (PIO Offset: 0xC4) ( /W 32) Level Select Register -------- */ +#define PIO_LSR_P0_Pos _U_(0) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P0_Msk (_U_(0x1) << PIO_LSR_P0_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P0(value) (PIO_LSR_P0_Msk & ((value) << PIO_LSR_P0_Pos)) +#define PIO_LSR_P1_Pos _U_(1) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P1_Msk (_U_(0x1) << PIO_LSR_P1_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P1(value) (PIO_LSR_P1_Msk & ((value) << PIO_LSR_P1_Pos)) +#define PIO_LSR_P2_Pos _U_(2) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P2_Msk (_U_(0x1) << PIO_LSR_P2_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P2(value) (PIO_LSR_P2_Msk & ((value) << PIO_LSR_P2_Pos)) +#define PIO_LSR_P3_Pos _U_(3) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P3_Msk (_U_(0x1) << PIO_LSR_P3_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P3(value) (PIO_LSR_P3_Msk & ((value) << PIO_LSR_P3_Pos)) +#define PIO_LSR_P4_Pos _U_(4) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P4_Msk (_U_(0x1) << PIO_LSR_P4_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P4(value) (PIO_LSR_P4_Msk & ((value) << PIO_LSR_P4_Pos)) +#define PIO_LSR_P5_Pos _U_(5) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P5_Msk (_U_(0x1) << PIO_LSR_P5_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P5(value) (PIO_LSR_P5_Msk & ((value) << PIO_LSR_P5_Pos)) +#define PIO_LSR_P6_Pos _U_(6) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P6_Msk (_U_(0x1) << PIO_LSR_P6_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P6(value) (PIO_LSR_P6_Msk & ((value) << PIO_LSR_P6_Pos)) +#define PIO_LSR_P7_Pos _U_(7) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P7_Msk (_U_(0x1) << PIO_LSR_P7_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P7(value) (PIO_LSR_P7_Msk & ((value) << PIO_LSR_P7_Pos)) +#define PIO_LSR_P8_Pos _U_(8) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P8_Msk (_U_(0x1) << PIO_LSR_P8_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P8(value) (PIO_LSR_P8_Msk & ((value) << PIO_LSR_P8_Pos)) +#define PIO_LSR_P9_Pos _U_(9) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P9_Msk (_U_(0x1) << PIO_LSR_P9_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P9(value) (PIO_LSR_P9_Msk & ((value) << PIO_LSR_P9_Pos)) +#define PIO_LSR_P10_Pos _U_(10) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P10_Msk (_U_(0x1) << PIO_LSR_P10_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P10(value) (PIO_LSR_P10_Msk & ((value) << PIO_LSR_P10_Pos)) +#define PIO_LSR_P11_Pos _U_(11) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P11_Msk (_U_(0x1) << PIO_LSR_P11_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P11(value) (PIO_LSR_P11_Msk & ((value) << PIO_LSR_P11_Pos)) +#define PIO_LSR_P12_Pos _U_(12) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P12_Msk (_U_(0x1) << PIO_LSR_P12_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P12(value) (PIO_LSR_P12_Msk & ((value) << PIO_LSR_P12_Pos)) +#define PIO_LSR_P13_Pos _U_(13) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P13_Msk (_U_(0x1) << PIO_LSR_P13_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P13(value) (PIO_LSR_P13_Msk & ((value) << PIO_LSR_P13_Pos)) +#define PIO_LSR_P14_Pos _U_(14) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P14_Msk (_U_(0x1) << PIO_LSR_P14_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P14(value) (PIO_LSR_P14_Msk & ((value) << PIO_LSR_P14_Pos)) +#define PIO_LSR_P15_Pos _U_(15) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P15_Msk (_U_(0x1) << PIO_LSR_P15_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P15(value) (PIO_LSR_P15_Msk & ((value) << PIO_LSR_P15_Pos)) +#define PIO_LSR_P16_Pos _U_(16) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P16_Msk (_U_(0x1) << PIO_LSR_P16_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P16(value) (PIO_LSR_P16_Msk & ((value) << PIO_LSR_P16_Pos)) +#define PIO_LSR_P17_Pos _U_(17) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P17_Msk (_U_(0x1) << PIO_LSR_P17_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P17(value) (PIO_LSR_P17_Msk & ((value) << PIO_LSR_P17_Pos)) +#define PIO_LSR_P18_Pos _U_(18) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P18_Msk (_U_(0x1) << PIO_LSR_P18_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P18(value) (PIO_LSR_P18_Msk & ((value) << PIO_LSR_P18_Pos)) +#define PIO_LSR_P19_Pos _U_(19) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P19_Msk (_U_(0x1) << PIO_LSR_P19_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P19(value) (PIO_LSR_P19_Msk & ((value) << PIO_LSR_P19_Pos)) +#define PIO_LSR_P20_Pos _U_(20) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P20_Msk (_U_(0x1) << PIO_LSR_P20_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P20(value) (PIO_LSR_P20_Msk & ((value) << PIO_LSR_P20_Pos)) +#define PIO_LSR_P21_Pos _U_(21) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P21_Msk (_U_(0x1) << PIO_LSR_P21_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P21(value) (PIO_LSR_P21_Msk & ((value) << PIO_LSR_P21_Pos)) +#define PIO_LSR_P22_Pos _U_(22) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P22_Msk (_U_(0x1) << PIO_LSR_P22_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P22(value) (PIO_LSR_P22_Msk & ((value) << PIO_LSR_P22_Pos)) +#define PIO_LSR_P23_Pos _U_(23) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P23_Msk (_U_(0x1) << PIO_LSR_P23_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P23(value) (PIO_LSR_P23_Msk & ((value) << PIO_LSR_P23_Pos)) +#define PIO_LSR_P24_Pos _U_(24) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P24_Msk (_U_(0x1) << PIO_LSR_P24_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P24(value) (PIO_LSR_P24_Msk & ((value) << PIO_LSR_P24_Pos)) +#define PIO_LSR_P25_Pos _U_(25) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P25_Msk (_U_(0x1) << PIO_LSR_P25_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P25(value) (PIO_LSR_P25_Msk & ((value) << PIO_LSR_P25_Pos)) +#define PIO_LSR_P26_Pos _U_(26) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P26_Msk (_U_(0x1) << PIO_LSR_P26_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P26(value) (PIO_LSR_P26_Msk & ((value) << PIO_LSR_P26_Pos)) +#define PIO_LSR_P27_Pos _U_(27) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P27_Msk (_U_(0x1) << PIO_LSR_P27_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P27(value) (PIO_LSR_P27_Msk & ((value) << PIO_LSR_P27_Pos)) +#define PIO_LSR_P28_Pos _U_(28) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P28_Msk (_U_(0x1) << PIO_LSR_P28_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P28(value) (PIO_LSR_P28_Msk & ((value) << PIO_LSR_P28_Pos)) +#define PIO_LSR_P29_Pos _U_(29) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P29_Msk (_U_(0x1) << PIO_LSR_P29_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P29(value) (PIO_LSR_P29_Msk & ((value) << PIO_LSR_P29_Pos)) +#define PIO_LSR_P30_Pos _U_(30) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P30_Msk (_U_(0x1) << PIO_LSR_P30_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P30(value) (PIO_LSR_P30_Msk & ((value) << PIO_LSR_P30_Pos)) +#define PIO_LSR_P31_Pos _U_(31) /**< (PIO_LSR) Level Interrupt Selection Position */ +#define PIO_LSR_P31_Msk (_U_(0x1) << PIO_LSR_P31_Pos) /**< (PIO_LSR) Level Interrupt Selection Mask */ +#define PIO_LSR_P31(value) (PIO_LSR_P31_Msk & ((value) << PIO_LSR_P31_Pos)) +#define PIO_LSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LSR) Register Mask */ + +#define PIO_LSR_P_Pos _U_(0) /**< (PIO_LSR Position) Level Interrupt Selection */ +#define PIO_LSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LSR_P_Pos) /**< (PIO_LSR Mask) P */ +#define PIO_LSR_P(value) (PIO_LSR_P_Msk & ((value) << PIO_LSR_P_Pos)) + +/* -------- PIO_ELSR : (PIO Offset: 0xC8) ( R/ 32) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0_Pos _U_(0) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P0_Msk (_U_(0x1) << PIO_ELSR_P0_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P0(value) (PIO_ELSR_P0_Msk & ((value) << PIO_ELSR_P0_Pos)) +#define PIO_ELSR_P1_Pos _U_(1) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P1_Msk (_U_(0x1) << PIO_ELSR_P1_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P1(value) (PIO_ELSR_P1_Msk & ((value) << PIO_ELSR_P1_Pos)) +#define PIO_ELSR_P2_Pos _U_(2) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P2_Msk (_U_(0x1) << PIO_ELSR_P2_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P2(value) (PIO_ELSR_P2_Msk & ((value) << PIO_ELSR_P2_Pos)) +#define PIO_ELSR_P3_Pos _U_(3) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P3_Msk (_U_(0x1) << PIO_ELSR_P3_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P3(value) (PIO_ELSR_P3_Msk & ((value) << PIO_ELSR_P3_Pos)) +#define PIO_ELSR_P4_Pos _U_(4) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P4_Msk (_U_(0x1) << PIO_ELSR_P4_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P4(value) (PIO_ELSR_P4_Msk & ((value) << PIO_ELSR_P4_Pos)) +#define PIO_ELSR_P5_Pos _U_(5) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P5_Msk (_U_(0x1) << PIO_ELSR_P5_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P5(value) (PIO_ELSR_P5_Msk & ((value) << PIO_ELSR_P5_Pos)) +#define PIO_ELSR_P6_Pos _U_(6) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P6_Msk (_U_(0x1) << PIO_ELSR_P6_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P6(value) (PIO_ELSR_P6_Msk & ((value) << PIO_ELSR_P6_Pos)) +#define PIO_ELSR_P7_Pos _U_(7) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P7_Msk (_U_(0x1) << PIO_ELSR_P7_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P7(value) (PIO_ELSR_P7_Msk & ((value) << PIO_ELSR_P7_Pos)) +#define PIO_ELSR_P8_Pos _U_(8) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P8_Msk (_U_(0x1) << PIO_ELSR_P8_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P8(value) (PIO_ELSR_P8_Msk & ((value) << PIO_ELSR_P8_Pos)) +#define PIO_ELSR_P9_Pos _U_(9) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P9_Msk (_U_(0x1) << PIO_ELSR_P9_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P9(value) (PIO_ELSR_P9_Msk & ((value) << PIO_ELSR_P9_Pos)) +#define PIO_ELSR_P10_Pos _U_(10) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P10_Msk (_U_(0x1) << PIO_ELSR_P10_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P10(value) (PIO_ELSR_P10_Msk & ((value) << PIO_ELSR_P10_Pos)) +#define PIO_ELSR_P11_Pos _U_(11) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P11_Msk (_U_(0x1) << PIO_ELSR_P11_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P11(value) (PIO_ELSR_P11_Msk & ((value) << PIO_ELSR_P11_Pos)) +#define PIO_ELSR_P12_Pos _U_(12) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P12_Msk (_U_(0x1) << PIO_ELSR_P12_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P12(value) (PIO_ELSR_P12_Msk & ((value) << PIO_ELSR_P12_Pos)) +#define PIO_ELSR_P13_Pos _U_(13) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P13_Msk (_U_(0x1) << PIO_ELSR_P13_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P13(value) (PIO_ELSR_P13_Msk & ((value) << PIO_ELSR_P13_Pos)) +#define PIO_ELSR_P14_Pos _U_(14) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P14_Msk (_U_(0x1) << PIO_ELSR_P14_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P14(value) (PIO_ELSR_P14_Msk & ((value) << PIO_ELSR_P14_Pos)) +#define PIO_ELSR_P15_Pos _U_(15) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P15_Msk (_U_(0x1) << PIO_ELSR_P15_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P15(value) (PIO_ELSR_P15_Msk & ((value) << PIO_ELSR_P15_Pos)) +#define PIO_ELSR_P16_Pos _U_(16) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P16_Msk (_U_(0x1) << PIO_ELSR_P16_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P16(value) (PIO_ELSR_P16_Msk & ((value) << PIO_ELSR_P16_Pos)) +#define PIO_ELSR_P17_Pos _U_(17) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P17_Msk (_U_(0x1) << PIO_ELSR_P17_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P17(value) (PIO_ELSR_P17_Msk & ((value) << PIO_ELSR_P17_Pos)) +#define PIO_ELSR_P18_Pos _U_(18) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P18_Msk (_U_(0x1) << PIO_ELSR_P18_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P18(value) (PIO_ELSR_P18_Msk & ((value) << PIO_ELSR_P18_Pos)) +#define PIO_ELSR_P19_Pos _U_(19) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P19_Msk (_U_(0x1) << PIO_ELSR_P19_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P19(value) (PIO_ELSR_P19_Msk & ((value) << PIO_ELSR_P19_Pos)) +#define PIO_ELSR_P20_Pos _U_(20) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P20_Msk (_U_(0x1) << PIO_ELSR_P20_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P20(value) (PIO_ELSR_P20_Msk & ((value) << PIO_ELSR_P20_Pos)) +#define PIO_ELSR_P21_Pos _U_(21) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P21_Msk (_U_(0x1) << PIO_ELSR_P21_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P21(value) (PIO_ELSR_P21_Msk & ((value) << PIO_ELSR_P21_Pos)) +#define PIO_ELSR_P22_Pos _U_(22) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P22_Msk (_U_(0x1) << PIO_ELSR_P22_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P22(value) (PIO_ELSR_P22_Msk & ((value) << PIO_ELSR_P22_Pos)) +#define PIO_ELSR_P23_Pos _U_(23) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P23_Msk (_U_(0x1) << PIO_ELSR_P23_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P23(value) (PIO_ELSR_P23_Msk & ((value) << PIO_ELSR_P23_Pos)) +#define PIO_ELSR_P24_Pos _U_(24) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P24_Msk (_U_(0x1) << PIO_ELSR_P24_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P24(value) (PIO_ELSR_P24_Msk & ((value) << PIO_ELSR_P24_Pos)) +#define PIO_ELSR_P25_Pos _U_(25) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P25_Msk (_U_(0x1) << PIO_ELSR_P25_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P25(value) (PIO_ELSR_P25_Msk & ((value) << PIO_ELSR_P25_Pos)) +#define PIO_ELSR_P26_Pos _U_(26) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P26_Msk (_U_(0x1) << PIO_ELSR_P26_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P26(value) (PIO_ELSR_P26_Msk & ((value) << PIO_ELSR_P26_Pos)) +#define PIO_ELSR_P27_Pos _U_(27) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P27_Msk (_U_(0x1) << PIO_ELSR_P27_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P27(value) (PIO_ELSR_P27_Msk & ((value) << PIO_ELSR_P27_Pos)) +#define PIO_ELSR_P28_Pos _U_(28) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P28_Msk (_U_(0x1) << PIO_ELSR_P28_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P28(value) (PIO_ELSR_P28_Msk & ((value) << PIO_ELSR_P28_Pos)) +#define PIO_ELSR_P29_Pos _U_(29) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P29_Msk (_U_(0x1) << PIO_ELSR_P29_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P29(value) (PIO_ELSR_P29_Msk & ((value) << PIO_ELSR_P29_Pos)) +#define PIO_ELSR_P30_Pos _U_(30) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P30_Msk (_U_(0x1) << PIO_ELSR_P30_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P30(value) (PIO_ELSR_P30_Msk & ((value) << PIO_ELSR_P30_Pos)) +#define PIO_ELSR_P31_Pos _U_(31) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_ELSR_P31_Msk (_U_(0x1) << PIO_ELSR_P31_Pos) /**< (PIO_ELSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_ELSR_P31(value) (PIO_ELSR_P31_Msk & ((value) << PIO_ELSR_P31_Pos)) +#define PIO_ELSR_Msk _U_(0xFFFFFFFF) /**< (PIO_ELSR) Register Mask */ + +#define PIO_ELSR_P_Pos _U_(0) /**< (PIO_ELSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P_Msk (_U_(0xFFFFFFFF) << PIO_ELSR_P_Pos) /**< (PIO_ELSR Mask) P */ +#define PIO_ELSR_P(value) (PIO_ELSR_P_Msk & ((value) << PIO_ELSR_P_Pos)) + +/* -------- PIO_FELLSR : (PIO Offset: 0xD0) ( /W 32) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0_Pos _U_(0) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P0_Msk (_U_(0x1) << PIO_FELLSR_P0_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P0(value) (PIO_FELLSR_P0_Msk & ((value) << PIO_FELLSR_P0_Pos)) +#define PIO_FELLSR_P1_Pos _U_(1) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P1_Msk (_U_(0x1) << PIO_FELLSR_P1_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P1(value) (PIO_FELLSR_P1_Msk & ((value) << PIO_FELLSR_P1_Pos)) +#define PIO_FELLSR_P2_Pos _U_(2) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P2_Msk (_U_(0x1) << PIO_FELLSR_P2_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P2(value) (PIO_FELLSR_P2_Msk & ((value) << PIO_FELLSR_P2_Pos)) +#define PIO_FELLSR_P3_Pos _U_(3) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P3_Msk (_U_(0x1) << PIO_FELLSR_P3_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P3(value) (PIO_FELLSR_P3_Msk & ((value) << PIO_FELLSR_P3_Pos)) +#define PIO_FELLSR_P4_Pos _U_(4) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P4_Msk (_U_(0x1) << PIO_FELLSR_P4_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P4(value) (PIO_FELLSR_P4_Msk & ((value) << PIO_FELLSR_P4_Pos)) +#define PIO_FELLSR_P5_Pos _U_(5) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P5_Msk (_U_(0x1) << PIO_FELLSR_P5_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P5(value) (PIO_FELLSR_P5_Msk & ((value) << PIO_FELLSR_P5_Pos)) +#define PIO_FELLSR_P6_Pos _U_(6) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P6_Msk (_U_(0x1) << PIO_FELLSR_P6_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P6(value) (PIO_FELLSR_P6_Msk & ((value) << PIO_FELLSR_P6_Pos)) +#define PIO_FELLSR_P7_Pos _U_(7) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P7_Msk (_U_(0x1) << PIO_FELLSR_P7_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P7(value) (PIO_FELLSR_P7_Msk & ((value) << PIO_FELLSR_P7_Pos)) +#define PIO_FELLSR_P8_Pos _U_(8) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P8_Msk (_U_(0x1) << PIO_FELLSR_P8_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P8(value) (PIO_FELLSR_P8_Msk & ((value) << PIO_FELLSR_P8_Pos)) +#define PIO_FELLSR_P9_Pos _U_(9) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P9_Msk (_U_(0x1) << PIO_FELLSR_P9_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P9(value) (PIO_FELLSR_P9_Msk & ((value) << PIO_FELLSR_P9_Pos)) +#define PIO_FELLSR_P10_Pos _U_(10) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P10_Msk (_U_(0x1) << PIO_FELLSR_P10_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P10(value) (PIO_FELLSR_P10_Msk & ((value) << PIO_FELLSR_P10_Pos)) +#define PIO_FELLSR_P11_Pos _U_(11) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P11_Msk (_U_(0x1) << PIO_FELLSR_P11_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P11(value) (PIO_FELLSR_P11_Msk & ((value) << PIO_FELLSR_P11_Pos)) +#define PIO_FELLSR_P12_Pos _U_(12) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P12_Msk (_U_(0x1) << PIO_FELLSR_P12_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P12(value) (PIO_FELLSR_P12_Msk & ((value) << PIO_FELLSR_P12_Pos)) +#define PIO_FELLSR_P13_Pos _U_(13) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P13_Msk (_U_(0x1) << PIO_FELLSR_P13_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P13(value) (PIO_FELLSR_P13_Msk & ((value) << PIO_FELLSR_P13_Pos)) +#define PIO_FELLSR_P14_Pos _U_(14) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P14_Msk (_U_(0x1) << PIO_FELLSR_P14_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P14(value) (PIO_FELLSR_P14_Msk & ((value) << PIO_FELLSR_P14_Pos)) +#define PIO_FELLSR_P15_Pos _U_(15) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P15_Msk (_U_(0x1) << PIO_FELLSR_P15_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P15(value) (PIO_FELLSR_P15_Msk & ((value) << PIO_FELLSR_P15_Pos)) +#define PIO_FELLSR_P16_Pos _U_(16) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P16_Msk (_U_(0x1) << PIO_FELLSR_P16_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P16(value) (PIO_FELLSR_P16_Msk & ((value) << PIO_FELLSR_P16_Pos)) +#define PIO_FELLSR_P17_Pos _U_(17) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P17_Msk (_U_(0x1) << PIO_FELLSR_P17_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P17(value) (PIO_FELLSR_P17_Msk & ((value) << PIO_FELLSR_P17_Pos)) +#define PIO_FELLSR_P18_Pos _U_(18) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P18_Msk (_U_(0x1) << PIO_FELLSR_P18_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P18(value) (PIO_FELLSR_P18_Msk & ((value) << PIO_FELLSR_P18_Pos)) +#define PIO_FELLSR_P19_Pos _U_(19) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P19_Msk (_U_(0x1) << PIO_FELLSR_P19_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P19(value) (PIO_FELLSR_P19_Msk & ((value) << PIO_FELLSR_P19_Pos)) +#define PIO_FELLSR_P20_Pos _U_(20) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P20_Msk (_U_(0x1) << PIO_FELLSR_P20_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P20(value) (PIO_FELLSR_P20_Msk & ((value) << PIO_FELLSR_P20_Pos)) +#define PIO_FELLSR_P21_Pos _U_(21) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P21_Msk (_U_(0x1) << PIO_FELLSR_P21_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P21(value) (PIO_FELLSR_P21_Msk & ((value) << PIO_FELLSR_P21_Pos)) +#define PIO_FELLSR_P22_Pos _U_(22) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P22_Msk (_U_(0x1) << PIO_FELLSR_P22_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P22(value) (PIO_FELLSR_P22_Msk & ((value) << PIO_FELLSR_P22_Pos)) +#define PIO_FELLSR_P23_Pos _U_(23) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P23_Msk (_U_(0x1) << PIO_FELLSR_P23_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P23(value) (PIO_FELLSR_P23_Msk & ((value) << PIO_FELLSR_P23_Pos)) +#define PIO_FELLSR_P24_Pos _U_(24) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P24_Msk (_U_(0x1) << PIO_FELLSR_P24_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P24(value) (PIO_FELLSR_P24_Msk & ((value) << PIO_FELLSR_P24_Pos)) +#define PIO_FELLSR_P25_Pos _U_(25) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P25_Msk (_U_(0x1) << PIO_FELLSR_P25_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P25(value) (PIO_FELLSR_P25_Msk & ((value) << PIO_FELLSR_P25_Pos)) +#define PIO_FELLSR_P26_Pos _U_(26) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P26_Msk (_U_(0x1) << PIO_FELLSR_P26_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P26(value) (PIO_FELLSR_P26_Msk & ((value) << PIO_FELLSR_P26_Pos)) +#define PIO_FELLSR_P27_Pos _U_(27) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P27_Msk (_U_(0x1) << PIO_FELLSR_P27_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P27(value) (PIO_FELLSR_P27_Msk & ((value) << PIO_FELLSR_P27_Pos)) +#define PIO_FELLSR_P28_Pos _U_(28) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P28_Msk (_U_(0x1) << PIO_FELLSR_P28_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P28(value) (PIO_FELLSR_P28_Msk & ((value) << PIO_FELLSR_P28_Pos)) +#define PIO_FELLSR_P29_Pos _U_(29) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P29_Msk (_U_(0x1) << PIO_FELLSR_P29_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P29(value) (PIO_FELLSR_P29_Msk & ((value) << PIO_FELLSR_P29_Pos)) +#define PIO_FELLSR_P30_Pos _U_(30) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P30_Msk (_U_(0x1) << PIO_FELLSR_P30_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P30(value) (PIO_FELLSR_P30_Msk & ((value) << PIO_FELLSR_P30_Pos)) +#define PIO_FELLSR_P31_Pos _U_(31) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Position */ +#define PIO_FELLSR_P31_Msk (_U_(0x1) << PIO_FELLSR_P31_Pos) /**< (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection Mask */ +#define PIO_FELLSR_P31(value) (PIO_FELLSR_P31_Msk & ((value) << PIO_FELLSR_P31_Pos)) +#define PIO_FELLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FELLSR) Register Mask */ + +#define PIO_FELLSR_P_Pos _U_(0) /**< (PIO_FELLSR Position) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FELLSR_P_Pos) /**< (PIO_FELLSR Mask) P */ +#define PIO_FELLSR_P(value) (PIO_FELLSR_P_Msk & ((value) << PIO_FELLSR_P_Pos)) + +/* -------- PIO_REHLSR : (PIO Offset: 0xD4) ( /W 32) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0_Pos _U_(0) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P0_Msk (_U_(0x1) << PIO_REHLSR_P0_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P0(value) (PIO_REHLSR_P0_Msk & ((value) << PIO_REHLSR_P0_Pos)) +#define PIO_REHLSR_P1_Pos _U_(1) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P1_Msk (_U_(0x1) << PIO_REHLSR_P1_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P1(value) (PIO_REHLSR_P1_Msk & ((value) << PIO_REHLSR_P1_Pos)) +#define PIO_REHLSR_P2_Pos _U_(2) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P2_Msk (_U_(0x1) << PIO_REHLSR_P2_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P2(value) (PIO_REHLSR_P2_Msk & ((value) << PIO_REHLSR_P2_Pos)) +#define PIO_REHLSR_P3_Pos _U_(3) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P3_Msk (_U_(0x1) << PIO_REHLSR_P3_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P3(value) (PIO_REHLSR_P3_Msk & ((value) << PIO_REHLSR_P3_Pos)) +#define PIO_REHLSR_P4_Pos _U_(4) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P4_Msk (_U_(0x1) << PIO_REHLSR_P4_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P4(value) (PIO_REHLSR_P4_Msk & ((value) << PIO_REHLSR_P4_Pos)) +#define PIO_REHLSR_P5_Pos _U_(5) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P5_Msk (_U_(0x1) << PIO_REHLSR_P5_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P5(value) (PIO_REHLSR_P5_Msk & ((value) << PIO_REHLSR_P5_Pos)) +#define PIO_REHLSR_P6_Pos _U_(6) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P6_Msk (_U_(0x1) << PIO_REHLSR_P6_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P6(value) (PIO_REHLSR_P6_Msk & ((value) << PIO_REHLSR_P6_Pos)) +#define PIO_REHLSR_P7_Pos _U_(7) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P7_Msk (_U_(0x1) << PIO_REHLSR_P7_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P7(value) (PIO_REHLSR_P7_Msk & ((value) << PIO_REHLSR_P7_Pos)) +#define PIO_REHLSR_P8_Pos _U_(8) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P8_Msk (_U_(0x1) << PIO_REHLSR_P8_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P8(value) (PIO_REHLSR_P8_Msk & ((value) << PIO_REHLSR_P8_Pos)) +#define PIO_REHLSR_P9_Pos _U_(9) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P9_Msk (_U_(0x1) << PIO_REHLSR_P9_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P9(value) (PIO_REHLSR_P9_Msk & ((value) << PIO_REHLSR_P9_Pos)) +#define PIO_REHLSR_P10_Pos _U_(10) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P10_Msk (_U_(0x1) << PIO_REHLSR_P10_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P10(value) (PIO_REHLSR_P10_Msk & ((value) << PIO_REHLSR_P10_Pos)) +#define PIO_REHLSR_P11_Pos _U_(11) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P11_Msk (_U_(0x1) << PIO_REHLSR_P11_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P11(value) (PIO_REHLSR_P11_Msk & ((value) << PIO_REHLSR_P11_Pos)) +#define PIO_REHLSR_P12_Pos _U_(12) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P12_Msk (_U_(0x1) << PIO_REHLSR_P12_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P12(value) (PIO_REHLSR_P12_Msk & ((value) << PIO_REHLSR_P12_Pos)) +#define PIO_REHLSR_P13_Pos _U_(13) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P13_Msk (_U_(0x1) << PIO_REHLSR_P13_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P13(value) (PIO_REHLSR_P13_Msk & ((value) << PIO_REHLSR_P13_Pos)) +#define PIO_REHLSR_P14_Pos _U_(14) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P14_Msk (_U_(0x1) << PIO_REHLSR_P14_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P14(value) (PIO_REHLSR_P14_Msk & ((value) << PIO_REHLSR_P14_Pos)) +#define PIO_REHLSR_P15_Pos _U_(15) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P15_Msk (_U_(0x1) << PIO_REHLSR_P15_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P15(value) (PIO_REHLSR_P15_Msk & ((value) << PIO_REHLSR_P15_Pos)) +#define PIO_REHLSR_P16_Pos _U_(16) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P16_Msk (_U_(0x1) << PIO_REHLSR_P16_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P16(value) (PIO_REHLSR_P16_Msk & ((value) << PIO_REHLSR_P16_Pos)) +#define PIO_REHLSR_P17_Pos _U_(17) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P17_Msk (_U_(0x1) << PIO_REHLSR_P17_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P17(value) (PIO_REHLSR_P17_Msk & ((value) << PIO_REHLSR_P17_Pos)) +#define PIO_REHLSR_P18_Pos _U_(18) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P18_Msk (_U_(0x1) << PIO_REHLSR_P18_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P18(value) (PIO_REHLSR_P18_Msk & ((value) << PIO_REHLSR_P18_Pos)) +#define PIO_REHLSR_P19_Pos _U_(19) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P19_Msk (_U_(0x1) << PIO_REHLSR_P19_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P19(value) (PIO_REHLSR_P19_Msk & ((value) << PIO_REHLSR_P19_Pos)) +#define PIO_REHLSR_P20_Pos _U_(20) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P20_Msk (_U_(0x1) << PIO_REHLSR_P20_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P20(value) (PIO_REHLSR_P20_Msk & ((value) << PIO_REHLSR_P20_Pos)) +#define PIO_REHLSR_P21_Pos _U_(21) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P21_Msk (_U_(0x1) << PIO_REHLSR_P21_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P21(value) (PIO_REHLSR_P21_Msk & ((value) << PIO_REHLSR_P21_Pos)) +#define PIO_REHLSR_P22_Pos _U_(22) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P22_Msk (_U_(0x1) << PIO_REHLSR_P22_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P22(value) (PIO_REHLSR_P22_Msk & ((value) << PIO_REHLSR_P22_Pos)) +#define PIO_REHLSR_P23_Pos _U_(23) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P23_Msk (_U_(0x1) << PIO_REHLSR_P23_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P23(value) (PIO_REHLSR_P23_Msk & ((value) << PIO_REHLSR_P23_Pos)) +#define PIO_REHLSR_P24_Pos _U_(24) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P24_Msk (_U_(0x1) << PIO_REHLSR_P24_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P24(value) (PIO_REHLSR_P24_Msk & ((value) << PIO_REHLSR_P24_Pos)) +#define PIO_REHLSR_P25_Pos _U_(25) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P25_Msk (_U_(0x1) << PIO_REHLSR_P25_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P25(value) (PIO_REHLSR_P25_Msk & ((value) << PIO_REHLSR_P25_Pos)) +#define PIO_REHLSR_P26_Pos _U_(26) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P26_Msk (_U_(0x1) << PIO_REHLSR_P26_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P26(value) (PIO_REHLSR_P26_Msk & ((value) << PIO_REHLSR_P26_Pos)) +#define PIO_REHLSR_P27_Pos _U_(27) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P27_Msk (_U_(0x1) << PIO_REHLSR_P27_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P27(value) (PIO_REHLSR_P27_Msk & ((value) << PIO_REHLSR_P27_Pos)) +#define PIO_REHLSR_P28_Pos _U_(28) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P28_Msk (_U_(0x1) << PIO_REHLSR_P28_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P28(value) (PIO_REHLSR_P28_Msk & ((value) << PIO_REHLSR_P28_Pos)) +#define PIO_REHLSR_P29_Pos _U_(29) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P29_Msk (_U_(0x1) << PIO_REHLSR_P29_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P29(value) (PIO_REHLSR_P29_Msk & ((value) << PIO_REHLSR_P29_Pos)) +#define PIO_REHLSR_P30_Pos _U_(30) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P30_Msk (_U_(0x1) << PIO_REHLSR_P30_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P30(value) (PIO_REHLSR_P30_Msk & ((value) << PIO_REHLSR_P30_Pos)) +#define PIO_REHLSR_P31_Pos _U_(31) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Position */ +#define PIO_REHLSR_P31_Msk (_U_(0x1) << PIO_REHLSR_P31_Pos) /**< (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection Mask */ +#define PIO_REHLSR_P31(value) (PIO_REHLSR_P31_Msk & ((value) << PIO_REHLSR_P31_Pos)) +#define PIO_REHLSR_Msk _U_(0xFFFFFFFF) /**< (PIO_REHLSR) Register Mask */ + +#define PIO_REHLSR_P_Pos _U_(0) /**< (PIO_REHLSR Position) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P_Msk (_U_(0xFFFFFFFF) << PIO_REHLSR_P_Pos) /**< (PIO_REHLSR Mask) P */ +#define PIO_REHLSR_P(value) (PIO_REHLSR_P_Msk & ((value) << PIO_REHLSR_P_Pos)) + +/* -------- PIO_FRLHSR : (PIO Offset: 0xD8) ( R/ 32) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0_Pos _U_(0) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P0_Msk (_U_(0x1) << PIO_FRLHSR_P0_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P0(value) (PIO_FRLHSR_P0_Msk & ((value) << PIO_FRLHSR_P0_Pos)) +#define PIO_FRLHSR_P1_Pos _U_(1) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P1_Msk (_U_(0x1) << PIO_FRLHSR_P1_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P1(value) (PIO_FRLHSR_P1_Msk & ((value) << PIO_FRLHSR_P1_Pos)) +#define PIO_FRLHSR_P2_Pos _U_(2) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P2_Msk (_U_(0x1) << PIO_FRLHSR_P2_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P2(value) (PIO_FRLHSR_P2_Msk & ((value) << PIO_FRLHSR_P2_Pos)) +#define PIO_FRLHSR_P3_Pos _U_(3) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P3_Msk (_U_(0x1) << PIO_FRLHSR_P3_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P3(value) (PIO_FRLHSR_P3_Msk & ((value) << PIO_FRLHSR_P3_Pos)) +#define PIO_FRLHSR_P4_Pos _U_(4) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P4_Msk (_U_(0x1) << PIO_FRLHSR_P4_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P4(value) (PIO_FRLHSR_P4_Msk & ((value) << PIO_FRLHSR_P4_Pos)) +#define PIO_FRLHSR_P5_Pos _U_(5) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P5_Msk (_U_(0x1) << PIO_FRLHSR_P5_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P5(value) (PIO_FRLHSR_P5_Msk & ((value) << PIO_FRLHSR_P5_Pos)) +#define PIO_FRLHSR_P6_Pos _U_(6) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P6_Msk (_U_(0x1) << PIO_FRLHSR_P6_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P6(value) (PIO_FRLHSR_P6_Msk & ((value) << PIO_FRLHSR_P6_Pos)) +#define PIO_FRLHSR_P7_Pos _U_(7) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P7_Msk (_U_(0x1) << PIO_FRLHSR_P7_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P7(value) (PIO_FRLHSR_P7_Msk & ((value) << PIO_FRLHSR_P7_Pos)) +#define PIO_FRLHSR_P8_Pos _U_(8) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P8_Msk (_U_(0x1) << PIO_FRLHSR_P8_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P8(value) (PIO_FRLHSR_P8_Msk & ((value) << PIO_FRLHSR_P8_Pos)) +#define PIO_FRLHSR_P9_Pos _U_(9) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P9_Msk (_U_(0x1) << PIO_FRLHSR_P9_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P9(value) (PIO_FRLHSR_P9_Msk & ((value) << PIO_FRLHSR_P9_Pos)) +#define PIO_FRLHSR_P10_Pos _U_(10) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P10_Msk (_U_(0x1) << PIO_FRLHSR_P10_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P10(value) (PIO_FRLHSR_P10_Msk & ((value) << PIO_FRLHSR_P10_Pos)) +#define PIO_FRLHSR_P11_Pos _U_(11) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P11_Msk (_U_(0x1) << PIO_FRLHSR_P11_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P11(value) (PIO_FRLHSR_P11_Msk & ((value) << PIO_FRLHSR_P11_Pos)) +#define PIO_FRLHSR_P12_Pos _U_(12) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P12_Msk (_U_(0x1) << PIO_FRLHSR_P12_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P12(value) (PIO_FRLHSR_P12_Msk & ((value) << PIO_FRLHSR_P12_Pos)) +#define PIO_FRLHSR_P13_Pos _U_(13) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P13_Msk (_U_(0x1) << PIO_FRLHSR_P13_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P13(value) (PIO_FRLHSR_P13_Msk & ((value) << PIO_FRLHSR_P13_Pos)) +#define PIO_FRLHSR_P14_Pos _U_(14) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P14_Msk (_U_(0x1) << PIO_FRLHSR_P14_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P14(value) (PIO_FRLHSR_P14_Msk & ((value) << PIO_FRLHSR_P14_Pos)) +#define PIO_FRLHSR_P15_Pos _U_(15) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P15_Msk (_U_(0x1) << PIO_FRLHSR_P15_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P15(value) (PIO_FRLHSR_P15_Msk & ((value) << PIO_FRLHSR_P15_Pos)) +#define PIO_FRLHSR_P16_Pos _U_(16) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P16_Msk (_U_(0x1) << PIO_FRLHSR_P16_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P16(value) (PIO_FRLHSR_P16_Msk & ((value) << PIO_FRLHSR_P16_Pos)) +#define PIO_FRLHSR_P17_Pos _U_(17) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P17_Msk (_U_(0x1) << PIO_FRLHSR_P17_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P17(value) (PIO_FRLHSR_P17_Msk & ((value) << PIO_FRLHSR_P17_Pos)) +#define PIO_FRLHSR_P18_Pos _U_(18) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P18_Msk (_U_(0x1) << PIO_FRLHSR_P18_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P18(value) (PIO_FRLHSR_P18_Msk & ((value) << PIO_FRLHSR_P18_Pos)) +#define PIO_FRLHSR_P19_Pos _U_(19) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P19_Msk (_U_(0x1) << PIO_FRLHSR_P19_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P19(value) (PIO_FRLHSR_P19_Msk & ((value) << PIO_FRLHSR_P19_Pos)) +#define PIO_FRLHSR_P20_Pos _U_(20) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P20_Msk (_U_(0x1) << PIO_FRLHSR_P20_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P20(value) (PIO_FRLHSR_P20_Msk & ((value) << PIO_FRLHSR_P20_Pos)) +#define PIO_FRLHSR_P21_Pos _U_(21) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P21_Msk (_U_(0x1) << PIO_FRLHSR_P21_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P21(value) (PIO_FRLHSR_P21_Msk & ((value) << PIO_FRLHSR_P21_Pos)) +#define PIO_FRLHSR_P22_Pos _U_(22) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P22_Msk (_U_(0x1) << PIO_FRLHSR_P22_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P22(value) (PIO_FRLHSR_P22_Msk & ((value) << PIO_FRLHSR_P22_Pos)) +#define PIO_FRLHSR_P23_Pos _U_(23) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P23_Msk (_U_(0x1) << PIO_FRLHSR_P23_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P23(value) (PIO_FRLHSR_P23_Msk & ((value) << PIO_FRLHSR_P23_Pos)) +#define PIO_FRLHSR_P24_Pos _U_(24) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P24_Msk (_U_(0x1) << PIO_FRLHSR_P24_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P24(value) (PIO_FRLHSR_P24_Msk & ((value) << PIO_FRLHSR_P24_Pos)) +#define PIO_FRLHSR_P25_Pos _U_(25) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P25_Msk (_U_(0x1) << PIO_FRLHSR_P25_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P25(value) (PIO_FRLHSR_P25_Msk & ((value) << PIO_FRLHSR_P25_Pos)) +#define PIO_FRLHSR_P26_Pos _U_(26) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P26_Msk (_U_(0x1) << PIO_FRLHSR_P26_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P26(value) (PIO_FRLHSR_P26_Msk & ((value) << PIO_FRLHSR_P26_Pos)) +#define PIO_FRLHSR_P27_Pos _U_(27) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P27_Msk (_U_(0x1) << PIO_FRLHSR_P27_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P27(value) (PIO_FRLHSR_P27_Msk & ((value) << PIO_FRLHSR_P27_Pos)) +#define PIO_FRLHSR_P28_Pos _U_(28) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P28_Msk (_U_(0x1) << PIO_FRLHSR_P28_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P28(value) (PIO_FRLHSR_P28_Msk & ((value) << PIO_FRLHSR_P28_Pos)) +#define PIO_FRLHSR_P29_Pos _U_(29) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P29_Msk (_U_(0x1) << PIO_FRLHSR_P29_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P29(value) (PIO_FRLHSR_P29_Msk & ((value) << PIO_FRLHSR_P29_Pos)) +#define PIO_FRLHSR_P30_Pos _U_(30) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P30_Msk (_U_(0x1) << PIO_FRLHSR_P30_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P30(value) (PIO_FRLHSR_P30_Msk & ((value) << PIO_FRLHSR_P30_Pos)) +#define PIO_FRLHSR_P31_Pos _U_(31) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Position */ +#define PIO_FRLHSR_P31_Msk (_U_(0x1) << PIO_FRLHSR_P31_Pos) /**< (PIO_FRLHSR) Edge/Level Interrupt Source Selection Mask */ +#define PIO_FRLHSR_P31(value) (PIO_FRLHSR_P31_Msk & ((value) << PIO_FRLHSR_P31_Pos)) +#define PIO_FRLHSR_Msk _U_(0xFFFFFFFF) /**< (PIO_FRLHSR) Register Mask */ + +#define PIO_FRLHSR_P_Pos _U_(0) /**< (PIO_FRLHSR Position) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P_Msk (_U_(0xFFFFFFFF) << PIO_FRLHSR_P_Pos) /**< (PIO_FRLHSR Mask) P */ +#define PIO_FRLHSR_P(value) (PIO_FRLHSR_P_Msk & ((value) << PIO_FRLHSR_P_Pos)) + +/* -------- PIO_LOCKSR : (PIO Offset: 0xE0) ( R/ 32) Lock Status -------- */ +#define PIO_LOCKSR_P0_Pos _U_(0) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P0_Msk (_U_(0x1) << PIO_LOCKSR_P0_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P0(value) (PIO_LOCKSR_P0_Msk & ((value) << PIO_LOCKSR_P0_Pos)) +#define PIO_LOCKSR_P1_Pos _U_(1) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P1_Msk (_U_(0x1) << PIO_LOCKSR_P1_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P1(value) (PIO_LOCKSR_P1_Msk & ((value) << PIO_LOCKSR_P1_Pos)) +#define PIO_LOCKSR_P2_Pos _U_(2) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P2_Msk (_U_(0x1) << PIO_LOCKSR_P2_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P2(value) (PIO_LOCKSR_P2_Msk & ((value) << PIO_LOCKSR_P2_Pos)) +#define PIO_LOCKSR_P3_Pos _U_(3) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P3_Msk (_U_(0x1) << PIO_LOCKSR_P3_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P3(value) (PIO_LOCKSR_P3_Msk & ((value) << PIO_LOCKSR_P3_Pos)) +#define PIO_LOCKSR_P4_Pos _U_(4) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P4_Msk (_U_(0x1) << PIO_LOCKSR_P4_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P4(value) (PIO_LOCKSR_P4_Msk & ((value) << PIO_LOCKSR_P4_Pos)) +#define PIO_LOCKSR_P5_Pos _U_(5) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P5_Msk (_U_(0x1) << PIO_LOCKSR_P5_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P5(value) (PIO_LOCKSR_P5_Msk & ((value) << PIO_LOCKSR_P5_Pos)) +#define PIO_LOCKSR_P6_Pos _U_(6) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P6_Msk (_U_(0x1) << PIO_LOCKSR_P6_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P6(value) (PIO_LOCKSR_P6_Msk & ((value) << PIO_LOCKSR_P6_Pos)) +#define PIO_LOCKSR_P7_Pos _U_(7) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P7_Msk (_U_(0x1) << PIO_LOCKSR_P7_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P7(value) (PIO_LOCKSR_P7_Msk & ((value) << PIO_LOCKSR_P7_Pos)) +#define PIO_LOCKSR_P8_Pos _U_(8) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P8_Msk (_U_(0x1) << PIO_LOCKSR_P8_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P8(value) (PIO_LOCKSR_P8_Msk & ((value) << PIO_LOCKSR_P8_Pos)) +#define PIO_LOCKSR_P9_Pos _U_(9) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P9_Msk (_U_(0x1) << PIO_LOCKSR_P9_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P9(value) (PIO_LOCKSR_P9_Msk & ((value) << PIO_LOCKSR_P9_Pos)) +#define PIO_LOCKSR_P10_Pos _U_(10) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P10_Msk (_U_(0x1) << PIO_LOCKSR_P10_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P10(value) (PIO_LOCKSR_P10_Msk & ((value) << PIO_LOCKSR_P10_Pos)) +#define PIO_LOCKSR_P11_Pos _U_(11) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P11_Msk (_U_(0x1) << PIO_LOCKSR_P11_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P11(value) (PIO_LOCKSR_P11_Msk & ((value) << PIO_LOCKSR_P11_Pos)) +#define PIO_LOCKSR_P12_Pos _U_(12) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P12_Msk (_U_(0x1) << PIO_LOCKSR_P12_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P12(value) (PIO_LOCKSR_P12_Msk & ((value) << PIO_LOCKSR_P12_Pos)) +#define PIO_LOCKSR_P13_Pos _U_(13) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P13_Msk (_U_(0x1) << PIO_LOCKSR_P13_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P13(value) (PIO_LOCKSR_P13_Msk & ((value) << PIO_LOCKSR_P13_Pos)) +#define PIO_LOCKSR_P14_Pos _U_(14) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P14_Msk (_U_(0x1) << PIO_LOCKSR_P14_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P14(value) (PIO_LOCKSR_P14_Msk & ((value) << PIO_LOCKSR_P14_Pos)) +#define PIO_LOCKSR_P15_Pos _U_(15) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P15_Msk (_U_(0x1) << PIO_LOCKSR_P15_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P15(value) (PIO_LOCKSR_P15_Msk & ((value) << PIO_LOCKSR_P15_Pos)) +#define PIO_LOCKSR_P16_Pos _U_(16) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P16_Msk (_U_(0x1) << PIO_LOCKSR_P16_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P16(value) (PIO_LOCKSR_P16_Msk & ((value) << PIO_LOCKSR_P16_Pos)) +#define PIO_LOCKSR_P17_Pos _U_(17) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P17_Msk (_U_(0x1) << PIO_LOCKSR_P17_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P17(value) (PIO_LOCKSR_P17_Msk & ((value) << PIO_LOCKSR_P17_Pos)) +#define PIO_LOCKSR_P18_Pos _U_(18) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P18_Msk (_U_(0x1) << PIO_LOCKSR_P18_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P18(value) (PIO_LOCKSR_P18_Msk & ((value) << PIO_LOCKSR_P18_Pos)) +#define PIO_LOCKSR_P19_Pos _U_(19) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P19_Msk (_U_(0x1) << PIO_LOCKSR_P19_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P19(value) (PIO_LOCKSR_P19_Msk & ((value) << PIO_LOCKSR_P19_Pos)) +#define PIO_LOCKSR_P20_Pos _U_(20) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P20_Msk (_U_(0x1) << PIO_LOCKSR_P20_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P20(value) (PIO_LOCKSR_P20_Msk & ((value) << PIO_LOCKSR_P20_Pos)) +#define PIO_LOCKSR_P21_Pos _U_(21) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P21_Msk (_U_(0x1) << PIO_LOCKSR_P21_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P21(value) (PIO_LOCKSR_P21_Msk & ((value) << PIO_LOCKSR_P21_Pos)) +#define PIO_LOCKSR_P22_Pos _U_(22) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P22_Msk (_U_(0x1) << PIO_LOCKSR_P22_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P22(value) (PIO_LOCKSR_P22_Msk & ((value) << PIO_LOCKSR_P22_Pos)) +#define PIO_LOCKSR_P23_Pos _U_(23) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P23_Msk (_U_(0x1) << PIO_LOCKSR_P23_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P23(value) (PIO_LOCKSR_P23_Msk & ((value) << PIO_LOCKSR_P23_Pos)) +#define PIO_LOCKSR_P24_Pos _U_(24) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P24_Msk (_U_(0x1) << PIO_LOCKSR_P24_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P24(value) (PIO_LOCKSR_P24_Msk & ((value) << PIO_LOCKSR_P24_Pos)) +#define PIO_LOCKSR_P25_Pos _U_(25) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P25_Msk (_U_(0x1) << PIO_LOCKSR_P25_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P25(value) (PIO_LOCKSR_P25_Msk & ((value) << PIO_LOCKSR_P25_Pos)) +#define PIO_LOCKSR_P26_Pos _U_(26) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P26_Msk (_U_(0x1) << PIO_LOCKSR_P26_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P26(value) (PIO_LOCKSR_P26_Msk & ((value) << PIO_LOCKSR_P26_Pos)) +#define PIO_LOCKSR_P27_Pos _U_(27) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P27_Msk (_U_(0x1) << PIO_LOCKSR_P27_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P27(value) (PIO_LOCKSR_P27_Msk & ((value) << PIO_LOCKSR_P27_Pos)) +#define PIO_LOCKSR_P28_Pos _U_(28) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P28_Msk (_U_(0x1) << PIO_LOCKSR_P28_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P28(value) (PIO_LOCKSR_P28_Msk & ((value) << PIO_LOCKSR_P28_Pos)) +#define PIO_LOCKSR_P29_Pos _U_(29) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P29_Msk (_U_(0x1) << PIO_LOCKSR_P29_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P29(value) (PIO_LOCKSR_P29_Msk & ((value) << PIO_LOCKSR_P29_Pos)) +#define PIO_LOCKSR_P30_Pos _U_(30) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P30_Msk (_U_(0x1) << PIO_LOCKSR_P30_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P30(value) (PIO_LOCKSR_P30_Msk & ((value) << PIO_LOCKSR_P30_Pos)) +#define PIO_LOCKSR_P31_Pos _U_(31) /**< (PIO_LOCKSR) Lock Status Position */ +#define PIO_LOCKSR_P31_Msk (_U_(0x1) << PIO_LOCKSR_P31_Pos) /**< (PIO_LOCKSR) Lock Status Mask */ +#define PIO_LOCKSR_P31(value) (PIO_LOCKSR_P31_Msk & ((value) << PIO_LOCKSR_P31_Pos)) +#define PIO_LOCKSR_Msk _U_(0xFFFFFFFF) /**< (PIO_LOCKSR) Register Mask */ + +#define PIO_LOCKSR_P_Pos _U_(0) /**< (PIO_LOCKSR Position) Lock Status */ +#define PIO_LOCKSR_P_Msk (_U_(0xFFFFFFFF) << PIO_LOCKSR_P_Pos) /**< (PIO_LOCKSR Mask) P */ +#define PIO_LOCKSR_P(value) (PIO_LOCKSR_P_Msk & ((value) << PIO_LOCKSR_P_Pos)) + +/* -------- PIO_WPMR : (PIO Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN_Pos _U_(0) /**< (PIO_WPMR) Write Protection Enable Position */ +#define PIO_WPMR_WPEN_Msk (_U_(0x1) << PIO_WPMR_WPEN_Pos) /**< (PIO_WPMR) Write Protection Enable Mask */ +#define PIO_WPMR_WPEN(value) (PIO_WPMR_WPEN_Msk & ((value) << PIO_WPMR_WPEN_Pos)) +#define PIO_WPMR_WPKEY_Pos _U_(8) /**< (PIO_WPMR) Write Protection Key Position */ +#define PIO_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Write Protection Key Mask */ +#define PIO_WPMR_WPKEY(value) (PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)) +#define PIO_WPMR_WPKEY_PASSWD_Val _U_(0x50494F) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define PIO_WPMR_WPKEY_PASSWD (PIO_WPMR_WPKEY_PASSWD_Val << PIO_WPMR_WPKEY_Pos) /**< (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define PIO_WPMR_Msk _U_(0xFFFFFF01) /**< (PIO_WPMR) Register Mask */ + + +/* -------- PIO_WPSR : (PIO Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS_Pos _U_(0) /**< (PIO_WPSR) Write Protection Violation Status Position */ +#define PIO_WPSR_WPVS_Msk (_U_(0x1) << PIO_WPSR_WPVS_Pos) /**< (PIO_WPSR) Write Protection Violation Status Mask */ +#define PIO_WPSR_WPVS(value) (PIO_WPSR_WPVS_Msk & ((value) << PIO_WPSR_WPVS_Pos)) +#define PIO_WPSR_WPVSRC_Pos _U_(8) /**< (PIO_WPSR) Write Protection Violation Source Position */ +#define PIO_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PIO_WPSR_WPVSRC_Pos) /**< (PIO_WPSR) Write Protection Violation Source Mask */ +#define PIO_WPSR_WPVSRC(value) (PIO_WPSR_WPVSRC_Msk & ((value) << PIO_WPSR_WPVSRC_Pos)) +#define PIO_WPSR_Msk _U_(0x00FFFF01) /**< (PIO_WPSR) Register Mask */ + + +/* -------- PIO_SCHMITT : (PIO Offset: 0x100) (R/W 32) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0_Pos _U_(0) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT0_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT0_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT0(value) (PIO_SCHMITT_SCHMITT0_Msk & ((value) << PIO_SCHMITT_SCHMITT0_Pos)) +#define PIO_SCHMITT_SCHMITT1_Pos _U_(1) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT1_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT1_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT1(value) (PIO_SCHMITT_SCHMITT1_Msk & ((value) << PIO_SCHMITT_SCHMITT1_Pos)) +#define PIO_SCHMITT_SCHMITT2_Pos _U_(2) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT2_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT2_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT2(value) (PIO_SCHMITT_SCHMITT2_Msk & ((value) << PIO_SCHMITT_SCHMITT2_Pos)) +#define PIO_SCHMITT_SCHMITT3_Pos _U_(3) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT3_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT3_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT3(value) (PIO_SCHMITT_SCHMITT3_Msk & ((value) << PIO_SCHMITT_SCHMITT3_Pos)) +#define PIO_SCHMITT_SCHMITT4_Pos _U_(4) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT4_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT4_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT4(value) (PIO_SCHMITT_SCHMITT4_Msk & ((value) << PIO_SCHMITT_SCHMITT4_Pos)) +#define PIO_SCHMITT_SCHMITT5_Pos _U_(5) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT5_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT5_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT5(value) (PIO_SCHMITT_SCHMITT5_Msk & ((value) << PIO_SCHMITT_SCHMITT5_Pos)) +#define PIO_SCHMITT_SCHMITT6_Pos _U_(6) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT6_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT6_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT6(value) (PIO_SCHMITT_SCHMITT6_Msk & ((value) << PIO_SCHMITT_SCHMITT6_Pos)) +#define PIO_SCHMITT_SCHMITT7_Pos _U_(7) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT7_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT7_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT7(value) (PIO_SCHMITT_SCHMITT7_Msk & ((value) << PIO_SCHMITT_SCHMITT7_Pos)) +#define PIO_SCHMITT_SCHMITT8_Pos _U_(8) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT8_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT8_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT8(value) (PIO_SCHMITT_SCHMITT8_Msk & ((value) << PIO_SCHMITT_SCHMITT8_Pos)) +#define PIO_SCHMITT_SCHMITT9_Pos _U_(9) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT9_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT9_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT9(value) (PIO_SCHMITT_SCHMITT9_Msk & ((value) << PIO_SCHMITT_SCHMITT9_Pos)) +#define PIO_SCHMITT_SCHMITT10_Pos _U_(10) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT10_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT10_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT10(value) (PIO_SCHMITT_SCHMITT10_Msk & ((value) << PIO_SCHMITT_SCHMITT10_Pos)) +#define PIO_SCHMITT_SCHMITT11_Pos _U_(11) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT11_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT11_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT11(value) (PIO_SCHMITT_SCHMITT11_Msk & ((value) << PIO_SCHMITT_SCHMITT11_Pos)) +#define PIO_SCHMITT_SCHMITT12_Pos _U_(12) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT12_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT12_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT12(value) (PIO_SCHMITT_SCHMITT12_Msk & ((value) << PIO_SCHMITT_SCHMITT12_Pos)) +#define PIO_SCHMITT_SCHMITT13_Pos _U_(13) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT13_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT13_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT13(value) (PIO_SCHMITT_SCHMITT13_Msk & ((value) << PIO_SCHMITT_SCHMITT13_Pos)) +#define PIO_SCHMITT_SCHMITT14_Pos _U_(14) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT14_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT14_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT14(value) (PIO_SCHMITT_SCHMITT14_Msk & ((value) << PIO_SCHMITT_SCHMITT14_Pos)) +#define PIO_SCHMITT_SCHMITT15_Pos _U_(15) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT15_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT15_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT15(value) (PIO_SCHMITT_SCHMITT15_Msk & ((value) << PIO_SCHMITT_SCHMITT15_Pos)) +#define PIO_SCHMITT_SCHMITT16_Pos _U_(16) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT16_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT16_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT16(value) (PIO_SCHMITT_SCHMITT16_Msk & ((value) << PIO_SCHMITT_SCHMITT16_Pos)) +#define PIO_SCHMITT_SCHMITT17_Pos _U_(17) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT17_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT17_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT17(value) (PIO_SCHMITT_SCHMITT17_Msk & ((value) << PIO_SCHMITT_SCHMITT17_Pos)) +#define PIO_SCHMITT_SCHMITT18_Pos _U_(18) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT18_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT18_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT18(value) (PIO_SCHMITT_SCHMITT18_Msk & ((value) << PIO_SCHMITT_SCHMITT18_Pos)) +#define PIO_SCHMITT_SCHMITT19_Pos _U_(19) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT19_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT19_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT19(value) (PIO_SCHMITT_SCHMITT19_Msk & ((value) << PIO_SCHMITT_SCHMITT19_Pos)) +#define PIO_SCHMITT_SCHMITT20_Pos _U_(20) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT20_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT20_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT20(value) (PIO_SCHMITT_SCHMITT20_Msk & ((value) << PIO_SCHMITT_SCHMITT20_Pos)) +#define PIO_SCHMITT_SCHMITT21_Pos _U_(21) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT21_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT21_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT21(value) (PIO_SCHMITT_SCHMITT21_Msk & ((value) << PIO_SCHMITT_SCHMITT21_Pos)) +#define PIO_SCHMITT_SCHMITT22_Pos _U_(22) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT22_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT22_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT22(value) (PIO_SCHMITT_SCHMITT22_Msk & ((value) << PIO_SCHMITT_SCHMITT22_Pos)) +#define PIO_SCHMITT_SCHMITT23_Pos _U_(23) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT23_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT23_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT23(value) (PIO_SCHMITT_SCHMITT23_Msk & ((value) << PIO_SCHMITT_SCHMITT23_Pos)) +#define PIO_SCHMITT_SCHMITT24_Pos _U_(24) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT24_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT24_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT24(value) (PIO_SCHMITT_SCHMITT24_Msk & ((value) << PIO_SCHMITT_SCHMITT24_Pos)) +#define PIO_SCHMITT_SCHMITT25_Pos _U_(25) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT25_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT25_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT25(value) (PIO_SCHMITT_SCHMITT25_Msk & ((value) << PIO_SCHMITT_SCHMITT25_Pos)) +#define PIO_SCHMITT_SCHMITT26_Pos _U_(26) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT26_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT26_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT26(value) (PIO_SCHMITT_SCHMITT26_Msk & ((value) << PIO_SCHMITT_SCHMITT26_Pos)) +#define PIO_SCHMITT_SCHMITT27_Pos _U_(27) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT27_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT27_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT27(value) (PIO_SCHMITT_SCHMITT27_Msk & ((value) << PIO_SCHMITT_SCHMITT27_Pos)) +#define PIO_SCHMITT_SCHMITT28_Pos _U_(28) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT28_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT28_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT28(value) (PIO_SCHMITT_SCHMITT28_Msk & ((value) << PIO_SCHMITT_SCHMITT28_Pos)) +#define PIO_SCHMITT_SCHMITT29_Pos _U_(29) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT29_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT29_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT29(value) (PIO_SCHMITT_SCHMITT29_Msk & ((value) << PIO_SCHMITT_SCHMITT29_Pos)) +#define PIO_SCHMITT_SCHMITT30_Pos _U_(30) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT30_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT30_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT30(value) (PIO_SCHMITT_SCHMITT30_Msk & ((value) << PIO_SCHMITT_SCHMITT30_Pos)) +#define PIO_SCHMITT_SCHMITT31_Pos _U_(31) /**< (PIO_SCHMITT) Schmitt Trigger Control Position */ +#define PIO_SCHMITT_SCHMITT31_Msk (_U_(0x1) << PIO_SCHMITT_SCHMITT31_Pos) /**< (PIO_SCHMITT) Schmitt Trigger Control Mask */ +#define PIO_SCHMITT_SCHMITT31(value) (PIO_SCHMITT_SCHMITT31_Msk & ((value) << PIO_SCHMITT_SCHMITT31_Pos)) +#define PIO_SCHMITT_Msk _U_(0xFFFFFFFF) /**< (PIO_SCHMITT) Register Mask */ + +#define PIO_SCHMITT_SCHMITT_Pos _U_(0) /**< (PIO_SCHMITT Position) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT_Msk (_U_(0xFFFFFFFF) << PIO_SCHMITT_SCHMITT_Pos) /**< (PIO_SCHMITT Mask) SCHMITT */ +#define PIO_SCHMITT_SCHMITT(value) (PIO_SCHMITT_SCHMITT_Msk & ((value) << PIO_SCHMITT_SCHMITT_Pos)) + +/* -------- PIO_DRIVER : (PIO Offset: 0x118) (R/W 32) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0_Pos _U_(0) /**< (PIO_DRIVER) Drive of PIO Line 0 Position */ +#define PIO_DRIVER_LINE0_Msk (_U_(0x1) << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Drive of PIO Line 0 Mask */ +#define PIO_DRIVER_LINE0(value) (PIO_DRIVER_LINE0_Msk & ((value) << PIO_DRIVER_LINE0_Pos)) +#define PIO_DRIVER_LINE0_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (PIO_DRIVER_LINE0_LOW_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (PIO_DRIVER_LINE0_HIGH_DRIVE_Val << PIO_DRIVER_LINE0_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE1_Pos _U_(1) /**< (PIO_DRIVER) Drive of PIO Line 1 Position */ +#define PIO_DRIVER_LINE1_Msk (_U_(0x1) << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Drive of PIO Line 1 Mask */ +#define PIO_DRIVER_LINE1(value) (PIO_DRIVER_LINE1_Msk & ((value) << PIO_DRIVER_LINE1_Pos)) +#define PIO_DRIVER_LINE1_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (PIO_DRIVER_LINE1_LOW_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (PIO_DRIVER_LINE1_HIGH_DRIVE_Val << PIO_DRIVER_LINE1_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE2_Pos _U_(2) /**< (PIO_DRIVER) Drive of PIO Line 2 Position */ +#define PIO_DRIVER_LINE2_Msk (_U_(0x1) << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Drive of PIO Line 2 Mask */ +#define PIO_DRIVER_LINE2(value) (PIO_DRIVER_LINE2_Msk & ((value) << PIO_DRIVER_LINE2_Pos)) +#define PIO_DRIVER_LINE2_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (PIO_DRIVER_LINE2_LOW_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (PIO_DRIVER_LINE2_HIGH_DRIVE_Val << PIO_DRIVER_LINE2_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE3_Pos _U_(3) /**< (PIO_DRIVER) Drive of PIO Line 3 Position */ +#define PIO_DRIVER_LINE3_Msk (_U_(0x1) << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Drive of PIO Line 3 Mask */ +#define PIO_DRIVER_LINE3(value) (PIO_DRIVER_LINE3_Msk & ((value) << PIO_DRIVER_LINE3_Pos)) +#define PIO_DRIVER_LINE3_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (PIO_DRIVER_LINE3_LOW_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (PIO_DRIVER_LINE3_HIGH_DRIVE_Val << PIO_DRIVER_LINE3_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE4_Pos _U_(4) /**< (PIO_DRIVER) Drive of PIO Line 4 Position */ +#define PIO_DRIVER_LINE4_Msk (_U_(0x1) << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Drive of PIO Line 4 Mask */ +#define PIO_DRIVER_LINE4(value) (PIO_DRIVER_LINE4_Msk & ((value) << PIO_DRIVER_LINE4_Pos)) +#define PIO_DRIVER_LINE4_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (PIO_DRIVER_LINE4_LOW_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (PIO_DRIVER_LINE4_HIGH_DRIVE_Val << PIO_DRIVER_LINE4_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE5_Pos _U_(5) /**< (PIO_DRIVER) Drive of PIO Line 5 Position */ +#define PIO_DRIVER_LINE5_Msk (_U_(0x1) << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Drive of PIO Line 5 Mask */ +#define PIO_DRIVER_LINE5(value) (PIO_DRIVER_LINE5_Msk & ((value) << PIO_DRIVER_LINE5_Pos)) +#define PIO_DRIVER_LINE5_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (PIO_DRIVER_LINE5_LOW_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (PIO_DRIVER_LINE5_HIGH_DRIVE_Val << PIO_DRIVER_LINE5_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE6_Pos _U_(6) /**< (PIO_DRIVER) Drive of PIO Line 6 Position */ +#define PIO_DRIVER_LINE6_Msk (_U_(0x1) << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Drive of PIO Line 6 Mask */ +#define PIO_DRIVER_LINE6(value) (PIO_DRIVER_LINE6_Msk & ((value) << PIO_DRIVER_LINE6_Pos)) +#define PIO_DRIVER_LINE6_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (PIO_DRIVER_LINE6_LOW_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (PIO_DRIVER_LINE6_HIGH_DRIVE_Val << PIO_DRIVER_LINE6_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE7_Pos _U_(7) /**< (PIO_DRIVER) Drive of PIO Line 7 Position */ +#define PIO_DRIVER_LINE7_Msk (_U_(0x1) << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Drive of PIO Line 7 Mask */ +#define PIO_DRIVER_LINE7(value) (PIO_DRIVER_LINE7_Msk & ((value) << PIO_DRIVER_LINE7_Pos)) +#define PIO_DRIVER_LINE7_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (PIO_DRIVER_LINE7_LOW_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (PIO_DRIVER_LINE7_HIGH_DRIVE_Val << PIO_DRIVER_LINE7_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE8_Pos _U_(8) /**< (PIO_DRIVER) Drive of PIO Line 8 Position */ +#define PIO_DRIVER_LINE8_Msk (_U_(0x1) << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Drive of PIO Line 8 Mask */ +#define PIO_DRIVER_LINE8(value) (PIO_DRIVER_LINE8_Msk & ((value) << PIO_DRIVER_LINE8_Pos)) +#define PIO_DRIVER_LINE8_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (PIO_DRIVER_LINE8_LOW_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (PIO_DRIVER_LINE8_HIGH_DRIVE_Val << PIO_DRIVER_LINE8_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE9_Pos _U_(9) /**< (PIO_DRIVER) Drive of PIO Line 9 Position */ +#define PIO_DRIVER_LINE9_Msk (_U_(0x1) << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Drive of PIO Line 9 Mask */ +#define PIO_DRIVER_LINE9(value) (PIO_DRIVER_LINE9_Msk & ((value) << PIO_DRIVER_LINE9_Pos)) +#define PIO_DRIVER_LINE9_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (PIO_DRIVER_LINE9_LOW_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (PIO_DRIVER_LINE9_HIGH_DRIVE_Val << PIO_DRIVER_LINE9_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE10_Pos _U_(10) /**< (PIO_DRIVER) Drive of PIO Line 10 Position */ +#define PIO_DRIVER_LINE10_Msk (_U_(0x1) << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Drive of PIO Line 10 Mask */ +#define PIO_DRIVER_LINE10(value) (PIO_DRIVER_LINE10_Msk & ((value) << PIO_DRIVER_LINE10_Pos)) +#define PIO_DRIVER_LINE10_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (PIO_DRIVER_LINE10_LOW_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (PIO_DRIVER_LINE10_HIGH_DRIVE_Val << PIO_DRIVER_LINE10_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE11_Pos _U_(11) /**< (PIO_DRIVER) Drive of PIO Line 11 Position */ +#define PIO_DRIVER_LINE11_Msk (_U_(0x1) << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Drive of PIO Line 11 Mask */ +#define PIO_DRIVER_LINE11(value) (PIO_DRIVER_LINE11_Msk & ((value) << PIO_DRIVER_LINE11_Pos)) +#define PIO_DRIVER_LINE11_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (PIO_DRIVER_LINE11_LOW_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (PIO_DRIVER_LINE11_HIGH_DRIVE_Val << PIO_DRIVER_LINE11_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE12_Pos _U_(12) /**< (PIO_DRIVER) Drive of PIO Line 12 Position */ +#define PIO_DRIVER_LINE12_Msk (_U_(0x1) << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Drive of PIO Line 12 Mask */ +#define PIO_DRIVER_LINE12(value) (PIO_DRIVER_LINE12_Msk & ((value) << PIO_DRIVER_LINE12_Pos)) +#define PIO_DRIVER_LINE12_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (PIO_DRIVER_LINE12_LOW_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (PIO_DRIVER_LINE12_HIGH_DRIVE_Val << PIO_DRIVER_LINE12_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE13_Pos _U_(13) /**< (PIO_DRIVER) Drive of PIO Line 13 Position */ +#define PIO_DRIVER_LINE13_Msk (_U_(0x1) << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Drive of PIO Line 13 Mask */ +#define PIO_DRIVER_LINE13(value) (PIO_DRIVER_LINE13_Msk & ((value) << PIO_DRIVER_LINE13_Pos)) +#define PIO_DRIVER_LINE13_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (PIO_DRIVER_LINE13_LOW_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (PIO_DRIVER_LINE13_HIGH_DRIVE_Val << PIO_DRIVER_LINE13_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE14_Pos _U_(14) /**< (PIO_DRIVER) Drive of PIO Line 14 Position */ +#define PIO_DRIVER_LINE14_Msk (_U_(0x1) << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Drive of PIO Line 14 Mask */ +#define PIO_DRIVER_LINE14(value) (PIO_DRIVER_LINE14_Msk & ((value) << PIO_DRIVER_LINE14_Pos)) +#define PIO_DRIVER_LINE14_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (PIO_DRIVER_LINE14_LOW_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (PIO_DRIVER_LINE14_HIGH_DRIVE_Val << PIO_DRIVER_LINE14_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE15_Pos _U_(15) /**< (PIO_DRIVER) Drive of PIO Line 15 Position */ +#define PIO_DRIVER_LINE15_Msk (_U_(0x1) << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Drive of PIO Line 15 Mask */ +#define PIO_DRIVER_LINE15(value) (PIO_DRIVER_LINE15_Msk & ((value) << PIO_DRIVER_LINE15_Pos)) +#define PIO_DRIVER_LINE15_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (PIO_DRIVER_LINE15_LOW_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (PIO_DRIVER_LINE15_HIGH_DRIVE_Val << PIO_DRIVER_LINE15_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE16_Pos _U_(16) /**< (PIO_DRIVER) Drive of PIO Line 16 Position */ +#define PIO_DRIVER_LINE16_Msk (_U_(0x1) << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Drive of PIO Line 16 Mask */ +#define PIO_DRIVER_LINE16(value) (PIO_DRIVER_LINE16_Msk & ((value) << PIO_DRIVER_LINE16_Pos)) +#define PIO_DRIVER_LINE16_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (PIO_DRIVER_LINE16_LOW_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (PIO_DRIVER_LINE16_HIGH_DRIVE_Val << PIO_DRIVER_LINE16_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE17_Pos _U_(17) /**< (PIO_DRIVER) Drive of PIO Line 17 Position */ +#define PIO_DRIVER_LINE17_Msk (_U_(0x1) << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Drive of PIO Line 17 Mask */ +#define PIO_DRIVER_LINE17(value) (PIO_DRIVER_LINE17_Msk & ((value) << PIO_DRIVER_LINE17_Pos)) +#define PIO_DRIVER_LINE17_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (PIO_DRIVER_LINE17_LOW_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (PIO_DRIVER_LINE17_HIGH_DRIVE_Val << PIO_DRIVER_LINE17_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE18_Pos _U_(18) /**< (PIO_DRIVER) Drive of PIO Line 18 Position */ +#define PIO_DRIVER_LINE18_Msk (_U_(0x1) << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Drive of PIO Line 18 Mask */ +#define PIO_DRIVER_LINE18(value) (PIO_DRIVER_LINE18_Msk & ((value) << PIO_DRIVER_LINE18_Pos)) +#define PIO_DRIVER_LINE18_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (PIO_DRIVER_LINE18_LOW_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (PIO_DRIVER_LINE18_HIGH_DRIVE_Val << PIO_DRIVER_LINE18_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE19_Pos _U_(19) /**< (PIO_DRIVER) Drive of PIO Line 19 Position */ +#define PIO_DRIVER_LINE19_Msk (_U_(0x1) << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Drive of PIO Line 19 Mask */ +#define PIO_DRIVER_LINE19(value) (PIO_DRIVER_LINE19_Msk & ((value) << PIO_DRIVER_LINE19_Pos)) +#define PIO_DRIVER_LINE19_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (PIO_DRIVER_LINE19_LOW_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (PIO_DRIVER_LINE19_HIGH_DRIVE_Val << PIO_DRIVER_LINE19_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE20_Pos _U_(20) /**< (PIO_DRIVER) Drive of PIO Line 20 Position */ +#define PIO_DRIVER_LINE20_Msk (_U_(0x1) << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Drive of PIO Line 20 Mask */ +#define PIO_DRIVER_LINE20(value) (PIO_DRIVER_LINE20_Msk & ((value) << PIO_DRIVER_LINE20_Pos)) +#define PIO_DRIVER_LINE20_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (PIO_DRIVER_LINE20_LOW_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (PIO_DRIVER_LINE20_HIGH_DRIVE_Val << PIO_DRIVER_LINE20_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE21_Pos _U_(21) /**< (PIO_DRIVER) Drive of PIO Line 21 Position */ +#define PIO_DRIVER_LINE21_Msk (_U_(0x1) << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Drive of PIO Line 21 Mask */ +#define PIO_DRIVER_LINE21(value) (PIO_DRIVER_LINE21_Msk & ((value) << PIO_DRIVER_LINE21_Pos)) +#define PIO_DRIVER_LINE21_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (PIO_DRIVER_LINE21_LOW_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (PIO_DRIVER_LINE21_HIGH_DRIVE_Val << PIO_DRIVER_LINE21_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE22_Pos _U_(22) /**< (PIO_DRIVER) Drive of PIO Line 22 Position */ +#define PIO_DRIVER_LINE22_Msk (_U_(0x1) << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Drive of PIO Line 22 Mask */ +#define PIO_DRIVER_LINE22(value) (PIO_DRIVER_LINE22_Msk & ((value) << PIO_DRIVER_LINE22_Pos)) +#define PIO_DRIVER_LINE22_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (PIO_DRIVER_LINE22_LOW_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (PIO_DRIVER_LINE22_HIGH_DRIVE_Val << PIO_DRIVER_LINE22_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE23_Pos _U_(23) /**< (PIO_DRIVER) Drive of PIO Line 23 Position */ +#define PIO_DRIVER_LINE23_Msk (_U_(0x1) << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Drive of PIO Line 23 Mask */ +#define PIO_DRIVER_LINE23(value) (PIO_DRIVER_LINE23_Msk & ((value) << PIO_DRIVER_LINE23_Pos)) +#define PIO_DRIVER_LINE23_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (PIO_DRIVER_LINE23_LOW_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (PIO_DRIVER_LINE23_HIGH_DRIVE_Val << PIO_DRIVER_LINE23_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE24_Pos _U_(24) /**< (PIO_DRIVER) Drive of PIO Line 24 Position */ +#define PIO_DRIVER_LINE24_Msk (_U_(0x1) << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Drive of PIO Line 24 Mask */ +#define PIO_DRIVER_LINE24(value) (PIO_DRIVER_LINE24_Msk & ((value) << PIO_DRIVER_LINE24_Pos)) +#define PIO_DRIVER_LINE24_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (PIO_DRIVER_LINE24_LOW_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (PIO_DRIVER_LINE24_HIGH_DRIVE_Val << PIO_DRIVER_LINE24_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE25_Pos _U_(25) /**< (PIO_DRIVER) Drive of PIO Line 25 Position */ +#define PIO_DRIVER_LINE25_Msk (_U_(0x1) << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Drive of PIO Line 25 Mask */ +#define PIO_DRIVER_LINE25(value) (PIO_DRIVER_LINE25_Msk & ((value) << PIO_DRIVER_LINE25_Pos)) +#define PIO_DRIVER_LINE25_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (PIO_DRIVER_LINE25_LOW_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (PIO_DRIVER_LINE25_HIGH_DRIVE_Val << PIO_DRIVER_LINE25_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE26_Pos _U_(26) /**< (PIO_DRIVER) Drive of PIO Line 26 Position */ +#define PIO_DRIVER_LINE26_Msk (_U_(0x1) << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Drive of PIO Line 26 Mask */ +#define PIO_DRIVER_LINE26(value) (PIO_DRIVER_LINE26_Msk & ((value) << PIO_DRIVER_LINE26_Pos)) +#define PIO_DRIVER_LINE26_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (PIO_DRIVER_LINE26_LOW_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (PIO_DRIVER_LINE26_HIGH_DRIVE_Val << PIO_DRIVER_LINE26_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE27_Pos _U_(27) /**< (PIO_DRIVER) Drive of PIO Line 27 Position */ +#define PIO_DRIVER_LINE27_Msk (_U_(0x1) << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Drive of PIO Line 27 Mask */ +#define PIO_DRIVER_LINE27(value) (PIO_DRIVER_LINE27_Msk & ((value) << PIO_DRIVER_LINE27_Pos)) +#define PIO_DRIVER_LINE27_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (PIO_DRIVER_LINE27_LOW_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (PIO_DRIVER_LINE27_HIGH_DRIVE_Val << PIO_DRIVER_LINE27_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE28_Pos _U_(28) /**< (PIO_DRIVER) Drive of PIO Line 28 Position */ +#define PIO_DRIVER_LINE28_Msk (_U_(0x1) << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Drive of PIO Line 28 Mask */ +#define PIO_DRIVER_LINE28(value) (PIO_DRIVER_LINE28_Msk & ((value) << PIO_DRIVER_LINE28_Pos)) +#define PIO_DRIVER_LINE28_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (PIO_DRIVER_LINE28_LOW_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (PIO_DRIVER_LINE28_HIGH_DRIVE_Val << PIO_DRIVER_LINE28_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE29_Pos _U_(29) /**< (PIO_DRIVER) Drive of PIO Line 29 Position */ +#define PIO_DRIVER_LINE29_Msk (_U_(0x1) << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Drive of PIO Line 29 Mask */ +#define PIO_DRIVER_LINE29(value) (PIO_DRIVER_LINE29_Msk & ((value) << PIO_DRIVER_LINE29_Pos)) +#define PIO_DRIVER_LINE29_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (PIO_DRIVER_LINE29_LOW_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (PIO_DRIVER_LINE29_HIGH_DRIVE_Val << PIO_DRIVER_LINE29_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE30_Pos _U_(30) /**< (PIO_DRIVER) Drive of PIO Line 30 Position */ +#define PIO_DRIVER_LINE30_Msk (_U_(0x1) << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Drive of PIO Line 30 Mask */ +#define PIO_DRIVER_LINE30(value) (PIO_DRIVER_LINE30_Msk & ((value) << PIO_DRIVER_LINE30_Pos)) +#define PIO_DRIVER_LINE30_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (PIO_DRIVER_LINE30_LOW_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (PIO_DRIVER_LINE30_HIGH_DRIVE_Val << PIO_DRIVER_LINE30_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_LINE31_Pos _U_(31) /**< (PIO_DRIVER) Drive of PIO Line 31 Position */ +#define PIO_DRIVER_LINE31_Msk (_U_(0x1) << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Drive of PIO Line 31 Mask */ +#define PIO_DRIVER_LINE31(value) (PIO_DRIVER_LINE31_Msk & ((value) << PIO_DRIVER_LINE31_Pos)) +#define PIO_DRIVER_LINE31_LOW_DRIVE_Val _U_(0x0) /**< (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE_Val _U_(0x1) /**< (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (PIO_DRIVER_LINE31_LOW_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Lowest drive Position */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (PIO_DRIVER_LINE31_HIGH_DRIVE_Val << PIO_DRIVER_LINE31_Pos) /**< (PIO_DRIVER) Highest drive Position */ +#define PIO_DRIVER_Msk _U_(0xFFFFFFFF) /**< (PIO_DRIVER) Register Mask */ + +#define PIO_DRIVER_LINE_Pos _U_(0) /**< (PIO_DRIVER Position) Drive of PIO Line 3x */ +#define PIO_DRIVER_LINE_Msk (_U_(0xFFFFFFFF) << PIO_DRIVER_LINE_Pos) /**< (PIO_DRIVER Mask) LINE */ +#define PIO_DRIVER_LINE(value) (PIO_DRIVER_LINE_Msk & ((value) << PIO_DRIVER_LINE_Pos)) + +/* -------- PIO_PCMR : (PIO Offset: 0x150) (R/W 32) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN_Pos _U_(0) /**< (PIO_PCMR) Parallel Capture Mode Enable Position */ +#define PIO_PCMR_PCEN_Msk (_U_(0x1) << PIO_PCMR_PCEN_Pos) /**< (PIO_PCMR) Parallel Capture Mode Enable Mask */ +#define PIO_PCMR_PCEN(value) (PIO_PCMR_PCEN_Msk & ((value) << PIO_PCMR_PCEN_Pos)) +#define PIO_PCMR_DSIZE_Pos _U_(4) /**< (PIO_PCMR) Parallel Capture Mode Data Size Position */ +#define PIO_PCMR_DSIZE_Msk (_U_(0x3) << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) Parallel Capture Mode Data Size Mask */ +#define PIO_PCMR_DSIZE(value) (PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)) +#define PIO_PCMR_DSIZE_BYTE_Val _U_(0x0) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD_Val _U_(0x1) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD_Val _U_(0x2) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_DSIZE_BYTE (PIO_PCMR_DSIZE_BYTE_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) Position */ +#define PIO_PCMR_DSIZE_HALFWORD (PIO_PCMR_DSIZE_HALFWORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) Position */ +#define PIO_PCMR_DSIZE_WORD (PIO_PCMR_DSIZE_WORD_Val << PIO_PCMR_DSIZE_Pos) /**< (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) Position */ +#define PIO_PCMR_ALWYS_Pos _U_(9) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Position */ +#define PIO_PCMR_ALWYS_Msk (_U_(0x1) << PIO_PCMR_ALWYS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Always Sampling Mask */ +#define PIO_PCMR_ALWYS(value) (PIO_PCMR_ALWYS_Msk & ((value) << PIO_PCMR_ALWYS_Pos)) +#define PIO_PCMR_HALFS_Pos _U_(10) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Position */ +#define PIO_PCMR_HALFS_Msk (_U_(0x1) << PIO_PCMR_HALFS_Pos) /**< (PIO_PCMR) Parallel Capture Mode Half Sampling Mask */ +#define PIO_PCMR_HALFS(value) (PIO_PCMR_HALFS_Msk & ((value) << PIO_PCMR_HALFS_Pos)) +#define PIO_PCMR_FRSTS_Pos _U_(11) /**< (PIO_PCMR) Parallel Capture Mode First Sample Position */ +#define PIO_PCMR_FRSTS_Msk (_U_(0x1) << PIO_PCMR_FRSTS_Pos) /**< (PIO_PCMR) Parallel Capture Mode First Sample Mask */ +#define PIO_PCMR_FRSTS(value) (PIO_PCMR_FRSTS_Msk & ((value) << PIO_PCMR_FRSTS_Pos)) +#define PIO_PCMR_Msk _U_(0x00000E31) /**< (PIO_PCMR) Register Mask */ + + +/* -------- PIO_PCIER : (PIO Offset: 0x154) ( /W 32) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY_Pos _U_(0) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Position */ +#define PIO_PCIER_DRDY_Msk (_U_(0x1) << PIO_PCIER_DRDY_Pos) /**< (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable Mask */ +#define PIO_PCIER_DRDY(value) (PIO_PCIER_DRDY_Msk & ((value) << PIO_PCIER_DRDY_Pos)) +#define PIO_PCIER_OVRE_Pos _U_(1) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Position */ +#define PIO_PCIER_OVRE_Msk (_U_(0x1) << PIO_PCIER_OVRE_Pos) /**< (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable Mask */ +#define PIO_PCIER_OVRE(value) (PIO_PCIER_OVRE_Msk & ((value) << PIO_PCIER_OVRE_Pos)) +#define PIO_PCIER_ENDRX_Pos _U_(2) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Position */ +#define PIO_PCIER_ENDRX_Msk (_U_(0x1) << PIO_PCIER_ENDRX_Pos) /**< (PIO_PCIER) End of Reception Transfer Interrupt Enable Mask */ +#define PIO_PCIER_ENDRX(value) (PIO_PCIER_ENDRX_Msk & ((value) << PIO_PCIER_ENDRX_Pos)) +#define PIO_PCIER_RXBUFF_Pos _U_(3) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Position */ +#define PIO_PCIER_RXBUFF_Msk (_U_(0x1) << PIO_PCIER_RXBUFF_Pos) /**< (PIO_PCIER) Reception Buffer Full Interrupt Enable Mask */ +#define PIO_PCIER_RXBUFF(value) (PIO_PCIER_RXBUFF_Msk & ((value) << PIO_PCIER_RXBUFF_Pos)) +#define PIO_PCIER_Msk _U_(0x0000000F) /**< (PIO_PCIER) Register Mask */ + + +/* -------- PIO_PCIDR : (PIO Offset: 0x158) ( /W 32) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY_Pos _U_(0) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Position */ +#define PIO_PCIDR_DRDY_Msk (_U_(0x1) << PIO_PCIDR_DRDY_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable Mask */ +#define PIO_PCIDR_DRDY(value) (PIO_PCIDR_DRDY_Msk & ((value) << PIO_PCIDR_DRDY_Pos)) +#define PIO_PCIDR_OVRE_Pos _U_(1) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Position */ +#define PIO_PCIDR_OVRE_Msk (_U_(0x1) << PIO_PCIDR_OVRE_Pos) /**< (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable Mask */ +#define PIO_PCIDR_OVRE(value) (PIO_PCIDR_OVRE_Msk & ((value) << PIO_PCIDR_OVRE_Pos)) +#define PIO_PCIDR_ENDRX_Pos _U_(2) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Position */ +#define PIO_PCIDR_ENDRX_Msk (_U_(0x1) << PIO_PCIDR_ENDRX_Pos) /**< (PIO_PCIDR) End of Reception Transfer Interrupt Disable Mask */ +#define PIO_PCIDR_ENDRX(value) (PIO_PCIDR_ENDRX_Msk & ((value) << PIO_PCIDR_ENDRX_Pos)) +#define PIO_PCIDR_RXBUFF_Pos _U_(3) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Position */ +#define PIO_PCIDR_RXBUFF_Msk (_U_(0x1) << PIO_PCIDR_RXBUFF_Pos) /**< (PIO_PCIDR) Reception Buffer Full Interrupt Disable Mask */ +#define PIO_PCIDR_RXBUFF(value) (PIO_PCIDR_RXBUFF_Msk & ((value) << PIO_PCIDR_RXBUFF_Pos)) +#define PIO_PCIDR_Msk _U_(0x0000000F) /**< (PIO_PCIDR) Register Mask */ + + +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) ( R/ 32) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY_Pos _U_(0) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Position */ +#define PIO_PCIMR_DRDY_Msk (_U_(0x1) << PIO_PCIMR_DRDY_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask Mask */ +#define PIO_PCIMR_DRDY(value) (PIO_PCIMR_DRDY_Msk & ((value) << PIO_PCIMR_DRDY_Pos)) +#define PIO_PCIMR_OVRE_Pos _U_(1) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Position */ +#define PIO_PCIMR_OVRE_Msk (_U_(0x1) << PIO_PCIMR_OVRE_Pos) /**< (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask Mask */ +#define PIO_PCIMR_OVRE(value) (PIO_PCIMR_OVRE_Msk & ((value) << PIO_PCIMR_OVRE_Pos)) +#define PIO_PCIMR_ENDRX_Pos _U_(2) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Position */ +#define PIO_PCIMR_ENDRX_Msk (_U_(0x1) << PIO_PCIMR_ENDRX_Pos) /**< (PIO_PCIMR) End of Reception Transfer Interrupt Mask Mask */ +#define PIO_PCIMR_ENDRX(value) (PIO_PCIMR_ENDRX_Msk & ((value) << PIO_PCIMR_ENDRX_Pos)) +#define PIO_PCIMR_RXBUFF_Pos _U_(3) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Position */ +#define PIO_PCIMR_RXBUFF_Msk (_U_(0x1) << PIO_PCIMR_RXBUFF_Pos) /**< (PIO_PCIMR) Reception Buffer Full Interrupt Mask Mask */ +#define PIO_PCIMR_RXBUFF(value) (PIO_PCIMR_RXBUFF_Msk & ((value) << PIO_PCIMR_RXBUFF_Pos)) +#define PIO_PCIMR_Msk _U_(0x0000000F) /**< (PIO_PCIMR) Register Mask */ + + +/* -------- PIO_PCISR : (PIO Offset: 0x160) ( R/ 32) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY_Pos _U_(0) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Position */ +#define PIO_PCISR_DRDY_Msk (_U_(0x1) << PIO_PCISR_DRDY_Pos) /**< (PIO_PCISR) Parallel Capture Mode Data Ready Mask */ +#define PIO_PCISR_DRDY(value) (PIO_PCISR_DRDY_Msk & ((value) << PIO_PCISR_DRDY_Pos)) +#define PIO_PCISR_OVRE_Pos _U_(1) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Position */ +#define PIO_PCISR_OVRE_Msk (_U_(0x1) << PIO_PCISR_OVRE_Pos) /**< (PIO_PCISR) Parallel Capture Mode Overrun Error Mask */ +#define PIO_PCISR_OVRE(value) (PIO_PCISR_OVRE_Msk & ((value) << PIO_PCISR_OVRE_Pos)) +#define PIO_PCISR_Msk _U_(0x00000003) /**< (PIO_PCISR) Register Mask */ + + +/* -------- PIO_PCRHR : (PIO Offset: 0x164) ( R/ 32) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos _U_(0) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Position */ +#define PIO_PCRHR_RDATA_Msk (_U_(0xFFFFFFFF) << PIO_PCRHR_RDATA_Pos) /**< (PIO_PCRHR) Parallel Capture Mode Reception Data Mask */ +#define PIO_PCRHR_RDATA(value) (PIO_PCRHR_RDATA_Msk & ((value) << PIO_PCRHR_RDATA_Pos)) +#define PIO_PCRHR_Msk _U_(0xFFFFFFFF) /**< (PIO_PCRHR) Register Mask */ + + +/** \brief PIO register offsets definitions */ +#define PIO_PER_REG_OFST (0x00) /**< (PIO_PER) PIO Enable Register Offset */ +#define PIO_PDR_REG_OFST (0x04) /**< (PIO_PDR) PIO Disable Register Offset */ +#define PIO_PSR_REG_OFST (0x08) /**< (PIO_PSR) PIO Status Register Offset */ +#define PIO_OER_REG_OFST (0x10) /**< (PIO_OER) Output Enable Register Offset */ +#define PIO_ODR_REG_OFST (0x14) /**< (PIO_ODR) Output Disable Register Offset */ +#define PIO_OSR_REG_OFST (0x18) /**< (PIO_OSR) Output Status Register Offset */ +#define PIO_IFER_REG_OFST (0x20) /**< (PIO_IFER) Glitch Input Filter Enable Register Offset */ +#define PIO_IFDR_REG_OFST (0x24) /**< (PIO_IFDR) Glitch Input Filter Disable Register Offset */ +#define PIO_IFSR_REG_OFST (0x28) /**< (PIO_IFSR) Glitch Input Filter Status Register Offset */ +#define PIO_SODR_REG_OFST (0x30) /**< (PIO_SODR) Set Output Data Register Offset */ +#define PIO_CODR_REG_OFST (0x34) /**< (PIO_CODR) Clear Output Data Register Offset */ +#define PIO_ODSR_REG_OFST (0x38) /**< (PIO_ODSR) Output Data Status Register Offset */ +#define PIO_PDSR_REG_OFST (0x3C) /**< (PIO_PDSR) Pin Data Status Register Offset */ +#define PIO_IER_REG_OFST (0x40) /**< (PIO_IER) Interrupt Enable Register Offset */ +#define PIO_IDR_REG_OFST (0x44) /**< (PIO_IDR) Interrupt Disable Register Offset */ +#define PIO_IMR_REG_OFST (0x48) /**< (PIO_IMR) Interrupt Mask Register Offset */ +#define PIO_ISR_REG_OFST (0x4C) /**< (PIO_ISR) Interrupt Status Register Offset */ +#define PIO_MDER_REG_OFST (0x50) /**< (PIO_MDER) Multi-driver Enable Register Offset */ +#define PIO_MDDR_REG_OFST (0x54) /**< (PIO_MDDR) Multi-driver Disable Register Offset */ +#define PIO_MDSR_REG_OFST (0x58) /**< (PIO_MDSR) Multi-driver Status Register Offset */ +#define PIO_PUDR_REG_OFST (0x60) /**< (PIO_PUDR) Pull-up Disable Register Offset */ +#define PIO_PUER_REG_OFST (0x64) /**< (PIO_PUER) Pull-up Enable Register Offset */ +#define PIO_PUSR_REG_OFST (0x68) /**< (PIO_PUSR) Pad Pull-up Status Register Offset */ +#define PIO_ABCDSR_REG_OFST (0x70) /**< (PIO_ABCDSR) Peripheral ABCD Select Register 0 Offset */ +#define PIO_IFSCDR_REG_OFST (0x80) /**< (PIO_IFSCDR) Input Filter Slow Clock Disable Register Offset */ +#define PIO_IFSCER_REG_OFST (0x84) /**< (PIO_IFSCER) Input Filter Slow Clock Enable Register Offset */ +#define PIO_IFSCSR_REG_OFST (0x88) /**< (PIO_IFSCSR) Input Filter Slow Clock Status Register Offset */ +#define PIO_SCDR_REG_OFST (0x8C) /**< (PIO_SCDR) Slow Clock Divider Debouncing Register Offset */ +#define PIO_PPDDR_REG_OFST (0x90) /**< (PIO_PPDDR) Pad Pull-down Disable Register Offset */ +#define PIO_PPDER_REG_OFST (0x94) /**< (PIO_PPDER) Pad Pull-down Enable Register Offset */ +#define PIO_PPDSR_REG_OFST (0x98) /**< (PIO_PPDSR) Pad Pull-down Status Register Offset */ +#define PIO_OWER_REG_OFST (0xA0) /**< (PIO_OWER) Output Write Enable Offset */ +#define PIO_OWDR_REG_OFST (0xA4) /**< (PIO_OWDR) Output Write Disable Offset */ +#define PIO_OWSR_REG_OFST (0xA8) /**< (PIO_OWSR) Output Write Status Register Offset */ +#define PIO_AIMER_REG_OFST (0xB0) /**< (PIO_AIMER) Additional Interrupt Modes Enable Register Offset */ +#define PIO_AIMDR_REG_OFST (0xB4) /**< (PIO_AIMDR) Additional Interrupt Modes Disable Register Offset */ +#define PIO_AIMMR_REG_OFST (0xB8) /**< (PIO_AIMMR) Additional Interrupt Modes Mask Register Offset */ +#define PIO_ESR_REG_OFST (0xC0) /**< (PIO_ESR) Edge Select Register Offset */ +#define PIO_LSR_REG_OFST (0xC4) /**< (PIO_LSR) Level Select Register Offset */ +#define PIO_ELSR_REG_OFST (0xC8) /**< (PIO_ELSR) Edge/Level Status Register Offset */ +#define PIO_FELLSR_REG_OFST (0xD0) /**< (PIO_FELLSR) Falling Edge/Low-Level Select Register Offset */ +#define PIO_REHLSR_REG_OFST (0xD4) /**< (PIO_REHLSR) Rising Edge/High-Level Select Register Offset */ +#define PIO_FRLHSR_REG_OFST (0xD8) /**< (PIO_FRLHSR) Fall/Rise - Low/High Status Register Offset */ +#define PIO_LOCKSR_REG_OFST (0xE0) /**< (PIO_LOCKSR) Lock Status Offset */ +#define PIO_WPMR_REG_OFST (0xE4) /**< (PIO_WPMR) Write Protection Mode Register Offset */ +#define PIO_WPSR_REG_OFST (0xE8) /**< (PIO_WPSR) Write Protection Status Register Offset */ +#define PIO_SCHMITT_REG_OFST (0x100) /**< (PIO_SCHMITT) Schmitt Trigger Register Offset */ +#define PIO_DRIVER_REG_OFST (0x118) /**< (PIO_DRIVER) I/O Drive Register Offset */ +#define PIO_PCMR_REG_OFST (0x150) /**< (PIO_PCMR) Parallel Capture Mode Register Offset */ +#define PIO_PCIER_REG_OFST (0x154) /**< (PIO_PCIER) Parallel Capture Interrupt Enable Register Offset */ +#define PIO_PCIDR_REG_OFST (0x158) /**< (PIO_PCIDR) Parallel Capture Interrupt Disable Register Offset */ +#define PIO_PCIMR_REG_OFST (0x15C) /**< (PIO_PCIMR) Parallel Capture Interrupt Mask Register Offset */ +#define PIO_PCISR_REG_OFST (0x160) /**< (PIO_PCISR) Parallel Capture Interrupt Status Register Offset */ +#define PIO_PCRHR_REG_OFST (0x164) /**< (PIO_PCRHR) Parallel Capture Reception Holding Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PIO register API structure */ +typedef struct +{ + __O uint32_t PIO_PER; /**< Offset: 0x00 ( /W 32) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< Offset: 0x04 ( /W 32) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< Offset: 0x08 (R/ 32) PIO Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t PIO_OER; /**< Offset: 0x10 ( /W 32) Output Enable Register */ + __O uint32_t PIO_ODR; /**< Offset: 0x14 ( /W 32) Output Disable Register */ + __I uint32_t PIO_OSR; /**< Offset: 0x18 (R/ 32) Output Status Register */ + __I uint8_t Reserved2[0x04]; + __O uint32_t PIO_IFER; /**< Offset: 0x20 ( /W 32) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< Offset: 0x24 ( /W 32) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< Offset: 0x28 (R/ 32) Glitch Input Filter Status Register */ + __I uint8_t Reserved3[0x04]; + __O uint32_t PIO_SODR; /**< Offset: 0x30 ( /W 32) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< Offset: 0x34 ( /W 32) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< Offset: 0x38 (R/W 32) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< Offset: 0x3C (R/ 32) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< Offset: 0x40 ( /W 32) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< Offset: 0x44 ( /W 32) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< Offset: 0x48 (R/ 32) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< Offset: 0x4C (R/ 32) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< Offset: 0x50 ( /W 32) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< Offset: 0x54 ( /W 32) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< Offset: 0x58 (R/ 32) Multi-driver Status Register */ + __I uint8_t Reserved4[0x04]; + __O uint32_t PIO_PUDR; /**< Offset: 0x60 ( /W 32) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< Offset: 0x64 ( /W 32) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< Offset: 0x68 (R/ 32) Pad Pull-up Status Register */ + __I uint8_t Reserved5[0x04]; + __IO uint32_t PIO_ABCDSR[2]; /**< Offset: 0x70 (R/W 32) Peripheral ABCD Select Register 0 */ + __I uint8_t Reserved6[0x08]; + __O uint32_t PIO_IFSCDR; /**< Offset: 0x80 ( /W 32) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< Offset: 0x84 ( /W 32) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< Offset: 0x88 (R/ 32) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< Offset: 0x8C (R/W 32) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< Offset: 0x90 ( /W 32) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< Offset: 0x94 ( /W 32) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< Offset: 0x98 (R/ 32) Pad Pull-down Status Register */ + __I uint8_t Reserved7[0x04]; + __O uint32_t PIO_OWER; /**< Offset: 0xA0 ( /W 32) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< Offset: 0xA4 ( /W 32) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< Offset: 0xA8 (R/ 32) Output Write Status Register */ + __I uint8_t Reserved8[0x04]; + __O uint32_t PIO_AIMER; /**< Offset: 0xB0 ( /W 32) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< Offset: 0xB4 ( /W 32) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< Offset: 0xB8 (R/ 32) Additional Interrupt Modes Mask Register */ + __I uint8_t Reserved9[0x04]; + __O uint32_t PIO_ESR; /**< Offset: 0xC0 ( /W 32) Edge Select Register */ + __O uint32_t PIO_LSR; /**< Offset: 0xC4 ( /W 32) Level Select Register */ + __I uint32_t PIO_ELSR; /**< Offset: 0xC8 (R/ 32) Edge/Level Status Register */ + __I uint8_t Reserved10[0x04]; + __O uint32_t PIO_FELLSR; /**< Offset: 0xD0 ( /W 32) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< Offset: 0xD4 ( /W 32) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< Offset: 0xD8 (R/ 32) Fall/Rise - Low/High Status Register */ + __I uint8_t Reserved11[0x04]; + __I uint32_t PIO_LOCKSR; /**< Offset: 0xE0 (R/ 32) Lock Status */ + __IO uint32_t PIO_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved12[0x14]; + __IO uint32_t PIO_SCHMITT; /**< Offset: 0x100 (R/W 32) Schmitt Trigger Register */ + __I uint8_t Reserved13[0x14]; + __IO uint32_t PIO_DRIVER; /**< Offset: 0x118 (R/W 32) I/O Drive Register */ + __I uint8_t Reserved14[0x34]; + __IO uint32_t PIO_PCMR; /**< Offset: 0x150 (R/W 32) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< Offset: 0x154 ( /W 32) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< Offset: 0x158 ( /W 32) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< Offset: 0x15C (R/ 32) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< Offset: 0x160 (R/ 32) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< Offset: 0x164 (R/ 32) Parallel Capture Reception Holding Register */ +} pio_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PIO_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/pmc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/pmc.h new file mode 100644 index 00000000..30572ea4 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/pmc.h @@ -0,0 +1,1983 @@ +/** + * \brief Component description for PMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_PMC_COMPONENT_H_ +#define _SAME70_PMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PMC */ +/* ************************************************************************** */ + +/* -------- PMC_SCER : (PMC Offset: 0x00) ( /W 32) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK_Pos _U_(5) /**< (PMC_SCER) Enable USB FS Clock Position */ +#define PMC_SCER_USBCLK_Msk (_U_(0x1) << PMC_SCER_USBCLK_Pos) /**< (PMC_SCER) Enable USB FS Clock Mask */ +#define PMC_SCER_USBCLK(value) (PMC_SCER_USBCLK_Msk & ((value) << PMC_SCER_USBCLK_Pos)) +#define PMC_SCER_PCK0_Pos _U_(8) /**< (PMC_SCER) Programmable Clock 0 Output Enable Position */ +#define PMC_SCER_PCK0_Msk (_U_(0x1) << PMC_SCER_PCK0_Pos) /**< (PMC_SCER) Programmable Clock 0 Output Enable Mask */ +#define PMC_SCER_PCK0(value) (PMC_SCER_PCK0_Msk & ((value) << PMC_SCER_PCK0_Pos)) +#define PMC_SCER_PCK1_Pos _U_(9) /**< (PMC_SCER) Programmable Clock 1 Output Enable Position */ +#define PMC_SCER_PCK1_Msk (_U_(0x1) << PMC_SCER_PCK1_Pos) /**< (PMC_SCER) Programmable Clock 1 Output Enable Mask */ +#define PMC_SCER_PCK1(value) (PMC_SCER_PCK1_Msk & ((value) << PMC_SCER_PCK1_Pos)) +#define PMC_SCER_PCK2_Pos _U_(10) /**< (PMC_SCER) Programmable Clock 2 Output Enable Position */ +#define PMC_SCER_PCK2_Msk (_U_(0x1) << PMC_SCER_PCK2_Pos) /**< (PMC_SCER) Programmable Clock 2 Output Enable Mask */ +#define PMC_SCER_PCK2(value) (PMC_SCER_PCK2_Msk & ((value) << PMC_SCER_PCK2_Pos)) +#define PMC_SCER_PCK3_Pos _U_(11) /**< (PMC_SCER) Programmable Clock 3 Output Enable Position */ +#define PMC_SCER_PCK3_Msk (_U_(0x1) << PMC_SCER_PCK3_Pos) /**< (PMC_SCER) Programmable Clock 3 Output Enable Mask */ +#define PMC_SCER_PCK3(value) (PMC_SCER_PCK3_Msk & ((value) << PMC_SCER_PCK3_Pos)) +#define PMC_SCER_PCK4_Pos _U_(12) /**< (PMC_SCER) Programmable Clock 4 Output Enable Position */ +#define PMC_SCER_PCK4_Msk (_U_(0x1) << PMC_SCER_PCK4_Pos) /**< (PMC_SCER) Programmable Clock 4 Output Enable Mask */ +#define PMC_SCER_PCK4(value) (PMC_SCER_PCK4_Msk & ((value) << PMC_SCER_PCK4_Pos)) +#define PMC_SCER_PCK5_Pos _U_(13) /**< (PMC_SCER) Programmable Clock 5 Output Enable Position */ +#define PMC_SCER_PCK5_Msk (_U_(0x1) << PMC_SCER_PCK5_Pos) /**< (PMC_SCER) Programmable Clock 5 Output Enable Mask */ +#define PMC_SCER_PCK5(value) (PMC_SCER_PCK5_Msk & ((value) << PMC_SCER_PCK5_Pos)) +#define PMC_SCER_PCK6_Pos _U_(14) /**< (PMC_SCER) Programmable Clock 6 Output Enable Position */ +#define PMC_SCER_PCK6_Msk (_U_(0x1) << PMC_SCER_PCK6_Pos) /**< (PMC_SCER) Programmable Clock 6 Output Enable Mask */ +#define PMC_SCER_PCK6(value) (PMC_SCER_PCK6_Msk & ((value) << PMC_SCER_PCK6_Pos)) +#define PMC_SCER_PCK7_Pos _U_(15) /**< (PMC_SCER) Programmable Clock 7 Output Enable Position */ +#define PMC_SCER_PCK7_Msk (_U_(0x1) << PMC_SCER_PCK7_Pos) /**< (PMC_SCER) Programmable Clock 7 Output Enable Mask */ +#define PMC_SCER_PCK7(value) (PMC_SCER_PCK7_Msk & ((value) << PMC_SCER_PCK7_Pos)) +#define PMC_SCER_Msk _U_(0x0000FF20) /**< (PMC_SCER) Register Mask */ + +#define PMC_SCER_PCK_Pos _U_(8) /**< (PMC_SCER Position) Programmable Clock 7 Output Enable */ +#define PMC_SCER_PCK_Msk (_U_(0xFF) << PMC_SCER_PCK_Pos) /**< (PMC_SCER Mask) PCK */ +#define PMC_SCER_PCK(value) (PMC_SCER_PCK_Msk & ((value) << PMC_SCER_PCK_Pos)) + +/* -------- PMC_SCDR : (PMC Offset: 0x04) ( /W 32) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK_Pos _U_(5) /**< (PMC_SCDR) Disable USB FS Clock Position */ +#define PMC_SCDR_USBCLK_Msk (_U_(0x1) << PMC_SCDR_USBCLK_Pos) /**< (PMC_SCDR) Disable USB FS Clock Mask */ +#define PMC_SCDR_USBCLK(value) (PMC_SCDR_USBCLK_Msk & ((value) << PMC_SCDR_USBCLK_Pos)) +#define PMC_SCDR_PCK0_Pos _U_(8) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Position */ +#define PMC_SCDR_PCK0_Msk (_U_(0x1) << PMC_SCDR_PCK0_Pos) /**< (PMC_SCDR) Programmable Clock 0 Output Disable Mask */ +#define PMC_SCDR_PCK0(value) (PMC_SCDR_PCK0_Msk & ((value) << PMC_SCDR_PCK0_Pos)) +#define PMC_SCDR_PCK1_Pos _U_(9) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Position */ +#define PMC_SCDR_PCK1_Msk (_U_(0x1) << PMC_SCDR_PCK1_Pos) /**< (PMC_SCDR) Programmable Clock 1 Output Disable Mask */ +#define PMC_SCDR_PCK1(value) (PMC_SCDR_PCK1_Msk & ((value) << PMC_SCDR_PCK1_Pos)) +#define PMC_SCDR_PCK2_Pos _U_(10) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Position */ +#define PMC_SCDR_PCK2_Msk (_U_(0x1) << PMC_SCDR_PCK2_Pos) /**< (PMC_SCDR) Programmable Clock 2 Output Disable Mask */ +#define PMC_SCDR_PCK2(value) (PMC_SCDR_PCK2_Msk & ((value) << PMC_SCDR_PCK2_Pos)) +#define PMC_SCDR_PCK3_Pos _U_(11) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Position */ +#define PMC_SCDR_PCK3_Msk (_U_(0x1) << PMC_SCDR_PCK3_Pos) /**< (PMC_SCDR) Programmable Clock 3 Output Disable Mask */ +#define PMC_SCDR_PCK3(value) (PMC_SCDR_PCK3_Msk & ((value) << PMC_SCDR_PCK3_Pos)) +#define PMC_SCDR_PCK4_Pos _U_(12) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Position */ +#define PMC_SCDR_PCK4_Msk (_U_(0x1) << PMC_SCDR_PCK4_Pos) /**< (PMC_SCDR) Programmable Clock 4 Output Disable Mask */ +#define PMC_SCDR_PCK4(value) (PMC_SCDR_PCK4_Msk & ((value) << PMC_SCDR_PCK4_Pos)) +#define PMC_SCDR_PCK5_Pos _U_(13) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Position */ +#define PMC_SCDR_PCK5_Msk (_U_(0x1) << PMC_SCDR_PCK5_Pos) /**< (PMC_SCDR) Programmable Clock 5 Output Disable Mask */ +#define PMC_SCDR_PCK5(value) (PMC_SCDR_PCK5_Msk & ((value) << PMC_SCDR_PCK5_Pos)) +#define PMC_SCDR_PCK6_Pos _U_(14) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Position */ +#define PMC_SCDR_PCK6_Msk (_U_(0x1) << PMC_SCDR_PCK6_Pos) /**< (PMC_SCDR) Programmable Clock 6 Output Disable Mask */ +#define PMC_SCDR_PCK6(value) (PMC_SCDR_PCK6_Msk & ((value) << PMC_SCDR_PCK6_Pos)) +#define PMC_SCDR_PCK7_Pos _U_(15) /**< (PMC_SCDR) Programmable Clock 7 Output Disable Position */ +#define PMC_SCDR_PCK7_Msk (_U_(0x1) << PMC_SCDR_PCK7_Pos) /**< (PMC_SCDR) Programmable Clock 7 Output Disable Mask */ +#define PMC_SCDR_PCK7(value) (PMC_SCDR_PCK7_Msk & ((value) << PMC_SCDR_PCK7_Pos)) +#define PMC_SCDR_Msk _U_(0x0000FF20) /**< (PMC_SCDR) Register Mask */ + +#define PMC_SCDR_PCK_Pos _U_(8) /**< (PMC_SCDR Position) Programmable Clock 7 Output Disable */ +#define PMC_SCDR_PCK_Msk (_U_(0xFF) << PMC_SCDR_PCK_Pos) /**< (PMC_SCDR Mask) PCK */ +#define PMC_SCDR_PCK(value) (PMC_SCDR_PCK_Msk & ((value) << PMC_SCDR_PCK_Pos)) + +/* -------- PMC_SCSR : (PMC Offset: 0x08) ( R/ 32) System Clock Status Register -------- */ +#define PMC_SCSR_HCLKS_Pos _U_(0) /**< (PMC_SCSR) HCLK Status Position */ +#define PMC_SCSR_HCLKS_Msk (_U_(0x1) << PMC_SCSR_HCLKS_Pos) /**< (PMC_SCSR) HCLK Status Mask */ +#define PMC_SCSR_HCLKS(value) (PMC_SCSR_HCLKS_Msk & ((value) << PMC_SCSR_HCLKS_Pos)) +#define PMC_SCSR_USBCLK_Pos _U_(5) /**< (PMC_SCSR) USB FS Clock Status Position */ +#define PMC_SCSR_USBCLK_Msk (_U_(0x1) << PMC_SCSR_USBCLK_Pos) /**< (PMC_SCSR) USB FS Clock Status Mask */ +#define PMC_SCSR_USBCLK(value) (PMC_SCSR_USBCLK_Msk & ((value) << PMC_SCSR_USBCLK_Pos)) +#define PMC_SCSR_PCK0_Pos _U_(8) /**< (PMC_SCSR) Programmable Clock 0 Output Status Position */ +#define PMC_SCSR_PCK0_Msk (_U_(0x1) << PMC_SCSR_PCK0_Pos) /**< (PMC_SCSR) Programmable Clock 0 Output Status Mask */ +#define PMC_SCSR_PCK0(value) (PMC_SCSR_PCK0_Msk & ((value) << PMC_SCSR_PCK0_Pos)) +#define PMC_SCSR_PCK1_Pos _U_(9) /**< (PMC_SCSR) Programmable Clock 1 Output Status Position */ +#define PMC_SCSR_PCK1_Msk (_U_(0x1) << PMC_SCSR_PCK1_Pos) /**< (PMC_SCSR) Programmable Clock 1 Output Status Mask */ +#define PMC_SCSR_PCK1(value) (PMC_SCSR_PCK1_Msk & ((value) << PMC_SCSR_PCK1_Pos)) +#define PMC_SCSR_PCK2_Pos _U_(10) /**< (PMC_SCSR) Programmable Clock 2 Output Status Position */ +#define PMC_SCSR_PCK2_Msk (_U_(0x1) << PMC_SCSR_PCK2_Pos) /**< (PMC_SCSR) Programmable Clock 2 Output Status Mask */ +#define PMC_SCSR_PCK2(value) (PMC_SCSR_PCK2_Msk & ((value) << PMC_SCSR_PCK2_Pos)) +#define PMC_SCSR_PCK3_Pos _U_(11) /**< (PMC_SCSR) Programmable Clock 3 Output Status Position */ +#define PMC_SCSR_PCK3_Msk (_U_(0x1) << PMC_SCSR_PCK3_Pos) /**< (PMC_SCSR) Programmable Clock 3 Output Status Mask */ +#define PMC_SCSR_PCK3(value) (PMC_SCSR_PCK3_Msk & ((value) << PMC_SCSR_PCK3_Pos)) +#define PMC_SCSR_PCK4_Pos _U_(12) /**< (PMC_SCSR) Programmable Clock 4 Output Status Position */ +#define PMC_SCSR_PCK4_Msk (_U_(0x1) << PMC_SCSR_PCK4_Pos) /**< (PMC_SCSR) Programmable Clock 4 Output Status Mask */ +#define PMC_SCSR_PCK4(value) (PMC_SCSR_PCK4_Msk & ((value) << PMC_SCSR_PCK4_Pos)) +#define PMC_SCSR_PCK5_Pos _U_(13) /**< (PMC_SCSR) Programmable Clock 5 Output Status Position */ +#define PMC_SCSR_PCK5_Msk (_U_(0x1) << PMC_SCSR_PCK5_Pos) /**< (PMC_SCSR) Programmable Clock 5 Output Status Mask */ +#define PMC_SCSR_PCK5(value) (PMC_SCSR_PCK5_Msk & ((value) << PMC_SCSR_PCK5_Pos)) +#define PMC_SCSR_PCK6_Pos _U_(14) /**< (PMC_SCSR) Programmable Clock 6 Output Status Position */ +#define PMC_SCSR_PCK6_Msk (_U_(0x1) << PMC_SCSR_PCK6_Pos) /**< (PMC_SCSR) Programmable Clock 6 Output Status Mask */ +#define PMC_SCSR_PCK6(value) (PMC_SCSR_PCK6_Msk & ((value) << PMC_SCSR_PCK6_Pos)) +#define PMC_SCSR_PCK7_Pos _U_(15) /**< (PMC_SCSR) Programmable Clock 7 Output Status Position */ +#define PMC_SCSR_PCK7_Msk (_U_(0x1) << PMC_SCSR_PCK7_Pos) /**< (PMC_SCSR) Programmable Clock 7 Output Status Mask */ +#define PMC_SCSR_PCK7(value) (PMC_SCSR_PCK7_Msk & ((value) << PMC_SCSR_PCK7_Pos)) +#define PMC_SCSR_Msk _U_(0x0000FF21) /**< (PMC_SCSR) Register Mask */ + +#define PMC_SCSR_PCK_Pos _U_(8) /**< (PMC_SCSR Position) Programmable Clock 7 Output Status */ +#define PMC_SCSR_PCK_Msk (_U_(0xFF) << PMC_SCSR_PCK_Pos) /**< (PMC_SCSR Mask) PCK */ +#define PMC_SCSR_PCK(value) (PMC_SCSR_PCK_Msk & ((value) << PMC_SCSR_PCK_Pos)) + +/* -------- PMC_PCER0 : (PMC Offset: 0x10) ( /W 32) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7_Pos _U_(7) /**< (PMC_PCER0) Peripheral Clock 7 Enable Position */ +#define PMC_PCER0_PID7_Msk (_U_(0x1) << PMC_PCER0_PID7_Pos) /**< (PMC_PCER0) Peripheral Clock 7 Enable Mask */ +#define PMC_PCER0_PID7(value) (PMC_PCER0_PID7_Msk & ((value) << PMC_PCER0_PID7_Pos)) +#define PMC_PCER0_PID8_Pos _U_(8) /**< (PMC_PCER0) Peripheral Clock 8 Enable Position */ +#define PMC_PCER0_PID8_Msk (_U_(0x1) << PMC_PCER0_PID8_Pos) /**< (PMC_PCER0) Peripheral Clock 8 Enable Mask */ +#define PMC_PCER0_PID8(value) (PMC_PCER0_PID8_Msk & ((value) << PMC_PCER0_PID8_Pos)) +#define PMC_PCER0_PID9_Pos _U_(9) /**< (PMC_PCER0) Peripheral Clock 9 Enable Position */ +#define PMC_PCER0_PID9_Msk (_U_(0x1) << PMC_PCER0_PID9_Pos) /**< (PMC_PCER0) Peripheral Clock 9 Enable Mask */ +#define PMC_PCER0_PID9(value) (PMC_PCER0_PID9_Msk & ((value) << PMC_PCER0_PID9_Pos)) +#define PMC_PCER0_PID10_Pos _U_(10) /**< (PMC_PCER0) Peripheral Clock 10 Enable Position */ +#define PMC_PCER0_PID10_Msk (_U_(0x1) << PMC_PCER0_PID10_Pos) /**< (PMC_PCER0) Peripheral Clock 10 Enable Mask */ +#define PMC_PCER0_PID10(value) (PMC_PCER0_PID10_Msk & ((value) << PMC_PCER0_PID10_Pos)) +#define PMC_PCER0_PID11_Pos _U_(11) /**< (PMC_PCER0) Peripheral Clock 11 Enable Position */ +#define PMC_PCER0_PID11_Msk (_U_(0x1) << PMC_PCER0_PID11_Pos) /**< (PMC_PCER0) Peripheral Clock 11 Enable Mask */ +#define PMC_PCER0_PID11(value) (PMC_PCER0_PID11_Msk & ((value) << PMC_PCER0_PID11_Pos)) +#define PMC_PCER0_PID12_Pos _U_(12) /**< (PMC_PCER0) Peripheral Clock 12 Enable Position */ +#define PMC_PCER0_PID12_Msk (_U_(0x1) << PMC_PCER0_PID12_Pos) /**< (PMC_PCER0) Peripheral Clock 12 Enable Mask */ +#define PMC_PCER0_PID12(value) (PMC_PCER0_PID12_Msk & ((value) << PMC_PCER0_PID12_Pos)) +#define PMC_PCER0_PID13_Pos _U_(13) /**< (PMC_PCER0) Peripheral Clock 13 Enable Position */ +#define PMC_PCER0_PID13_Msk (_U_(0x1) << PMC_PCER0_PID13_Pos) /**< (PMC_PCER0) Peripheral Clock 13 Enable Mask */ +#define PMC_PCER0_PID13(value) (PMC_PCER0_PID13_Msk & ((value) << PMC_PCER0_PID13_Pos)) +#define PMC_PCER0_PID14_Pos _U_(14) /**< (PMC_PCER0) Peripheral Clock 14 Enable Position */ +#define PMC_PCER0_PID14_Msk (_U_(0x1) << PMC_PCER0_PID14_Pos) /**< (PMC_PCER0) Peripheral Clock 14 Enable Mask */ +#define PMC_PCER0_PID14(value) (PMC_PCER0_PID14_Msk & ((value) << PMC_PCER0_PID14_Pos)) +#define PMC_PCER0_PID15_Pos _U_(15) /**< (PMC_PCER0) Peripheral Clock 15 Enable Position */ +#define PMC_PCER0_PID15_Msk (_U_(0x1) << PMC_PCER0_PID15_Pos) /**< (PMC_PCER0) Peripheral Clock 15 Enable Mask */ +#define PMC_PCER0_PID15(value) (PMC_PCER0_PID15_Msk & ((value) << PMC_PCER0_PID15_Pos)) +#define PMC_PCER0_PID16_Pos _U_(16) /**< (PMC_PCER0) Peripheral Clock 16 Enable Position */ +#define PMC_PCER0_PID16_Msk (_U_(0x1) << PMC_PCER0_PID16_Pos) /**< (PMC_PCER0) Peripheral Clock 16 Enable Mask */ +#define PMC_PCER0_PID16(value) (PMC_PCER0_PID16_Msk & ((value) << PMC_PCER0_PID16_Pos)) +#define PMC_PCER0_PID17_Pos _U_(17) /**< (PMC_PCER0) Peripheral Clock 17 Enable Position */ +#define PMC_PCER0_PID17_Msk (_U_(0x1) << PMC_PCER0_PID17_Pos) /**< (PMC_PCER0) Peripheral Clock 17 Enable Mask */ +#define PMC_PCER0_PID17(value) (PMC_PCER0_PID17_Msk & ((value) << PMC_PCER0_PID17_Pos)) +#define PMC_PCER0_PID18_Pos _U_(18) /**< (PMC_PCER0) Peripheral Clock 18 Enable Position */ +#define PMC_PCER0_PID18_Msk (_U_(0x1) << PMC_PCER0_PID18_Pos) /**< (PMC_PCER0) Peripheral Clock 18 Enable Mask */ +#define PMC_PCER0_PID18(value) (PMC_PCER0_PID18_Msk & ((value) << PMC_PCER0_PID18_Pos)) +#define PMC_PCER0_PID19_Pos _U_(19) /**< (PMC_PCER0) Peripheral Clock 19 Enable Position */ +#define PMC_PCER0_PID19_Msk (_U_(0x1) << PMC_PCER0_PID19_Pos) /**< (PMC_PCER0) Peripheral Clock 19 Enable Mask */ +#define PMC_PCER0_PID19(value) (PMC_PCER0_PID19_Msk & ((value) << PMC_PCER0_PID19_Pos)) +#define PMC_PCER0_PID20_Pos _U_(20) /**< (PMC_PCER0) Peripheral Clock 20 Enable Position */ +#define PMC_PCER0_PID20_Msk (_U_(0x1) << PMC_PCER0_PID20_Pos) /**< (PMC_PCER0) Peripheral Clock 20 Enable Mask */ +#define PMC_PCER0_PID20(value) (PMC_PCER0_PID20_Msk & ((value) << PMC_PCER0_PID20_Pos)) +#define PMC_PCER0_PID21_Pos _U_(21) /**< (PMC_PCER0) Peripheral Clock 21 Enable Position */ +#define PMC_PCER0_PID21_Msk (_U_(0x1) << PMC_PCER0_PID21_Pos) /**< (PMC_PCER0) Peripheral Clock 21 Enable Mask */ +#define PMC_PCER0_PID21(value) (PMC_PCER0_PID21_Msk & ((value) << PMC_PCER0_PID21_Pos)) +#define PMC_PCER0_PID22_Pos _U_(22) /**< (PMC_PCER0) Peripheral Clock 22 Enable Position */ +#define PMC_PCER0_PID22_Msk (_U_(0x1) << PMC_PCER0_PID22_Pos) /**< (PMC_PCER0) Peripheral Clock 22 Enable Mask */ +#define PMC_PCER0_PID22(value) (PMC_PCER0_PID22_Msk & ((value) << PMC_PCER0_PID22_Pos)) +#define PMC_PCER0_PID23_Pos _U_(23) /**< (PMC_PCER0) Peripheral Clock 23 Enable Position */ +#define PMC_PCER0_PID23_Msk (_U_(0x1) << PMC_PCER0_PID23_Pos) /**< (PMC_PCER0) Peripheral Clock 23 Enable Mask */ +#define PMC_PCER0_PID23(value) (PMC_PCER0_PID23_Msk & ((value) << PMC_PCER0_PID23_Pos)) +#define PMC_PCER0_PID24_Pos _U_(24) /**< (PMC_PCER0) Peripheral Clock 24 Enable Position */ +#define PMC_PCER0_PID24_Msk (_U_(0x1) << PMC_PCER0_PID24_Pos) /**< (PMC_PCER0) Peripheral Clock 24 Enable Mask */ +#define PMC_PCER0_PID24(value) (PMC_PCER0_PID24_Msk & ((value) << PMC_PCER0_PID24_Pos)) +#define PMC_PCER0_PID25_Pos _U_(25) /**< (PMC_PCER0) Peripheral Clock 25 Enable Position */ +#define PMC_PCER0_PID25_Msk (_U_(0x1) << PMC_PCER0_PID25_Pos) /**< (PMC_PCER0) Peripheral Clock 25 Enable Mask */ +#define PMC_PCER0_PID25(value) (PMC_PCER0_PID25_Msk & ((value) << PMC_PCER0_PID25_Pos)) +#define PMC_PCER0_PID26_Pos _U_(26) /**< (PMC_PCER0) Peripheral Clock 26 Enable Position */ +#define PMC_PCER0_PID26_Msk (_U_(0x1) << PMC_PCER0_PID26_Pos) /**< (PMC_PCER0) Peripheral Clock 26 Enable Mask */ +#define PMC_PCER0_PID26(value) (PMC_PCER0_PID26_Msk & ((value) << PMC_PCER0_PID26_Pos)) +#define PMC_PCER0_PID27_Pos _U_(27) /**< (PMC_PCER0) Peripheral Clock 27 Enable Position */ +#define PMC_PCER0_PID27_Msk (_U_(0x1) << PMC_PCER0_PID27_Pos) /**< (PMC_PCER0) Peripheral Clock 27 Enable Mask */ +#define PMC_PCER0_PID27(value) (PMC_PCER0_PID27_Msk & ((value) << PMC_PCER0_PID27_Pos)) +#define PMC_PCER0_PID28_Pos _U_(28) /**< (PMC_PCER0) Peripheral Clock 28 Enable Position */ +#define PMC_PCER0_PID28_Msk (_U_(0x1) << PMC_PCER0_PID28_Pos) /**< (PMC_PCER0) Peripheral Clock 28 Enable Mask */ +#define PMC_PCER0_PID28(value) (PMC_PCER0_PID28_Msk & ((value) << PMC_PCER0_PID28_Pos)) +#define PMC_PCER0_PID29_Pos _U_(29) /**< (PMC_PCER0) Peripheral Clock 29 Enable Position */ +#define PMC_PCER0_PID29_Msk (_U_(0x1) << PMC_PCER0_PID29_Pos) /**< (PMC_PCER0) Peripheral Clock 29 Enable Mask */ +#define PMC_PCER0_PID29(value) (PMC_PCER0_PID29_Msk & ((value) << PMC_PCER0_PID29_Pos)) +#define PMC_PCER0_PID30_Pos _U_(30) /**< (PMC_PCER0) Peripheral Clock 30 Enable Position */ +#define PMC_PCER0_PID30_Msk (_U_(0x1) << PMC_PCER0_PID30_Pos) /**< (PMC_PCER0) Peripheral Clock 30 Enable Mask */ +#define PMC_PCER0_PID30(value) (PMC_PCER0_PID30_Msk & ((value) << PMC_PCER0_PID30_Pos)) +#define PMC_PCER0_PID31_Pos _U_(31) /**< (PMC_PCER0) Peripheral Clock 31 Enable Position */ +#define PMC_PCER0_PID31_Msk (_U_(0x1) << PMC_PCER0_PID31_Pos) /**< (PMC_PCER0) Peripheral Clock 31 Enable Mask */ +#define PMC_PCER0_PID31(value) (PMC_PCER0_PID31_Msk & ((value) << PMC_PCER0_PID31_Pos)) +#define PMC_PCER0_Msk _U_(0xFFFFFF80) /**< (PMC_PCER0) Register Mask */ + +#define PMC_PCER0_PID_Pos _U_(7) /**< (PMC_PCER0 Position) Peripheral Clock 3x Enable */ +#define PMC_PCER0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCER0_PID_Pos) /**< (PMC_PCER0 Mask) PID */ +#define PMC_PCER0_PID(value) (PMC_PCER0_PID_Msk & ((value) << PMC_PCER0_PID_Pos)) + +/* -------- PMC_PCDR0 : (PMC Offset: 0x14) ( /W 32) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7_Pos _U_(7) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Position */ +#define PMC_PCDR0_PID7_Msk (_U_(0x1) << PMC_PCDR0_PID7_Pos) /**< (PMC_PCDR0) Peripheral Clock 7 Disable Mask */ +#define PMC_PCDR0_PID7(value) (PMC_PCDR0_PID7_Msk & ((value) << PMC_PCDR0_PID7_Pos)) +#define PMC_PCDR0_PID8_Pos _U_(8) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Position */ +#define PMC_PCDR0_PID8_Msk (_U_(0x1) << PMC_PCDR0_PID8_Pos) /**< (PMC_PCDR0) Peripheral Clock 8 Disable Mask */ +#define PMC_PCDR0_PID8(value) (PMC_PCDR0_PID8_Msk & ((value) << PMC_PCDR0_PID8_Pos)) +#define PMC_PCDR0_PID9_Pos _U_(9) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Position */ +#define PMC_PCDR0_PID9_Msk (_U_(0x1) << PMC_PCDR0_PID9_Pos) /**< (PMC_PCDR0) Peripheral Clock 9 Disable Mask */ +#define PMC_PCDR0_PID9(value) (PMC_PCDR0_PID9_Msk & ((value) << PMC_PCDR0_PID9_Pos)) +#define PMC_PCDR0_PID10_Pos _U_(10) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Position */ +#define PMC_PCDR0_PID10_Msk (_U_(0x1) << PMC_PCDR0_PID10_Pos) /**< (PMC_PCDR0) Peripheral Clock 10 Disable Mask */ +#define PMC_PCDR0_PID10(value) (PMC_PCDR0_PID10_Msk & ((value) << PMC_PCDR0_PID10_Pos)) +#define PMC_PCDR0_PID11_Pos _U_(11) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Position */ +#define PMC_PCDR0_PID11_Msk (_U_(0x1) << PMC_PCDR0_PID11_Pos) /**< (PMC_PCDR0) Peripheral Clock 11 Disable Mask */ +#define PMC_PCDR0_PID11(value) (PMC_PCDR0_PID11_Msk & ((value) << PMC_PCDR0_PID11_Pos)) +#define PMC_PCDR0_PID12_Pos _U_(12) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Position */ +#define PMC_PCDR0_PID12_Msk (_U_(0x1) << PMC_PCDR0_PID12_Pos) /**< (PMC_PCDR0) Peripheral Clock 12 Disable Mask */ +#define PMC_PCDR0_PID12(value) (PMC_PCDR0_PID12_Msk & ((value) << PMC_PCDR0_PID12_Pos)) +#define PMC_PCDR0_PID13_Pos _U_(13) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Position */ +#define PMC_PCDR0_PID13_Msk (_U_(0x1) << PMC_PCDR0_PID13_Pos) /**< (PMC_PCDR0) Peripheral Clock 13 Disable Mask */ +#define PMC_PCDR0_PID13(value) (PMC_PCDR0_PID13_Msk & ((value) << PMC_PCDR0_PID13_Pos)) +#define PMC_PCDR0_PID14_Pos _U_(14) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Position */ +#define PMC_PCDR0_PID14_Msk (_U_(0x1) << PMC_PCDR0_PID14_Pos) /**< (PMC_PCDR0) Peripheral Clock 14 Disable Mask */ +#define PMC_PCDR0_PID14(value) (PMC_PCDR0_PID14_Msk & ((value) << PMC_PCDR0_PID14_Pos)) +#define PMC_PCDR0_PID15_Pos _U_(15) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Position */ +#define PMC_PCDR0_PID15_Msk (_U_(0x1) << PMC_PCDR0_PID15_Pos) /**< (PMC_PCDR0) Peripheral Clock 15 Disable Mask */ +#define PMC_PCDR0_PID15(value) (PMC_PCDR0_PID15_Msk & ((value) << PMC_PCDR0_PID15_Pos)) +#define PMC_PCDR0_PID16_Pos _U_(16) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Position */ +#define PMC_PCDR0_PID16_Msk (_U_(0x1) << PMC_PCDR0_PID16_Pos) /**< (PMC_PCDR0) Peripheral Clock 16 Disable Mask */ +#define PMC_PCDR0_PID16(value) (PMC_PCDR0_PID16_Msk & ((value) << PMC_PCDR0_PID16_Pos)) +#define PMC_PCDR0_PID17_Pos _U_(17) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Position */ +#define PMC_PCDR0_PID17_Msk (_U_(0x1) << PMC_PCDR0_PID17_Pos) /**< (PMC_PCDR0) Peripheral Clock 17 Disable Mask */ +#define PMC_PCDR0_PID17(value) (PMC_PCDR0_PID17_Msk & ((value) << PMC_PCDR0_PID17_Pos)) +#define PMC_PCDR0_PID18_Pos _U_(18) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Position */ +#define PMC_PCDR0_PID18_Msk (_U_(0x1) << PMC_PCDR0_PID18_Pos) /**< (PMC_PCDR0) Peripheral Clock 18 Disable Mask */ +#define PMC_PCDR0_PID18(value) (PMC_PCDR0_PID18_Msk & ((value) << PMC_PCDR0_PID18_Pos)) +#define PMC_PCDR0_PID19_Pos _U_(19) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Position */ +#define PMC_PCDR0_PID19_Msk (_U_(0x1) << PMC_PCDR0_PID19_Pos) /**< (PMC_PCDR0) Peripheral Clock 19 Disable Mask */ +#define PMC_PCDR0_PID19(value) (PMC_PCDR0_PID19_Msk & ((value) << PMC_PCDR0_PID19_Pos)) +#define PMC_PCDR0_PID20_Pos _U_(20) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Position */ +#define PMC_PCDR0_PID20_Msk (_U_(0x1) << PMC_PCDR0_PID20_Pos) /**< (PMC_PCDR0) Peripheral Clock 20 Disable Mask */ +#define PMC_PCDR0_PID20(value) (PMC_PCDR0_PID20_Msk & ((value) << PMC_PCDR0_PID20_Pos)) +#define PMC_PCDR0_PID21_Pos _U_(21) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Position */ +#define PMC_PCDR0_PID21_Msk (_U_(0x1) << PMC_PCDR0_PID21_Pos) /**< (PMC_PCDR0) Peripheral Clock 21 Disable Mask */ +#define PMC_PCDR0_PID21(value) (PMC_PCDR0_PID21_Msk & ((value) << PMC_PCDR0_PID21_Pos)) +#define PMC_PCDR0_PID22_Pos _U_(22) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Position */ +#define PMC_PCDR0_PID22_Msk (_U_(0x1) << PMC_PCDR0_PID22_Pos) /**< (PMC_PCDR0) Peripheral Clock 22 Disable Mask */ +#define PMC_PCDR0_PID22(value) (PMC_PCDR0_PID22_Msk & ((value) << PMC_PCDR0_PID22_Pos)) +#define PMC_PCDR0_PID23_Pos _U_(23) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Position */ +#define PMC_PCDR0_PID23_Msk (_U_(0x1) << PMC_PCDR0_PID23_Pos) /**< (PMC_PCDR0) Peripheral Clock 23 Disable Mask */ +#define PMC_PCDR0_PID23(value) (PMC_PCDR0_PID23_Msk & ((value) << PMC_PCDR0_PID23_Pos)) +#define PMC_PCDR0_PID24_Pos _U_(24) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Position */ +#define PMC_PCDR0_PID24_Msk (_U_(0x1) << PMC_PCDR0_PID24_Pos) /**< (PMC_PCDR0) Peripheral Clock 24 Disable Mask */ +#define PMC_PCDR0_PID24(value) (PMC_PCDR0_PID24_Msk & ((value) << PMC_PCDR0_PID24_Pos)) +#define PMC_PCDR0_PID25_Pos _U_(25) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Position */ +#define PMC_PCDR0_PID25_Msk (_U_(0x1) << PMC_PCDR0_PID25_Pos) /**< (PMC_PCDR0) Peripheral Clock 25 Disable Mask */ +#define PMC_PCDR0_PID25(value) (PMC_PCDR0_PID25_Msk & ((value) << PMC_PCDR0_PID25_Pos)) +#define PMC_PCDR0_PID26_Pos _U_(26) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Position */ +#define PMC_PCDR0_PID26_Msk (_U_(0x1) << PMC_PCDR0_PID26_Pos) /**< (PMC_PCDR0) Peripheral Clock 26 Disable Mask */ +#define PMC_PCDR0_PID26(value) (PMC_PCDR0_PID26_Msk & ((value) << PMC_PCDR0_PID26_Pos)) +#define PMC_PCDR0_PID27_Pos _U_(27) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Position */ +#define PMC_PCDR0_PID27_Msk (_U_(0x1) << PMC_PCDR0_PID27_Pos) /**< (PMC_PCDR0) Peripheral Clock 27 Disable Mask */ +#define PMC_PCDR0_PID27(value) (PMC_PCDR0_PID27_Msk & ((value) << PMC_PCDR0_PID27_Pos)) +#define PMC_PCDR0_PID28_Pos _U_(28) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Position */ +#define PMC_PCDR0_PID28_Msk (_U_(0x1) << PMC_PCDR0_PID28_Pos) /**< (PMC_PCDR0) Peripheral Clock 28 Disable Mask */ +#define PMC_PCDR0_PID28(value) (PMC_PCDR0_PID28_Msk & ((value) << PMC_PCDR0_PID28_Pos)) +#define PMC_PCDR0_PID29_Pos _U_(29) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Position */ +#define PMC_PCDR0_PID29_Msk (_U_(0x1) << PMC_PCDR0_PID29_Pos) /**< (PMC_PCDR0) Peripheral Clock 29 Disable Mask */ +#define PMC_PCDR0_PID29(value) (PMC_PCDR0_PID29_Msk & ((value) << PMC_PCDR0_PID29_Pos)) +#define PMC_PCDR0_PID30_Pos _U_(30) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Position */ +#define PMC_PCDR0_PID30_Msk (_U_(0x1) << PMC_PCDR0_PID30_Pos) /**< (PMC_PCDR0) Peripheral Clock 30 Disable Mask */ +#define PMC_PCDR0_PID30(value) (PMC_PCDR0_PID30_Msk & ((value) << PMC_PCDR0_PID30_Pos)) +#define PMC_PCDR0_PID31_Pos _U_(31) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Position */ +#define PMC_PCDR0_PID31_Msk (_U_(0x1) << PMC_PCDR0_PID31_Pos) /**< (PMC_PCDR0) Peripheral Clock 31 Disable Mask */ +#define PMC_PCDR0_PID31(value) (PMC_PCDR0_PID31_Msk & ((value) << PMC_PCDR0_PID31_Pos)) +#define PMC_PCDR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCDR0) Register Mask */ + +#define PMC_PCDR0_PID_Pos _U_(7) /**< (PMC_PCDR0 Position) Peripheral Clock 3x Disable */ +#define PMC_PCDR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCDR0_PID_Pos) /**< (PMC_PCDR0 Mask) PID */ +#define PMC_PCDR0_PID(value) (PMC_PCDR0_PID_Msk & ((value) << PMC_PCDR0_PID_Pos)) + +/* -------- PMC_PCSR0 : (PMC Offset: 0x18) ( R/ 32) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7_Pos _U_(7) /**< (PMC_PCSR0) Peripheral Clock 7 Status Position */ +#define PMC_PCSR0_PID7_Msk (_U_(0x1) << PMC_PCSR0_PID7_Pos) /**< (PMC_PCSR0) Peripheral Clock 7 Status Mask */ +#define PMC_PCSR0_PID7(value) (PMC_PCSR0_PID7_Msk & ((value) << PMC_PCSR0_PID7_Pos)) +#define PMC_PCSR0_PID8_Pos _U_(8) /**< (PMC_PCSR0) Peripheral Clock 8 Status Position */ +#define PMC_PCSR0_PID8_Msk (_U_(0x1) << PMC_PCSR0_PID8_Pos) /**< (PMC_PCSR0) Peripheral Clock 8 Status Mask */ +#define PMC_PCSR0_PID8(value) (PMC_PCSR0_PID8_Msk & ((value) << PMC_PCSR0_PID8_Pos)) +#define PMC_PCSR0_PID9_Pos _U_(9) /**< (PMC_PCSR0) Peripheral Clock 9 Status Position */ +#define PMC_PCSR0_PID9_Msk (_U_(0x1) << PMC_PCSR0_PID9_Pos) /**< (PMC_PCSR0) Peripheral Clock 9 Status Mask */ +#define PMC_PCSR0_PID9(value) (PMC_PCSR0_PID9_Msk & ((value) << PMC_PCSR0_PID9_Pos)) +#define PMC_PCSR0_PID10_Pos _U_(10) /**< (PMC_PCSR0) Peripheral Clock 10 Status Position */ +#define PMC_PCSR0_PID10_Msk (_U_(0x1) << PMC_PCSR0_PID10_Pos) /**< (PMC_PCSR0) Peripheral Clock 10 Status Mask */ +#define PMC_PCSR0_PID10(value) (PMC_PCSR0_PID10_Msk & ((value) << PMC_PCSR0_PID10_Pos)) +#define PMC_PCSR0_PID11_Pos _U_(11) /**< (PMC_PCSR0) Peripheral Clock 11 Status Position */ +#define PMC_PCSR0_PID11_Msk (_U_(0x1) << PMC_PCSR0_PID11_Pos) /**< (PMC_PCSR0) Peripheral Clock 11 Status Mask */ +#define PMC_PCSR0_PID11(value) (PMC_PCSR0_PID11_Msk & ((value) << PMC_PCSR0_PID11_Pos)) +#define PMC_PCSR0_PID12_Pos _U_(12) /**< (PMC_PCSR0) Peripheral Clock 12 Status Position */ +#define PMC_PCSR0_PID12_Msk (_U_(0x1) << PMC_PCSR0_PID12_Pos) /**< (PMC_PCSR0) Peripheral Clock 12 Status Mask */ +#define PMC_PCSR0_PID12(value) (PMC_PCSR0_PID12_Msk & ((value) << PMC_PCSR0_PID12_Pos)) +#define PMC_PCSR0_PID13_Pos _U_(13) /**< (PMC_PCSR0) Peripheral Clock 13 Status Position */ +#define PMC_PCSR0_PID13_Msk (_U_(0x1) << PMC_PCSR0_PID13_Pos) /**< (PMC_PCSR0) Peripheral Clock 13 Status Mask */ +#define PMC_PCSR0_PID13(value) (PMC_PCSR0_PID13_Msk & ((value) << PMC_PCSR0_PID13_Pos)) +#define PMC_PCSR0_PID14_Pos _U_(14) /**< (PMC_PCSR0) Peripheral Clock 14 Status Position */ +#define PMC_PCSR0_PID14_Msk (_U_(0x1) << PMC_PCSR0_PID14_Pos) /**< (PMC_PCSR0) Peripheral Clock 14 Status Mask */ +#define PMC_PCSR0_PID14(value) (PMC_PCSR0_PID14_Msk & ((value) << PMC_PCSR0_PID14_Pos)) +#define PMC_PCSR0_PID15_Pos _U_(15) /**< (PMC_PCSR0) Peripheral Clock 15 Status Position */ +#define PMC_PCSR0_PID15_Msk (_U_(0x1) << PMC_PCSR0_PID15_Pos) /**< (PMC_PCSR0) Peripheral Clock 15 Status Mask */ +#define PMC_PCSR0_PID15(value) (PMC_PCSR0_PID15_Msk & ((value) << PMC_PCSR0_PID15_Pos)) +#define PMC_PCSR0_PID16_Pos _U_(16) /**< (PMC_PCSR0) Peripheral Clock 16 Status Position */ +#define PMC_PCSR0_PID16_Msk (_U_(0x1) << PMC_PCSR0_PID16_Pos) /**< (PMC_PCSR0) Peripheral Clock 16 Status Mask */ +#define PMC_PCSR0_PID16(value) (PMC_PCSR0_PID16_Msk & ((value) << PMC_PCSR0_PID16_Pos)) +#define PMC_PCSR0_PID17_Pos _U_(17) /**< (PMC_PCSR0) Peripheral Clock 17 Status Position */ +#define PMC_PCSR0_PID17_Msk (_U_(0x1) << PMC_PCSR0_PID17_Pos) /**< (PMC_PCSR0) Peripheral Clock 17 Status Mask */ +#define PMC_PCSR0_PID17(value) (PMC_PCSR0_PID17_Msk & ((value) << PMC_PCSR0_PID17_Pos)) +#define PMC_PCSR0_PID18_Pos _U_(18) /**< (PMC_PCSR0) Peripheral Clock 18 Status Position */ +#define PMC_PCSR0_PID18_Msk (_U_(0x1) << PMC_PCSR0_PID18_Pos) /**< (PMC_PCSR0) Peripheral Clock 18 Status Mask */ +#define PMC_PCSR0_PID18(value) (PMC_PCSR0_PID18_Msk & ((value) << PMC_PCSR0_PID18_Pos)) +#define PMC_PCSR0_PID19_Pos _U_(19) /**< (PMC_PCSR0) Peripheral Clock 19 Status Position */ +#define PMC_PCSR0_PID19_Msk (_U_(0x1) << PMC_PCSR0_PID19_Pos) /**< (PMC_PCSR0) Peripheral Clock 19 Status Mask */ +#define PMC_PCSR0_PID19(value) (PMC_PCSR0_PID19_Msk & ((value) << PMC_PCSR0_PID19_Pos)) +#define PMC_PCSR0_PID20_Pos _U_(20) /**< (PMC_PCSR0) Peripheral Clock 20 Status Position */ +#define PMC_PCSR0_PID20_Msk (_U_(0x1) << PMC_PCSR0_PID20_Pos) /**< (PMC_PCSR0) Peripheral Clock 20 Status Mask */ +#define PMC_PCSR0_PID20(value) (PMC_PCSR0_PID20_Msk & ((value) << PMC_PCSR0_PID20_Pos)) +#define PMC_PCSR0_PID21_Pos _U_(21) /**< (PMC_PCSR0) Peripheral Clock 21 Status Position */ +#define PMC_PCSR0_PID21_Msk (_U_(0x1) << PMC_PCSR0_PID21_Pos) /**< (PMC_PCSR0) Peripheral Clock 21 Status Mask */ +#define PMC_PCSR0_PID21(value) (PMC_PCSR0_PID21_Msk & ((value) << PMC_PCSR0_PID21_Pos)) +#define PMC_PCSR0_PID22_Pos _U_(22) /**< (PMC_PCSR0) Peripheral Clock 22 Status Position */ +#define PMC_PCSR0_PID22_Msk (_U_(0x1) << PMC_PCSR0_PID22_Pos) /**< (PMC_PCSR0) Peripheral Clock 22 Status Mask */ +#define PMC_PCSR0_PID22(value) (PMC_PCSR0_PID22_Msk & ((value) << PMC_PCSR0_PID22_Pos)) +#define PMC_PCSR0_PID23_Pos _U_(23) /**< (PMC_PCSR0) Peripheral Clock 23 Status Position */ +#define PMC_PCSR0_PID23_Msk (_U_(0x1) << PMC_PCSR0_PID23_Pos) /**< (PMC_PCSR0) Peripheral Clock 23 Status Mask */ +#define PMC_PCSR0_PID23(value) (PMC_PCSR0_PID23_Msk & ((value) << PMC_PCSR0_PID23_Pos)) +#define PMC_PCSR0_PID24_Pos _U_(24) /**< (PMC_PCSR0) Peripheral Clock 24 Status Position */ +#define PMC_PCSR0_PID24_Msk (_U_(0x1) << PMC_PCSR0_PID24_Pos) /**< (PMC_PCSR0) Peripheral Clock 24 Status Mask */ +#define PMC_PCSR0_PID24(value) (PMC_PCSR0_PID24_Msk & ((value) << PMC_PCSR0_PID24_Pos)) +#define PMC_PCSR0_PID25_Pos _U_(25) /**< (PMC_PCSR0) Peripheral Clock 25 Status Position */ +#define PMC_PCSR0_PID25_Msk (_U_(0x1) << PMC_PCSR0_PID25_Pos) /**< (PMC_PCSR0) Peripheral Clock 25 Status Mask */ +#define PMC_PCSR0_PID25(value) (PMC_PCSR0_PID25_Msk & ((value) << PMC_PCSR0_PID25_Pos)) +#define PMC_PCSR0_PID26_Pos _U_(26) /**< (PMC_PCSR0) Peripheral Clock 26 Status Position */ +#define PMC_PCSR0_PID26_Msk (_U_(0x1) << PMC_PCSR0_PID26_Pos) /**< (PMC_PCSR0) Peripheral Clock 26 Status Mask */ +#define PMC_PCSR0_PID26(value) (PMC_PCSR0_PID26_Msk & ((value) << PMC_PCSR0_PID26_Pos)) +#define PMC_PCSR0_PID27_Pos _U_(27) /**< (PMC_PCSR0) Peripheral Clock 27 Status Position */ +#define PMC_PCSR0_PID27_Msk (_U_(0x1) << PMC_PCSR0_PID27_Pos) /**< (PMC_PCSR0) Peripheral Clock 27 Status Mask */ +#define PMC_PCSR0_PID27(value) (PMC_PCSR0_PID27_Msk & ((value) << PMC_PCSR0_PID27_Pos)) +#define PMC_PCSR0_PID28_Pos _U_(28) /**< (PMC_PCSR0) Peripheral Clock 28 Status Position */ +#define PMC_PCSR0_PID28_Msk (_U_(0x1) << PMC_PCSR0_PID28_Pos) /**< (PMC_PCSR0) Peripheral Clock 28 Status Mask */ +#define PMC_PCSR0_PID28(value) (PMC_PCSR0_PID28_Msk & ((value) << PMC_PCSR0_PID28_Pos)) +#define PMC_PCSR0_PID29_Pos _U_(29) /**< (PMC_PCSR0) Peripheral Clock 29 Status Position */ +#define PMC_PCSR0_PID29_Msk (_U_(0x1) << PMC_PCSR0_PID29_Pos) /**< (PMC_PCSR0) Peripheral Clock 29 Status Mask */ +#define PMC_PCSR0_PID29(value) (PMC_PCSR0_PID29_Msk & ((value) << PMC_PCSR0_PID29_Pos)) +#define PMC_PCSR0_PID30_Pos _U_(30) /**< (PMC_PCSR0) Peripheral Clock 30 Status Position */ +#define PMC_PCSR0_PID30_Msk (_U_(0x1) << PMC_PCSR0_PID30_Pos) /**< (PMC_PCSR0) Peripheral Clock 30 Status Mask */ +#define PMC_PCSR0_PID30(value) (PMC_PCSR0_PID30_Msk & ((value) << PMC_PCSR0_PID30_Pos)) +#define PMC_PCSR0_PID31_Pos _U_(31) /**< (PMC_PCSR0) Peripheral Clock 31 Status Position */ +#define PMC_PCSR0_PID31_Msk (_U_(0x1) << PMC_PCSR0_PID31_Pos) /**< (PMC_PCSR0) Peripheral Clock 31 Status Mask */ +#define PMC_PCSR0_PID31(value) (PMC_PCSR0_PID31_Msk & ((value) << PMC_PCSR0_PID31_Pos)) +#define PMC_PCSR0_Msk _U_(0xFFFFFF80) /**< (PMC_PCSR0) Register Mask */ + +#define PMC_PCSR0_PID_Pos _U_(7) /**< (PMC_PCSR0 Position) Peripheral Clock 3x Status */ +#define PMC_PCSR0_PID_Msk (_U_(0x1FFFFFF) << PMC_PCSR0_PID_Pos) /**< (PMC_PCSR0 Mask) PID */ +#define PMC_PCSR0_PID(value) (PMC_PCSR0_PID_Msk & ((value) << PMC_PCSR0_PID_Pos)) + +/* -------- CKGR_UCKR : (PMC Offset: 0x1C) (R/W 32) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN_Pos _U_(16) /**< (CKGR_UCKR) UTMI PLL Enable Position */ +#define CKGR_UCKR_UPLLEN_Msk (_U_(0x1) << CKGR_UCKR_UPLLEN_Pos) /**< (CKGR_UCKR) UTMI PLL Enable Mask */ +#define CKGR_UCKR_UPLLEN(value) (CKGR_UCKR_UPLLEN_Msk & ((value) << CKGR_UCKR_UPLLEN_Pos)) +#define CKGR_UCKR_UPLLCOUNT_Pos _U_(20) /**< (CKGR_UCKR) UTMI PLL Start-up Time Position */ +#define CKGR_UCKR_UPLLCOUNT_Msk (_U_(0xF) << CKGR_UCKR_UPLLCOUNT_Pos) /**< (CKGR_UCKR) UTMI PLL Start-up Time Mask */ +#define CKGR_UCKR_UPLLCOUNT(value) (CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)) +#define CKGR_UCKR_Msk _U_(0x00F10000) /**< (CKGR_UCKR) Register Mask */ + + +/* -------- CKGR_MOR : (PMC Offset: 0x20) (R/W 32) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN_Pos _U_(0) /**< (CKGR_MOR) Main Crystal Oscillator Enable Position */ +#define CKGR_MOR_MOSCXTEN_Msk (_U_(0x1) << CKGR_MOR_MOSCXTEN_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Enable Mask */ +#define CKGR_MOR_MOSCXTEN(value) (CKGR_MOR_MOSCXTEN_Msk & ((value) << CKGR_MOR_MOSCXTEN_Pos)) +#define CKGR_MOR_MOSCXTBY_Pos _U_(1) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Position */ +#define CKGR_MOR_MOSCXTBY_Msk (_U_(0x1) << CKGR_MOR_MOSCXTBY_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Bypass Mask */ +#define CKGR_MOR_MOSCXTBY(value) (CKGR_MOR_MOSCXTBY_Msk & ((value) << CKGR_MOR_MOSCXTBY_Pos)) +#define CKGR_MOR_WAITMODE_Pos _U_(2) /**< (CKGR_MOR) Wait Mode Command (Write-only) Position */ +#define CKGR_MOR_WAITMODE_Msk (_U_(0x1) << CKGR_MOR_WAITMODE_Pos) /**< (CKGR_MOR) Wait Mode Command (Write-only) Mask */ +#define CKGR_MOR_WAITMODE(value) (CKGR_MOR_WAITMODE_Msk & ((value) << CKGR_MOR_WAITMODE_Pos)) +#define CKGR_MOR_MOSCRCEN_Pos _U_(3) /**< (CKGR_MOR) Main RC Oscillator Enable Position */ +#define CKGR_MOR_MOSCRCEN_Msk (_U_(0x1) << CKGR_MOR_MOSCRCEN_Pos) /**< (CKGR_MOR) Main RC Oscillator Enable Mask */ +#define CKGR_MOR_MOSCRCEN(value) (CKGR_MOR_MOSCRCEN_Msk & ((value) << CKGR_MOR_MOSCRCEN_Pos)) +#define CKGR_MOR_MOSCRCF_Pos _U_(4) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Position */ +#define CKGR_MOR_MOSCRCF_Msk (_U_(0x7) << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) Main RC Oscillator Frequency Selection Mask */ +#define CKGR_MOR_MOSCRCF(value) (CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)) +#define CKGR_MOR_MOSCRCF_4_MHz_Val _U_(0x0) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz */ +#define CKGR_MOR_MOSCRCF_8_MHz_Val _U_(0x1) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz_Val _U_(0x2) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCRCF_4_MHz (CKGR_MOR_MOSCRCF_4_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 4 MHz Position */ +#define CKGR_MOR_MOSCRCF_8_MHz (CKGR_MOR_MOSCRCF_8_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 8 MHz Position */ +#define CKGR_MOR_MOSCRCF_12_MHz (CKGR_MOR_MOSCRCF_12_MHz_Val << CKGR_MOR_MOSCRCF_Pos) /**< (CKGR_MOR) The RC oscillator frequency is at 12 MHz Position */ +#define CKGR_MOR_MOSCXTST_Pos _U_(8) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Position */ +#define CKGR_MOR_MOSCXTST_Msk (_U_(0xFF) << CKGR_MOR_MOSCXTST_Pos) /**< (CKGR_MOR) Main Crystal Oscillator Startup Time Mask */ +#define CKGR_MOR_MOSCXTST(value) (CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)) +#define CKGR_MOR_KEY_Pos _U_(16) /**< (CKGR_MOR) Write Access Password Position */ +#define CKGR_MOR_KEY_Msk (_U_(0xFF) << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Write Access Password Mask */ +#define CKGR_MOR_KEY(value) (CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)) +#define CKGR_MOR_KEY_PASSWD_Val _U_(0x37) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_KEY_PASSWD (CKGR_MOR_KEY_PASSWD_Val << CKGR_MOR_KEY_Pos) /**< (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define CKGR_MOR_MOSCSEL_Pos _U_(24) /**< (CKGR_MOR) Main Clock Oscillator Selection Position */ +#define CKGR_MOR_MOSCSEL_Msk (_U_(0x1) << CKGR_MOR_MOSCSEL_Pos) /**< (CKGR_MOR) Main Clock Oscillator Selection Mask */ +#define CKGR_MOR_MOSCSEL(value) (CKGR_MOR_MOSCSEL_Msk & ((value) << CKGR_MOR_MOSCSEL_Pos)) +#define CKGR_MOR_CFDEN_Pos _U_(25) /**< (CKGR_MOR) Clock Failure Detector Enable Position */ +#define CKGR_MOR_CFDEN_Msk (_U_(0x1) << CKGR_MOR_CFDEN_Pos) /**< (CKGR_MOR) Clock Failure Detector Enable Mask */ +#define CKGR_MOR_CFDEN(value) (CKGR_MOR_CFDEN_Msk & ((value) << CKGR_MOR_CFDEN_Pos)) +#define CKGR_MOR_XT32KFME_Pos _U_(26) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Position */ +#define CKGR_MOR_XT32KFME_Msk (_U_(0x1) << CKGR_MOR_XT32KFME_Pos) /**< (CKGR_MOR) 32.768 kHz Crystal Oscillator Frequency Monitoring Enable Mask */ +#define CKGR_MOR_XT32KFME(value) (CKGR_MOR_XT32KFME_Msk & ((value) << CKGR_MOR_XT32KFME_Pos)) +#define CKGR_MOR_Msk _U_(0x07FFFF7F) /**< (CKGR_MOR) Register Mask */ + + +/* -------- CKGR_MCFR : (PMC Offset: 0x24) (R/W 32) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos _U_(0) /**< (CKGR_MCFR) Main Clock Frequency Position */ +#define CKGR_MCFR_MAINF_Msk (_U_(0xFFFF) << CKGR_MCFR_MAINF_Pos) /**< (CKGR_MCFR) Main Clock Frequency Mask */ +#define CKGR_MCFR_MAINF(value) (CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)) +#define CKGR_MCFR_MAINFRDY_Pos _U_(16) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Position */ +#define CKGR_MCFR_MAINFRDY_Msk (_U_(0x1) << CKGR_MCFR_MAINFRDY_Pos) /**< (CKGR_MCFR) Main Clock Frequency Measure Ready Mask */ +#define CKGR_MCFR_MAINFRDY(value) (CKGR_MCFR_MAINFRDY_Msk & ((value) << CKGR_MCFR_MAINFRDY_Pos)) +#define CKGR_MCFR_RCMEAS_Pos _U_(20) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Position */ +#define CKGR_MCFR_RCMEAS_Msk (_U_(0x1) << CKGR_MCFR_RCMEAS_Pos) /**< (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) Mask */ +#define CKGR_MCFR_RCMEAS(value) (CKGR_MCFR_RCMEAS_Msk & ((value) << CKGR_MCFR_RCMEAS_Pos)) +#define CKGR_MCFR_CCSS_Pos _U_(24) /**< (CKGR_MCFR) Counter Clock Source Selection Position */ +#define CKGR_MCFR_CCSS_Msk (_U_(0x1) << CKGR_MCFR_CCSS_Pos) /**< (CKGR_MCFR) Counter Clock Source Selection Mask */ +#define CKGR_MCFR_CCSS(value) (CKGR_MCFR_CCSS_Msk & ((value) << CKGR_MCFR_CCSS_Pos)) +#define CKGR_MCFR_Msk _U_(0x0111FFFF) /**< (CKGR_MCFR) Register Mask */ + + +/* -------- CKGR_PLLAR : (PMC Offset: 0x28) (R/W 32) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos _U_(0) /**< (CKGR_PLLAR) PLLA Front End Divider Position */ +#define CKGR_PLLAR_DIVA_Msk (_U_(0xFF) << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) PLLA Front End Divider Mask */ +#define CKGR_PLLAR_DIVA(value) (CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)) +#define CKGR_PLLAR_DIVA_0_Val _U_(0x0) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS_Val _U_(0x1) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_DIVA_0 (CKGR_PLLAR_DIVA_0_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. Position */ +#define CKGR_PLLAR_DIVA_BYPASS (CKGR_PLLAR_DIVA_BYPASS_Val << CKGR_PLLAR_DIVA_Pos) /**< (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. Position */ +#define CKGR_PLLAR_PLLACOUNT_Pos _U_(8) /**< (CKGR_PLLAR) PLLA Counter Position */ +#define CKGR_PLLAR_PLLACOUNT_Msk (_U_(0x3F) << CKGR_PLLAR_PLLACOUNT_Pos) /**< (CKGR_PLLAR) PLLA Counter Mask */ +#define CKGR_PLLAR_PLLACOUNT(value) (CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)) +#define CKGR_PLLAR_MULA_Pos _U_(16) /**< (CKGR_PLLAR) PLLA Multiplier Position */ +#define CKGR_PLLAR_MULA_Msk (_U_(0x7FF) << CKGR_PLLAR_MULA_Pos) /**< (CKGR_PLLAR) PLLA Multiplier Mask */ +#define CKGR_PLLAR_MULA(value) (CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)) +#define CKGR_PLLAR_ONE_Pos _U_(29) /**< (CKGR_PLLAR) Must Be Set to 1 Position */ +#define CKGR_PLLAR_ONE_Msk (_U_(0x1) << CKGR_PLLAR_ONE_Pos) /**< (CKGR_PLLAR) Must Be Set to 1 Mask */ +#define CKGR_PLLAR_ONE(value) (CKGR_PLLAR_ONE_Msk & ((value) << CKGR_PLLAR_ONE_Pos)) +#define CKGR_PLLAR_Msk _U_(0x27FF3FFF) /**< (CKGR_PLLAR) Register Mask */ + + +/* -------- PMC_MCKR : (PMC Offset: 0x30) (R/W 32) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos _U_(0) /**< (PMC_MCKR) Master Clock Source Selection Position */ +#define PMC_MCKR_CSS_Msk (_U_(0x3) << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Master Clock Source Selection Mask */ +#define PMC_MCKR_CSS(value) (PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)) +#define PMC_MCKR_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_CSS_SLOW_CLK (PMC_MCKR_CSS_SLOW_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Slow Clock is selected Position */ +#define PMC_MCKR_CSS_MAIN_CLK (PMC_MCKR_CSS_MAIN_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Main Clock is selected Position */ +#define PMC_MCKR_CSS_PLLA_CLK (PMC_MCKR_CSS_PLLA_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) PLLA Clock is selected Position */ +#define PMC_MCKR_CSS_UPLL_CLK (PMC_MCKR_CSS_UPLL_CLK_Val << PMC_MCKR_CSS_Pos) /**< (PMC_MCKR) Divided UPLL Clock is selected Position */ +#define PMC_MCKR_PRES_Pos _U_(4) /**< (PMC_MCKR) Processor Clock Prescaler Position */ +#define PMC_MCKR_PRES_Msk (_U_(0x7) << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Processor Clock Prescaler Mask */ +#define PMC_MCKR_PRES(value) (PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)) +#define PMC_MCKR_PRES_CLK_1_Val _U_(0x0) /**< (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2_Val _U_(0x1) /**< (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4_Val _U_(0x2) /**< (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8_Val _U_(0x3) /**< (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16_Val _U_(0x4) /**< (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32_Val _U_(0x5) /**< (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64_Val _U_(0x6) /**< (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3_Val _U_(0x7) /**< (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PRES_CLK_1 (PMC_MCKR_PRES_CLK_1_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock Position */ +#define PMC_MCKR_PRES_CLK_2 (PMC_MCKR_PRES_CLK_2_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 2 Position */ +#define PMC_MCKR_PRES_CLK_4 (PMC_MCKR_PRES_CLK_4_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 4 Position */ +#define PMC_MCKR_PRES_CLK_8 (PMC_MCKR_PRES_CLK_8_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 8 Position */ +#define PMC_MCKR_PRES_CLK_16 (PMC_MCKR_PRES_CLK_16_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 16 Position */ +#define PMC_MCKR_PRES_CLK_32 (PMC_MCKR_PRES_CLK_32_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 32 Position */ +#define PMC_MCKR_PRES_CLK_64 (PMC_MCKR_PRES_CLK_64_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 64 Position */ +#define PMC_MCKR_PRES_CLK_3 (PMC_MCKR_PRES_CLK_3_Val << PMC_MCKR_PRES_Pos) /**< (PMC_MCKR) Selected clock divided by 3 Position */ +#define PMC_MCKR_MDIV_Pos _U_(8) /**< (PMC_MCKR) Master Clock Division Position */ +#define PMC_MCKR_MDIV_Msk (_U_(0x3) << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock Division Mask */ +#define PMC_MCKR_MDIV(value) (PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)) +#define PMC_MCKR_MDIV_EQ_PCK_Val _U_(0x0) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2_Val _U_(0x1) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4_Val _U_(0x2) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3_Val _U_(0x3) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_MDIV_EQ_PCK (PMC_MCKR_MDIV_EQ_PCK_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. Position */ +#define PMC_MCKR_MDIV_PCK_DIV2 (PMC_MCKR_MDIV_PCK_DIV2_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. Position */ +#define PMC_MCKR_MDIV_PCK_DIV4 (PMC_MCKR_MDIV_PCK_DIV4_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. Position */ +#define PMC_MCKR_MDIV_PCK_DIV3 (PMC_MCKR_MDIV_PCK_DIV3_Val << PMC_MCKR_MDIV_Pos) /**< (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. Position */ +#define PMC_MCKR_UPLLDIV2_Pos _U_(13) /**< (PMC_MCKR) UPLL Divider by 2 Position */ +#define PMC_MCKR_UPLLDIV2_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV2_Pos) /**< (PMC_MCKR) UPLL Divider by 2 Mask */ +#define PMC_MCKR_UPLLDIV2(value) (PMC_MCKR_UPLLDIV2_Msk & ((value) << PMC_MCKR_UPLLDIV2_Pos)) +#define PMC_MCKR_Msk _U_(0x00002373) /**< (PMC_MCKR) Register Mask */ + +#define PMC_MCKR_UPLLDIV_Pos _U_(13) /**< (PMC_MCKR Position) UPLL Divider by 2 */ +#define PMC_MCKR_UPLLDIV_Msk (_U_(0x1) << PMC_MCKR_UPLLDIV_Pos) /**< (PMC_MCKR Mask) UPLLDIV */ +#define PMC_MCKR_UPLLDIV(value) (PMC_MCKR_UPLLDIV_Msk & ((value) << PMC_MCKR_UPLLDIV_Pos)) + +/* -------- PMC_USB : (PMC Offset: 0x38) (R/W 32) USB Clock Register -------- */ +#define PMC_USB_USBS_Pos _U_(0) /**< (PMC_USB) USB Input Clock Selection Position */ +#define PMC_USB_USBS_Msk (_U_(0x1) << PMC_USB_USBS_Pos) /**< (PMC_USB) USB Input Clock Selection Mask */ +#define PMC_USB_USBS(value) (PMC_USB_USBS_Msk & ((value) << PMC_USB_USBS_Pos)) +#define PMC_USB_USBDIV_Pos _U_(8) /**< (PMC_USB) Divider for USB_48M Position */ +#define PMC_USB_USBDIV_Msk (_U_(0xF) << PMC_USB_USBDIV_Pos) /**< (PMC_USB) Divider for USB_48M Mask */ +#define PMC_USB_USBDIV(value) (PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)) +#define PMC_USB_Msk _U_(0x00000F01) /**< (PMC_USB) Register Mask */ + + +/* -------- PMC_PCK : (PMC Offset: 0x40) (R/W 32) Programmable Clock Register -------- */ +#define PMC_PCK_CSS_Pos _U_(0) /**< (PMC_PCK) Programmable Clock Source Selection Position */ +#define PMC_PCK_CSS_Msk (_U_(0x7) << PMC_PCK_CSS_Pos) /**< (PMC_PCK) Programmable Clock Source Selection Mask */ +#define PMC_PCK_CSS(value) (PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)) +#define PMC_PCK_CSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCK) SLCK is selected */ +#define PMC_PCK_CSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCK) MAINCK is selected */ +#define PMC_PCK_CSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCK) PLLACK is selected */ +#define PMC_PCK_CSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCK) UPLLCKDIV is selected */ +#define PMC_PCK_CSS_MCK_Val _U_(0x4) /**< (PMC_PCK) MCK is selected */ +#define PMC_PCK_CSS_SLOW_CLK (PMC_PCK_CSS_SLOW_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) SLCK is selected Position */ +#define PMC_PCK_CSS_MAIN_CLK (PMC_PCK_CSS_MAIN_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MAINCK is selected Position */ +#define PMC_PCK_CSS_PLLA_CLK (PMC_PCK_CSS_PLLA_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) PLLACK is selected Position */ +#define PMC_PCK_CSS_UPLL_CLK (PMC_PCK_CSS_UPLL_CLK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) UPLLCKDIV is selected Position */ +#define PMC_PCK_CSS_MCK (PMC_PCK_CSS_MCK_Val << PMC_PCK_CSS_Pos) /**< (PMC_PCK) MCK is selected Position */ +#define PMC_PCK_PRES_Pos _U_(4) /**< (PMC_PCK) Programmable Clock Prescaler Position */ +#define PMC_PCK_PRES_Msk (_U_(0xFF) << PMC_PCK_PRES_Pos) /**< (PMC_PCK) Programmable Clock Prescaler Mask */ +#define PMC_PCK_PRES(value) (PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)) +#define PMC_PCK_Msk _U_(0x00000FF7) /**< (PMC_PCK) Register Mask */ + + +/* -------- PMC_IER : (PMC Offset: 0x60) ( /W 32) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS_Pos _U_(0) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCXTS_Msk (_U_(0x1) << PMC_IER_MOSCXTS_Pos) /**< (PMC_IER) Main Crystal Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCXTS(value) (PMC_IER_MOSCXTS_Msk & ((value) << PMC_IER_MOSCXTS_Pos)) +#define PMC_IER_LOCKA_Pos _U_(1) /**< (PMC_IER) PLLA Lock Interrupt Enable Position */ +#define PMC_IER_LOCKA_Msk (_U_(0x1) << PMC_IER_LOCKA_Pos) /**< (PMC_IER) PLLA Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKA(value) (PMC_IER_LOCKA_Msk & ((value) << PMC_IER_LOCKA_Pos)) +#define PMC_IER_MCKRDY_Pos _U_(3) /**< (PMC_IER) Master Clock Ready Interrupt Enable Position */ +#define PMC_IER_MCKRDY_Msk (_U_(0x1) << PMC_IER_MCKRDY_Pos) /**< (PMC_IER) Master Clock Ready Interrupt Enable Mask */ +#define PMC_IER_MCKRDY(value) (PMC_IER_MCKRDY_Msk & ((value) << PMC_IER_MCKRDY_Pos)) +#define PMC_IER_LOCKU_Pos _U_(6) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Position */ +#define PMC_IER_LOCKU_Msk (_U_(0x1) << PMC_IER_LOCKU_Pos) /**< (PMC_IER) UTMI PLL Lock Interrupt Enable Mask */ +#define PMC_IER_LOCKU(value) (PMC_IER_LOCKU_Msk & ((value) << PMC_IER_LOCKU_Pos)) +#define PMC_IER_PCKRDY0_Pos _U_(8) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Position */ +#define PMC_IER_PCKRDY0_Msk (_U_(0x1) << PMC_IER_PCKRDY0_Pos) /**< (PMC_IER) Programmable Clock Ready 0 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY0(value) (PMC_IER_PCKRDY0_Msk & ((value) << PMC_IER_PCKRDY0_Pos)) +#define PMC_IER_PCKRDY1_Pos _U_(9) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Position */ +#define PMC_IER_PCKRDY1_Msk (_U_(0x1) << PMC_IER_PCKRDY1_Pos) /**< (PMC_IER) Programmable Clock Ready 1 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY1(value) (PMC_IER_PCKRDY1_Msk & ((value) << PMC_IER_PCKRDY1_Pos)) +#define PMC_IER_PCKRDY2_Pos _U_(10) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Position */ +#define PMC_IER_PCKRDY2_Msk (_U_(0x1) << PMC_IER_PCKRDY2_Pos) /**< (PMC_IER) Programmable Clock Ready 2 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY2(value) (PMC_IER_PCKRDY2_Msk & ((value) << PMC_IER_PCKRDY2_Pos)) +#define PMC_IER_PCKRDY3_Pos _U_(11) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Position */ +#define PMC_IER_PCKRDY3_Msk (_U_(0x1) << PMC_IER_PCKRDY3_Pos) /**< (PMC_IER) Programmable Clock Ready 3 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY3(value) (PMC_IER_PCKRDY3_Msk & ((value) << PMC_IER_PCKRDY3_Pos)) +#define PMC_IER_PCKRDY4_Pos _U_(12) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Position */ +#define PMC_IER_PCKRDY4_Msk (_U_(0x1) << PMC_IER_PCKRDY4_Pos) /**< (PMC_IER) Programmable Clock Ready 4 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY4(value) (PMC_IER_PCKRDY4_Msk & ((value) << PMC_IER_PCKRDY4_Pos)) +#define PMC_IER_PCKRDY5_Pos _U_(13) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Position */ +#define PMC_IER_PCKRDY5_Msk (_U_(0x1) << PMC_IER_PCKRDY5_Pos) /**< (PMC_IER) Programmable Clock Ready 5 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY5(value) (PMC_IER_PCKRDY5_Msk & ((value) << PMC_IER_PCKRDY5_Pos)) +#define PMC_IER_PCKRDY6_Pos _U_(14) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Position */ +#define PMC_IER_PCKRDY6_Msk (_U_(0x1) << PMC_IER_PCKRDY6_Pos) /**< (PMC_IER) Programmable Clock Ready 6 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY6(value) (PMC_IER_PCKRDY6_Msk & ((value) << PMC_IER_PCKRDY6_Pos)) +#define PMC_IER_PCKRDY7_Pos _U_(15) /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Position */ +#define PMC_IER_PCKRDY7_Msk (_U_(0x1) << PMC_IER_PCKRDY7_Pos) /**< (PMC_IER) Programmable Clock Ready 7 Interrupt Enable Mask */ +#define PMC_IER_PCKRDY7(value) (PMC_IER_PCKRDY7_Msk & ((value) << PMC_IER_PCKRDY7_Pos)) +#define PMC_IER_MOSCSELS_Pos _U_(16) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Position */ +#define PMC_IER_MOSCSELS_Msk (_U_(0x1) << PMC_IER_MOSCSELS_Pos) /**< (PMC_IER) Main Clock Source Oscillator Selection Status Interrupt Enable Mask */ +#define PMC_IER_MOSCSELS(value) (PMC_IER_MOSCSELS_Msk & ((value) << PMC_IER_MOSCSELS_Pos)) +#define PMC_IER_MOSCRCS_Pos _U_(17) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Position */ +#define PMC_IER_MOSCRCS_Msk (_U_(0x1) << PMC_IER_MOSCRCS_Pos) /**< (PMC_IER) Main RC Oscillator Status Interrupt Enable Mask */ +#define PMC_IER_MOSCRCS(value) (PMC_IER_MOSCRCS_Msk & ((value) << PMC_IER_MOSCRCS_Pos)) +#define PMC_IER_CFDEV_Pos _U_(18) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Position */ +#define PMC_IER_CFDEV_Msk (_U_(0x1) << PMC_IER_CFDEV_Pos) /**< (PMC_IER) Clock Failure Detector Event Interrupt Enable Mask */ +#define PMC_IER_CFDEV(value) (PMC_IER_CFDEV_Msk & ((value) << PMC_IER_CFDEV_Pos)) +#define PMC_IER_XT32KERR_Pos _U_(21) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Position */ +#define PMC_IER_XT32KERR_Msk (_U_(0x1) << PMC_IER_XT32KERR_Pos) /**< (PMC_IER) 32.768 kHz Crystal Oscillator Error Interrupt Enable Mask */ +#define PMC_IER_XT32KERR(value) (PMC_IER_XT32KERR_Msk & ((value) << PMC_IER_XT32KERR_Pos)) +#define PMC_IER_Msk _U_(0x0027FF4B) /**< (PMC_IER) Register Mask */ + +#define PMC_IER_PCKRDY_Pos _U_(8) /**< (PMC_IER Position) Programmable Clock Ready x Interrupt Enable */ +#define PMC_IER_PCKRDY_Msk (_U_(0xFF) << PMC_IER_PCKRDY_Pos) /**< (PMC_IER Mask) PCKRDY */ +#define PMC_IER_PCKRDY(value) (PMC_IER_PCKRDY_Msk & ((value) << PMC_IER_PCKRDY_Pos)) + +/* -------- PMC_IDR : (PMC Offset: 0x64) ( /W 32) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS_Pos _U_(0) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Position */ +#define PMC_IDR_MOSCXTS_Msk (_U_(0x1) << PMC_IDR_MOSCXTS_Pos) /**< (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCXTS(value) (PMC_IDR_MOSCXTS_Msk & ((value) << PMC_IDR_MOSCXTS_Pos)) +#define PMC_IDR_LOCKA_Pos _U_(1) /**< (PMC_IDR) PLLA Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKA_Msk (_U_(0x1) << PMC_IDR_LOCKA_Pos) /**< (PMC_IDR) PLLA Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKA(value) (PMC_IDR_LOCKA_Msk & ((value) << PMC_IDR_LOCKA_Pos)) +#define PMC_IDR_MCKRDY_Pos _U_(3) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Position */ +#define PMC_IDR_MCKRDY_Msk (_U_(0x1) << PMC_IDR_MCKRDY_Pos) /**< (PMC_IDR) Master Clock Ready Interrupt Disable Mask */ +#define PMC_IDR_MCKRDY(value) (PMC_IDR_MCKRDY_Msk & ((value) << PMC_IDR_MCKRDY_Pos)) +#define PMC_IDR_LOCKU_Pos _U_(6) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Position */ +#define PMC_IDR_LOCKU_Msk (_U_(0x1) << PMC_IDR_LOCKU_Pos) /**< (PMC_IDR) UTMI PLL Lock Interrupt Disable Mask */ +#define PMC_IDR_LOCKU(value) (PMC_IDR_LOCKU_Msk & ((value) << PMC_IDR_LOCKU_Pos)) +#define PMC_IDR_PCKRDY0_Pos _U_(8) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY0_Msk (_U_(0x1) << PMC_IDR_PCKRDY0_Pos) /**< (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY0(value) (PMC_IDR_PCKRDY0_Msk & ((value) << PMC_IDR_PCKRDY0_Pos)) +#define PMC_IDR_PCKRDY1_Pos _U_(9) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY1_Msk (_U_(0x1) << PMC_IDR_PCKRDY1_Pos) /**< (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY1(value) (PMC_IDR_PCKRDY1_Msk & ((value) << PMC_IDR_PCKRDY1_Pos)) +#define PMC_IDR_PCKRDY2_Pos _U_(10) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY2_Msk (_U_(0x1) << PMC_IDR_PCKRDY2_Pos) /**< (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY2(value) (PMC_IDR_PCKRDY2_Msk & ((value) << PMC_IDR_PCKRDY2_Pos)) +#define PMC_IDR_PCKRDY3_Pos _U_(11) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY3_Msk (_U_(0x1) << PMC_IDR_PCKRDY3_Pos) /**< (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY3(value) (PMC_IDR_PCKRDY3_Msk & ((value) << PMC_IDR_PCKRDY3_Pos)) +#define PMC_IDR_PCKRDY4_Pos _U_(12) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY4_Msk (_U_(0x1) << PMC_IDR_PCKRDY4_Pos) /**< (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY4(value) (PMC_IDR_PCKRDY4_Msk & ((value) << PMC_IDR_PCKRDY4_Pos)) +#define PMC_IDR_PCKRDY5_Pos _U_(13) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY5_Msk (_U_(0x1) << PMC_IDR_PCKRDY5_Pos) /**< (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY5(value) (PMC_IDR_PCKRDY5_Msk & ((value) << PMC_IDR_PCKRDY5_Pos)) +#define PMC_IDR_PCKRDY6_Pos _U_(14) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY6_Msk (_U_(0x1) << PMC_IDR_PCKRDY6_Pos) /**< (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY6(value) (PMC_IDR_PCKRDY6_Msk & ((value) << PMC_IDR_PCKRDY6_Pos)) +#define PMC_IDR_PCKRDY7_Pos _U_(15) /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Position */ +#define PMC_IDR_PCKRDY7_Msk (_U_(0x1) << PMC_IDR_PCKRDY7_Pos) /**< (PMC_IDR) Programmable Clock Ready 7 Interrupt Disable Mask */ +#define PMC_IDR_PCKRDY7(value) (PMC_IDR_PCKRDY7_Msk & ((value) << PMC_IDR_PCKRDY7_Pos)) +#define PMC_IDR_MOSCSELS_Pos _U_(16) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Position */ +#define PMC_IDR_MOSCSELS_Msk (_U_(0x1) << PMC_IDR_MOSCSELS_Pos) /**< (PMC_IDR) Main Clock Source Oscillator Selection Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCSELS(value) (PMC_IDR_MOSCSELS_Msk & ((value) << PMC_IDR_MOSCSELS_Pos)) +#define PMC_IDR_MOSCRCS_Pos _U_(17) /**< (PMC_IDR) Main RC Status Interrupt Disable Position */ +#define PMC_IDR_MOSCRCS_Msk (_U_(0x1) << PMC_IDR_MOSCRCS_Pos) /**< (PMC_IDR) Main RC Status Interrupt Disable Mask */ +#define PMC_IDR_MOSCRCS(value) (PMC_IDR_MOSCRCS_Msk & ((value) << PMC_IDR_MOSCRCS_Pos)) +#define PMC_IDR_CFDEV_Pos _U_(18) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Position */ +#define PMC_IDR_CFDEV_Msk (_U_(0x1) << PMC_IDR_CFDEV_Pos) /**< (PMC_IDR) Clock Failure Detector Event Interrupt Disable Mask */ +#define PMC_IDR_CFDEV(value) (PMC_IDR_CFDEV_Msk & ((value) << PMC_IDR_CFDEV_Pos)) +#define PMC_IDR_XT32KERR_Pos _U_(21) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Position */ +#define PMC_IDR_XT32KERR_Msk (_U_(0x1) << PMC_IDR_XT32KERR_Pos) /**< (PMC_IDR) 32.768 kHz Crystal Oscillator Error Interrupt Disable Mask */ +#define PMC_IDR_XT32KERR(value) (PMC_IDR_XT32KERR_Msk & ((value) << PMC_IDR_XT32KERR_Pos)) +#define PMC_IDR_Msk _U_(0x0027FF4B) /**< (PMC_IDR) Register Mask */ + +#define PMC_IDR_PCKRDY_Pos _U_(8) /**< (PMC_IDR Position) Programmable Clock Ready x Interrupt Disable */ +#define PMC_IDR_PCKRDY_Msk (_U_(0xFF) << PMC_IDR_PCKRDY_Pos) /**< (PMC_IDR Mask) PCKRDY */ +#define PMC_IDR_PCKRDY(value) (PMC_IDR_PCKRDY_Msk & ((value) << PMC_IDR_PCKRDY_Pos)) + +/* -------- PMC_SR : (PMC Offset: 0x68) ( R/ 32) Status Register -------- */ +#define PMC_SR_MOSCXTS_Pos _U_(0) /**< (PMC_SR) Main Crystal Oscillator Status Position */ +#define PMC_SR_MOSCXTS_Msk (_U_(0x1) << PMC_SR_MOSCXTS_Pos) /**< (PMC_SR) Main Crystal Oscillator Status Mask */ +#define PMC_SR_MOSCXTS(value) (PMC_SR_MOSCXTS_Msk & ((value) << PMC_SR_MOSCXTS_Pos)) +#define PMC_SR_LOCKA_Pos _U_(1) /**< (PMC_SR) PLLA Lock Status Position */ +#define PMC_SR_LOCKA_Msk (_U_(0x1) << PMC_SR_LOCKA_Pos) /**< (PMC_SR) PLLA Lock Status Mask */ +#define PMC_SR_LOCKA(value) (PMC_SR_LOCKA_Msk & ((value) << PMC_SR_LOCKA_Pos)) +#define PMC_SR_MCKRDY_Pos _U_(3) /**< (PMC_SR) Master Clock Status Position */ +#define PMC_SR_MCKRDY_Msk (_U_(0x1) << PMC_SR_MCKRDY_Pos) /**< (PMC_SR) Master Clock Status Mask */ +#define PMC_SR_MCKRDY(value) (PMC_SR_MCKRDY_Msk & ((value) << PMC_SR_MCKRDY_Pos)) +#define PMC_SR_LOCKU_Pos _U_(6) /**< (PMC_SR) UTMI PLL Lock Status Position */ +#define PMC_SR_LOCKU_Msk (_U_(0x1) << PMC_SR_LOCKU_Pos) /**< (PMC_SR) UTMI PLL Lock Status Mask */ +#define PMC_SR_LOCKU(value) (PMC_SR_LOCKU_Msk & ((value) << PMC_SR_LOCKU_Pos)) +#define PMC_SR_OSCSELS_Pos _U_(7) /**< (PMC_SR) Slow Clock Source Oscillator Selection Position */ +#define PMC_SR_OSCSELS_Msk (_U_(0x1) << PMC_SR_OSCSELS_Pos) /**< (PMC_SR) Slow Clock Source Oscillator Selection Mask */ +#define PMC_SR_OSCSELS(value) (PMC_SR_OSCSELS_Msk & ((value) << PMC_SR_OSCSELS_Pos)) +#define PMC_SR_PCKRDY0_Pos _U_(8) /**< (PMC_SR) Programmable Clock Ready 0 Status Position */ +#define PMC_SR_PCKRDY0_Msk (_U_(0x1) << PMC_SR_PCKRDY0_Pos) /**< (PMC_SR) Programmable Clock Ready 0 Status Mask */ +#define PMC_SR_PCKRDY0(value) (PMC_SR_PCKRDY0_Msk & ((value) << PMC_SR_PCKRDY0_Pos)) +#define PMC_SR_PCKRDY1_Pos _U_(9) /**< (PMC_SR) Programmable Clock Ready 1 Status Position */ +#define PMC_SR_PCKRDY1_Msk (_U_(0x1) << PMC_SR_PCKRDY1_Pos) /**< (PMC_SR) Programmable Clock Ready 1 Status Mask */ +#define PMC_SR_PCKRDY1(value) (PMC_SR_PCKRDY1_Msk & ((value) << PMC_SR_PCKRDY1_Pos)) +#define PMC_SR_PCKRDY2_Pos _U_(10) /**< (PMC_SR) Programmable Clock Ready 2 Status Position */ +#define PMC_SR_PCKRDY2_Msk (_U_(0x1) << PMC_SR_PCKRDY2_Pos) /**< (PMC_SR) Programmable Clock Ready 2 Status Mask */ +#define PMC_SR_PCKRDY2(value) (PMC_SR_PCKRDY2_Msk & ((value) << PMC_SR_PCKRDY2_Pos)) +#define PMC_SR_PCKRDY3_Pos _U_(11) /**< (PMC_SR) Programmable Clock Ready 3 Status Position */ +#define PMC_SR_PCKRDY3_Msk (_U_(0x1) << PMC_SR_PCKRDY3_Pos) /**< (PMC_SR) Programmable Clock Ready 3 Status Mask */ +#define PMC_SR_PCKRDY3(value) (PMC_SR_PCKRDY3_Msk & ((value) << PMC_SR_PCKRDY3_Pos)) +#define PMC_SR_PCKRDY4_Pos _U_(12) /**< (PMC_SR) Programmable Clock Ready 4 Status Position */ +#define PMC_SR_PCKRDY4_Msk (_U_(0x1) << PMC_SR_PCKRDY4_Pos) /**< (PMC_SR) Programmable Clock Ready 4 Status Mask */ +#define PMC_SR_PCKRDY4(value) (PMC_SR_PCKRDY4_Msk & ((value) << PMC_SR_PCKRDY4_Pos)) +#define PMC_SR_PCKRDY5_Pos _U_(13) /**< (PMC_SR) Programmable Clock Ready 5 Status Position */ +#define PMC_SR_PCKRDY5_Msk (_U_(0x1) << PMC_SR_PCKRDY5_Pos) /**< (PMC_SR) Programmable Clock Ready 5 Status Mask */ +#define PMC_SR_PCKRDY5(value) (PMC_SR_PCKRDY5_Msk & ((value) << PMC_SR_PCKRDY5_Pos)) +#define PMC_SR_PCKRDY6_Pos _U_(14) /**< (PMC_SR) Programmable Clock Ready 6 Status Position */ +#define PMC_SR_PCKRDY6_Msk (_U_(0x1) << PMC_SR_PCKRDY6_Pos) /**< (PMC_SR) Programmable Clock Ready 6 Status Mask */ +#define PMC_SR_PCKRDY6(value) (PMC_SR_PCKRDY6_Msk & ((value) << PMC_SR_PCKRDY6_Pos)) +#define PMC_SR_PCKRDY7_Pos _U_(15) /**< (PMC_SR) Programmable Clock Ready 7 Status Position */ +#define PMC_SR_PCKRDY7_Msk (_U_(0x1) << PMC_SR_PCKRDY7_Pos) /**< (PMC_SR) Programmable Clock Ready 7 Status Mask */ +#define PMC_SR_PCKRDY7(value) (PMC_SR_PCKRDY7_Msk & ((value) << PMC_SR_PCKRDY7_Pos)) +#define PMC_SR_MOSCSELS_Pos _U_(16) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Position */ +#define PMC_SR_MOSCSELS_Msk (_U_(0x1) << PMC_SR_MOSCSELS_Pos) /**< (PMC_SR) Main Clock Source Oscillator Selection Status Mask */ +#define PMC_SR_MOSCSELS(value) (PMC_SR_MOSCSELS_Msk & ((value) << PMC_SR_MOSCSELS_Pos)) +#define PMC_SR_MOSCRCS_Pos _U_(17) /**< (PMC_SR) Main RC Oscillator Status Position */ +#define PMC_SR_MOSCRCS_Msk (_U_(0x1) << PMC_SR_MOSCRCS_Pos) /**< (PMC_SR) Main RC Oscillator Status Mask */ +#define PMC_SR_MOSCRCS(value) (PMC_SR_MOSCRCS_Msk & ((value) << PMC_SR_MOSCRCS_Pos)) +#define PMC_SR_CFDEV_Pos _U_(18) /**< (PMC_SR) Clock Failure Detector Event Position */ +#define PMC_SR_CFDEV_Msk (_U_(0x1) << PMC_SR_CFDEV_Pos) /**< (PMC_SR) Clock Failure Detector Event Mask */ +#define PMC_SR_CFDEV(value) (PMC_SR_CFDEV_Msk & ((value) << PMC_SR_CFDEV_Pos)) +#define PMC_SR_CFDS_Pos _U_(19) /**< (PMC_SR) Clock Failure Detector Status Position */ +#define PMC_SR_CFDS_Msk (_U_(0x1) << PMC_SR_CFDS_Pos) /**< (PMC_SR) Clock Failure Detector Status Mask */ +#define PMC_SR_CFDS(value) (PMC_SR_CFDS_Msk & ((value) << PMC_SR_CFDS_Pos)) +#define PMC_SR_FOS_Pos _U_(20) /**< (PMC_SR) Clock Failure Detector Fault Output Status Position */ +#define PMC_SR_FOS_Msk (_U_(0x1) << PMC_SR_FOS_Pos) /**< (PMC_SR) Clock Failure Detector Fault Output Status Mask */ +#define PMC_SR_FOS(value) (PMC_SR_FOS_Msk & ((value) << PMC_SR_FOS_Pos)) +#define PMC_SR_XT32KERR_Pos _U_(21) /**< (PMC_SR) Slow Crystal Oscillator Error Position */ +#define PMC_SR_XT32KERR_Msk (_U_(0x1) << PMC_SR_XT32KERR_Pos) /**< (PMC_SR) Slow Crystal Oscillator Error Mask */ +#define PMC_SR_XT32KERR(value) (PMC_SR_XT32KERR_Msk & ((value) << PMC_SR_XT32KERR_Pos)) +#define PMC_SR_Msk _U_(0x003FFFCB) /**< (PMC_SR) Register Mask */ + +#define PMC_SR_PCKRDY_Pos _U_(8) /**< (PMC_SR Position) Programmable Clock Ready x Status */ +#define PMC_SR_PCKRDY_Msk (_U_(0xFF) << PMC_SR_PCKRDY_Pos) /**< (PMC_SR Mask) PCKRDY */ +#define PMC_SR_PCKRDY(value) (PMC_SR_PCKRDY_Msk & ((value) << PMC_SR_PCKRDY_Pos)) + +/* -------- PMC_IMR : (PMC Offset: 0x6C) ( R/ 32) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS_Pos _U_(0) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Position */ +#define PMC_IMR_MOSCXTS_Msk (_U_(0x1) << PMC_IMR_MOSCXTS_Pos) /**< (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCXTS(value) (PMC_IMR_MOSCXTS_Msk & ((value) << PMC_IMR_MOSCXTS_Pos)) +#define PMC_IMR_LOCKA_Pos _U_(1) /**< (PMC_IMR) PLLA Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKA_Msk (_U_(0x1) << PMC_IMR_LOCKA_Pos) /**< (PMC_IMR) PLLA Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKA(value) (PMC_IMR_LOCKA_Msk & ((value) << PMC_IMR_LOCKA_Pos)) +#define PMC_IMR_MCKRDY_Pos _U_(3) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Position */ +#define PMC_IMR_MCKRDY_Msk (_U_(0x1) << PMC_IMR_MCKRDY_Pos) /**< (PMC_IMR) Master Clock Ready Interrupt Mask Mask */ +#define PMC_IMR_MCKRDY(value) (PMC_IMR_MCKRDY_Msk & ((value) << PMC_IMR_MCKRDY_Pos)) +#define PMC_IMR_LOCKU_Pos _U_(6) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Position */ +#define PMC_IMR_LOCKU_Msk (_U_(0x1) << PMC_IMR_LOCKU_Pos) /**< (PMC_IMR) UTMI PLL Lock Interrupt Mask Mask */ +#define PMC_IMR_LOCKU(value) (PMC_IMR_LOCKU_Msk & ((value) << PMC_IMR_LOCKU_Pos)) +#define PMC_IMR_PCKRDY0_Pos _U_(8) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY0_Msk (_U_(0x1) << PMC_IMR_PCKRDY0_Pos) /**< (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY0(value) (PMC_IMR_PCKRDY0_Msk & ((value) << PMC_IMR_PCKRDY0_Pos)) +#define PMC_IMR_PCKRDY1_Pos _U_(9) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY1_Msk (_U_(0x1) << PMC_IMR_PCKRDY1_Pos) /**< (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY1(value) (PMC_IMR_PCKRDY1_Msk & ((value) << PMC_IMR_PCKRDY1_Pos)) +#define PMC_IMR_PCKRDY2_Pos _U_(10) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY2_Msk (_U_(0x1) << PMC_IMR_PCKRDY2_Pos) /**< (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY2(value) (PMC_IMR_PCKRDY2_Msk & ((value) << PMC_IMR_PCKRDY2_Pos)) +#define PMC_IMR_PCKRDY3_Pos _U_(11) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY3_Msk (_U_(0x1) << PMC_IMR_PCKRDY3_Pos) /**< (PMC_IMR) Programmable Clock Ready 3 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY3(value) (PMC_IMR_PCKRDY3_Msk & ((value) << PMC_IMR_PCKRDY3_Pos)) +#define PMC_IMR_PCKRDY4_Pos _U_(12) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY4_Msk (_U_(0x1) << PMC_IMR_PCKRDY4_Pos) /**< (PMC_IMR) Programmable Clock Ready 4 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY4(value) (PMC_IMR_PCKRDY4_Msk & ((value) << PMC_IMR_PCKRDY4_Pos)) +#define PMC_IMR_PCKRDY5_Pos _U_(13) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY5_Msk (_U_(0x1) << PMC_IMR_PCKRDY5_Pos) /**< (PMC_IMR) Programmable Clock Ready 5 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY5(value) (PMC_IMR_PCKRDY5_Msk & ((value) << PMC_IMR_PCKRDY5_Pos)) +#define PMC_IMR_PCKRDY6_Pos _U_(14) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY6_Msk (_U_(0x1) << PMC_IMR_PCKRDY6_Pos) /**< (PMC_IMR) Programmable Clock Ready 6 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY6(value) (PMC_IMR_PCKRDY6_Msk & ((value) << PMC_IMR_PCKRDY6_Pos)) +#define PMC_IMR_PCKRDY7_Pos _U_(15) /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Position */ +#define PMC_IMR_PCKRDY7_Msk (_U_(0x1) << PMC_IMR_PCKRDY7_Pos) /**< (PMC_IMR) Programmable Clock Ready 7 Interrupt Mask Mask */ +#define PMC_IMR_PCKRDY7(value) (PMC_IMR_PCKRDY7_Msk & ((value) << PMC_IMR_PCKRDY7_Pos)) +#define PMC_IMR_MOSCSELS_Pos _U_(16) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Position */ +#define PMC_IMR_MOSCSELS_Msk (_U_(0x1) << PMC_IMR_MOSCSELS_Pos) /**< (PMC_IMR) Main Clock Source Oscillator Selection Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCSELS(value) (PMC_IMR_MOSCSELS_Msk & ((value) << PMC_IMR_MOSCSELS_Pos)) +#define PMC_IMR_MOSCRCS_Pos _U_(17) /**< (PMC_IMR) Main RC Status Interrupt Mask Position */ +#define PMC_IMR_MOSCRCS_Msk (_U_(0x1) << PMC_IMR_MOSCRCS_Pos) /**< (PMC_IMR) Main RC Status Interrupt Mask Mask */ +#define PMC_IMR_MOSCRCS(value) (PMC_IMR_MOSCRCS_Msk & ((value) << PMC_IMR_MOSCRCS_Pos)) +#define PMC_IMR_CFDEV_Pos _U_(18) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Position */ +#define PMC_IMR_CFDEV_Msk (_U_(0x1) << PMC_IMR_CFDEV_Pos) /**< (PMC_IMR) Clock Failure Detector Event Interrupt Mask Mask */ +#define PMC_IMR_CFDEV(value) (PMC_IMR_CFDEV_Msk & ((value) << PMC_IMR_CFDEV_Pos)) +#define PMC_IMR_XT32KERR_Pos _U_(21) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Position */ +#define PMC_IMR_XT32KERR_Msk (_U_(0x1) << PMC_IMR_XT32KERR_Pos) /**< (PMC_IMR) 32.768 kHz Crystal Oscillator Error Interrupt Mask Mask */ +#define PMC_IMR_XT32KERR(value) (PMC_IMR_XT32KERR_Msk & ((value) << PMC_IMR_XT32KERR_Pos)) +#define PMC_IMR_Msk _U_(0x0027FF4B) /**< (PMC_IMR) Register Mask */ + +#define PMC_IMR_PCKRDY_Pos _U_(8) /**< (PMC_IMR Position) Programmable Clock Ready x Interrupt Mask */ +#define PMC_IMR_PCKRDY_Msk (_U_(0xFF) << PMC_IMR_PCKRDY_Pos) /**< (PMC_IMR Mask) PCKRDY */ +#define PMC_IMR_PCKRDY(value) (PMC_IMR_PCKRDY_Msk & ((value) << PMC_IMR_PCKRDY_Pos)) + +/* -------- PMC_FSMR : (PMC Offset: 0x70) (R/W 32) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0_Pos _U_(0) /**< (PMC_FSMR) Fast Startup Input Enable 0 Position */ +#define PMC_FSMR_FSTT0_Msk (_U_(0x1) << PMC_FSMR_FSTT0_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 0 Mask */ +#define PMC_FSMR_FSTT0(value) (PMC_FSMR_FSTT0_Msk & ((value) << PMC_FSMR_FSTT0_Pos)) +#define PMC_FSMR_FSTT1_Pos _U_(1) /**< (PMC_FSMR) Fast Startup Input Enable 1 Position */ +#define PMC_FSMR_FSTT1_Msk (_U_(0x1) << PMC_FSMR_FSTT1_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 1 Mask */ +#define PMC_FSMR_FSTT1(value) (PMC_FSMR_FSTT1_Msk & ((value) << PMC_FSMR_FSTT1_Pos)) +#define PMC_FSMR_FSTT2_Pos _U_(2) /**< (PMC_FSMR) Fast Startup Input Enable 2 Position */ +#define PMC_FSMR_FSTT2_Msk (_U_(0x1) << PMC_FSMR_FSTT2_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 2 Mask */ +#define PMC_FSMR_FSTT2(value) (PMC_FSMR_FSTT2_Msk & ((value) << PMC_FSMR_FSTT2_Pos)) +#define PMC_FSMR_FSTT3_Pos _U_(3) /**< (PMC_FSMR) Fast Startup Input Enable 3 Position */ +#define PMC_FSMR_FSTT3_Msk (_U_(0x1) << PMC_FSMR_FSTT3_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 3 Mask */ +#define PMC_FSMR_FSTT3(value) (PMC_FSMR_FSTT3_Msk & ((value) << PMC_FSMR_FSTT3_Pos)) +#define PMC_FSMR_FSTT4_Pos _U_(4) /**< (PMC_FSMR) Fast Startup Input Enable 4 Position */ +#define PMC_FSMR_FSTT4_Msk (_U_(0x1) << PMC_FSMR_FSTT4_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 4 Mask */ +#define PMC_FSMR_FSTT4(value) (PMC_FSMR_FSTT4_Msk & ((value) << PMC_FSMR_FSTT4_Pos)) +#define PMC_FSMR_FSTT5_Pos _U_(5) /**< (PMC_FSMR) Fast Startup Input Enable 5 Position */ +#define PMC_FSMR_FSTT5_Msk (_U_(0x1) << PMC_FSMR_FSTT5_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 5 Mask */ +#define PMC_FSMR_FSTT5(value) (PMC_FSMR_FSTT5_Msk & ((value) << PMC_FSMR_FSTT5_Pos)) +#define PMC_FSMR_FSTT6_Pos _U_(6) /**< (PMC_FSMR) Fast Startup Input Enable 6 Position */ +#define PMC_FSMR_FSTT6_Msk (_U_(0x1) << PMC_FSMR_FSTT6_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 6 Mask */ +#define PMC_FSMR_FSTT6(value) (PMC_FSMR_FSTT6_Msk & ((value) << PMC_FSMR_FSTT6_Pos)) +#define PMC_FSMR_FSTT7_Pos _U_(7) /**< (PMC_FSMR) Fast Startup Input Enable 7 Position */ +#define PMC_FSMR_FSTT7_Msk (_U_(0x1) << PMC_FSMR_FSTT7_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 7 Mask */ +#define PMC_FSMR_FSTT7(value) (PMC_FSMR_FSTT7_Msk & ((value) << PMC_FSMR_FSTT7_Pos)) +#define PMC_FSMR_FSTT8_Pos _U_(8) /**< (PMC_FSMR) Fast Startup Input Enable 8 Position */ +#define PMC_FSMR_FSTT8_Msk (_U_(0x1) << PMC_FSMR_FSTT8_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 8 Mask */ +#define PMC_FSMR_FSTT8(value) (PMC_FSMR_FSTT8_Msk & ((value) << PMC_FSMR_FSTT8_Pos)) +#define PMC_FSMR_FSTT9_Pos _U_(9) /**< (PMC_FSMR) Fast Startup Input Enable 9 Position */ +#define PMC_FSMR_FSTT9_Msk (_U_(0x1) << PMC_FSMR_FSTT9_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 9 Mask */ +#define PMC_FSMR_FSTT9(value) (PMC_FSMR_FSTT9_Msk & ((value) << PMC_FSMR_FSTT9_Pos)) +#define PMC_FSMR_FSTT10_Pos _U_(10) /**< (PMC_FSMR) Fast Startup Input Enable 10 Position */ +#define PMC_FSMR_FSTT10_Msk (_U_(0x1) << PMC_FSMR_FSTT10_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 10 Mask */ +#define PMC_FSMR_FSTT10(value) (PMC_FSMR_FSTT10_Msk & ((value) << PMC_FSMR_FSTT10_Pos)) +#define PMC_FSMR_FSTT11_Pos _U_(11) /**< (PMC_FSMR) Fast Startup Input Enable 11 Position */ +#define PMC_FSMR_FSTT11_Msk (_U_(0x1) << PMC_FSMR_FSTT11_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 11 Mask */ +#define PMC_FSMR_FSTT11(value) (PMC_FSMR_FSTT11_Msk & ((value) << PMC_FSMR_FSTT11_Pos)) +#define PMC_FSMR_FSTT12_Pos _U_(12) /**< (PMC_FSMR) Fast Startup Input Enable 12 Position */ +#define PMC_FSMR_FSTT12_Msk (_U_(0x1) << PMC_FSMR_FSTT12_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 12 Mask */ +#define PMC_FSMR_FSTT12(value) (PMC_FSMR_FSTT12_Msk & ((value) << PMC_FSMR_FSTT12_Pos)) +#define PMC_FSMR_FSTT13_Pos _U_(13) /**< (PMC_FSMR) Fast Startup Input Enable 13 Position */ +#define PMC_FSMR_FSTT13_Msk (_U_(0x1) << PMC_FSMR_FSTT13_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 13 Mask */ +#define PMC_FSMR_FSTT13(value) (PMC_FSMR_FSTT13_Msk & ((value) << PMC_FSMR_FSTT13_Pos)) +#define PMC_FSMR_FSTT14_Pos _U_(14) /**< (PMC_FSMR) Fast Startup Input Enable 14 Position */ +#define PMC_FSMR_FSTT14_Msk (_U_(0x1) << PMC_FSMR_FSTT14_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 14 Mask */ +#define PMC_FSMR_FSTT14(value) (PMC_FSMR_FSTT14_Msk & ((value) << PMC_FSMR_FSTT14_Pos)) +#define PMC_FSMR_FSTT15_Pos _U_(15) /**< (PMC_FSMR) Fast Startup Input Enable 15 Position */ +#define PMC_FSMR_FSTT15_Msk (_U_(0x1) << PMC_FSMR_FSTT15_Pos) /**< (PMC_FSMR) Fast Startup Input Enable 15 Mask */ +#define PMC_FSMR_FSTT15(value) (PMC_FSMR_FSTT15_Msk & ((value) << PMC_FSMR_FSTT15_Pos)) +#define PMC_FSMR_RTTAL_Pos _U_(16) /**< (PMC_FSMR) RTT Alarm Enable Position */ +#define PMC_FSMR_RTTAL_Msk (_U_(0x1) << PMC_FSMR_RTTAL_Pos) /**< (PMC_FSMR) RTT Alarm Enable Mask */ +#define PMC_FSMR_RTTAL(value) (PMC_FSMR_RTTAL_Msk & ((value) << PMC_FSMR_RTTAL_Pos)) +#define PMC_FSMR_RTCAL_Pos _U_(17) /**< (PMC_FSMR) RTC Alarm Enable Position */ +#define PMC_FSMR_RTCAL_Msk (_U_(0x1) << PMC_FSMR_RTCAL_Pos) /**< (PMC_FSMR) RTC Alarm Enable Mask */ +#define PMC_FSMR_RTCAL(value) (PMC_FSMR_RTCAL_Msk & ((value) << PMC_FSMR_RTCAL_Pos)) +#define PMC_FSMR_USBAL_Pos _U_(18) /**< (PMC_FSMR) USB Alarm Enable Position */ +#define PMC_FSMR_USBAL_Msk (_U_(0x1) << PMC_FSMR_USBAL_Pos) /**< (PMC_FSMR) USB Alarm Enable Mask */ +#define PMC_FSMR_USBAL(value) (PMC_FSMR_USBAL_Msk & ((value) << PMC_FSMR_USBAL_Pos)) +#define PMC_FSMR_LPM_Pos _U_(20) /**< (PMC_FSMR) Low-power Mode Position */ +#define PMC_FSMR_LPM_Msk (_U_(0x1) << PMC_FSMR_LPM_Pos) /**< (PMC_FSMR) Low-power Mode Mask */ +#define PMC_FSMR_LPM(value) (PMC_FSMR_LPM_Msk & ((value) << PMC_FSMR_LPM_Pos)) +#define PMC_FSMR_FLPM_Pos _U_(21) /**< (PMC_FSMR) Flash Low-power Mode Position */ +#define PMC_FSMR_FLPM_Msk (_U_(0x3) << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash Low-power Mode Mask */ +#define PMC_FSMR_FLPM(value) (PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)) +#define PMC_FSMR_FLPM_FLASH_STANDBY_Val _U_(0x0) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val _U_(0x1) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE_Val _U_(0x2) /**< (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FLPM_FLASH_STANDBY (PMC_FSMR_FLPM_FLASH_STANDBY_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode Position */ +#define PMC_FSMR_FLPM_FLASH_IDLE (PMC_FSMR_FLPM_FLASH_IDLE_Val << PMC_FSMR_FLPM_Pos) /**< (PMC_FSMR) Idle mode Position */ +#define PMC_FSMR_FFLPM_Pos _U_(23) /**< (PMC_FSMR) Force Flash Low-power Mode Position */ +#define PMC_FSMR_FFLPM_Msk (_U_(0x1) << PMC_FSMR_FFLPM_Pos) /**< (PMC_FSMR) Force Flash Low-power Mode Mask */ +#define PMC_FSMR_FFLPM(value) (PMC_FSMR_FFLPM_Msk & ((value) << PMC_FSMR_FFLPM_Pos)) +#define PMC_FSMR_Msk _U_(0x00F7FFFF) /**< (PMC_FSMR) Register Mask */ + +#define PMC_FSMR_FSTT_Pos _U_(0) /**< (PMC_FSMR Position) Fast Startup Input Enable x */ +#define PMC_FSMR_FSTT_Msk (_U_(0xFFFF) << PMC_FSMR_FSTT_Pos) /**< (PMC_FSMR Mask) FSTT */ +#define PMC_FSMR_FSTT(value) (PMC_FSMR_FSTT_Msk & ((value) << PMC_FSMR_FSTT_Pos)) + +/* -------- PMC_FSPR : (PMC Offset: 0x74) (R/W 32) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0_Pos _U_(0) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Position */ +#define PMC_FSPR_FSTP0_Msk (_U_(0x1) << PMC_FSPR_FSTP0_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 0 Mask */ +#define PMC_FSPR_FSTP0(value) (PMC_FSPR_FSTP0_Msk & ((value) << PMC_FSPR_FSTP0_Pos)) +#define PMC_FSPR_FSTP1_Pos _U_(1) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Position */ +#define PMC_FSPR_FSTP1_Msk (_U_(0x1) << PMC_FSPR_FSTP1_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 1 Mask */ +#define PMC_FSPR_FSTP1(value) (PMC_FSPR_FSTP1_Msk & ((value) << PMC_FSPR_FSTP1_Pos)) +#define PMC_FSPR_FSTP2_Pos _U_(2) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Position */ +#define PMC_FSPR_FSTP2_Msk (_U_(0x1) << PMC_FSPR_FSTP2_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 2 Mask */ +#define PMC_FSPR_FSTP2(value) (PMC_FSPR_FSTP2_Msk & ((value) << PMC_FSPR_FSTP2_Pos)) +#define PMC_FSPR_FSTP3_Pos _U_(3) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Position */ +#define PMC_FSPR_FSTP3_Msk (_U_(0x1) << PMC_FSPR_FSTP3_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 3 Mask */ +#define PMC_FSPR_FSTP3(value) (PMC_FSPR_FSTP3_Msk & ((value) << PMC_FSPR_FSTP3_Pos)) +#define PMC_FSPR_FSTP4_Pos _U_(4) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Position */ +#define PMC_FSPR_FSTP4_Msk (_U_(0x1) << PMC_FSPR_FSTP4_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 4 Mask */ +#define PMC_FSPR_FSTP4(value) (PMC_FSPR_FSTP4_Msk & ((value) << PMC_FSPR_FSTP4_Pos)) +#define PMC_FSPR_FSTP5_Pos _U_(5) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Position */ +#define PMC_FSPR_FSTP5_Msk (_U_(0x1) << PMC_FSPR_FSTP5_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 5 Mask */ +#define PMC_FSPR_FSTP5(value) (PMC_FSPR_FSTP5_Msk & ((value) << PMC_FSPR_FSTP5_Pos)) +#define PMC_FSPR_FSTP6_Pos _U_(6) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Position */ +#define PMC_FSPR_FSTP6_Msk (_U_(0x1) << PMC_FSPR_FSTP6_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 6 Mask */ +#define PMC_FSPR_FSTP6(value) (PMC_FSPR_FSTP6_Msk & ((value) << PMC_FSPR_FSTP6_Pos)) +#define PMC_FSPR_FSTP7_Pos _U_(7) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Position */ +#define PMC_FSPR_FSTP7_Msk (_U_(0x1) << PMC_FSPR_FSTP7_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 7 Mask */ +#define PMC_FSPR_FSTP7(value) (PMC_FSPR_FSTP7_Msk & ((value) << PMC_FSPR_FSTP7_Pos)) +#define PMC_FSPR_FSTP8_Pos _U_(8) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Position */ +#define PMC_FSPR_FSTP8_Msk (_U_(0x1) << PMC_FSPR_FSTP8_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 8 Mask */ +#define PMC_FSPR_FSTP8(value) (PMC_FSPR_FSTP8_Msk & ((value) << PMC_FSPR_FSTP8_Pos)) +#define PMC_FSPR_FSTP9_Pos _U_(9) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Position */ +#define PMC_FSPR_FSTP9_Msk (_U_(0x1) << PMC_FSPR_FSTP9_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 9 Mask */ +#define PMC_FSPR_FSTP9(value) (PMC_FSPR_FSTP9_Msk & ((value) << PMC_FSPR_FSTP9_Pos)) +#define PMC_FSPR_FSTP10_Pos _U_(10) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Position */ +#define PMC_FSPR_FSTP10_Msk (_U_(0x1) << PMC_FSPR_FSTP10_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 10 Mask */ +#define PMC_FSPR_FSTP10(value) (PMC_FSPR_FSTP10_Msk & ((value) << PMC_FSPR_FSTP10_Pos)) +#define PMC_FSPR_FSTP11_Pos _U_(11) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Position */ +#define PMC_FSPR_FSTP11_Msk (_U_(0x1) << PMC_FSPR_FSTP11_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 11 Mask */ +#define PMC_FSPR_FSTP11(value) (PMC_FSPR_FSTP11_Msk & ((value) << PMC_FSPR_FSTP11_Pos)) +#define PMC_FSPR_FSTP12_Pos _U_(12) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Position */ +#define PMC_FSPR_FSTP12_Msk (_U_(0x1) << PMC_FSPR_FSTP12_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 12 Mask */ +#define PMC_FSPR_FSTP12(value) (PMC_FSPR_FSTP12_Msk & ((value) << PMC_FSPR_FSTP12_Pos)) +#define PMC_FSPR_FSTP13_Pos _U_(13) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Position */ +#define PMC_FSPR_FSTP13_Msk (_U_(0x1) << PMC_FSPR_FSTP13_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 13 Mask */ +#define PMC_FSPR_FSTP13(value) (PMC_FSPR_FSTP13_Msk & ((value) << PMC_FSPR_FSTP13_Pos)) +#define PMC_FSPR_FSTP14_Pos _U_(14) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Position */ +#define PMC_FSPR_FSTP14_Msk (_U_(0x1) << PMC_FSPR_FSTP14_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 14 Mask */ +#define PMC_FSPR_FSTP14(value) (PMC_FSPR_FSTP14_Msk & ((value) << PMC_FSPR_FSTP14_Pos)) +#define PMC_FSPR_FSTP15_Pos _U_(15) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Position */ +#define PMC_FSPR_FSTP15_Msk (_U_(0x1) << PMC_FSPR_FSTP15_Pos) /**< (PMC_FSPR) Fast Startup Input Polarity 15 Mask */ +#define PMC_FSPR_FSTP15(value) (PMC_FSPR_FSTP15_Msk & ((value) << PMC_FSPR_FSTP15_Pos)) +#define PMC_FSPR_Msk _U_(0x0000FFFF) /**< (PMC_FSPR) Register Mask */ + +#define PMC_FSPR_FSTP_Pos _U_(0) /**< (PMC_FSPR Position) Fast Startup Input Polarity x5 */ +#define PMC_FSPR_FSTP_Msk (_U_(0xFFFF) << PMC_FSPR_FSTP_Pos) /**< (PMC_FSPR Mask) FSTP */ +#define PMC_FSPR_FSTP(value) (PMC_FSPR_FSTP_Msk & ((value) << PMC_FSPR_FSTP_Pos)) + +/* -------- PMC_FOCR : (PMC Offset: 0x78) ( /W 32) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR_Pos _U_(0) /**< (PMC_FOCR) Fault Output Clear Position */ +#define PMC_FOCR_FOCLR_Msk (_U_(0x1) << PMC_FOCR_FOCLR_Pos) /**< (PMC_FOCR) Fault Output Clear Mask */ +#define PMC_FOCR_FOCLR(value) (PMC_FOCR_FOCLR_Msk & ((value) << PMC_FOCR_FOCLR_Pos)) +#define PMC_FOCR_Msk _U_(0x00000001) /**< (PMC_FOCR) Register Mask */ + + +/* -------- PMC_WPMR : (PMC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN_Pos _U_(0) /**< (PMC_WPMR) Write Protection Enable Position */ +#define PMC_WPMR_WPEN_Msk (_U_(0x1) << PMC_WPMR_WPEN_Pos) /**< (PMC_WPMR) Write Protection Enable Mask */ +#define PMC_WPMR_WPEN(value) (PMC_WPMR_WPEN_Msk & ((value) << PMC_WPMR_WPEN_Pos)) +#define PMC_WPMR_WPKEY_Pos _U_(8) /**< (PMC_WPMR) Write Protection Key Position */ +#define PMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Write Protection Key Mask */ +#define PMC_WPMR_WPKEY(value) (PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)) +#define PMC_WPMR_WPKEY_PASSWD_Val _U_(0x504D43) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define PMC_WPMR_WPKEY_PASSWD (PMC_WPMR_WPKEY_PASSWD_Val << PMC_WPMR_WPKEY_Pos) /**< (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define PMC_WPMR_Msk _U_(0xFFFFFF01) /**< (PMC_WPMR) Register Mask */ + + +/* -------- PMC_WPSR : (PMC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS_Pos _U_(0) /**< (PMC_WPSR) Write Protection Violation Status Position */ +#define PMC_WPSR_WPVS_Msk (_U_(0x1) << PMC_WPSR_WPVS_Pos) /**< (PMC_WPSR) Write Protection Violation Status Mask */ +#define PMC_WPSR_WPVS(value) (PMC_WPSR_WPVS_Msk & ((value) << PMC_WPSR_WPVS_Pos)) +#define PMC_WPSR_WPVSRC_Pos _U_(8) /**< (PMC_WPSR) Write Protection Violation Source Position */ +#define PMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PMC_WPSR_WPVSRC_Pos) /**< (PMC_WPSR) Write Protection Violation Source Mask */ +#define PMC_WPSR_WPVSRC(value) (PMC_WPSR_WPVSRC_Msk & ((value) << PMC_WPSR_WPVSRC_Pos)) +#define PMC_WPSR_Msk _U_(0x00FFFF01) /**< (PMC_WPSR) Register Mask */ + + +/* -------- PMC_PCER1 : (PMC Offset: 0x100) ( /W 32) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32_Pos _U_(0) /**< (PMC_PCER1) Peripheral Clock 32 Enable Position */ +#define PMC_PCER1_PID32_Msk (_U_(0x1) << PMC_PCER1_PID32_Pos) /**< (PMC_PCER1) Peripheral Clock 32 Enable Mask */ +#define PMC_PCER1_PID32(value) (PMC_PCER1_PID32_Msk & ((value) << PMC_PCER1_PID32_Pos)) +#define PMC_PCER1_PID33_Pos _U_(1) /**< (PMC_PCER1) Peripheral Clock 33 Enable Position */ +#define PMC_PCER1_PID33_Msk (_U_(0x1) << PMC_PCER1_PID33_Pos) /**< (PMC_PCER1) Peripheral Clock 33 Enable Mask */ +#define PMC_PCER1_PID33(value) (PMC_PCER1_PID33_Msk & ((value) << PMC_PCER1_PID33_Pos)) +#define PMC_PCER1_PID34_Pos _U_(2) /**< (PMC_PCER1) Peripheral Clock 34 Enable Position */ +#define PMC_PCER1_PID34_Msk (_U_(0x1) << PMC_PCER1_PID34_Pos) /**< (PMC_PCER1) Peripheral Clock 34 Enable Mask */ +#define PMC_PCER1_PID34(value) (PMC_PCER1_PID34_Msk & ((value) << PMC_PCER1_PID34_Pos)) +#define PMC_PCER1_PID35_Pos _U_(3) /**< (PMC_PCER1) Peripheral Clock 35 Enable Position */ +#define PMC_PCER1_PID35_Msk (_U_(0x1) << PMC_PCER1_PID35_Pos) /**< (PMC_PCER1) Peripheral Clock 35 Enable Mask */ +#define PMC_PCER1_PID35(value) (PMC_PCER1_PID35_Msk & ((value) << PMC_PCER1_PID35_Pos)) +#define PMC_PCER1_PID37_Pos _U_(5) /**< (PMC_PCER1) Peripheral Clock 37 Enable Position */ +#define PMC_PCER1_PID37_Msk (_U_(0x1) << PMC_PCER1_PID37_Pos) /**< (PMC_PCER1) Peripheral Clock 37 Enable Mask */ +#define PMC_PCER1_PID37(value) (PMC_PCER1_PID37_Msk & ((value) << PMC_PCER1_PID37_Pos)) +#define PMC_PCER1_PID39_Pos _U_(7) /**< (PMC_PCER1) Peripheral Clock 39 Enable Position */ +#define PMC_PCER1_PID39_Msk (_U_(0x1) << PMC_PCER1_PID39_Pos) /**< (PMC_PCER1) Peripheral Clock 39 Enable Mask */ +#define PMC_PCER1_PID39(value) (PMC_PCER1_PID39_Msk & ((value) << PMC_PCER1_PID39_Pos)) +#define PMC_PCER1_PID40_Pos _U_(8) /**< (PMC_PCER1) Peripheral Clock 40 Enable Position */ +#define PMC_PCER1_PID40_Msk (_U_(0x1) << PMC_PCER1_PID40_Pos) /**< (PMC_PCER1) Peripheral Clock 40 Enable Mask */ +#define PMC_PCER1_PID40(value) (PMC_PCER1_PID40_Msk & ((value) << PMC_PCER1_PID40_Pos)) +#define PMC_PCER1_PID41_Pos _U_(9) /**< (PMC_PCER1) Peripheral Clock 41 Enable Position */ +#define PMC_PCER1_PID41_Msk (_U_(0x1) << PMC_PCER1_PID41_Pos) /**< (PMC_PCER1) Peripheral Clock 41 Enable Mask */ +#define PMC_PCER1_PID41(value) (PMC_PCER1_PID41_Msk & ((value) << PMC_PCER1_PID41_Pos)) +#define PMC_PCER1_PID42_Pos _U_(10) /**< (PMC_PCER1) Peripheral Clock 42 Enable Position */ +#define PMC_PCER1_PID42_Msk (_U_(0x1) << PMC_PCER1_PID42_Pos) /**< (PMC_PCER1) Peripheral Clock 42 Enable Mask */ +#define PMC_PCER1_PID42(value) (PMC_PCER1_PID42_Msk & ((value) << PMC_PCER1_PID42_Pos)) +#define PMC_PCER1_PID43_Pos _U_(11) /**< (PMC_PCER1) Peripheral Clock 43 Enable Position */ +#define PMC_PCER1_PID43_Msk (_U_(0x1) << PMC_PCER1_PID43_Pos) /**< (PMC_PCER1) Peripheral Clock 43 Enable Mask */ +#define PMC_PCER1_PID43(value) (PMC_PCER1_PID43_Msk & ((value) << PMC_PCER1_PID43_Pos)) +#define PMC_PCER1_PID44_Pos _U_(12) /**< (PMC_PCER1) Peripheral Clock 44 Enable Position */ +#define PMC_PCER1_PID44_Msk (_U_(0x1) << PMC_PCER1_PID44_Pos) /**< (PMC_PCER1) Peripheral Clock 44 Enable Mask */ +#define PMC_PCER1_PID44(value) (PMC_PCER1_PID44_Msk & ((value) << PMC_PCER1_PID44_Pos)) +#define PMC_PCER1_PID45_Pos _U_(13) /**< (PMC_PCER1) Peripheral Clock 45 Enable Position */ +#define PMC_PCER1_PID45_Msk (_U_(0x1) << PMC_PCER1_PID45_Pos) /**< (PMC_PCER1) Peripheral Clock 45 Enable Mask */ +#define PMC_PCER1_PID45(value) (PMC_PCER1_PID45_Msk & ((value) << PMC_PCER1_PID45_Pos)) +#define PMC_PCER1_PID46_Pos _U_(14) /**< (PMC_PCER1) Peripheral Clock 46 Enable Position */ +#define PMC_PCER1_PID46_Msk (_U_(0x1) << PMC_PCER1_PID46_Pos) /**< (PMC_PCER1) Peripheral Clock 46 Enable Mask */ +#define PMC_PCER1_PID46(value) (PMC_PCER1_PID46_Msk & ((value) << PMC_PCER1_PID46_Pos)) +#define PMC_PCER1_PID47_Pos _U_(15) /**< (PMC_PCER1) Peripheral Clock 47 Enable Position */ +#define PMC_PCER1_PID47_Msk (_U_(0x1) << PMC_PCER1_PID47_Pos) /**< (PMC_PCER1) Peripheral Clock 47 Enable Mask */ +#define PMC_PCER1_PID47(value) (PMC_PCER1_PID47_Msk & ((value) << PMC_PCER1_PID47_Pos)) +#define PMC_PCER1_PID48_Pos _U_(16) /**< (PMC_PCER1) Peripheral Clock 48 Enable Position */ +#define PMC_PCER1_PID48_Msk (_U_(0x1) << PMC_PCER1_PID48_Pos) /**< (PMC_PCER1) Peripheral Clock 48 Enable Mask */ +#define PMC_PCER1_PID48(value) (PMC_PCER1_PID48_Msk & ((value) << PMC_PCER1_PID48_Pos)) +#define PMC_PCER1_PID49_Pos _U_(17) /**< (PMC_PCER1) Peripheral Clock 49 Enable Position */ +#define PMC_PCER1_PID49_Msk (_U_(0x1) << PMC_PCER1_PID49_Pos) /**< (PMC_PCER1) Peripheral Clock 49 Enable Mask */ +#define PMC_PCER1_PID49(value) (PMC_PCER1_PID49_Msk & ((value) << PMC_PCER1_PID49_Pos)) +#define PMC_PCER1_PID50_Pos _U_(18) /**< (PMC_PCER1) Peripheral Clock 50 Enable Position */ +#define PMC_PCER1_PID50_Msk (_U_(0x1) << PMC_PCER1_PID50_Pos) /**< (PMC_PCER1) Peripheral Clock 50 Enable Mask */ +#define PMC_PCER1_PID50(value) (PMC_PCER1_PID50_Msk & ((value) << PMC_PCER1_PID50_Pos)) +#define PMC_PCER1_PID51_Pos _U_(19) /**< (PMC_PCER1) Peripheral Clock 51 Enable Position */ +#define PMC_PCER1_PID51_Msk (_U_(0x1) << PMC_PCER1_PID51_Pos) /**< (PMC_PCER1) Peripheral Clock 51 Enable Mask */ +#define PMC_PCER1_PID51(value) (PMC_PCER1_PID51_Msk & ((value) << PMC_PCER1_PID51_Pos)) +#define PMC_PCER1_PID52_Pos _U_(20) /**< (PMC_PCER1) Peripheral Clock 52 Enable Position */ +#define PMC_PCER1_PID52_Msk (_U_(0x1) << PMC_PCER1_PID52_Pos) /**< (PMC_PCER1) Peripheral Clock 52 Enable Mask */ +#define PMC_PCER1_PID52(value) (PMC_PCER1_PID52_Msk & ((value) << PMC_PCER1_PID52_Pos)) +#define PMC_PCER1_PID56_Pos _U_(24) /**< (PMC_PCER1) Peripheral Clock 56 Enable Position */ +#define PMC_PCER1_PID56_Msk (_U_(0x1) << PMC_PCER1_PID56_Pos) /**< (PMC_PCER1) Peripheral Clock 56 Enable Mask */ +#define PMC_PCER1_PID56(value) (PMC_PCER1_PID56_Msk & ((value) << PMC_PCER1_PID56_Pos)) +#define PMC_PCER1_PID57_Pos _U_(25) /**< (PMC_PCER1) Peripheral Clock 57 Enable Position */ +#define PMC_PCER1_PID57_Msk (_U_(0x1) << PMC_PCER1_PID57_Pos) /**< (PMC_PCER1) Peripheral Clock 57 Enable Mask */ +#define PMC_PCER1_PID57(value) (PMC_PCER1_PID57_Msk & ((value) << PMC_PCER1_PID57_Pos)) +#define PMC_PCER1_PID58_Pos _U_(26) /**< (PMC_PCER1) Peripheral Clock 58 Enable Position */ +#define PMC_PCER1_PID58_Msk (_U_(0x1) << PMC_PCER1_PID58_Pos) /**< (PMC_PCER1) Peripheral Clock 58 Enable Mask */ +#define PMC_PCER1_PID58(value) (PMC_PCER1_PID58_Msk & ((value) << PMC_PCER1_PID58_Pos)) +#define PMC_PCER1_PID59_Pos _U_(27) /**< (PMC_PCER1) Peripheral Clock 59 Enable Position */ +#define PMC_PCER1_PID59_Msk (_U_(0x1) << PMC_PCER1_PID59_Pos) /**< (PMC_PCER1) Peripheral Clock 59 Enable Mask */ +#define PMC_PCER1_PID59(value) (PMC_PCER1_PID59_Msk & ((value) << PMC_PCER1_PID59_Pos)) +#define PMC_PCER1_PID60_Pos _U_(28) /**< (PMC_PCER1) Peripheral Clock 60 Enable Position */ +#define PMC_PCER1_PID60_Msk (_U_(0x1) << PMC_PCER1_PID60_Pos) /**< (PMC_PCER1) Peripheral Clock 60 Enable Mask */ +#define PMC_PCER1_PID60(value) (PMC_PCER1_PID60_Msk & ((value) << PMC_PCER1_PID60_Pos)) +#define PMC_PCER1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCER1) Register Mask */ + +#define PMC_PCER1_PID_Pos _U_(0) /**< (PMC_PCER1 Position) Peripheral Clock 6x Enable */ +#define PMC_PCER1_PID_Msk (_U_(0xFFFFFF) << PMC_PCER1_PID_Pos) /**< (PMC_PCER1 Mask) PID */ +#define PMC_PCER1_PID(value) (PMC_PCER1_PID_Msk & ((value) << PMC_PCER1_PID_Pos)) + +/* -------- PMC_PCDR1 : (PMC Offset: 0x104) ( /W 32) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32_Pos _U_(0) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Position */ +#define PMC_PCDR1_PID32_Msk (_U_(0x1) << PMC_PCDR1_PID32_Pos) /**< (PMC_PCDR1) Peripheral Clock 32 Disable Mask */ +#define PMC_PCDR1_PID32(value) (PMC_PCDR1_PID32_Msk & ((value) << PMC_PCDR1_PID32_Pos)) +#define PMC_PCDR1_PID33_Pos _U_(1) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Position */ +#define PMC_PCDR1_PID33_Msk (_U_(0x1) << PMC_PCDR1_PID33_Pos) /**< (PMC_PCDR1) Peripheral Clock 33 Disable Mask */ +#define PMC_PCDR1_PID33(value) (PMC_PCDR1_PID33_Msk & ((value) << PMC_PCDR1_PID33_Pos)) +#define PMC_PCDR1_PID34_Pos _U_(2) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Position */ +#define PMC_PCDR1_PID34_Msk (_U_(0x1) << PMC_PCDR1_PID34_Pos) /**< (PMC_PCDR1) Peripheral Clock 34 Disable Mask */ +#define PMC_PCDR1_PID34(value) (PMC_PCDR1_PID34_Msk & ((value) << PMC_PCDR1_PID34_Pos)) +#define PMC_PCDR1_PID35_Pos _U_(3) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Position */ +#define PMC_PCDR1_PID35_Msk (_U_(0x1) << PMC_PCDR1_PID35_Pos) /**< (PMC_PCDR1) Peripheral Clock 35 Disable Mask */ +#define PMC_PCDR1_PID35(value) (PMC_PCDR1_PID35_Msk & ((value) << PMC_PCDR1_PID35_Pos)) +#define PMC_PCDR1_PID37_Pos _U_(5) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Position */ +#define PMC_PCDR1_PID37_Msk (_U_(0x1) << PMC_PCDR1_PID37_Pos) /**< (PMC_PCDR1) Peripheral Clock 37 Disable Mask */ +#define PMC_PCDR1_PID37(value) (PMC_PCDR1_PID37_Msk & ((value) << PMC_PCDR1_PID37_Pos)) +#define PMC_PCDR1_PID39_Pos _U_(7) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Position */ +#define PMC_PCDR1_PID39_Msk (_U_(0x1) << PMC_PCDR1_PID39_Pos) /**< (PMC_PCDR1) Peripheral Clock 39 Disable Mask */ +#define PMC_PCDR1_PID39(value) (PMC_PCDR1_PID39_Msk & ((value) << PMC_PCDR1_PID39_Pos)) +#define PMC_PCDR1_PID40_Pos _U_(8) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Position */ +#define PMC_PCDR1_PID40_Msk (_U_(0x1) << PMC_PCDR1_PID40_Pos) /**< (PMC_PCDR1) Peripheral Clock 40 Disable Mask */ +#define PMC_PCDR1_PID40(value) (PMC_PCDR1_PID40_Msk & ((value) << PMC_PCDR1_PID40_Pos)) +#define PMC_PCDR1_PID41_Pos _U_(9) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Position */ +#define PMC_PCDR1_PID41_Msk (_U_(0x1) << PMC_PCDR1_PID41_Pos) /**< (PMC_PCDR1) Peripheral Clock 41 Disable Mask */ +#define PMC_PCDR1_PID41(value) (PMC_PCDR1_PID41_Msk & ((value) << PMC_PCDR1_PID41_Pos)) +#define PMC_PCDR1_PID42_Pos _U_(10) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Position */ +#define PMC_PCDR1_PID42_Msk (_U_(0x1) << PMC_PCDR1_PID42_Pos) /**< (PMC_PCDR1) Peripheral Clock 42 Disable Mask */ +#define PMC_PCDR1_PID42(value) (PMC_PCDR1_PID42_Msk & ((value) << PMC_PCDR1_PID42_Pos)) +#define PMC_PCDR1_PID43_Pos _U_(11) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Position */ +#define PMC_PCDR1_PID43_Msk (_U_(0x1) << PMC_PCDR1_PID43_Pos) /**< (PMC_PCDR1) Peripheral Clock 43 Disable Mask */ +#define PMC_PCDR1_PID43(value) (PMC_PCDR1_PID43_Msk & ((value) << PMC_PCDR1_PID43_Pos)) +#define PMC_PCDR1_PID44_Pos _U_(12) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Position */ +#define PMC_PCDR1_PID44_Msk (_U_(0x1) << PMC_PCDR1_PID44_Pos) /**< (PMC_PCDR1) Peripheral Clock 44 Disable Mask */ +#define PMC_PCDR1_PID44(value) (PMC_PCDR1_PID44_Msk & ((value) << PMC_PCDR1_PID44_Pos)) +#define PMC_PCDR1_PID45_Pos _U_(13) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Position */ +#define PMC_PCDR1_PID45_Msk (_U_(0x1) << PMC_PCDR1_PID45_Pos) /**< (PMC_PCDR1) Peripheral Clock 45 Disable Mask */ +#define PMC_PCDR1_PID45(value) (PMC_PCDR1_PID45_Msk & ((value) << PMC_PCDR1_PID45_Pos)) +#define PMC_PCDR1_PID46_Pos _U_(14) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Position */ +#define PMC_PCDR1_PID46_Msk (_U_(0x1) << PMC_PCDR1_PID46_Pos) /**< (PMC_PCDR1) Peripheral Clock 46 Disable Mask */ +#define PMC_PCDR1_PID46(value) (PMC_PCDR1_PID46_Msk & ((value) << PMC_PCDR1_PID46_Pos)) +#define PMC_PCDR1_PID47_Pos _U_(15) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Position */ +#define PMC_PCDR1_PID47_Msk (_U_(0x1) << PMC_PCDR1_PID47_Pos) /**< (PMC_PCDR1) Peripheral Clock 47 Disable Mask */ +#define PMC_PCDR1_PID47(value) (PMC_PCDR1_PID47_Msk & ((value) << PMC_PCDR1_PID47_Pos)) +#define PMC_PCDR1_PID48_Pos _U_(16) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Position */ +#define PMC_PCDR1_PID48_Msk (_U_(0x1) << PMC_PCDR1_PID48_Pos) /**< (PMC_PCDR1) Peripheral Clock 48 Disable Mask */ +#define PMC_PCDR1_PID48(value) (PMC_PCDR1_PID48_Msk & ((value) << PMC_PCDR1_PID48_Pos)) +#define PMC_PCDR1_PID49_Pos _U_(17) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Position */ +#define PMC_PCDR1_PID49_Msk (_U_(0x1) << PMC_PCDR1_PID49_Pos) /**< (PMC_PCDR1) Peripheral Clock 49 Disable Mask */ +#define PMC_PCDR1_PID49(value) (PMC_PCDR1_PID49_Msk & ((value) << PMC_PCDR1_PID49_Pos)) +#define PMC_PCDR1_PID50_Pos _U_(18) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Position */ +#define PMC_PCDR1_PID50_Msk (_U_(0x1) << PMC_PCDR1_PID50_Pos) /**< (PMC_PCDR1) Peripheral Clock 50 Disable Mask */ +#define PMC_PCDR1_PID50(value) (PMC_PCDR1_PID50_Msk & ((value) << PMC_PCDR1_PID50_Pos)) +#define PMC_PCDR1_PID51_Pos _U_(19) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Position */ +#define PMC_PCDR1_PID51_Msk (_U_(0x1) << PMC_PCDR1_PID51_Pos) /**< (PMC_PCDR1) Peripheral Clock 51 Disable Mask */ +#define PMC_PCDR1_PID51(value) (PMC_PCDR1_PID51_Msk & ((value) << PMC_PCDR1_PID51_Pos)) +#define PMC_PCDR1_PID52_Pos _U_(20) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Position */ +#define PMC_PCDR1_PID52_Msk (_U_(0x1) << PMC_PCDR1_PID52_Pos) /**< (PMC_PCDR1) Peripheral Clock 52 Disable Mask */ +#define PMC_PCDR1_PID52(value) (PMC_PCDR1_PID52_Msk & ((value) << PMC_PCDR1_PID52_Pos)) +#define PMC_PCDR1_PID56_Pos _U_(24) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Position */ +#define PMC_PCDR1_PID56_Msk (_U_(0x1) << PMC_PCDR1_PID56_Pos) /**< (PMC_PCDR1) Peripheral Clock 56 Disable Mask */ +#define PMC_PCDR1_PID56(value) (PMC_PCDR1_PID56_Msk & ((value) << PMC_PCDR1_PID56_Pos)) +#define PMC_PCDR1_PID57_Pos _U_(25) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Position */ +#define PMC_PCDR1_PID57_Msk (_U_(0x1) << PMC_PCDR1_PID57_Pos) /**< (PMC_PCDR1) Peripheral Clock 57 Disable Mask */ +#define PMC_PCDR1_PID57(value) (PMC_PCDR1_PID57_Msk & ((value) << PMC_PCDR1_PID57_Pos)) +#define PMC_PCDR1_PID58_Pos _U_(26) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Position */ +#define PMC_PCDR1_PID58_Msk (_U_(0x1) << PMC_PCDR1_PID58_Pos) /**< (PMC_PCDR1) Peripheral Clock 58 Disable Mask */ +#define PMC_PCDR1_PID58(value) (PMC_PCDR1_PID58_Msk & ((value) << PMC_PCDR1_PID58_Pos)) +#define PMC_PCDR1_PID59_Pos _U_(27) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Position */ +#define PMC_PCDR1_PID59_Msk (_U_(0x1) << PMC_PCDR1_PID59_Pos) /**< (PMC_PCDR1) Peripheral Clock 59 Disable Mask */ +#define PMC_PCDR1_PID59(value) (PMC_PCDR1_PID59_Msk & ((value) << PMC_PCDR1_PID59_Pos)) +#define PMC_PCDR1_PID60_Pos _U_(28) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Position */ +#define PMC_PCDR1_PID60_Msk (_U_(0x1) << PMC_PCDR1_PID60_Pos) /**< (PMC_PCDR1) Peripheral Clock 60 Disable Mask */ +#define PMC_PCDR1_PID60(value) (PMC_PCDR1_PID60_Msk & ((value) << PMC_PCDR1_PID60_Pos)) +#define PMC_PCDR1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCDR1) Register Mask */ + +#define PMC_PCDR1_PID_Pos _U_(0) /**< (PMC_PCDR1 Position) Peripheral Clock 6x Disable */ +#define PMC_PCDR1_PID_Msk (_U_(0xFFFFFF) << PMC_PCDR1_PID_Pos) /**< (PMC_PCDR1 Mask) PID */ +#define PMC_PCDR1_PID(value) (PMC_PCDR1_PID_Msk & ((value) << PMC_PCDR1_PID_Pos)) + +/* -------- PMC_PCSR1 : (PMC Offset: 0x108) ( R/ 32) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32_Pos _U_(0) /**< (PMC_PCSR1) Peripheral Clock 32 Status Position */ +#define PMC_PCSR1_PID32_Msk (_U_(0x1) << PMC_PCSR1_PID32_Pos) /**< (PMC_PCSR1) Peripheral Clock 32 Status Mask */ +#define PMC_PCSR1_PID32(value) (PMC_PCSR1_PID32_Msk & ((value) << PMC_PCSR1_PID32_Pos)) +#define PMC_PCSR1_PID33_Pos _U_(1) /**< (PMC_PCSR1) Peripheral Clock 33 Status Position */ +#define PMC_PCSR1_PID33_Msk (_U_(0x1) << PMC_PCSR1_PID33_Pos) /**< (PMC_PCSR1) Peripheral Clock 33 Status Mask */ +#define PMC_PCSR1_PID33(value) (PMC_PCSR1_PID33_Msk & ((value) << PMC_PCSR1_PID33_Pos)) +#define PMC_PCSR1_PID34_Pos _U_(2) /**< (PMC_PCSR1) Peripheral Clock 34 Status Position */ +#define PMC_PCSR1_PID34_Msk (_U_(0x1) << PMC_PCSR1_PID34_Pos) /**< (PMC_PCSR1) Peripheral Clock 34 Status Mask */ +#define PMC_PCSR1_PID34(value) (PMC_PCSR1_PID34_Msk & ((value) << PMC_PCSR1_PID34_Pos)) +#define PMC_PCSR1_PID35_Pos _U_(3) /**< (PMC_PCSR1) Peripheral Clock 35 Status Position */ +#define PMC_PCSR1_PID35_Msk (_U_(0x1) << PMC_PCSR1_PID35_Pos) /**< (PMC_PCSR1) Peripheral Clock 35 Status Mask */ +#define PMC_PCSR1_PID35(value) (PMC_PCSR1_PID35_Msk & ((value) << PMC_PCSR1_PID35_Pos)) +#define PMC_PCSR1_PID37_Pos _U_(5) /**< (PMC_PCSR1) Peripheral Clock 37 Status Position */ +#define PMC_PCSR1_PID37_Msk (_U_(0x1) << PMC_PCSR1_PID37_Pos) /**< (PMC_PCSR1) Peripheral Clock 37 Status Mask */ +#define PMC_PCSR1_PID37(value) (PMC_PCSR1_PID37_Msk & ((value) << PMC_PCSR1_PID37_Pos)) +#define PMC_PCSR1_PID39_Pos _U_(7) /**< (PMC_PCSR1) Peripheral Clock 39 Status Position */ +#define PMC_PCSR1_PID39_Msk (_U_(0x1) << PMC_PCSR1_PID39_Pos) /**< (PMC_PCSR1) Peripheral Clock 39 Status Mask */ +#define PMC_PCSR1_PID39(value) (PMC_PCSR1_PID39_Msk & ((value) << PMC_PCSR1_PID39_Pos)) +#define PMC_PCSR1_PID40_Pos _U_(8) /**< (PMC_PCSR1) Peripheral Clock 40 Status Position */ +#define PMC_PCSR1_PID40_Msk (_U_(0x1) << PMC_PCSR1_PID40_Pos) /**< (PMC_PCSR1) Peripheral Clock 40 Status Mask */ +#define PMC_PCSR1_PID40(value) (PMC_PCSR1_PID40_Msk & ((value) << PMC_PCSR1_PID40_Pos)) +#define PMC_PCSR1_PID41_Pos _U_(9) /**< (PMC_PCSR1) Peripheral Clock 41 Status Position */ +#define PMC_PCSR1_PID41_Msk (_U_(0x1) << PMC_PCSR1_PID41_Pos) /**< (PMC_PCSR1) Peripheral Clock 41 Status Mask */ +#define PMC_PCSR1_PID41(value) (PMC_PCSR1_PID41_Msk & ((value) << PMC_PCSR1_PID41_Pos)) +#define PMC_PCSR1_PID42_Pos _U_(10) /**< (PMC_PCSR1) Peripheral Clock 42 Status Position */ +#define PMC_PCSR1_PID42_Msk (_U_(0x1) << PMC_PCSR1_PID42_Pos) /**< (PMC_PCSR1) Peripheral Clock 42 Status Mask */ +#define PMC_PCSR1_PID42(value) (PMC_PCSR1_PID42_Msk & ((value) << PMC_PCSR1_PID42_Pos)) +#define PMC_PCSR1_PID43_Pos _U_(11) /**< (PMC_PCSR1) Peripheral Clock 43 Status Position */ +#define PMC_PCSR1_PID43_Msk (_U_(0x1) << PMC_PCSR1_PID43_Pos) /**< (PMC_PCSR1) Peripheral Clock 43 Status Mask */ +#define PMC_PCSR1_PID43(value) (PMC_PCSR1_PID43_Msk & ((value) << PMC_PCSR1_PID43_Pos)) +#define PMC_PCSR1_PID44_Pos _U_(12) /**< (PMC_PCSR1) Peripheral Clock 44 Status Position */ +#define PMC_PCSR1_PID44_Msk (_U_(0x1) << PMC_PCSR1_PID44_Pos) /**< (PMC_PCSR1) Peripheral Clock 44 Status Mask */ +#define PMC_PCSR1_PID44(value) (PMC_PCSR1_PID44_Msk & ((value) << PMC_PCSR1_PID44_Pos)) +#define PMC_PCSR1_PID45_Pos _U_(13) /**< (PMC_PCSR1) Peripheral Clock 45 Status Position */ +#define PMC_PCSR1_PID45_Msk (_U_(0x1) << PMC_PCSR1_PID45_Pos) /**< (PMC_PCSR1) Peripheral Clock 45 Status Mask */ +#define PMC_PCSR1_PID45(value) (PMC_PCSR1_PID45_Msk & ((value) << PMC_PCSR1_PID45_Pos)) +#define PMC_PCSR1_PID46_Pos _U_(14) /**< (PMC_PCSR1) Peripheral Clock 46 Status Position */ +#define PMC_PCSR1_PID46_Msk (_U_(0x1) << PMC_PCSR1_PID46_Pos) /**< (PMC_PCSR1) Peripheral Clock 46 Status Mask */ +#define PMC_PCSR1_PID46(value) (PMC_PCSR1_PID46_Msk & ((value) << PMC_PCSR1_PID46_Pos)) +#define PMC_PCSR1_PID47_Pos _U_(15) /**< (PMC_PCSR1) Peripheral Clock 47 Status Position */ +#define PMC_PCSR1_PID47_Msk (_U_(0x1) << PMC_PCSR1_PID47_Pos) /**< (PMC_PCSR1) Peripheral Clock 47 Status Mask */ +#define PMC_PCSR1_PID47(value) (PMC_PCSR1_PID47_Msk & ((value) << PMC_PCSR1_PID47_Pos)) +#define PMC_PCSR1_PID48_Pos _U_(16) /**< (PMC_PCSR1) Peripheral Clock 48 Status Position */ +#define PMC_PCSR1_PID48_Msk (_U_(0x1) << PMC_PCSR1_PID48_Pos) /**< (PMC_PCSR1) Peripheral Clock 48 Status Mask */ +#define PMC_PCSR1_PID48(value) (PMC_PCSR1_PID48_Msk & ((value) << PMC_PCSR1_PID48_Pos)) +#define PMC_PCSR1_PID49_Pos _U_(17) /**< (PMC_PCSR1) Peripheral Clock 49 Status Position */ +#define PMC_PCSR1_PID49_Msk (_U_(0x1) << PMC_PCSR1_PID49_Pos) /**< (PMC_PCSR1) Peripheral Clock 49 Status Mask */ +#define PMC_PCSR1_PID49(value) (PMC_PCSR1_PID49_Msk & ((value) << PMC_PCSR1_PID49_Pos)) +#define PMC_PCSR1_PID50_Pos _U_(18) /**< (PMC_PCSR1) Peripheral Clock 50 Status Position */ +#define PMC_PCSR1_PID50_Msk (_U_(0x1) << PMC_PCSR1_PID50_Pos) /**< (PMC_PCSR1) Peripheral Clock 50 Status Mask */ +#define PMC_PCSR1_PID50(value) (PMC_PCSR1_PID50_Msk & ((value) << PMC_PCSR1_PID50_Pos)) +#define PMC_PCSR1_PID51_Pos _U_(19) /**< (PMC_PCSR1) Peripheral Clock 51 Status Position */ +#define PMC_PCSR1_PID51_Msk (_U_(0x1) << PMC_PCSR1_PID51_Pos) /**< (PMC_PCSR1) Peripheral Clock 51 Status Mask */ +#define PMC_PCSR1_PID51(value) (PMC_PCSR1_PID51_Msk & ((value) << PMC_PCSR1_PID51_Pos)) +#define PMC_PCSR1_PID52_Pos _U_(20) /**< (PMC_PCSR1) Peripheral Clock 52 Status Position */ +#define PMC_PCSR1_PID52_Msk (_U_(0x1) << PMC_PCSR1_PID52_Pos) /**< (PMC_PCSR1) Peripheral Clock 52 Status Mask */ +#define PMC_PCSR1_PID52(value) (PMC_PCSR1_PID52_Msk & ((value) << PMC_PCSR1_PID52_Pos)) +#define PMC_PCSR1_PID56_Pos _U_(24) /**< (PMC_PCSR1) Peripheral Clock 56 Status Position */ +#define PMC_PCSR1_PID56_Msk (_U_(0x1) << PMC_PCSR1_PID56_Pos) /**< (PMC_PCSR1) Peripheral Clock 56 Status Mask */ +#define PMC_PCSR1_PID56(value) (PMC_PCSR1_PID56_Msk & ((value) << PMC_PCSR1_PID56_Pos)) +#define PMC_PCSR1_PID57_Pos _U_(25) /**< (PMC_PCSR1) Peripheral Clock 57 Status Position */ +#define PMC_PCSR1_PID57_Msk (_U_(0x1) << PMC_PCSR1_PID57_Pos) /**< (PMC_PCSR1) Peripheral Clock 57 Status Mask */ +#define PMC_PCSR1_PID57(value) (PMC_PCSR1_PID57_Msk & ((value) << PMC_PCSR1_PID57_Pos)) +#define PMC_PCSR1_PID58_Pos _U_(26) /**< (PMC_PCSR1) Peripheral Clock 58 Status Position */ +#define PMC_PCSR1_PID58_Msk (_U_(0x1) << PMC_PCSR1_PID58_Pos) /**< (PMC_PCSR1) Peripheral Clock 58 Status Mask */ +#define PMC_PCSR1_PID58(value) (PMC_PCSR1_PID58_Msk & ((value) << PMC_PCSR1_PID58_Pos)) +#define PMC_PCSR1_PID59_Pos _U_(27) /**< (PMC_PCSR1) Peripheral Clock 59 Status Position */ +#define PMC_PCSR1_PID59_Msk (_U_(0x1) << PMC_PCSR1_PID59_Pos) /**< (PMC_PCSR1) Peripheral Clock 59 Status Mask */ +#define PMC_PCSR1_PID59(value) (PMC_PCSR1_PID59_Msk & ((value) << PMC_PCSR1_PID59_Pos)) +#define PMC_PCSR1_PID60_Pos _U_(28) /**< (PMC_PCSR1) Peripheral Clock 60 Status Position */ +#define PMC_PCSR1_PID60_Msk (_U_(0x1) << PMC_PCSR1_PID60_Pos) /**< (PMC_PCSR1) Peripheral Clock 60 Status Mask */ +#define PMC_PCSR1_PID60(value) (PMC_PCSR1_PID60_Msk & ((value) << PMC_PCSR1_PID60_Pos)) +#define PMC_PCSR1_Msk _U_(0x1F1FFFAF) /**< (PMC_PCSR1) Register Mask */ + +#define PMC_PCSR1_PID_Pos _U_(0) /**< (PMC_PCSR1 Position) Peripheral Clock 6x Status */ +#define PMC_PCSR1_PID_Msk (_U_(0xFFFFFF) << PMC_PCSR1_PID_Pos) /**< (PMC_PCSR1 Mask) PID */ +#define PMC_PCSR1_PID(value) (PMC_PCSR1_PID_Msk & ((value) << PMC_PCSR1_PID_Pos)) + +/* -------- PMC_PCR : (PMC Offset: 0x10C) (R/W 32) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos _U_(0) /**< (PMC_PCR) Peripheral ID Position */ +#define PMC_PCR_PID_Msk (_U_(0x7F) << PMC_PCR_PID_Pos) /**< (PMC_PCR) Peripheral ID Mask */ +#define PMC_PCR_PID(value) (PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)) +#define PMC_PCR_GCLKCSS_Pos _U_(8) /**< (PMC_PCR) Generic Clock Source Selection Position */ +#define PMC_PCR_GCLKCSS_Msk (_U_(0x7) << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Generic Clock Source Selection Mask */ +#define PMC_PCR_GCLKCSS(value) (PMC_PCR_GCLKCSS_Msk & ((value) << PMC_PCR_GCLKCSS_Pos)) +#define PMC_PCR_GCLKCSS_SLOW_CLK_Val _U_(0x0) /**< (PMC_PCR) Slow clock is selected */ +#define PMC_PCR_GCLKCSS_MAIN_CLK_Val _U_(0x1) /**< (PMC_PCR) Main clock is selected */ +#define PMC_PCR_GCLKCSS_PLLA_CLK_Val _U_(0x2) /**< (PMC_PCR) PLLACK is selected */ +#define PMC_PCR_GCLKCSS_UPLL_CLK_Val _U_(0x3) /**< (PMC_PCR) UPLL Clock is selected */ +#define PMC_PCR_GCLKCSS_MCK_CLK_Val _U_(0x4) /**< (PMC_PCR) Master Clock is selected */ +#define PMC_PCR_GCLKCSS_SLOW_CLK (PMC_PCR_GCLKCSS_SLOW_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Slow clock is selected Position */ +#define PMC_PCR_GCLKCSS_MAIN_CLK (PMC_PCR_GCLKCSS_MAIN_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Main clock is selected Position */ +#define PMC_PCR_GCLKCSS_PLLA_CLK (PMC_PCR_GCLKCSS_PLLA_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) PLLACK is selected Position */ +#define PMC_PCR_GCLKCSS_UPLL_CLK (PMC_PCR_GCLKCSS_UPLL_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) UPLL Clock is selected Position */ +#define PMC_PCR_GCLKCSS_MCK_CLK (PMC_PCR_GCLKCSS_MCK_CLK_Val << PMC_PCR_GCLKCSS_Pos) /**< (PMC_PCR) Master Clock is selected Position */ +#define PMC_PCR_CMD_Pos _U_(12) /**< (PMC_PCR) Command Position */ +#define PMC_PCR_CMD_Msk (_U_(0x1) << PMC_PCR_CMD_Pos) /**< (PMC_PCR) Command Mask */ +#define PMC_PCR_CMD(value) (PMC_PCR_CMD_Msk & ((value) << PMC_PCR_CMD_Pos)) +#define PMC_PCR_GCLKDIV_Pos _U_(20) /**< (PMC_PCR) Generic Clock Division Ratio Position */ +#define PMC_PCR_GCLKDIV_Msk (_U_(0xFF) << PMC_PCR_GCLKDIV_Pos) /**< (PMC_PCR) Generic Clock Division Ratio Mask */ +#define PMC_PCR_GCLKDIV(value) (PMC_PCR_GCLKDIV_Msk & ((value) << PMC_PCR_GCLKDIV_Pos)) +#define PMC_PCR_EN_Pos _U_(28) /**< (PMC_PCR) Enable Position */ +#define PMC_PCR_EN_Msk (_U_(0x1) << PMC_PCR_EN_Pos) /**< (PMC_PCR) Enable Mask */ +#define PMC_PCR_EN(value) (PMC_PCR_EN_Msk & ((value) << PMC_PCR_EN_Pos)) +#define PMC_PCR_GCLKEN_Pos _U_(29) /**< (PMC_PCR) Generic Clock Enable Position */ +#define PMC_PCR_GCLKEN_Msk (_U_(0x1) << PMC_PCR_GCLKEN_Pos) /**< (PMC_PCR) Generic Clock Enable Mask */ +#define PMC_PCR_GCLKEN(value) (PMC_PCR_GCLKEN_Msk & ((value) << PMC_PCR_GCLKEN_Pos)) +#define PMC_PCR_Msk _U_(0x3FF0177F) /**< (PMC_PCR) Register Mask */ + + +/* -------- PMC_OCR : (PMC Offset: 0x110) (R/W 32) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos _U_(0) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_CAL4_Msk (_U_(0x7F) << PMC_OCR_CAL4_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_CAL4(value) (PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)) +#define PMC_OCR_SEL4_Pos _U_(7) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Position */ +#define PMC_OCR_SEL4_Msk (_U_(0x1) << PMC_OCR_SEL4_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 4 MHz Mask */ +#define PMC_OCR_SEL4(value) (PMC_OCR_SEL4_Msk & ((value) << PMC_OCR_SEL4_Pos)) +#define PMC_OCR_CAL8_Pos _U_(8) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_CAL8_Msk (_U_(0x7F) << PMC_OCR_CAL8_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_CAL8(value) (PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)) +#define PMC_OCR_SEL8_Pos _U_(15) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Position */ +#define PMC_OCR_SEL8_Msk (_U_(0x1) << PMC_OCR_SEL8_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 8 MHz Mask */ +#define PMC_OCR_SEL8(value) (PMC_OCR_SEL8_Msk & ((value) << PMC_OCR_SEL8_Pos)) +#define PMC_OCR_CAL12_Pos _U_(16) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_CAL12_Msk (_U_(0x7F) << PMC_OCR_CAL12_Pos) /**< (PMC_OCR) Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_CAL12(value) (PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)) +#define PMC_OCR_SEL12_Pos _U_(23) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Position */ +#define PMC_OCR_SEL12_Msk (_U_(0x1) << PMC_OCR_SEL12_Pos) /**< (PMC_OCR) Selection of Main RC Oscillator Calibration Bits for 12 MHz Mask */ +#define PMC_OCR_SEL12(value) (PMC_OCR_SEL12_Msk & ((value) << PMC_OCR_SEL12_Pos)) +#define PMC_OCR_Msk _U_(0x00FFFFFF) /**< (PMC_OCR) Register Mask */ + + +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x114) ( /W 32) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7_Pos _U_(7) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID7_Pos) /**< (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID7(value) (PMC_SLPWK_ER0_PID7_Msk & ((value) << PMC_SLPWK_ER0_PID7_Pos)) +#define PMC_SLPWK_ER0_PID8_Pos _U_(8) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID8_Pos) /**< (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID8(value) (PMC_SLPWK_ER0_PID8_Msk & ((value) << PMC_SLPWK_ER0_PID8_Pos)) +#define PMC_SLPWK_ER0_PID9_Pos _U_(9) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID9_Pos) /**< (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID9(value) (PMC_SLPWK_ER0_PID9_Msk & ((value) << PMC_SLPWK_ER0_PID9_Pos)) +#define PMC_SLPWK_ER0_PID10_Pos _U_(10) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID10_Pos) /**< (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID10(value) (PMC_SLPWK_ER0_PID10_Msk & ((value) << PMC_SLPWK_ER0_PID10_Pos)) +#define PMC_SLPWK_ER0_PID11_Pos _U_(11) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID11_Pos) /**< (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID11(value) (PMC_SLPWK_ER0_PID11_Msk & ((value) << PMC_SLPWK_ER0_PID11_Pos)) +#define PMC_SLPWK_ER0_PID12_Pos _U_(12) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID12_Pos) /**< (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID12(value) (PMC_SLPWK_ER0_PID12_Msk & ((value) << PMC_SLPWK_ER0_PID12_Pos)) +#define PMC_SLPWK_ER0_PID13_Pos _U_(13) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID13_Pos) /**< (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID13(value) (PMC_SLPWK_ER0_PID13_Msk & ((value) << PMC_SLPWK_ER0_PID13_Pos)) +#define PMC_SLPWK_ER0_PID14_Pos _U_(14) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID14_Pos) /**< (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID14(value) (PMC_SLPWK_ER0_PID14_Msk & ((value) << PMC_SLPWK_ER0_PID14_Pos)) +#define PMC_SLPWK_ER0_PID15_Pos _U_(15) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID15_Pos) /**< (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID15(value) (PMC_SLPWK_ER0_PID15_Msk & ((value) << PMC_SLPWK_ER0_PID15_Pos)) +#define PMC_SLPWK_ER0_PID16_Pos _U_(16) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID16_Pos) /**< (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID16(value) (PMC_SLPWK_ER0_PID16_Msk & ((value) << PMC_SLPWK_ER0_PID16_Pos)) +#define PMC_SLPWK_ER0_PID17_Pos _U_(17) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID17_Pos) /**< (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID17(value) (PMC_SLPWK_ER0_PID17_Msk & ((value) << PMC_SLPWK_ER0_PID17_Pos)) +#define PMC_SLPWK_ER0_PID18_Pos _U_(18) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID18_Pos) /**< (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID18(value) (PMC_SLPWK_ER0_PID18_Msk & ((value) << PMC_SLPWK_ER0_PID18_Pos)) +#define PMC_SLPWK_ER0_PID19_Pos _U_(19) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID19_Pos) /**< (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID19(value) (PMC_SLPWK_ER0_PID19_Msk & ((value) << PMC_SLPWK_ER0_PID19_Pos)) +#define PMC_SLPWK_ER0_PID20_Pos _U_(20) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID20_Pos) /**< (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID20(value) (PMC_SLPWK_ER0_PID20_Msk & ((value) << PMC_SLPWK_ER0_PID20_Pos)) +#define PMC_SLPWK_ER0_PID21_Pos _U_(21) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID21_Pos) /**< (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID21(value) (PMC_SLPWK_ER0_PID21_Msk & ((value) << PMC_SLPWK_ER0_PID21_Pos)) +#define PMC_SLPWK_ER0_PID22_Pos _U_(22) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID22_Pos) /**< (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID22(value) (PMC_SLPWK_ER0_PID22_Msk & ((value) << PMC_SLPWK_ER0_PID22_Pos)) +#define PMC_SLPWK_ER0_PID23_Pos _U_(23) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID23_Pos) /**< (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID23(value) (PMC_SLPWK_ER0_PID23_Msk & ((value) << PMC_SLPWK_ER0_PID23_Pos)) +#define PMC_SLPWK_ER0_PID24_Pos _U_(24) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID24_Pos) /**< (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID24(value) (PMC_SLPWK_ER0_PID24_Msk & ((value) << PMC_SLPWK_ER0_PID24_Pos)) +#define PMC_SLPWK_ER0_PID25_Pos _U_(25) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID25_Pos) /**< (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID25(value) (PMC_SLPWK_ER0_PID25_Msk & ((value) << PMC_SLPWK_ER0_PID25_Pos)) +#define PMC_SLPWK_ER0_PID26_Pos _U_(26) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID26_Pos) /**< (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID26(value) (PMC_SLPWK_ER0_PID26_Msk & ((value) << PMC_SLPWK_ER0_PID26_Pos)) +#define PMC_SLPWK_ER0_PID27_Pos _U_(27) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID27_Pos) /**< (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID27(value) (PMC_SLPWK_ER0_PID27_Msk & ((value) << PMC_SLPWK_ER0_PID27_Pos)) +#define PMC_SLPWK_ER0_PID28_Pos _U_(28) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID28_Pos) /**< (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID28(value) (PMC_SLPWK_ER0_PID28_Msk & ((value) << PMC_SLPWK_ER0_PID28_Pos)) +#define PMC_SLPWK_ER0_PID29_Pos _U_(29) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID29_Pos) /**< (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID29(value) (PMC_SLPWK_ER0_PID29_Msk & ((value) << PMC_SLPWK_ER0_PID29_Pos)) +#define PMC_SLPWK_ER0_PID30_Pos _U_(30) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID30_Pos) /**< (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID30(value) (PMC_SLPWK_ER0_PID30_Msk & ((value) << PMC_SLPWK_ER0_PID30_Pos)) +#define PMC_SLPWK_ER0_PID31_Pos _U_(31) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Position */ +#define PMC_SLPWK_ER0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ER0_PID31_Pos) /**< (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER0_PID31(value) (PMC_SLPWK_ER0_PID31_Msk & ((value) << PMC_SLPWK_ER0_PID31_Pos)) +#define PMC_SLPWK_ER0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ER0) Register Mask */ + +#define PMC_SLPWK_ER0_PID_Pos _U_(7) /**< (PMC_SLPWK_ER0 Position) Peripheral 3x SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ER0_PID_Pos) /**< (PMC_SLPWK_ER0 Mask) PID */ +#define PMC_SLPWK_ER0_PID(value) (PMC_SLPWK_ER0_PID_Msk & ((value) << PMC_SLPWK_ER0_PID_Pos)) + +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x118) ( /W 32) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID7_Pos) /**< (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID7(value) (PMC_SLPWK_DR0_PID7_Msk & ((value) << PMC_SLPWK_DR0_PID7_Pos)) +#define PMC_SLPWK_DR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID8_Pos) /**< (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID8(value) (PMC_SLPWK_DR0_PID8_Msk & ((value) << PMC_SLPWK_DR0_PID8_Pos)) +#define PMC_SLPWK_DR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID9_Pos) /**< (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID9(value) (PMC_SLPWK_DR0_PID9_Msk & ((value) << PMC_SLPWK_DR0_PID9_Pos)) +#define PMC_SLPWK_DR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID10_Pos) /**< (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID10(value) (PMC_SLPWK_DR0_PID10_Msk & ((value) << PMC_SLPWK_DR0_PID10_Pos)) +#define PMC_SLPWK_DR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID11_Pos) /**< (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID11(value) (PMC_SLPWK_DR0_PID11_Msk & ((value) << PMC_SLPWK_DR0_PID11_Pos)) +#define PMC_SLPWK_DR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID12_Pos) /**< (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID12(value) (PMC_SLPWK_DR0_PID12_Msk & ((value) << PMC_SLPWK_DR0_PID12_Pos)) +#define PMC_SLPWK_DR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID13_Pos) /**< (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID13(value) (PMC_SLPWK_DR0_PID13_Msk & ((value) << PMC_SLPWK_DR0_PID13_Pos)) +#define PMC_SLPWK_DR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID14_Pos) /**< (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID14(value) (PMC_SLPWK_DR0_PID14_Msk & ((value) << PMC_SLPWK_DR0_PID14_Pos)) +#define PMC_SLPWK_DR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID15_Pos) /**< (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID15(value) (PMC_SLPWK_DR0_PID15_Msk & ((value) << PMC_SLPWK_DR0_PID15_Pos)) +#define PMC_SLPWK_DR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID16_Pos) /**< (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID16(value) (PMC_SLPWK_DR0_PID16_Msk & ((value) << PMC_SLPWK_DR0_PID16_Pos)) +#define PMC_SLPWK_DR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID17_Pos) /**< (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID17(value) (PMC_SLPWK_DR0_PID17_Msk & ((value) << PMC_SLPWK_DR0_PID17_Pos)) +#define PMC_SLPWK_DR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID18_Pos) /**< (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID18(value) (PMC_SLPWK_DR0_PID18_Msk & ((value) << PMC_SLPWK_DR0_PID18_Pos)) +#define PMC_SLPWK_DR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID19_Pos) /**< (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID19(value) (PMC_SLPWK_DR0_PID19_Msk & ((value) << PMC_SLPWK_DR0_PID19_Pos)) +#define PMC_SLPWK_DR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID20_Pos) /**< (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID20(value) (PMC_SLPWK_DR0_PID20_Msk & ((value) << PMC_SLPWK_DR0_PID20_Pos)) +#define PMC_SLPWK_DR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID21_Pos) /**< (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID21(value) (PMC_SLPWK_DR0_PID21_Msk & ((value) << PMC_SLPWK_DR0_PID21_Pos)) +#define PMC_SLPWK_DR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID22_Pos) /**< (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID22(value) (PMC_SLPWK_DR0_PID22_Msk & ((value) << PMC_SLPWK_DR0_PID22_Pos)) +#define PMC_SLPWK_DR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID23_Pos) /**< (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID23(value) (PMC_SLPWK_DR0_PID23_Msk & ((value) << PMC_SLPWK_DR0_PID23_Pos)) +#define PMC_SLPWK_DR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID24_Pos) /**< (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID24(value) (PMC_SLPWK_DR0_PID24_Msk & ((value) << PMC_SLPWK_DR0_PID24_Pos)) +#define PMC_SLPWK_DR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID25_Pos) /**< (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID25(value) (PMC_SLPWK_DR0_PID25_Msk & ((value) << PMC_SLPWK_DR0_PID25_Pos)) +#define PMC_SLPWK_DR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID26_Pos) /**< (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID26(value) (PMC_SLPWK_DR0_PID26_Msk & ((value) << PMC_SLPWK_DR0_PID26_Pos)) +#define PMC_SLPWK_DR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID27_Pos) /**< (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID27(value) (PMC_SLPWK_DR0_PID27_Msk & ((value) << PMC_SLPWK_DR0_PID27_Pos)) +#define PMC_SLPWK_DR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID28_Pos) /**< (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID28(value) (PMC_SLPWK_DR0_PID28_Msk & ((value) << PMC_SLPWK_DR0_PID28_Pos)) +#define PMC_SLPWK_DR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID29_Pos) /**< (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID29(value) (PMC_SLPWK_DR0_PID29_Msk & ((value) << PMC_SLPWK_DR0_PID29_Pos)) +#define PMC_SLPWK_DR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID30_Pos) /**< (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID30(value) (PMC_SLPWK_DR0_PID30_Msk & ((value) << PMC_SLPWK_DR0_PID30_Pos)) +#define PMC_SLPWK_DR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Position */ +#define PMC_SLPWK_DR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_DR0_PID31_Pos) /**< (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR0_PID31(value) (PMC_SLPWK_DR0_PID31_Msk & ((value) << PMC_SLPWK_DR0_PID31_Pos)) +#define PMC_SLPWK_DR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_DR0) Register Mask */ + +#define PMC_SLPWK_DR0_PID_Pos _U_(7) /**< (PMC_SLPWK_DR0 Position) Peripheral 3x SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_DR0_PID_Pos) /**< (PMC_SLPWK_DR0 Mask) PID */ +#define PMC_SLPWK_DR0_PID(value) (PMC_SLPWK_DR0_PID_Msk & ((value) << PMC_SLPWK_DR0_PID_Pos)) + +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x11C) ( R/ 32) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID7_Pos) /**< (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID7(value) (PMC_SLPWK_SR0_PID7_Msk & ((value) << PMC_SLPWK_SR0_PID7_Pos)) +#define PMC_SLPWK_SR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID8_Pos) /**< (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID8(value) (PMC_SLPWK_SR0_PID8_Msk & ((value) << PMC_SLPWK_SR0_PID8_Pos)) +#define PMC_SLPWK_SR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID9_Pos) /**< (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID9(value) (PMC_SLPWK_SR0_PID9_Msk & ((value) << PMC_SLPWK_SR0_PID9_Pos)) +#define PMC_SLPWK_SR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID10_Pos) /**< (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID10(value) (PMC_SLPWK_SR0_PID10_Msk & ((value) << PMC_SLPWK_SR0_PID10_Pos)) +#define PMC_SLPWK_SR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID11_Pos) /**< (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID11(value) (PMC_SLPWK_SR0_PID11_Msk & ((value) << PMC_SLPWK_SR0_PID11_Pos)) +#define PMC_SLPWK_SR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID12_Pos) /**< (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID12(value) (PMC_SLPWK_SR0_PID12_Msk & ((value) << PMC_SLPWK_SR0_PID12_Pos)) +#define PMC_SLPWK_SR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID13_Pos) /**< (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID13(value) (PMC_SLPWK_SR0_PID13_Msk & ((value) << PMC_SLPWK_SR0_PID13_Pos)) +#define PMC_SLPWK_SR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID14_Pos) /**< (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID14(value) (PMC_SLPWK_SR0_PID14_Msk & ((value) << PMC_SLPWK_SR0_PID14_Pos)) +#define PMC_SLPWK_SR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID15_Pos) /**< (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID15(value) (PMC_SLPWK_SR0_PID15_Msk & ((value) << PMC_SLPWK_SR0_PID15_Pos)) +#define PMC_SLPWK_SR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID16_Pos) /**< (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID16(value) (PMC_SLPWK_SR0_PID16_Msk & ((value) << PMC_SLPWK_SR0_PID16_Pos)) +#define PMC_SLPWK_SR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID17_Pos) /**< (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID17(value) (PMC_SLPWK_SR0_PID17_Msk & ((value) << PMC_SLPWK_SR0_PID17_Pos)) +#define PMC_SLPWK_SR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID18_Pos) /**< (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID18(value) (PMC_SLPWK_SR0_PID18_Msk & ((value) << PMC_SLPWK_SR0_PID18_Pos)) +#define PMC_SLPWK_SR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID19_Pos) /**< (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID19(value) (PMC_SLPWK_SR0_PID19_Msk & ((value) << PMC_SLPWK_SR0_PID19_Pos)) +#define PMC_SLPWK_SR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID20_Pos) /**< (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID20(value) (PMC_SLPWK_SR0_PID20_Msk & ((value) << PMC_SLPWK_SR0_PID20_Pos)) +#define PMC_SLPWK_SR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID21_Pos) /**< (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID21(value) (PMC_SLPWK_SR0_PID21_Msk & ((value) << PMC_SLPWK_SR0_PID21_Pos)) +#define PMC_SLPWK_SR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID22_Pos) /**< (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID22(value) (PMC_SLPWK_SR0_PID22_Msk & ((value) << PMC_SLPWK_SR0_PID22_Pos)) +#define PMC_SLPWK_SR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID23_Pos) /**< (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID23(value) (PMC_SLPWK_SR0_PID23_Msk & ((value) << PMC_SLPWK_SR0_PID23_Pos)) +#define PMC_SLPWK_SR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID24_Pos) /**< (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID24(value) (PMC_SLPWK_SR0_PID24_Msk & ((value) << PMC_SLPWK_SR0_PID24_Pos)) +#define PMC_SLPWK_SR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID25_Pos) /**< (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID25(value) (PMC_SLPWK_SR0_PID25_Msk & ((value) << PMC_SLPWK_SR0_PID25_Pos)) +#define PMC_SLPWK_SR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID26_Pos) /**< (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID26(value) (PMC_SLPWK_SR0_PID26_Msk & ((value) << PMC_SLPWK_SR0_PID26_Pos)) +#define PMC_SLPWK_SR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID27_Pos) /**< (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID27(value) (PMC_SLPWK_SR0_PID27_Msk & ((value) << PMC_SLPWK_SR0_PID27_Pos)) +#define PMC_SLPWK_SR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID28_Pos) /**< (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID28(value) (PMC_SLPWK_SR0_PID28_Msk & ((value) << PMC_SLPWK_SR0_PID28_Pos)) +#define PMC_SLPWK_SR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID29_Pos) /**< (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID29(value) (PMC_SLPWK_SR0_PID29_Msk & ((value) << PMC_SLPWK_SR0_PID29_Pos)) +#define PMC_SLPWK_SR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID30_Pos) /**< (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID30(value) (PMC_SLPWK_SR0_PID30_Msk & ((value) << PMC_SLPWK_SR0_PID30_Pos)) +#define PMC_SLPWK_SR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Position */ +#define PMC_SLPWK_SR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_SR0_PID31_Pos) /**< (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status Mask */ +#define PMC_SLPWK_SR0_PID31(value) (PMC_SLPWK_SR0_PID31_Msk & ((value) << PMC_SLPWK_SR0_PID31_Pos)) +#define PMC_SLPWK_SR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_SR0) Register Mask */ + +#define PMC_SLPWK_SR0_PID_Pos _U_(7) /**< (PMC_SLPWK_SR0 Position) Peripheral 3x SleepWalking Status */ +#define PMC_SLPWK_SR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_SR0_PID_Pos) /**< (PMC_SLPWK_SR0 Mask) PID */ +#define PMC_SLPWK_SR0_PID(value) (PMC_SLPWK_SR0_PID_Msk & ((value) << PMC_SLPWK_SR0_PID_Pos)) + +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x120) ( R/ 32) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7_Pos _U_(7) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID7_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID7_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 7 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID7(value) (PMC_SLPWK_ASR0_PID7_Msk & ((value) << PMC_SLPWK_ASR0_PID7_Pos)) +#define PMC_SLPWK_ASR0_PID8_Pos _U_(8) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID8_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID8_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 8 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID8(value) (PMC_SLPWK_ASR0_PID8_Msk & ((value) << PMC_SLPWK_ASR0_PID8_Pos)) +#define PMC_SLPWK_ASR0_PID9_Pos _U_(9) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID9_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID9_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 9 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID9(value) (PMC_SLPWK_ASR0_PID9_Msk & ((value) << PMC_SLPWK_ASR0_PID9_Pos)) +#define PMC_SLPWK_ASR0_PID10_Pos _U_(10) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID10_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID10_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 10 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID10(value) (PMC_SLPWK_ASR0_PID10_Msk & ((value) << PMC_SLPWK_ASR0_PID10_Pos)) +#define PMC_SLPWK_ASR0_PID11_Pos _U_(11) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID11_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID11_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 11 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID11(value) (PMC_SLPWK_ASR0_PID11_Msk & ((value) << PMC_SLPWK_ASR0_PID11_Pos)) +#define PMC_SLPWK_ASR0_PID12_Pos _U_(12) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID12_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID12_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 12 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID12(value) (PMC_SLPWK_ASR0_PID12_Msk & ((value) << PMC_SLPWK_ASR0_PID12_Pos)) +#define PMC_SLPWK_ASR0_PID13_Pos _U_(13) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID13_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID13_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 13 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID13(value) (PMC_SLPWK_ASR0_PID13_Msk & ((value) << PMC_SLPWK_ASR0_PID13_Pos)) +#define PMC_SLPWK_ASR0_PID14_Pos _U_(14) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID14_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID14_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 14 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID14(value) (PMC_SLPWK_ASR0_PID14_Msk & ((value) << PMC_SLPWK_ASR0_PID14_Pos)) +#define PMC_SLPWK_ASR0_PID15_Pos _U_(15) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID15_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID15_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 15 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID15(value) (PMC_SLPWK_ASR0_PID15_Msk & ((value) << PMC_SLPWK_ASR0_PID15_Pos)) +#define PMC_SLPWK_ASR0_PID16_Pos _U_(16) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID16_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID16_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 16 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID16(value) (PMC_SLPWK_ASR0_PID16_Msk & ((value) << PMC_SLPWK_ASR0_PID16_Pos)) +#define PMC_SLPWK_ASR0_PID17_Pos _U_(17) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID17_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID17_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 17 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID17(value) (PMC_SLPWK_ASR0_PID17_Msk & ((value) << PMC_SLPWK_ASR0_PID17_Pos)) +#define PMC_SLPWK_ASR0_PID18_Pos _U_(18) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID18_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID18_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 18 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID18(value) (PMC_SLPWK_ASR0_PID18_Msk & ((value) << PMC_SLPWK_ASR0_PID18_Pos)) +#define PMC_SLPWK_ASR0_PID19_Pos _U_(19) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID19_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID19_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 19 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID19(value) (PMC_SLPWK_ASR0_PID19_Msk & ((value) << PMC_SLPWK_ASR0_PID19_Pos)) +#define PMC_SLPWK_ASR0_PID20_Pos _U_(20) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID20_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID20_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 20 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID20(value) (PMC_SLPWK_ASR0_PID20_Msk & ((value) << PMC_SLPWK_ASR0_PID20_Pos)) +#define PMC_SLPWK_ASR0_PID21_Pos _U_(21) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID21_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID21_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 21 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID21(value) (PMC_SLPWK_ASR0_PID21_Msk & ((value) << PMC_SLPWK_ASR0_PID21_Pos)) +#define PMC_SLPWK_ASR0_PID22_Pos _U_(22) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID22_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID22_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 22 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID22(value) (PMC_SLPWK_ASR0_PID22_Msk & ((value) << PMC_SLPWK_ASR0_PID22_Pos)) +#define PMC_SLPWK_ASR0_PID23_Pos _U_(23) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID23_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID23_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 23 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID23(value) (PMC_SLPWK_ASR0_PID23_Msk & ((value) << PMC_SLPWK_ASR0_PID23_Pos)) +#define PMC_SLPWK_ASR0_PID24_Pos _U_(24) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID24_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID24_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 24 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID24(value) (PMC_SLPWK_ASR0_PID24_Msk & ((value) << PMC_SLPWK_ASR0_PID24_Pos)) +#define PMC_SLPWK_ASR0_PID25_Pos _U_(25) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID25_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID25_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 25 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID25(value) (PMC_SLPWK_ASR0_PID25_Msk & ((value) << PMC_SLPWK_ASR0_PID25_Pos)) +#define PMC_SLPWK_ASR0_PID26_Pos _U_(26) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID26_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID26_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 26 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID26(value) (PMC_SLPWK_ASR0_PID26_Msk & ((value) << PMC_SLPWK_ASR0_PID26_Pos)) +#define PMC_SLPWK_ASR0_PID27_Pos _U_(27) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID27_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID27_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 27 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID27(value) (PMC_SLPWK_ASR0_PID27_Msk & ((value) << PMC_SLPWK_ASR0_PID27_Pos)) +#define PMC_SLPWK_ASR0_PID28_Pos _U_(28) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID28_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID28_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 28 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID28(value) (PMC_SLPWK_ASR0_PID28_Msk & ((value) << PMC_SLPWK_ASR0_PID28_Pos)) +#define PMC_SLPWK_ASR0_PID29_Pos _U_(29) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID29_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID29_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 29 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID29(value) (PMC_SLPWK_ASR0_PID29_Msk & ((value) << PMC_SLPWK_ASR0_PID29_Pos)) +#define PMC_SLPWK_ASR0_PID30_Pos _U_(30) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID30_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID30_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 30 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID30(value) (PMC_SLPWK_ASR0_PID30_Msk & ((value) << PMC_SLPWK_ASR0_PID30_Pos)) +#define PMC_SLPWK_ASR0_PID31_Pos _U_(31) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Position */ +#define PMC_SLPWK_ASR0_PID31_Msk (_U_(0x1) << PMC_SLPWK_ASR0_PID31_Pos) /**< (PMC_SLPWK_ASR0) Peripheral 31 Activity Status Mask */ +#define PMC_SLPWK_ASR0_PID31(value) (PMC_SLPWK_ASR0_PID31_Msk & ((value) << PMC_SLPWK_ASR0_PID31_Pos)) +#define PMC_SLPWK_ASR0_Msk _U_(0xFFFFFF80) /**< (PMC_SLPWK_ASR0) Register Mask */ + +#define PMC_SLPWK_ASR0_PID_Pos _U_(7) /**< (PMC_SLPWK_ASR0 Position) Peripheral 3x Activity Status */ +#define PMC_SLPWK_ASR0_PID_Msk (_U_(0x1FFFFFF) << PMC_SLPWK_ASR0_PID_Pos) /**< (PMC_SLPWK_ASR0 Mask) PID */ +#define PMC_SLPWK_ASR0_PID(value) (PMC_SLPWK_ASR0_PID_Msk & ((value) << PMC_SLPWK_ASR0_PID_Pos)) + +/* -------- PMC_PMMR : (PMC Offset: 0x130) (R/W 32) PLL Maximum Multiplier Value Register -------- */ +#define PMC_PMMR_PLLA_MMAX_Pos _U_(0) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Position */ +#define PMC_PMMR_PLLA_MMAX_Msk (_U_(0x7FF) << PMC_PMMR_PLLA_MMAX_Pos) /**< (PMC_PMMR) PLLA Maximum Allowed Multiplier Value Mask */ +#define PMC_PMMR_PLLA_MMAX(value) (PMC_PMMR_PLLA_MMAX_Msk & ((value) << PMC_PMMR_PLLA_MMAX_Pos)) +#define PMC_PMMR_Msk _U_(0x000007FF) /**< (PMC_PMMR) Register Mask */ + + +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x134) ( /W 32) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32_Pos _U_(0) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID32_Pos) /**< (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID32(value) (PMC_SLPWK_ER1_PID32_Msk & ((value) << PMC_SLPWK_ER1_PID32_Pos)) +#define PMC_SLPWK_ER1_PID33_Pos _U_(1) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID33_Pos) /**< (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID33(value) (PMC_SLPWK_ER1_PID33_Msk & ((value) << PMC_SLPWK_ER1_PID33_Pos)) +#define PMC_SLPWK_ER1_PID34_Pos _U_(2) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID34_Pos) /**< (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID34(value) (PMC_SLPWK_ER1_PID34_Msk & ((value) << PMC_SLPWK_ER1_PID34_Pos)) +#define PMC_SLPWK_ER1_PID35_Pos _U_(3) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID35_Pos) /**< (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID35(value) (PMC_SLPWK_ER1_PID35_Msk & ((value) << PMC_SLPWK_ER1_PID35_Pos)) +#define PMC_SLPWK_ER1_PID37_Pos _U_(5) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID37_Pos) /**< (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID37(value) (PMC_SLPWK_ER1_PID37_Msk & ((value) << PMC_SLPWK_ER1_PID37_Pos)) +#define PMC_SLPWK_ER1_PID39_Pos _U_(7) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID39_Pos) /**< (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID39(value) (PMC_SLPWK_ER1_PID39_Msk & ((value) << PMC_SLPWK_ER1_PID39_Pos)) +#define PMC_SLPWK_ER1_PID40_Pos _U_(8) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID40_Pos) /**< (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID40(value) (PMC_SLPWK_ER1_PID40_Msk & ((value) << PMC_SLPWK_ER1_PID40_Pos)) +#define PMC_SLPWK_ER1_PID41_Pos _U_(9) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID41_Pos) /**< (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID41(value) (PMC_SLPWK_ER1_PID41_Msk & ((value) << PMC_SLPWK_ER1_PID41_Pos)) +#define PMC_SLPWK_ER1_PID42_Pos _U_(10) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID42_Pos) /**< (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID42(value) (PMC_SLPWK_ER1_PID42_Msk & ((value) << PMC_SLPWK_ER1_PID42_Pos)) +#define PMC_SLPWK_ER1_PID43_Pos _U_(11) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID43_Pos) /**< (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID43(value) (PMC_SLPWK_ER1_PID43_Msk & ((value) << PMC_SLPWK_ER1_PID43_Pos)) +#define PMC_SLPWK_ER1_PID44_Pos _U_(12) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID44_Pos) /**< (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID44(value) (PMC_SLPWK_ER1_PID44_Msk & ((value) << PMC_SLPWK_ER1_PID44_Pos)) +#define PMC_SLPWK_ER1_PID45_Pos _U_(13) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID45_Pos) /**< (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID45(value) (PMC_SLPWK_ER1_PID45_Msk & ((value) << PMC_SLPWK_ER1_PID45_Pos)) +#define PMC_SLPWK_ER1_PID46_Pos _U_(14) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID46_Pos) /**< (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID46(value) (PMC_SLPWK_ER1_PID46_Msk & ((value) << PMC_SLPWK_ER1_PID46_Pos)) +#define PMC_SLPWK_ER1_PID47_Pos _U_(15) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID47_Pos) /**< (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID47(value) (PMC_SLPWK_ER1_PID47_Msk & ((value) << PMC_SLPWK_ER1_PID47_Pos)) +#define PMC_SLPWK_ER1_PID48_Pos _U_(16) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID48_Pos) /**< (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID48(value) (PMC_SLPWK_ER1_PID48_Msk & ((value) << PMC_SLPWK_ER1_PID48_Pos)) +#define PMC_SLPWK_ER1_PID49_Pos _U_(17) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID49_Pos) /**< (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID49(value) (PMC_SLPWK_ER1_PID49_Msk & ((value) << PMC_SLPWK_ER1_PID49_Pos)) +#define PMC_SLPWK_ER1_PID50_Pos _U_(18) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID50_Pos) /**< (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID50(value) (PMC_SLPWK_ER1_PID50_Msk & ((value) << PMC_SLPWK_ER1_PID50_Pos)) +#define PMC_SLPWK_ER1_PID51_Pos _U_(19) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID51_Pos) /**< (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID51(value) (PMC_SLPWK_ER1_PID51_Msk & ((value) << PMC_SLPWK_ER1_PID51_Pos)) +#define PMC_SLPWK_ER1_PID52_Pos _U_(20) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID52_Pos) /**< (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID52(value) (PMC_SLPWK_ER1_PID52_Msk & ((value) << PMC_SLPWK_ER1_PID52_Pos)) +#define PMC_SLPWK_ER1_PID56_Pos _U_(24) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID56_Pos) /**< (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID56(value) (PMC_SLPWK_ER1_PID56_Msk & ((value) << PMC_SLPWK_ER1_PID56_Pos)) +#define PMC_SLPWK_ER1_PID57_Pos _U_(25) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID57_Pos) /**< (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID57(value) (PMC_SLPWK_ER1_PID57_Msk & ((value) << PMC_SLPWK_ER1_PID57_Pos)) +#define PMC_SLPWK_ER1_PID58_Pos _U_(26) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID58_Pos) /**< (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID58(value) (PMC_SLPWK_ER1_PID58_Msk & ((value) << PMC_SLPWK_ER1_PID58_Pos)) +#define PMC_SLPWK_ER1_PID59_Pos _U_(27) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID59_Pos) /**< (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID59(value) (PMC_SLPWK_ER1_PID59_Msk & ((value) << PMC_SLPWK_ER1_PID59_Pos)) +#define PMC_SLPWK_ER1_PID60_Pos _U_(28) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Position */ +#define PMC_SLPWK_ER1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ER1_PID60_Pos) /**< (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable Mask */ +#define PMC_SLPWK_ER1_PID60(value) (PMC_SLPWK_ER1_PID60_Msk & ((value) << PMC_SLPWK_ER1_PID60_Pos)) +#define PMC_SLPWK_ER1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_ER1) Register Mask */ + +#define PMC_SLPWK_ER1_PID_Pos _U_(0) /**< (PMC_SLPWK_ER1 Position) Peripheral 6x SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_ER1_PID_Pos) /**< (PMC_SLPWK_ER1 Mask) PID */ +#define PMC_SLPWK_ER1_PID(value) (PMC_SLPWK_ER1_PID_Msk & ((value) << PMC_SLPWK_ER1_PID_Pos)) + +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x138) ( /W 32) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID32_Pos) /**< (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID32(value) (PMC_SLPWK_DR1_PID32_Msk & ((value) << PMC_SLPWK_DR1_PID32_Pos)) +#define PMC_SLPWK_DR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID33_Pos) /**< (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID33(value) (PMC_SLPWK_DR1_PID33_Msk & ((value) << PMC_SLPWK_DR1_PID33_Pos)) +#define PMC_SLPWK_DR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID34_Pos) /**< (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID34(value) (PMC_SLPWK_DR1_PID34_Msk & ((value) << PMC_SLPWK_DR1_PID34_Pos)) +#define PMC_SLPWK_DR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID35_Pos) /**< (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID35(value) (PMC_SLPWK_DR1_PID35_Msk & ((value) << PMC_SLPWK_DR1_PID35_Pos)) +#define PMC_SLPWK_DR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID37_Pos) /**< (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID37(value) (PMC_SLPWK_DR1_PID37_Msk & ((value) << PMC_SLPWK_DR1_PID37_Pos)) +#define PMC_SLPWK_DR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID39_Pos) /**< (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID39(value) (PMC_SLPWK_DR1_PID39_Msk & ((value) << PMC_SLPWK_DR1_PID39_Pos)) +#define PMC_SLPWK_DR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID40_Pos) /**< (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID40(value) (PMC_SLPWK_DR1_PID40_Msk & ((value) << PMC_SLPWK_DR1_PID40_Pos)) +#define PMC_SLPWK_DR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID41_Pos) /**< (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID41(value) (PMC_SLPWK_DR1_PID41_Msk & ((value) << PMC_SLPWK_DR1_PID41_Pos)) +#define PMC_SLPWK_DR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID42_Pos) /**< (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID42(value) (PMC_SLPWK_DR1_PID42_Msk & ((value) << PMC_SLPWK_DR1_PID42_Pos)) +#define PMC_SLPWK_DR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID43_Pos) /**< (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID43(value) (PMC_SLPWK_DR1_PID43_Msk & ((value) << PMC_SLPWK_DR1_PID43_Pos)) +#define PMC_SLPWK_DR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID44_Pos) /**< (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID44(value) (PMC_SLPWK_DR1_PID44_Msk & ((value) << PMC_SLPWK_DR1_PID44_Pos)) +#define PMC_SLPWK_DR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID45_Pos) /**< (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID45(value) (PMC_SLPWK_DR1_PID45_Msk & ((value) << PMC_SLPWK_DR1_PID45_Pos)) +#define PMC_SLPWK_DR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID46_Pos) /**< (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID46(value) (PMC_SLPWK_DR1_PID46_Msk & ((value) << PMC_SLPWK_DR1_PID46_Pos)) +#define PMC_SLPWK_DR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID47_Pos) /**< (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID47(value) (PMC_SLPWK_DR1_PID47_Msk & ((value) << PMC_SLPWK_DR1_PID47_Pos)) +#define PMC_SLPWK_DR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID48_Pos) /**< (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID48(value) (PMC_SLPWK_DR1_PID48_Msk & ((value) << PMC_SLPWK_DR1_PID48_Pos)) +#define PMC_SLPWK_DR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID49_Pos) /**< (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID49(value) (PMC_SLPWK_DR1_PID49_Msk & ((value) << PMC_SLPWK_DR1_PID49_Pos)) +#define PMC_SLPWK_DR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID50_Pos) /**< (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID50(value) (PMC_SLPWK_DR1_PID50_Msk & ((value) << PMC_SLPWK_DR1_PID50_Pos)) +#define PMC_SLPWK_DR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID51_Pos) /**< (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID51(value) (PMC_SLPWK_DR1_PID51_Msk & ((value) << PMC_SLPWK_DR1_PID51_Pos)) +#define PMC_SLPWK_DR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID52_Pos) /**< (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID52(value) (PMC_SLPWK_DR1_PID52_Msk & ((value) << PMC_SLPWK_DR1_PID52_Pos)) +#define PMC_SLPWK_DR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID56_Pos) /**< (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID56(value) (PMC_SLPWK_DR1_PID56_Msk & ((value) << PMC_SLPWK_DR1_PID56_Pos)) +#define PMC_SLPWK_DR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID57_Pos) /**< (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID57(value) (PMC_SLPWK_DR1_PID57_Msk & ((value) << PMC_SLPWK_DR1_PID57_Pos)) +#define PMC_SLPWK_DR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID58_Pos) /**< (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID58(value) (PMC_SLPWK_DR1_PID58_Msk & ((value) << PMC_SLPWK_DR1_PID58_Pos)) +#define PMC_SLPWK_DR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID59_Pos) /**< (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID59(value) (PMC_SLPWK_DR1_PID59_Msk & ((value) << PMC_SLPWK_DR1_PID59_Pos)) +#define PMC_SLPWK_DR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Position */ +#define PMC_SLPWK_DR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_DR1_PID60_Pos) /**< (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable Mask */ +#define PMC_SLPWK_DR1_PID60(value) (PMC_SLPWK_DR1_PID60_Msk & ((value) << PMC_SLPWK_DR1_PID60_Pos)) +#define PMC_SLPWK_DR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_DR1) Register Mask */ + +#define PMC_SLPWK_DR1_PID_Pos _U_(0) /**< (PMC_SLPWK_DR1 Position) Peripheral 6x SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_DR1_PID_Pos) /**< (PMC_SLPWK_DR1 Mask) PID */ +#define PMC_SLPWK_DR1_PID(value) (PMC_SLPWK_DR1_PID_Msk & ((value) << PMC_SLPWK_DR1_PID_Pos)) + +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x13C) ( R/ 32) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID32_Pos) /**< (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID32(value) (PMC_SLPWK_SR1_PID32_Msk & ((value) << PMC_SLPWK_SR1_PID32_Pos)) +#define PMC_SLPWK_SR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID33_Pos) /**< (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID33(value) (PMC_SLPWK_SR1_PID33_Msk & ((value) << PMC_SLPWK_SR1_PID33_Pos)) +#define PMC_SLPWK_SR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID34_Pos) /**< (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID34(value) (PMC_SLPWK_SR1_PID34_Msk & ((value) << PMC_SLPWK_SR1_PID34_Pos)) +#define PMC_SLPWK_SR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID35_Pos) /**< (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID35(value) (PMC_SLPWK_SR1_PID35_Msk & ((value) << PMC_SLPWK_SR1_PID35_Pos)) +#define PMC_SLPWK_SR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID37_Pos) /**< (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID37(value) (PMC_SLPWK_SR1_PID37_Msk & ((value) << PMC_SLPWK_SR1_PID37_Pos)) +#define PMC_SLPWK_SR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID39_Pos) /**< (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID39(value) (PMC_SLPWK_SR1_PID39_Msk & ((value) << PMC_SLPWK_SR1_PID39_Pos)) +#define PMC_SLPWK_SR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID40_Pos) /**< (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID40(value) (PMC_SLPWK_SR1_PID40_Msk & ((value) << PMC_SLPWK_SR1_PID40_Pos)) +#define PMC_SLPWK_SR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID41_Pos) /**< (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID41(value) (PMC_SLPWK_SR1_PID41_Msk & ((value) << PMC_SLPWK_SR1_PID41_Pos)) +#define PMC_SLPWK_SR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID42_Pos) /**< (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID42(value) (PMC_SLPWK_SR1_PID42_Msk & ((value) << PMC_SLPWK_SR1_PID42_Pos)) +#define PMC_SLPWK_SR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID43_Pos) /**< (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID43(value) (PMC_SLPWK_SR1_PID43_Msk & ((value) << PMC_SLPWK_SR1_PID43_Pos)) +#define PMC_SLPWK_SR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID44_Pos) /**< (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID44(value) (PMC_SLPWK_SR1_PID44_Msk & ((value) << PMC_SLPWK_SR1_PID44_Pos)) +#define PMC_SLPWK_SR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID45_Pos) /**< (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID45(value) (PMC_SLPWK_SR1_PID45_Msk & ((value) << PMC_SLPWK_SR1_PID45_Pos)) +#define PMC_SLPWK_SR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID46_Pos) /**< (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID46(value) (PMC_SLPWK_SR1_PID46_Msk & ((value) << PMC_SLPWK_SR1_PID46_Pos)) +#define PMC_SLPWK_SR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID47_Pos) /**< (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID47(value) (PMC_SLPWK_SR1_PID47_Msk & ((value) << PMC_SLPWK_SR1_PID47_Pos)) +#define PMC_SLPWK_SR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID48_Pos) /**< (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID48(value) (PMC_SLPWK_SR1_PID48_Msk & ((value) << PMC_SLPWK_SR1_PID48_Pos)) +#define PMC_SLPWK_SR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID49_Pos) /**< (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID49(value) (PMC_SLPWK_SR1_PID49_Msk & ((value) << PMC_SLPWK_SR1_PID49_Pos)) +#define PMC_SLPWK_SR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID50_Pos) /**< (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID50(value) (PMC_SLPWK_SR1_PID50_Msk & ((value) << PMC_SLPWK_SR1_PID50_Pos)) +#define PMC_SLPWK_SR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID51_Pos) /**< (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID51(value) (PMC_SLPWK_SR1_PID51_Msk & ((value) << PMC_SLPWK_SR1_PID51_Pos)) +#define PMC_SLPWK_SR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID52_Pos) /**< (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID52(value) (PMC_SLPWK_SR1_PID52_Msk & ((value) << PMC_SLPWK_SR1_PID52_Pos)) +#define PMC_SLPWK_SR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID56_Pos) /**< (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID56(value) (PMC_SLPWK_SR1_PID56_Msk & ((value) << PMC_SLPWK_SR1_PID56_Pos)) +#define PMC_SLPWK_SR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID57_Pos) /**< (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID57(value) (PMC_SLPWK_SR1_PID57_Msk & ((value) << PMC_SLPWK_SR1_PID57_Pos)) +#define PMC_SLPWK_SR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID58_Pos) /**< (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID58(value) (PMC_SLPWK_SR1_PID58_Msk & ((value) << PMC_SLPWK_SR1_PID58_Pos)) +#define PMC_SLPWK_SR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID59_Pos) /**< (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID59(value) (PMC_SLPWK_SR1_PID59_Msk & ((value) << PMC_SLPWK_SR1_PID59_Pos)) +#define PMC_SLPWK_SR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Position */ +#define PMC_SLPWK_SR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_SR1_PID60_Pos) /**< (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status Mask */ +#define PMC_SLPWK_SR1_PID60(value) (PMC_SLPWK_SR1_PID60_Msk & ((value) << PMC_SLPWK_SR1_PID60_Pos)) +#define PMC_SLPWK_SR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_SR1) Register Mask */ + +#define PMC_SLPWK_SR1_PID_Pos _U_(0) /**< (PMC_SLPWK_SR1 Position) Peripheral 6x SleepWalking Status */ +#define PMC_SLPWK_SR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_SR1_PID_Pos) /**< (PMC_SLPWK_SR1 Mask) PID */ +#define PMC_SLPWK_SR1_PID(value) (PMC_SLPWK_SR1_PID_Msk & ((value) << PMC_SLPWK_SR1_PID_Pos)) + +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x140) ( R/ 32) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32_Pos _U_(0) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID32_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID32_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 32 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID32(value) (PMC_SLPWK_ASR1_PID32_Msk & ((value) << PMC_SLPWK_ASR1_PID32_Pos)) +#define PMC_SLPWK_ASR1_PID33_Pos _U_(1) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID33_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID33_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 33 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID33(value) (PMC_SLPWK_ASR1_PID33_Msk & ((value) << PMC_SLPWK_ASR1_PID33_Pos)) +#define PMC_SLPWK_ASR1_PID34_Pos _U_(2) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID34_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID34_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 34 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID34(value) (PMC_SLPWK_ASR1_PID34_Msk & ((value) << PMC_SLPWK_ASR1_PID34_Pos)) +#define PMC_SLPWK_ASR1_PID35_Pos _U_(3) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID35_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID35_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 35 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID35(value) (PMC_SLPWK_ASR1_PID35_Msk & ((value) << PMC_SLPWK_ASR1_PID35_Pos)) +#define PMC_SLPWK_ASR1_PID37_Pos _U_(5) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID37_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID37_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 37 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID37(value) (PMC_SLPWK_ASR1_PID37_Msk & ((value) << PMC_SLPWK_ASR1_PID37_Pos)) +#define PMC_SLPWK_ASR1_PID39_Pos _U_(7) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID39_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID39_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 39 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID39(value) (PMC_SLPWK_ASR1_PID39_Msk & ((value) << PMC_SLPWK_ASR1_PID39_Pos)) +#define PMC_SLPWK_ASR1_PID40_Pos _U_(8) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID40_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID40_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 40 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID40(value) (PMC_SLPWK_ASR1_PID40_Msk & ((value) << PMC_SLPWK_ASR1_PID40_Pos)) +#define PMC_SLPWK_ASR1_PID41_Pos _U_(9) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID41_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID41_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 41 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID41(value) (PMC_SLPWK_ASR1_PID41_Msk & ((value) << PMC_SLPWK_ASR1_PID41_Pos)) +#define PMC_SLPWK_ASR1_PID42_Pos _U_(10) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID42_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID42_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 42 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID42(value) (PMC_SLPWK_ASR1_PID42_Msk & ((value) << PMC_SLPWK_ASR1_PID42_Pos)) +#define PMC_SLPWK_ASR1_PID43_Pos _U_(11) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID43_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID43_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 43 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID43(value) (PMC_SLPWK_ASR1_PID43_Msk & ((value) << PMC_SLPWK_ASR1_PID43_Pos)) +#define PMC_SLPWK_ASR1_PID44_Pos _U_(12) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID44_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID44_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 44 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID44(value) (PMC_SLPWK_ASR1_PID44_Msk & ((value) << PMC_SLPWK_ASR1_PID44_Pos)) +#define PMC_SLPWK_ASR1_PID45_Pos _U_(13) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID45_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID45_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 45 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID45(value) (PMC_SLPWK_ASR1_PID45_Msk & ((value) << PMC_SLPWK_ASR1_PID45_Pos)) +#define PMC_SLPWK_ASR1_PID46_Pos _U_(14) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID46_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID46_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 46 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID46(value) (PMC_SLPWK_ASR1_PID46_Msk & ((value) << PMC_SLPWK_ASR1_PID46_Pos)) +#define PMC_SLPWK_ASR1_PID47_Pos _U_(15) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID47_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID47_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 47 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID47(value) (PMC_SLPWK_ASR1_PID47_Msk & ((value) << PMC_SLPWK_ASR1_PID47_Pos)) +#define PMC_SLPWK_ASR1_PID48_Pos _U_(16) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID48_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID48_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 48 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID48(value) (PMC_SLPWK_ASR1_PID48_Msk & ((value) << PMC_SLPWK_ASR1_PID48_Pos)) +#define PMC_SLPWK_ASR1_PID49_Pos _U_(17) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID49_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID49_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 49 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID49(value) (PMC_SLPWK_ASR1_PID49_Msk & ((value) << PMC_SLPWK_ASR1_PID49_Pos)) +#define PMC_SLPWK_ASR1_PID50_Pos _U_(18) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID50_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID50_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 50 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID50(value) (PMC_SLPWK_ASR1_PID50_Msk & ((value) << PMC_SLPWK_ASR1_PID50_Pos)) +#define PMC_SLPWK_ASR1_PID51_Pos _U_(19) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID51_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID51_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 51 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID51(value) (PMC_SLPWK_ASR1_PID51_Msk & ((value) << PMC_SLPWK_ASR1_PID51_Pos)) +#define PMC_SLPWK_ASR1_PID52_Pos _U_(20) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID52_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID52_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 52 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID52(value) (PMC_SLPWK_ASR1_PID52_Msk & ((value) << PMC_SLPWK_ASR1_PID52_Pos)) +#define PMC_SLPWK_ASR1_PID56_Pos _U_(24) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID56_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID56_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 56 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID56(value) (PMC_SLPWK_ASR1_PID56_Msk & ((value) << PMC_SLPWK_ASR1_PID56_Pos)) +#define PMC_SLPWK_ASR1_PID57_Pos _U_(25) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID57_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID57_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 57 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID57(value) (PMC_SLPWK_ASR1_PID57_Msk & ((value) << PMC_SLPWK_ASR1_PID57_Pos)) +#define PMC_SLPWK_ASR1_PID58_Pos _U_(26) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID58_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID58_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 58 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID58(value) (PMC_SLPWK_ASR1_PID58_Msk & ((value) << PMC_SLPWK_ASR1_PID58_Pos)) +#define PMC_SLPWK_ASR1_PID59_Pos _U_(27) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID59_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID59_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 59 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID59(value) (PMC_SLPWK_ASR1_PID59_Msk & ((value) << PMC_SLPWK_ASR1_PID59_Pos)) +#define PMC_SLPWK_ASR1_PID60_Pos _U_(28) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Position */ +#define PMC_SLPWK_ASR1_PID60_Msk (_U_(0x1) << PMC_SLPWK_ASR1_PID60_Pos) /**< (PMC_SLPWK_ASR1) Peripheral 60 Activity Status Mask */ +#define PMC_SLPWK_ASR1_PID60(value) (PMC_SLPWK_ASR1_PID60_Msk & ((value) << PMC_SLPWK_ASR1_PID60_Pos)) +#define PMC_SLPWK_ASR1_Msk _U_(0x1F1FFFAF) /**< (PMC_SLPWK_ASR1) Register Mask */ + +#define PMC_SLPWK_ASR1_PID_Pos _U_(0) /**< (PMC_SLPWK_ASR1 Position) Peripheral 6x Activity Status */ +#define PMC_SLPWK_ASR1_PID_Msk (_U_(0xFFFFFF) << PMC_SLPWK_ASR1_PID_Pos) /**< (PMC_SLPWK_ASR1 Mask) PID */ +#define PMC_SLPWK_ASR1_PID(value) (PMC_SLPWK_ASR1_PID_Msk & ((value) << PMC_SLPWK_ASR1_PID_Pos)) + +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x144) ( R/ 32) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP_Pos _U_(0) /**< (PMC_SLPWK_AIPR) Activity In Progress Position */ +#define PMC_SLPWK_AIPR_AIP_Msk (_U_(0x1) << PMC_SLPWK_AIPR_AIP_Pos) /**< (PMC_SLPWK_AIPR) Activity In Progress Mask */ +#define PMC_SLPWK_AIPR_AIP(value) (PMC_SLPWK_AIPR_AIP_Msk & ((value) << PMC_SLPWK_AIPR_AIP_Pos)) +#define PMC_SLPWK_AIPR_Msk _U_(0x00000001) /**< (PMC_SLPWK_AIPR) Register Mask */ + + +/** \brief PMC register offsets definitions */ +#define PMC_SCER_REG_OFST (0x00) /**< (PMC_SCER) System Clock Enable Register Offset */ +#define PMC_SCDR_REG_OFST (0x04) /**< (PMC_SCDR) System Clock Disable Register Offset */ +#define PMC_SCSR_REG_OFST (0x08) /**< (PMC_SCSR) System Clock Status Register Offset */ +#define PMC_PCER0_REG_OFST (0x10) /**< (PMC_PCER0) Peripheral Clock Enable Register 0 Offset */ +#define PMC_PCDR0_REG_OFST (0x14) /**< (PMC_PCDR0) Peripheral Clock Disable Register 0 Offset */ +#define PMC_PCSR0_REG_OFST (0x18) /**< (PMC_PCSR0) Peripheral Clock Status Register 0 Offset */ +#define CKGR_UCKR_REG_OFST (0x1C) /**< (CKGR_UCKR) UTMI Clock Register Offset */ +#define CKGR_MOR_REG_OFST (0x20) /**< (CKGR_MOR) Main Oscillator Register Offset */ +#define CKGR_MCFR_REG_OFST (0x24) /**< (CKGR_MCFR) Main Clock Frequency Register Offset */ +#define CKGR_PLLAR_REG_OFST (0x28) /**< (CKGR_PLLAR) PLLA Register Offset */ +#define PMC_MCKR_REG_OFST (0x30) /**< (PMC_MCKR) Master Clock Register Offset */ +#define PMC_USB_REG_OFST (0x38) /**< (PMC_USB) USB Clock Register Offset */ +#define PMC_PCK_REG_OFST (0x40) /**< (PMC_PCK) Programmable Clock Register Offset */ +#define PMC_IER_REG_OFST (0x60) /**< (PMC_IER) Interrupt Enable Register Offset */ +#define PMC_IDR_REG_OFST (0x64) /**< (PMC_IDR) Interrupt Disable Register Offset */ +#define PMC_SR_REG_OFST (0x68) /**< (PMC_SR) Status Register Offset */ +#define PMC_IMR_REG_OFST (0x6C) /**< (PMC_IMR) Interrupt Mask Register Offset */ +#define PMC_FSMR_REG_OFST (0x70) /**< (PMC_FSMR) Fast Startup Mode Register Offset */ +#define PMC_FSPR_REG_OFST (0x74) /**< (PMC_FSPR) Fast Startup Polarity Register Offset */ +#define PMC_FOCR_REG_OFST (0x78) /**< (PMC_FOCR) Fault Output Clear Register Offset */ +#define PMC_WPMR_REG_OFST (0xE4) /**< (PMC_WPMR) Write Protection Mode Register Offset */ +#define PMC_WPSR_REG_OFST (0xE8) /**< (PMC_WPSR) Write Protection Status Register Offset */ +#define PMC_PCER1_REG_OFST (0x100) /**< (PMC_PCER1) Peripheral Clock Enable Register 1 Offset */ +#define PMC_PCDR1_REG_OFST (0x104) /**< (PMC_PCDR1) Peripheral Clock Disable Register 1 Offset */ +#define PMC_PCSR1_REG_OFST (0x108) /**< (PMC_PCSR1) Peripheral Clock Status Register 1 Offset */ +#define PMC_PCR_REG_OFST (0x10C) /**< (PMC_PCR) Peripheral Control Register Offset */ +#define PMC_OCR_REG_OFST (0x110) /**< (PMC_OCR) Oscillator Calibration Register Offset */ +#define PMC_SLPWK_ER0_REG_OFST (0x114) /**< (PMC_SLPWK_ER0) SleepWalking Enable Register 0 Offset */ +#define PMC_SLPWK_DR0_REG_OFST (0x118) /**< (PMC_SLPWK_DR0) SleepWalking Disable Register 0 Offset */ +#define PMC_SLPWK_SR0_REG_OFST (0x11C) /**< (PMC_SLPWK_SR0) SleepWalking Status Register 0 Offset */ +#define PMC_SLPWK_ASR0_REG_OFST (0x120) /**< (PMC_SLPWK_ASR0) SleepWalking Activity Status Register 0 Offset */ +#define PMC_PMMR_REG_OFST (0x130) /**< (PMC_PMMR) PLL Maximum Multiplier Value Register Offset */ +#define PMC_SLPWK_ER1_REG_OFST (0x134) /**< (PMC_SLPWK_ER1) SleepWalking Enable Register 1 Offset */ +#define PMC_SLPWK_DR1_REG_OFST (0x138) /**< (PMC_SLPWK_DR1) SleepWalking Disable Register 1 Offset */ +#define PMC_SLPWK_SR1_REG_OFST (0x13C) /**< (PMC_SLPWK_SR1) SleepWalking Status Register 1 Offset */ +#define PMC_SLPWK_ASR1_REG_OFST (0x140) /**< (PMC_SLPWK_ASR1) SleepWalking Activity Status Register 1 Offset */ +#define PMC_SLPWK_AIPR_REG_OFST (0x144) /**< (PMC_SLPWK_AIPR) SleepWalking Activity In Progress Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PMC register API structure */ +typedef struct +{ + __O uint32_t PMC_SCER; /**< Offset: 0x00 ( /W 32) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< Offset: 0x04 ( /W 32) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< Offset: 0x08 (R/ 32) System Clock Status Register */ + __I uint8_t Reserved1[0x04]; + __O uint32_t PMC_PCER0; /**< Offset: 0x10 ( /W 32) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< Offset: 0x14 ( /W 32) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< Offset: 0x18 (R/ 32) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< Offset: 0x1C (R/W 32) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< Offset: 0x20 (R/W 32) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< Offset: 0x24 (R/W 32) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< Offset: 0x28 (R/W 32) PLLA Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t PMC_MCKR; /**< Offset: 0x30 (R/W 32) Master Clock Register */ + __I uint8_t Reserved3[0x04]; + __IO uint32_t PMC_USB; /**< Offset: 0x38 (R/W 32) USB Clock Register */ + __I uint8_t Reserved4[0x04]; + __IO uint32_t PMC_PCK[8]; /**< Offset: 0x40 (R/W 32) Programmable Clock Register */ + __O uint32_t PMC_IER; /**< Offset: 0x60 ( /W 32) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< Offset: 0x64 ( /W 32) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< Offset: 0x68 (R/ 32) Status Register */ + __I uint32_t PMC_IMR; /**< Offset: 0x6C (R/ 32) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< Offset: 0x70 (R/W 32) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< Offset: 0x74 (R/W 32) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< Offset: 0x78 ( /W 32) Fault Output Clear Register */ + __I uint8_t Reserved5[0x68]; + __IO uint32_t PMC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ + __I uint8_t Reserved6[0x14]; + __O uint32_t PMC_PCER1; /**< Offset: 0x100 ( /W 32) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< Offset: 0x104 ( /W 32) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< Offset: 0x108 (R/ 32) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< Offset: 0x10C (R/W 32) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< Offset: 0x110 (R/W 32) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< Offset: 0x114 ( /W 32) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< Offset: 0x118 ( /W 32) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< Offset: 0x11C (R/ 32) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< Offset: 0x120 (R/ 32) SleepWalking Activity Status Register 0 */ + __I uint8_t Reserved7[0x0C]; + __IO uint32_t PMC_PMMR; /**< Offset: 0x130 (R/W 32) PLL Maximum Multiplier Value Register */ + __O uint32_t PMC_SLPWK_ER1; /**< Offset: 0x134 ( /W 32) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< Offset: 0x138 ( /W 32) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< Offset: 0x13C (R/ 32) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< Offset: 0x140 (R/ 32) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< Offset: 0x144 (R/ 32) SleepWalking Activity In Progress Register */ +} pmc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/pwm.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/pwm.h new file mode 100644 index 00000000..912e9aff --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/pwm.h @@ -0,0 +1,1583 @@ +/** + * \brief Component description for PWM + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_PWM_COMPONENT_H_ +#define _SAME70_PWM_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR PWM */ +/* ************************************************************************** */ + +/* -------- PWM_CMR : (PWM Offset: 0x00) (R/W 32) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos _U_(0) /**< (PWM_CMR) Channel Pre-scaler Position */ +#define PWM_CMR_CPRE_Msk (_U_(0xF) << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Channel Pre-scaler Mask */ +#define PWM_CMR_CPRE(value) (PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)) +#define PWM_CMR_CPRE_MCK_Val _U_(0x0) /**< (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2_Val _U_(0x1) /**< (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4_Val _U_(0x2) /**< (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8_Val _U_(0x3) /**< (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16_Val _U_(0x4) /**< (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32_Val _U_(0x5) /**< (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64_Val _U_(0x6) /**< (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128_Val _U_(0x7) /**< (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256_Val _U_(0x8) /**< (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512_Val _U_(0x9) /**< (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024_Val _U_(0xA) /**< (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA_Val _U_(0xB) /**< (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB_Val _U_(0xC) /**< (PWM_CMR) Clock B */ +#define PWM_CMR_CPRE_MCK (PWM_CMR_CPRE_MCK_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock Position */ +#define PWM_CMR_CPRE_MCK_DIV_2 (PWM_CMR_CPRE_MCK_DIV_2_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/2 Position */ +#define PWM_CMR_CPRE_MCK_DIV_4 (PWM_CMR_CPRE_MCK_DIV_4_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/4 Position */ +#define PWM_CMR_CPRE_MCK_DIV_8 (PWM_CMR_CPRE_MCK_DIV_8_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/8 Position */ +#define PWM_CMR_CPRE_MCK_DIV_16 (PWM_CMR_CPRE_MCK_DIV_16_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/16 Position */ +#define PWM_CMR_CPRE_MCK_DIV_32 (PWM_CMR_CPRE_MCK_DIV_32_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/32 Position */ +#define PWM_CMR_CPRE_MCK_DIV_64 (PWM_CMR_CPRE_MCK_DIV_64_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/64 Position */ +#define PWM_CMR_CPRE_MCK_DIV_128 (PWM_CMR_CPRE_MCK_DIV_128_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/128 Position */ +#define PWM_CMR_CPRE_MCK_DIV_256 (PWM_CMR_CPRE_MCK_DIV_256_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/256 Position */ +#define PWM_CMR_CPRE_MCK_DIV_512 (PWM_CMR_CPRE_MCK_DIV_512_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/512 Position */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (PWM_CMR_CPRE_MCK_DIV_1024_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Peripheral clock/1024 Position */ +#define PWM_CMR_CPRE_CLKA (PWM_CMR_CPRE_CLKA_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock A Position */ +#define PWM_CMR_CPRE_CLKB (PWM_CMR_CPRE_CLKB_Val << PWM_CMR_CPRE_Pos) /**< (PWM_CMR) Clock B Position */ +#define PWM_CMR_CALG_Pos _U_(8) /**< (PWM_CMR) Channel Alignment Position */ +#define PWM_CMR_CALG_Msk (_U_(0x1) << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Channel Alignment Mask */ +#define PWM_CMR_CALG(value) (PWM_CMR_CALG_Msk & ((value) << PWM_CMR_CALG_Pos)) +#define PWM_CMR_CALG_LEFT_ALIGNED_Val _U_(0x0) /**< (PWM_CMR) Left aligned */ +#define PWM_CMR_CALG_CENTER_ALIGNED_Val _U_(0x1) /**< (PWM_CMR) Center aligned */ +#define PWM_CMR_CALG_LEFT_ALIGNED (PWM_CMR_CALG_LEFT_ALIGNED_Val << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Left aligned Position */ +#define PWM_CMR_CALG_CENTER_ALIGNED (PWM_CMR_CALG_CENTER_ALIGNED_Val << PWM_CMR_CALG_Pos) /**< (PWM_CMR) Center aligned Position */ +#define PWM_CMR_CPOL_Pos _U_(9) /**< (PWM_CMR) Channel Polarity Position */ +#define PWM_CMR_CPOL_Msk (_U_(0x1) << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Channel Polarity Mask */ +#define PWM_CMR_CPOL(value) (PWM_CMR_CPOL_Msk & ((value) << PWM_CMR_CPOL_Pos)) +#define PWM_CMR_CPOL_LOW_POLARITY_Val _U_(0x0) /**< (PWM_CMR) Waveform starts at low level */ +#define PWM_CMR_CPOL_HIGH_POLARITY_Val _U_(0x1) /**< (PWM_CMR) Waveform starts at high level */ +#define PWM_CMR_CPOL_LOW_POLARITY (PWM_CMR_CPOL_LOW_POLARITY_Val << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Waveform starts at low level Position */ +#define PWM_CMR_CPOL_HIGH_POLARITY (PWM_CMR_CPOL_HIGH_POLARITY_Val << PWM_CMR_CPOL_Pos) /**< (PWM_CMR) Waveform starts at high level Position */ +#define PWM_CMR_CES_Pos _U_(10) /**< (PWM_CMR) Counter Event Selection Position */ +#define PWM_CMR_CES_Msk (_U_(0x1) << PWM_CMR_CES_Pos) /**< (PWM_CMR) Counter Event Selection Mask */ +#define PWM_CMR_CES(value) (PWM_CMR_CES_Msk & ((value) << PWM_CMR_CES_Pos)) +#define PWM_CMR_CES_SINGLE_EVENT_Val _U_(0x0) /**< (PWM_CMR) At the end of PWM period */ +#define PWM_CMR_CES_DOUBLE_EVENT_Val _U_(0x1) /**< (PWM_CMR) At half of PWM period AND at the end of PWM period */ +#define PWM_CMR_CES_SINGLE_EVENT (PWM_CMR_CES_SINGLE_EVENT_Val << PWM_CMR_CES_Pos) /**< (PWM_CMR) At the end of PWM period Position */ +#define PWM_CMR_CES_DOUBLE_EVENT (PWM_CMR_CES_DOUBLE_EVENT_Val << PWM_CMR_CES_Pos) /**< (PWM_CMR) At half of PWM period AND at the end of PWM period Position */ +#define PWM_CMR_UPDS_Pos _U_(11) /**< (PWM_CMR) Update Selection Position */ +#define PWM_CMR_UPDS_Msk (_U_(0x1) << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) Update Selection Mask */ +#define PWM_CMR_UPDS(value) (PWM_CMR_UPDS_Msk & ((value) << PWM_CMR_UPDS_Pos)) +#define PWM_CMR_UPDS_UPDATE_AT_PERIOD_Val _U_(0x0) /**< (PWM_CMR) At the next end of PWM period */ +#define PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD_Val _U_(0x1) /**< (PWM_CMR) At the next end of Half PWM period */ +#define PWM_CMR_UPDS_UPDATE_AT_PERIOD (PWM_CMR_UPDS_UPDATE_AT_PERIOD_Val << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) At the next end of PWM period Position */ +#define PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD (PWM_CMR_UPDS_UPDATE_AT_HALF_PERIOD_Val << PWM_CMR_UPDS_Pos) /**< (PWM_CMR) At the next end of Half PWM period Position */ +#define PWM_CMR_DPOLI_Pos _U_(12) /**< (PWM_CMR) Disabled Polarity Inverted Position */ +#define PWM_CMR_DPOLI_Msk (_U_(0x1) << PWM_CMR_DPOLI_Pos) /**< (PWM_CMR) Disabled Polarity Inverted Mask */ +#define PWM_CMR_DPOLI(value) (PWM_CMR_DPOLI_Msk & ((value) << PWM_CMR_DPOLI_Pos)) +#define PWM_CMR_TCTS_Pos _U_(13) /**< (PWM_CMR) Timer Counter Trigger Selection Position */ +#define PWM_CMR_TCTS_Msk (_U_(0x1) << PWM_CMR_TCTS_Pos) /**< (PWM_CMR) Timer Counter Trigger Selection Mask */ +#define PWM_CMR_TCTS(value) (PWM_CMR_TCTS_Msk & ((value) << PWM_CMR_TCTS_Pos)) +#define PWM_CMR_DTE_Pos _U_(16) /**< (PWM_CMR) Dead-Time Generator Enable Position */ +#define PWM_CMR_DTE_Msk (_U_(0x1) << PWM_CMR_DTE_Pos) /**< (PWM_CMR) Dead-Time Generator Enable Mask */ +#define PWM_CMR_DTE(value) (PWM_CMR_DTE_Msk & ((value) << PWM_CMR_DTE_Pos)) +#define PWM_CMR_DTHI_Pos _U_(17) /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Position */ +#define PWM_CMR_DTHI_Msk (_U_(0x1) << PWM_CMR_DTHI_Pos) /**< (PWM_CMR) Dead-Time PWMHx Output Inverted Mask */ +#define PWM_CMR_DTHI(value) (PWM_CMR_DTHI_Msk & ((value) << PWM_CMR_DTHI_Pos)) +#define PWM_CMR_DTLI_Pos _U_(18) /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Position */ +#define PWM_CMR_DTLI_Msk (_U_(0x1) << PWM_CMR_DTLI_Pos) /**< (PWM_CMR) Dead-Time PWMLx Output Inverted Mask */ +#define PWM_CMR_DTLI(value) (PWM_CMR_DTLI_Msk & ((value) << PWM_CMR_DTLI_Pos)) +#define PWM_CMR_PPM_Pos _U_(19) /**< (PWM_CMR) Push-Pull Mode Position */ +#define PWM_CMR_PPM_Msk (_U_(0x1) << PWM_CMR_PPM_Pos) /**< (PWM_CMR) Push-Pull Mode Mask */ +#define PWM_CMR_PPM(value) (PWM_CMR_PPM_Msk & ((value) << PWM_CMR_PPM_Pos)) +#define PWM_CMR_Msk _U_(0x000F3F0F) /**< (PWM_CMR) Register Mask */ + + +/* -------- PWM_CDTY : (PWM Offset: 0x04) (R/W 32) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos _U_(0) /**< (PWM_CDTY) Channel Duty-Cycle Position */ +#define PWM_CDTY_CDTY_Msk (_U_(0xFFFFFF) << PWM_CDTY_CDTY_Pos) /**< (PWM_CDTY) Channel Duty-Cycle Mask */ +#define PWM_CDTY_CDTY(value) (PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)) +#define PWM_CDTY_Msk _U_(0x00FFFFFF) /**< (PWM_CDTY) Register Mask */ + + +/* -------- PWM_CDTYUPD : (PWM Offset: 0x08) ( /W 32) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos _U_(0) /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Position */ +#define PWM_CDTYUPD_CDTYUPD_Msk (_U_(0xFFFFFF) << PWM_CDTYUPD_CDTYUPD_Pos) /**< (PWM_CDTYUPD) Channel Duty-Cycle Update Mask */ +#define PWM_CDTYUPD_CDTYUPD(value) (PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)) +#define PWM_CDTYUPD_Msk _U_(0x00FFFFFF) /**< (PWM_CDTYUPD) Register Mask */ + + +/* -------- PWM_CPRD : (PWM Offset: 0x0C) (R/W 32) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos _U_(0) /**< (PWM_CPRD) Channel Period Position */ +#define PWM_CPRD_CPRD_Msk (_U_(0xFFFFFF) << PWM_CPRD_CPRD_Pos) /**< (PWM_CPRD) Channel Period Mask */ +#define PWM_CPRD_CPRD(value) (PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)) +#define PWM_CPRD_Msk _U_(0x00FFFFFF) /**< (PWM_CPRD) Register Mask */ + + +/* -------- PWM_CPRDUPD : (PWM Offset: 0x10) ( /W 32) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos _U_(0) /**< (PWM_CPRDUPD) Channel Period Update Position */ +#define PWM_CPRDUPD_CPRDUPD_Msk (_U_(0xFFFFFF) << PWM_CPRDUPD_CPRDUPD_Pos) /**< (PWM_CPRDUPD) Channel Period Update Mask */ +#define PWM_CPRDUPD_CPRDUPD(value) (PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)) +#define PWM_CPRDUPD_Msk _U_(0x00FFFFFF) /**< (PWM_CPRDUPD) Register Mask */ + + +/* -------- PWM_CCNT : (PWM Offset: 0x14) ( R/ 32) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos _U_(0) /**< (PWM_CCNT) Channel Counter Register Position */ +#define PWM_CCNT_CNT_Msk (_U_(0xFFFFFF) << PWM_CCNT_CNT_Pos) /**< (PWM_CCNT) Channel Counter Register Mask */ +#define PWM_CCNT_CNT(value) (PWM_CCNT_CNT_Msk & ((value) << PWM_CCNT_CNT_Pos)) +#define PWM_CCNT_Msk _U_(0x00FFFFFF) /**< (PWM_CCNT) Register Mask */ + + +/* -------- PWM_DT : (PWM Offset: 0x18) (R/W 32) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos _U_(0) /**< (PWM_DT) Dead-Time Value for PWMHx Output Position */ +#define PWM_DT_DTH_Msk (_U_(0xFFFF) << PWM_DT_DTH_Pos) /**< (PWM_DT) Dead-Time Value for PWMHx Output Mask */ +#define PWM_DT_DTH(value) (PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)) +#define PWM_DT_DTL_Pos _U_(16) /**< (PWM_DT) Dead-Time Value for PWMLx Output Position */ +#define PWM_DT_DTL_Msk (_U_(0xFFFF) << PWM_DT_DTL_Pos) /**< (PWM_DT) Dead-Time Value for PWMLx Output Mask */ +#define PWM_DT_DTL(value) (PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)) +#define PWM_DT_Msk _U_(0xFFFFFFFF) /**< (PWM_DT) Register Mask */ + + +/* -------- PWM_DTUPD : (PWM Offset: 0x1C) ( /W 32) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos _U_(0) /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Position */ +#define PWM_DTUPD_DTHUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTHUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMHx Output Mask */ +#define PWM_DTUPD_DTHUPD(value) (PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)) +#define PWM_DTUPD_DTLUPD_Pos _U_(16) /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Position */ +#define PWM_DTUPD_DTLUPD_Msk (_U_(0xFFFF) << PWM_DTUPD_DTLUPD_Pos) /**< (PWM_DTUPD) Dead-Time Value Update for PWMLx Output Mask */ +#define PWM_DTUPD_DTLUPD(value) (PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)) +#define PWM_DTUPD_Msk _U_(0xFFFFFFFF) /**< (PWM_DTUPD) Register Mask */ + + +/* -------- PWM_CMPV : (PWM Offset: 0x00) (R/W 32) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos _U_(0) /**< (PWM_CMPV) Comparison x Value Position */ +#define PWM_CMPV_CV_Msk (_U_(0xFFFFFF) << PWM_CMPV_CV_Pos) /**< (PWM_CMPV) Comparison x Value Mask */ +#define PWM_CMPV_CV(value) (PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)) +#define PWM_CMPV_CVM_Pos _U_(24) /**< (PWM_CMPV) Comparison x Value Mode Position */ +#define PWM_CMPV_CVM_Msk (_U_(0x1) << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Comparison x Value Mode Mask */ +#define PWM_CMPV_CVM(value) (PWM_CMPV_CVM_Msk & ((value) << PWM_CMPV_CVM_Pos)) +#define PWM_CMPV_CVM_COMPARE_AT_INCREMENT_Val _U_(0x0) /**< (PWM_CMPV) Compare when counter is incrementing */ +#define PWM_CMPV_CVM_COMPARE_AT_DECREMENT_Val _U_(0x1) /**< (PWM_CMPV) Compare when counter is decrementing */ +#define PWM_CMPV_CVM_COMPARE_AT_INCREMENT (PWM_CMPV_CVM_COMPARE_AT_INCREMENT_Val << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Compare when counter is incrementing Position */ +#define PWM_CMPV_CVM_COMPARE_AT_DECREMENT (PWM_CMPV_CVM_COMPARE_AT_DECREMENT_Val << PWM_CMPV_CVM_Pos) /**< (PWM_CMPV) Compare when counter is decrementing Position */ +#define PWM_CMPV_Msk _U_(0x01FFFFFF) /**< (PWM_CMPV) Register Mask */ + + +/* -------- PWM_CMPVUPD : (PWM Offset: 0x04) ( /W 32) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos _U_(0) /**< (PWM_CMPVUPD) Comparison x Value Update Position */ +#define PWM_CMPVUPD_CVUPD_Msk (_U_(0xFFFFFF) << PWM_CMPVUPD_CVUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Update Mask */ +#define PWM_CMPVUPD_CVUPD(value) (PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)) +#define PWM_CMPVUPD_CVMUPD_Pos _U_(24) /**< (PWM_CMPVUPD) Comparison x Value Mode Update Position */ +#define PWM_CMPVUPD_CVMUPD_Msk (_U_(0x1) << PWM_CMPVUPD_CVMUPD_Pos) /**< (PWM_CMPVUPD) Comparison x Value Mode Update Mask */ +#define PWM_CMPVUPD_CVMUPD(value) (PWM_CMPVUPD_CVMUPD_Msk & ((value) << PWM_CMPVUPD_CVMUPD_Pos)) +#define PWM_CMPVUPD_Msk _U_(0x01FFFFFF) /**< (PWM_CMPVUPD) Register Mask */ + + +/* -------- PWM_CMPM : (PWM Offset: 0x08) (R/W 32) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN_Pos _U_(0) /**< (PWM_CMPM) Comparison x Enable Position */ +#define PWM_CMPM_CEN_Msk (_U_(0x1) << PWM_CMPM_CEN_Pos) /**< (PWM_CMPM) Comparison x Enable Mask */ +#define PWM_CMPM_CEN(value) (PWM_CMPM_CEN_Msk & ((value) << PWM_CMPM_CEN_Pos)) +#define PWM_CMPM_CTR_Pos _U_(4) /**< (PWM_CMPM) Comparison x Trigger Position */ +#define PWM_CMPM_CTR_Msk (_U_(0xF) << PWM_CMPM_CTR_Pos) /**< (PWM_CMPM) Comparison x Trigger Mask */ +#define PWM_CMPM_CTR(value) (PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)) +#define PWM_CMPM_CPR_Pos _U_(8) /**< (PWM_CMPM) Comparison x Period Position */ +#define PWM_CMPM_CPR_Msk (_U_(0xF) << PWM_CMPM_CPR_Pos) /**< (PWM_CMPM) Comparison x Period Mask */ +#define PWM_CMPM_CPR(value) (PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)) +#define PWM_CMPM_CPRCNT_Pos _U_(12) /**< (PWM_CMPM) Comparison x Period Counter Position */ +#define PWM_CMPM_CPRCNT_Msk (_U_(0xF) << PWM_CMPM_CPRCNT_Pos) /**< (PWM_CMPM) Comparison x Period Counter Mask */ +#define PWM_CMPM_CPRCNT(value) (PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)) +#define PWM_CMPM_CUPR_Pos _U_(16) /**< (PWM_CMPM) Comparison x Update Period Position */ +#define PWM_CMPM_CUPR_Msk (_U_(0xF) << PWM_CMPM_CUPR_Pos) /**< (PWM_CMPM) Comparison x Update Period Mask */ +#define PWM_CMPM_CUPR(value) (PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)) +#define PWM_CMPM_CUPRCNT_Pos _U_(20) /**< (PWM_CMPM) Comparison x Update Period Counter Position */ +#define PWM_CMPM_CUPRCNT_Msk (_U_(0xF) << PWM_CMPM_CUPRCNT_Pos) /**< (PWM_CMPM) Comparison x Update Period Counter Mask */ +#define PWM_CMPM_CUPRCNT(value) (PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)) +#define PWM_CMPM_Msk _U_(0x00FFFFF1) /**< (PWM_CMPM) Register Mask */ + + +/* -------- PWM_CMPMUPD : (PWM Offset: 0x0C) ( /W 32) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD_Pos _U_(0) /**< (PWM_CMPMUPD) Comparison x Enable Update Position */ +#define PWM_CMPMUPD_CENUPD_Msk (_U_(0x1) << PWM_CMPMUPD_CENUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Enable Update Mask */ +#define PWM_CMPMUPD_CENUPD(value) (PWM_CMPMUPD_CENUPD_Msk & ((value) << PWM_CMPMUPD_CENUPD_Pos)) +#define PWM_CMPMUPD_CTRUPD_Pos _U_(4) /**< (PWM_CMPMUPD) Comparison x Trigger Update Position */ +#define PWM_CMPMUPD_CTRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CTRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Trigger Update Mask */ +#define PWM_CMPMUPD_CTRUPD(value) (PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)) +#define PWM_CMPMUPD_CPRUPD_Pos _U_(8) /**< (PWM_CMPMUPD) Comparison x Period Update Position */ +#define PWM_CMPMUPD_CPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Period Update Mask */ +#define PWM_CMPMUPD_CPRUPD(value) (PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)) +#define PWM_CMPMUPD_CUPRUPD_Pos _U_(16) /**< (PWM_CMPMUPD) Comparison x Update Period Update Position */ +#define PWM_CMPMUPD_CUPRUPD_Msk (_U_(0xF) << PWM_CMPMUPD_CUPRUPD_Pos) /**< (PWM_CMPMUPD) Comparison x Update Period Update Mask */ +#define PWM_CMPMUPD_CUPRUPD(value) (PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)) +#define PWM_CMPMUPD_Msk _U_(0x000F0FF1) /**< (PWM_CMPMUPD) Register Mask */ + + +/* -------- PWM_CLK : (PWM Offset: 0x00) (R/W 32) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos _U_(0) /**< (PWM_CLK) CLKA Divide Factor Position */ +#define PWM_CLK_DIVA_Msk (_U_(0xFF) << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA Divide Factor Mask */ +#define PWM_CLK_DIVA(value) (PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)) +#define PWM_CLK_DIVA_CLKA_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA_Val _U_(0x1) /**< (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_DIVA_CLKA_POFF (PWM_CLK_DIVA_CLKA_POFF_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is turned off Position */ +#define PWM_CLK_DIVA_PREA (PWM_CLK_DIVA_PREA_Val << PWM_CLK_DIVA_Pos) /**< (PWM_CLK) CLKA clock is clock selected by PREA Position */ +#define PWM_CLK_PREA_Pos _U_(8) /**< (PWM_CLK) CLKA Source Clock Selection Position */ +#define PWM_CLK_PREA_Msk (_U_(0xF) << PWM_CLK_PREA_Pos) /**< (PWM_CLK) CLKA Source Clock Selection Mask */ +#define PWM_CLK_PREA(value) (PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)) +#define PWM_CLK_PREA_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREA_CLK (PWM_CLK_PREA_CLK_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREA_CLK_DIV2 (PWM_CLK_PREA_CLK_DIV2_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREA_CLK_DIV4 (PWM_CLK_PREA_CLK_DIV4_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREA_CLK_DIV8 (PWM_CLK_PREA_CLK_DIV8_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREA_CLK_DIV16 (PWM_CLK_PREA_CLK_DIV16_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREA_CLK_DIV32 (PWM_CLK_PREA_CLK_DIV32_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREA_CLK_DIV64 (PWM_CLK_PREA_CLK_DIV64_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREA_CLK_DIV128 (PWM_CLK_PREA_CLK_DIV128_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREA_CLK_DIV256 (PWM_CLK_PREA_CLK_DIV256_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREA_CLK_DIV512 (PWM_CLK_PREA_CLK_DIV512_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREA_CLK_DIV1024 (PWM_CLK_PREA_CLK_DIV1024_Val << PWM_CLK_PREA_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_DIVB_Pos _U_(16) /**< (PWM_CLK) CLKB Divide Factor Position */ +#define PWM_CLK_DIVB_Msk (_U_(0xFF) << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB Divide Factor Mask */ +#define PWM_CLK_DIVB(value) (PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)) +#define PWM_CLK_DIVB_CLKB_POFF_Val _U_(0x0) /**< (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB_Val _U_(0x1) /**< (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_DIVB_CLKB_POFF (PWM_CLK_DIVB_CLKB_POFF_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is turned off Position */ +#define PWM_CLK_DIVB_PREB (PWM_CLK_DIVB_PREB_Val << PWM_CLK_DIVB_Pos) /**< (PWM_CLK) CLKB clock is clock selected by PREB Position */ +#define PWM_CLK_PREB_Pos _U_(24) /**< (PWM_CLK) CLKB Source Clock Selection Position */ +#define PWM_CLK_PREB_Msk (_U_(0xF) << PWM_CLK_PREB_Pos) /**< (PWM_CLK) CLKB Source Clock Selection Mask */ +#define PWM_CLK_PREB(value) (PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)) +#define PWM_CLK_PREB_CLK_Val _U_(0x0) /**< (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2_Val _U_(0x1) /**< (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4_Val _U_(0x2) /**< (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8_Val _U_(0x3) /**< (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16_Val _U_(0x4) /**< (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32_Val _U_(0x5) /**< (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64_Val _U_(0x6) /**< (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128_Val _U_(0x7) /**< (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256_Val _U_(0x8) /**< (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512_Val _U_(0x9) /**< (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024_Val _U_(0xA) /**< (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_PREB_CLK (PWM_CLK_PREB_CLK_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock Position */ +#define PWM_CLK_PREB_CLK_DIV2 (PWM_CLK_PREB_CLK_DIV2_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/2 Position */ +#define PWM_CLK_PREB_CLK_DIV4 (PWM_CLK_PREB_CLK_DIV4_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/4 Position */ +#define PWM_CLK_PREB_CLK_DIV8 (PWM_CLK_PREB_CLK_DIV8_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/8 Position */ +#define PWM_CLK_PREB_CLK_DIV16 (PWM_CLK_PREB_CLK_DIV16_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/16 Position */ +#define PWM_CLK_PREB_CLK_DIV32 (PWM_CLK_PREB_CLK_DIV32_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/32 Position */ +#define PWM_CLK_PREB_CLK_DIV64 (PWM_CLK_PREB_CLK_DIV64_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/64 Position */ +#define PWM_CLK_PREB_CLK_DIV128 (PWM_CLK_PREB_CLK_DIV128_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/128 Position */ +#define PWM_CLK_PREB_CLK_DIV256 (PWM_CLK_PREB_CLK_DIV256_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/256 Position */ +#define PWM_CLK_PREB_CLK_DIV512 (PWM_CLK_PREB_CLK_DIV512_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/512 Position */ +#define PWM_CLK_PREB_CLK_DIV1024 (PWM_CLK_PREB_CLK_DIV1024_Val << PWM_CLK_PREB_Pos) /**< (PWM_CLK) Peripheral clock/1024 Position */ +#define PWM_CLK_Msk _U_(0x0FFF0FFF) /**< (PWM_CLK) Register Mask */ + + +/* -------- PWM_ENA : (PWM Offset: 0x04) ( /W 32) PWM Enable Register -------- */ +#define PWM_ENA_CHID0_Pos _U_(0) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID0_Msk (_U_(0x1) << PWM_ENA_CHID0_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID0(value) (PWM_ENA_CHID0_Msk & ((value) << PWM_ENA_CHID0_Pos)) +#define PWM_ENA_CHID1_Pos _U_(1) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID1_Msk (_U_(0x1) << PWM_ENA_CHID1_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID1(value) (PWM_ENA_CHID1_Msk & ((value) << PWM_ENA_CHID1_Pos)) +#define PWM_ENA_CHID2_Pos _U_(2) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID2_Msk (_U_(0x1) << PWM_ENA_CHID2_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID2(value) (PWM_ENA_CHID2_Msk & ((value) << PWM_ENA_CHID2_Pos)) +#define PWM_ENA_CHID3_Pos _U_(3) /**< (PWM_ENA) Channel ID Position */ +#define PWM_ENA_CHID3_Msk (_U_(0x1) << PWM_ENA_CHID3_Pos) /**< (PWM_ENA) Channel ID Mask */ +#define PWM_ENA_CHID3(value) (PWM_ENA_CHID3_Msk & ((value) << PWM_ENA_CHID3_Pos)) +#define PWM_ENA_Msk _U_(0x0000000F) /**< (PWM_ENA) Register Mask */ + +#define PWM_ENA_CHID_Pos _U_(0) /**< (PWM_ENA Position) Channel ID */ +#define PWM_ENA_CHID_Msk (_U_(0xF) << PWM_ENA_CHID_Pos) /**< (PWM_ENA Mask) CHID */ +#define PWM_ENA_CHID(value) (PWM_ENA_CHID_Msk & ((value) << PWM_ENA_CHID_Pos)) + +/* -------- PWM_DIS : (PWM Offset: 0x08) ( /W 32) PWM Disable Register -------- */ +#define PWM_DIS_CHID0_Pos _U_(0) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID0_Msk (_U_(0x1) << PWM_DIS_CHID0_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID0(value) (PWM_DIS_CHID0_Msk & ((value) << PWM_DIS_CHID0_Pos)) +#define PWM_DIS_CHID1_Pos _U_(1) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID1_Msk (_U_(0x1) << PWM_DIS_CHID1_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID1(value) (PWM_DIS_CHID1_Msk & ((value) << PWM_DIS_CHID1_Pos)) +#define PWM_DIS_CHID2_Pos _U_(2) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID2_Msk (_U_(0x1) << PWM_DIS_CHID2_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID2(value) (PWM_DIS_CHID2_Msk & ((value) << PWM_DIS_CHID2_Pos)) +#define PWM_DIS_CHID3_Pos _U_(3) /**< (PWM_DIS) Channel ID Position */ +#define PWM_DIS_CHID3_Msk (_U_(0x1) << PWM_DIS_CHID3_Pos) /**< (PWM_DIS) Channel ID Mask */ +#define PWM_DIS_CHID3(value) (PWM_DIS_CHID3_Msk & ((value) << PWM_DIS_CHID3_Pos)) +#define PWM_DIS_Msk _U_(0x0000000F) /**< (PWM_DIS) Register Mask */ + +#define PWM_DIS_CHID_Pos _U_(0) /**< (PWM_DIS Position) Channel ID */ +#define PWM_DIS_CHID_Msk (_U_(0xF) << PWM_DIS_CHID_Pos) /**< (PWM_DIS Mask) CHID */ +#define PWM_DIS_CHID(value) (PWM_DIS_CHID_Msk & ((value) << PWM_DIS_CHID_Pos)) + +/* -------- PWM_SR : (PWM Offset: 0x0C) ( R/ 32) PWM Status Register -------- */ +#define PWM_SR_CHID0_Pos _U_(0) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID0_Msk (_U_(0x1) << PWM_SR_CHID0_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID0(value) (PWM_SR_CHID0_Msk & ((value) << PWM_SR_CHID0_Pos)) +#define PWM_SR_CHID1_Pos _U_(1) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID1_Msk (_U_(0x1) << PWM_SR_CHID1_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID1(value) (PWM_SR_CHID1_Msk & ((value) << PWM_SR_CHID1_Pos)) +#define PWM_SR_CHID2_Pos _U_(2) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID2_Msk (_U_(0x1) << PWM_SR_CHID2_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID2(value) (PWM_SR_CHID2_Msk & ((value) << PWM_SR_CHID2_Pos)) +#define PWM_SR_CHID3_Pos _U_(3) /**< (PWM_SR) Channel ID Position */ +#define PWM_SR_CHID3_Msk (_U_(0x1) << PWM_SR_CHID3_Pos) /**< (PWM_SR) Channel ID Mask */ +#define PWM_SR_CHID3(value) (PWM_SR_CHID3_Msk & ((value) << PWM_SR_CHID3_Pos)) +#define PWM_SR_Msk _U_(0x0000000F) /**< (PWM_SR) Register Mask */ + +#define PWM_SR_CHID_Pos _U_(0) /**< (PWM_SR Position) Channel ID */ +#define PWM_SR_CHID_Msk (_U_(0xF) << PWM_SR_CHID_Pos) /**< (PWM_SR Mask) CHID */ +#define PWM_SR_CHID(value) (PWM_SR_CHID_Msk & ((value) << PWM_SR_CHID_Pos)) + +/* -------- PWM_IER1 : (PWM Offset: 0x10) ( /W 32) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0_Pos _U_(0) /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_CHID0_Msk (_U_(0x1) << PWM_IER1_CHID0_Pos) /**< (PWM_IER1) Counter Event on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_CHID0(value) (PWM_IER1_CHID0_Msk & ((value) << PWM_IER1_CHID0_Pos)) +#define PWM_IER1_CHID1_Pos _U_(1) /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_CHID1_Msk (_U_(0x1) << PWM_IER1_CHID1_Pos) /**< (PWM_IER1) Counter Event on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_CHID1(value) (PWM_IER1_CHID1_Msk & ((value) << PWM_IER1_CHID1_Pos)) +#define PWM_IER1_CHID2_Pos _U_(2) /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_CHID2_Msk (_U_(0x1) << PWM_IER1_CHID2_Pos) /**< (PWM_IER1) Counter Event on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_CHID2(value) (PWM_IER1_CHID2_Msk & ((value) << PWM_IER1_CHID2_Pos)) +#define PWM_IER1_CHID3_Pos _U_(3) /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_CHID3_Msk (_U_(0x1) << PWM_IER1_CHID3_Pos) /**< (PWM_IER1) Counter Event on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_CHID3(value) (PWM_IER1_CHID3_Msk & ((value) << PWM_IER1_CHID3_Pos)) +#define PWM_IER1_FCHID0_Pos _U_(16) /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Position */ +#define PWM_IER1_FCHID0_Msk (_U_(0x1) << PWM_IER1_FCHID0_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable Mask */ +#define PWM_IER1_FCHID0(value) (PWM_IER1_FCHID0_Msk & ((value) << PWM_IER1_FCHID0_Pos)) +#define PWM_IER1_FCHID1_Pos _U_(17) /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Position */ +#define PWM_IER1_FCHID1_Msk (_U_(0x1) << PWM_IER1_FCHID1_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable Mask */ +#define PWM_IER1_FCHID1(value) (PWM_IER1_FCHID1_Msk & ((value) << PWM_IER1_FCHID1_Pos)) +#define PWM_IER1_FCHID2_Pos _U_(18) /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Position */ +#define PWM_IER1_FCHID2_Msk (_U_(0x1) << PWM_IER1_FCHID2_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable Mask */ +#define PWM_IER1_FCHID2(value) (PWM_IER1_FCHID2_Msk & ((value) << PWM_IER1_FCHID2_Pos)) +#define PWM_IER1_FCHID3_Pos _U_(19) /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Position */ +#define PWM_IER1_FCHID3_Msk (_U_(0x1) << PWM_IER1_FCHID3_Pos) /**< (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable Mask */ +#define PWM_IER1_FCHID3(value) (PWM_IER1_FCHID3_Msk & ((value) << PWM_IER1_FCHID3_Pos)) +#define PWM_IER1_Msk _U_(0x000F000F) /**< (PWM_IER1) Register Mask */ + +#define PWM_IER1_CHID_Pos _U_(0) /**< (PWM_IER1 Position) Counter Event on Channel x Interrupt Enable */ +#define PWM_IER1_CHID_Msk (_U_(0xF) << PWM_IER1_CHID_Pos) /**< (PWM_IER1 Mask) CHID */ +#define PWM_IER1_CHID(value) (PWM_IER1_CHID_Msk & ((value) << PWM_IER1_CHID_Pos)) +#define PWM_IER1_FCHID_Pos _U_(16) /**< (PWM_IER1 Position) Fault Protection Trigger on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID_Msk (_U_(0xF) << PWM_IER1_FCHID_Pos) /**< (PWM_IER1 Mask) FCHID */ +#define PWM_IER1_FCHID(value) (PWM_IER1_FCHID_Msk & ((value) << PWM_IER1_FCHID_Pos)) + +/* -------- PWM_IDR1 : (PWM Offset: 0x14) ( /W 32) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0_Pos _U_(0) /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_CHID0_Msk (_U_(0x1) << PWM_IDR1_CHID0_Pos) /**< (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_CHID0(value) (PWM_IDR1_CHID0_Msk & ((value) << PWM_IDR1_CHID0_Pos)) +#define PWM_IDR1_CHID1_Pos _U_(1) /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_CHID1_Msk (_U_(0x1) << PWM_IDR1_CHID1_Pos) /**< (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_CHID1(value) (PWM_IDR1_CHID1_Msk & ((value) << PWM_IDR1_CHID1_Pos)) +#define PWM_IDR1_CHID2_Pos _U_(2) /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_CHID2_Msk (_U_(0x1) << PWM_IDR1_CHID2_Pos) /**< (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_CHID2(value) (PWM_IDR1_CHID2_Msk & ((value) << PWM_IDR1_CHID2_Pos)) +#define PWM_IDR1_CHID3_Pos _U_(3) /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_CHID3_Msk (_U_(0x1) << PWM_IDR1_CHID3_Pos) /**< (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_CHID3(value) (PWM_IDR1_CHID3_Msk & ((value) << PWM_IDR1_CHID3_Pos)) +#define PWM_IDR1_FCHID0_Pos _U_(16) /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Position */ +#define PWM_IDR1_FCHID0_Msk (_U_(0x1) << PWM_IDR1_FCHID0_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID0(value) (PWM_IDR1_FCHID0_Msk & ((value) << PWM_IDR1_FCHID0_Pos)) +#define PWM_IDR1_FCHID1_Pos _U_(17) /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Position */ +#define PWM_IDR1_FCHID1_Msk (_U_(0x1) << PWM_IDR1_FCHID1_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID1(value) (PWM_IDR1_FCHID1_Msk & ((value) << PWM_IDR1_FCHID1_Pos)) +#define PWM_IDR1_FCHID2_Pos _U_(18) /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Position */ +#define PWM_IDR1_FCHID2_Msk (_U_(0x1) << PWM_IDR1_FCHID2_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID2(value) (PWM_IDR1_FCHID2_Msk & ((value) << PWM_IDR1_FCHID2_Pos)) +#define PWM_IDR1_FCHID3_Pos _U_(19) /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Position */ +#define PWM_IDR1_FCHID3_Msk (_U_(0x1) << PWM_IDR1_FCHID3_Pos) /**< (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable Mask */ +#define PWM_IDR1_FCHID3(value) (PWM_IDR1_FCHID3_Msk & ((value) << PWM_IDR1_FCHID3_Pos)) +#define PWM_IDR1_Msk _U_(0x000F000F) /**< (PWM_IDR1) Register Mask */ + +#define PWM_IDR1_CHID_Pos _U_(0) /**< (PWM_IDR1 Position) Counter Event on Channel x Interrupt Disable */ +#define PWM_IDR1_CHID_Msk (_U_(0xF) << PWM_IDR1_CHID_Pos) /**< (PWM_IDR1 Mask) CHID */ +#define PWM_IDR1_CHID(value) (PWM_IDR1_CHID_Msk & ((value) << PWM_IDR1_CHID_Pos)) +#define PWM_IDR1_FCHID_Pos _U_(16) /**< (PWM_IDR1 Position) Fault Protection Trigger on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID_Msk (_U_(0xF) << PWM_IDR1_FCHID_Pos) /**< (PWM_IDR1 Mask) FCHID */ +#define PWM_IDR1_FCHID(value) (PWM_IDR1_FCHID_Msk & ((value) << PWM_IDR1_FCHID_Pos)) + +/* -------- PWM_IMR1 : (PWM Offset: 0x18) ( R/ 32) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0_Pos _U_(0) /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_CHID0_Msk (_U_(0x1) << PWM_IMR1_CHID0_Pos) /**< (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_CHID0(value) (PWM_IMR1_CHID0_Msk & ((value) << PWM_IMR1_CHID0_Pos)) +#define PWM_IMR1_CHID1_Pos _U_(1) /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_CHID1_Msk (_U_(0x1) << PWM_IMR1_CHID1_Pos) /**< (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_CHID1(value) (PWM_IMR1_CHID1_Msk & ((value) << PWM_IMR1_CHID1_Pos)) +#define PWM_IMR1_CHID2_Pos _U_(2) /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_CHID2_Msk (_U_(0x1) << PWM_IMR1_CHID2_Pos) /**< (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_CHID2(value) (PWM_IMR1_CHID2_Msk & ((value) << PWM_IMR1_CHID2_Pos)) +#define PWM_IMR1_CHID3_Pos _U_(3) /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_CHID3_Msk (_U_(0x1) << PWM_IMR1_CHID3_Pos) /**< (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_CHID3(value) (PWM_IMR1_CHID3_Msk & ((value) << PWM_IMR1_CHID3_Pos)) +#define PWM_IMR1_FCHID0_Pos _U_(16) /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Position */ +#define PWM_IMR1_FCHID0_Msk (_U_(0x1) << PWM_IMR1_FCHID0_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID0(value) (PWM_IMR1_FCHID0_Msk & ((value) << PWM_IMR1_FCHID0_Pos)) +#define PWM_IMR1_FCHID1_Pos _U_(17) /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Position */ +#define PWM_IMR1_FCHID1_Msk (_U_(0x1) << PWM_IMR1_FCHID1_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID1(value) (PWM_IMR1_FCHID1_Msk & ((value) << PWM_IMR1_FCHID1_Pos)) +#define PWM_IMR1_FCHID2_Pos _U_(18) /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Position */ +#define PWM_IMR1_FCHID2_Msk (_U_(0x1) << PWM_IMR1_FCHID2_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID2(value) (PWM_IMR1_FCHID2_Msk & ((value) << PWM_IMR1_FCHID2_Pos)) +#define PWM_IMR1_FCHID3_Pos _U_(19) /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Position */ +#define PWM_IMR1_FCHID3_Msk (_U_(0x1) << PWM_IMR1_FCHID3_Pos) /**< (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask Mask */ +#define PWM_IMR1_FCHID3(value) (PWM_IMR1_FCHID3_Msk & ((value) << PWM_IMR1_FCHID3_Pos)) +#define PWM_IMR1_Msk _U_(0x000F000F) /**< (PWM_IMR1) Register Mask */ + +#define PWM_IMR1_CHID_Pos _U_(0) /**< (PWM_IMR1 Position) Counter Event on Channel x Interrupt Mask */ +#define PWM_IMR1_CHID_Msk (_U_(0xF) << PWM_IMR1_CHID_Pos) /**< (PWM_IMR1 Mask) CHID */ +#define PWM_IMR1_CHID(value) (PWM_IMR1_CHID_Msk & ((value) << PWM_IMR1_CHID_Pos)) +#define PWM_IMR1_FCHID_Pos _U_(16) /**< (PWM_IMR1 Position) Fault Protection Trigger on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID_Msk (_U_(0xF) << PWM_IMR1_FCHID_Pos) /**< (PWM_IMR1 Mask) FCHID */ +#define PWM_IMR1_FCHID(value) (PWM_IMR1_FCHID_Msk & ((value) << PWM_IMR1_FCHID_Pos)) + +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) ( R/ 32) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0_Pos _U_(0) /**< (PWM_ISR1) Counter Event on Channel 0 Position */ +#define PWM_ISR1_CHID0_Msk (_U_(0x1) << PWM_ISR1_CHID0_Pos) /**< (PWM_ISR1) Counter Event on Channel 0 Mask */ +#define PWM_ISR1_CHID0(value) (PWM_ISR1_CHID0_Msk & ((value) << PWM_ISR1_CHID0_Pos)) +#define PWM_ISR1_CHID1_Pos _U_(1) /**< (PWM_ISR1) Counter Event on Channel 1 Position */ +#define PWM_ISR1_CHID1_Msk (_U_(0x1) << PWM_ISR1_CHID1_Pos) /**< (PWM_ISR1) Counter Event on Channel 1 Mask */ +#define PWM_ISR1_CHID1(value) (PWM_ISR1_CHID1_Msk & ((value) << PWM_ISR1_CHID1_Pos)) +#define PWM_ISR1_CHID2_Pos _U_(2) /**< (PWM_ISR1) Counter Event on Channel 2 Position */ +#define PWM_ISR1_CHID2_Msk (_U_(0x1) << PWM_ISR1_CHID2_Pos) /**< (PWM_ISR1) Counter Event on Channel 2 Mask */ +#define PWM_ISR1_CHID2(value) (PWM_ISR1_CHID2_Msk & ((value) << PWM_ISR1_CHID2_Pos)) +#define PWM_ISR1_CHID3_Pos _U_(3) /**< (PWM_ISR1) Counter Event on Channel 3 Position */ +#define PWM_ISR1_CHID3_Msk (_U_(0x1) << PWM_ISR1_CHID3_Pos) /**< (PWM_ISR1) Counter Event on Channel 3 Mask */ +#define PWM_ISR1_CHID3(value) (PWM_ISR1_CHID3_Msk & ((value) << PWM_ISR1_CHID3_Pos)) +#define PWM_ISR1_FCHID0_Pos _U_(16) /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Position */ +#define PWM_ISR1_FCHID0_Msk (_U_(0x1) << PWM_ISR1_FCHID0_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 0 Mask */ +#define PWM_ISR1_FCHID0(value) (PWM_ISR1_FCHID0_Msk & ((value) << PWM_ISR1_FCHID0_Pos)) +#define PWM_ISR1_FCHID1_Pos _U_(17) /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Position */ +#define PWM_ISR1_FCHID1_Msk (_U_(0x1) << PWM_ISR1_FCHID1_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 1 Mask */ +#define PWM_ISR1_FCHID1(value) (PWM_ISR1_FCHID1_Msk & ((value) << PWM_ISR1_FCHID1_Pos)) +#define PWM_ISR1_FCHID2_Pos _U_(18) /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Position */ +#define PWM_ISR1_FCHID2_Msk (_U_(0x1) << PWM_ISR1_FCHID2_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 2 Mask */ +#define PWM_ISR1_FCHID2(value) (PWM_ISR1_FCHID2_Msk & ((value) << PWM_ISR1_FCHID2_Pos)) +#define PWM_ISR1_FCHID3_Pos _U_(19) /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Position */ +#define PWM_ISR1_FCHID3_Msk (_U_(0x1) << PWM_ISR1_FCHID3_Pos) /**< (PWM_ISR1) Fault Protection Trigger on Channel 3 Mask */ +#define PWM_ISR1_FCHID3(value) (PWM_ISR1_FCHID3_Msk & ((value) << PWM_ISR1_FCHID3_Pos)) +#define PWM_ISR1_Msk _U_(0x000F000F) /**< (PWM_ISR1) Register Mask */ + +#define PWM_ISR1_CHID_Pos _U_(0) /**< (PWM_ISR1 Position) Counter Event on Channel x */ +#define PWM_ISR1_CHID_Msk (_U_(0xF) << PWM_ISR1_CHID_Pos) /**< (PWM_ISR1 Mask) CHID */ +#define PWM_ISR1_CHID(value) (PWM_ISR1_CHID_Msk & ((value) << PWM_ISR1_CHID_Pos)) +#define PWM_ISR1_FCHID_Pos _U_(16) /**< (PWM_ISR1 Position) Fault Protection Trigger on Channel 3 */ +#define PWM_ISR1_FCHID_Msk (_U_(0xF) << PWM_ISR1_FCHID_Pos) /**< (PWM_ISR1 Mask) FCHID */ +#define PWM_ISR1_FCHID(value) (PWM_ISR1_FCHID_Msk & ((value) << PWM_ISR1_FCHID_Pos)) + +/* -------- PWM_SCM : (PWM Offset: 0x20) (R/W 32) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0_Pos _U_(0) /**< (PWM_SCM) Synchronous Channel 0 Position */ +#define PWM_SCM_SYNC0_Msk (_U_(0x1) << PWM_SCM_SYNC0_Pos) /**< (PWM_SCM) Synchronous Channel 0 Mask */ +#define PWM_SCM_SYNC0(value) (PWM_SCM_SYNC0_Msk & ((value) << PWM_SCM_SYNC0_Pos)) +#define PWM_SCM_SYNC1_Pos _U_(1) /**< (PWM_SCM) Synchronous Channel 1 Position */ +#define PWM_SCM_SYNC1_Msk (_U_(0x1) << PWM_SCM_SYNC1_Pos) /**< (PWM_SCM) Synchronous Channel 1 Mask */ +#define PWM_SCM_SYNC1(value) (PWM_SCM_SYNC1_Msk & ((value) << PWM_SCM_SYNC1_Pos)) +#define PWM_SCM_SYNC2_Pos _U_(2) /**< (PWM_SCM) Synchronous Channel 2 Position */ +#define PWM_SCM_SYNC2_Msk (_U_(0x1) << PWM_SCM_SYNC2_Pos) /**< (PWM_SCM) Synchronous Channel 2 Mask */ +#define PWM_SCM_SYNC2(value) (PWM_SCM_SYNC2_Msk & ((value) << PWM_SCM_SYNC2_Pos)) +#define PWM_SCM_SYNC3_Pos _U_(3) /**< (PWM_SCM) Synchronous Channel 3 Position */ +#define PWM_SCM_SYNC3_Msk (_U_(0x1) << PWM_SCM_SYNC3_Pos) /**< (PWM_SCM) Synchronous Channel 3 Mask */ +#define PWM_SCM_SYNC3(value) (PWM_SCM_SYNC3_Msk & ((value) << PWM_SCM_SYNC3_Pos)) +#define PWM_SCM_UPDM_Pos _U_(16) /**< (PWM_SCM) Synchronous Channels Update Mode Position */ +#define PWM_SCM_UPDM_Msk (_U_(0x3) << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Synchronous Channels Update Mode Mask */ +#define PWM_SCM_UPDM(value) (PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)) +#define PWM_SCM_UPDM_MODE0_Val _U_(0x0) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1_Val _U_(0x1) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2_Val _U_(0x2) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE0 (PWM_SCM_UPDM_MODE0_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE1 (PWM_SCM_UPDM_MODE1_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels Position */ +#define PWM_SCM_UPDM_MODE2 (PWM_SCM_UPDM_MODE2_Val << PWM_SCM_UPDM_Pos) /**< (PWM_SCM) Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels Position */ +#define PWM_SCM_PTRM_Pos _U_(20) /**< (PWM_SCM) DMA Controller Transfer Request Mode Position */ +#define PWM_SCM_PTRM_Msk (_U_(0x1) << PWM_SCM_PTRM_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Mode Mask */ +#define PWM_SCM_PTRM(value) (PWM_SCM_PTRM_Msk & ((value) << PWM_SCM_PTRM_Pos)) +#define PWM_SCM_PTRCS_Pos _U_(21) /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Position */ +#define PWM_SCM_PTRCS_Msk (_U_(0x7) << PWM_SCM_PTRCS_Pos) /**< (PWM_SCM) DMA Controller Transfer Request Comparison Selection Mask */ +#define PWM_SCM_PTRCS(value) (PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)) +#define PWM_SCM_Msk _U_(0x00F3000F) /**< (PWM_SCM) Register Mask */ + +#define PWM_SCM_SYNC_Pos _U_(0) /**< (PWM_SCM Position) Synchronous Channel x */ +#define PWM_SCM_SYNC_Msk (_U_(0xF) << PWM_SCM_SYNC_Pos) /**< (PWM_SCM Mask) SYNC */ +#define PWM_SCM_SYNC(value) (PWM_SCM_SYNC_Msk & ((value) << PWM_SCM_SYNC_Pos)) + +/* -------- PWM_DMAR : (PWM Offset: 0x24) ( /W 32) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos _U_(0) /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Position */ +#define PWM_DMAR_DMADUTY_Msk (_U_(0xFFFFFF) << PWM_DMAR_DMADUTY_Pos) /**< (PWM_DMAR) Duty-Cycle Holding Register for DMA Access Mask */ +#define PWM_DMAR_DMADUTY(value) (PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)) +#define PWM_DMAR_Msk _U_(0x00FFFFFF) /**< (PWM_DMAR) Register Mask */ + + +/* -------- PWM_SCUC : (PWM Offset: 0x28) (R/W 32) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK_Pos _U_(0) /**< (PWM_SCUC) Synchronous Channels Update Unlock Position */ +#define PWM_SCUC_UPDULOCK_Msk (_U_(0x1) << PWM_SCUC_UPDULOCK_Pos) /**< (PWM_SCUC) Synchronous Channels Update Unlock Mask */ +#define PWM_SCUC_UPDULOCK(value) (PWM_SCUC_UPDULOCK_Msk & ((value) << PWM_SCUC_UPDULOCK_Pos)) +#define PWM_SCUC_Msk _U_(0x00000001) /**< (PWM_SCUC) Register Mask */ + + +/* -------- PWM_SCUP : (PWM Offset: 0x2C) (R/W 32) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos _U_(0) /**< (PWM_SCUP) Update Period Position */ +#define PWM_SCUP_UPR_Msk (_U_(0xF) << PWM_SCUP_UPR_Pos) /**< (PWM_SCUP) Update Period Mask */ +#define PWM_SCUP_UPR(value) (PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)) +#define PWM_SCUP_UPRCNT_Pos _U_(4) /**< (PWM_SCUP) Update Period Counter Position */ +#define PWM_SCUP_UPRCNT_Msk (_U_(0xF) << PWM_SCUP_UPRCNT_Pos) /**< (PWM_SCUP) Update Period Counter Mask */ +#define PWM_SCUP_UPRCNT(value) (PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)) +#define PWM_SCUP_Msk _U_(0x000000FF) /**< (PWM_SCUP) Register Mask */ + + +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) ( /W 32) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos _U_(0) /**< (PWM_SCUPUPD) Update Period Update Position */ +#define PWM_SCUPUPD_UPRUPD_Msk (_U_(0xF) << PWM_SCUPUPD_UPRUPD_Pos) /**< (PWM_SCUPUPD) Update Period Update Mask */ +#define PWM_SCUPUPD_UPRUPD(value) (PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)) +#define PWM_SCUPUPD_Msk _U_(0x0000000F) /**< (PWM_SCUPUPD) Register Mask */ + + +/* -------- PWM_IER2 : (PWM Offset: 0x34) ( /W 32) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY_Pos _U_(0) /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Position */ +#define PWM_IER2_WRDY_Msk (_U_(0x1) << PWM_IER2_WRDY_Pos) /**< (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable Mask */ +#define PWM_IER2_WRDY(value) (PWM_IER2_WRDY_Msk & ((value) << PWM_IER2_WRDY_Pos)) +#define PWM_IER2_UNRE_Pos _U_(3) /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Position */ +#define PWM_IER2_UNRE_Msk (_U_(0x1) << PWM_IER2_UNRE_Pos) /**< (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable Mask */ +#define PWM_IER2_UNRE(value) (PWM_IER2_UNRE_Msk & ((value) << PWM_IER2_UNRE_Pos)) +#define PWM_IER2_CMPM0_Pos _U_(8) /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM0_Msk (_U_(0x1) << PWM_IER2_CMPM0_Pos) /**< (PWM_IER2) Comparison 0 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM0(value) (PWM_IER2_CMPM0_Msk & ((value) << PWM_IER2_CMPM0_Pos)) +#define PWM_IER2_CMPM1_Pos _U_(9) /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM1_Msk (_U_(0x1) << PWM_IER2_CMPM1_Pos) /**< (PWM_IER2) Comparison 1 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM1(value) (PWM_IER2_CMPM1_Msk & ((value) << PWM_IER2_CMPM1_Pos)) +#define PWM_IER2_CMPM2_Pos _U_(10) /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM2_Msk (_U_(0x1) << PWM_IER2_CMPM2_Pos) /**< (PWM_IER2) Comparison 2 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM2(value) (PWM_IER2_CMPM2_Msk & ((value) << PWM_IER2_CMPM2_Pos)) +#define PWM_IER2_CMPM3_Pos _U_(11) /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM3_Msk (_U_(0x1) << PWM_IER2_CMPM3_Pos) /**< (PWM_IER2) Comparison 3 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM3(value) (PWM_IER2_CMPM3_Msk & ((value) << PWM_IER2_CMPM3_Pos)) +#define PWM_IER2_CMPM4_Pos _U_(12) /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM4_Msk (_U_(0x1) << PWM_IER2_CMPM4_Pos) /**< (PWM_IER2) Comparison 4 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM4(value) (PWM_IER2_CMPM4_Msk & ((value) << PWM_IER2_CMPM4_Pos)) +#define PWM_IER2_CMPM5_Pos _U_(13) /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM5_Msk (_U_(0x1) << PWM_IER2_CMPM5_Pos) /**< (PWM_IER2) Comparison 5 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM5(value) (PWM_IER2_CMPM5_Msk & ((value) << PWM_IER2_CMPM5_Pos)) +#define PWM_IER2_CMPM6_Pos _U_(14) /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM6_Msk (_U_(0x1) << PWM_IER2_CMPM6_Pos) /**< (PWM_IER2) Comparison 6 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM6(value) (PWM_IER2_CMPM6_Msk & ((value) << PWM_IER2_CMPM6_Pos)) +#define PWM_IER2_CMPM7_Pos _U_(15) /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Position */ +#define PWM_IER2_CMPM7_Msk (_U_(0x1) << PWM_IER2_CMPM7_Pos) /**< (PWM_IER2) Comparison 7 Match Interrupt Enable Mask */ +#define PWM_IER2_CMPM7(value) (PWM_IER2_CMPM7_Msk & ((value) << PWM_IER2_CMPM7_Pos)) +#define PWM_IER2_CMPU0_Pos _U_(16) /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU0_Msk (_U_(0x1) << PWM_IER2_CMPU0_Pos) /**< (PWM_IER2) Comparison 0 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU0(value) (PWM_IER2_CMPU0_Msk & ((value) << PWM_IER2_CMPU0_Pos)) +#define PWM_IER2_CMPU1_Pos _U_(17) /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU1_Msk (_U_(0x1) << PWM_IER2_CMPU1_Pos) /**< (PWM_IER2) Comparison 1 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU1(value) (PWM_IER2_CMPU1_Msk & ((value) << PWM_IER2_CMPU1_Pos)) +#define PWM_IER2_CMPU2_Pos _U_(18) /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU2_Msk (_U_(0x1) << PWM_IER2_CMPU2_Pos) /**< (PWM_IER2) Comparison 2 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU2(value) (PWM_IER2_CMPU2_Msk & ((value) << PWM_IER2_CMPU2_Pos)) +#define PWM_IER2_CMPU3_Pos _U_(19) /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU3_Msk (_U_(0x1) << PWM_IER2_CMPU3_Pos) /**< (PWM_IER2) Comparison 3 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU3(value) (PWM_IER2_CMPU3_Msk & ((value) << PWM_IER2_CMPU3_Pos)) +#define PWM_IER2_CMPU4_Pos _U_(20) /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU4_Msk (_U_(0x1) << PWM_IER2_CMPU4_Pos) /**< (PWM_IER2) Comparison 4 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU4(value) (PWM_IER2_CMPU4_Msk & ((value) << PWM_IER2_CMPU4_Pos)) +#define PWM_IER2_CMPU5_Pos _U_(21) /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU5_Msk (_U_(0x1) << PWM_IER2_CMPU5_Pos) /**< (PWM_IER2) Comparison 5 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU5(value) (PWM_IER2_CMPU5_Msk & ((value) << PWM_IER2_CMPU5_Pos)) +#define PWM_IER2_CMPU6_Pos _U_(22) /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU6_Msk (_U_(0x1) << PWM_IER2_CMPU6_Pos) /**< (PWM_IER2) Comparison 6 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU6(value) (PWM_IER2_CMPU6_Msk & ((value) << PWM_IER2_CMPU6_Pos)) +#define PWM_IER2_CMPU7_Pos _U_(23) /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Position */ +#define PWM_IER2_CMPU7_Msk (_U_(0x1) << PWM_IER2_CMPU7_Pos) /**< (PWM_IER2) Comparison 7 Update Interrupt Enable Mask */ +#define PWM_IER2_CMPU7(value) (PWM_IER2_CMPU7_Msk & ((value) << PWM_IER2_CMPU7_Pos)) +#define PWM_IER2_Msk _U_(0x00FFFF09) /**< (PWM_IER2) Register Mask */ + +#define PWM_IER2_CMPM_Pos _U_(8) /**< (PWM_IER2 Position) Comparison x Match Interrupt Enable */ +#define PWM_IER2_CMPM_Msk (_U_(0xFF) << PWM_IER2_CMPM_Pos) /**< (PWM_IER2 Mask) CMPM */ +#define PWM_IER2_CMPM(value) (PWM_IER2_CMPM_Msk & ((value) << PWM_IER2_CMPM_Pos)) +#define PWM_IER2_CMPU_Pos _U_(16) /**< (PWM_IER2 Position) Comparison 7 Update Interrupt Enable */ +#define PWM_IER2_CMPU_Msk (_U_(0xFF) << PWM_IER2_CMPU_Pos) /**< (PWM_IER2 Mask) CMPU */ +#define PWM_IER2_CMPU(value) (PWM_IER2_CMPU_Msk & ((value) << PWM_IER2_CMPU_Pos)) + +/* -------- PWM_IDR2 : (PWM Offset: 0x38) ( /W 32) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY_Pos _U_(0) /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Position */ +#define PWM_IDR2_WRDY_Msk (_U_(0x1) << PWM_IDR2_WRDY_Pos) /**< (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable Mask */ +#define PWM_IDR2_WRDY(value) (PWM_IDR2_WRDY_Msk & ((value) << PWM_IDR2_WRDY_Pos)) +#define PWM_IDR2_UNRE_Pos _U_(3) /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Position */ +#define PWM_IDR2_UNRE_Msk (_U_(0x1) << PWM_IDR2_UNRE_Pos) /**< (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable Mask */ +#define PWM_IDR2_UNRE(value) (PWM_IDR2_UNRE_Msk & ((value) << PWM_IDR2_UNRE_Pos)) +#define PWM_IDR2_CMPM0_Pos _U_(8) /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM0_Msk (_U_(0x1) << PWM_IDR2_CMPM0_Pos) /**< (PWM_IDR2) Comparison 0 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM0(value) (PWM_IDR2_CMPM0_Msk & ((value) << PWM_IDR2_CMPM0_Pos)) +#define PWM_IDR2_CMPM1_Pos _U_(9) /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM1_Msk (_U_(0x1) << PWM_IDR2_CMPM1_Pos) /**< (PWM_IDR2) Comparison 1 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM1(value) (PWM_IDR2_CMPM1_Msk & ((value) << PWM_IDR2_CMPM1_Pos)) +#define PWM_IDR2_CMPM2_Pos _U_(10) /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM2_Msk (_U_(0x1) << PWM_IDR2_CMPM2_Pos) /**< (PWM_IDR2) Comparison 2 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM2(value) (PWM_IDR2_CMPM2_Msk & ((value) << PWM_IDR2_CMPM2_Pos)) +#define PWM_IDR2_CMPM3_Pos _U_(11) /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM3_Msk (_U_(0x1) << PWM_IDR2_CMPM3_Pos) /**< (PWM_IDR2) Comparison 3 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM3(value) (PWM_IDR2_CMPM3_Msk & ((value) << PWM_IDR2_CMPM3_Pos)) +#define PWM_IDR2_CMPM4_Pos _U_(12) /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM4_Msk (_U_(0x1) << PWM_IDR2_CMPM4_Pos) /**< (PWM_IDR2) Comparison 4 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM4(value) (PWM_IDR2_CMPM4_Msk & ((value) << PWM_IDR2_CMPM4_Pos)) +#define PWM_IDR2_CMPM5_Pos _U_(13) /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM5_Msk (_U_(0x1) << PWM_IDR2_CMPM5_Pos) /**< (PWM_IDR2) Comparison 5 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM5(value) (PWM_IDR2_CMPM5_Msk & ((value) << PWM_IDR2_CMPM5_Pos)) +#define PWM_IDR2_CMPM6_Pos _U_(14) /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM6_Msk (_U_(0x1) << PWM_IDR2_CMPM6_Pos) /**< (PWM_IDR2) Comparison 6 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM6(value) (PWM_IDR2_CMPM6_Msk & ((value) << PWM_IDR2_CMPM6_Pos)) +#define PWM_IDR2_CMPM7_Pos _U_(15) /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Position */ +#define PWM_IDR2_CMPM7_Msk (_U_(0x1) << PWM_IDR2_CMPM7_Pos) /**< (PWM_IDR2) Comparison 7 Match Interrupt Disable Mask */ +#define PWM_IDR2_CMPM7(value) (PWM_IDR2_CMPM7_Msk & ((value) << PWM_IDR2_CMPM7_Pos)) +#define PWM_IDR2_CMPU0_Pos _U_(16) /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU0_Msk (_U_(0x1) << PWM_IDR2_CMPU0_Pos) /**< (PWM_IDR2) Comparison 0 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU0(value) (PWM_IDR2_CMPU0_Msk & ((value) << PWM_IDR2_CMPU0_Pos)) +#define PWM_IDR2_CMPU1_Pos _U_(17) /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU1_Msk (_U_(0x1) << PWM_IDR2_CMPU1_Pos) /**< (PWM_IDR2) Comparison 1 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU1(value) (PWM_IDR2_CMPU1_Msk & ((value) << PWM_IDR2_CMPU1_Pos)) +#define PWM_IDR2_CMPU2_Pos _U_(18) /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU2_Msk (_U_(0x1) << PWM_IDR2_CMPU2_Pos) /**< (PWM_IDR2) Comparison 2 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU2(value) (PWM_IDR2_CMPU2_Msk & ((value) << PWM_IDR2_CMPU2_Pos)) +#define PWM_IDR2_CMPU3_Pos _U_(19) /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU3_Msk (_U_(0x1) << PWM_IDR2_CMPU3_Pos) /**< (PWM_IDR2) Comparison 3 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU3(value) (PWM_IDR2_CMPU3_Msk & ((value) << PWM_IDR2_CMPU3_Pos)) +#define PWM_IDR2_CMPU4_Pos _U_(20) /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU4_Msk (_U_(0x1) << PWM_IDR2_CMPU4_Pos) /**< (PWM_IDR2) Comparison 4 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU4(value) (PWM_IDR2_CMPU4_Msk & ((value) << PWM_IDR2_CMPU4_Pos)) +#define PWM_IDR2_CMPU5_Pos _U_(21) /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU5_Msk (_U_(0x1) << PWM_IDR2_CMPU5_Pos) /**< (PWM_IDR2) Comparison 5 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU5(value) (PWM_IDR2_CMPU5_Msk & ((value) << PWM_IDR2_CMPU5_Pos)) +#define PWM_IDR2_CMPU6_Pos _U_(22) /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU6_Msk (_U_(0x1) << PWM_IDR2_CMPU6_Pos) /**< (PWM_IDR2) Comparison 6 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU6(value) (PWM_IDR2_CMPU6_Msk & ((value) << PWM_IDR2_CMPU6_Pos)) +#define PWM_IDR2_CMPU7_Pos _U_(23) /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Position */ +#define PWM_IDR2_CMPU7_Msk (_U_(0x1) << PWM_IDR2_CMPU7_Pos) /**< (PWM_IDR2) Comparison 7 Update Interrupt Disable Mask */ +#define PWM_IDR2_CMPU7(value) (PWM_IDR2_CMPU7_Msk & ((value) << PWM_IDR2_CMPU7_Pos)) +#define PWM_IDR2_Msk _U_(0x00FFFF09) /**< (PWM_IDR2) Register Mask */ + +#define PWM_IDR2_CMPM_Pos _U_(8) /**< (PWM_IDR2 Position) Comparison x Match Interrupt Disable */ +#define PWM_IDR2_CMPM_Msk (_U_(0xFF) << PWM_IDR2_CMPM_Pos) /**< (PWM_IDR2 Mask) CMPM */ +#define PWM_IDR2_CMPM(value) (PWM_IDR2_CMPM_Msk & ((value) << PWM_IDR2_CMPM_Pos)) +#define PWM_IDR2_CMPU_Pos _U_(16) /**< (PWM_IDR2 Position) Comparison 7 Update Interrupt Disable */ +#define PWM_IDR2_CMPU_Msk (_U_(0xFF) << PWM_IDR2_CMPU_Pos) /**< (PWM_IDR2 Mask) CMPU */ +#define PWM_IDR2_CMPU(value) (PWM_IDR2_CMPU_Msk & ((value) << PWM_IDR2_CMPU_Pos)) + +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) ( R/ 32) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY_Pos _U_(0) /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Position */ +#define PWM_IMR2_WRDY_Msk (_U_(0x1) << PWM_IMR2_WRDY_Pos) /**< (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask Mask */ +#define PWM_IMR2_WRDY(value) (PWM_IMR2_WRDY_Msk & ((value) << PWM_IMR2_WRDY_Pos)) +#define PWM_IMR2_UNRE_Pos _U_(3) /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Position */ +#define PWM_IMR2_UNRE_Msk (_U_(0x1) << PWM_IMR2_UNRE_Pos) /**< (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask Mask */ +#define PWM_IMR2_UNRE(value) (PWM_IMR2_UNRE_Msk & ((value) << PWM_IMR2_UNRE_Pos)) +#define PWM_IMR2_CMPM0_Pos _U_(8) /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM0_Msk (_U_(0x1) << PWM_IMR2_CMPM0_Pos) /**< (PWM_IMR2) Comparison 0 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM0(value) (PWM_IMR2_CMPM0_Msk & ((value) << PWM_IMR2_CMPM0_Pos)) +#define PWM_IMR2_CMPM1_Pos _U_(9) /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM1_Msk (_U_(0x1) << PWM_IMR2_CMPM1_Pos) /**< (PWM_IMR2) Comparison 1 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM1(value) (PWM_IMR2_CMPM1_Msk & ((value) << PWM_IMR2_CMPM1_Pos)) +#define PWM_IMR2_CMPM2_Pos _U_(10) /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM2_Msk (_U_(0x1) << PWM_IMR2_CMPM2_Pos) /**< (PWM_IMR2) Comparison 2 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM2(value) (PWM_IMR2_CMPM2_Msk & ((value) << PWM_IMR2_CMPM2_Pos)) +#define PWM_IMR2_CMPM3_Pos _U_(11) /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM3_Msk (_U_(0x1) << PWM_IMR2_CMPM3_Pos) /**< (PWM_IMR2) Comparison 3 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM3(value) (PWM_IMR2_CMPM3_Msk & ((value) << PWM_IMR2_CMPM3_Pos)) +#define PWM_IMR2_CMPM4_Pos _U_(12) /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM4_Msk (_U_(0x1) << PWM_IMR2_CMPM4_Pos) /**< (PWM_IMR2) Comparison 4 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM4(value) (PWM_IMR2_CMPM4_Msk & ((value) << PWM_IMR2_CMPM4_Pos)) +#define PWM_IMR2_CMPM5_Pos _U_(13) /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM5_Msk (_U_(0x1) << PWM_IMR2_CMPM5_Pos) /**< (PWM_IMR2) Comparison 5 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM5(value) (PWM_IMR2_CMPM5_Msk & ((value) << PWM_IMR2_CMPM5_Pos)) +#define PWM_IMR2_CMPM6_Pos _U_(14) /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM6_Msk (_U_(0x1) << PWM_IMR2_CMPM6_Pos) /**< (PWM_IMR2) Comparison 6 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM6(value) (PWM_IMR2_CMPM6_Msk & ((value) << PWM_IMR2_CMPM6_Pos)) +#define PWM_IMR2_CMPM7_Pos _U_(15) /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Position */ +#define PWM_IMR2_CMPM7_Msk (_U_(0x1) << PWM_IMR2_CMPM7_Pos) /**< (PWM_IMR2) Comparison 7 Match Interrupt Mask Mask */ +#define PWM_IMR2_CMPM7(value) (PWM_IMR2_CMPM7_Msk & ((value) << PWM_IMR2_CMPM7_Pos)) +#define PWM_IMR2_CMPU0_Pos _U_(16) /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU0_Msk (_U_(0x1) << PWM_IMR2_CMPU0_Pos) /**< (PWM_IMR2) Comparison 0 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU0(value) (PWM_IMR2_CMPU0_Msk & ((value) << PWM_IMR2_CMPU0_Pos)) +#define PWM_IMR2_CMPU1_Pos _U_(17) /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU1_Msk (_U_(0x1) << PWM_IMR2_CMPU1_Pos) /**< (PWM_IMR2) Comparison 1 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU1(value) (PWM_IMR2_CMPU1_Msk & ((value) << PWM_IMR2_CMPU1_Pos)) +#define PWM_IMR2_CMPU2_Pos _U_(18) /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU2_Msk (_U_(0x1) << PWM_IMR2_CMPU2_Pos) /**< (PWM_IMR2) Comparison 2 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU2(value) (PWM_IMR2_CMPU2_Msk & ((value) << PWM_IMR2_CMPU2_Pos)) +#define PWM_IMR2_CMPU3_Pos _U_(19) /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU3_Msk (_U_(0x1) << PWM_IMR2_CMPU3_Pos) /**< (PWM_IMR2) Comparison 3 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU3(value) (PWM_IMR2_CMPU3_Msk & ((value) << PWM_IMR2_CMPU3_Pos)) +#define PWM_IMR2_CMPU4_Pos _U_(20) /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU4_Msk (_U_(0x1) << PWM_IMR2_CMPU4_Pos) /**< (PWM_IMR2) Comparison 4 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU4(value) (PWM_IMR2_CMPU4_Msk & ((value) << PWM_IMR2_CMPU4_Pos)) +#define PWM_IMR2_CMPU5_Pos _U_(21) /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU5_Msk (_U_(0x1) << PWM_IMR2_CMPU5_Pos) /**< (PWM_IMR2) Comparison 5 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU5(value) (PWM_IMR2_CMPU5_Msk & ((value) << PWM_IMR2_CMPU5_Pos)) +#define PWM_IMR2_CMPU6_Pos _U_(22) /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU6_Msk (_U_(0x1) << PWM_IMR2_CMPU6_Pos) /**< (PWM_IMR2) Comparison 6 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU6(value) (PWM_IMR2_CMPU6_Msk & ((value) << PWM_IMR2_CMPU6_Pos)) +#define PWM_IMR2_CMPU7_Pos _U_(23) /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Position */ +#define PWM_IMR2_CMPU7_Msk (_U_(0x1) << PWM_IMR2_CMPU7_Pos) /**< (PWM_IMR2) Comparison 7 Update Interrupt Mask Mask */ +#define PWM_IMR2_CMPU7(value) (PWM_IMR2_CMPU7_Msk & ((value) << PWM_IMR2_CMPU7_Pos)) +#define PWM_IMR2_Msk _U_(0x00FFFF09) /**< (PWM_IMR2) Register Mask */ + +#define PWM_IMR2_CMPM_Pos _U_(8) /**< (PWM_IMR2 Position) Comparison x Match Interrupt Mask */ +#define PWM_IMR2_CMPM_Msk (_U_(0xFF) << PWM_IMR2_CMPM_Pos) /**< (PWM_IMR2 Mask) CMPM */ +#define PWM_IMR2_CMPM(value) (PWM_IMR2_CMPM_Msk & ((value) << PWM_IMR2_CMPM_Pos)) +#define PWM_IMR2_CMPU_Pos _U_(16) /**< (PWM_IMR2 Position) Comparison 7 Update Interrupt Mask */ +#define PWM_IMR2_CMPU_Msk (_U_(0xFF) << PWM_IMR2_CMPU_Pos) /**< (PWM_IMR2 Mask) CMPU */ +#define PWM_IMR2_CMPU(value) (PWM_IMR2_CMPU_Msk & ((value) << PWM_IMR2_CMPU_Pos)) + +/* -------- PWM_ISR2 : (PWM Offset: 0x40) ( R/ 32) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY_Pos _U_(0) /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Position */ +#define PWM_ISR2_WRDY_Msk (_U_(0x1) << PWM_ISR2_WRDY_Pos) /**< (PWM_ISR2) Write Ready for Synchronous Channels Update Mask */ +#define PWM_ISR2_WRDY(value) (PWM_ISR2_WRDY_Msk & ((value) << PWM_ISR2_WRDY_Pos)) +#define PWM_ISR2_UNRE_Pos _U_(3) /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Position */ +#define PWM_ISR2_UNRE_Msk (_U_(0x1) << PWM_ISR2_UNRE_Pos) /**< (PWM_ISR2) Synchronous Channels Update Underrun Error Mask */ +#define PWM_ISR2_UNRE(value) (PWM_ISR2_UNRE_Msk & ((value) << PWM_ISR2_UNRE_Pos)) +#define PWM_ISR2_CMPM0_Pos _U_(8) /**< (PWM_ISR2) Comparison 0 Match Position */ +#define PWM_ISR2_CMPM0_Msk (_U_(0x1) << PWM_ISR2_CMPM0_Pos) /**< (PWM_ISR2) Comparison 0 Match Mask */ +#define PWM_ISR2_CMPM0(value) (PWM_ISR2_CMPM0_Msk & ((value) << PWM_ISR2_CMPM0_Pos)) +#define PWM_ISR2_CMPM1_Pos _U_(9) /**< (PWM_ISR2) Comparison 1 Match Position */ +#define PWM_ISR2_CMPM1_Msk (_U_(0x1) << PWM_ISR2_CMPM1_Pos) /**< (PWM_ISR2) Comparison 1 Match Mask */ +#define PWM_ISR2_CMPM1(value) (PWM_ISR2_CMPM1_Msk & ((value) << PWM_ISR2_CMPM1_Pos)) +#define PWM_ISR2_CMPM2_Pos _U_(10) /**< (PWM_ISR2) Comparison 2 Match Position */ +#define PWM_ISR2_CMPM2_Msk (_U_(0x1) << PWM_ISR2_CMPM2_Pos) /**< (PWM_ISR2) Comparison 2 Match Mask */ +#define PWM_ISR2_CMPM2(value) (PWM_ISR2_CMPM2_Msk & ((value) << PWM_ISR2_CMPM2_Pos)) +#define PWM_ISR2_CMPM3_Pos _U_(11) /**< (PWM_ISR2) Comparison 3 Match Position */ +#define PWM_ISR2_CMPM3_Msk (_U_(0x1) << PWM_ISR2_CMPM3_Pos) /**< (PWM_ISR2) Comparison 3 Match Mask */ +#define PWM_ISR2_CMPM3(value) (PWM_ISR2_CMPM3_Msk & ((value) << PWM_ISR2_CMPM3_Pos)) +#define PWM_ISR2_CMPM4_Pos _U_(12) /**< (PWM_ISR2) Comparison 4 Match Position */ +#define PWM_ISR2_CMPM4_Msk (_U_(0x1) << PWM_ISR2_CMPM4_Pos) /**< (PWM_ISR2) Comparison 4 Match Mask */ +#define PWM_ISR2_CMPM4(value) (PWM_ISR2_CMPM4_Msk & ((value) << PWM_ISR2_CMPM4_Pos)) +#define PWM_ISR2_CMPM5_Pos _U_(13) /**< (PWM_ISR2) Comparison 5 Match Position */ +#define PWM_ISR2_CMPM5_Msk (_U_(0x1) << PWM_ISR2_CMPM5_Pos) /**< (PWM_ISR2) Comparison 5 Match Mask */ +#define PWM_ISR2_CMPM5(value) (PWM_ISR2_CMPM5_Msk & ((value) << PWM_ISR2_CMPM5_Pos)) +#define PWM_ISR2_CMPM6_Pos _U_(14) /**< (PWM_ISR2) Comparison 6 Match Position */ +#define PWM_ISR2_CMPM6_Msk (_U_(0x1) << PWM_ISR2_CMPM6_Pos) /**< (PWM_ISR2) Comparison 6 Match Mask */ +#define PWM_ISR2_CMPM6(value) (PWM_ISR2_CMPM6_Msk & ((value) << PWM_ISR2_CMPM6_Pos)) +#define PWM_ISR2_CMPM7_Pos _U_(15) /**< (PWM_ISR2) Comparison 7 Match Position */ +#define PWM_ISR2_CMPM7_Msk (_U_(0x1) << PWM_ISR2_CMPM7_Pos) /**< (PWM_ISR2) Comparison 7 Match Mask */ +#define PWM_ISR2_CMPM7(value) (PWM_ISR2_CMPM7_Msk & ((value) << PWM_ISR2_CMPM7_Pos)) +#define PWM_ISR2_CMPU0_Pos _U_(16) /**< (PWM_ISR2) Comparison 0 Update Position */ +#define PWM_ISR2_CMPU0_Msk (_U_(0x1) << PWM_ISR2_CMPU0_Pos) /**< (PWM_ISR2) Comparison 0 Update Mask */ +#define PWM_ISR2_CMPU0(value) (PWM_ISR2_CMPU0_Msk & ((value) << PWM_ISR2_CMPU0_Pos)) +#define PWM_ISR2_CMPU1_Pos _U_(17) /**< (PWM_ISR2) Comparison 1 Update Position */ +#define PWM_ISR2_CMPU1_Msk (_U_(0x1) << PWM_ISR2_CMPU1_Pos) /**< (PWM_ISR2) Comparison 1 Update Mask */ +#define PWM_ISR2_CMPU1(value) (PWM_ISR2_CMPU1_Msk & ((value) << PWM_ISR2_CMPU1_Pos)) +#define PWM_ISR2_CMPU2_Pos _U_(18) /**< (PWM_ISR2) Comparison 2 Update Position */ +#define PWM_ISR2_CMPU2_Msk (_U_(0x1) << PWM_ISR2_CMPU2_Pos) /**< (PWM_ISR2) Comparison 2 Update Mask */ +#define PWM_ISR2_CMPU2(value) (PWM_ISR2_CMPU2_Msk & ((value) << PWM_ISR2_CMPU2_Pos)) +#define PWM_ISR2_CMPU3_Pos _U_(19) /**< (PWM_ISR2) Comparison 3 Update Position */ +#define PWM_ISR2_CMPU3_Msk (_U_(0x1) << PWM_ISR2_CMPU3_Pos) /**< (PWM_ISR2) Comparison 3 Update Mask */ +#define PWM_ISR2_CMPU3(value) (PWM_ISR2_CMPU3_Msk & ((value) << PWM_ISR2_CMPU3_Pos)) +#define PWM_ISR2_CMPU4_Pos _U_(20) /**< (PWM_ISR2) Comparison 4 Update Position */ +#define PWM_ISR2_CMPU4_Msk (_U_(0x1) << PWM_ISR2_CMPU4_Pos) /**< (PWM_ISR2) Comparison 4 Update Mask */ +#define PWM_ISR2_CMPU4(value) (PWM_ISR2_CMPU4_Msk & ((value) << PWM_ISR2_CMPU4_Pos)) +#define PWM_ISR2_CMPU5_Pos _U_(21) /**< (PWM_ISR2) Comparison 5 Update Position */ +#define PWM_ISR2_CMPU5_Msk (_U_(0x1) << PWM_ISR2_CMPU5_Pos) /**< (PWM_ISR2) Comparison 5 Update Mask */ +#define PWM_ISR2_CMPU5(value) (PWM_ISR2_CMPU5_Msk & ((value) << PWM_ISR2_CMPU5_Pos)) +#define PWM_ISR2_CMPU6_Pos _U_(22) /**< (PWM_ISR2) Comparison 6 Update Position */ +#define PWM_ISR2_CMPU6_Msk (_U_(0x1) << PWM_ISR2_CMPU6_Pos) /**< (PWM_ISR2) Comparison 6 Update Mask */ +#define PWM_ISR2_CMPU6(value) (PWM_ISR2_CMPU6_Msk & ((value) << PWM_ISR2_CMPU6_Pos)) +#define PWM_ISR2_CMPU7_Pos _U_(23) /**< (PWM_ISR2) Comparison 7 Update Position */ +#define PWM_ISR2_CMPU7_Msk (_U_(0x1) << PWM_ISR2_CMPU7_Pos) /**< (PWM_ISR2) Comparison 7 Update Mask */ +#define PWM_ISR2_CMPU7(value) (PWM_ISR2_CMPU7_Msk & ((value) << PWM_ISR2_CMPU7_Pos)) +#define PWM_ISR2_Msk _U_(0x00FFFF09) /**< (PWM_ISR2) Register Mask */ + +#define PWM_ISR2_CMPM_Pos _U_(8) /**< (PWM_ISR2 Position) Comparison x Match */ +#define PWM_ISR2_CMPM_Msk (_U_(0xFF) << PWM_ISR2_CMPM_Pos) /**< (PWM_ISR2 Mask) CMPM */ +#define PWM_ISR2_CMPM(value) (PWM_ISR2_CMPM_Msk & ((value) << PWM_ISR2_CMPM_Pos)) +#define PWM_ISR2_CMPU_Pos _U_(16) /**< (PWM_ISR2 Position) Comparison 7 Update */ +#define PWM_ISR2_CMPU_Msk (_U_(0xFF) << PWM_ISR2_CMPU_Pos) /**< (PWM_ISR2 Mask) CMPU */ +#define PWM_ISR2_CMPU(value) (PWM_ISR2_CMPU_Msk & ((value) << PWM_ISR2_CMPU_Pos)) + +/* -------- PWM_OOV : (PWM Offset: 0x44) (R/W 32) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0_Pos _U_(0) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Position */ +#define PWM_OOV_OOVH0_Msk (_U_(0x1) << PWM_OOV_OOVH0_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 0 Mask */ +#define PWM_OOV_OOVH0(value) (PWM_OOV_OOVH0_Msk & ((value) << PWM_OOV_OOVH0_Pos)) +#define PWM_OOV_OOVH1_Pos _U_(1) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Position */ +#define PWM_OOV_OOVH1_Msk (_U_(0x1) << PWM_OOV_OOVH1_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 1 Mask */ +#define PWM_OOV_OOVH1(value) (PWM_OOV_OOVH1_Msk & ((value) << PWM_OOV_OOVH1_Pos)) +#define PWM_OOV_OOVH2_Pos _U_(2) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Position */ +#define PWM_OOV_OOVH2_Msk (_U_(0x1) << PWM_OOV_OOVH2_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 2 Mask */ +#define PWM_OOV_OOVH2(value) (PWM_OOV_OOVH2_Msk & ((value) << PWM_OOV_OOVH2_Pos)) +#define PWM_OOV_OOVH3_Pos _U_(3) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Position */ +#define PWM_OOV_OOVH3_Msk (_U_(0x1) << PWM_OOV_OOVH3_Pos) /**< (PWM_OOV) Output Override Value for PWMH output of the channel 3 Mask */ +#define PWM_OOV_OOVH3(value) (PWM_OOV_OOVH3_Msk & ((value) << PWM_OOV_OOVH3_Pos)) +#define PWM_OOV_OOVL0_Pos _U_(16) /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Position */ +#define PWM_OOV_OOVL0_Msk (_U_(0x1) << PWM_OOV_OOVL0_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 0 Mask */ +#define PWM_OOV_OOVL0(value) (PWM_OOV_OOVL0_Msk & ((value) << PWM_OOV_OOVL0_Pos)) +#define PWM_OOV_OOVL1_Pos _U_(17) /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Position */ +#define PWM_OOV_OOVL1_Msk (_U_(0x1) << PWM_OOV_OOVL1_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 1 Mask */ +#define PWM_OOV_OOVL1(value) (PWM_OOV_OOVL1_Msk & ((value) << PWM_OOV_OOVL1_Pos)) +#define PWM_OOV_OOVL2_Pos _U_(18) /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Position */ +#define PWM_OOV_OOVL2_Msk (_U_(0x1) << PWM_OOV_OOVL2_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 2 Mask */ +#define PWM_OOV_OOVL2(value) (PWM_OOV_OOVL2_Msk & ((value) << PWM_OOV_OOVL2_Pos)) +#define PWM_OOV_OOVL3_Pos _U_(19) /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Position */ +#define PWM_OOV_OOVL3_Msk (_U_(0x1) << PWM_OOV_OOVL3_Pos) /**< (PWM_OOV) Output Override Value for PWML output of the channel 3 Mask */ +#define PWM_OOV_OOVL3(value) (PWM_OOV_OOVL3_Msk & ((value) << PWM_OOV_OOVL3_Pos)) +#define PWM_OOV_Msk _U_(0x000F000F) /**< (PWM_OOV) Register Mask */ + +#define PWM_OOV_OOVH_Pos _U_(0) /**< (PWM_OOV Position) Output Override Value for PWMH output of the channel x */ +#define PWM_OOV_OOVH_Msk (_U_(0xF) << PWM_OOV_OOVH_Pos) /**< (PWM_OOV Mask) OOVH */ +#define PWM_OOV_OOVH(value) (PWM_OOV_OOVH_Msk & ((value) << PWM_OOV_OOVH_Pos)) +#define PWM_OOV_OOVL_Pos _U_(16) /**< (PWM_OOV Position) Output Override Value for PWML output of the channel 3 */ +#define PWM_OOV_OOVL_Msk (_U_(0xF) << PWM_OOV_OOVL_Pos) /**< (PWM_OOV Mask) OOVL */ +#define PWM_OOV_OOVL(value) (PWM_OOV_OOVL_Msk & ((value) << PWM_OOV_OOVL_Pos)) + +/* -------- PWM_OS : (PWM Offset: 0x48) (R/W 32) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0_Pos _U_(0) /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Position */ +#define PWM_OS_OSH0_Msk (_U_(0x1) << PWM_OS_OSH0_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 0 Mask */ +#define PWM_OS_OSH0(value) (PWM_OS_OSH0_Msk & ((value) << PWM_OS_OSH0_Pos)) +#define PWM_OS_OSH1_Pos _U_(1) /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Position */ +#define PWM_OS_OSH1_Msk (_U_(0x1) << PWM_OS_OSH1_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 1 Mask */ +#define PWM_OS_OSH1(value) (PWM_OS_OSH1_Msk & ((value) << PWM_OS_OSH1_Pos)) +#define PWM_OS_OSH2_Pos _U_(2) /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Position */ +#define PWM_OS_OSH2_Msk (_U_(0x1) << PWM_OS_OSH2_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 2 Mask */ +#define PWM_OS_OSH2(value) (PWM_OS_OSH2_Msk & ((value) << PWM_OS_OSH2_Pos)) +#define PWM_OS_OSH3_Pos _U_(3) /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Position */ +#define PWM_OS_OSH3_Msk (_U_(0x1) << PWM_OS_OSH3_Pos) /**< (PWM_OS) Output Selection for PWMH output of the channel 3 Mask */ +#define PWM_OS_OSH3(value) (PWM_OS_OSH3_Msk & ((value) << PWM_OS_OSH3_Pos)) +#define PWM_OS_OSL0_Pos _U_(16) /**< (PWM_OS) Output Selection for PWML output of the channel 0 Position */ +#define PWM_OS_OSL0_Msk (_U_(0x1) << PWM_OS_OSL0_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 0 Mask */ +#define PWM_OS_OSL0(value) (PWM_OS_OSL0_Msk & ((value) << PWM_OS_OSL0_Pos)) +#define PWM_OS_OSL1_Pos _U_(17) /**< (PWM_OS) Output Selection for PWML output of the channel 1 Position */ +#define PWM_OS_OSL1_Msk (_U_(0x1) << PWM_OS_OSL1_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 1 Mask */ +#define PWM_OS_OSL1(value) (PWM_OS_OSL1_Msk & ((value) << PWM_OS_OSL1_Pos)) +#define PWM_OS_OSL2_Pos _U_(18) /**< (PWM_OS) Output Selection for PWML output of the channel 2 Position */ +#define PWM_OS_OSL2_Msk (_U_(0x1) << PWM_OS_OSL2_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 2 Mask */ +#define PWM_OS_OSL2(value) (PWM_OS_OSL2_Msk & ((value) << PWM_OS_OSL2_Pos)) +#define PWM_OS_OSL3_Pos _U_(19) /**< (PWM_OS) Output Selection for PWML output of the channel 3 Position */ +#define PWM_OS_OSL3_Msk (_U_(0x1) << PWM_OS_OSL3_Pos) /**< (PWM_OS) Output Selection for PWML output of the channel 3 Mask */ +#define PWM_OS_OSL3(value) (PWM_OS_OSL3_Msk & ((value) << PWM_OS_OSL3_Pos)) +#define PWM_OS_Msk _U_(0x000F000F) /**< (PWM_OS) Register Mask */ + +#define PWM_OS_OSH_Pos _U_(0) /**< (PWM_OS Position) Output Selection for PWMH output of the channel x */ +#define PWM_OS_OSH_Msk (_U_(0xF) << PWM_OS_OSH_Pos) /**< (PWM_OS Mask) OSH */ +#define PWM_OS_OSH(value) (PWM_OS_OSH_Msk & ((value) << PWM_OS_OSH_Pos)) +#define PWM_OS_OSL_Pos _U_(16) /**< (PWM_OS Position) Output Selection for PWML output of the channel 3 */ +#define PWM_OS_OSL_Msk (_U_(0xF) << PWM_OS_OSL_Pos) /**< (PWM_OS Mask) OSL */ +#define PWM_OS_OSL(value) (PWM_OS_OSL_Msk & ((value) << PWM_OS_OSL_Pos)) + +/* -------- PWM_OSS : (PWM Offset: 0x4C) ( /W 32) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0_Pos _U_(0) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSS_OSSH0_Msk (_U_(0x1) << PWM_OSS_OSSH0_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSS_OSSH0(value) (PWM_OSS_OSSH0_Msk & ((value) << PWM_OSS_OSSH0_Pos)) +#define PWM_OSS_OSSH1_Pos _U_(1) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSS_OSSH1_Msk (_U_(0x1) << PWM_OSS_OSSH1_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSS_OSSH1(value) (PWM_OSS_OSSH1_Msk & ((value) << PWM_OSS_OSSH1_Pos)) +#define PWM_OSS_OSSH2_Pos _U_(2) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSS_OSSH2_Msk (_U_(0x1) << PWM_OSS_OSSH2_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSS_OSSH2(value) (PWM_OSS_OSSH2_Msk & ((value) << PWM_OSS_OSSH2_Pos)) +#define PWM_OSS_OSSH3_Pos _U_(3) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSS_OSSH3_Msk (_U_(0x1) << PWM_OSS_OSSH3_Pos) /**< (PWM_OSS) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSS_OSSH3(value) (PWM_OSS_OSSH3_Msk & ((value) << PWM_OSS_OSSH3_Pos)) +#define PWM_OSS_OSSL0_Pos _U_(16) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSS_OSSL0_Msk (_U_(0x1) << PWM_OSS_OSSL0_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSS_OSSL0(value) (PWM_OSS_OSSL0_Msk & ((value) << PWM_OSS_OSSL0_Pos)) +#define PWM_OSS_OSSL1_Pos _U_(17) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSS_OSSL1_Msk (_U_(0x1) << PWM_OSS_OSSL1_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSS_OSSL1(value) (PWM_OSS_OSSL1_Msk & ((value) << PWM_OSS_OSSL1_Pos)) +#define PWM_OSS_OSSL2_Pos _U_(18) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSS_OSSL2_Msk (_U_(0x1) << PWM_OSS_OSSL2_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSS_OSSL2(value) (PWM_OSS_OSSL2_Msk & ((value) << PWM_OSS_OSSL2_Pos)) +#define PWM_OSS_OSSL3_Pos _U_(19) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSS_OSSL3_Msk (_U_(0x1) << PWM_OSS_OSSL3_Pos) /**< (PWM_OSS) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSS_OSSL3(value) (PWM_OSS_OSSL3_Msk & ((value) << PWM_OSS_OSSL3_Pos)) +#define PWM_OSS_Msk _U_(0x000F000F) /**< (PWM_OSS) Register Mask */ + +#define PWM_OSS_OSSH_Pos _U_(0) /**< (PWM_OSS Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSS_OSSH_Msk (_U_(0xF) << PWM_OSS_OSSH_Pos) /**< (PWM_OSS Mask) OSSH */ +#define PWM_OSS_OSSH(value) (PWM_OSS_OSSH_Msk & ((value) << PWM_OSS_OSSH_Pos)) +#define PWM_OSS_OSSL_Pos _U_(16) /**< (PWM_OSS Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSS_OSSL_Msk (_U_(0xF) << PWM_OSS_OSSL_Pos) /**< (PWM_OSS Mask) OSSL */ +#define PWM_OSS_OSSL(value) (PWM_OSS_OSSL_Msk & ((value) << PWM_OSS_OSSL_Pos)) + +/* -------- PWM_OSC : (PWM Offset: 0x50) ( /W 32) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0_Pos _U_(0) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSC_OSCH0_Msk (_U_(0x1) << PWM_OSC_OSCH0_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSC_OSCH0(value) (PWM_OSC_OSCH0_Msk & ((value) << PWM_OSC_OSCH0_Pos)) +#define PWM_OSC_OSCH1_Pos _U_(1) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSC_OSCH1_Msk (_U_(0x1) << PWM_OSC_OSCH1_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSC_OSCH1(value) (PWM_OSC_OSCH1_Msk & ((value) << PWM_OSC_OSCH1_Pos)) +#define PWM_OSC_OSCH2_Pos _U_(2) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSC_OSCH2_Msk (_U_(0x1) << PWM_OSC_OSCH2_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSC_OSCH2(value) (PWM_OSC_OSCH2_Msk & ((value) << PWM_OSC_OSCH2_Pos)) +#define PWM_OSC_OSCH3_Pos _U_(3) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSC_OSCH3_Msk (_U_(0x1) << PWM_OSC_OSCH3_Pos) /**< (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSC_OSCH3(value) (PWM_OSC_OSCH3_Msk & ((value) << PWM_OSC_OSCH3_Pos)) +#define PWM_OSC_OSCL0_Pos _U_(16) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSC_OSCL0_Msk (_U_(0x1) << PWM_OSC_OSCL0_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSC_OSCL0(value) (PWM_OSC_OSCL0_Msk & ((value) << PWM_OSC_OSCL0_Pos)) +#define PWM_OSC_OSCL1_Pos _U_(17) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSC_OSCL1_Msk (_U_(0x1) << PWM_OSC_OSCL1_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSC_OSCL1(value) (PWM_OSC_OSCL1_Msk & ((value) << PWM_OSC_OSCL1_Pos)) +#define PWM_OSC_OSCL2_Pos _U_(18) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSC_OSCL2_Msk (_U_(0x1) << PWM_OSC_OSCL2_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSC_OSCL2(value) (PWM_OSC_OSCL2_Msk & ((value) << PWM_OSC_OSCL2_Pos)) +#define PWM_OSC_OSCL3_Pos _U_(19) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSC_OSCL3_Msk (_U_(0x1) << PWM_OSC_OSCL3_Pos) /**< (PWM_OSC) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSC_OSCL3(value) (PWM_OSC_OSCL3_Msk & ((value) << PWM_OSC_OSCL3_Pos)) +#define PWM_OSC_Msk _U_(0x000F000F) /**< (PWM_OSC) Register Mask */ + +#define PWM_OSC_OSCH_Pos _U_(0) /**< (PWM_OSC Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSC_OSCH_Msk (_U_(0xF) << PWM_OSC_OSCH_Pos) /**< (PWM_OSC Mask) OSCH */ +#define PWM_OSC_OSCH(value) (PWM_OSC_OSCH_Msk & ((value) << PWM_OSC_OSCH_Pos)) +#define PWM_OSC_OSCL_Pos _U_(16) /**< (PWM_OSC Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSC_OSCL_Msk (_U_(0xF) << PWM_OSC_OSCL_Pos) /**< (PWM_OSC Mask) OSCL */ +#define PWM_OSC_OSCL(value) (PWM_OSC_OSCL_Msk & ((value) << PWM_OSC_OSCL_Pos)) + +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) ( /W 32) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0_Pos _U_(0) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPH0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPH0(value) (PWM_OSSUPD_OSSUPH0_Msk & ((value) << PWM_OSSUPD_OSSUPH0_Pos)) +#define PWM_OSSUPD_OSSUPH1_Pos _U_(1) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPH1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPH1(value) (PWM_OSSUPD_OSSUPH1_Msk & ((value) << PWM_OSSUPD_OSSUPH1_Pos)) +#define PWM_OSSUPD_OSSUPH2_Pos _U_(2) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPH2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPH2(value) (PWM_OSSUPD_OSSUPH2_Msk & ((value) << PWM_OSSUPD_OSSUPH2_Pos)) +#define PWM_OSSUPD_OSSUPH3_Pos _U_(3) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPH3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPH3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPH3(value) (PWM_OSSUPD_OSSUPH3_Msk & ((value) << PWM_OSSUPD_OSSUPH3_Pos)) +#define PWM_OSSUPD_OSSUPL0_Pos _U_(16) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Position */ +#define PWM_OSSUPD_OSSUPL0_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL0_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 Mask */ +#define PWM_OSSUPD_OSSUPL0(value) (PWM_OSSUPD_OSSUPL0_Msk & ((value) << PWM_OSSUPD_OSSUPL0_Pos)) +#define PWM_OSSUPD_OSSUPL1_Pos _U_(17) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Position */ +#define PWM_OSSUPD_OSSUPL1_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL1_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 Mask */ +#define PWM_OSSUPD_OSSUPL1(value) (PWM_OSSUPD_OSSUPL1_Msk & ((value) << PWM_OSSUPD_OSSUPL1_Pos)) +#define PWM_OSSUPD_OSSUPL2_Pos _U_(18) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Position */ +#define PWM_OSSUPD_OSSUPL2_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL2_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 Mask */ +#define PWM_OSSUPD_OSSUPL2(value) (PWM_OSSUPD_OSSUPL2_Msk & ((value) << PWM_OSSUPD_OSSUPL2_Pos)) +#define PWM_OSSUPD_OSSUPL3_Pos _U_(19) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Position */ +#define PWM_OSSUPD_OSSUPL3_Msk (_U_(0x1) << PWM_OSSUPD_OSSUPL3_Pos) /**< (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 Mask */ +#define PWM_OSSUPD_OSSUPL3(value) (PWM_OSSUPD_OSSUPL3_Msk & ((value) << PWM_OSSUPD_OSSUPL3_Pos)) +#define PWM_OSSUPD_Msk _U_(0x000F000F) /**< (PWM_OSSUPD) Register Mask */ + +#define PWM_OSSUPD_OSSUPH_Pos _U_(0) /**< (PWM_OSSUPD Position) Output Selection Set for PWMH output of the channel x */ +#define PWM_OSSUPD_OSSUPH_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPH_Pos) /**< (PWM_OSSUPD Mask) OSSUPH */ +#define PWM_OSSUPD_OSSUPH(value) (PWM_OSSUPD_OSSUPH_Msk & ((value) << PWM_OSSUPD_OSSUPH_Pos)) +#define PWM_OSSUPD_OSSUPL_Pos _U_(16) /**< (PWM_OSSUPD Position) Output Selection Set for PWML output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL_Msk (_U_(0xF) << PWM_OSSUPD_OSSUPL_Pos) /**< (PWM_OSSUPD Mask) OSSUPL */ +#define PWM_OSSUPD_OSSUPL(value) (PWM_OSSUPD_OSSUPL_Msk & ((value) << PWM_OSSUPD_OSSUPL_Pos)) + +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) ( /W 32) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0_Pos _U_(0) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPH0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPH0(value) (PWM_OSCUPD_OSCUPH0_Msk & ((value) << PWM_OSCUPD_OSCUPH0_Pos)) +#define PWM_OSCUPD_OSCUPH1_Pos _U_(1) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPH1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPH1(value) (PWM_OSCUPD_OSCUPH1_Msk & ((value) << PWM_OSCUPD_OSCUPH1_Pos)) +#define PWM_OSCUPD_OSCUPH2_Pos _U_(2) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPH2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPH2(value) (PWM_OSCUPD_OSCUPH2_Msk & ((value) << PWM_OSCUPD_OSCUPH2_Pos)) +#define PWM_OSCUPD_OSCUPH3_Pos _U_(3) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPH3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPH3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPH3(value) (PWM_OSCUPD_OSCUPH3_Msk & ((value) << PWM_OSCUPD_OSCUPH3_Pos)) +#define PWM_OSCUPD_OSCUPL0_Pos _U_(16) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Position */ +#define PWM_OSCUPD_OSCUPL0_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL0_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 Mask */ +#define PWM_OSCUPD_OSCUPL0(value) (PWM_OSCUPD_OSCUPL0_Msk & ((value) << PWM_OSCUPD_OSCUPL0_Pos)) +#define PWM_OSCUPD_OSCUPL1_Pos _U_(17) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Position */ +#define PWM_OSCUPD_OSCUPL1_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL1_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 Mask */ +#define PWM_OSCUPD_OSCUPL1(value) (PWM_OSCUPD_OSCUPL1_Msk & ((value) << PWM_OSCUPD_OSCUPL1_Pos)) +#define PWM_OSCUPD_OSCUPL2_Pos _U_(18) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Position */ +#define PWM_OSCUPD_OSCUPL2_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL2_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 Mask */ +#define PWM_OSCUPD_OSCUPL2(value) (PWM_OSCUPD_OSCUPL2_Msk & ((value) << PWM_OSCUPD_OSCUPL2_Pos)) +#define PWM_OSCUPD_OSCUPL3_Pos _U_(19) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Position */ +#define PWM_OSCUPD_OSCUPL3_Msk (_U_(0x1) << PWM_OSCUPD_OSCUPL3_Pos) /**< (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 Mask */ +#define PWM_OSCUPD_OSCUPL3(value) (PWM_OSCUPD_OSCUPL3_Msk & ((value) << PWM_OSCUPD_OSCUPL3_Pos)) +#define PWM_OSCUPD_Msk _U_(0x000F000F) /**< (PWM_OSCUPD) Register Mask */ + +#define PWM_OSCUPD_OSCUPH_Pos _U_(0) /**< (PWM_OSCUPD Position) Output Selection Clear for PWMH output of the channel x */ +#define PWM_OSCUPD_OSCUPH_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPH_Pos) /**< (PWM_OSCUPD Mask) OSCUPH */ +#define PWM_OSCUPD_OSCUPH(value) (PWM_OSCUPD_OSCUPH_Msk & ((value) << PWM_OSCUPD_OSCUPH_Pos)) +#define PWM_OSCUPD_OSCUPL_Pos _U_(16) /**< (PWM_OSCUPD Position) Output Selection Clear for PWML output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL_Msk (_U_(0xF) << PWM_OSCUPD_OSCUPL_Pos) /**< (PWM_OSCUPD Mask) OSCUPL */ +#define PWM_OSCUPD_OSCUPL(value) (PWM_OSCUPD_OSCUPL_Msk & ((value) << PWM_OSCUPD_OSCUPL_Pos)) + +/* -------- PWM_FMR : (PWM Offset: 0x5C) (R/W 32) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos _U_(0) /**< (PWM_FMR) Fault Polarity Position */ +#define PWM_FMR_FPOL_Msk (_U_(0xFF) << PWM_FMR_FPOL_Pos) /**< (PWM_FMR) Fault Polarity Mask */ +#define PWM_FMR_FPOL(value) (PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)) +#define PWM_FMR_FMOD_Pos _U_(8) /**< (PWM_FMR) Fault Activation Mode Position */ +#define PWM_FMR_FMOD_Msk (_U_(0xFF) << PWM_FMR_FMOD_Pos) /**< (PWM_FMR) Fault Activation Mode Mask */ +#define PWM_FMR_FMOD(value) (PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)) +#define PWM_FMR_FFIL_Pos _U_(16) /**< (PWM_FMR) Fault Filtering Position */ +#define PWM_FMR_FFIL_Msk (_U_(0xFF) << PWM_FMR_FFIL_Pos) /**< (PWM_FMR) Fault Filtering Mask */ +#define PWM_FMR_FFIL(value) (PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)) +#define PWM_FMR_Msk _U_(0x00FFFFFF) /**< (PWM_FMR) Register Mask */ + + +/* -------- PWM_FSR : (PWM Offset: 0x60) ( R/ 32) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos _U_(0) /**< (PWM_FSR) Fault Input Value Position */ +#define PWM_FSR_FIV_Msk (_U_(0xFF) << PWM_FSR_FIV_Pos) /**< (PWM_FSR) Fault Input Value Mask */ +#define PWM_FSR_FIV(value) (PWM_FSR_FIV_Msk & ((value) << PWM_FSR_FIV_Pos)) +#define PWM_FSR_FS_Pos _U_(8) /**< (PWM_FSR) Fault Status Position */ +#define PWM_FSR_FS_Msk (_U_(0xFF) << PWM_FSR_FS_Pos) /**< (PWM_FSR) Fault Status Mask */ +#define PWM_FSR_FS(value) (PWM_FSR_FS_Msk & ((value) << PWM_FSR_FS_Pos)) +#define PWM_FSR_Msk _U_(0x0000FFFF) /**< (PWM_FSR) Register Mask */ + + +/* -------- PWM_FCR : (PWM Offset: 0x64) ( /W 32) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos _U_(0) /**< (PWM_FCR) Fault Clear Position */ +#define PWM_FCR_FCLR_Msk (_U_(0xFF) << PWM_FCR_FCLR_Pos) /**< (PWM_FCR) Fault Clear Mask */ +#define PWM_FCR_FCLR(value) (PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)) +#define PWM_FCR_Msk _U_(0x000000FF) /**< (PWM_FCR) Register Mask */ + + +/* -------- PWM_FPV1 : (PWM Offset: 0x68) (R/W 32) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0_Pos _U_(0) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Position */ +#define PWM_FPV1_FPVH0_Msk (_U_(0x1) << PWM_FPV1_FPVH0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 Mask */ +#define PWM_FPV1_FPVH0(value) (PWM_FPV1_FPVH0_Msk & ((value) << PWM_FPV1_FPVH0_Pos)) +#define PWM_FPV1_FPVH1_Pos _U_(1) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Position */ +#define PWM_FPV1_FPVH1_Msk (_U_(0x1) << PWM_FPV1_FPVH1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 Mask */ +#define PWM_FPV1_FPVH1(value) (PWM_FPV1_FPVH1_Msk & ((value) << PWM_FPV1_FPVH1_Pos)) +#define PWM_FPV1_FPVH2_Pos _U_(2) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Position */ +#define PWM_FPV1_FPVH2_Msk (_U_(0x1) << PWM_FPV1_FPVH2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 Mask */ +#define PWM_FPV1_FPVH2(value) (PWM_FPV1_FPVH2_Msk & ((value) << PWM_FPV1_FPVH2_Pos)) +#define PWM_FPV1_FPVH3_Pos _U_(3) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Position */ +#define PWM_FPV1_FPVH3_Msk (_U_(0x1) << PWM_FPV1_FPVH3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 Mask */ +#define PWM_FPV1_FPVH3(value) (PWM_FPV1_FPVH3_Msk & ((value) << PWM_FPV1_FPVH3_Pos)) +#define PWM_FPV1_FPVL0_Pos _U_(16) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Position */ +#define PWM_FPV1_FPVL0_Msk (_U_(0x1) << PWM_FPV1_FPVL0_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 0 Mask */ +#define PWM_FPV1_FPVL0(value) (PWM_FPV1_FPVL0_Msk & ((value) << PWM_FPV1_FPVL0_Pos)) +#define PWM_FPV1_FPVL1_Pos _U_(17) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Position */ +#define PWM_FPV1_FPVL1_Msk (_U_(0x1) << PWM_FPV1_FPVL1_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 1 Mask */ +#define PWM_FPV1_FPVL1(value) (PWM_FPV1_FPVL1_Msk & ((value) << PWM_FPV1_FPVL1_Pos)) +#define PWM_FPV1_FPVL2_Pos _U_(18) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Position */ +#define PWM_FPV1_FPVL2_Msk (_U_(0x1) << PWM_FPV1_FPVL2_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 2 Mask */ +#define PWM_FPV1_FPVL2(value) (PWM_FPV1_FPVL2_Msk & ((value) << PWM_FPV1_FPVL2_Pos)) +#define PWM_FPV1_FPVL3_Pos _U_(19) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Position */ +#define PWM_FPV1_FPVL3_Msk (_U_(0x1) << PWM_FPV1_FPVL3_Pos) /**< (PWM_FPV1) Fault Protection Value for PWML output on channel 3 Mask */ +#define PWM_FPV1_FPVL3(value) (PWM_FPV1_FPVL3_Msk & ((value) << PWM_FPV1_FPVL3_Pos)) +#define PWM_FPV1_Msk _U_(0x000F000F) /**< (PWM_FPV1) Register Mask */ + +#define PWM_FPV1_FPVH_Pos _U_(0) /**< (PWM_FPV1 Position) Fault Protection Value for PWMH output on channel x */ +#define PWM_FPV1_FPVH_Msk (_U_(0xF) << PWM_FPV1_FPVH_Pos) /**< (PWM_FPV1 Mask) FPVH */ +#define PWM_FPV1_FPVH(value) (PWM_FPV1_FPVH_Msk & ((value) << PWM_FPV1_FPVH_Pos)) +#define PWM_FPV1_FPVL_Pos _U_(16) /**< (PWM_FPV1 Position) Fault Protection Value for PWML output on channel 3 */ +#define PWM_FPV1_FPVL_Msk (_U_(0xF) << PWM_FPV1_FPVL_Pos) /**< (PWM_FPV1 Mask) FPVL */ +#define PWM_FPV1_FPVL(value) (PWM_FPV1_FPVL_Msk & ((value) << PWM_FPV1_FPVL_Pos)) + +/* -------- PWM_FPE : (PWM Offset: 0x6C) (R/W 32) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos _U_(0) /**< (PWM_FPE) Fault Protection Enable for channel 0 Position */ +#define PWM_FPE_FPE0_Msk (_U_(0xFF) << PWM_FPE_FPE0_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 0 Mask */ +#define PWM_FPE_FPE0(value) (PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)) +#define PWM_FPE_FPE1_Pos _U_(8) /**< (PWM_FPE) Fault Protection Enable for channel 1 Position */ +#define PWM_FPE_FPE1_Msk (_U_(0xFF) << PWM_FPE_FPE1_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 1 Mask */ +#define PWM_FPE_FPE1(value) (PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)) +#define PWM_FPE_FPE2_Pos _U_(16) /**< (PWM_FPE) Fault Protection Enable for channel 2 Position */ +#define PWM_FPE_FPE2_Msk (_U_(0xFF) << PWM_FPE_FPE2_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 2 Mask */ +#define PWM_FPE_FPE2(value) (PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)) +#define PWM_FPE_FPE3_Pos _U_(24) /**< (PWM_FPE) Fault Protection Enable for channel 3 Position */ +#define PWM_FPE_FPE3_Msk (_U_(0xFF) << PWM_FPE_FPE3_Pos) /**< (PWM_FPE) Fault Protection Enable for channel 3 Mask */ +#define PWM_FPE_FPE3(value) (PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)) +#define PWM_FPE_Msk _U_(0xFFFFFFFF) /**< (PWM_FPE) Register Mask */ + + +/* -------- PWM_ELMR : (PWM Offset: 0x7C) (R/W 32) PWM Event Line 0 Mode Register 0 -------- */ +#define PWM_ELMR_CSEL0_Pos _U_(0) /**< (PWM_ELMR) Comparison 0 Selection Position */ +#define PWM_ELMR_CSEL0_Msk (_U_(0x1) << PWM_ELMR_CSEL0_Pos) /**< (PWM_ELMR) Comparison 0 Selection Mask */ +#define PWM_ELMR_CSEL0(value) (PWM_ELMR_CSEL0_Msk & ((value) << PWM_ELMR_CSEL0_Pos)) +#define PWM_ELMR_CSEL1_Pos _U_(1) /**< (PWM_ELMR) Comparison 1 Selection Position */ +#define PWM_ELMR_CSEL1_Msk (_U_(0x1) << PWM_ELMR_CSEL1_Pos) /**< (PWM_ELMR) Comparison 1 Selection Mask */ +#define PWM_ELMR_CSEL1(value) (PWM_ELMR_CSEL1_Msk & ((value) << PWM_ELMR_CSEL1_Pos)) +#define PWM_ELMR_CSEL2_Pos _U_(2) /**< (PWM_ELMR) Comparison 2 Selection Position */ +#define PWM_ELMR_CSEL2_Msk (_U_(0x1) << PWM_ELMR_CSEL2_Pos) /**< (PWM_ELMR) Comparison 2 Selection Mask */ +#define PWM_ELMR_CSEL2(value) (PWM_ELMR_CSEL2_Msk & ((value) << PWM_ELMR_CSEL2_Pos)) +#define PWM_ELMR_CSEL3_Pos _U_(3) /**< (PWM_ELMR) Comparison 3 Selection Position */ +#define PWM_ELMR_CSEL3_Msk (_U_(0x1) << PWM_ELMR_CSEL3_Pos) /**< (PWM_ELMR) Comparison 3 Selection Mask */ +#define PWM_ELMR_CSEL3(value) (PWM_ELMR_CSEL3_Msk & ((value) << PWM_ELMR_CSEL3_Pos)) +#define PWM_ELMR_CSEL4_Pos _U_(4) /**< (PWM_ELMR) Comparison 4 Selection Position */ +#define PWM_ELMR_CSEL4_Msk (_U_(0x1) << PWM_ELMR_CSEL4_Pos) /**< (PWM_ELMR) Comparison 4 Selection Mask */ +#define PWM_ELMR_CSEL4(value) (PWM_ELMR_CSEL4_Msk & ((value) << PWM_ELMR_CSEL4_Pos)) +#define PWM_ELMR_CSEL5_Pos _U_(5) /**< (PWM_ELMR) Comparison 5 Selection Position */ +#define PWM_ELMR_CSEL5_Msk (_U_(0x1) << PWM_ELMR_CSEL5_Pos) /**< (PWM_ELMR) Comparison 5 Selection Mask */ +#define PWM_ELMR_CSEL5(value) (PWM_ELMR_CSEL5_Msk & ((value) << PWM_ELMR_CSEL5_Pos)) +#define PWM_ELMR_CSEL6_Pos _U_(6) /**< (PWM_ELMR) Comparison 6 Selection Position */ +#define PWM_ELMR_CSEL6_Msk (_U_(0x1) << PWM_ELMR_CSEL6_Pos) /**< (PWM_ELMR) Comparison 6 Selection Mask */ +#define PWM_ELMR_CSEL6(value) (PWM_ELMR_CSEL6_Msk & ((value) << PWM_ELMR_CSEL6_Pos)) +#define PWM_ELMR_CSEL7_Pos _U_(7) /**< (PWM_ELMR) Comparison 7 Selection Position */ +#define PWM_ELMR_CSEL7_Msk (_U_(0x1) << PWM_ELMR_CSEL7_Pos) /**< (PWM_ELMR) Comparison 7 Selection Mask */ +#define PWM_ELMR_CSEL7(value) (PWM_ELMR_CSEL7_Msk & ((value) << PWM_ELMR_CSEL7_Pos)) +#define PWM_ELMR_Msk _U_(0x000000FF) /**< (PWM_ELMR) Register Mask */ + +#define PWM_ELMR_CSEL_Pos _U_(0) /**< (PWM_ELMR Position) Comparison 7 Selection */ +#define PWM_ELMR_CSEL_Msk (_U_(0xFF) << PWM_ELMR_CSEL_Pos) /**< (PWM_ELMR Mask) CSEL */ +#define PWM_ELMR_CSEL(value) (PWM_ELMR_CSEL_Msk & ((value) << PWM_ELMR_CSEL_Pos)) + +/* -------- PWM_SSPR : (PWM Offset: 0xA0) (R/W 32) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos _U_(0) /**< (PWM_SSPR) Spread Spectrum Limit Value Position */ +#define PWM_SSPR_SPRD_Msk (_U_(0xFFFFFF) << PWM_SSPR_SPRD_Pos) /**< (PWM_SSPR) Spread Spectrum Limit Value Mask */ +#define PWM_SSPR_SPRD(value) (PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)) +#define PWM_SSPR_SPRDM_Pos _U_(24) /**< (PWM_SSPR) Spread Spectrum Counter Mode Position */ +#define PWM_SSPR_SPRDM_Msk (_U_(0x1) << PWM_SSPR_SPRDM_Pos) /**< (PWM_SSPR) Spread Spectrum Counter Mode Mask */ +#define PWM_SSPR_SPRDM(value) (PWM_SSPR_SPRDM_Msk & ((value) << PWM_SSPR_SPRDM_Pos)) +#define PWM_SSPR_Msk _U_(0x01FFFFFF) /**< (PWM_SSPR) Register Mask */ + + +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) ( /W 32) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos _U_(0) /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Position */ +#define PWM_SSPUP_SPRDUP_Msk (_U_(0xFFFFFF) << PWM_SSPUP_SPRDUP_Pos) /**< (PWM_SSPUP) Spread Spectrum Limit Value Update Mask */ +#define PWM_SSPUP_SPRDUP(value) (PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)) +#define PWM_SSPUP_Msk _U_(0x00FFFFFF) /**< (PWM_SSPUP) Register Mask */ + + +/* -------- PWM_SMMR : (PWM Offset: 0xB0) (R/W 32) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0_Pos _U_(0) /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN0_Msk (_U_(0x1) << PWM_SMMR_GCEN0_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN0(value) (PWM_SMMR_GCEN0_Msk & ((value) << PWM_SMMR_GCEN0_Pos)) +#define PWM_SMMR_GCEN1_Pos _U_(1) /**< (PWM_SMMR) Gray Count ENable Position */ +#define PWM_SMMR_GCEN1_Msk (_U_(0x1) << PWM_SMMR_GCEN1_Pos) /**< (PWM_SMMR) Gray Count ENable Mask */ +#define PWM_SMMR_GCEN1(value) (PWM_SMMR_GCEN1_Msk & ((value) << PWM_SMMR_GCEN1_Pos)) +#define PWM_SMMR_DOWN0_Pos _U_(16) /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN0_Msk (_U_(0x1) << PWM_SMMR_DOWN0_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN0(value) (PWM_SMMR_DOWN0_Msk & ((value) << PWM_SMMR_DOWN0_Pos)) +#define PWM_SMMR_DOWN1_Pos _U_(17) /**< (PWM_SMMR) DOWN Count Position */ +#define PWM_SMMR_DOWN1_Msk (_U_(0x1) << PWM_SMMR_DOWN1_Pos) /**< (PWM_SMMR) DOWN Count Mask */ +#define PWM_SMMR_DOWN1(value) (PWM_SMMR_DOWN1_Msk & ((value) << PWM_SMMR_DOWN1_Pos)) +#define PWM_SMMR_Msk _U_(0x00030003) /**< (PWM_SMMR) Register Mask */ + +#define PWM_SMMR_GCEN_Pos _U_(0) /**< (PWM_SMMR Position) Gray Count ENable */ +#define PWM_SMMR_GCEN_Msk (_U_(0x3) << PWM_SMMR_GCEN_Pos) /**< (PWM_SMMR Mask) GCEN */ +#define PWM_SMMR_GCEN(value) (PWM_SMMR_GCEN_Msk & ((value) << PWM_SMMR_GCEN_Pos)) +#define PWM_SMMR_DOWN_Pos _U_(16) /**< (PWM_SMMR Position) DOWN Count */ +#define PWM_SMMR_DOWN_Msk (_U_(0x3) << PWM_SMMR_DOWN_Pos) /**< (PWM_SMMR Mask) DOWN */ +#define PWM_SMMR_DOWN(value) (PWM_SMMR_DOWN_Msk & ((value) << PWM_SMMR_DOWN_Pos)) + +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) (R/W 32) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0_Pos _U_(0) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Position */ +#define PWM_FPV2_FPZH0_Msk (_U_(0x1) << PWM_FPV2_FPZH0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 Mask */ +#define PWM_FPV2_FPZH0(value) (PWM_FPV2_FPZH0_Msk & ((value) << PWM_FPV2_FPZH0_Pos)) +#define PWM_FPV2_FPZH1_Pos _U_(1) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Position */ +#define PWM_FPV2_FPZH1_Msk (_U_(0x1) << PWM_FPV2_FPZH1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 Mask */ +#define PWM_FPV2_FPZH1(value) (PWM_FPV2_FPZH1_Msk & ((value) << PWM_FPV2_FPZH1_Pos)) +#define PWM_FPV2_FPZH2_Pos _U_(2) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Position */ +#define PWM_FPV2_FPZH2_Msk (_U_(0x1) << PWM_FPV2_FPZH2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 Mask */ +#define PWM_FPV2_FPZH2(value) (PWM_FPV2_FPZH2_Msk & ((value) << PWM_FPV2_FPZH2_Pos)) +#define PWM_FPV2_FPZH3_Pos _U_(3) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Position */ +#define PWM_FPV2_FPZH3_Msk (_U_(0x1) << PWM_FPV2_FPZH3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 Mask */ +#define PWM_FPV2_FPZH3(value) (PWM_FPV2_FPZH3_Msk & ((value) << PWM_FPV2_FPZH3_Pos)) +#define PWM_FPV2_FPZL0_Pos _U_(16) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Position */ +#define PWM_FPV2_FPZL0_Msk (_U_(0x1) << PWM_FPV2_FPZL0_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 Mask */ +#define PWM_FPV2_FPZL0(value) (PWM_FPV2_FPZL0_Msk & ((value) << PWM_FPV2_FPZL0_Pos)) +#define PWM_FPV2_FPZL1_Pos _U_(17) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Position */ +#define PWM_FPV2_FPZL1_Msk (_U_(0x1) << PWM_FPV2_FPZL1_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 Mask */ +#define PWM_FPV2_FPZL1(value) (PWM_FPV2_FPZL1_Msk & ((value) << PWM_FPV2_FPZL1_Pos)) +#define PWM_FPV2_FPZL2_Pos _U_(18) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Position */ +#define PWM_FPV2_FPZL2_Msk (_U_(0x1) << PWM_FPV2_FPZL2_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 Mask */ +#define PWM_FPV2_FPZL2(value) (PWM_FPV2_FPZL2_Msk & ((value) << PWM_FPV2_FPZL2_Pos)) +#define PWM_FPV2_FPZL3_Pos _U_(19) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Position */ +#define PWM_FPV2_FPZL3_Msk (_U_(0x1) << PWM_FPV2_FPZL3_Pos) /**< (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 Mask */ +#define PWM_FPV2_FPZL3(value) (PWM_FPV2_FPZL3_Msk & ((value) << PWM_FPV2_FPZL3_Pos)) +#define PWM_FPV2_Msk _U_(0x000F000F) /**< (PWM_FPV2) Register Mask */ + +#define PWM_FPV2_FPZH_Pos _U_(0) /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWMH output on channel x */ +#define PWM_FPV2_FPZH_Msk (_U_(0xF) << PWM_FPV2_FPZH_Pos) /**< (PWM_FPV2 Mask) FPZH */ +#define PWM_FPV2_FPZH(value) (PWM_FPV2_FPZH_Msk & ((value) << PWM_FPV2_FPZH_Pos)) +#define PWM_FPV2_FPZL_Pos _U_(16) /**< (PWM_FPV2 Position) Fault Protection to Hi-Z for PWML output on channel 3 */ +#define PWM_FPV2_FPZL_Msk (_U_(0xF) << PWM_FPV2_FPZL_Pos) /**< (PWM_FPV2 Mask) FPZL */ +#define PWM_FPV2_FPZL(value) (PWM_FPV2_FPZL_Msk & ((value) << PWM_FPV2_FPZL_Pos)) + +/* -------- PWM_WPCR : (PWM Offset: 0xE4) ( /W 32) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos _U_(0) /**< (PWM_WPCR) Write Protection Command Position */ +#define PWM_WPCR_WPCMD_Msk (_U_(0x3) << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Write Protection Command Mask */ +#define PWM_WPCR_WPCMD(value) (PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val _U_(0x0) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val _U_(0x1) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val _U_(0x2) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (PWM_WPCR_WPCMD_DISABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (PWM_WPCR_WPCMD_ENABLE_SW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. Position */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (PWM_WPCR_WPCMD_ENABLE_HW_PROT_Val << PWM_WPCR_WPCMD_Pos) /**< (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. Position */ +#define PWM_WPCR_WPRG0_Pos _U_(2) /**< (PWM_WPCR) Write Protection Register Group 0 Position */ +#define PWM_WPCR_WPRG0_Msk (_U_(0x1) << PWM_WPCR_WPRG0_Pos) /**< (PWM_WPCR) Write Protection Register Group 0 Mask */ +#define PWM_WPCR_WPRG0(value) (PWM_WPCR_WPRG0_Msk & ((value) << PWM_WPCR_WPRG0_Pos)) +#define PWM_WPCR_WPRG1_Pos _U_(3) /**< (PWM_WPCR) Write Protection Register Group 1 Position */ +#define PWM_WPCR_WPRG1_Msk (_U_(0x1) << PWM_WPCR_WPRG1_Pos) /**< (PWM_WPCR) Write Protection Register Group 1 Mask */ +#define PWM_WPCR_WPRG1(value) (PWM_WPCR_WPRG1_Msk & ((value) << PWM_WPCR_WPRG1_Pos)) +#define PWM_WPCR_WPRG2_Pos _U_(4) /**< (PWM_WPCR) Write Protection Register Group 2 Position */ +#define PWM_WPCR_WPRG2_Msk (_U_(0x1) << PWM_WPCR_WPRG2_Pos) /**< (PWM_WPCR) Write Protection Register Group 2 Mask */ +#define PWM_WPCR_WPRG2(value) (PWM_WPCR_WPRG2_Msk & ((value) << PWM_WPCR_WPRG2_Pos)) +#define PWM_WPCR_WPRG3_Pos _U_(5) /**< (PWM_WPCR) Write Protection Register Group 3 Position */ +#define PWM_WPCR_WPRG3_Msk (_U_(0x1) << PWM_WPCR_WPRG3_Pos) /**< (PWM_WPCR) Write Protection Register Group 3 Mask */ +#define PWM_WPCR_WPRG3(value) (PWM_WPCR_WPRG3_Msk & ((value) << PWM_WPCR_WPRG3_Pos)) +#define PWM_WPCR_WPRG4_Pos _U_(6) /**< (PWM_WPCR) Write Protection Register Group 4 Position */ +#define PWM_WPCR_WPRG4_Msk (_U_(0x1) << PWM_WPCR_WPRG4_Pos) /**< (PWM_WPCR) Write Protection Register Group 4 Mask */ +#define PWM_WPCR_WPRG4(value) (PWM_WPCR_WPRG4_Msk & ((value) << PWM_WPCR_WPRG4_Pos)) +#define PWM_WPCR_WPRG5_Pos _U_(7) /**< (PWM_WPCR) Write Protection Register Group 5 Position */ +#define PWM_WPCR_WPRG5_Msk (_U_(0x1) << PWM_WPCR_WPRG5_Pos) /**< (PWM_WPCR) Write Protection Register Group 5 Mask */ +#define PWM_WPCR_WPRG5(value) (PWM_WPCR_WPRG5_Msk & ((value) << PWM_WPCR_WPRG5_Pos)) +#define PWM_WPCR_WPKEY_Pos _U_(8) /**< (PWM_WPCR) Write Protection Key Position */ +#define PWM_WPCR_WPKEY_Msk (_U_(0xFFFFFF) << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Write Protection Key Mask */ +#define PWM_WPCR_WPKEY(value) (PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)) +#define PWM_WPCR_WPKEY_PASSWD_Val _U_(0x50574D) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +#define PWM_WPCR_WPKEY_PASSWD (PWM_WPCR_WPKEY_PASSWD_Val << PWM_WPCR_WPKEY_Pos) /**< (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 Position */ +#define PWM_WPCR_Msk _U_(0xFFFFFFFF) /**< (PWM_WPCR) Register Mask */ + +#define PWM_WPCR_WPRG_Pos _U_(2) /**< (PWM_WPCR Position) Write Protection Register Group x */ +#define PWM_WPCR_WPRG_Msk (_U_(0x3F) << PWM_WPCR_WPRG_Pos) /**< (PWM_WPCR Mask) WPRG */ +#define PWM_WPCR_WPRG(value) (PWM_WPCR_WPRG_Msk & ((value) << PWM_WPCR_WPRG_Pos)) + +/* -------- PWM_WPSR : (PWM Offset: 0xE8) ( R/ 32) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0_Pos _U_(0) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS0_Msk (_U_(0x1) << PWM_WPSR_WPSWS0_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS0(value) (PWM_WPSR_WPSWS0_Msk & ((value) << PWM_WPSR_WPSWS0_Pos)) +#define PWM_WPSR_WPSWS1_Pos _U_(1) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS1_Msk (_U_(0x1) << PWM_WPSR_WPSWS1_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS1(value) (PWM_WPSR_WPSWS1_Msk & ((value) << PWM_WPSR_WPSWS1_Pos)) +#define PWM_WPSR_WPSWS2_Pos _U_(2) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS2_Msk (_U_(0x1) << PWM_WPSR_WPSWS2_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS2(value) (PWM_WPSR_WPSWS2_Msk & ((value) << PWM_WPSR_WPSWS2_Pos)) +#define PWM_WPSR_WPSWS3_Pos _U_(3) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS3_Msk (_U_(0x1) << PWM_WPSR_WPSWS3_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS3(value) (PWM_WPSR_WPSWS3_Msk & ((value) << PWM_WPSR_WPSWS3_Pos)) +#define PWM_WPSR_WPSWS4_Pos _U_(4) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS4_Msk (_U_(0x1) << PWM_WPSR_WPSWS4_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS4(value) (PWM_WPSR_WPSWS4_Msk & ((value) << PWM_WPSR_WPSWS4_Pos)) +#define PWM_WPSR_WPSWS5_Pos _U_(5) /**< (PWM_WPSR) Write Protect SW Status Position */ +#define PWM_WPSR_WPSWS5_Msk (_U_(0x1) << PWM_WPSR_WPSWS5_Pos) /**< (PWM_WPSR) Write Protect SW Status Mask */ +#define PWM_WPSR_WPSWS5(value) (PWM_WPSR_WPSWS5_Msk & ((value) << PWM_WPSR_WPSWS5_Pos)) +#define PWM_WPSR_WPVS_Pos _U_(7) /**< (PWM_WPSR) Write Protect Violation Status Position */ +#define PWM_WPSR_WPVS_Msk (_U_(0x1) << PWM_WPSR_WPVS_Pos) /**< (PWM_WPSR) Write Protect Violation Status Mask */ +#define PWM_WPSR_WPVS(value) (PWM_WPSR_WPVS_Msk & ((value) << PWM_WPSR_WPVS_Pos)) +#define PWM_WPSR_WPHWS0_Pos _U_(8) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS0_Msk (_U_(0x1) << PWM_WPSR_WPHWS0_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS0(value) (PWM_WPSR_WPHWS0_Msk & ((value) << PWM_WPSR_WPHWS0_Pos)) +#define PWM_WPSR_WPHWS1_Pos _U_(9) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS1_Msk (_U_(0x1) << PWM_WPSR_WPHWS1_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS1(value) (PWM_WPSR_WPHWS1_Msk & ((value) << PWM_WPSR_WPHWS1_Pos)) +#define PWM_WPSR_WPHWS2_Pos _U_(10) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS2_Msk (_U_(0x1) << PWM_WPSR_WPHWS2_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS2(value) (PWM_WPSR_WPHWS2_Msk & ((value) << PWM_WPSR_WPHWS2_Pos)) +#define PWM_WPSR_WPHWS3_Pos _U_(11) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS3_Msk (_U_(0x1) << PWM_WPSR_WPHWS3_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS3(value) (PWM_WPSR_WPHWS3_Msk & ((value) << PWM_WPSR_WPHWS3_Pos)) +#define PWM_WPSR_WPHWS4_Pos _U_(12) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS4_Msk (_U_(0x1) << PWM_WPSR_WPHWS4_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS4(value) (PWM_WPSR_WPHWS4_Msk & ((value) << PWM_WPSR_WPHWS4_Pos)) +#define PWM_WPSR_WPHWS5_Pos _U_(13) /**< (PWM_WPSR) Write Protect HW Status Position */ +#define PWM_WPSR_WPHWS5_Msk (_U_(0x1) << PWM_WPSR_WPHWS5_Pos) /**< (PWM_WPSR) Write Protect HW Status Mask */ +#define PWM_WPSR_WPHWS5(value) (PWM_WPSR_WPHWS5_Msk & ((value) << PWM_WPSR_WPHWS5_Pos)) +#define PWM_WPSR_WPVSRC_Pos _U_(16) /**< (PWM_WPSR) Write Protect Violation Source Position */ +#define PWM_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PWM_WPSR_WPVSRC_Pos) /**< (PWM_WPSR) Write Protect Violation Source Mask */ +#define PWM_WPSR_WPVSRC(value) (PWM_WPSR_WPVSRC_Msk & ((value) << PWM_WPSR_WPVSRC_Pos)) +#define PWM_WPSR_Msk _U_(0xFFFF3FBF) /**< (PWM_WPSR) Register Mask */ + +#define PWM_WPSR_WPSWS_Pos _U_(0) /**< (PWM_WPSR Position) Write Protect SW Status */ +#define PWM_WPSR_WPSWS_Msk (_U_(0x3F) << PWM_WPSR_WPSWS_Pos) /**< (PWM_WPSR Mask) WPSWS */ +#define PWM_WPSR_WPSWS(value) (PWM_WPSR_WPSWS_Msk & ((value) << PWM_WPSR_WPSWS_Pos)) +#define PWM_WPSR_WPHWS_Pos _U_(8) /**< (PWM_WPSR Position) Write Protect HW Status */ +#define PWM_WPSR_WPHWS_Msk (_U_(0x3F) << PWM_WPSR_WPHWS_Pos) /**< (PWM_WPSR Mask) WPHWS */ +#define PWM_WPSR_WPHWS(value) (PWM_WPSR_WPHWS_Msk & ((value) << PWM_WPSR_WPHWS_Pos)) + +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) ( /W 32) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD0) Channel Polarity Update Position */ +#define PWM_CMUPD0_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Update Mask */ +#define PWM_CMUPD0_CPOLUP(value) (PWM_CMUPD0_CPOLUP_Msk & ((value) << PWM_CMUPD0_CPOLUP_Pos)) +#define PWM_CMUPD0_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD0) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD0_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD0_CPOLINVUP_Pos) /**< (PWM_CMUPD0) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD0_CPOLINVUP(value) (PWM_CMUPD0_CPOLINVUP_Msk & ((value) << PWM_CMUPD0_CPOLINVUP_Pos)) +#define PWM_CMUPD0_Msk _U_(0x00002200) /**< (PWM_CMUPD0) Register Mask */ + + +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) ( /W 32) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD1) Channel Polarity Update Position */ +#define PWM_CMUPD1_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Update Mask */ +#define PWM_CMUPD1_CPOLUP(value) (PWM_CMUPD1_CPOLUP_Msk & ((value) << PWM_CMUPD1_CPOLUP_Pos)) +#define PWM_CMUPD1_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD1) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD1_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD1_CPOLINVUP_Pos) /**< (PWM_CMUPD1) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD1_CPOLINVUP(value) (PWM_CMUPD1_CPOLINVUP_Msk & ((value) << PWM_CMUPD1_CPOLINVUP_Pos)) +#define PWM_CMUPD1_Msk _U_(0x00002200) /**< (PWM_CMUPD1) Register Mask */ + + +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) (R/W 32) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos _U_(0) /**< (PWM_ETRG1) Maximum Counter value Position */ +#define PWM_ETRG1_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG1_MAXCNT_Pos) /**< (PWM_ETRG1) Maximum Counter value Mask */ +#define PWM_ETRG1_MAXCNT(value) (PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)) +#define PWM_ETRG1_TRGMODE_Pos _U_(24) /**< (PWM_ETRG1) External Trigger Mode Position */ +#define PWM_ETRG1_TRGMODE_Msk (_U_(0x3) << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External Trigger Mode Mask */ +#define PWM_ETRG1_TRGMODE(value) (PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)) +#define PWM_ETRG1_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGMODE_OFF (PWM_ETRG1_TRGMODE_OFF_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External trigger is not enabled. Position */ +#define PWM_ETRG1_TRGMODE_MODE1 (PWM_ETRG1_TRGMODE_MODE1_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Reset Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE2 (PWM_ETRG1_TRGMODE_MODE2_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) External PWM Start Mode Position */ +#define PWM_ETRG1_TRGMODE_MODE3 (PWM_ETRG1_TRGMODE_MODE3_Val << PWM_ETRG1_TRGMODE_Pos) /**< (PWM_ETRG1) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG1_TRGEDGE_Pos _U_(28) /**< (PWM_ETRG1) Edge Selection Position */ +#define PWM_ETRG1_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) Edge Selection Mask */ +#define PWM_ETRG1_TRGEDGE(value) (PWM_ETRG1_TRGEDGE_Msk & ((value) << PWM_ETRG1_TRGEDGE_Pos)) +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (PWM_ETRG1_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (PWM_ETRG1_TRGEDGE_RISING_ONE_Val << PWM_ETRG1_TRGEDGE_Pos) /**< (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG1_TRGFILT_Pos _U_(29) /**< (PWM_ETRG1) Filtered input Position */ +#define PWM_ETRG1_TRGFILT_Msk (_U_(0x1) << PWM_ETRG1_TRGFILT_Pos) /**< (PWM_ETRG1) Filtered input Mask */ +#define PWM_ETRG1_TRGFILT(value) (PWM_ETRG1_TRGFILT_Msk & ((value) << PWM_ETRG1_TRGFILT_Pos)) +#define PWM_ETRG1_TRGSRC_Pos _U_(30) /**< (PWM_ETRG1) Trigger Source Position */ +#define PWM_ETRG1_TRGSRC_Msk (_U_(0x1) << PWM_ETRG1_TRGSRC_Pos) /**< (PWM_ETRG1) Trigger Source Mask */ +#define PWM_ETRG1_TRGSRC(value) (PWM_ETRG1_TRGSRC_Msk & ((value) << PWM_ETRG1_TRGSRC_Pos)) +#define PWM_ETRG1_RFEN_Pos _U_(31) /**< (PWM_ETRG1) Recoverable Fault Enable Position */ +#define PWM_ETRG1_RFEN_Msk (_U_(0x1) << PWM_ETRG1_RFEN_Pos) /**< (PWM_ETRG1) Recoverable Fault Enable Mask */ +#define PWM_ETRG1_RFEN(value) (PWM_ETRG1_RFEN_Msk & ((value) << PWM_ETRG1_RFEN_Pos)) +#define PWM_ETRG1_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG1) Register Mask */ + + +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos _U_(0) /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR1_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR1_LEBDELAY_Pos) /**< (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR1_LEBDELAY(value) (PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)) +#define PWM_LEBR1_PWMLFEN_Pos _U_(16) /**< (PWM_LEBR1) PWML Falling Edge Enable Position */ +#define PWM_LEBR1_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMLFEN_Pos) /**< (PWM_LEBR1) PWML Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMLFEN(value) (PWM_LEBR1_PWMLFEN_Msk & ((value) << PWM_LEBR1_PWMLFEN_Pos)) +#define PWM_LEBR1_PWMLREN_Pos _U_(17) /**< (PWM_LEBR1) PWML Rising Edge Enable Position */ +#define PWM_LEBR1_PWMLREN_Msk (_U_(0x1) << PWM_LEBR1_PWMLREN_Pos) /**< (PWM_LEBR1) PWML Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMLREN(value) (PWM_LEBR1_PWMLREN_Msk & ((value) << PWM_LEBR1_PWMLREN_Pos)) +#define PWM_LEBR1_PWMHFEN_Pos _U_(18) /**< (PWM_LEBR1) PWMH Falling Edge Enable Position */ +#define PWM_LEBR1_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR1_PWMHFEN_Pos) /**< (PWM_LEBR1) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR1_PWMHFEN(value) (PWM_LEBR1_PWMHFEN_Msk & ((value) << PWM_LEBR1_PWMHFEN_Pos)) +#define PWM_LEBR1_PWMHREN_Pos _U_(19) /**< (PWM_LEBR1) PWMH Rising Edge Enable Position */ +#define PWM_LEBR1_PWMHREN_Msk (_U_(0x1) << PWM_LEBR1_PWMHREN_Pos) /**< (PWM_LEBR1) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR1_PWMHREN(value) (PWM_LEBR1_PWMHREN_Msk & ((value) << PWM_LEBR1_PWMHREN_Pos)) +#define PWM_LEBR1_Msk _U_(0x000F007F) /**< (PWM_LEBR1) Register Mask */ + + +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) ( /W 32) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD2) Channel Polarity Update Position */ +#define PWM_CMUPD2_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Update Mask */ +#define PWM_CMUPD2_CPOLUP(value) (PWM_CMUPD2_CPOLUP_Msk & ((value) << PWM_CMUPD2_CPOLUP_Pos)) +#define PWM_CMUPD2_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD2) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD2_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD2_CPOLINVUP_Pos) /**< (PWM_CMUPD2) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD2_CPOLINVUP(value) (PWM_CMUPD2_CPOLINVUP_Msk & ((value) << PWM_CMUPD2_CPOLINVUP_Pos)) +#define PWM_CMUPD2_Msk _U_(0x00002200) /**< (PWM_CMUPD2) Register Mask */ + + +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) (R/W 32) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos _U_(0) /**< (PWM_ETRG2) Maximum Counter value Position */ +#define PWM_ETRG2_MAXCNT_Msk (_U_(0xFFFFFF) << PWM_ETRG2_MAXCNT_Pos) /**< (PWM_ETRG2) Maximum Counter value Mask */ +#define PWM_ETRG2_MAXCNT(value) (PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)) +#define PWM_ETRG2_TRGMODE_Pos _U_(24) /**< (PWM_ETRG2) External Trigger Mode Position */ +#define PWM_ETRG2_TRGMODE_Msk (_U_(0x3) << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External Trigger Mode Mask */ +#define PWM_ETRG2_TRGMODE(value) (PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)) +#define PWM_ETRG2_TRGMODE_OFF_Val _U_(0x0) /**< (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1_Val _U_(0x1) /**< (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2_Val _U_(0x2) /**< (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3_Val _U_(0x3) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGMODE_OFF (PWM_ETRG2_TRGMODE_OFF_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External trigger is not enabled. Position */ +#define PWM_ETRG2_TRGMODE_MODE1 (PWM_ETRG2_TRGMODE_MODE1_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Reset Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE2 (PWM_ETRG2_TRGMODE_MODE2_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) External PWM Start Mode Position */ +#define PWM_ETRG2_TRGMODE_MODE3 (PWM_ETRG2_TRGMODE_MODE3_Val << PWM_ETRG2_TRGMODE_Pos) /**< (PWM_ETRG2) Cycle-by-cycle Duty Mode Position */ +#define PWM_ETRG2_TRGEDGE_Pos _U_(28) /**< (PWM_ETRG2) Edge Selection Position */ +#define PWM_ETRG2_TRGEDGE_Msk (_U_(0x1) << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) Edge Selection Mask */ +#define PWM_ETRG2_TRGEDGE(value) (PWM_ETRG2_TRGEDGE_Msk & ((value) << PWM_ETRG2_TRGEDGE_Pos)) +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val _U_(0x0) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE_Val _U_(0x1) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (PWM_ETRG2_TRGEDGE_FALLING_ZERO_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 Position */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (PWM_ETRG2_TRGEDGE_RISING_ONE_Val << PWM_ETRG2_TRGEDGE_Pos) /**< (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 Position */ +#define PWM_ETRG2_TRGFILT_Pos _U_(29) /**< (PWM_ETRG2) Filtered input Position */ +#define PWM_ETRG2_TRGFILT_Msk (_U_(0x1) << PWM_ETRG2_TRGFILT_Pos) /**< (PWM_ETRG2) Filtered input Mask */ +#define PWM_ETRG2_TRGFILT(value) (PWM_ETRG2_TRGFILT_Msk & ((value) << PWM_ETRG2_TRGFILT_Pos)) +#define PWM_ETRG2_TRGSRC_Pos _U_(30) /**< (PWM_ETRG2) Trigger Source Position */ +#define PWM_ETRG2_TRGSRC_Msk (_U_(0x1) << PWM_ETRG2_TRGSRC_Pos) /**< (PWM_ETRG2) Trigger Source Mask */ +#define PWM_ETRG2_TRGSRC(value) (PWM_ETRG2_TRGSRC_Msk & ((value) << PWM_ETRG2_TRGSRC_Pos)) +#define PWM_ETRG2_RFEN_Pos _U_(31) /**< (PWM_ETRG2) Recoverable Fault Enable Position */ +#define PWM_ETRG2_RFEN_Msk (_U_(0x1) << PWM_ETRG2_RFEN_Pos) /**< (PWM_ETRG2) Recoverable Fault Enable Mask */ +#define PWM_ETRG2_RFEN(value) (PWM_ETRG2_RFEN_Msk & ((value) << PWM_ETRG2_RFEN_Pos)) +#define PWM_ETRG2_Msk _U_(0xF3FFFFFF) /**< (PWM_ETRG2) Register Mask */ + + +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos _U_(0) /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Position */ +#define PWM_LEBR2_LEBDELAY_Msk (_U_(0x7F) << PWM_LEBR2_LEBDELAY_Pos) /**< (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx Mask */ +#define PWM_LEBR2_LEBDELAY(value) (PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)) +#define PWM_LEBR2_PWMLFEN_Pos _U_(16) /**< (PWM_LEBR2) PWML Falling Edge Enable Position */ +#define PWM_LEBR2_PWMLFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMLFEN_Pos) /**< (PWM_LEBR2) PWML Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMLFEN(value) (PWM_LEBR2_PWMLFEN_Msk & ((value) << PWM_LEBR2_PWMLFEN_Pos)) +#define PWM_LEBR2_PWMLREN_Pos _U_(17) /**< (PWM_LEBR2) PWML Rising Edge Enable Position */ +#define PWM_LEBR2_PWMLREN_Msk (_U_(0x1) << PWM_LEBR2_PWMLREN_Pos) /**< (PWM_LEBR2) PWML Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMLREN(value) (PWM_LEBR2_PWMLREN_Msk & ((value) << PWM_LEBR2_PWMLREN_Pos)) +#define PWM_LEBR2_PWMHFEN_Pos _U_(18) /**< (PWM_LEBR2) PWMH Falling Edge Enable Position */ +#define PWM_LEBR2_PWMHFEN_Msk (_U_(0x1) << PWM_LEBR2_PWMHFEN_Pos) /**< (PWM_LEBR2) PWMH Falling Edge Enable Mask */ +#define PWM_LEBR2_PWMHFEN(value) (PWM_LEBR2_PWMHFEN_Msk & ((value) << PWM_LEBR2_PWMHFEN_Pos)) +#define PWM_LEBR2_PWMHREN_Pos _U_(19) /**< (PWM_LEBR2) PWMH Rising Edge Enable Position */ +#define PWM_LEBR2_PWMHREN_Msk (_U_(0x1) << PWM_LEBR2_PWMHREN_Pos) /**< (PWM_LEBR2) PWMH Rising Edge Enable Mask */ +#define PWM_LEBR2_PWMHREN(value) (PWM_LEBR2_PWMHREN_Msk & ((value) << PWM_LEBR2_PWMHREN_Pos)) +#define PWM_LEBR2_Msk _U_(0x000F007F) /**< (PWM_LEBR2) Register Mask */ + + +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) ( /W 32) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP_Pos _U_(9) /**< (PWM_CMUPD3) Channel Polarity Update Position */ +#define PWM_CMUPD3_CPOLUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Update Mask */ +#define PWM_CMUPD3_CPOLUP(value) (PWM_CMUPD3_CPOLUP_Msk & ((value) << PWM_CMUPD3_CPOLUP_Pos)) +#define PWM_CMUPD3_CPOLINVUP_Pos _U_(13) /**< (PWM_CMUPD3) Channel Polarity Inversion Update Position */ +#define PWM_CMUPD3_CPOLINVUP_Msk (_U_(0x1) << PWM_CMUPD3_CPOLINVUP_Pos) /**< (PWM_CMUPD3) Channel Polarity Inversion Update Mask */ +#define PWM_CMUPD3_CPOLINVUP(value) (PWM_CMUPD3_CPOLINVUP_Msk & ((value) << PWM_CMUPD3_CPOLINVUP_Pos)) +#define PWM_CMUPD3_Msk _U_(0x00002200) /**< (PWM_CMUPD3) Register Mask */ + + +/** \brief PWM register offsets definitions */ +#define PWM_CMR_REG_OFST (0x00) /**< (PWM_CMR) PWM Channel Mode Register Offset */ +#define PWM_CDTY_REG_OFST (0x04) /**< (PWM_CDTY) PWM Channel Duty Cycle Register Offset */ +#define PWM_CDTYUPD_REG_OFST (0x08) /**< (PWM_CDTYUPD) PWM Channel Duty Cycle Update Register Offset */ +#define PWM_CPRD_REG_OFST (0x0C) /**< (PWM_CPRD) PWM Channel Period Register Offset */ +#define PWM_CPRDUPD_REG_OFST (0x10) /**< (PWM_CPRDUPD) PWM Channel Period Update Register Offset */ +#define PWM_CCNT_REG_OFST (0x14) /**< (PWM_CCNT) PWM Channel Counter Register Offset */ +#define PWM_DT_REG_OFST (0x18) /**< (PWM_DT) PWM Channel Dead Time Register Offset */ +#define PWM_DTUPD_REG_OFST (0x1C) /**< (PWM_DTUPD) PWM Channel Dead Time Update Register Offset */ +#define PWM_CMPV_REG_OFST (0x00) /**< (PWM_CMPV) PWM Comparison 0 Value Register Offset */ +#define PWM_CMPVUPD_REG_OFST (0x04) /**< (PWM_CMPVUPD) PWM Comparison 0 Value Update Register Offset */ +#define PWM_CMPM_REG_OFST (0x08) /**< (PWM_CMPM) PWM Comparison 0 Mode Register Offset */ +#define PWM_CMPMUPD_REG_OFST (0x0C) /**< (PWM_CMPMUPD) PWM Comparison 0 Mode Update Register Offset */ +#define PWM_CLK_REG_OFST (0x00) /**< (PWM_CLK) PWM Clock Register Offset */ +#define PWM_ENA_REG_OFST (0x04) /**< (PWM_ENA) PWM Enable Register Offset */ +#define PWM_DIS_REG_OFST (0x08) /**< (PWM_DIS) PWM Disable Register Offset */ +#define PWM_SR_REG_OFST (0x0C) /**< (PWM_SR) PWM Status Register Offset */ +#define PWM_IER1_REG_OFST (0x10) /**< (PWM_IER1) PWM Interrupt Enable Register 1 Offset */ +#define PWM_IDR1_REG_OFST (0x14) /**< (PWM_IDR1) PWM Interrupt Disable Register 1 Offset */ +#define PWM_IMR1_REG_OFST (0x18) /**< (PWM_IMR1) PWM Interrupt Mask Register 1 Offset */ +#define PWM_ISR1_REG_OFST (0x1C) /**< (PWM_ISR1) PWM Interrupt Status Register 1 Offset */ +#define PWM_SCM_REG_OFST (0x20) /**< (PWM_SCM) PWM Sync Channels Mode Register Offset */ +#define PWM_DMAR_REG_OFST (0x24) /**< (PWM_DMAR) PWM DMA Register Offset */ +#define PWM_SCUC_REG_OFST (0x28) /**< (PWM_SCUC) PWM Sync Channels Update Control Register Offset */ +#define PWM_SCUP_REG_OFST (0x2C) /**< (PWM_SCUP) PWM Sync Channels Update Period Register Offset */ +#define PWM_SCUPUPD_REG_OFST (0x30) /**< (PWM_SCUPUPD) PWM Sync Channels Update Period Update Register Offset */ +#define PWM_IER2_REG_OFST (0x34) /**< (PWM_IER2) PWM Interrupt Enable Register 2 Offset */ +#define PWM_IDR2_REG_OFST (0x38) /**< (PWM_IDR2) PWM Interrupt Disable Register 2 Offset */ +#define PWM_IMR2_REG_OFST (0x3C) /**< (PWM_IMR2) PWM Interrupt Mask Register 2 Offset */ +#define PWM_ISR2_REG_OFST (0x40) /**< (PWM_ISR2) PWM Interrupt Status Register 2 Offset */ +#define PWM_OOV_REG_OFST (0x44) /**< (PWM_OOV) PWM Output Override Value Register Offset */ +#define PWM_OS_REG_OFST (0x48) /**< (PWM_OS) PWM Output Selection Register Offset */ +#define PWM_OSS_REG_OFST (0x4C) /**< (PWM_OSS) PWM Output Selection Set Register Offset */ +#define PWM_OSC_REG_OFST (0x50) /**< (PWM_OSC) PWM Output Selection Clear Register Offset */ +#define PWM_OSSUPD_REG_OFST (0x54) /**< (PWM_OSSUPD) PWM Output Selection Set Update Register Offset */ +#define PWM_OSCUPD_REG_OFST (0x58) /**< (PWM_OSCUPD) PWM Output Selection Clear Update Register Offset */ +#define PWM_FMR_REG_OFST (0x5C) /**< (PWM_FMR) PWM Fault Mode Register Offset */ +#define PWM_FSR_REG_OFST (0x60) /**< (PWM_FSR) PWM Fault Status Register Offset */ +#define PWM_FCR_REG_OFST (0x64) /**< (PWM_FCR) PWM Fault Clear Register Offset */ +#define PWM_FPV1_REG_OFST (0x68) /**< (PWM_FPV1) PWM Fault Protection Value Register 1 Offset */ +#define PWM_FPE_REG_OFST (0x6C) /**< (PWM_FPE) PWM Fault Protection Enable Register Offset */ +#define PWM_ELMR_REG_OFST (0x7C) /**< (PWM_ELMR) PWM Event Line 0 Mode Register 0 Offset */ +#define PWM_SSPR_REG_OFST (0xA0) /**< (PWM_SSPR) PWM Spread Spectrum Register Offset */ +#define PWM_SSPUP_REG_OFST (0xA4) /**< (PWM_SSPUP) PWM Spread Spectrum Update Register Offset */ +#define PWM_SMMR_REG_OFST (0xB0) /**< (PWM_SMMR) PWM Stepper Motor Mode Register Offset */ +#define PWM_FPV2_REG_OFST (0xC0) /**< (PWM_FPV2) PWM Fault Protection Value 2 Register Offset */ +#define PWM_WPCR_REG_OFST (0xE4) /**< (PWM_WPCR) PWM Write Protection Control Register Offset */ +#define PWM_WPSR_REG_OFST (0xE8) /**< (PWM_WPSR) PWM Write Protection Status Register Offset */ +#define PWM_CMUPD0_REG_OFST (0x400) /**< (PWM_CMUPD0) PWM Channel Mode Update Register (ch_num = 0) Offset */ +#define PWM_CMUPD1_REG_OFST (0x420) /**< (PWM_CMUPD1) PWM Channel Mode Update Register (ch_num = 1) Offset */ +#define PWM_ETRG1_REG_OFST (0x42C) /**< (PWM_ETRG1) PWM External Trigger Register (trg_num = 1) Offset */ +#define PWM_LEBR1_REG_OFST (0x430) /**< (PWM_LEBR1) PWM Leading-Edge Blanking Register (trg_num = 1) Offset */ +#define PWM_CMUPD2_REG_OFST (0x440) /**< (PWM_CMUPD2) PWM Channel Mode Update Register (ch_num = 2) Offset */ +#define PWM_ETRG2_REG_OFST (0x44C) /**< (PWM_ETRG2) PWM External Trigger Register (trg_num = 2) Offset */ +#define PWM_LEBR2_REG_OFST (0x450) /**< (PWM_LEBR2) PWM Leading-Edge Blanking Register (trg_num = 2) Offset */ +#define PWM_CMUPD3_REG_OFST (0x460) /**< (PWM_CMUPD3) PWM Channel Mode Update Register (ch_num = 3) Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PWM_CH_NUM register API structure */ +typedef struct +{ + __IO uint32_t PWM_CMR; /**< Offset: 0x00 (R/W 32) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< Offset: 0x04 (R/W 32) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< Offset: 0x08 ( /W 32) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< Offset: 0x0C (R/W 32) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< Offset: 0x10 ( /W 32) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< Offset: 0x14 (R/ 32) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< Offset: 0x18 (R/W 32) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< Offset: 0x1C ( /W 32) PWM Channel Dead Time Update Register */ +} pwm_ch_num_registers_t; + +/** \brief PWM_CMP register API structure */ +typedef struct +{ + __IO uint32_t PWM_CMPV; /**< Offset: 0x00 (R/W 32) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< Offset: 0x04 ( /W 32) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< Offset: 0x08 (R/W 32) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< Offset: 0x0C ( /W 32) PWM Comparison 0 Mode Update Register */ +} pwm_cmp_registers_t; + +#define PWM_CMP_NUMBER _U_(8) + +#define PWM_CH_NUM_NUMBER _U_(4) + +/** \brief PWM register API structure */ +typedef struct +{ + __IO uint32_t PWM_CLK; /**< Offset: 0x00 (R/W 32) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< Offset: 0x04 ( /W 32) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< Offset: 0x08 ( /W 32) PWM Disable Register */ + __I uint32_t PWM_SR; /**< Offset: 0x0C (R/ 32) PWM Status Register */ + __O uint32_t PWM_IER1; /**< Offset: 0x10 ( /W 32) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< Offset: 0x14 ( /W 32) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< Offset: 0x18 (R/ 32) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< Offset: 0x1C (R/ 32) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< Offset: 0x20 (R/W 32) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< Offset: 0x24 ( /W 32) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< Offset: 0x28 (R/W 32) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< Offset: 0x2C (R/W 32) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< Offset: 0x30 ( /W 32) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< Offset: 0x34 ( /W 32) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< Offset: 0x38 ( /W 32) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< Offset: 0x3C (R/ 32) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< Offset: 0x40 (R/ 32) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< Offset: 0x44 (R/W 32) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< Offset: 0x48 (R/W 32) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< Offset: 0x4C ( /W 32) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< Offset: 0x50 ( /W 32) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< Offset: 0x54 ( /W 32) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< Offset: 0x58 ( /W 32) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< Offset: 0x5C (R/W 32) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< Offset: 0x60 (R/ 32) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< Offset: 0x64 ( /W 32) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< Offset: 0x68 (R/W 32) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< Offset: 0x6C (R/W 32) PWM Fault Protection Enable Register */ + __I uint8_t Reserved1[0x0C]; + __IO uint32_t PWM_ELMR[2]; /**< Offset: 0x7C (R/W 32) PWM Event Line 0 Mode Register 0 */ + __I uint8_t Reserved2[0x1C]; + __IO uint32_t PWM_SSPR; /**< Offset: 0xA0 (R/W 32) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< Offset: 0xA4 ( /W 32) PWM Spread Spectrum Update Register */ + __I uint8_t Reserved3[0x08]; + __IO uint32_t PWM_SMMR; /**< Offset: 0xB0 (R/W 32) PWM Stepper Motor Mode Register */ + __I uint8_t Reserved4[0x0C]; + __IO uint32_t PWM_FPV2; /**< Offset: 0xC0 (R/W 32) PWM Fault Protection Value 2 Register */ + __I uint8_t Reserved5[0x20]; + __O uint32_t PWM_WPCR; /**< Offset: 0xE4 ( /W 32) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< Offset: 0xE8 (R/ 32) PWM Write Protection Status Register */ + __I uint8_t Reserved6[0x44]; + pwm_cmp_registers_t PWM_CMP[PWM_CMP_NUMBER]; /**< Offset: 0x130 PWM Comparison 0 Value Register */ + __I uint8_t Reserved7[0x50]; + pwm_ch_num_registers_t PWM_CH_NUM[PWM_CH_NUM_NUMBER]; /**< Offset: 0x200 PWM Channel Mode Register */ + __I uint8_t Reserved8[0x180]; + __O uint32_t PWM_CMUPD0; /**< Offset: 0x400 ( /W 32) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint8_t Reserved9[0x1C]; + __O uint32_t PWM_CMUPD1; /**< Offset: 0x420 ( /W 32) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint8_t Reserved10[0x08]; + __IO uint32_t PWM_ETRG1; /**< Offset: 0x42C (R/W 32) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< Offset: 0x430 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint8_t Reserved11[0x0C]; + __O uint32_t PWM_CMUPD2; /**< Offset: 0x440 ( /W 32) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint8_t Reserved12[0x08]; + __IO uint32_t PWM_ETRG2; /**< Offset: 0x44C (R/W 32) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< Offset: 0x450 (R/W 32) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint8_t Reserved13[0x0C]; + __O uint32_t PWM_CMUPD3; /**< Offset: 0x460 ( /W 32) PWM Channel Mode Update Register (ch_num = 3) */ +} pwm_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_PWM_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/qspi.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/qspi.h new file mode 100644 index 00000000..98d56b4c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/qspi.h @@ -0,0 +1,404 @@ +/** + * \brief Component description for QSPI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_QSPI_COMPONENT_H_ +#define _SAME70_QSPI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR QSPI */ +/* ************************************************************************** */ + +/* -------- QSPI_CR : (QSPI Offset: 0x00) ( /W 32) Control Register -------- */ +#define QSPI_CR_QSPIEN_Pos _U_(0) /**< (QSPI_CR) QSPI Enable Position */ +#define QSPI_CR_QSPIEN_Msk (_U_(0x1) << QSPI_CR_QSPIEN_Pos) /**< (QSPI_CR) QSPI Enable Mask */ +#define QSPI_CR_QSPIEN(value) (QSPI_CR_QSPIEN_Msk & ((value) << QSPI_CR_QSPIEN_Pos)) +#define QSPI_CR_QSPIDIS_Pos _U_(1) /**< (QSPI_CR) QSPI Disable Position */ +#define QSPI_CR_QSPIDIS_Msk (_U_(0x1) << QSPI_CR_QSPIDIS_Pos) /**< (QSPI_CR) QSPI Disable Mask */ +#define QSPI_CR_QSPIDIS(value) (QSPI_CR_QSPIDIS_Msk & ((value) << QSPI_CR_QSPIDIS_Pos)) +#define QSPI_CR_SWRST_Pos _U_(7) /**< (QSPI_CR) QSPI Software Reset Position */ +#define QSPI_CR_SWRST_Msk (_U_(0x1) << QSPI_CR_SWRST_Pos) /**< (QSPI_CR) QSPI Software Reset Mask */ +#define QSPI_CR_SWRST(value) (QSPI_CR_SWRST_Msk & ((value) << QSPI_CR_SWRST_Pos)) +#define QSPI_CR_LASTXFER_Pos _U_(24) /**< (QSPI_CR) Last Transfer Position */ +#define QSPI_CR_LASTXFER_Msk (_U_(0x1) << QSPI_CR_LASTXFER_Pos) /**< (QSPI_CR) Last Transfer Mask */ +#define QSPI_CR_LASTXFER(value) (QSPI_CR_LASTXFER_Msk & ((value) << QSPI_CR_LASTXFER_Pos)) +#define QSPI_CR_Msk _U_(0x01000083) /**< (QSPI_CR) Register Mask */ + + +/* -------- QSPI_MR : (QSPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define QSPI_MR_SMM_Pos _U_(0) /**< (QSPI_MR) Serial Memory Mode Position */ +#define QSPI_MR_SMM_Msk (_U_(0x1) << QSPI_MR_SMM_Pos) /**< (QSPI_MR) Serial Memory Mode Mask */ +#define QSPI_MR_SMM(value) (QSPI_MR_SMM_Msk & ((value) << QSPI_MR_SMM_Pos)) +#define QSPI_MR_SMM_SPI_Val _U_(0x0) /**< (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY_Val _U_(0x1) /**< (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_SMM_SPI (QSPI_MR_SMM_SPI_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in SPI mode. Position */ +#define QSPI_MR_SMM_MEMORY (QSPI_MR_SMM_MEMORY_Val << QSPI_MR_SMM_Pos) /**< (QSPI_MR) The QSPI is in Serial Memory mode. Position */ +#define QSPI_MR_LLB_Pos _U_(1) /**< (QSPI_MR) Local Loopback Enable Position */ +#define QSPI_MR_LLB_Msk (_U_(0x1) << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local Loopback Enable Mask */ +#define QSPI_MR_LLB(value) (QSPI_MR_LLB_Msk & ((value) << QSPI_MR_LLB_Pos)) +#define QSPI_MR_LLB_DISABLED_Val _U_(0x0) /**< (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED_Val _U_(0x1) /**< (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_LLB_DISABLED (QSPI_MR_LLB_DISABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path disabled. Position */ +#define QSPI_MR_LLB_ENABLED (QSPI_MR_LLB_ENABLED_Val << QSPI_MR_LLB_Pos) /**< (QSPI_MR) Local loopback path enabled. Position */ +#define QSPI_MR_WDRBT_Pos _U_(2) /**< (QSPI_MR) Wait Data Read Before Transfer Position */ +#define QSPI_MR_WDRBT_Msk (_U_(0x1) << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) Wait Data Read Before Transfer Mask */ +#define QSPI_MR_WDRBT(value) (QSPI_MR_WDRBT_Msk & ((value) << QSPI_MR_WDRBT_Pos)) +#define QSPI_MR_WDRBT_DISABLED_Val _U_(0x0) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED_Val _U_(0x1) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_WDRBT_DISABLED (QSPI_MR_WDRBT_DISABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. Position */ +#define QSPI_MR_WDRBT_ENABLED (QSPI_MR_WDRBT_ENABLED_Val << QSPI_MR_WDRBT_Pos) /**< (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. Position */ +#define QSPI_MR_CSMODE_Pos _U_(4) /**< (QSPI_MR) Chip Select Mode Position */ +#define QSPI_MR_CSMODE_Msk (_U_(0x3) << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) Chip Select Mode Mask */ +#define QSPI_MR_CSMODE(value) (QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)) +#define QSPI_MR_CSMODE_NOT_RELOADED_Val _U_(0x0) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_CSMODE_NOT_RELOADED (QSPI_MR_CSMODE_NOT_RELOADED_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. Position */ +#define QSPI_MR_CSMODE_LASTXFER (QSPI_MR_CSMODE_LASTXFER_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. Position */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (QSPI_MR_CSMODE_SYSTEMATICALLY_Val << QSPI_MR_CSMODE_Pos) /**< (QSPI_MR) The chip select is deasserted systematically after each transfer. Position */ +#define QSPI_MR_NBBITS_Pos _U_(8) /**< (QSPI_MR) Number Of Bits Per Transfer Position */ +#define QSPI_MR_NBBITS_Msk (_U_(0xF) << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) Number Of Bits Per Transfer Mask */ +#define QSPI_MR_NBBITS(value) (QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)) +#define QSPI_MR_NBBITS_8_BIT_Val _U_(0x0) /**< (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT_Val _U_(0x8) /**< (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_NBBITS_8_BIT (QSPI_MR_NBBITS_8_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 8 bits for transfer Position */ +#define QSPI_MR_NBBITS_16_BIT (QSPI_MR_NBBITS_16_BIT_Val << QSPI_MR_NBBITS_Pos) /**< (QSPI_MR) 16 bits for transfer Position */ +#define QSPI_MR_DLYBCT_Pos _U_(16) /**< (QSPI_MR) Delay Between Consecutive Transfers Position */ +#define QSPI_MR_DLYBCT_Msk (_U_(0xFF) << QSPI_MR_DLYBCT_Pos) /**< (QSPI_MR) Delay Between Consecutive Transfers Mask */ +#define QSPI_MR_DLYBCT(value) (QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)) +#define QSPI_MR_DLYCS_Pos _U_(24) /**< (QSPI_MR) Minimum Inactive QCS Delay Position */ +#define QSPI_MR_DLYCS_Msk (_U_(0xFF) << QSPI_MR_DLYCS_Pos) /**< (QSPI_MR) Minimum Inactive QCS Delay Mask */ +#define QSPI_MR_DLYCS(value) (QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)) +#define QSPI_MR_Msk _U_(0xFFFF0F37) /**< (QSPI_MR) Register Mask */ + + +/* -------- QSPI_RDR : (QSPI Offset: 0x08) ( R/ 32) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos _U_(0) /**< (QSPI_RDR) Receive Data Position */ +#define QSPI_RDR_RD_Msk (_U_(0xFFFF) << QSPI_RDR_RD_Pos) /**< (QSPI_RDR) Receive Data Mask */ +#define QSPI_RDR_RD(value) (QSPI_RDR_RD_Msk & ((value) << QSPI_RDR_RD_Pos)) +#define QSPI_RDR_Msk _U_(0x0000FFFF) /**< (QSPI_RDR) Register Mask */ + + +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) ( /W 32) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos _U_(0) /**< (QSPI_TDR) Transmit Data Position */ +#define QSPI_TDR_TD_Msk (_U_(0xFFFF) << QSPI_TDR_TD_Pos) /**< (QSPI_TDR) Transmit Data Mask */ +#define QSPI_TDR_TD(value) (QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)) +#define QSPI_TDR_Msk _U_(0x0000FFFF) /**< (QSPI_TDR) Register Mask */ + + +/* -------- QSPI_SR : (QSPI Offset: 0x10) ( R/ 32) Status Register -------- */ +#define QSPI_SR_RDRF_Pos _U_(0) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define QSPI_SR_RDRF_Msk (_U_(0x1) << QSPI_SR_RDRF_Pos) /**< (QSPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define QSPI_SR_RDRF(value) (QSPI_SR_RDRF_Msk & ((value) << QSPI_SR_RDRF_Pos)) +#define QSPI_SR_TDRE_Pos _U_(1) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TDRE_Msk (_U_(0x1) << QSPI_SR_TDRE_Pos) /**< (QSPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TDRE(value) (QSPI_SR_TDRE_Msk & ((value) << QSPI_SR_TDRE_Pos)) +#define QSPI_SR_TXEMPTY_Pos _U_(2) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define QSPI_SR_TXEMPTY_Msk (_U_(0x1) << QSPI_SR_TXEMPTY_Pos) /**< (QSPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define QSPI_SR_TXEMPTY(value) (QSPI_SR_TXEMPTY_Msk & ((value) << QSPI_SR_TXEMPTY_Pos)) +#define QSPI_SR_OVRES_Pos _U_(3) /**< (QSPI_SR) Overrun Error Status (cleared on read) Position */ +#define QSPI_SR_OVRES_Msk (_U_(0x1) << QSPI_SR_OVRES_Pos) /**< (QSPI_SR) Overrun Error Status (cleared on read) Mask */ +#define QSPI_SR_OVRES(value) (QSPI_SR_OVRES_Msk & ((value) << QSPI_SR_OVRES_Pos)) +#define QSPI_SR_CSR_Pos _U_(8) /**< (QSPI_SR) Chip Select Rise (cleared on read) Position */ +#define QSPI_SR_CSR_Msk (_U_(0x1) << QSPI_SR_CSR_Pos) /**< (QSPI_SR) Chip Select Rise (cleared on read) Mask */ +#define QSPI_SR_CSR(value) (QSPI_SR_CSR_Msk & ((value) << QSPI_SR_CSR_Pos)) +#define QSPI_SR_CSS_Pos _U_(9) /**< (QSPI_SR) Chip Select Status Position */ +#define QSPI_SR_CSS_Msk (_U_(0x1) << QSPI_SR_CSS_Pos) /**< (QSPI_SR) Chip Select Status Mask */ +#define QSPI_SR_CSS(value) (QSPI_SR_CSS_Msk & ((value) << QSPI_SR_CSS_Pos)) +#define QSPI_SR_INSTRE_Pos _U_(10) /**< (QSPI_SR) Instruction End Status (cleared on read) Position */ +#define QSPI_SR_INSTRE_Msk (_U_(0x1) << QSPI_SR_INSTRE_Pos) /**< (QSPI_SR) Instruction End Status (cleared on read) Mask */ +#define QSPI_SR_INSTRE(value) (QSPI_SR_INSTRE_Msk & ((value) << QSPI_SR_INSTRE_Pos)) +#define QSPI_SR_QSPIENS_Pos _U_(24) /**< (QSPI_SR) QSPI Enable Status Position */ +#define QSPI_SR_QSPIENS_Msk (_U_(0x1) << QSPI_SR_QSPIENS_Pos) /**< (QSPI_SR) QSPI Enable Status Mask */ +#define QSPI_SR_QSPIENS(value) (QSPI_SR_QSPIENS_Msk & ((value) << QSPI_SR_QSPIENS_Pos)) +#define QSPI_SR_Msk _U_(0x0100070F) /**< (QSPI_SR) Register Mask */ + + +/* -------- QSPI_IER : (QSPI Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF_Pos _U_(0) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define QSPI_IER_RDRF_Msk (_U_(0x1) << QSPI_IER_RDRF_Pos) /**< (QSPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define QSPI_IER_RDRF(value) (QSPI_IER_RDRF_Msk & ((value) << QSPI_IER_RDRF_Pos)) +#define QSPI_IER_TDRE_Pos _U_(1) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Position */ +#define QSPI_IER_TDRE_Msk (_U_(0x1) << QSPI_IER_TDRE_Pos) /**< (QSPI_IER) Transmit Data Register Empty Interrupt Enable Mask */ +#define QSPI_IER_TDRE(value) (QSPI_IER_TDRE_Msk & ((value) << QSPI_IER_TDRE_Pos)) +#define QSPI_IER_TXEMPTY_Pos _U_(2) /**< (QSPI_IER) Transmission Registers Empty Enable Position */ +#define QSPI_IER_TXEMPTY_Msk (_U_(0x1) << QSPI_IER_TXEMPTY_Pos) /**< (QSPI_IER) Transmission Registers Empty Enable Mask */ +#define QSPI_IER_TXEMPTY(value) (QSPI_IER_TXEMPTY_Msk & ((value) << QSPI_IER_TXEMPTY_Pos)) +#define QSPI_IER_OVRES_Pos _U_(3) /**< (QSPI_IER) Overrun Error Interrupt Enable Position */ +#define QSPI_IER_OVRES_Msk (_U_(0x1) << QSPI_IER_OVRES_Pos) /**< (QSPI_IER) Overrun Error Interrupt Enable Mask */ +#define QSPI_IER_OVRES(value) (QSPI_IER_OVRES_Msk & ((value) << QSPI_IER_OVRES_Pos)) +#define QSPI_IER_CSR_Pos _U_(8) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Position */ +#define QSPI_IER_CSR_Msk (_U_(0x1) << QSPI_IER_CSR_Pos) /**< (QSPI_IER) Chip Select Rise Interrupt Enable Mask */ +#define QSPI_IER_CSR(value) (QSPI_IER_CSR_Msk & ((value) << QSPI_IER_CSR_Pos)) +#define QSPI_IER_CSS_Pos _U_(9) /**< (QSPI_IER) Chip Select Status Interrupt Enable Position */ +#define QSPI_IER_CSS_Msk (_U_(0x1) << QSPI_IER_CSS_Pos) /**< (QSPI_IER) Chip Select Status Interrupt Enable Mask */ +#define QSPI_IER_CSS(value) (QSPI_IER_CSS_Msk & ((value) << QSPI_IER_CSS_Pos)) +#define QSPI_IER_INSTRE_Pos _U_(10) /**< (QSPI_IER) Instruction End Interrupt Enable Position */ +#define QSPI_IER_INSTRE_Msk (_U_(0x1) << QSPI_IER_INSTRE_Pos) /**< (QSPI_IER) Instruction End Interrupt Enable Mask */ +#define QSPI_IER_INSTRE(value) (QSPI_IER_INSTRE_Msk & ((value) << QSPI_IER_INSTRE_Pos)) +#define QSPI_IER_Msk _U_(0x0000070F) /**< (QSPI_IER) Register Mask */ + + +/* -------- QSPI_IDR : (QSPI Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF_Pos _U_(0) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define QSPI_IDR_RDRF_Msk (_U_(0x1) << QSPI_IDR_RDRF_Pos) /**< (QSPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define QSPI_IDR_RDRF(value) (QSPI_IDR_RDRF_Msk & ((value) << QSPI_IDR_RDRF_Pos)) +#define QSPI_IDR_TDRE_Pos _U_(1) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Position */ +#define QSPI_IDR_TDRE_Msk (_U_(0x1) << QSPI_IDR_TDRE_Pos) /**< (QSPI_IDR) Transmit Data Register Empty Interrupt Disable Mask */ +#define QSPI_IDR_TDRE(value) (QSPI_IDR_TDRE_Msk & ((value) << QSPI_IDR_TDRE_Pos)) +#define QSPI_IDR_TXEMPTY_Pos _U_(2) /**< (QSPI_IDR) Transmission Registers Empty Disable Position */ +#define QSPI_IDR_TXEMPTY_Msk (_U_(0x1) << QSPI_IDR_TXEMPTY_Pos) /**< (QSPI_IDR) Transmission Registers Empty Disable Mask */ +#define QSPI_IDR_TXEMPTY(value) (QSPI_IDR_TXEMPTY_Msk & ((value) << QSPI_IDR_TXEMPTY_Pos)) +#define QSPI_IDR_OVRES_Pos _U_(3) /**< (QSPI_IDR) Overrun Error Interrupt Disable Position */ +#define QSPI_IDR_OVRES_Msk (_U_(0x1) << QSPI_IDR_OVRES_Pos) /**< (QSPI_IDR) Overrun Error Interrupt Disable Mask */ +#define QSPI_IDR_OVRES(value) (QSPI_IDR_OVRES_Msk & ((value) << QSPI_IDR_OVRES_Pos)) +#define QSPI_IDR_CSR_Pos _U_(8) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Position */ +#define QSPI_IDR_CSR_Msk (_U_(0x1) << QSPI_IDR_CSR_Pos) /**< (QSPI_IDR) Chip Select Rise Interrupt Disable Mask */ +#define QSPI_IDR_CSR(value) (QSPI_IDR_CSR_Msk & ((value) << QSPI_IDR_CSR_Pos)) +#define QSPI_IDR_CSS_Pos _U_(9) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Position */ +#define QSPI_IDR_CSS_Msk (_U_(0x1) << QSPI_IDR_CSS_Pos) /**< (QSPI_IDR) Chip Select Status Interrupt Disable Mask */ +#define QSPI_IDR_CSS(value) (QSPI_IDR_CSS_Msk & ((value) << QSPI_IDR_CSS_Pos)) +#define QSPI_IDR_INSTRE_Pos _U_(10) /**< (QSPI_IDR) Instruction End Interrupt Disable Position */ +#define QSPI_IDR_INSTRE_Msk (_U_(0x1) << QSPI_IDR_INSTRE_Pos) /**< (QSPI_IDR) Instruction End Interrupt Disable Mask */ +#define QSPI_IDR_INSTRE(value) (QSPI_IDR_INSTRE_Msk & ((value) << QSPI_IDR_INSTRE_Pos)) +#define QSPI_IDR_Msk _U_(0x0000070F) /**< (QSPI_IDR) Register Mask */ + + +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) ( R/ 32) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF_Pos _U_(0) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define QSPI_IMR_RDRF_Msk (_U_(0x1) << QSPI_IMR_RDRF_Pos) /**< (QSPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define QSPI_IMR_RDRF(value) (QSPI_IMR_RDRF_Msk & ((value) << QSPI_IMR_RDRF_Pos)) +#define QSPI_IMR_TDRE_Pos _U_(1) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Position */ +#define QSPI_IMR_TDRE_Msk (_U_(0x1) << QSPI_IMR_TDRE_Pos) /**< (QSPI_IMR) Transmit Data Register Empty Interrupt Mask Mask */ +#define QSPI_IMR_TDRE(value) (QSPI_IMR_TDRE_Msk & ((value) << QSPI_IMR_TDRE_Pos)) +#define QSPI_IMR_TXEMPTY_Pos _U_(2) /**< (QSPI_IMR) Transmission Registers Empty Mask Position */ +#define QSPI_IMR_TXEMPTY_Msk (_U_(0x1) << QSPI_IMR_TXEMPTY_Pos) /**< (QSPI_IMR) Transmission Registers Empty Mask Mask */ +#define QSPI_IMR_TXEMPTY(value) (QSPI_IMR_TXEMPTY_Msk & ((value) << QSPI_IMR_TXEMPTY_Pos)) +#define QSPI_IMR_OVRES_Pos _U_(3) /**< (QSPI_IMR) Overrun Error Interrupt Mask Position */ +#define QSPI_IMR_OVRES_Msk (_U_(0x1) << QSPI_IMR_OVRES_Pos) /**< (QSPI_IMR) Overrun Error Interrupt Mask Mask */ +#define QSPI_IMR_OVRES(value) (QSPI_IMR_OVRES_Msk & ((value) << QSPI_IMR_OVRES_Pos)) +#define QSPI_IMR_CSR_Pos _U_(8) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Position */ +#define QSPI_IMR_CSR_Msk (_U_(0x1) << QSPI_IMR_CSR_Pos) /**< (QSPI_IMR) Chip Select Rise Interrupt Mask Mask */ +#define QSPI_IMR_CSR(value) (QSPI_IMR_CSR_Msk & ((value) << QSPI_IMR_CSR_Pos)) +#define QSPI_IMR_CSS_Pos _U_(9) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Position */ +#define QSPI_IMR_CSS_Msk (_U_(0x1) << QSPI_IMR_CSS_Pos) /**< (QSPI_IMR) Chip Select Status Interrupt Mask Mask */ +#define QSPI_IMR_CSS(value) (QSPI_IMR_CSS_Msk & ((value) << QSPI_IMR_CSS_Pos)) +#define QSPI_IMR_INSTRE_Pos _U_(10) /**< (QSPI_IMR) Instruction End Interrupt Mask Position */ +#define QSPI_IMR_INSTRE_Msk (_U_(0x1) << QSPI_IMR_INSTRE_Pos) /**< (QSPI_IMR) Instruction End Interrupt Mask Mask */ +#define QSPI_IMR_INSTRE(value) (QSPI_IMR_INSTRE_Msk & ((value) << QSPI_IMR_INSTRE_Pos)) +#define QSPI_IMR_Msk _U_(0x0000070F) /**< (QSPI_IMR) Register Mask */ + + +/* -------- QSPI_SCR : (QSPI Offset: 0x20) (R/W 32) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL_Pos _U_(0) /**< (QSPI_SCR) Clock Polarity Position */ +#define QSPI_SCR_CPOL_Msk (_U_(0x1) << QSPI_SCR_CPOL_Pos) /**< (QSPI_SCR) Clock Polarity Mask */ +#define QSPI_SCR_CPOL(value) (QSPI_SCR_CPOL_Msk & ((value) << QSPI_SCR_CPOL_Pos)) +#define QSPI_SCR_CPHA_Pos _U_(1) /**< (QSPI_SCR) Clock Phase Position */ +#define QSPI_SCR_CPHA_Msk (_U_(0x1) << QSPI_SCR_CPHA_Pos) /**< (QSPI_SCR) Clock Phase Mask */ +#define QSPI_SCR_CPHA(value) (QSPI_SCR_CPHA_Msk & ((value) << QSPI_SCR_CPHA_Pos)) +#define QSPI_SCR_SCBR_Pos _U_(8) /**< (QSPI_SCR) Serial Clock Baud Rate Position */ +#define QSPI_SCR_SCBR_Msk (_U_(0xFF) << QSPI_SCR_SCBR_Pos) /**< (QSPI_SCR) Serial Clock Baud Rate Mask */ +#define QSPI_SCR_SCBR(value) (QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)) +#define QSPI_SCR_DLYBS_Pos _U_(16) /**< (QSPI_SCR) Delay Before QSCK Position */ +#define QSPI_SCR_DLYBS_Msk (_U_(0xFF) << QSPI_SCR_DLYBS_Pos) /**< (QSPI_SCR) Delay Before QSCK Mask */ +#define QSPI_SCR_DLYBS(value) (QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)) +#define QSPI_SCR_Msk _U_(0x00FFFF03) /**< (QSPI_SCR) Register Mask */ + + +/* -------- QSPI_IAR : (QSPI Offset: 0x30) (R/W 32) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos _U_(0) /**< (QSPI_IAR) Address Position */ +#define QSPI_IAR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_IAR_ADDR_Pos) /**< (QSPI_IAR) Address Mask */ +#define QSPI_IAR_ADDR(value) (QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)) +#define QSPI_IAR_Msk _U_(0xFFFFFFFF) /**< (QSPI_IAR) Register Mask */ + + +/* -------- QSPI_ICR : (QSPI Offset: 0x34) (R/W 32) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos _U_(0) /**< (QSPI_ICR) Instruction Code Position */ +#define QSPI_ICR_INST_Msk (_U_(0xFF) << QSPI_ICR_INST_Pos) /**< (QSPI_ICR) Instruction Code Mask */ +#define QSPI_ICR_INST(value) (QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)) +#define QSPI_ICR_OPT_Pos _U_(16) /**< (QSPI_ICR) Option Code Position */ +#define QSPI_ICR_OPT_Msk (_U_(0xFF) << QSPI_ICR_OPT_Pos) /**< (QSPI_ICR) Option Code Mask */ +#define QSPI_ICR_OPT(value) (QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)) +#define QSPI_ICR_Msk _U_(0x00FF00FF) /**< (QSPI_ICR) Register Mask */ + + +/* -------- QSPI_IFR : (QSPI Offset: 0x38) (R/W 32) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos _U_(0) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Position */ +#define QSPI_IFR_WIDTH_Msk (_U_(0x7) << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data Mask */ +#define QSPI_IFR_WIDTH(value) (QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (QSPI_IFR_WIDTH_SINGLE_BIT_SPI_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (QSPI_IFR_WIDTH_DUAL_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (QSPI_IFR_WIDTH_QUAD_OUTPUT_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_IO (QSPI_IFR_WIDTH_DUAL_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_IO (QSPI_IFR_WIDTH_QUAD_IO_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_WIDTH_DUAL_CMD (QSPI_IFR_WIDTH_DUAL_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */ +#define QSPI_IFR_WIDTH_QUAD_CMD (QSPI_IFR_WIDTH_QUAD_CMD_Val << QSPI_IFR_WIDTH_Pos) /**< (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */ +#define QSPI_IFR_INSTEN_Pos _U_(4) /**< (QSPI_IFR) Instruction Enable Position */ +#define QSPI_IFR_INSTEN_Msk (_U_(0x1) << QSPI_IFR_INSTEN_Pos) /**< (QSPI_IFR) Instruction Enable Mask */ +#define QSPI_IFR_INSTEN(value) (QSPI_IFR_INSTEN_Msk & ((value) << QSPI_IFR_INSTEN_Pos)) +#define QSPI_IFR_ADDREN_Pos _U_(5) /**< (QSPI_IFR) Address Enable Position */ +#define QSPI_IFR_ADDREN_Msk (_U_(0x1) << QSPI_IFR_ADDREN_Pos) /**< (QSPI_IFR) Address Enable Mask */ +#define QSPI_IFR_ADDREN(value) (QSPI_IFR_ADDREN_Msk & ((value) << QSPI_IFR_ADDREN_Pos)) +#define QSPI_IFR_OPTEN_Pos _U_(6) /**< (QSPI_IFR) Option Enable Position */ +#define QSPI_IFR_OPTEN_Msk (_U_(0x1) << QSPI_IFR_OPTEN_Pos) /**< (QSPI_IFR) Option Enable Mask */ +#define QSPI_IFR_OPTEN(value) (QSPI_IFR_OPTEN_Msk & ((value) << QSPI_IFR_OPTEN_Pos)) +#define QSPI_IFR_DATAEN_Pos _U_(7) /**< (QSPI_IFR) Data Enable Position */ +#define QSPI_IFR_DATAEN_Msk (_U_(0x1) << QSPI_IFR_DATAEN_Pos) /**< (QSPI_IFR) Data Enable Mask */ +#define QSPI_IFR_DATAEN(value) (QSPI_IFR_DATAEN_Msk & ((value) << QSPI_IFR_DATAEN_Pos)) +#define QSPI_IFR_OPTL_Pos _U_(8) /**< (QSPI_IFR) Option Code Length Position */ +#define QSPI_IFR_OPTL_Msk (_U_(0x3) << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) Option Code Length Mask */ +#define QSPI_IFR_OPTL(value) (QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)) +#define QSPI_IFR_OPTL_OPTION_1BIT_Val _U_(0x0) /**< (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT_Val _U_(0x1) /**< (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT_Val _U_(0x2) /**< (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT_Val _U_(0x3) /**< (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_OPTL_OPTION_1BIT (QSPI_IFR_OPTL_OPTION_1BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 1 bit long. Position */ +#define QSPI_IFR_OPTL_OPTION_2BIT (QSPI_IFR_OPTL_OPTION_2BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 2 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_4BIT (QSPI_IFR_OPTL_OPTION_4BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 4 bits long. Position */ +#define QSPI_IFR_OPTL_OPTION_8BIT (QSPI_IFR_OPTL_OPTION_8BIT_Val << QSPI_IFR_OPTL_Pos) /**< (QSPI_IFR) The option code is 8 bits long. Position */ +#define QSPI_IFR_ADDRL_Pos _U_(10) /**< (QSPI_IFR) Address Length Position */ +#define QSPI_IFR_ADDRL_Msk (_U_(0x1) << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) Address Length Mask */ +#define QSPI_IFR_ADDRL(value) (QSPI_IFR_ADDRL_Msk & ((value) << QSPI_IFR_ADDRL_Pos)) +#define QSPI_IFR_ADDRL_24_BIT_Val _U_(0x0) /**< (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT_Val _U_(0x1) /**< (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_ADDRL_24_BIT (QSPI_IFR_ADDRL_24_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 24 bits long. Position */ +#define QSPI_IFR_ADDRL_32_BIT (QSPI_IFR_ADDRL_32_BIT_Val << QSPI_IFR_ADDRL_Pos) /**< (QSPI_IFR) The address is 32 bits long. Position */ +#define QSPI_IFR_TFRTYP_Pos _U_(12) /**< (QSPI_IFR) Data Transfer Type Position */ +#define QSPI_IFR_TFRTYP_Msk (_U_(0x3) << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Data Transfer Type Mask */ +#define QSPI_IFR_TFRTYP(value) (QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)) +#define QSPI_IFR_TFRTYP_TRSFR_READ_Val _U_(0x0) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val _U_(0x1) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_Val _U_(0x2) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val _U_(0x3) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ (QSPI_IFR_TFRTYP_TRSFR_READ_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (QSPI_IFR_TFRTYP_TRSFR_WRITE_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. Position */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY_Val << QSPI_IFR_TFRTYP_Pos) /**< (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */ +#define QSPI_IFR_CRM_Pos _U_(14) /**< (QSPI_IFR) Continuous Read Mode Position */ +#define QSPI_IFR_CRM_Msk (_U_(0x1) << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) Continuous Read Mode Mask */ +#define QSPI_IFR_CRM(value) (QSPI_IFR_CRM_Msk & ((value) << QSPI_IFR_CRM_Pos)) +#define QSPI_IFR_CRM_DISABLED_Val _U_(0x0) /**< (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED_Val _U_(0x1) /**< (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_CRM_DISABLED (QSPI_IFR_CRM_DISABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is disabled. Position */ +#define QSPI_IFR_CRM_ENABLED (QSPI_IFR_CRM_ENABLED_Val << QSPI_IFR_CRM_Pos) /**< (QSPI_IFR) The Continuous Read mode is enabled. Position */ +#define QSPI_IFR_NBDUM_Pos _U_(16) /**< (QSPI_IFR) Number Of Dummy Cycles Position */ +#define QSPI_IFR_NBDUM_Msk (_U_(0x1F) << QSPI_IFR_NBDUM_Pos) /**< (QSPI_IFR) Number Of Dummy Cycles Mask */ +#define QSPI_IFR_NBDUM(value) (QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)) +#define QSPI_IFR_Msk _U_(0x001F77F7) /**< (QSPI_IFR) Register Mask */ + + +/* -------- QSPI_SMR : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN_Pos _U_(0) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Position */ +#define QSPI_SMR_SCREN_Msk (_U_(0x1) << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Enable Mask */ +#define QSPI_SMR_SCREN(value) (QSPI_SMR_SCREN_Msk & ((value) << QSPI_SMR_SCREN_Pos)) +#define QSPI_SMR_SCREN_DISABLED_Val _U_(0x0) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED_Val _U_(0x1) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_SCREN_DISABLED (QSPI_SMR_SCREN_DISABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is disabled. Position */ +#define QSPI_SMR_SCREN_ENABLED (QSPI_SMR_SCREN_ENABLED_Val << QSPI_SMR_SCREN_Pos) /**< (QSPI_SMR) The scrambling/unscrambling is enabled. Position */ +#define QSPI_SMR_RVDIS_Pos _U_(1) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Position */ +#define QSPI_SMR_RVDIS_Msk (_U_(0x1) << QSPI_SMR_RVDIS_Pos) /**< (QSPI_SMR) Scrambling/Unscrambling Random Value Disable Mask */ +#define QSPI_SMR_RVDIS(value) (QSPI_SMR_RVDIS_Msk & ((value) << QSPI_SMR_RVDIS_Pos)) +#define QSPI_SMR_Msk _U_(0x00000003) /**< (QSPI_SMR) Register Mask */ + + +/* -------- QSPI_SKR : (QSPI Offset: 0x44) ( /W 32) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos _U_(0) /**< (QSPI_SKR) User Scrambling Key Position */ +#define QSPI_SKR_USRK_Msk (_U_(0xFFFFFFFF) << QSPI_SKR_USRK_Pos) /**< (QSPI_SKR) User Scrambling Key Mask */ +#define QSPI_SKR_USRK(value) (QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)) +#define QSPI_SKR_Msk _U_(0xFFFFFFFF) /**< (QSPI_SKR) Register Mask */ + + +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN_Pos _U_(0) /**< (QSPI_WPMR) Write Protection Enable Position */ +#define QSPI_WPMR_WPEN_Msk (_U_(0x1) << QSPI_WPMR_WPEN_Pos) /**< (QSPI_WPMR) Write Protection Enable Mask */ +#define QSPI_WPMR_WPEN(value) (QSPI_WPMR_WPEN_Msk & ((value) << QSPI_WPMR_WPEN_Pos)) +#define QSPI_WPMR_WPKEY_Pos _U_(8) /**< (QSPI_WPMR) Write Protection Key Position */ +#define QSPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Write Protection Key Mask */ +#define QSPI_WPMR_WPKEY(value) (QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)) +#define QSPI_WPMR_WPKEY_PASSWD_Val _U_(0x515350) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define QSPI_WPMR_WPKEY_PASSWD (QSPI_WPMR_WPKEY_PASSWD_Val << QSPI_WPMR_WPKEY_Pos) /**< (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define QSPI_WPMR_Msk _U_(0xFFFFFF01) /**< (QSPI_WPMR) Register Mask */ + + +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS_Pos _U_(0) /**< (QSPI_WPSR) Write Protection Violation Status Position */ +#define QSPI_WPSR_WPVS_Msk (_U_(0x1) << QSPI_WPSR_WPVS_Pos) /**< (QSPI_WPSR) Write Protection Violation Status Mask */ +#define QSPI_WPSR_WPVS(value) (QSPI_WPSR_WPVS_Msk & ((value) << QSPI_WPSR_WPVS_Pos)) +#define QSPI_WPSR_WPVSRC_Pos _U_(8) /**< (QSPI_WPSR) Write Protection Violation Source Position */ +#define QSPI_WPSR_WPVSRC_Msk (_U_(0xFF) << QSPI_WPSR_WPVSRC_Pos) /**< (QSPI_WPSR) Write Protection Violation Source Mask */ +#define QSPI_WPSR_WPVSRC(value) (QSPI_WPSR_WPVSRC_Msk & ((value) << QSPI_WPSR_WPVSRC_Pos)) +#define QSPI_WPSR_Msk _U_(0x0000FF01) /**< (QSPI_WPSR) Register Mask */ + + +/** \brief QSPI register offsets definitions */ +#define QSPI_CR_REG_OFST (0x00) /**< (QSPI_CR) Control Register Offset */ +#define QSPI_MR_REG_OFST (0x04) /**< (QSPI_MR) Mode Register Offset */ +#define QSPI_RDR_REG_OFST (0x08) /**< (QSPI_RDR) Receive Data Register Offset */ +#define QSPI_TDR_REG_OFST (0x0C) /**< (QSPI_TDR) Transmit Data Register Offset */ +#define QSPI_SR_REG_OFST (0x10) /**< (QSPI_SR) Status Register Offset */ +#define QSPI_IER_REG_OFST (0x14) /**< (QSPI_IER) Interrupt Enable Register Offset */ +#define QSPI_IDR_REG_OFST (0x18) /**< (QSPI_IDR) Interrupt Disable Register Offset */ +#define QSPI_IMR_REG_OFST (0x1C) /**< (QSPI_IMR) Interrupt Mask Register Offset */ +#define QSPI_SCR_REG_OFST (0x20) /**< (QSPI_SCR) Serial Clock Register Offset */ +#define QSPI_IAR_REG_OFST (0x30) /**< (QSPI_IAR) Instruction Address Register Offset */ +#define QSPI_ICR_REG_OFST (0x34) /**< (QSPI_ICR) Instruction Code Register Offset */ +#define QSPI_IFR_REG_OFST (0x38) /**< (QSPI_IFR) Instruction Frame Register Offset */ +#define QSPI_SMR_REG_OFST (0x40) /**< (QSPI_SMR) Scrambling Mode Register Offset */ +#define QSPI_SKR_REG_OFST (0x44) /**< (QSPI_SKR) Scrambling Key Register Offset */ +#define QSPI_WPMR_REG_OFST (0xE4) /**< (QSPI_WPMR) Write Protection Mode Register Offset */ +#define QSPI_WPSR_REG_OFST (0xE8) /**< (QSPI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief QSPI register API structure */ +typedef struct +{ + __O uint32_t QSPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t QSPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t QSPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O uint32_t QSPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< Offset: 0x20 (R/W 32) Serial Clock Register */ + __I uint8_t Reserved1[0x0C]; + __IO uint32_t QSPI_IAR; /**< Offset: 0x30 (R/W 32) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< Offset: 0x34 (R/W 32) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< Offset: 0x38 (R/W 32) Instruction Frame Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t QSPI_SMR; /**< Offset: 0x40 (R/W 32) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< Offset: 0x44 ( /W 32) Scrambling Key Register */ + __I uint8_t Reserved3[0x9C]; + __IO uint32_t QSPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} qspi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_QSPI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/rstc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/rstc.h new file mode 100644 index 00000000..2009c587 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/rstc.h @@ -0,0 +1,106 @@ +/** + * \brief Component description for RSTC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_RSTC_COMPONENT_H_ +#define _SAME70_RSTC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RSTC */ +/* ************************************************************************** */ + +/* -------- RSTC_CR : (RSTC Offset: 0x00) ( /W 32) Control Register -------- */ +#define RSTC_CR_PROCRST_Pos _U_(0) /**< (RSTC_CR) Processor Reset Position */ +#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */ +#define RSTC_CR_PROCRST(value) (RSTC_CR_PROCRST_Msk & ((value) << RSTC_CR_PROCRST_Pos)) +#define RSTC_CR_EXTRST_Pos _U_(3) /**< (RSTC_CR) External Reset Position */ +#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */ +#define RSTC_CR_EXTRST(value) (RSTC_CR_EXTRST_Msk & ((value) << RSTC_CR_EXTRST_Pos)) +#define RSTC_CR_KEY_Pos _U_(24) /**< (RSTC_CR) System Reset Key Position */ +#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */ +#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)) +#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */ +#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */ + + +/* -------- RSTC_SR : (RSTC Offset: 0x04) ( R/ 32) Status Register -------- */ +#define RSTC_SR_URSTS_Pos _U_(0) /**< (RSTC_SR) User Reset Status Position */ +#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */ +#define RSTC_SR_URSTS(value) (RSTC_SR_URSTS_Msk & ((value) << RSTC_SR_URSTS_Pos)) +#define RSTC_SR_RSTTYP_Pos _U_(8) /**< (RSTC_SR) Reset Type Position */ +#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */ +#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos)) +#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */ +#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */ +#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */ +#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */ +#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */ +#define RSTC_SR_NRSTL_Pos _U_(16) /**< (RSTC_SR) NRST Pin Level Position */ +#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */ +#define RSTC_SR_NRSTL(value) (RSTC_SR_NRSTL_Msk & ((value) << RSTC_SR_NRSTL_Pos)) +#define RSTC_SR_SRCMP_Pos _U_(17) /**< (RSTC_SR) Software Reset Command in Progress Position */ +#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */ +#define RSTC_SR_SRCMP(value) (RSTC_SR_SRCMP_Msk & ((value) << RSTC_SR_SRCMP_Pos)) +#define RSTC_SR_Msk _U_(0x00030701) /**< (RSTC_SR) Register Mask */ + + +/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */ +#define RSTC_MR_URSTEN_Pos _U_(0) /**< (RSTC_MR) User Reset Enable Position */ +#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */ +#define RSTC_MR_URSTEN(value) (RSTC_MR_URSTEN_Msk & ((value) << RSTC_MR_URSTEN_Pos)) +#define RSTC_MR_URSTIEN_Pos _U_(4) /**< (RSTC_MR) User Reset Interrupt Enable Position */ +#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */ +#define RSTC_MR_URSTIEN(value) (RSTC_MR_URSTIEN_Msk & ((value) << RSTC_MR_URSTIEN_Pos)) +#define RSTC_MR_ERSTL_Pos _U_(8) /**< (RSTC_MR) External Reset Length Position */ +#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */ +#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)) +#define RSTC_MR_KEY_Pos _U_(24) /**< (RSTC_MR) Write Access Password Position */ +#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */ +#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)) +#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */ + + +/** \brief RSTC register offsets definitions */ +#define RSTC_CR_REG_OFST (0x00) /**< (RSTC_CR) Control Register Offset */ +#define RSTC_SR_REG_OFST (0x04) /**< (RSTC_SR) Status Register Offset */ +#define RSTC_MR_REG_OFST (0x08) /**< (RSTC_MR) Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RSTC register API structure */ +typedef struct +{ + __O uint32_t RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I uint32_t RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */ + __IO uint32_t RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */ +} rstc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RSTC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/rswdt.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/rswdt.h new file mode 100644 index 00000000..05c587dc --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/rswdt.h @@ -0,0 +1,91 @@ +/** + * \brief Component description for RSWDT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_RSWDT_COMPONENT_H_ +#define _SAME70_RSWDT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RSWDT */ +/* ************************************************************************** */ + +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) ( /W 32) Control Register -------- */ +#define RSWDT_CR_WDRSTT_Pos _U_(0) /**< (RSWDT_CR) Watchdog Restart Position */ +#define RSWDT_CR_WDRSTT_Msk (_U_(0x1) << RSWDT_CR_WDRSTT_Pos) /**< (RSWDT_CR) Watchdog Restart Mask */ +#define RSWDT_CR_WDRSTT(value) (RSWDT_CR_WDRSTT_Msk & ((value) << RSWDT_CR_WDRSTT_Pos)) +#define RSWDT_CR_KEY_Pos _U_(24) /**< (RSWDT_CR) Password Position */ +#define RSWDT_CR_KEY_Msk (_U_(0xFF) << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Password Mask */ +#define RSWDT_CR_KEY(value) (RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)) +#define RSWDT_CR_KEY_PASSWD_Val _U_(0xC4) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +#define RSWDT_CR_KEY_PASSWD (RSWDT_CR_KEY_PASSWD_Val << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define RSWDT_CR_Msk _U_(0xFF000001) /**< (RSWDT_CR) Register Mask */ + + +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos _U_(0) /**< (RSWDT_MR) Watchdog Counter Value Position */ +#define RSWDT_MR_WDV_Msk (_U_(0xFFF) << RSWDT_MR_WDV_Pos) /**< (RSWDT_MR) Watchdog Counter Value Mask */ +#define RSWDT_MR_WDV(value) (RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)) +#define RSWDT_MR_WDFIEN_Pos _U_(12) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Position */ +#define RSWDT_MR_WDFIEN_Msk (_U_(0x1) << RSWDT_MR_WDFIEN_Pos) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define RSWDT_MR_WDFIEN(value) (RSWDT_MR_WDFIEN_Msk & ((value) << RSWDT_MR_WDFIEN_Pos)) +#define RSWDT_MR_WDRSTEN_Pos _U_(13) /**< (RSWDT_MR) Watchdog Reset Enable Position */ +#define RSWDT_MR_WDRSTEN_Msk (_U_(0x1) << RSWDT_MR_WDRSTEN_Pos) /**< (RSWDT_MR) Watchdog Reset Enable Mask */ +#define RSWDT_MR_WDRSTEN(value) (RSWDT_MR_WDRSTEN_Msk & ((value) << RSWDT_MR_WDRSTEN_Pos)) +#define RSWDT_MR_WDDIS_Pos _U_(15) /**< (RSWDT_MR) Watchdog Disable Position */ +#define RSWDT_MR_WDDIS_Msk (_U_(0x1) << RSWDT_MR_WDDIS_Pos) /**< (RSWDT_MR) Watchdog Disable Mask */ +#define RSWDT_MR_WDDIS(value) (RSWDT_MR_WDDIS_Msk & ((value) << RSWDT_MR_WDDIS_Pos)) +#define RSWDT_MR_ALLONES_Pos _U_(16) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Position */ +#define RSWDT_MR_ALLONES_Msk (_U_(0xFFF) << RSWDT_MR_ALLONES_Pos) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Mask */ +#define RSWDT_MR_ALLONES(value) (RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)) +#define RSWDT_MR_WDDBGHLT_Pos _U_(28) /**< (RSWDT_MR) Watchdog Debug Halt Position */ +#define RSWDT_MR_WDDBGHLT_Msk (_U_(0x1) << RSWDT_MR_WDDBGHLT_Pos) /**< (RSWDT_MR) Watchdog Debug Halt Mask */ +#define RSWDT_MR_WDDBGHLT(value) (RSWDT_MR_WDDBGHLT_Msk & ((value) << RSWDT_MR_WDDBGHLT_Pos)) +#define RSWDT_MR_WDIDLEHLT_Pos _U_(29) /**< (RSWDT_MR) Watchdog Idle Halt Position */ +#define RSWDT_MR_WDIDLEHLT_Msk (_U_(0x1) << RSWDT_MR_WDIDLEHLT_Pos) /**< (RSWDT_MR) Watchdog Idle Halt Mask */ +#define RSWDT_MR_WDIDLEHLT(value) (RSWDT_MR_WDIDLEHLT_Msk & ((value) << RSWDT_MR_WDIDLEHLT_Pos)) +#define RSWDT_MR_Msk _U_(0x3FFFBFFF) /**< (RSWDT_MR) Register Mask */ + + +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) ( R/ 32) Status Register -------- */ +#define RSWDT_SR_WDUNF_Pos _U_(0) /**< (RSWDT_SR) Watchdog Underflow Position */ +#define RSWDT_SR_WDUNF_Msk (_U_(0x1) << RSWDT_SR_WDUNF_Pos) /**< (RSWDT_SR) Watchdog Underflow Mask */ +#define RSWDT_SR_WDUNF(value) (RSWDT_SR_WDUNF_Msk & ((value) << RSWDT_SR_WDUNF_Pos)) +#define RSWDT_SR_Msk _U_(0x00000001) /**< (RSWDT_SR) Register Mask */ + + +/** \brief RSWDT register offsets definitions */ +#define RSWDT_CR_REG_OFST (0x00) /**< (RSWDT_CR) Control Register Offset */ +#define RSWDT_MR_REG_OFST (0x04) /**< (RSWDT_MR) Mode Register Offset */ +#define RSWDT_SR_REG_OFST (0x08) /**< (RSWDT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RSWDT register API structure */ +typedef struct +{ + __O uint32_t RSWDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t RSWDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t RSWDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} rswdt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RSWDT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/rtc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/rtc.h new file mode 100644 index 00000000..b78df901 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/rtc.h @@ -0,0 +1,408 @@ +/** + * \brief Component description for RTC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_RTC_COMPONENT_H_ +#define _SAME70_RTC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RTC */ +/* ************************************************************************** */ + +/* -------- RTC_CR : (RTC Offset: 0x00) (R/W 32) Control Register -------- */ +#define RTC_CR_UPDTIM_Pos _U_(0) /**< (RTC_CR) Update Request Time Register Position */ +#define RTC_CR_UPDTIM_Msk (_U_(0x1) << RTC_CR_UPDTIM_Pos) /**< (RTC_CR) Update Request Time Register Mask */ +#define RTC_CR_UPDTIM(value) (RTC_CR_UPDTIM_Msk & ((value) << RTC_CR_UPDTIM_Pos)) +#define RTC_CR_UPDCAL_Pos _U_(1) /**< (RTC_CR) Update Request Calendar Register Position */ +#define RTC_CR_UPDCAL_Msk (_U_(0x1) << RTC_CR_UPDCAL_Pos) /**< (RTC_CR) Update Request Calendar Register Mask */ +#define RTC_CR_UPDCAL(value) (RTC_CR_UPDCAL_Msk & ((value) << RTC_CR_UPDCAL_Pos)) +#define RTC_CR_TIMEVSEL_Pos _U_(8) /**< (RTC_CR) Time Event Selection Position */ +#define RTC_CR_TIMEVSEL_Msk (_U_(0x3) << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Time Event Selection Mask */ +#define RTC_CR_TIMEVSEL(value) (RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)) +#define RTC_CR_TIMEVSEL_MINUTE_Val _U_(0x0) /**< (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR_Val _U_(0x1) /**< (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT_Val _U_(0x2) /**< (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON_Val _U_(0x3) /**< (RTC_CR) Every day at noon */ +#define RTC_CR_TIMEVSEL_MINUTE (RTC_CR_TIMEVSEL_MINUTE_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Minute change Position */ +#define RTC_CR_TIMEVSEL_HOUR (RTC_CR_TIMEVSEL_HOUR_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Hour change Position */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (RTC_CR_TIMEVSEL_MIDNIGHT_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at midnight Position */ +#define RTC_CR_TIMEVSEL_NOON (RTC_CR_TIMEVSEL_NOON_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at noon Position */ +#define RTC_CR_CALEVSEL_Pos _U_(16) /**< (RTC_CR) Calendar Event Selection Position */ +#define RTC_CR_CALEVSEL_Msk (_U_(0x3) << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Calendar Event Selection Mask */ +#define RTC_CR_CALEVSEL(value) (RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)) +#define RTC_CR_CALEVSEL_WEEK_Val _U_(0x0) /**< (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH_Val _U_(0x1) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR_Val _U_(0x2) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) */ +#define RTC_CR_CALEVSEL_WEEK (RTC_CR_CALEVSEL_WEEK_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Week change (every Monday at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_MONTH (RTC_CR_CALEVSEL_MONTH_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) Position */ +#define RTC_CR_CALEVSEL_YEAR (RTC_CR_CALEVSEL_YEAR_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) Position */ +#define RTC_CR_Msk _U_(0x00030303) /**< (RTC_CR) Register Mask */ + + +/* -------- RTC_MR : (RTC Offset: 0x04) (R/W 32) Mode Register -------- */ +#define RTC_MR_HRMOD_Pos _U_(0) /**< (RTC_MR) 12-/24-hour Mode Position */ +#define RTC_MR_HRMOD_Msk (_U_(0x1) << RTC_MR_HRMOD_Pos) /**< (RTC_MR) 12-/24-hour Mode Mask */ +#define RTC_MR_HRMOD(value) (RTC_MR_HRMOD_Msk & ((value) << RTC_MR_HRMOD_Pos)) +#define RTC_MR_PERSIAN_Pos _U_(1) /**< (RTC_MR) PERSIAN Calendar Position */ +#define RTC_MR_PERSIAN_Msk (_U_(0x1) << RTC_MR_PERSIAN_Pos) /**< (RTC_MR) PERSIAN Calendar Mask */ +#define RTC_MR_PERSIAN(value) (RTC_MR_PERSIAN_Msk & ((value) << RTC_MR_PERSIAN_Pos)) +#define RTC_MR_NEGPPM_Pos _U_(4) /**< (RTC_MR) NEGative PPM Correction Position */ +#define RTC_MR_NEGPPM_Msk (_U_(0x1) << RTC_MR_NEGPPM_Pos) /**< (RTC_MR) NEGative PPM Correction Mask */ +#define RTC_MR_NEGPPM(value) (RTC_MR_NEGPPM_Msk & ((value) << RTC_MR_NEGPPM_Pos)) +#define RTC_MR_CORRECTION_Pos _U_(8) /**< (RTC_MR) Slow Clock Correction Position */ +#define RTC_MR_CORRECTION_Msk (_U_(0x7F) << RTC_MR_CORRECTION_Pos) /**< (RTC_MR) Slow Clock Correction Mask */ +#define RTC_MR_CORRECTION(value) (RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)) +#define RTC_MR_HIGHPPM_Pos _U_(15) /**< (RTC_MR) HIGH PPM Correction Position */ +#define RTC_MR_HIGHPPM_Msk (_U_(0x1) << RTC_MR_HIGHPPM_Pos) /**< (RTC_MR) HIGH PPM Correction Mask */ +#define RTC_MR_HIGHPPM(value) (RTC_MR_HIGHPPM_Msk & ((value) << RTC_MR_HIGHPPM_Pos)) +#define RTC_MR_OUT0_Pos _U_(16) /**< (RTC_MR) RTCOUT0 OutputSource Selection Position */ +#define RTC_MR_OUT0_Msk (_U_(0x7) << RTC_MR_OUT0_Pos) /**< (RTC_MR) RTCOUT0 OutputSource Selection Mask */ +#define RTC_MR_OUT0(value) (RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)) +#define RTC_MR_OUT0_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT0_NO_WAVE (RTC_MR_OUT0_NO_WAVE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT0_FREQ1HZ (RTC_MR_OUT0_FREQ1HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ32HZ (RTC_MR_OUT0_FREQ32HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ64HZ (RTC_MR_OUT0_FREQ64HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT0_FREQ512HZ (RTC_MR_OUT0_FREQ512HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT0_ALARM_TOGGLE (RTC_MR_OUT0_ALARM_TOGGLE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT0_ALARM_FLAG (RTC_MR_OUT0_ALARM_FLAG_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT0_PROG_PULSE (RTC_MR_OUT0_PROG_PULSE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_OUT1_Pos _U_(20) /**< (RTC_MR) RTCOUT1 Output Source Selection Position */ +#define RTC_MR_OUT1_Msk (_U_(0x7) << RTC_MR_OUT1_Pos) /**< (RTC_MR) RTCOUT1 Output Source Selection Mask */ +#define RTC_MR_OUT1(value) (RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)) +#define RTC_MR_OUT1_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_NO_WAVE (RTC_MR_OUT1_NO_WAVE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ +#define RTC_MR_OUT1_FREQ1HZ (RTC_MR_OUT1_FREQ1HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 1 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ32HZ (RTC_MR_OUT1_FREQ32HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 32 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ64HZ (RTC_MR_OUT1_FREQ64HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 64 Hz square wave Position */ +#define RTC_MR_OUT1_FREQ512HZ (RTC_MR_OUT1_FREQ512HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 512 Hz square wave Position */ +#define RTC_MR_OUT1_ALARM_TOGGLE (RTC_MR_OUT1_ALARM_TOGGLE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ +#define RTC_MR_OUT1_ALARM_FLAG (RTC_MR_OUT1_ALARM_FLAG_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ +#define RTC_MR_OUT1_PROG_PULSE (RTC_MR_OUT1_PROG_PULSE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ +#define RTC_MR_THIGH_Pos _U_(24) /**< (RTC_MR) High Duration of the Output Pulse Position */ +#define RTC_MR_THIGH_Msk (_U_(0x7) << RTC_MR_THIGH_Pos) /**< (RTC_MR) High Duration of the Output Pulse Mask */ +#define RTC_MR_THIGH(value) (RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)) +#define RTC_MR_THIGH_H_31MS_Val _U_(0x0) /**< (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS_Val _U_(0x1) /**< (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS_Val _U_(0x2) /**< (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US_Val _U_(0x3) /**< (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US_Val _U_(0x4) /**< (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US_Val _U_(0x5) /**< (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US_Val _U_(0x6) /**< (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US_Val _U_(0x7) /**< (RTC_MR) 15.2 us */ +#define RTC_MR_THIGH_H_31MS (RTC_MR_THIGH_H_31MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 31.2 ms Position */ +#define RTC_MR_THIGH_H_16MS (RTC_MR_THIGH_H_16MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.6 ms Position */ +#define RTC_MR_THIGH_H_4MS (RTC_MR_THIGH_H_4MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 3.91 ms Position */ +#define RTC_MR_THIGH_H_976US (RTC_MR_THIGH_H_976US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 976 us Position */ +#define RTC_MR_THIGH_H_488US (RTC_MR_THIGH_H_488US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 488 us Position */ +#define RTC_MR_THIGH_H_122US (RTC_MR_THIGH_H_122US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 122 us Position */ +#define RTC_MR_THIGH_H_30US (RTC_MR_THIGH_H_30US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 30.5 us Position */ +#define RTC_MR_THIGH_H_15US (RTC_MR_THIGH_H_15US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.2 us Position */ +#define RTC_MR_TPERIOD_Pos _U_(28) /**< (RTC_MR) Period of the Output Pulse Position */ +#define RTC_MR_TPERIOD_Msk (_U_(0x3) << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) Period of the Output Pulse Mask */ +#define RTC_MR_TPERIOD(value) (RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)) +#define RTC_MR_TPERIOD_P_1S_Val _U_(0x0) /**< (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS_Val _U_(0x1) /**< (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS_Val _U_(0x2) /**< (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS_Val _U_(0x3) /**< (RTC_MR) 125 ms */ +#define RTC_MR_TPERIOD_P_1S (RTC_MR_TPERIOD_P_1S_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 1 second Position */ +#define RTC_MR_TPERIOD_P_500MS (RTC_MR_TPERIOD_P_500MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 500 ms Position */ +#define RTC_MR_TPERIOD_P_250MS (RTC_MR_TPERIOD_P_250MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 250 ms Position */ +#define RTC_MR_TPERIOD_P_125MS (RTC_MR_TPERIOD_P_125MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 125 ms Position */ +#define RTC_MR_Msk _U_(0x3777FF13) /**< (RTC_MR) Register Mask */ + + +/* -------- RTC_TIMR : (RTC Offset: 0x08) (R/W 32) Time Register -------- */ +#define RTC_TIMR_SEC_Pos _U_(0) /**< (RTC_TIMR) Current Second Position */ +#define RTC_TIMR_SEC_Msk (_U_(0x7F) << RTC_TIMR_SEC_Pos) /**< (RTC_TIMR) Current Second Mask */ +#define RTC_TIMR_SEC(value) (RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)) +#define RTC_TIMR_MIN_Pos _U_(8) /**< (RTC_TIMR) Current Minute Position */ +#define RTC_TIMR_MIN_Msk (_U_(0x7F) << RTC_TIMR_MIN_Pos) /**< (RTC_TIMR) Current Minute Mask */ +#define RTC_TIMR_MIN(value) (RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)) +#define RTC_TIMR_HOUR_Pos _U_(16) /**< (RTC_TIMR) Current Hour Position */ +#define RTC_TIMR_HOUR_Msk (_U_(0x3F) << RTC_TIMR_HOUR_Pos) /**< (RTC_TIMR) Current Hour Mask */ +#define RTC_TIMR_HOUR(value) (RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)) +#define RTC_TIMR_AMPM_Pos _U_(22) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Position */ +#define RTC_TIMR_AMPM_Msk (_U_(0x1) << RTC_TIMR_AMPM_Pos) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Mask */ +#define RTC_TIMR_AMPM(value) (RTC_TIMR_AMPM_Msk & ((value) << RTC_TIMR_AMPM_Pos)) +#define RTC_TIMR_Msk _U_(0x007F7F7F) /**< (RTC_TIMR) Register Mask */ + + +/* -------- RTC_CALR : (RTC Offset: 0x0C) (R/W 32) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos _U_(0) /**< (RTC_CALR) Current Century Position */ +#define RTC_CALR_CENT_Msk (_U_(0x7F) << RTC_CALR_CENT_Pos) /**< (RTC_CALR) Current Century Mask */ +#define RTC_CALR_CENT(value) (RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)) +#define RTC_CALR_YEAR_Pos _U_(8) /**< (RTC_CALR) Current Year Position */ +#define RTC_CALR_YEAR_Msk (_U_(0xFF) << RTC_CALR_YEAR_Pos) /**< (RTC_CALR) Current Year Mask */ +#define RTC_CALR_YEAR(value) (RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)) +#define RTC_CALR_MONTH_Pos _U_(16) /**< (RTC_CALR) Current Month Position */ +#define RTC_CALR_MONTH_Msk (_U_(0x1F) << RTC_CALR_MONTH_Pos) /**< (RTC_CALR) Current Month Mask */ +#define RTC_CALR_MONTH(value) (RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)) +#define RTC_CALR_DAY_Pos _U_(21) /**< (RTC_CALR) Current Day in Current Week Position */ +#define RTC_CALR_DAY_Msk (_U_(0x7) << RTC_CALR_DAY_Pos) /**< (RTC_CALR) Current Day in Current Week Mask */ +#define RTC_CALR_DAY(value) (RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)) +#define RTC_CALR_DATE_Pos _U_(24) /**< (RTC_CALR) Current Day in Current Month Position */ +#define RTC_CALR_DATE_Msk (_U_(0x3F) << RTC_CALR_DATE_Pos) /**< (RTC_CALR) Current Day in Current Month Mask */ +#define RTC_CALR_DATE(value) (RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)) +#define RTC_CALR_Msk _U_(0x3FFFFF7F) /**< (RTC_CALR) Register Mask */ + + +/* -------- RTC_TIMALR : (RTC Offset: 0x10) (R/W 32) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos _U_(0) /**< (RTC_TIMALR) Second Alarm Position */ +#define RTC_TIMALR_SEC_Msk (_U_(0x7F) << RTC_TIMALR_SEC_Pos) /**< (RTC_TIMALR) Second Alarm Mask */ +#define RTC_TIMALR_SEC(value) (RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)) +#define RTC_TIMALR_SECEN_Pos _U_(7) /**< (RTC_TIMALR) Second Alarm Enable Position */ +#define RTC_TIMALR_SECEN_Msk (_U_(0x1) << RTC_TIMALR_SECEN_Pos) /**< (RTC_TIMALR) Second Alarm Enable Mask */ +#define RTC_TIMALR_SECEN(value) (RTC_TIMALR_SECEN_Msk & ((value) << RTC_TIMALR_SECEN_Pos)) +#define RTC_TIMALR_MIN_Pos _U_(8) /**< (RTC_TIMALR) Minute Alarm Position */ +#define RTC_TIMALR_MIN_Msk (_U_(0x7F) << RTC_TIMALR_MIN_Pos) /**< (RTC_TIMALR) Minute Alarm Mask */ +#define RTC_TIMALR_MIN(value) (RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)) +#define RTC_TIMALR_MINEN_Pos _U_(15) /**< (RTC_TIMALR) Minute Alarm Enable Position */ +#define RTC_TIMALR_MINEN_Msk (_U_(0x1) << RTC_TIMALR_MINEN_Pos) /**< (RTC_TIMALR) Minute Alarm Enable Mask */ +#define RTC_TIMALR_MINEN(value) (RTC_TIMALR_MINEN_Msk & ((value) << RTC_TIMALR_MINEN_Pos)) +#define RTC_TIMALR_HOUR_Pos _U_(16) /**< (RTC_TIMALR) Hour Alarm Position */ +#define RTC_TIMALR_HOUR_Msk (_U_(0x3F) << RTC_TIMALR_HOUR_Pos) /**< (RTC_TIMALR) Hour Alarm Mask */ +#define RTC_TIMALR_HOUR(value) (RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)) +#define RTC_TIMALR_AMPM_Pos _U_(22) /**< (RTC_TIMALR) AM/PM Indicator Position */ +#define RTC_TIMALR_AMPM_Msk (_U_(0x1) << RTC_TIMALR_AMPM_Pos) /**< (RTC_TIMALR) AM/PM Indicator Mask */ +#define RTC_TIMALR_AMPM(value) (RTC_TIMALR_AMPM_Msk & ((value) << RTC_TIMALR_AMPM_Pos)) +#define RTC_TIMALR_HOUREN_Pos _U_(23) /**< (RTC_TIMALR) Hour Alarm Enable Position */ +#define RTC_TIMALR_HOUREN_Msk (_U_(0x1) << RTC_TIMALR_HOUREN_Pos) /**< (RTC_TIMALR) Hour Alarm Enable Mask */ +#define RTC_TIMALR_HOUREN(value) (RTC_TIMALR_HOUREN_Msk & ((value) << RTC_TIMALR_HOUREN_Pos)) +#define RTC_TIMALR_Msk _U_(0x00FFFFFF) /**< (RTC_TIMALR) Register Mask */ + + +/* -------- RTC_CALALR : (RTC Offset: 0x14) (R/W 32) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos _U_(16) /**< (RTC_CALALR) Month Alarm Position */ +#define RTC_CALALR_MONTH_Msk (_U_(0x1F) << RTC_CALALR_MONTH_Pos) /**< (RTC_CALALR) Month Alarm Mask */ +#define RTC_CALALR_MONTH(value) (RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)) +#define RTC_CALALR_MTHEN_Pos _U_(23) /**< (RTC_CALALR) Month Alarm Enable Position */ +#define RTC_CALALR_MTHEN_Msk (_U_(0x1) << RTC_CALALR_MTHEN_Pos) /**< (RTC_CALALR) Month Alarm Enable Mask */ +#define RTC_CALALR_MTHEN(value) (RTC_CALALR_MTHEN_Msk & ((value) << RTC_CALALR_MTHEN_Pos)) +#define RTC_CALALR_DATE_Pos _U_(24) /**< (RTC_CALALR) Date Alarm Position */ +#define RTC_CALALR_DATE_Msk (_U_(0x3F) << RTC_CALALR_DATE_Pos) /**< (RTC_CALALR) Date Alarm Mask */ +#define RTC_CALALR_DATE(value) (RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)) +#define RTC_CALALR_DATEEN_Pos _U_(31) /**< (RTC_CALALR) Date Alarm Enable Position */ +#define RTC_CALALR_DATEEN_Msk (_U_(0x1) << RTC_CALALR_DATEEN_Pos) /**< (RTC_CALALR) Date Alarm Enable Mask */ +#define RTC_CALALR_DATEEN(value) (RTC_CALALR_DATEEN_Msk & ((value) << RTC_CALALR_DATEEN_Pos)) +#define RTC_CALALR_Msk _U_(0xBF9F0000) /**< (RTC_CALALR) Register Mask */ + + +/* -------- RTC_SR : (RTC Offset: 0x18) ( R/ 32) Status Register -------- */ +#define RTC_SR_ACKUPD_Pos _U_(0) /**< (RTC_SR) Acknowledge for Update Position */ +#define RTC_SR_ACKUPD_Msk (_U_(0x1) << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Acknowledge for Update Mask */ +#define RTC_SR_ACKUPD(value) (RTC_SR_ACKUPD_Msk & ((value) << RTC_SR_ACKUPD_Pos)) +#define RTC_SR_ACKUPD_FREERUN_Val _U_(0x0) /**< (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE_Val _U_(0x1) /**< (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ACKUPD_FREERUN (RTC_SR_ACKUPD_FREERUN_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers cannot be updated. Position */ +#define RTC_SR_ACKUPD_UPDATE (RTC_SR_ACKUPD_UPDATE_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers can be updated. Position */ +#define RTC_SR_ALARM_Pos _U_(1) /**< (RTC_SR) Alarm Flag Position */ +#define RTC_SR_ALARM_Msk (_U_(0x1) << RTC_SR_ALARM_Pos) /**< (RTC_SR) Alarm Flag Mask */ +#define RTC_SR_ALARM(value) (RTC_SR_ALARM_Msk & ((value) << RTC_SR_ALARM_Pos)) +#define RTC_SR_ALARM_NO_ALARMEVENT_Val _U_(0x0) /**< (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT_Val _U_(0x1) /**< (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_ALARM_NO_ALARMEVENT (RTC_SR_ALARM_NO_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) No alarm matching condition occurred. Position */ +#define RTC_SR_ALARM_ALARMEVENT (RTC_SR_ALARM_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) An alarm matching condition has occurred. Position */ +#define RTC_SR_SEC_Pos _U_(2) /**< (RTC_SR) Second Event Position */ +#define RTC_SR_SEC_Msk (_U_(0x1) << RTC_SR_SEC_Pos) /**< (RTC_SR) Second Event Mask */ +#define RTC_SR_SEC(value) (RTC_SR_SEC_Msk & ((value) << RTC_SR_SEC_Pos)) +#define RTC_SR_SEC_NO_SECEVENT_Val _U_(0x0) /**< (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT_Val _U_(0x1) /**< (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_SEC_NO_SECEVENT (RTC_SR_SEC_NO_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) No second event has occurred since the last clear. Position */ +#define RTC_SR_SEC_SECEVENT (RTC_SR_SEC_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) At least one second event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_Pos _U_(3) /**< (RTC_SR) Time Event Position */ +#define RTC_SR_TIMEV_Msk (_U_(0x1) << RTC_SR_TIMEV_Pos) /**< (RTC_SR) Time Event Mask */ +#define RTC_SR_TIMEV(value) (RTC_SR_TIMEV_Msk & ((value) << RTC_SR_TIMEV_Pos)) +#define RTC_SR_TIMEV_NO_TIMEVENT_Val _U_(0x0) /**< (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT_Val _U_(0x1) /**< (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_NO_TIMEVENT (RTC_SR_TIMEV_NO_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) No time event has occurred since the last clear. Position */ +#define RTC_SR_TIMEV_TIMEVENT (RTC_SR_TIMEV_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) At least one time event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_Pos _U_(4) /**< (RTC_SR) Calendar Event Position */ +#define RTC_SR_CALEV_Msk (_U_(0x1) << RTC_SR_CALEV_Pos) /**< (RTC_SR) Calendar Event Mask */ +#define RTC_SR_CALEV(value) (RTC_SR_CALEV_Msk & ((value) << RTC_SR_CALEV_Pos)) +#define RTC_SR_CALEV_NO_CALEVENT_Val _U_(0x0) /**< (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT_Val _U_(0x1) /**< (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_NO_CALEVENT (RTC_SR_CALEV_NO_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) No calendar event has occurred since the last clear. Position */ +#define RTC_SR_CALEV_CALEVENT (RTC_SR_CALEV_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) At least one calendar event has occurred since the last clear. Position */ +#define RTC_SR_TDERR_Pos _U_(5) /**< (RTC_SR) Time and/or Date Free Running Error Position */ +#define RTC_SR_TDERR_Msk (_U_(0x1) << RTC_SR_TDERR_Pos) /**< (RTC_SR) Time and/or Date Free Running Error Mask */ +#define RTC_SR_TDERR(value) (RTC_SR_TDERR_Msk & ((value) << RTC_SR_TDERR_Pos)) +#define RTC_SR_TDERR_CORRECT_Val _U_(0x0) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE_Val _U_(0x1) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +#define RTC_SR_TDERR_CORRECT (RTC_SR_TDERR_CORRECT_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). Position */ +#define RTC_SR_TDERR_ERR_TIMEDATE (RTC_SR_TDERR_ERR_TIMEDATE_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. Position */ +#define RTC_SR_Msk _U_(0x0000003F) /**< (RTC_SR) Register Mask */ + + +/* -------- RTC_SCCR : (RTC Offset: 0x1C) ( /W 32) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR_Pos _U_(0) /**< (RTC_SCCR) Acknowledge Clear Position */ +#define RTC_SCCR_ACKCLR_Msk (_U_(0x1) << RTC_SCCR_ACKCLR_Pos) /**< (RTC_SCCR) Acknowledge Clear Mask */ +#define RTC_SCCR_ACKCLR(value) (RTC_SCCR_ACKCLR_Msk & ((value) << RTC_SCCR_ACKCLR_Pos)) +#define RTC_SCCR_ALRCLR_Pos _U_(1) /**< (RTC_SCCR) Alarm Clear Position */ +#define RTC_SCCR_ALRCLR_Msk (_U_(0x1) << RTC_SCCR_ALRCLR_Pos) /**< (RTC_SCCR) Alarm Clear Mask */ +#define RTC_SCCR_ALRCLR(value) (RTC_SCCR_ALRCLR_Msk & ((value) << RTC_SCCR_ALRCLR_Pos)) +#define RTC_SCCR_SECCLR_Pos _U_(2) /**< (RTC_SCCR) Second Clear Position */ +#define RTC_SCCR_SECCLR_Msk (_U_(0x1) << RTC_SCCR_SECCLR_Pos) /**< (RTC_SCCR) Second Clear Mask */ +#define RTC_SCCR_SECCLR(value) (RTC_SCCR_SECCLR_Msk & ((value) << RTC_SCCR_SECCLR_Pos)) +#define RTC_SCCR_TIMCLR_Pos _U_(3) /**< (RTC_SCCR) Time Clear Position */ +#define RTC_SCCR_TIMCLR_Msk (_U_(0x1) << RTC_SCCR_TIMCLR_Pos) /**< (RTC_SCCR) Time Clear Mask */ +#define RTC_SCCR_TIMCLR(value) (RTC_SCCR_TIMCLR_Msk & ((value) << RTC_SCCR_TIMCLR_Pos)) +#define RTC_SCCR_CALCLR_Pos _U_(4) /**< (RTC_SCCR) Calendar Clear Position */ +#define RTC_SCCR_CALCLR_Msk (_U_(0x1) << RTC_SCCR_CALCLR_Pos) /**< (RTC_SCCR) Calendar Clear Mask */ +#define RTC_SCCR_CALCLR(value) (RTC_SCCR_CALCLR_Msk & ((value) << RTC_SCCR_CALCLR_Pos)) +#define RTC_SCCR_TDERRCLR_Pos _U_(5) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Position */ +#define RTC_SCCR_TDERRCLR_Msk (_U_(0x1) << RTC_SCCR_TDERRCLR_Pos) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Mask */ +#define RTC_SCCR_TDERRCLR(value) (RTC_SCCR_TDERRCLR_Msk & ((value) << RTC_SCCR_TDERRCLR_Pos)) +#define RTC_SCCR_Msk _U_(0x0000003F) /**< (RTC_SCCR) Register Mask */ + + +/* -------- RTC_IER : (RTC Offset: 0x20) ( /W 32) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN_Pos _U_(0) /**< (RTC_IER) Acknowledge Update Interrupt Enable Position */ +#define RTC_IER_ACKEN_Msk (_U_(0x1) << RTC_IER_ACKEN_Pos) /**< (RTC_IER) Acknowledge Update Interrupt Enable Mask */ +#define RTC_IER_ACKEN(value) (RTC_IER_ACKEN_Msk & ((value) << RTC_IER_ACKEN_Pos)) +#define RTC_IER_ALREN_Pos _U_(1) /**< (RTC_IER) Alarm Interrupt Enable Position */ +#define RTC_IER_ALREN_Msk (_U_(0x1) << RTC_IER_ALREN_Pos) /**< (RTC_IER) Alarm Interrupt Enable Mask */ +#define RTC_IER_ALREN(value) (RTC_IER_ALREN_Msk & ((value) << RTC_IER_ALREN_Pos)) +#define RTC_IER_SECEN_Pos _U_(2) /**< (RTC_IER) Second Event Interrupt Enable Position */ +#define RTC_IER_SECEN_Msk (_U_(0x1) << RTC_IER_SECEN_Pos) /**< (RTC_IER) Second Event Interrupt Enable Mask */ +#define RTC_IER_SECEN(value) (RTC_IER_SECEN_Msk & ((value) << RTC_IER_SECEN_Pos)) +#define RTC_IER_TIMEN_Pos _U_(3) /**< (RTC_IER) Time Event Interrupt Enable Position */ +#define RTC_IER_TIMEN_Msk (_U_(0x1) << RTC_IER_TIMEN_Pos) /**< (RTC_IER) Time Event Interrupt Enable Mask */ +#define RTC_IER_TIMEN(value) (RTC_IER_TIMEN_Msk & ((value) << RTC_IER_TIMEN_Pos)) +#define RTC_IER_CALEN_Pos _U_(4) /**< (RTC_IER) Calendar Event Interrupt Enable Position */ +#define RTC_IER_CALEN_Msk (_U_(0x1) << RTC_IER_CALEN_Pos) /**< (RTC_IER) Calendar Event Interrupt Enable Mask */ +#define RTC_IER_CALEN(value) (RTC_IER_CALEN_Msk & ((value) << RTC_IER_CALEN_Pos)) +#define RTC_IER_TDERREN_Pos _U_(5) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Position */ +#define RTC_IER_TDERREN_Msk (_U_(0x1) << RTC_IER_TDERREN_Pos) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Mask */ +#define RTC_IER_TDERREN(value) (RTC_IER_TDERREN_Msk & ((value) << RTC_IER_TDERREN_Pos)) +#define RTC_IER_Msk _U_(0x0000003F) /**< (RTC_IER) Register Mask */ + + +/* -------- RTC_IDR : (RTC Offset: 0x24) ( /W 32) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS_Pos _U_(0) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Position */ +#define RTC_IDR_ACKDIS_Msk (_U_(0x1) << RTC_IDR_ACKDIS_Pos) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Mask */ +#define RTC_IDR_ACKDIS(value) (RTC_IDR_ACKDIS_Msk & ((value) << RTC_IDR_ACKDIS_Pos)) +#define RTC_IDR_ALRDIS_Pos _U_(1) /**< (RTC_IDR) Alarm Interrupt Disable Position */ +#define RTC_IDR_ALRDIS_Msk (_U_(0x1) << RTC_IDR_ALRDIS_Pos) /**< (RTC_IDR) Alarm Interrupt Disable Mask */ +#define RTC_IDR_ALRDIS(value) (RTC_IDR_ALRDIS_Msk & ((value) << RTC_IDR_ALRDIS_Pos)) +#define RTC_IDR_SECDIS_Pos _U_(2) /**< (RTC_IDR) Second Event Interrupt Disable Position */ +#define RTC_IDR_SECDIS_Msk (_U_(0x1) << RTC_IDR_SECDIS_Pos) /**< (RTC_IDR) Second Event Interrupt Disable Mask */ +#define RTC_IDR_SECDIS(value) (RTC_IDR_SECDIS_Msk & ((value) << RTC_IDR_SECDIS_Pos)) +#define RTC_IDR_TIMDIS_Pos _U_(3) /**< (RTC_IDR) Time Event Interrupt Disable Position */ +#define RTC_IDR_TIMDIS_Msk (_U_(0x1) << RTC_IDR_TIMDIS_Pos) /**< (RTC_IDR) Time Event Interrupt Disable Mask */ +#define RTC_IDR_TIMDIS(value) (RTC_IDR_TIMDIS_Msk & ((value) << RTC_IDR_TIMDIS_Pos)) +#define RTC_IDR_CALDIS_Pos _U_(4) /**< (RTC_IDR) Calendar Event Interrupt Disable Position */ +#define RTC_IDR_CALDIS_Msk (_U_(0x1) << RTC_IDR_CALDIS_Pos) /**< (RTC_IDR) Calendar Event Interrupt Disable Mask */ +#define RTC_IDR_CALDIS(value) (RTC_IDR_CALDIS_Msk & ((value) << RTC_IDR_CALDIS_Pos)) +#define RTC_IDR_TDERRDIS_Pos _U_(5) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Position */ +#define RTC_IDR_TDERRDIS_Msk (_U_(0x1) << RTC_IDR_TDERRDIS_Pos) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Mask */ +#define RTC_IDR_TDERRDIS(value) (RTC_IDR_TDERRDIS_Msk & ((value) << RTC_IDR_TDERRDIS_Pos)) +#define RTC_IDR_Msk _U_(0x0000003F) /**< (RTC_IDR) Register Mask */ + + +/* -------- RTC_IMR : (RTC Offset: 0x28) ( R/ 32) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK_Pos _U_(0) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Position */ +#define RTC_IMR_ACK_Msk (_U_(0x1) << RTC_IMR_ACK_Pos) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Mask */ +#define RTC_IMR_ACK(value) (RTC_IMR_ACK_Msk & ((value) << RTC_IMR_ACK_Pos)) +#define RTC_IMR_ALR_Pos _U_(1) /**< (RTC_IMR) Alarm Interrupt Mask Position */ +#define RTC_IMR_ALR_Msk (_U_(0x1) << RTC_IMR_ALR_Pos) /**< (RTC_IMR) Alarm Interrupt Mask Mask */ +#define RTC_IMR_ALR(value) (RTC_IMR_ALR_Msk & ((value) << RTC_IMR_ALR_Pos)) +#define RTC_IMR_SEC_Pos _U_(2) /**< (RTC_IMR) Second Event Interrupt Mask Position */ +#define RTC_IMR_SEC_Msk (_U_(0x1) << RTC_IMR_SEC_Pos) /**< (RTC_IMR) Second Event Interrupt Mask Mask */ +#define RTC_IMR_SEC(value) (RTC_IMR_SEC_Msk & ((value) << RTC_IMR_SEC_Pos)) +#define RTC_IMR_TIM_Pos _U_(3) /**< (RTC_IMR) Time Event Interrupt Mask Position */ +#define RTC_IMR_TIM_Msk (_U_(0x1) << RTC_IMR_TIM_Pos) /**< (RTC_IMR) Time Event Interrupt Mask Mask */ +#define RTC_IMR_TIM(value) (RTC_IMR_TIM_Msk & ((value) << RTC_IMR_TIM_Pos)) +#define RTC_IMR_CAL_Pos _U_(4) /**< (RTC_IMR) Calendar Event Interrupt Mask Position */ +#define RTC_IMR_CAL_Msk (_U_(0x1) << RTC_IMR_CAL_Pos) /**< (RTC_IMR) Calendar Event Interrupt Mask Mask */ +#define RTC_IMR_CAL(value) (RTC_IMR_CAL_Msk & ((value) << RTC_IMR_CAL_Pos)) +#define RTC_IMR_TDERR_Pos _U_(5) /**< (RTC_IMR) Time and/or Date Error Mask Position */ +#define RTC_IMR_TDERR_Msk (_U_(0x1) << RTC_IMR_TDERR_Pos) /**< (RTC_IMR) Time and/or Date Error Mask Mask */ +#define RTC_IMR_TDERR(value) (RTC_IMR_TDERR_Msk & ((value) << RTC_IMR_TDERR_Pos)) +#define RTC_IMR_Msk _U_(0x0000003F) /**< (RTC_IMR) Register Mask */ + + +/* -------- RTC_VER : (RTC Offset: 0x2C) ( R/ 32) Valid Entry Register -------- */ +#define RTC_VER_NVTIM_Pos _U_(0) /**< (RTC_VER) Non-valid Time Position */ +#define RTC_VER_NVTIM_Msk (_U_(0x1) << RTC_VER_NVTIM_Pos) /**< (RTC_VER) Non-valid Time Mask */ +#define RTC_VER_NVTIM(value) (RTC_VER_NVTIM_Msk & ((value) << RTC_VER_NVTIM_Pos)) +#define RTC_VER_NVCAL_Pos _U_(1) /**< (RTC_VER) Non-valid Calendar Position */ +#define RTC_VER_NVCAL_Msk (_U_(0x1) << RTC_VER_NVCAL_Pos) /**< (RTC_VER) Non-valid Calendar Mask */ +#define RTC_VER_NVCAL(value) (RTC_VER_NVCAL_Msk & ((value) << RTC_VER_NVCAL_Pos)) +#define RTC_VER_NVTIMALR_Pos _U_(2) /**< (RTC_VER) Non-valid Time Alarm Position */ +#define RTC_VER_NVTIMALR_Msk (_U_(0x1) << RTC_VER_NVTIMALR_Pos) /**< (RTC_VER) Non-valid Time Alarm Mask */ +#define RTC_VER_NVTIMALR(value) (RTC_VER_NVTIMALR_Msk & ((value) << RTC_VER_NVTIMALR_Pos)) +#define RTC_VER_NVCALALR_Pos _U_(3) /**< (RTC_VER) Non-valid Calendar Alarm Position */ +#define RTC_VER_NVCALALR_Msk (_U_(0x1) << RTC_VER_NVCALALR_Pos) /**< (RTC_VER) Non-valid Calendar Alarm Mask */ +#define RTC_VER_NVCALALR(value) (RTC_VER_NVCALALR_Msk & ((value) << RTC_VER_NVCALALR_Pos)) +#define RTC_VER_Msk _U_(0x0000000F) /**< (RTC_VER) Register Mask */ + + +/** \brief RTC register offsets definitions */ +#define RTC_CR_REG_OFST (0x00) /**< (RTC_CR) Control Register Offset */ +#define RTC_MR_REG_OFST (0x04) /**< (RTC_MR) Mode Register Offset */ +#define RTC_TIMR_REG_OFST (0x08) /**< (RTC_TIMR) Time Register Offset */ +#define RTC_CALR_REG_OFST (0x0C) /**< (RTC_CALR) Calendar Register Offset */ +#define RTC_TIMALR_REG_OFST (0x10) /**< (RTC_TIMALR) Time Alarm Register Offset */ +#define RTC_CALALR_REG_OFST (0x14) /**< (RTC_CALALR) Calendar Alarm Register Offset */ +#define RTC_SR_REG_OFST (0x18) /**< (RTC_SR) Status Register Offset */ +#define RTC_SCCR_REG_OFST (0x1C) /**< (RTC_SCCR) Status Clear Command Register Offset */ +#define RTC_IER_REG_OFST (0x20) /**< (RTC_IER) Interrupt Enable Register Offset */ +#define RTC_IDR_REG_OFST (0x24) /**< (RTC_IDR) Interrupt Disable Register Offset */ +#define RTC_IMR_REG_OFST (0x28) /**< (RTC_IMR) Interrupt Mask Register Offset */ +#define RTC_VER_REG_OFST (0x2C) /**< (RTC_VER) Valid Entry Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RTC register API structure */ +typedef struct +{ + __IO uint32_t RTC_CR; /**< Offset: 0x00 (R/W 32) Control Register */ + __IO uint32_t RTC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __IO uint32_t RTC_TIMR; /**< Offset: 0x08 (R/W 32) Time Register */ + __IO uint32_t RTC_CALR; /**< Offset: 0x0C (R/W 32) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< Offset: 0x10 (R/W 32) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< Offset: 0x14 (R/W 32) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< Offset: 0x18 (R/ 32) Status Register */ + __O uint32_t RTC_SCCR; /**< Offset: 0x1C ( /W 32) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< Offset: 0x20 ( /W 32) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< Offset: 0x24 ( /W 32) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< Offset: 0x28 (R/ 32) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< Offset: 0x2C (R/ 32) Valid Entry Register */ +} rtc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RTC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/rtt.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/rtt.h new file mode 100644 index 00000000..ac2c6adb --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/rtt.h @@ -0,0 +1,95 @@ +/** + * \brief Component description for RTT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_RTT_COMPONENT_H_ +#define _SAME70_RTT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR RTT */ +/* ************************************************************************** */ + +/* -------- RTT_MR : (RTT Offset: 0x00) (R/W 32) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos _U_(0) /**< (RTT_MR) Real-time Timer Prescaler Value Position */ +#define RTT_MR_RTPRES_Msk (_U_(0xFFFF) << RTT_MR_RTPRES_Pos) /**< (RTT_MR) Real-time Timer Prescaler Value Mask */ +#define RTT_MR_RTPRES(value) (RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)) +#define RTT_MR_ALMIEN_Pos _U_(16) /**< (RTT_MR) Alarm Interrupt Enable Position */ +#define RTT_MR_ALMIEN_Msk (_U_(0x1) << RTT_MR_ALMIEN_Pos) /**< (RTT_MR) Alarm Interrupt Enable Mask */ +#define RTT_MR_ALMIEN(value) (RTT_MR_ALMIEN_Msk & ((value) << RTT_MR_ALMIEN_Pos)) +#define RTT_MR_RTTINCIEN_Pos _U_(17) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Position */ +#define RTT_MR_RTTINCIEN_Msk (_U_(0x1) << RTT_MR_RTTINCIEN_Pos) /**< (RTT_MR) Real-time Timer Increment Interrupt Enable Mask */ +#define RTT_MR_RTTINCIEN(value) (RTT_MR_RTTINCIEN_Msk & ((value) << RTT_MR_RTTINCIEN_Pos)) +#define RTT_MR_RTTRST_Pos _U_(18) /**< (RTT_MR) Real-time Timer Restart Position */ +#define RTT_MR_RTTRST_Msk (_U_(0x1) << RTT_MR_RTTRST_Pos) /**< (RTT_MR) Real-time Timer Restart Mask */ +#define RTT_MR_RTTRST(value) (RTT_MR_RTTRST_Msk & ((value) << RTT_MR_RTTRST_Pos)) +#define RTT_MR_RTTDIS_Pos _U_(20) /**< (RTT_MR) Real-time Timer Disable Position */ +#define RTT_MR_RTTDIS_Msk (_U_(0x1) << RTT_MR_RTTDIS_Pos) /**< (RTT_MR) Real-time Timer Disable Mask */ +#define RTT_MR_RTTDIS(value) (RTT_MR_RTTDIS_Msk & ((value) << RTT_MR_RTTDIS_Pos)) +#define RTT_MR_RTC1HZ_Pos _U_(24) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Position */ +#define RTT_MR_RTC1HZ_Msk (_U_(0x1) << RTT_MR_RTC1HZ_Pos) /**< (RTT_MR) Real-Time Clock 1Hz Clock Selection Mask */ +#define RTT_MR_RTC1HZ(value) (RTT_MR_RTC1HZ_Msk & ((value) << RTT_MR_RTC1HZ_Pos)) +#define RTT_MR_Msk _U_(0x0117FFFF) /**< (RTT_MR) Register Mask */ + + +/* -------- RTT_AR : (RTT Offset: 0x04) (R/W 32) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos _U_(0) /**< (RTT_AR) Alarm Value Position */ +#define RTT_AR_ALMV_Msk (_U_(0xFFFFFFFF) << RTT_AR_ALMV_Pos) /**< (RTT_AR) Alarm Value Mask */ +#define RTT_AR_ALMV(value) (RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)) +#define RTT_AR_Msk _U_(0xFFFFFFFF) /**< (RTT_AR) Register Mask */ + + +/* -------- RTT_VR : (RTT Offset: 0x08) ( R/ 32) Value Register -------- */ +#define RTT_VR_CRTV_Pos _U_(0) /**< (RTT_VR) Current Real-time Value Position */ +#define RTT_VR_CRTV_Msk (_U_(0xFFFFFFFF) << RTT_VR_CRTV_Pos) /**< (RTT_VR) Current Real-time Value Mask */ +#define RTT_VR_CRTV(value) (RTT_VR_CRTV_Msk & ((value) << RTT_VR_CRTV_Pos)) +#define RTT_VR_Msk _U_(0xFFFFFFFF) /**< (RTT_VR) Register Mask */ + + +/* -------- RTT_SR : (RTT Offset: 0x0C) ( R/ 32) Status Register -------- */ +#define RTT_SR_ALMS_Pos _U_(0) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Position */ +#define RTT_SR_ALMS_Msk (_U_(0x1) << RTT_SR_ALMS_Pos) /**< (RTT_SR) Real-time Alarm Status (cleared on read) Mask */ +#define RTT_SR_ALMS(value) (RTT_SR_ALMS_Msk & ((value) << RTT_SR_ALMS_Pos)) +#define RTT_SR_RTTINC_Pos _U_(1) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Position */ +#define RTT_SR_RTTINC_Msk (_U_(0x1) << RTT_SR_RTTINC_Pos) /**< (RTT_SR) Prescaler Roll-over Status (cleared on read) Mask */ +#define RTT_SR_RTTINC(value) (RTT_SR_RTTINC_Msk & ((value) << RTT_SR_RTTINC_Pos)) +#define RTT_SR_Msk _U_(0x00000003) /**< (RTT_SR) Register Mask */ + + +/** \brief RTT register offsets definitions */ +#define RTT_MR_REG_OFST (0x00) /**< (RTT_MR) Mode Register Offset */ +#define RTT_AR_REG_OFST (0x04) /**< (RTT_AR) Alarm Register Offset */ +#define RTT_VR_REG_OFST (0x08) /**< (RTT_VR) Value Register Offset */ +#define RTT_SR_REG_OFST (0x0C) /**< (RTT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief RTT register API structure */ +typedef struct +{ + __IO uint32_t RTT_MR; /**< Offset: 0x00 (R/W 32) Mode Register */ + __IO uint32_t RTT_AR; /**< Offset: 0x04 (R/W 32) Alarm Register */ + __I uint32_t RTT_VR; /**< Offset: 0x08 (R/ 32) Value Register */ + __I uint32_t RTT_SR; /**< Offset: 0x0C (R/ 32) Status Register */ +} rtt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_RTT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/sdramc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/sdramc.h new file mode 100644 index 00000000..fce0f7dd --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/sdramc.h @@ -0,0 +1,264 @@ +/** + * \brief Component description for SDRAMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_SDRAMC_COMPONENT_H_ +#define _SAME70_SDRAMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SDRAMC */ +/* ************************************************************************** */ + +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) (R/W 32) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos _U_(0) /**< (SDRAMC_MR) SDRAMC Command Mode Position */ +#define SDRAMC_MR_MODE_Msk (_U_(0x7) << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) SDRAMC Command Mode Mask */ +#define SDRAMC_MR_MODE(value) (SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)) +#define SDRAMC_MR_MODE_NORMAL_Val _U_(0x0) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP_Val _U_(0x1) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val _U_(0x2) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG_Val _U_(0x3) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH_Val _U_(0x4) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val _U_(0x5) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN_Val _U_(0x6) /**< (SDRAMC_MR) Deep Power-down mode. Enters Deep Power-down mode. */ +#define SDRAMC_MR_MODE_NORMAL (SDRAMC_MR_MODE_NORMAL_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_NOP (SDRAMC_MR_MODE_NOP_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (SDRAMC_MR_MODE_ALLBANKS_PRECHARGE_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (SDRAMC_MR_MODE_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (SDRAMC_MR_MODE_AUTO_REFRESH_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, the command must be followed by a write to the SDRAM. Position */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (SDRAMC_MR_MODE_EXT_LOAD_MODEREG_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. Position */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (SDRAMC_MR_MODE_DEEP_POWERDOWN_Val << SDRAMC_MR_MODE_Pos) /**< (SDRAMC_MR) Deep Power-down mode. Enters Deep Power-down mode. Position */ +#define SDRAMC_MR_Msk _U_(0x00000007) /**< (SDRAMC_MR) Register Mask */ + + +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) (R/W 32) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos _U_(0) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Position */ +#define SDRAMC_TR_COUNT_Msk (_U_(0xFFF) << SDRAMC_TR_COUNT_Pos) /**< (SDRAMC_TR) SDRAMC Refresh Timer Count Mask */ +#define SDRAMC_TR_COUNT(value) (SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)) +#define SDRAMC_TR_Msk _U_(0x00000FFF) /**< (SDRAMC_TR) Register Mask */ + + +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) (R/W 32) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos _U_(0) /**< (SDRAMC_CR) Number of Column Bits Position */ +#define SDRAMC_CR_NC_Msk (_U_(0x3) << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) Number of Column Bits Mask */ +#define SDRAMC_CR_NC(value) (SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)) +#define SDRAMC_CR_NC_COL8_Val _U_(0x0) /**< (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9_Val _U_(0x1) /**< (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10_Val _U_(0x2) /**< (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11_Val _U_(0x3) /**< (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NC_COL8 (SDRAMC_CR_NC_COL8_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 8 column bits Position */ +#define SDRAMC_CR_NC_COL9 (SDRAMC_CR_NC_COL9_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 9 column bits Position */ +#define SDRAMC_CR_NC_COL10 (SDRAMC_CR_NC_COL10_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 10 column bits Position */ +#define SDRAMC_CR_NC_COL11 (SDRAMC_CR_NC_COL11_Val << SDRAMC_CR_NC_Pos) /**< (SDRAMC_CR) 11 column bits Position */ +#define SDRAMC_CR_NR_Pos _U_(2) /**< (SDRAMC_CR) Number of Row Bits Position */ +#define SDRAMC_CR_NR_Msk (_U_(0x3) << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) Number of Row Bits Mask */ +#define SDRAMC_CR_NR(value) (SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)) +#define SDRAMC_CR_NR_ROW11_Val _U_(0x0) /**< (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12_Val _U_(0x1) /**< (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13_Val _U_(0x2) /**< (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NR_ROW11 (SDRAMC_CR_NR_ROW11_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 11 row bits Position */ +#define SDRAMC_CR_NR_ROW12 (SDRAMC_CR_NR_ROW12_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 12 row bits Position */ +#define SDRAMC_CR_NR_ROW13 (SDRAMC_CR_NR_ROW13_Val << SDRAMC_CR_NR_Pos) /**< (SDRAMC_CR) 13 row bits Position */ +#define SDRAMC_CR_NB_Pos _U_(4) /**< (SDRAMC_CR) Number of Banks Position */ +#define SDRAMC_CR_NB_Msk (_U_(0x1) << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) Number of Banks Mask */ +#define SDRAMC_CR_NB(value) (SDRAMC_CR_NB_Msk & ((value) << SDRAMC_CR_NB_Pos)) +#define SDRAMC_CR_NB_BANK2_Val _U_(0x0) /**< (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4_Val _U_(0x1) /**< (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_NB_BANK2 (SDRAMC_CR_NB_BANK2_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 2 banks Position */ +#define SDRAMC_CR_NB_BANK4 (SDRAMC_CR_NB_BANK4_Val << SDRAMC_CR_NB_Pos) /**< (SDRAMC_CR) 4 banks Position */ +#define SDRAMC_CR_CAS_Pos _U_(5) /**< (SDRAMC_CR) CAS Latency Position */ +#define SDRAMC_CR_CAS_Msk (_U_(0x3) << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) CAS Latency Mask */ +#define SDRAMC_CR_CAS(value) (SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)) +#define SDRAMC_CR_CAS_LATENCY1_Val _U_(0x1) /**< (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2_Val _U_(0x2) /**< (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3_Val _U_(0x3) /**< (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY1 (SDRAMC_CR_CAS_LATENCY1_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 1 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY2 (SDRAMC_CR_CAS_LATENCY2_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 2 cycle CAS latency Position */ +#define SDRAMC_CR_CAS_LATENCY3 (SDRAMC_CR_CAS_LATENCY3_Val << SDRAMC_CR_CAS_Pos) /**< (SDRAMC_CR) 3 cycle CAS latency Position */ +#define SDRAMC_CR_DBW_Pos _U_(7) /**< (SDRAMC_CR) Data Bus Width Position */ +#define SDRAMC_CR_DBW_Msk (_U_(0x1) << SDRAMC_CR_DBW_Pos) /**< (SDRAMC_CR) Data Bus Width Mask */ +#define SDRAMC_CR_DBW(value) (SDRAMC_CR_DBW_Msk & ((value) << SDRAMC_CR_DBW_Pos)) +#define SDRAMC_CR_TWR_Pos _U_(8) /**< (SDRAMC_CR) Write Recovery Delay Position */ +#define SDRAMC_CR_TWR_Msk (_U_(0xF) << SDRAMC_CR_TWR_Pos) /**< (SDRAMC_CR) Write Recovery Delay Mask */ +#define SDRAMC_CR_TWR(value) (SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)) +#define SDRAMC_CR_TRC_TRFC_Pos _U_(12) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Position */ +#define SDRAMC_CR_TRC_TRFC_Msk (_U_(0xF) << SDRAMC_CR_TRC_TRFC_Pos) /**< (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle Mask */ +#define SDRAMC_CR_TRC_TRFC(value) (SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)) +#define SDRAMC_CR_TRP_Pos _U_(16) /**< (SDRAMC_CR) Row Precharge Delay Position */ +#define SDRAMC_CR_TRP_Msk (_U_(0xF) << SDRAMC_CR_TRP_Pos) /**< (SDRAMC_CR) Row Precharge Delay Mask */ +#define SDRAMC_CR_TRP(value) (SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)) +#define SDRAMC_CR_TRCD_Pos _U_(20) /**< (SDRAMC_CR) Row to Column Delay Position */ +#define SDRAMC_CR_TRCD_Msk (_U_(0xF) << SDRAMC_CR_TRCD_Pos) /**< (SDRAMC_CR) Row to Column Delay Mask */ +#define SDRAMC_CR_TRCD(value) (SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)) +#define SDRAMC_CR_TRAS_Pos _U_(24) /**< (SDRAMC_CR) Active to Precharge Delay Position */ +#define SDRAMC_CR_TRAS_Msk (_U_(0xF) << SDRAMC_CR_TRAS_Pos) /**< (SDRAMC_CR) Active to Precharge Delay Mask */ +#define SDRAMC_CR_TRAS(value) (SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)) +#define SDRAMC_CR_TXSR_Pos _U_(28) /**< (SDRAMC_CR) Exit Self-Refresh to Active Delay Position */ +#define SDRAMC_CR_TXSR_Msk (_U_(0xF) << SDRAMC_CR_TXSR_Pos) /**< (SDRAMC_CR) Exit Self-Refresh to Active Delay Mask */ +#define SDRAMC_CR_TXSR(value) (SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)) +#define SDRAMC_CR_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_CR) Register Mask */ + + +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) (R/W 32) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos _U_(0) /**< (SDRAMC_LPR) Low-power Configuration Bits Position */ +#define SDRAMC_LPR_LPCB_Msk (_U_(0x3) << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) Low-power Configuration Bits Mask */ +#define SDRAMC_LPR_LPCB(value) (SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)) +#define SDRAMC_LPR_LPCB_DISABLED_Val _U_(0x0) /**< (SDRAMC_LPR) The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val _U_(0x3) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_LPCB_DISABLED (SDRAMC_LPR_LPCB_DISABLED_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The low-power feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. Position */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (SDRAMC_LPR_LPCB_SELF_REFRESH_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self-refresh mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (SDRAMC_LPR_LPCB_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down mode when accessed and enters it after the access. Position */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (SDRAMC_LPR_LPCB_DEEP_POWER_DOWN_Val << SDRAMC_LPR_LPCB_Pos) /**< (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. Position */ +#define SDRAMC_LPR_PASR_Pos _U_(4) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_PASR_Msk (_U_(0x7) << SDRAMC_LPR_PASR_Pos) /**< (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_PASR(value) (SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)) +#define SDRAMC_LPR_TCSR_Pos _U_(8) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_TCSR_Msk (_U_(0x3) << SDRAMC_LPR_TCSR_Pos) /**< (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_TCSR(value) (SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)) +#define SDRAMC_LPR_DS_Pos _U_(10) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Position */ +#define SDRAMC_LPR_DS_Msk (_U_(0x3) << SDRAMC_LPR_DS_Pos) /**< (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) Mask */ +#define SDRAMC_LPR_DS(value) (SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)) +#define SDRAMC_LPR_TIMEOUT_Pos _U_(12) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Position */ +#define SDRAMC_LPR_TIMEOUT_Msk (_U_(0x3) << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled Mask */ +#define SDRAMC_LPR_TIMEOUT(value) (SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val _U_(0x0) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val _U_(0x1) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val _U_(0x2) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode immediately after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128_Val << SDRAMC_LPR_TIMEOUT_Pos) /**< (SDRAMC_LPR) The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after the end of the last transfer. Position */ +#define SDRAMC_LPR_Msk _U_(0x00003F73) /**< (SDRAMC_LPR) Register Mask */ + + +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) ( /W 32) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES_Pos _U_(0) /**< (SDRAMC_IER) Refresh Error Interrupt Enable Position */ +#define SDRAMC_IER_RES_Msk (_U_(0x1) << SDRAMC_IER_RES_Pos) /**< (SDRAMC_IER) Refresh Error Interrupt Enable Mask */ +#define SDRAMC_IER_RES(value) (SDRAMC_IER_RES_Msk & ((value) << SDRAMC_IER_RES_Pos)) +#define SDRAMC_IER_Msk _U_(0x00000001) /**< (SDRAMC_IER) Register Mask */ + + +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) ( /W 32) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES_Pos _U_(0) /**< (SDRAMC_IDR) Refresh Error Interrupt Disable Position */ +#define SDRAMC_IDR_RES_Msk (_U_(0x1) << SDRAMC_IDR_RES_Pos) /**< (SDRAMC_IDR) Refresh Error Interrupt Disable Mask */ +#define SDRAMC_IDR_RES(value) (SDRAMC_IDR_RES_Msk & ((value) << SDRAMC_IDR_RES_Pos)) +#define SDRAMC_IDR_Msk _U_(0x00000001) /**< (SDRAMC_IDR) Register Mask */ + + +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) ( R/ 32) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES_Pos _U_(0) /**< (SDRAMC_IMR) Refresh Error Interrupt Mask Position */ +#define SDRAMC_IMR_RES_Msk (_U_(0x1) << SDRAMC_IMR_RES_Pos) /**< (SDRAMC_IMR) Refresh Error Interrupt Mask Mask */ +#define SDRAMC_IMR_RES(value) (SDRAMC_IMR_RES_Msk & ((value) << SDRAMC_IMR_RES_Pos)) +#define SDRAMC_IMR_Msk _U_(0x00000001) /**< (SDRAMC_IMR) Register Mask */ + + +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) ( R/ 32) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES_Pos _U_(0) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Position */ +#define SDRAMC_ISR_RES_Msk (_U_(0x1) << SDRAMC_ISR_RES_Pos) /**< (SDRAMC_ISR) Refresh Error Status (cleared on read) Mask */ +#define SDRAMC_ISR_RES(value) (SDRAMC_ISR_RES_Msk & ((value) << SDRAMC_ISR_RES_Pos)) +#define SDRAMC_ISR_Msk _U_(0x00000001) /**< (SDRAMC_ISR) Register Mask */ + + +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) (R/W 32) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos _U_(0) /**< (SDRAMC_MDR) Memory Device Type Position */ +#define SDRAMC_MDR_MD_Msk (_U_(0x3) << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Memory Device Type Mask */ +#define SDRAMC_MDR_MD(value) (SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)) +#define SDRAMC_MDR_MD_SDRAM_Val _U_(0x0) /**< (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM_Val _U_(0x1) /**< (SDRAMC_MDR) Low-power SDRAM */ +#define SDRAMC_MDR_MD_SDRAM (SDRAMC_MDR_MD_SDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) SDRAM Position */ +#define SDRAMC_MDR_MD_LPSDRAM (SDRAMC_MDR_MD_LPSDRAM_Val << SDRAMC_MDR_MD_Pos) /**< (SDRAMC_MDR) Low-power SDRAM Position */ +#define SDRAMC_MDR_Msk _U_(0x00000003) /**< (SDRAMC_MDR) Register Mask */ + + +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) (R/W 32) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos _U_(0) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Position */ +#define SDRAMC_CFR1_TMRD_Msk (_U_(0xF) << SDRAMC_CFR1_TMRD_Pos) /**< (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command Mask */ +#define SDRAMC_CFR1_TMRD(value) (SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)) +#define SDRAMC_CFR1_UNAL_Pos _U_(8) /**< (SDRAMC_CFR1) Support Unaligned Access Position */ +#define SDRAMC_CFR1_UNAL_Msk (_U_(0x1) << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Support Unaligned Access Mask */ +#define SDRAMC_CFR1_UNAL(value) (SDRAMC_CFR1_UNAL_Msk & ((value) << SDRAMC_CFR1_UNAL_Pos)) +#define SDRAMC_CFR1_UNAL_UNSUPPORTED_Val _U_(0x0) /**< (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED_Val _U_(0x1) /**< (SDRAMC_CFR1) Unaligned access is supported. */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (SDRAMC_CFR1_UNAL_UNSUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is not supported. Position */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (SDRAMC_CFR1_UNAL_SUPPORTED_Val << SDRAMC_CFR1_UNAL_Pos) /**< (SDRAMC_CFR1) Unaligned access is supported. Position */ +#define SDRAMC_CFR1_Msk _U_(0x0000010F) /**< (SDRAMC_CFR1) Register Mask */ + + +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) (R/W 32) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE_Pos _U_(0) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Position */ +#define SDRAMC_OCMS_SDR_SE_Msk (_U_(0x1) << SDRAMC_OCMS_SDR_SE_Pos) /**< (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable Mask */ +#define SDRAMC_OCMS_SDR_SE(value) (SDRAMC_OCMS_SDR_SE_Msk & ((value) << SDRAMC_OCMS_SDR_SE_Pos)) +#define SDRAMC_OCMS_Msk _U_(0x00000001) /**< (SDRAMC_OCMS) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) ( /W 32) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos _U_(0) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SDRAMC_OCMS_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SDRAMC_OCMS_KEY1_KEY1(value) (SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)) +#define SDRAMC_OCMS_KEY1_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY1) Register Mask */ + + +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) ( /W 32) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos _U_(0) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SDRAMC_OCMS_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SDRAMC_OCMS_KEY2_KEY2(value) (SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)) +#define SDRAMC_OCMS_KEY2_Msk _U_(0xFFFFFFFF) /**< (SDRAMC_OCMS_KEY2) Register Mask */ + + +/** \brief SDRAMC register offsets definitions */ +#define SDRAMC_MR_REG_OFST (0x00) /**< (SDRAMC_MR) SDRAMC Mode Register Offset */ +#define SDRAMC_TR_REG_OFST (0x04) /**< (SDRAMC_TR) SDRAMC Refresh Timer Register Offset */ +#define SDRAMC_CR_REG_OFST (0x08) /**< (SDRAMC_CR) SDRAMC Configuration Register Offset */ +#define SDRAMC_LPR_REG_OFST (0x10) /**< (SDRAMC_LPR) SDRAMC Low Power Register Offset */ +#define SDRAMC_IER_REG_OFST (0x14) /**< (SDRAMC_IER) SDRAMC Interrupt Enable Register Offset */ +#define SDRAMC_IDR_REG_OFST (0x18) /**< (SDRAMC_IDR) SDRAMC Interrupt Disable Register Offset */ +#define SDRAMC_IMR_REG_OFST (0x1C) /**< (SDRAMC_IMR) SDRAMC Interrupt Mask Register Offset */ +#define SDRAMC_ISR_REG_OFST (0x20) /**< (SDRAMC_ISR) SDRAMC Interrupt Status Register Offset */ +#define SDRAMC_MDR_REG_OFST (0x24) /**< (SDRAMC_MDR) SDRAMC Memory Device Register Offset */ +#define SDRAMC_CFR1_REG_OFST (0x28) /**< (SDRAMC_CFR1) SDRAMC Configuration Register 1 Offset */ +#define SDRAMC_OCMS_REG_OFST (0x2C) /**< (SDRAMC_OCMS) SDRAMC OCMS Register Offset */ +#define SDRAMC_OCMS_KEY1_REG_OFST (0x30) /**< (SDRAMC_OCMS_KEY1) SDRAMC OCMS KEY1 Register Offset */ +#define SDRAMC_OCMS_KEY2_REG_OFST (0x34) /**< (SDRAMC_OCMS_KEY2) SDRAMC OCMS KEY2 Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SDRAMC register API structure */ +typedef struct +{ + __IO uint32_t SDRAMC_MR; /**< Offset: 0x00 (R/W 32) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< Offset: 0x04 (R/W 32) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< Offset: 0x08 (R/W 32) SDRAMC Configuration Register */ + __I uint8_t Reserved1[0x04]; + __IO uint32_t SDRAMC_LPR; /**< Offset: 0x10 (R/W 32) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< Offset: 0x14 ( /W 32) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< Offset: 0x18 ( /W 32) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< Offset: 0x1C (R/ 32) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< Offset: 0x20 (R/ 32) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< Offset: 0x24 (R/W 32) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< Offset: 0x28 (R/W 32) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< Offset: 0x2C (R/W 32) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< Offset: 0x30 ( /W 32) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< Offset: 0x34 ( /W 32) SDRAMC OCMS KEY2 Register */ +} sdramc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SDRAMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/smc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/smc.h new file mode 100644 index 00000000..08dd4098 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/smc.h @@ -0,0 +1,219 @@ +/** + * \brief Component description for SMC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_SMC_COMPONENT_H_ +#define _SAME70_SMC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SMC */ +/* ************************************************************************** */ + +/* -------- SMC_SETUP : (SMC Offset: 0x00) (R/W 32) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos _U_(0) /**< (SMC_SETUP) NWE Setup Length Position */ +#define SMC_SETUP_NWE_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NWE_SETUP_Pos) /**< (SMC_SETUP) NWE Setup Length Mask */ +#define SMC_SETUP_NWE_SETUP(value) (SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)) +#define SMC_SETUP_NCS_WR_SETUP_Pos _U_(8) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Position */ +#define SMC_SETUP_NCS_WR_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_WR_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Mask */ +#define SMC_SETUP_NCS_WR_SETUP(value) (SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)) +#define SMC_SETUP_NRD_SETUP_Pos _U_(16) /**< (SMC_SETUP) NRD Setup Length Position */ +#define SMC_SETUP_NRD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NRD_SETUP_Pos) /**< (SMC_SETUP) NRD Setup Length Mask */ +#define SMC_SETUP_NRD_SETUP(value) (SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)) +#define SMC_SETUP_NCS_RD_SETUP_Pos _U_(24) /**< (SMC_SETUP) NCS Setup Length in READ Access Position */ +#define SMC_SETUP_NCS_RD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_RD_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in READ Access Mask */ +#define SMC_SETUP_NCS_RD_SETUP(value) (SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)) +#define SMC_SETUP_Msk _U_(0x3F3F3F3F) /**< (SMC_SETUP) Register Mask */ + + +/* -------- SMC_PULSE : (SMC Offset: 0x04) (R/W 32) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos _U_(0) /**< (SMC_PULSE) NWE Pulse Length Position */ +#define SMC_PULSE_NWE_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NWE_PULSE_Pos) /**< (SMC_PULSE) NWE Pulse Length Mask */ +#define SMC_PULSE_NWE_PULSE(value) (SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)) +#define SMC_PULSE_NCS_WR_PULSE_Pos _U_(8) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Position */ +#define SMC_PULSE_NCS_WR_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_WR_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Mask */ +#define SMC_PULSE_NCS_WR_PULSE(value) (SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)) +#define SMC_PULSE_NRD_PULSE_Pos _U_(16) /**< (SMC_PULSE) NRD Pulse Length Position */ +#define SMC_PULSE_NRD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NRD_PULSE_Pos) /**< (SMC_PULSE) NRD Pulse Length Mask */ +#define SMC_PULSE_NRD_PULSE(value) (SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)) +#define SMC_PULSE_NCS_RD_PULSE_Pos _U_(24) /**< (SMC_PULSE) NCS Pulse Length in READ Access Position */ +#define SMC_PULSE_NCS_RD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_RD_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in READ Access Mask */ +#define SMC_PULSE_NCS_RD_PULSE(value) (SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)) +#define SMC_PULSE_Msk _U_(0x7F7F7F7F) /**< (SMC_PULSE) Register Mask */ + + +/* -------- SMC_CYCLE : (SMC Offset: 0x08) (R/W 32) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos _U_(0) /**< (SMC_CYCLE) Total Write Cycle Length Position */ +#define SMC_CYCLE_NWE_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NWE_CYCLE_Pos) /**< (SMC_CYCLE) Total Write Cycle Length Mask */ +#define SMC_CYCLE_NWE_CYCLE(value) (SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)) +#define SMC_CYCLE_NRD_CYCLE_Pos _U_(16) /**< (SMC_CYCLE) Total Read Cycle Length Position */ +#define SMC_CYCLE_NRD_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NRD_CYCLE_Pos) /**< (SMC_CYCLE) Total Read Cycle Length Mask */ +#define SMC_CYCLE_NRD_CYCLE(value) (SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)) +#define SMC_CYCLE_Msk _U_(0x01FF01FF) /**< (SMC_CYCLE) Register Mask */ + + +/* -------- SMC_MODE : (SMC Offset: 0x0C) (R/W 32) SMC Mode Register -------- */ +#define SMC_MODE_READ_MODE_Pos _U_(0) /**< (SMC_MODE) Read Mode Position */ +#define SMC_MODE_READ_MODE_Msk (_U_(0x1) << SMC_MODE_READ_MODE_Pos) /**< (SMC_MODE) Read Mode Mask */ +#define SMC_MODE_READ_MODE(value) (SMC_MODE_READ_MODE_Msk & ((value) << SMC_MODE_READ_MODE_Pos)) +#define SMC_MODE_WRITE_MODE_Pos _U_(1) /**< (SMC_MODE) Write Mode Position */ +#define SMC_MODE_WRITE_MODE_Msk (_U_(0x1) << SMC_MODE_WRITE_MODE_Pos) /**< (SMC_MODE) Write Mode Mask */ +#define SMC_MODE_WRITE_MODE(value) (SMC_MODE_WRITE_MODE_Msk & ((value) << SMC_MODE_WRITE_MODE_Pos)) +#define SMC_MODE_EXNW_MODE_Pos _U_(4) /**< (SMC_MODE) NWAIT Mode Position */ +#define SMC_MODE_EXNW_MODE_Msk (_U_(0x3) << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) NWAIT Mode Mask */ +#define SMC_MODE_EXNW_MODE(value) (SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)) +#define SMC_MODE_EXNW_MODE_DISABLED_Val _U_(0x0) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. */ +#define SMC_MODE_EXNW_MODE_FROZEN_Val _U_(0x2) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */ +#define SMC_MODE_EXNW_MODE_READY_Val _U_(0x3) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */ +#define SMC_MODE_EXNW_MODE_DISABLED (SMC_MODE_EXNW_MODE_DISABLED_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. Position */ +#define SMC_MODE_EXNW_MODE_FROZEN (SMC_MODE_EXNW_MODE_FROZEN_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. Position */ +#define SMC_MODE_EXNW_MODE_READY (SMC_MODE_EXNW_MODE_READY_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. Position */ +#define SMC_MODE_BAT_Pos _U_(8) /**< (SMC_MODE) Byte Access Type Position */ +#define SMC_MODE_BAT_Msk (_U_(0x1) << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte Access Type Mask */ +#define SMC_MODE_BAT(value) (SMC_MODE_BAT_Msk & ((value) << SMC_MODE_BAT_Pos)) +#define SMC_MODE_BAT_BYTE_SELECT_Val _U_(0x0) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE_Val _U_(0x1) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_BAT_BYTE_SELECT (SMC_MODE_BAT_BYTE_SELECT_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. Position */ +#define SMC_MODE_BAT_BYTE_WRITE (SMC_MODE_BAT_BYTE_WRITE_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. Position */ +#define SMC_MODE_DBW_Pos _U_(12) /**< (SMC_MODE) Data Bus Width Position */ +#define SMC_MODE_DBW_Msk (_U_(0x1) << SMC_MODE_DBW_Pos) /**< (SMC_MODE) Data Bus Width Mask */ +#define SMC_MODE_DBW(value) (SMC_MODE_DBW_Msk & ((value) << SMC_MODE_DBW_Pos)) +#define SMC_MODE_DBW_8_BIT_Val _U_(0x0) /**< (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT_Val _U_(0x1) /**< (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_DBW_8_BIT (SMC_MODE_DBW_8_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 8-bit Data Bus Position */ +#define SMC_MODE_DBW_16_BIT (SMC_MODE_DBW_16_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 16-bit Data Bus Position */ +#define SMC_MODE_TDF_CYCLES_Pos _U_(16) /**< (SMC_MODE) Data Float Time Position */ +#define SMC_MODE_TDF_CYCLES_Msk (_U_(0xF) << SMC_MODE_TDF_CYCLES_Pos) /**< (SMC_MODE) Data Float Time Mask */ +#define SMC_MODE_TDF_CYCLES(value) (SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)) +#define SMC_MODE_TDF_MODE_Pos _U_(20) /**< (SMC_MODE) TDF Optimization Position */ +#define SMC_MODE_TDF_MODE_Msk (_U_(0x1) << SMC_MODE_TDF_MODE_Pos) /**< (SMC_MODE) TDF Optimization Mask */ +#define SMC_MODE_TDF_MODE(value) (SMC_MODE_TDF_MODE_Msk & ((value) << SMC_MODE_TDF_MODE_Pos)) +#define SMC_MODE_PMEN_Pos _U_(24) /**< (SMC_MODE) Page Mode Enabled Position */ +#define SMC_MODE_PMEN_Msk (_U_(0x1) << SMC_MODE_PMEN_Pos) /**< (SMC_MODE) Page Mode Enabled Mask */ +#define SMC_MODE_PMEN(value) (SMC_MODE_PMEN_Msk & ((value) << SMC_MODE_PMEN_Pos)) +#define SMC_MODE_PS_Pos _U_(28) /**< (SMC_MODE) Page Size Position */ +#define SMC_MODE_PS_Msk (_U_(0x3) << SMC_MODE_PS_Pos) /**< (SMC_MODE) Page Size Mask */ +#define SMC_MODE_PS(value) (SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)) +#define SMC_MODE_PS_4_BYTE_Val _U_(0x0) /**< (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE_Val _U_(0x1) /**< (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE_Val _U_(0x2) /**< (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE_Val _U_(0x3) /**< (SMC_MODE) 32-byte page */ +#define SMC_MODE_PS_4_BYTE (SMC_MODE_PS_4_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 4-byte page Position */ +#define SMC_MODE_PS_8_BYTE (SMC_MODE_PS_8_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 8-byte page Position */ +#define SMC_MODE_PS_16_BYTE (SMC_MODE_PS_16_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 16-byte page Position */ +#define SMC_MODE_PS_32_BYTE (SMC_MODE_PS_32_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 32-byte page Position */ +#define SMC_MODE_Msk _U_(0x311F1133) /**< (SMC_MODE) Register Mask */ + + +/* -------- SMC_OCMS : (SMC Offset: 0x80) (R/W 32) SMC Off-Chip Memory Scrambling Register -------- */ +#define SMC_OCMS_SMSE_Pos _U_(0) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Position */ +#define SMC_OCMS_SMSE_Msk (_U_(0x1) << SMC_OCMS_SMSE_Pos) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Mask */ +#define SMC_OCMS_SMSE(value) (SMC_OCMS_SMSE_Msk & ((value) << SMC_OCMS_SMSE_Pos)) +#define SMC_OCMS_CS0SE_Pos _U_(8) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS0SE_Msk (_U_(0x1) << SMC_OCMS_CS0SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS0SE(value) (SMC_OCMS_CS0SE_Msk & ((value) << SMC_OCMS_CS0SE_Pos)) +#define SMC_OCMS_CS1SE_Pos _U_(9) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS1SE_Msk (_U_(0x1) << SMC_OCMS_CS1SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS1SE(value) (SMC_OCMS_CS1SE_Msk & ((value) << SMC_OCMS_CS1SE_Pos)) +#define SMC_OCMS_CS2SE_Pos _U_(10) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS2SE_Msk (_U_(0x1) << SMC_OCMS_CS2SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS2SE(value) (SMC_OCMS_CS2SE_Msk & ((value) << SMC_OCMS_CS2SE_Pos)) +#define SMC_OCMS_CS3SE_Pos _U_(11) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ +#define SMC_OCMS_CS3SE_Msk (_U_(0x1) << SMC_OCMS_CS3SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ +#define SMC_OCMS_CS3SE(value) (SMC_OCMS_CS3SE_Msk & ((value) << SMC_OCMS_CS3SE_Pos)) +#define SMC_OCMS_Msk _U_(0x00000F01) /**< (SMC_OCMS) Register Mask */ + + +/* -------- SMC_KEY1 : (SMC Offset: 0x84) ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos _U_(0) /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Position */ +#define SMC_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SMC_KEY1_KEY1_Pos) /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Mask */ +#define SMC_KEY1_KEY1(value) (SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)) +#define SMC_KEY1_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY1) Register Mask */ + + +/* -------- SMC_KEY2 : (SMC Offset: 0x88) ( /W 32) SMC Off-Chip Memory Scrambling KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos _U_(0) /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Position */ +#define SMC_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SMC_KEY2_KEY2_Pos) /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Mask */ +#define SMC_KEY2_KEY2(value) (SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)) +#define SMC_KEY2_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY2) Register Mask */ + + +/* -------- SMC_WPMR : (SMC Offset: 0xE4) (R/W 32) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN_Pos _U_(0) /**< (SMC_WPMR) Write Protect Enable Position */ +#define SMC_WPMR_WPEN_Msk (_U_(0x1) << SMC_WPMR_WPEN_Pos) /**< (SMC_WPMR) Write Protect Enable Mask */ +#define SMC_WPMR_WPEN(value) (SMC_WPMR_WPEN_Msk & ((value) << SMC_WPMR_WPEN_Pos)) +#define SMC_WPMR_WPKEY_Pos _U_(8) /**< (SMC_WPMR) Write Protection Key Position */ +#define SMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Write Protection Key Mask */ +#define SMC_WPMR_WPKEY(value) (SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)) +#define SMC_WPMR_WPKEY_PASSWD_Val _U_(0x534D43) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define SMC_WPMR_WPKEY_PASSWD (SMC_WPMR_WPKEY_PASSWD_Val << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define SMC_WPMR_Msk _U_(0xFFFFFF01) /**< (SMC_WPMR) Register Mask */ + + +/* -------- SMC_WPSR : (SMC Offset: 0xE8) ( R/ 32) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS_Pos _U_(0) /**< (SMC_WPSR) Write Protection Violation Status Position */ +#define SMC_WPSR_WPVS_Msk (_U_(0x1) << SMC_WPSR_WPVS_Pos) /**< (SMC_WPSR) Write Protection Violation Status Mask */ +#define SMC_WPSR_WPVS(value) (SMC_WPSR_WPVS_Msk & ((value) << SMC_WPSR_WPVS_Pos)) +#define SMC_WPSR_WPVSRC_Pos _U_(8) /**< (SMC_WPSR) Write Protection Violation Source Position */ +#define SMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SMC_WPSR_WPVSRC_Pos) /**< (SMC_WPSR) Write Protection Violation Source Mask */ +#define SMC_WPSR_WPVSRC(value) (SMC_WPSR_WPVSRC_Msk & ((value) << SMC_WPSR_WPVSRC_Pos)) +#define SMC_WPSR_Msk _U_(0x00FFFF01) /**< (SMC_WPSR) Register Mask */ + + +/** \brief SMC register offsets definitions */ +#define SMC_SETUP_REG_OFST (0x00) /**< (SMC_SETUP) SMC Setup Register Offset */ +#define SMC_PULSE_REG_OFST (0x04) /**< (SMC_PULSE) SMC Pulse Register Offset */ +#define SMC_CYCLE_REG_OFST (0x08) /**< (SMC_CYCLE) SMC Cycle Register Offset */ +#define SMC_MODE_REG_OFST (0x0C) /**< (SMC_MODE) SMC Mode Register Offset */ +#define SMC_OCMS_REG_OFST (0x80) /**< (SMC_OCMS) SMC Off-Chip Memory Scrambling Register Offset */ +#define SMC_KEY1_REG_OFST (0x84) /**< (SMC_KEY1) SMC Off-Chip Memory Scrambling KEY1 Register Offset */ +#define SMC_KEY2_REG_OFST (0x88) /**< (SMC_KEY2) SMC Off-Chip Memory Scrambling KEY2 Register Offset */ +#define SMC_WPMR_REG_OFST (0xE4) /**< (SMC_WPMR) SMC Write Protection Mode Register Offset */ +#define SMC_WPSR_REG_OFST (0xE8) /**< (SMC_WPSR) SMC Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SMC_CS_NUMBER register API structure */ +typedef struct +{ + __IO uint32_t SMC_SETUP; /**< Offset: 0x00 (R/W 32) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register */ +} smc_cs_number_registers_t; + +#define SMC_CS_NUMBER_NUMBER _U_(4) + +/** \brief SMC register API structure */ +typedef struct +{ + smc_cs_number_registers_t SMC_CS_NUMBER[SMC_CS_NUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register */ + __I uint8_t Reserved1[0x40]; + __IO uint32_t SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */ + __O uint32_t SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */ + __O uint32_t SMC_KEY2; /**< Offset: 0x88 ( /W 32) SMC Off-Chip Memory Scrambling KEY2 Register */ + __I uint8_t Reserved2[0x58]; + __IO uint32_t SMC_WPMR; /**< Offset: 0xE4 (R/W 32) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< Offset: 0xE8 (R/ 32) SMC Write Protection Status Register */ +} smc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SMC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/spi.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/spi.h new file mode 100644 index 00000000..549145be --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/spi.h @@ -0,0 +1,334 @@ +/** + * \brief Component description for SPI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_SPI_COMPONENT_H_ +#define _SAME70_SPI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SPI */ +/* ************************************************************************** */ + +/* -------- SPI_CR : (SPI Offset: 0x00) ( /W 32) Control Register -------- */ +#define SPI_CR_SPIEN_Pos _U_(0) /**< (SPI_CR) SPI Enable Position */ +#define SPI_CR_SPIEN_Msk (_U_(0x1) << SPI_CR_SPIEN_Pos) /**< (SPI_CR) SPI Enable Mask */ +#define SPI_CR_SPIEN(value) (SPI_CR_SPIEN_Msk & ((value) << SPI_CR_SPIEN_Pos)) +#define SPI_CR_SPIDIS_Pos _U_(1) /**< (SPI_CR) SPI Disable Position */ +#define SPI_CR_SPIDIS_Msk (_U_(0x1) << SPI_CR_SPIDIS_Pos) /**< (SPI_CR) SPI Disable Mask */ +#define SPI_CR_SPIDIS(value) (SPI_CR_SPIDIS_Msk & ((value) << SPI_CR_SPIDIS_Pos)) +#define SPI_CR_SWRST_Pos _U_(7) /**< (SPI_CR) SPI Software Reset Position */ +#define SPI_CR_SWRST_Msk (_U_(0x1) << SPI_CR_SWRST_Pos) /**< (SPI_CR) SPI Software Reset Mask */ +#define SPI_CR_SWRST(value) (SPI_CR_SWRST_Msk & ((value) << SPI_CR_SWRST_Pos)) +#define SPI_CR_REQCLR_Pos _U_(12) /**< (SPI_CR) Request to Clear the Comparison Trigger Position */ +#define SPI_CR_REQCLR_Msk (_U_(0x1) << SPI_CR_REQCLR_Pos) /**< (SPI_CR) Request to Clear the Comparison Trigger Mask */ +#define SPI_CR_REQCLR(value) (SPI_CR_REQCLR_Msk & ((value) << SPI_CR_REQCLR_Pos)) +#define SPI_CR_LASTXFER_Pos _U_(24) /**< (SPI_CR) Last Transfer Position */ +#define SPI_CR_LASTXFER_Msk (_U_(0x1) << SPI_CR_LASTXFER_Pos) /**< (SPI_CR) Last Transfer Mask */ +#define SPI_CR_LASTXFER(value) (SPI_CR_LASTXFER_Msk & ((value) << SPI_CR_LASTXFER_Pos)) +#define SPI_CR_Msk _U_(0x01001083) /**< (SPI_CR) Register Mask */ + + +/* -------- SPI_MR : (SPI Offset: 0x04) (R/W 32) Mode Register -------- */ +#define SPI_MR_MSTR_Pos _U_(0) /**< (SPI_MR) Master/Slave Mode Position */ +#define SPI_MR_MSTR_Msk (_U_(0x1) << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master/Slave Mode Mask */ +#define SPI_MR_MSTR(value) (SPI_MR_MSTR_Msk & ((value) << SPI_MR_MSTR_Pos)) +#define SPI_MR_MSTR_MASTER_Val _U_(0x1) /**< (SPI_MR) Master */ +#define SPI_MR_MSTR_SLAVE_Val _U_(0x0) /**< (SPI_MR) Slave */ +#define SPI_MR_MSTR_MASTER (SPI_MR_MSTR_MASTER_Val << SPI_MR_MSTR_Pos) /**< (SPI_MR) Master Position */ +#define SPI_MR_MSTR_SLAVE (SPI_MR_MSTR_SLAVE_Val << SPI_MR_MSTR_Pos) /**< (SPI_MR) Slave Position */ +#define SPI_MR_PS_Pos _U_(1) /**< (SPI_MR) Peripheral Select Position */ +#define SPI_MR_PS_Msk (_U_(0x1) << SPI_MR_PS_Pos) /**< (SPI_MR) Peripheral Select Mask */ +#define SPI_MR_PS(value) (SPI_MR_PS_Msk & ((value) << SPI_MR_PS_Pos)) +#define SPI_MR_PCSDEC_Pos _U_(2) /**< (SPI_MR) Chip Select Decode Position */ +#define SPI_MR_PCSDEC_Msk (_U_(0x1) << SPI_MR_PCSDEC_Pos) /**< (SPI_MR) Chip Select Decode Mask */ +#define SPI_MR_PCSDEC(value) (SPI_MR_PCSDEC_Msk & ((value) << SPI_MR_PCSDEC_Pos)) +#define SPI_MR_MODFDIS_Pos _U_(4) /**< (SPI_MR) Mode Fault Detection Position */ +#define SPI_MR_MODFDIS_Msk (_U_(0x1) << SPI_MR_MODFDIS_Pos) /**< (SPI_MR) Mode Fault Detection Mask */ +#define SPI_MR_MODFDIS(value) (SPI_MR_MODFDIS_Msk & ((value) << SPI_MR_MODFDIS_Pos)) +#define SPI_MR_WDRBT_Pos _U_(5) /**< (SPI_MR) Wait Data Read Before Transfer Position */ +#define SPI_MR_WDRBT_Msk (_U_(0x1) << SPI_MR_WDRBT_Pos) /**< (SPI_MR) Wait Data Read Before Transfer Mask */ +#define SPI_MR_WDRBT(value) (SPI_MR_WDRBT_Msk & ((value) << SPI_MR_WDRBT_Pos)) +#define SPI_MR_LLB_Pos _U_(7) /**< (SPI_MR) Local Loopback Enable Position */ +#define SPI_MR_LLB_Msk (_U_(0x1) << SPI_MR_LLB_Pos) /**< (SPI_MR) Local Loopback Enable Mask */ +#define SPI_MR_LLB(value) (SPI_MR_LLB_Msk & ((value) << SPI_MR_LLB_Pos)) +#define SPI_MR_PCS_Pos _U_(16) /**< (SPI_MR) Peripheral Chip Select Position */ +#define SPI_MR_PCS_Msk (_U_(0xF) << SPI_MR_PCS_Pos) /**< (SPI_MR) Peripheral Chip Select Mask */ +#define SPI_MR_PCS(value) (SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)) +#define SPI_MR_PCS_NPCS0_Val _U_(0xE) /**< (SPI_MR) NPCS0 as Chip Select */ +#define SPI_MR_PCS_NPCS1_Val _U_(0xD) /**< (SPI_MR) NPCS1 as Chip Select */ +#define SPI_MR_PCS_NPCS2_Val _U_(0xB) /**< (SPI_MR) NPCS2 as Chip Select */ +#define SPI_MR_PCS_NPCS3_Val _U_(0x7) /**< (SPI_MR) NPCS3 as Chip Select */ +#define SPI_MR_PCS_NPCS0 (SPI_MR_PCS_NPCS0_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS0 as Chip Select Position */ +#define SPI_MR_PCS_NPCS1 (SPI_MR_PCS_NPCS1_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS1 as Chip Select Position */ +#define SPI_MR_PCS_NPCS2 (SPI_MR_PCS_NPCS2_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS2 as Chip Select Position */ +#define SPI_MR_PCS_NPCS3 (SPI_MR_PCS_NPCS3_Val << SPI_MR_PCS_Pos) /**< (SPI_MR) NPCS3 as Chip Select Position */ +#define SPI_MR_DLYBCS_Pos _U_(24) /**< (SPI_MR) Delay Between Chip Selects Position */ +#define SPI_MR_DLYBCS_Msk (_U_(0xFF) << SPI_MR_DLYBCS_Pos) /**< (SPI_MR) Delay Between Chip Selects Mask */ +#define SPI_MR_DLYBCS(value) (SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)) +#define SPI_MR_Msk _U_(0xFF0F00B7) /**< (SPI_MR) Register Mask */ + + +/* -------- SPI_RDR : (SPI Offset: 0x08) ( R/ 32) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos _U_(0) /**< (SPI_RDR) Receive Data Position */ +#define SPI_RDR_RD_Msk (_U_(0xFFFF) << SPI_RDR_RD_Pos) /**< (SPI_RDR) Receive Data Mask */ +#define SPI_RDR_RD(value) (SPI_RDR_RD_Msk & ((value) << SPI_RDR_RD_Pos)) +#define SPI_RDR_PCS_Pos _U_(16) /**< (SPI_RDR) Peripheral Chip Select Position */ +#define SPI_RDR_PCS_Msk (_U_(0xF) << SPI_RDR_PCS_Pos) /**< (SPI_RDR) Peripheral Chip Select Mask */ +#define SPI_RDR_PCS(value) (SPI_RDR_PCS_Msk & ((value) << SPI_RDR_PCS_Pos)) +#define SPI_RDR_Msk _U_(0x000FFFFF) /**< (SPI_RDR) Register Mask */ + + +/* -------- SPI_TDR : (SPI Offset: 0x0C) ( /W 32) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos _U_(0) /**< (SPI_TDR) Transmit Data Position */ +#define SPI_TDR_TD_Msk (_U_(0xFFFF) << SPI_TDR_TD_Pos) /**< (SPI_TDR) Transmit Data Mask */ +#define SPI_TDR_TD(value) (SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)) +#define SPI_TDR_PCS_Pos _U_(16) /**< (SPI_TDR) Peripheral Chip Select Position */ +#define SPI_TDR_PCS_Msk (_U_(0xF) << SPI_TDR_PCS_Pos) /**< (SPI_TDR) Peripheral Chip Select Mask */ +#define SPI_TDR_PCS(value) (SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)) +#define SPI_TDR_PCS_NPCS0_Val _U_(0xE) /**< (SPI_TDR) NPCS0 as Chip Select */ +#define SPI_TDR_PCS_NPCS1_Val _U_(0xD) /**< (SPI_TDR) NPCS1 as Chip Select */ +#define SPI_TDR_PCS_NPCS2_Val _U_(0xB) /**< (SPI_TDR) NPCS2 as Chip Select */ +#define SPI_TDR_PCS_NPCS3_Val _U_(0x7) /**< (SPI_TDR) NPCS3 as Chip Select */ +#define SPI_TDR_PCS_NPCS0 (SPI_TDR_PCS_NPCS0_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS0 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS1 (SPI_TDR_PCS_NPCS1_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS1 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS2 (SPI_TDR_PCS_NPCS2_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS2 as Chip Select Position */ +#define SPI_TDR_PCS_NPCS3 (SPI_TDR_PCS_NPCS3_Val << SPI_TDR_PCS_Pos) /**< (SPI_TDR) NPCS3 as Chip Select Position */ +#define SPI_TDR_LASTXFER_Pos _U_(24) /**< (SPI_TDR) Last Transfer Position */ +#define SPI_TDR_LASTXFER_Msk (_U_(0x1) << SPI_TDR_LASTXFER_Pos) /**< (SPI_TDR) Last Transfer Mask */ +#define SPI_TDR_LASTXFER(value) (SPI_TDR_LASTXFER_Msk & ((value) << SPI_TDR_LASTXFER_Pos)) +#define SPI_TDR_Msk _U_(0x010FFFFF) /**< (SPI_TDR) Register Mask */ + + +/* -------- SPI_SR : (SPI Offset: 0x10) ( R/ 32) Status Register -------- */ +#define SPI_SR_RDRF_Pos _U_(0) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Position */ +#define SPI_SR_RDRF_Msk (_U_(0x1) << SPI_SR_RDRF_Pos) /**< (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) Mask */ +#define SPI_SR_RDRF(value) (SPI_SR_RDRF_Msk & ((value) << SPI_SR_RDRF_Pos)) +#define SPI_SR_TDRE_Pos _U_(1) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TDRE_Msk (_U_(0x1) << SPI_SR_TDRE_Pos) /**< (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TDRE(value) (SPI_SR_TDRE_Msk & ((value) << SPI_SR_TDRE_Pos)) +#define SPI_SR_MODF_Pos _U_(2) /**< (SPI_SR) Mode Fault Error (cleared on read) Position */ +#define SPI_SR_MODF_Msk (_U_(0x1) << SPI_SR_MODF_Pos) /**< (SPI_SR) Mode Fault Error (cleared on read) Mask */ +#define SPI_SR_MODF(value) (SPI_SR_MODF_Msk & ((value) << SPI_SR_MODF_Pos)) +#define SPI_SR_OVRES_Pos _U_(3) /**< (SPI_SR) Overrun Error Status (cleared on read) Position */ +#define SPI_SR_OVRES_Msk (_U_(0x1) << SPI_SR_OVRES_Pos) /**< (SPI_SR) Overrun Error Status (cleared on read) Mask */ +#define SPI_SR_OVRES(value) (SPI_SR_OVRES_Msk & ((value) << SPI_SR_OVRES_Pos)) +#define SPI_SR_NSSR_Pos _U_(8) /**< (SPI_SR) NSS Rising (cleared on read) Position */ +#define SPI_SR_NSSR_Msk (_U_(0x1) << SPI_SR_NSSR_Pos) /**< (SPI_SR) NSS Rising (cleared on read) Mask */ +#define SPI_SR_NSSR(value) (SPI_SR_NSSR_Msk & ((value) << SPI_SR_NSSR_Pos)) +#define SPI_SR_TXEMPTY_Pos _U_(9) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Position */ +#define SPI_SR_TXEMPTY_Msk (_U_(0x1) << SPI_SR_TXEMPTY_Pos) /**< (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) Mask */ +#define SPI_SR_TXEMPTY(value) (SPI_SR_TXEMPTY_Msk & ((value) << SPI_SR_TXEMPTY_Pos)) +#define SPI_SR_UNDES_Pos _U_(10) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Position */ +#define SPI_SR_UNDES_Msk (_U_(0x1) << SPI_SR_UNDES_Pos) /**< (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) Mask */ +#define SPI_SR_UNDES(value) (SPI_SR_UNDES_Msk & ((value) << SPI_SR_UNDES_Pos)) +#define SPI_SR_SPIENS_Pos _U_(16) /**< (SPI_SR) SPI Enable Status Position */ +#define SPI_SR_SPIENS_Msk (_U_(0x1) << SPI_SR_SPIENS_Pos) /**< (SPI_SR) SPI Enable Status Mask */ +#define SPI_SR_SPIENS(value) (SPI_SR_SPIENS_Msk & ((value) << SPI_SR_SPIENS_Pos)) +#define SPI_SR_Msk _U_(0x0001070F) /**< (SPI_SR) Register Mask */ + + +/* -------- SPI_IER : (SPI Offset: 0x14) ( /W 32) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF_Pos _U_(0) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Position */ +#define SPI_IER_RDRF_Msk (_U_(0x1) << SPI_IER_RDRF_Pos) /**< (SPI_IER) Receive Data Register Full Interrupt Enable Mask */ +#define SPI_IER_RDRF(value) (SPI_IER_RDRF_Msk & ((value) << SPI_IER_RDRF_Pos)) +#define SPI_IER_TDRE_Pos _U_(1) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Position */ +#define SPI_IER_TDRE_Msk (_U_(0x1) << SPI_IER_TDRE_Pos) /**< (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable Mask */ +#define SPI_IER_TDRE(value) (SPI_IER_TDRE_Msk & ((value) << SPI_IER_TDRE_Pos)) +#define SPI_IER_MODF_Pos _U_(2) /**< (SPI_IER) Mode Fault Error Interrupt Enable Position */ +#define SPI_IER_MODF_Msk (_U_(0x1) << SPI_IER_MODF_Pos) /**< (SPI_IER) Mode Fault Error Interrupt Enable Mask */ +#define SPI_IER_MODF(value) (SPI_IER_MODF_Msk & ((value) << SPI_IER_MODF_Pos)) +#define SPI_IER_OVRES_Pos _U_(3) /**< (SPI_IER) Overrun Error Interrupt Enable Position */ +#define SPI_IER_OVRES_Msk (_U_(0x1) << SPI_IER_OVRES_Pos) /**< (SPI_IER) Overrun Error Interrupt Enable Mask */ +#define SPI_IER_OVRES(value) (SPI_IER_OVRES_Msk & ((value) << SPI_IER_OVRES_Pos)) +#define SPI_IER_NSSR_Pos _U_(8) /**< (SPI_IER) NSS Rising Interrupt Enable Position */ +#define SPI_IER_NSSR_Msk (_U_(0x1) << SPI_IER_NSSR_Pos) /**< (SPI_IER) NSS Rising Interrupt Enable Mask */ +#define SPI_IER_NSSR(value) (SPI_IER_NSSR_Msk & ((value) << SPI_IER_NSSR_Pos)) +#define SPI_IER_TXEMPTY_Pos _U_(9) /**< (SPI_IER) Transmission Registers Empty Enable Position */ +#define SPI_IER_TXEMPTY_Msk (_U_(0x1) << SPI_IER_TXEMPTY_Pos) /**< (SPI_IER) Transmission Registers Empty Enable Mask */ +#define SPI_IER_TXEMPTY(value) (SPI_IER_TXEMPTY_Msk & ((value) << SPI_IER_TXEMPTY_Pos)) +#define SPI_IER_UNDES_Pos _U_(10) /**< (SPI_IER) Underrun Error Interrupt Enable Position */ +#define SPI_IER_UNDES_Msk (_U_(0x1) << SPI_IER_UNDES_Pos) /**< (SPI_IER) Underrun Error Interrupt Enable Mask */ +#define SPI_IER_UNDES(value) (SPI_IER_UNDES_Msk & ((value) << SPI_IER_UNDES_Pos)) +#define SPI_IER_Msk _U_(0x0000070F) /**< (SPI_IER) Register Mask */ + + +/* -------- SPI_IDR : (SPI Offset: 0x18) ( /W 32) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF_Pos _U_(0) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Position */ +#define SPI_IDR_RDRF_Msk (_U_(0x1) << SPI_IDR_RDRF_Pos) /**< (SPI_IDR) Receive Data Register Full Interrupt Disable Mask */ +#define SPI_IDR_RDRF(value) (SPI_IDR_RDRF_Msk & ((value) << SPI_IDR_RDRF_Pos)) +#define SPI_IDR_TDRE_Pos _U_(1) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Position */ +#define SPI_IDR_TDRE_Msk (_U_(0x1) << SPI_IDR_TDRE_Pos) /**< (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable Mask */ +#define SPI_IDR_TDRE(value) (SPI_IDR_TDRE_Msk & ((value) << SPI_IDR_TDRE_Pos)) +#define SPI_IDR_MODF_Pos _U_(2) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Position */ +#define SPI_IDR_MODF_Msk (_U_(0x1) << SPI_IDR_MODF_Pos) /**< (SPI_IDR) Mode Fault Error Interrupt Disable Mask */ +#define SPI_IDR_MODF(value) (SPI_IDR_MODF_Msk & ((value) << SPI_IDR_MODF_Pos)) +#define SPI_IDR_OVRES_Pos _U_(3) /**< (SPI_IDR) Overrun Error Interrupt Disable Position */ +#define SPI_IDR_OVRES_Msk (_U_(0x1) << SPI_IDR_OVRES_Pos) /**< (SPI_IDR) Overrun Error Interrupt Disable Mask */ +#define SPI_IDR_OVRES(value) (SPI_IDR_OVRES_Msk & ((value) << SPI_IDR_OVRES_Pos)) +#define SPI_IDR_NSSR_Pos _U_(8) /**< (SPI_IDR) NSS Rising Interrupt Disable Position */ +#define SPI_IDR_NSSR_Msk (_U_(0x1) << SPI_IDR_NSSR_Pos) /**< (SPI_IDR) NSS Rising Interrupt Disable Mask */ +#define SPI_IDR_NSSR(value) (SPI_IDR_NSSR_Msk & ((value) << SPI_IDR_NSSR_Pos)) +#define SPI_IDR_TXEMPTY_Pos _U_(9) /**< (SPI_IDR) Transmission Registers Empty Disable Position */ +#define SPI_IDR_TXEMPTY_Msk (_U_(0x1) << SPI_IDR_TXEMPTY_Pos) /**< (SPI_IDR) Transmission Registers Empty Disable Mask */ +#define SPI_IDR_TXEMPTY(value) (SPI_IDR_TXEMPTY_Msk & ((value) << SPI_IDR_TXEMPTY_Pos)) +#define SPI_IDR_UNDES_Pos _U_(10) /**< (SPI_IDR) Underrun Error Interrupt Disable Position */ +#define SPI_IDR_UNDES_Msk (_U_(0x1) << SPI_IDR_UNDES_Pos) /**< (SPI_IDR) Underrun Error Interrupt Disable Mask */ +#define SPI_IDR_UNDES(value) (SPI_IDR_UNDES_Msk & ((value) << SPI_IDR_UNDES_Pos)) +#define SPI_IDR_Msk _U_(0x0000070F) /**< (SPI_IDR) Register Mask */ + + +/* -------- SPI_IMR : (SPI Offset: 0x1C) ( R/ 32) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF_Pos _U_(0) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Position */ +#define SPI_IMR_RDRF_Msk (_U_(0x1) << SPI_IMR_RDRF_Pos) /**< (SPI_IMR) Receive Data Register Full Interrupt Mask Mask */ +#define SPI_IMR_RDRF(value) (SPI_IMR_RDRF_Msk & ((value) << SPI_IMR_RDRF_Pos)) +#define SPI_IMR_TDRE_Pos _U_(1) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Position */ +#define SPI_IMR_TDRE_Msk (_U_(0x1) << SPI_IMR_TDRE_Pos) /**< (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask Mask */ +#define SPI_IMR_TDRE(value) (SPI_IMR_TDRE_Msk & ((value) << SPI_IMR_TDRE_Pos)) +#define SPI_IMR_MODF_Pos _U_(2) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Position */ +#define SPI_IMR_MODF_Msk (_U_(0x1) << SPI_IMR_MODF_Pos) /**< (SPI_IMR) Mode Fault Error Interrupt Mask Mask */ +#define SPI_IMR_MODF(value) (SPI_IMR_MODF_Msk & ((value) << SPI_IMR_MODF_Pos)) +#define SPI_IMR_OVRES_Pos _U_(3) /**< (SPI_IMR) Overrun Error Interrupt Mask Position */ +#define SPI_IMR_OVRES_Msk (_U_(0x1) << SPI_IMR_OVRES_Pos) /**< (SPI_IMR) Overrun Error Interrupt Mask Mask */ +#define SPI_IMR_OVRES(value) (SPI_IMR_OVRES_Msk & ((value) << SPI_IMR_OVRES_Pos)) +#define SPI_IMR_NSSR_Pos _U_(8) /**< (SPI_IMR) NSS Rising Interrupt Mask Position */ +#define SPI_IMR_NSSR_Msk (_U_(0x1) << SPI_IMR_NSSR_Pos) /**< (SPI_IMR) NSS Rising Interrupt Mask Mask */ +#define SPI_IMR_NSSR(value) (SPI_IMR_NSSR_Msk & ((value) << SPI_IMR_NSSR_Pos)) +#define SPI_IMR_TXEMPTY_Pos _U_(9) /**< (SPI_IMR) Transmission Registers Empty Mask Position */ +#define SPI_IMR_TXEMPTY_Msk (_U_(0x1) << SPI_IMR_TXEMPTY_Pos) /**< (SPI_IMR) Transmission Registers Empty Mask Mask */ +#define SPI_IMR_TXEMPTY(value) (SPI_IMR_TXEMPTY_Msk & ((value) << SPI_IMR_TXEMPTY_Pos)) +#define SPI_IMR_UNDES_Pos _U_(10) /**< (SPI_IMR) Underrun Error Interrupt Mask Position */ +#define SPI_IMR_UNDES_Msk (_U_(0x1) << SPI_IMR_UNDES_Pos) /**< (SPI_IMR) Underrun Error Interrupt Mask Mask */ +#define SPI_IMR_UNDES(value) (SPI_IMR_UNDES_Msk & ((value) << SPI_IMR_UNDES_Pos)) +#define SPI_IMR_Msk _U_(0x0000070F) /**< (SPI_IMR) Register Mask */ + + +/* -------- SPI_CSR : (SPI Offset: 0x30) (R/W 32) Chip Select Register -------- */ +#define SPI_CSR_CPOL_Pos _U_(0) /**< (SPI_CSR) Clock Polarity Position */ +#define SPI_CSR_CPOL_Msk (_U_(0x1) << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock Polarity Mask */ +#define SPI_CSR_CPOL(value) (SPI_CSR_CPOL_Msk & ((value) << SPI_CSR_CPOL_Pos)) +#define SPI_CSR_CPOL_IDLE_LOW_Val _U_(0x0) /**< (SPI_CSR) Clock is low when inactive (CPOL=0) */ +#define SPI_CSR_CPOL_IDLE_HIGH_Val _U_(0x1) /**< (SPI_CSR) Clock is high when inactive (CPOL=1) */ +#define SPI_CSR_CPOL_IDLE_LOW (SPI_CSR_CPOL_IDLE_LOW_Val << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock is low when inactive (CPOL=0) Position */ +#define SPI_CSR_CPOL_IDLE_HIGH (SPI_CSR_CPOL_IDLE_HIGH_Val << SPI_CSR_CPOL_Pos) /**< (SPI_CSR) Clock is high when inactive (CPOL=1) Position */ +#define SPI_CSR_NCPHA_Pos _U_(1) /**< (SPI_CSR) Clock Phase Position */ +#define SPI_CSR_NCPHA_Msk (_U_(0x1) << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Clock Phase Mask */ +#define SPI_CSR_NCPHA(value) (SPI_CSR_NCPHA_Msk & ((value) << SPI_CSR_NCPHA_Pos)) +#define SPI_CSR_NCPHA_VALID_LEADING_EDGE_Val _U_(0x1) /**< (SPI_CSR) Data is valid on clock leading edge (CPHA=0) */ +#define SPI_CSR_NCPHA_VALID_TRAILING_EDGE_Val _U_(0x0) /**< (SPI_CSR) Data is valid on clock trailing edge (CPHA=1) */ +#define SPI_CSR_NCPHA_VALID_LEADING_EDGE (SPI_CSR_NCPHA_VALID_LEADING_EDGE_Val << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Data is valid on clock leading edge (CPHA=0) Position */ +#define SPI_CSR_NCPHA_VALID_TRAILING_EDGE (SPI_CSR_NCPHA_VALID_TRAILING_EDGE_Val << SPI_CSR_NCPHA_Pos) /**< (SPI_CSR) Data is valid on clock trailing edge (CPHA=1) Position */ +#define SPI_CSR_CSNAAT_Pos _U_(2) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Position */ +#define SPI_CSR_CSNAAT_Msk (_U_(0x1) << SPI_CSR_CSNAAT_Pos) /**< (SPI_CSR) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) Mask */ +#define SPI_CSR_CSNAAT(value) (SPI_CSR_CSNAAT_Msk & ((value) << SPI_CSR_CSNAAT_Pos)) +#define SPI_CSR_CSAAT_Pos _U_(3) /**< (SPI_CSR) Chip Select Active After Transfer Position */ +#define SPI_CSR_CSAAT_Msk (_U_(0x1) << SPI_CSR_CSAAT_Pos) /**< (SPI_CSR) Chip Select Active After Transfer Mask */ +#define SPI_CSR_CSAAT(value) (SPI_CSR_CSAAT_Msk & ((value) << SPI_CSR_CSAAT_Pos)) +#define SPI_CSR_BITS_Pos _U_(4) /**< (SPI_CSR) Bits Per Transfer Position */ +#define SPI_CSR_BITS_Msk (_U_(0xF) << SPI_CSR_BITS_Pos) /**< (SPI_CSR) Bits Per Transfer Mask */ +#define SPI_CSR_BITS(value) (SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)) +#define SPI_CSR_BITS_8_BIT_Val _U_(0x0) /**< (SPI_CSR) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT_Val _U_(0x1) /**< (SPI_CSR) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT_Val _U_(0x2) /**< (SPI_CSR) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT_Val _U_(0x3) /**< (SPI_CSR) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT_Val _U_(0x4) /**< (SPI_CSR) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT_Val _U_(0x5) /**< (SPI_CSR) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT_Val _U_(0x6) /**< (SPI_CSR) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT_Val _U_(0x7) /**< (SPI_CSR) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT_Val _U_(0x8) /**< (SPI_CSR) 16 bits for transfer */ +#define SPI_CSR_BITS_8_BIT (SPI_CSR_BITS_8_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 8 bits for transfer Position */ +#define SPI_CSR_BITS_9_BIT (SPI_CSR_BITS_9_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 9 bits for transfer Position */ +#define SPI_CSR_BITS_10_BIT (SPI_CSR_BITS_10_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 10 bits for transfer Position */ +#define SPI_CSR_BITS_11_BIT (SPI_CSR_BITS_11_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 11 bits for transfer Position */ +#define SPI_CSR_BITS_12_BIT (SPI_CSR_BITS_12_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 12 bits for transfer Position */ +#define SPI_CSR_BITS_13_BIT (SPI_CSR_BITS_13_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 13 bits for transfer Position */ +#define SPI_CSR_BITS_14_BIT (SPI_CSR_BITS_14_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 14 bits for transfer Position */ +#define SPI_CSR_BITS_15_BIT (SPI_CSR_BITS_15_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 15 bits for transfer Position */ +#define SPI_CSR_BITS_16_BIT (SPI_CSR_BITS_16_BIT_Val << SPI_CSR_BITS_Pos) /**< (SPI_CSR) 16 bits for transfer Position */ +#define SPI_CSR_SCBR_Pos _U_(8) /**< (SPI_CSR) Serial Clock Bit Rate Position */ +#define SPI_CSR_SCBR_Msk (_U_(0xFF) << SPI_CSR_SCBR_Pos) /**< (SPI_CSR) Serial Clock Bit Rate Mask */ +#define SPI_CSR_SCBR(value) (SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)) +#define SPI_CSR_DLYBS_Pos _U_(16) /**< (SPI_CSR) Delay Before SPCK Position */ +#define SPI_CSR_DLYBS_Msk (_U_(0xFF) << SPI_CSR_DLYBS_Pos) /**< (SPI_CSR) Delay Before SPCK Mask */ +#define SPI_CSR_DLYBS(value) (SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)) +#define SPI_CSR_DLYBCT_Pos _U_(24) /**< (SPI_CSR) Delay Between Consecutive Transfers Position */ +#define SPI_CSR_DLYBCT_Msk (_U_(0xFF) << SPI_CSR_DLYBCT_Pos) /**< (SPI_CSR) Delay Between Consecutive Transfers Mask */ +#define SPI_CSR_DLYBCT(value) (SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)) +#define SPI_CSR_Msk _U_(0xFFFFFFFF) /**< (SPI_CSR) Register Mask */ + + +/* -------- SPI_WPMR : (SPI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN_Pos _U_(0) /**< (SPI_WPMR) Write Protection Enable Position */ +#define SPI_WPMR_WPEN_Msk (_U_(0x1) << SPI_WPMR_WPEN_Pos) /**< (SPI_WPMR) Write Protection Enable Mask */ +#define SPI_WPMR_WPEN(value) (SPI_WPMR_WPEN_Msk & ((value) << SPI_WPMR_WPEN_Pos)) +#define SPI_WPMR_WPKEY_Pos _U_(8) /**< (SPI_WPMR) Write Protection Key Position */ +#define SPI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Write Protection Key Mask */ +#define SPI_WPMR_WPKEY(value) (SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)) +#define SPI_WPMR_WPKEY_PASSWD_Val _U_(0x535049) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SPI_WPMR_WPKEY_PASSWD (SPI_WPMR_WPKEY_PASSWD_Val << SPI_WPMR_WPKEY_Pos) /**< (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SPI_WPMR_Msk _U_(0xFFFFFF01) /**< (SPI_WPMR) Register Mask */ + + +/* -------- SPI_WPSR : (SPI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS_Pos _U_(0) /**< (SPI_WPSR) Write Protection Violation Status Position */ +#define SPI_WPSR_WPVS_Msk (_U_(0x1) << SPI_WPSR_WPVS_Pos) /**< (SPI_WPSR) Write Protection Violation Status Mask */ +#define SPI_WPSR_WPVS(value) (SPI_WPSR_WPVS_Msk & ((value) << SPI_WPSR_WPVS_Pos)) +#define SPI_WPSR_WPVSRC_Pos _U_(8) /**< (SPI_WPSR) Write Protection Violation Source Position */ +#define SPI_WPSR_WPVSRC_Msk (_U_(0xFF) << SPI_WPSR_WPVSRC_Pos) /**< (SPI_WPSR) Write Protection Violation Source Mask */ +#define SPI_WPSR_WPVSRC(value) (SPI_WPSR_WPVSRC_Msk & ((value) << SPI_WPSR_WPVSRC_Pos)) +#define SPI_WPSR_Msk _U_(0x0000FF01) /**< (SPI_WPSR) Register Mask */ + + +/** \brief SPI register offsets definitions */ +#define SPI_CR_REG_OFST (0x00) /**< (SPI_CR) Control Register Offset */ +#define SPI_MR_REG_OFST (0x04) /**< (SPI_MR) Mode Register Offset */ +#define SPI_RDR_REG_OFST (0x08) /**< (SPI_RDR) Receive Data Register Offset */ +#define SPI_TDR_REG_OFST (0x0C) /**< (SPI_TDR) Transmit Data Register Offset */ +#define SPI_SR_REG_OFST (0x10) /**< (SPI_SR) Status Register Offset */ +#define SPI_IER_REG_OFST (0x14) /**< (SPI_IER) Interrupt Enable Register Offset */ +#define SPI_IDR_REG_OFST (0x18) /**< (SPI_IDR) Interrupt Disable Register Offset */ +#define SPI_IMR_REG_OFST (0x1C) /**< (SPI_IMR) Interrupt Mask Register Offset */ +#define SPI_CSR_REG_OFST (0x30) /**< (SPI_CSR) Chip Select Register Offset */ +#define SPI_WPMR_REG_OFST (0xE4) /**< (SPI_WPMR) Write Protection Mode Register Offset */ +#define SPI_WPSR_REG_OFST (0xE8) /**< (SPI_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SPI register API structure */ +typedef struct +{ + __O uint32_t SPI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t SPI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t SPI_RDR; /**< Offset: 0x08 (R/ 32) Receive Data Register */ + __O uint32_t SPI_TDR; /**< Offset: 0x0C ( /W 32) Transmit Data Register */ + __I uint32_t SPI_SR; /**< Offset: 0x10 (R/ 32) Status Register */ + __O uint32_t SPI_IER; /**< Offset: 0x14 ( /W 32) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< Offset: 0x18 ( /W 32) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< Offset: 0x1C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved1[0x10]; + __IO uint32_t SPI_CSR[4]; /**< Offset: 0x30 (R/W 32) Chip Select Register */ + __I uint8_t Reserved2[0xA4]; + __IO uint32_t SPI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} spi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SPI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/ssc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/ssc.h new file mode 100644 index 00000000..e2e02c00 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/ssc.h @@ -0,0 +1,514 @@ +/** + * \brief Component description for SSC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_SSC_COMPONENT_H_ +#define _SAME70_SSC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SSC */ +/* ************************************************************************** */ + +/* -------- SSC_CR : (SSC Offset: 0x00) ( /W 32) Control Register -------- */ +#define SSC_CR_RXEN_Pos _U_(0) /**< (SSC_CR) Receive Enable Position */ +#define SSC_CR_RXEN_Msk (_U_(0x1) << SSC_CR_RXEN_Pos) /**< (SSC_CR) Receive Enable Mask */ +#define SSC_CR_RXEN(value) (SSC_CR_RXEN_Msk & ((value) << SSC_CR_RXEN_Pos)) +#define SSC_CR_RXDIS_Pos _U_(1) /**< (SSC_CR) Receive Disable Position */ +#define SSC_CR_RXDIS_Msk (_U_(0x1) << SSC_CR_RXDIS_Pos) /**< (SSC_CR) Receive Disable Mask */ +#define SSC_CR_RXDIS(value) (SSC_CR_RXDIS_Msk & ((value) << SSC_CR_RXDIS_Pos)) +#define SSC_CR_TXEN_Pos _U_(8) /**< (SSC_CR) Transmit Enable Position */ +#define SSC_CR_TXEN_Msk (_U_(0x1) << SSC_CR_TXEN_Pos) /**< (SSC_CR) Transmit Enable Mask */ +#define SSC_CR_TXEN(value) (SSC_CR_TXEN_Msk & ((value) << SSC_CR_TXEN_Pos)) +#define SSC_CR_TXDIS_Pos _U_(9) /**< (SSC_CR) Transmit Disable Position */ +#define SSC_CR_TXDIS_Msk (_U_(0x1) << SSC_CR_TXDIS_Pos) /**< (SSC_CR) Transmit Disable Mask */ +#define SSC_CR_TXDIS(value) (SSC_CR_TXDIS_Msk & ((value) << SSC_CR_TXDIS_Pos)) +#define SSC_CR_SWRST_Pos _U_(15) /**< (SSC_CR) Software Reset Position */ +#define SSC_CR_SWRST_Msk (_U_(0x1) << SSC_CR_SWRST_Pos) /**< (SSC_CR) Software Reset Mask */ +#define SSC_CR_SWRST(value) (SSC_CR_SWRST_Msk & ((value) << SSC_CR_SWRST_Pos)) +#define SSC_CR_Msk _U_(0x00008303) /**< (SSC_CR) Register Mask */ + + +/* -------- SSC_CMR : (SSC Offset: 0x04) (R/W 32) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos _U_(0) /**< (SSC_CMR) Clock Divider Position */ +#define SSC_CMR_DIV_Msk (_U_(0xFFF) << SSC_CMR_DIV_Pos) /**< (SSC_CMR) Clock Divider Mask */ +#define SSC_CMR_DIV(value) (SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)) +#define SSC_CMR_Msk _U_(0x00000FFF) /**< (SSC_CMR) Register Mask */ + + +/* -------- SSC_RCMR : (SSC Offset: 0x10) (R/W 32) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos _U_(0) /**< (SSC_RCMR) Receive Clock Selection Position */ +#define SSC_RCMR_CKS_Msk (_U_(0x3) << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Receive Clock Selection Mask */ +#define SSC_RCMR_CKS(value) (SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)) +#define SSC_RCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK_Val _U_(0x1) /**< (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK_Val _U_(0x2) /**< (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKS_MCK (SSC_RCMR_CKS_MCK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Divided Clock Position */ +#define SSC_RCMR_CKS_TK (SSC_RCMR_CKS_TK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) TK Clock signal Position */ +#define SSC_RCMR_CKS_RK (SSC_RCMR_CKS_RK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) RK pin Position */ +#define SSC_RCMR_CKO_Pos _U_(2) /**< (SSC_RCMR) Receive Clock Output Mode Selection Position */ +#define SSC_RCMR_CKO_Msk (_U_(0x7) << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock Output Mode Selection Mask */ +#define SSC_RCMR_CKO(value) (SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)) +#define SSC_RCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKO_NONE (SSC_RCMR_CKO_NONE_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) None, RK pin is an input Position */ +#define SSC_RCMR_CKO_CONTINUOUS (SSC_RCMR_CKO_CONTINUOUS_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output Position */ +#define SSC_RCMR_CKO_TRANSFER (SSC_RCMR_CKO_TRANSFER_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output Position */ +#define SSC_RCMR_CKI_Pos _U_(5) /**< (SSC_RCMR) Receive Clock Inversion Position */ +#define SSC_RCMR_CKI_Msk (_U_(0x1) << SSC_RCMR_CKI_Pos) /**< (SSC_RCMR) Receive Clock Inversion Mask */ +#define SSC_RCMR_CKI(value) (SSC_RCMR_CKI_Msk & ((value) << SSC_RCMR_CKI_Pos)) +#define SSC_RCMR_CKG_Pos _U_(6) /**< (SSC_RCMR) Receive Clock Gating Selection Position */ +#define SSC_RCMR_CKG_Msk (_U_(0x3) << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock Gating Selection Mask */ +#define SSC_RCMR_CKG(value) (SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)) +#define SSC_RCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW_Val _U_(0x1) /**< (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_CKG_CONTINUOUS (SSC_RCMR_CKG_CONTINUOUS_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) None Position */ +#define SSC_RCMR_CKG_EN_RF_LOW (SSC_RCMR_CKG_EN_RF_LOW_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF Low Position */ +#define SSC_RCMR_CKG_EN_RF_HIGH (SSC_RCMR_CKG_EN_RF_HIGH_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF High Position */ +#define SSC_RCMR_START_Pos _U_(8) /**< (SSC_RCMR) Receive Start Selection Position */ +#define SSC_RCMR_START_Msk (_U_(0xF) << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Receive Start Selection Mask */ +#define SSC_RCMR_START(value) (SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)) +#define SSC_RCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT_Val _U_(0x1) /**< (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW_Val _U_(0x2) /**< (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH_Val _U_(0x3) /**< (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING_Val _U_(0x4) /**< (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING_Val _U_(0x5) /**< (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL_Val _U_(0x6) /**< (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE_Val _U_(0x7) /**< (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0_Val _U_(0x8) /**< (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_START_CONTINUOUS (SSC_RCMR_START_CONTINUOUS_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Position */ +#define SSC_RCMR_START_TRANSMIT (SSC_RCMR_START_TRANSMIT_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Transmit start Position */ +#define SSC_RCMR_START_RF_LOW (SSC_RCMR_START_RF_LOW_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a low level on RF signal Position */ +#define SSC_RCMR_START_RF_HIGH (SSC_RCMR_START_RF_HIGH_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a high level on RF signal Position */ +#define SSC_RCMR_START_RF_FALLING (SSC_RCMR_START_RF_FALLING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a falling edge on RF signal Position */ +#define SSC_RCMR_START_RF_RISING (SSC_RCMR_START_RF_RISING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a rising edge on RF signal Position */ +#define SSC_RCMR_START_RF_LEVEL (SSC_RCMR_START_RF_LEVEL_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any level change on RF signal Position */ +#define SSC_RCMR_START_RF_EDGE (SSC_RCMR_START_RF_EDGE_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any edge on RF signal Position */ +#define SSC_RCMR_START_CMP_0 (SSC_RCMR_START_CMP_0_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Compare 0 Position */ +#define SSC_RCMR_STOP_Pos _U_(12) /**< (SSC_RCMR) Receive Stop Selection Position */ +#define SSC_RCMR_STOP_Msk (_U_(0x1) << SSC_RCMR_STOP_Pos) /**< (SSC_RCMR) Receive Stop Selection Mask */ +#define SSC_RCMR_STOP(value) (SSC_RCMR_STOP_Msk & ((value) << SSC_RCMR_STOP_Pos)) +#define SSC_RCMR_STTDLY_Pos _U_(16) /**< (SSC_RCMR) Receive Start Delay Position */ +#define SSC_RCMR_STTDLY_Msk (_U_(0xFF) << SSC_RCMR_STTDLY_Pos) /**< (SSC_RCMR) Receive Start Delay Mask */ +#define SSC_RCMR_STTDLY(value) (SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)) +#define SSC_RCMR_PERIOD_Pos _U_(24) /**< (SSC_RCMR) Receive Period Divider Selection Position */ +#define SSC_RCMR_PERIOD_Msk (_U_(0xFF) << SSC_RCMR_PERIOD_Pos) /**< (SSC_RCMR) Receive Period Divider Selection Mask */ +#define SSC_RCMR_PERIOD(value) (SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)) +#define SSC_RCMR_Msk _U_(0xFFFF1FFF) /**< (SSC_RCMR) Register Mask */ + + +/* -------- SSC_RFMR : (SSC Offset: 0x14) (R/W 32) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos _U_(0) /**< (SSC_RFMR) Data Length Position */ +#define SSC_RFMR_DATLEN_Msk (_U_(0x1F) << SSC_RFMR_DATLEN_Pos) /**< (SSC_RFMR) Data Length Mask */ +#define SSC_RFMR_DATLEN(value) (SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)) +#define SSC_RFMR_LOOP_Pos _U_(5) /**< (SSC_RFMR) Loop Mode Position */ +#define SSC_RFMR_LOOP_Msk (_U_(0x1) << SSC_RFMR_LOOP_Pos) /**< (SSC_RFMR) Loop Mode Mask */ +#define SSC_RFMR_LOOP(value) (SSC_RFMR_LOOP_Msk & ((value) << SSC_RFMR_LOOP_Pos)) +#define SSC_RFMR_MSBF_Pos _U_(7) /**< (SSC_RFMR) Most Significant Bit First Position */ +#define SSC_RFMR_MSBF_Msk (_U_(0x1) << SSC_RFMR_MSBF_Pos) /**< (SSC_RFMR) Most Significant Bit First Mask */ +#define SSC_RFMR_MSBF(value) (SSC_RFMR_MSBF_Msk & ((value) << SSC_RFMR_MSBF_Pos)) +#define SSC_RFMR_DATNB_Pos _U_(8) /**< (SSC_RFMR) Data Number per Frame Position */ +#define SSC_RFMR_DATNB_Msk (_U_(0xF) << SSC_RFMR_DATNB_Pos) /**< (SSC_RFMR) Data Number per Frame Mask */ +#define SSC_RFMR_DATNB(value) (SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)) +#define SSC_RFMR_FSLEN_Pos _U_(16) /**< (SSC_RFMR) Receive Frame Sync Length Position */ +#define SSC_RFMR_FSLEN_Msk (_U_(0xF) << SSC_RFMR_FSLEN_Pos) /**< (SSC_RFMR) Receive Frame Sync Length Mask */ +#define SSC_RFMR_FSLEN(value) (SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)) +#define SSC_RFMR_FSOS_Pos _U_(20) /**< (SSC_RFMR) Receive Frame Sync Output Selection Position */ +#define SSC_RFMR_FSOS_Msk (_U_(0x7) << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Receive Frame Sync Output Selection Mask */ +#define SSC_RFMR_FSOS(value) (SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)) +#define SSC_RFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_NONE (SSC_RFMR_FSOS_NONE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) None, RF pin is an input Position */ +#define SSC_RFMR_FSOS_NEGATIVE (SSC_RFMR_FSOS_NEGATIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Negative Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_POSITIVE (SSC_RFMR_FSOS_POSITIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Positive Pulse, RF pin is an output Position */ +#define SSC_RFMR_FSOS_LOW (SSC_RFMR_FSOS_LOW_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_HIGH (SSC_RFMR_FSOS_HIGH_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSOS_TOGGLING (SSC_RFMR_FSOS_TOGGLING_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output Position */ +#define SSC_RFMR_FSEDGE_Pos _U_(24) /**< (SSC_RFMR) Frame Sync Edge Detection Position */ +#define SSC_RFMR_FSEDGE_Msk (_U_(0x1) << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Frame Sync Edge Detection Mask */ +#define SSC_RFMR_FSEDGE(value) (SSC_RFMR_FSEDGE_Msk & ((value) << SSC_RFMR_FSEDGE_Pos)) +#define SSC_RFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (SSC_RFMR_FSEDGE_POSITIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Positive Edge Detection Position */ +#define SSC_RFMR_FSEDGE_NEGATIVE (SSC_RFMR_FSEDGE_NEGATIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Negative Edge Detection Position */ +#define SSC_RFMR_FSLEN_EXT_Pos _U_(28) /**< (SSC_RFMR) FSLEN Field Extension Position */ +#define SSC_RFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_RFMR_FSLEN_EXT_Pos) /**< (SSC_RFMR) FSLEN Field Extension Mask */ +#define SSC_RFMR_FSLEN_EXT(value) (SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)) +#define SSC_RFMR_Msk _U_(0xF17F0FBF) /**< (SSC_RFMR) Register Mask */ + + +/* -------- SSC_TCMR : (SSC Offset: 0x18) (R/W 32) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos _U_(0) /**< (SSC_TCMR) Transmit Clock Selection Position */ +#define SSC_TCMR_CKS_Msk (_U_(0x3) << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Transmit Clock Selection Mask */ +#define SSC_TCMR_CKS(value) (SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)) +#define SSC_TCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK_Val _U_(0x1) /**< (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK_Val _U_(0x2) /**< (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKS_MCK (SSC_TCMR_CKS_MCK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Divided Clock Position */ +#define SSC_TCMR_CKS_RK (SSC_TCMR_CKS_RK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) RK Clock signal Position */ +#define SSC_TCMR_CKS_TK (SSC_TCMR_CKS_TK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) TK pin Position */ +#define SSC_TCMR_CKO_Pos _U_(2) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Position */ +#define SSC_TCMR_CKO_Msk (_U_(0x7) << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Mask */ +#define SSC_TCMR_CKO(value) (SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)) +#define SSC_TCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKO_NONE (SSC_TCMR_CKO_NONE_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) None, TK pin is an input Position */ +#define SSC_TCMR_CKO_CONTINUOUS (SSC_TCMR_CKO_CONTINUOUS_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output Position */ +#define SSC_TCMR_CKO_TRANSFER (SSC_TCMR_CKO_TRANSFER_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output Position */ +#define SSC_TCMR_CKI_Pos _U_(5) /**< (SSC_TCMR) Transmit Clock Inversion Position */ +#define SSC_TCMR_CKI_Msk (_U_(0x1) << SSC_TCMR_CKI_Pos) /**< (SSC_TCMR) Transmit Clock Inversion Mask */ +#define SSC_TCMR_CKI(value) (SSC_TCMR_CKI_Msk & ((value) << SSC_TCMR_CKI_Pos)) +#define SSC_TCMR_CKG_Pos _U_(6) /**< (SSC_TCMR) Transmit Clock Gating Selection Position */ +#define SSC_TCMR_CKG_Msk (_U_(0x3) << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock Gating Selection Mask */ +#define SSC_TCMR_CKG(value) (SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)) +#define SSC_TCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW_Val _U_(0x1) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_CKG_CONTINUOUS (SSC_TCMR_CKG_CONTINUOUS_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) None Position */ +#define SSC_TCMR_CKG_EN_TF_LOW (SSC_TCMR_CKG_EN_TF_LOW_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low Position */ +#define SSC_TCMR_CKG_EN_TF_HIGH (SSC_TCMR_CKG_EN_TF_HIGH_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF High Position */ +#define SSC_TCMR_START_Pos _U_(8) /**< (SSC_TCMR) Transmit Start Selection Position */ +#define SSC_TCMR_START_Msk (_U_(0xF) << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Transmit Start Selection Mask */ +#define SSC_TCMR_START(value) (SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)) +#define SSC_TCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE_Val _U_(0x1) /**< (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW_Val _U_(0x2) /**< (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH_Val _U_(0x3) /**< (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING_Val _U_(0x4) /**< (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING_Val _U_(0x5) /**< (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL_Val _U_(0x6) /**< (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE_Val _U_(0x7) /**< (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CONTINUOUS (SSC_TCMR_START_CONTINUOUS_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data Position */ +#define SSC_TCMR_START_RECEIVE (SSC_TCMR_START_RECEIVE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Receive start Position */ +#define SSC_TCMR_START_TF_LOW (SSC_TCMR_START_TF_LOW_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a low level on TF signal Position */ +#define SSC_TCMR_START_TF_HIGH (SSC_TCMR_START_TF_HIGH_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a high level on TF signal Position */ +#define SSC_TCMR_START_TF_FALLING (SSC_TCMR_START_TF_FALLING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a falling edge on TF signal Position */ +#define SSC_TCMR_START_TF_RISING (SSC_TCMR_START_TF_RISING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a rising edge on TF signal Position */ +#define SSC_TCMR_START_TF_LEVEL (SSC_TCMR_START_TF_LEVEL_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any level change on TF signal Position */ +#define SSC_TCMR_START_TF_EDGE (SSC_TCMR_START_TF_EDGE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any edge on TF signal Position */ +#define SSC_TCMR_STTDLY_Pos _U_(16) /**< (SSC_TCMR) Transmit Start Delay Position */ +#define SSC_TCMR_STTDLY_Msk (_U_(0xFF) << SSC_TCMR_STTDLY_Pos) /**< (SSC_TCMR) Transmit Start Delay Mask */ +#define SSC_TCMR_STTDLY(value) (SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)) +#define SSC_TCMR_PERIOD_Pos _U_(24) /**< (SSC_TCMR) Transmit Period Divider Selection Position */ +#define SSC_TCMR_PERIOD_Msk (_U_(0xFF) << SSC_TCMR_PERIOD_Pos) /**< (SSC_TCMR) Transmit Period Divider Selection Mask */ +#define SSC_TCMR_PERIOD(value) (SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)) +#define SSC_TCMR_Msk _U_(0xFFFF0FFF) /**< (SSC_TCMR) Register Mask */ + + +/* -------- SSC_TFMR : (SSC Offset: 0x1C) (R/W 32) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos _U_(0) /**< (SSC_TFMR) Data Length Position */ +#define SSC_TFMR_DATLEN_Msk (_U_(0x1F) << SSC_TFMR_DATLEN_Pos) /**< (SSC_TFMR) Data Length Mask */ +#define SSC_TFMR_DATLEN(value) (SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)) +#define SSC_TFMR_DATDEF_Pos _U_(5) /**< (SSC_TFMR) Data Default Value Position */ +#define SSC_TFMR_DATDEF_Msk (_U_(0x1) << SSC_TFMR_DATDEF_Pos) /**< (SSC_TFMR) Data Default Value Mask */ +#define SSC_TFMR_DATDEF(value) (SSC_TFMR_DATDEF_Msk & ((value) << SSC_TFMR_DATDEF_Pos)) +#define SSC_TFMR_MSBF_Pos _U_(7) /**< (SSC_TFMR) Most Significant Bit First Position */ +#define SSC_TFMR_MSBF_Msk (_U_(0x1) << SSC_TFMR_MSBF_Pos) /**< (SSC_TFMR) Most Significant Bit First Mask */ +#define SSC_TFMR_MSBF(value) (SSC_TFMR_MSBF_Msk & ((value) << SSC_TFMR_MSBF_Pos)) +#define SSC_TFMR_DATNB_Pos _U_(8) /**< (SSC_TFMR) Data Number per Frame Position */ +#define SSC_TFMR_DATNB_Msk (_U_(0xF) << SSC_TFMR_DATNB_Pos) /**< (SSC_TFMR) Data Number per Frame Mask */ +#define SSC_TFMR_DATNB(value) (SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)) +#define SSC_TFMR_FSLEN_Pos _U_(16) /**< (SSC_TFMR) Transmit Frame Sync Length Position */ +#define SSC_TFMR_FSLEN_Msk (_U_(0xF) << SSC_TFMR_FSLEN_Pos) /**< (SSC_TFMR) Transmit Frame Sync Length Mask */ +#define SSC_TFMR_FSLEN(value) (SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)) +#define SSC_TFMR_FSOS_Pos _U_(20) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Position */ +#define SSC_TFMR_FSOS_Msk (_U_(0x7) << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Mask */ +#define SSC_TFMR_FSOS(value) (SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)) +#define SSC_TFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSOS_NONE (SSC_TFMR_FSOS_NONE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) None, TF pin is an input Position */ +#define SSC_TFMR_FSOS_NEGATIVE (SSC_TFMR_FSOS_NEGATIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Negative Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_POSITIVE (SSC_TFMR_FSOS_POSITIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Positive Pulse, TF pin is an output Position */ +#define SSC_TFMR_FSOS_LOW (SSC_TFMR_FSOS_LOW_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven Low during data transfer Position */ +#define SSC_TFMR_FSOS_HIGH (SSC_TFMR_FSOS_HIGH_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven High during data transfer Position */ +#define SSC_TFMR_FSOS_TOGGLING (SSC_TFMR_FSOS_TOGGLING_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Toggling at each start of data transfer Position */ +#define SSC_TFMR_FSDEN_Pos _U_(23) /**< (SSC_TFMR) Frame Sync Data Enable Position */ +#define SSC_TFMR_FSDEN_Msk (_U_(0x1) << SSC_TFMR_FSDEN_Pos) /**< (SSC_TFMR) Frame Sync Data Enable Mask */ +#define SSC_TFMR_FSDEN(value) (SSC_TFMR_FSDEN_Msk & ((value) << SSC_TFMR_FSDEN_Pos)) +#define SSC_TFMR_FSEDGE_Pos _U_(24) /**< (SSC_TFMR) Frame Sync Edge Detection Position */ +#define SSC_TFMR_FSEDGE_Msk (_U_(0x1) << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Frame Sync Edge Detection Mask */ +#define SSC_TFMR_FSEDGE(value) (SSC_TFMR_FSEDGE_Msk & ((value) << SSC_TFMR_FSEDGE_Pos)) +#define SSC_TFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (SSC_TFMR_FSEDGE_POSITIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Positive Edge Detection Position */ +#define SSC_TFMR_FSEDGE_NEGATIVE (SSC_TFMR_FSEDGE_NEGATIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Negative Edge Detection Position */ +#define SSC_TFMR_FSLEN_EXT_Pos _U_(28) /**< (SSC_TFMR) FSLEN Field Extension Position */ +#define SSC_TFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_TFMR_FSLEN_EXT_Pos) /**< (SSC_TFMR) FSLEN Field Extension Mask */ +#define SSC_TFMR_FSLEN_EXT(value) (SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)) +#define SSC_TFMR_Msk _U_(0xF1FF0FBF) /**< (SSC_TFMR) Register Mask */ + + +/* -------- SSC_RHR : (SSC Offset: 0x20) ( R/ 32) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos _U_(0) /**< (SSC_RHR) Receive Data Position */ +#define SSC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << SSC_RHR_RDAT_Pos) /**< (SSC_RHR) Receive Data Mask */ +#define SSC_RHR_RDAT(value) (SSC_RHR_RDAT_Msk & ((value) << SSC_RHR_RDAT_Pos)) +#define SSC_RHR_Msk _U_(0xFFFFFFFF) /**< (SSC_RHR) Register Mask */ + + +/* -------- SSC_THR : (SSC Offset: 0x24) ( /W 32) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos _U_(0) /**< (SSC_THR) Transmit Data Position */ +#define SSC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << SSC_THR_TDAT_Pos) /**< (SSC_THR) Transmit Data Mask */ +#define SSC_THR_TDAT(value) (SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)) +#define SSC_THR_Msk _U_(0xFFFFFFFF) /**< (SSC_THR) Register Mask */ + + +/* -------- SSC_RSHR : (SSC Offset: 0x30) ( R/ 32) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos _U_(0) /**< (SSC_RSHR) Receive Synchronization Data Position */ +#define SSC_RSHR_RSDAT_Msk (_U_(0xFFFF) << SSC_RSHR_RSDAT_Pos) /**< (SSC_RSHR) Receive Synchronization Data Mask */ +#define SSC_RSHR_RSDAT(value) (SSC_RSHR_RSDAT_Msk & ((value) << SSC_RSHR_RSDAT_Pos)) +#define SSC_RSHR_Msk _U_(0x0000FFFF) /**< (SSC_RSHR) Register Mask */ + + +/* -------- SSC_TSHR : (SSC Offset: 0x34) (R/W 32) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos _U_(0) /**< (SSC_TSHR) Transmit Synchronization Data Position */ +#define SSC_TSHR_TSDAT_Msk (_U_(0xFFFF) << SSC_TSHR_TSDAT_Pos) /**< (SSC_TSHR) Transmit Synchronization Data Mask */ +#define SSC_TSHR_TSDAT(value) (SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)) +#define SSC_TSHR_Msk _U_(0x0000FFFF) /**< (SSC_TSHR) Register Mask */ + + +/* -------- SSC_RC0R : (SSC Offset: 0x38) (R/W 32) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos _U_(0) /**< (SSC_RC0R) Receive Compare Data 0 Position */ +#define SSC_RC0R_CP0_Msk (_U_(0xFFFF) << SSC_RC0R_CP0_Pos) /**< (SSC_RC0R) Receive Compare Data 0 Mask */ +#define SSC_RC0R_CP0(value) (SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)) +#define SSC_RC0R_Msk _U_(0x0000FFFF) /**< (SSC_RC0R) Register Mask */ + + +/* -------- SSC_RC1R : (SSC Offset: 0x3C) (R/W 32) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos _U_(0) /**< (SSC_RC1R) Receive Compare Data 1 Position */ +#define SSC_RC1R_CP1_Msk (_U_(0xFFFF) << SSC_RC1R_CP1_Pos) /**< (SSC_RC1R) Receive Compare Data 1 Mask */ +#define SSC_RC1R_CP1(value) (SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)) +#define SSC_RC1R_Msk _U_(0x0000FFFF) /**< (SSC_RC1R) Register Mask */ + + +/* -------- SSC_SR : (SSC Offset: 0x40) ( R/ 32) Status Register -------- */ +#define SSC_SR_TXRDY_Pos _U_(0) /**< (SSC_SR) Transmit Ready Position */ +#define SSC_SR_TXRDY_Msk (_U_(0x1) << SSC_SR_TXRDY_Pos) /**< (SSC_SR) Transmit Ready Mask */ +#define SSC_SR_TXRDY(value) (SSC_SR_TXRDY_Msk & ((value) << SSC_SR_TXRDY_Pos)) +#define SSC_SR_TXEMPTY_Pos _U_(1) /**< (SSC_SR) Transmit Empty Position */ +#define SSC_SR_TXEMPTY_Msk (_U_(0x1) << SSC_SR_TXEMPTY_Pos) /**< (SSC_SR) Transmit Empty Mask */ +#define SSC_SR_TXEMPTY(value) (SSC_SR_TXEMPTY_Msk & ((value) << SSC_SR_TXEMPTY_Pos)) +#define SSC_SR_RXRDY_Pos _U_(4) /**< (SSC_SR) Receive Ready Position */ +#define SSC_SR_RXRDY_Msk (_U_(0x1) << SSC_SR_RXRDY_Pos) /**< (SSC_SR) Receive Ready Mask */ +#define SSC_SR_RXRDY(value) (SSC_SR_RXRDY_Msk & ((value) << SSC_SR_RXRDY_Pos)) +#define SSC_SR_OVRUN_Pos _U_(5) /**< (SSC_SR) Receive Overrun Position */ +#define SSC_SR_OVRUN_Msk (_U_(0x1) << SSC_SR_OVRUN_Pos) /**< (SSC_SR) Receive Overrun Mask */ +#define SSC_SR_OVRUN(value) (SSC_SR_OVRUN_Msk & ((value) << SSC_SR_OVRUN_Pos)) +#define SSC_SR_CP0_Pos _U_(8) /**< (SSC_SR) Compare 0 Position */ +#define SSC_SR_CP0_Msk (_U_(0x1) << SSC_SR_CP0_Pos) /**< (SSC_SR) Compare 0 Mask */ +#define SSC_SR_CP0(value) (SSC_SR_CP0_Msk & ((value) << SSC_SR_CP0_Pos)) +#define SSC_SR_CP1_Pos _U_(9) /**< (SSC_SR) Compare 1 Position */ +#define SSC_SR_CP1_Msk (_U_(0x1) << SSC_SR_CP1_Pos) /**< (SSC_SR) Compare 1 Mask */ +#define SSC_SR_CP1(value) (SSC_SR_CP1_Msk & ((value) << SSC_SR_CP1_Pos)) +#define SSC_SR_TXSYN_Pos _U_(10) /**< (SSC_SR) Transmit Sync Position */ +#define SSC_SR_TXSYN_Msk (_U_(0x1) << SSC_SR_TXSYN_Pos) /**< (SSC_SR) Transmit Sync Mask */ +#define SSC_SR_TXSYN(value) (SSC_SR_TXSYN_Msk & ((value) << SSC_SR_TXSYN_Pos)) +#define SSC_SR_RXSYN_Pos _U_(11) /**< (SSC_SR) Receive Sync Position */ +#define SSC_SR_RXSYN_Msk (_U_(0x1) << SSC_SR_RXSYN_Pos) /**< (SSC_SR) Receive Sync Mask */ +#define SSC_SR_RXSYN(value) (SSC_SR_RXSYN_Msk & ((value) << SSC_SR_RXSYN_Pos)) +#define SSC_SR_TXEN_Pos _U_(16) /**< (SSC_SR) Transmit Enable Position */ +#define SSC_SR_TXEN_Msk (_U_(0x1) << SSC_SR_TXEN_Pos) /**< (SSC_SR) Transmit Enable Mask */ +#define SSC_SR_TXEN(value) (SSC_SR_TXEN_Msk & ((value) << SSC_SR_TXEN_Pos)) +#define SSC_SR_RXEN_Pos _U_(17) /**< (SSC_SR) Receive Enable Position */ +#define SSC_SR_RXEN_Msk (_U_(0x1) << SSC_SR_RXEN_Pos) /**< (SSC_SR) Receive Enable Mask */ +#define SSC_SR_RXEN(value) (SSC_SR_RXEN_Msk & ((value) << SSC_SR_RXEN_Pos)) +#define SSC_SR_Msk _U_(0x00030F33) /**< (SSC_SR) Register Mask */ + +#define SSC_SR_CP_Pos _U_(8) /**< (SSC_SR Position) Compare x */ +#define SSC_SR_CP_Msk (_U_(0x3) << SSC_SR_CP_Pos) /**< (SSC_SR Mask) CP */ +#define SSC_SR_CP(value) (SSC_SR_CP_Msk & ((value) << SSC_SR_CP_Pos)) + +/* -------- SSC_IER : (SSC Offset: 0x44) ( /W 32) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY_Pos _U_(0) /**< (SSC_IER) Transmit Ready Interrupt Enable Position */ +#define SSC_IER_TXRDY_Msk (_U_(0x1) << SSC_IER_TXRDY_Pos) /**< (SSC_IER) Transmit Ready Interrupt Enable Mask */ +#define SSC_IER_TXRDY(value) (SSC_IER_TXRDY_Msk & ((value) << SSC_IER_TXRDY_Pos)) +#define SSC_IER_TXEMPTY_Pos _U_(1) /**< (SSC_IER) Transmit Empty Interrupt Enable Position */ +#define SSC_IER_TXEMPTY_Msk (_U_(0x1) << SSC_IER_TXEMPTY_Pos) /**< (SSC_IER) Transmit Empty Interrupt Enable Mask */ +#define SSC_IER_TXEMPTY(value) (SSC_IER_TXEMPTY_Msk & ((value) << SSC_IER_TXEMPTY_Pos)) +#define SSC_IER_RXRDY_Pos _U_(4) /**< (SSC_IER) Receive Ready Interrupt Enable Position */ +#define SSC_IER_RXRDY_Msk (_U_(0x1) << SSC_IER_RXRDY_Pos) /**< (SSC_IER) Receive Ready Interrupt Enable Mask */ +#define SSC_IER_RXRDY(value) (SSC_IER_RXRDY_Msk & ((value) << SSC_IER_RXRDY_Pos)) +#define SSC_IER_OVRUN_Pos _U_(5) /**< (SSC_IER) Receive Overrun Interrupt Enable Position */ +#define SSC_IER_OVRUN_Msk (_U_(0x1) << SSC_IER_OVRUN_Pos) /**< (SSC_IER) Receive Overrun Interrupt Enable Mask */ +#define SSC_IER_OVRUN(value) (SSC_IER_OVRUN_Msk & ((value) << SSC_IER_OVRUN_Pos)) +#define SSC_IER_CP0_Pos _U_(8) /**< (SSC_IER) Compare 0 Interrupt Enable Position */ +#define SSC_IER_CP0_Msk (_U_(0x1) << SSC_IER_CP0_Pos) /**< (SSC_IER) Compare 0 Interrupt Enable Mask */ +#define SSC_IER_CP0(value) (SSC_IER_CP0_Msk & ((value) << SSC_IER_CP0_Pos)) +#define SSC_IER_CP1_Pos _U_(9) /**< (SSC_IER) Compare 1 Interrupt Enable Position */ +#define SSC_IER_CP1_Msk (_U_(0x1) << SSC_IER_CP1_Pos) /**< (SSC_IER) Compare 1 Interrupt Enable Mask */ +#define SSC_IER_CP1(value) (SSC_IER_CP1_Msk & ((value) << SSC_IER_CP1_Pos)) +#define SSC_IER_TXSYN_Pos _U_(10) /**< (SSC_IER) Tx Sync Interrupt Enable Position */ +#define SSC_IER_TXSYN_Msk (_U_(0x1) << SSC_IER_TXSYN_Pos) /**< (SSC_IER) Tx Sync Interrupt Enable Mask */ +#define SSC_IER_TXSYN(value) (SSC_IER_TXSYN_Msk & ((value) << SSC_IER_TXSYN_Pos)) +#define SSC_IER_RXSYN_Pos _U_(11) /**< (SSC_IER) Rx Sync Interrupt Enable Position */ +#define SSC_IER_RXSYN_Msk (_U_(0x1) << SSC_IER_RXSYN_Pos) /**< (SSC_IER) Rx Sync Interrupt Enable Mask */ +#define SSC_IER_RXSYN(value) (SSC_IER_RXSYN_Msk & ((value) << SSC_IER_RXSYN_Pos)) +#define SSC_IER_Msk _U_(0x00000F33) /**< (SSC_IER) Register Mask */ + +#define SSC_IER_CP_Pos _U_(8) /**< (SSC_IER Position) Compare x Interrupt Enable */ +#define SSC_IER_CP_Msk (_U_(0x3) << SSC_IER_CP_Pos) /**< (SSC_IER Mask) CP */ +#define SSC_IER_CP(value) (SSC_IER_CP_Msk & ((value) << SSC_IER_CP_Pos)) + +/* -------- SSC_IDR : (SSC Offset: 0x48) ( /W 32) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY_Pos _U_(0) /**< (SSC_IDR) Transmit Ready Interrupt Disable Position */ +#define SSC_IDR_TXRDY_Msk (_U_(0x1) << SSC_IDR_TXRDY_Pos) /**< (SSC_IDR) Transmit Ready Interrupt Disable Mask */ +#define SSC_IDR_TXRDY(value) (SSC_IDR_TXRDY_Msk & ((value) << SSC_IDR_TXRDY_Pos)) +#define SSC_IDR_TXEMPTY_Pos _U_(1) /**< (SSC_IDR) Transmit Empty Interrupt Disable Position */ +#define SSC_IDR_TXEMPTY_Msk (_U_(0x1) << SSC_IDR_TXEMPTY_Pos) /**< (SSC_IDR) Transmit Empty Interrupt Disable Mask */ +#define SSC_IDR_TXEMPTY(value) (SSC_IDR_TXEMPTY_Msk & ((value) << SSC_IDR_TXEMPTY_Pos)) +#define SSC_IDR_RXRDY_Pos _U_(4) /**< (SSC_IDR) Receive Ready Interrupt Disable Position */ +#define SSC_IDR_RXRDY_Msk (_U_(0x1) << SSC_IDR_RXRDY_Pos) /**< (SSC_IDR) Receive Ready Interrupt Disable Mask */ +#define SSC_IDR_RXRDY(value) (SSC_IDR_RXRDY_Msk & ((value) << SSC_IDR_RXRDY_Pos)) +#define SSC_IDR_OVRUN_Pos _U_(5) /**< (SSC_IDR) Receive Overrun Interrupt Disable Position */ +#define SSC_IDR_OVRUN_Msk (_U_(0x1) << SSC_IDR_OVRUN_Pos) /**< (SSC_IDR) Receive Overrun Interrupt Disable Mask */ +#define SSC_IDR_OVRUN(value) (SSC_IDR_OVRUN_Msk & ((value) << SSC_IDR_OVRUN_Pos)) +#define SSC_IDR_CP0_Pos _U_(8) /**< (SSC_IDR) Compare 0 Interrupt Disable Position */ +#define SSC_IDR_CP0_Msk (_U_(0x1) << SSC_IDR_CP0_Pos) /**< (SSC_IDR) Compare 0 Interrupt Disable Mask */ +#define SSC_IDR_CP0(value) (SSC_IDR_CP0_Msk & ((value) << SSC_IDR_CP0_Pos)) +#define SSC_IDR_CP1_Pos _U_(9) /**< (SSC_IDR) Compare 1 Interrupt Disable Position */ +#define SSC_IDR_CP1_Msk (_U_(0x1) << SSC_IDR_CP1_Pos) /**< (SSC_IDR) Compare 1 Interrupt Disable Mask */ +#define SSC_IDR_CP1(value) (SSC_IDR_CP1_Msk & ((value) << SSC_IDR_CP1_Pos)) +#define SSC_IDR_TXSYN_Pos _U_(10) /**< (SSC_IDR) Tx Sync Interrupt Enable Position */ +#define SSC_IDR_TXSYN_Msk (_U_(0x1) << SSC_IDR_TXSYN_Pos) /**< (SSC_IDR) Tx Sync Interrupt Enable Mask */ +#define SSC_IDR_TXSYN(value) (SSC_IDR_TXSYN_Msk & ((value) << SSC_IDR_TXSYN_Pos)) +#define SSC_IDR_RXSYN_Pos _U_(11) /**< (SSC_IDR) Rx Sync Interrupt Enable Position */ +#define SSC_IDR_RXSYN_Msk (_U_(0x1) << SSC_IDR_RXSYN_Pos) /**< (SSC_IDR) Rx Sync Interrupt Enable Mask */ +#define SSC_IDR_RXSYN(value) (SSC_IDR_RXSYN_Msk & ((value) << SSC_IDR_RXSYN_Pos)) +#define SSC_IDR_Msk _U_(0x00000F33) /**< (SSC_IDR) Register Mask */ + +#define SSC_IDR_CP_Pos _U_(8) /**< (SSC_IDR Position) Compare x Interrupt Disable */ +#define SSC_IDR_CP_Msk (_U_(0x3) << SSC_IDR_CP_Pos) /**< (SSC_IDR Mask) CP */ +#define SSC_IDR_CP(value) (SSC_IDR_CP_Msk & ((value) << SSC_IDR_CP_Pos)) + +/* -------- SSC_IMR : (SSC Offset: 0x4C) ( R/ 32) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY_Pos _U_(0) /**< (SSC_IMR) Transmit Ready Interrupt Mask Position */ +#define SSC_IMR_TXRDY_Msk (_U_(0x1) << SSC_IMR_TXRDY_Pos) /**< (SSC_IMR) Transmit Ready Interrupt Mask Mask */ +#define SSC_IMR_TXRDY(value) (SSC_IMR_TXRDY_Msk & ((value) << SSC_IMR_TXRDY_Pos)) +#define SSC_IMR_TXEMPTY_Pos _U_(1) /**< (SSC_IMR) Transmit Empty Interrupt Mask Position */ +#define SSC_IMR_TXEMPTY_Msk (_U_(0x1) << SSC_IMR_TXEMPTY_Pos) /**< (SSC_IMR) Transmit Empty Interrupt Mask Mask */ +#define SSC_IMR_TXEMPTY(value) (SSC_IMR_TXEMPTY_Msk & ((value) << SSC_IMR_TXEMPTY_Pos)) +#define SSC_IMR_RXRDY_Pos _U_(4) /**< (SSC_IMR) Receive Ready Interrupt Mask Position */ +#define SSC_IMR_RXRDY_Msk (_U_(0x1) << SSC_IMR_RXRDY_Pos) /**< (SSC_IMR) Receive Ready Interrupt Mask Mask */ +#define SSC_IMR_RXRDY(value) (SSC_IMR_RXRDY_Msk & ((value) << SSC_IMR_RXRDY_Pos)) +#define SSC_IMR_OVRUN_Pos _U_(5) /**< (SSC_IMR) Receive Overrun Interrupt Mask Position */ +#define SSC_IMR_OVRUN_Msk (_U_(0x1) << SSC_IMR_OVRUN_Pos) /**< (SSC_IMR) Receive Overrun Interrupt Mask Mask */ +#define SSC_IMR_OVRUN(value) (SSC_IMR_OVRUN_Msk & ((value) << SSC_IMR_OVRUN_Pos)) +#define SSC_IMR_CP0_Pos _U_(8) /**< (SSC_IMR) Compare 0 Interrupt Mask Position */ +#define SSC_IMR_CP0_Msk (_U_(0x1) << SSC_IMR_CP0_Pos) /**< (SSC_IMR) Compare 0 Interrupt Mask Mask */ +#define SSC_IMR_CP0(value) (SSC_IMR_CP0_Msk & ((value) << SSC_IMR_CP0_Pos)) +#define SSC_IMR_CP1_Pos _U_(9) /**< (SSC_IMR) Compare 1 Interrupt Mask Position */ +#define SSC_IMR_CP1_Msk (_U_(0x1) << SSC_IMR_CP1_Pos) /**< (SSC_IMR) Compare 1 Interrupt Mask Mask */ +#define SSC_IMR_CP1(value) (SSC_IMR_CP1_Msk & ((value) << SSC_IMR_CP1_Pos)) +#define SSC_IMR_TXSYN_Pos _U_(10) /**< (SSC_IMR) Tx Sync Interrupt Mask Position */ +#define SSC_IMR_TXSYN_Msk (_U_(0x1) << SSC_IMR_TXSYN_Pos) /**< (SSC_IMR) Tx Sync Interrupt Mask Mask */ +#define SSC_IMR_TXSYN(value) (SSC_IMR_TXSYN_Msk & ((value) << SSC_IMR_TXSYN_Pos)) +#define SSC_IMR_RXSYN_Pos _U_(11) /**< (SSC_IMR) Rx Sync Interrupt Mask Position */ +#define SSC_IMR_RXSYN_Msk (_U_(0x1) << SSC_IMR_RXSYN_Pos) /**< (SSC_IMR) Rx Sync Interrupt Mask Mask */ +#define SSC_IMR_RXSYN(value) (SSC_IMR_RXSYN_Msk & ((value) << SSC_IMR_RXSYN_Pos)) +#define SSC_IMR_Msk _U_(0x00000F33) /**< (SSC_IMR) Register Mask */ + +#define SSC_IMR_CP_Pos _U_(8) /**< (SSC_IMR Position) Compare x Interrupt Mask */ +#define SSC_IMR_CP_Msk (_U_(0x3) << SSC_IMR_CP_Pos) /**< (SSC_IMR Mask) CP */ +#define SSC_IMR_CP(value) (SSC_IMR_CP_Msk & ((value) << SSC_IMR_CP_Pos)) + +/* -------- SSC_WPMR : (SSC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN_Pos _U_(0) /**< (SSC_WPMR) Write Protection Enable Position */ +#define SSC_WPMR_WPEN_Msk (_U_(0x1) << SSC_WPMR_WPEN_Pos) /**< (SSC_WPMR) Write Protection Enable Mask */ +#define SSC_WPMR_WPEN(value) (SSC_WPMR_WPEN_Msk & ((value) << SSC_WPMR_WPEN_Pos)) +#define SSC_WPMR_WPKEY_Pos _U_(8) /**< (SSC_WPMR) Write Protection Key Position */ +#define SSC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Write Protection Key Mask */ +#define SSC_WPMR_WPKEY(value) (SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)) +#define SSC_WPMR_WPKEY_PASSWD_Val _U_(0x535343) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define SSC_WPMR_WPKEY_PASSWD (SSC_WPMR_WPKEY_PASSWD_Val << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define SSC_WPMR_Msk _U_(0xFFFFFF01) /**< (SSC_WPMR) Register Mask */ + + +/* -------- SSC_WPSR : (SSC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS_Pos _U_(0) /**< (SSC_WPSR) Write Protection Violation Status Position */ +#define SSC_WPSR_WPVS_Msk (_U_(0x1) << SSC_WPSR_WPVS_Pos) /**< (SSC_WPSR) Write Protection Violation Status Mask */ +#define SSC_WPSR_WPVS(value) (SSC_WPSR_WPVS_Msk & ((value) << SSC_WPSR_WPVS_Pos)) +#define SSC_WPSR_WPVSRC_Pos _U_(8) /**< (SSC_WPSR) Write Protect Violation Source Position */ +#define SSC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SSC_WPSR_WPVSRC_Pos) /**< (SSC_WPSR) Write Protect Violation Source Mask */ +#define SSC_WPSR_WPVSRC(value) (SSC_WPSR_WPVSRC_Msk & ((value) << SSC_WPSR_WPVSRC_Pos)) +#define SSC_WPSR_Msk _U_(0x00FFFF01) /**< (SSC_WPSR) Register Mask */ + + +/** \brief SSC register offsets definitions */ +#define SSC_CR_REG_OFST (0x00) /**< (SSC_CR) Control Register Offset */ +#define SSC_CMR_REG_OFST (0x04) /**< (SSC_CMR) Clock Mode Register Offset */ +#define SSC_RCMR_REG_OFST (0x10) /**< (SSC_RCMR) Receive Clock Mode Register Offset */ +#define SSC_RFMR_REG_OFST (0x14) /**< (SSC_RFMR) Receive Frame Mode Register Offset */ +#define SSC_TCMR_REG_OFST (0x18) /**< (SSC_TCMR) Transmit Clock Mode Register Offset */ +#define SSC_TFMR_REG_OFST (0x1C) /**< (SSC_TFMR) Transmit Frame Mode Register Offset */ +#define SSC_RHR_REG_OFST (0x20) /**< (SSC_RHR) Receive Holding Register Offset */ +#define SSC_THR_REG_OFST (0x24) /**< (SSC_THR) Transmit Holding Register Offset */ +#define SSC_RSHR_REG_OFST (0x30) /**< (SSC_RSHR) Receive Sync. Holding Register Offset */ +#define SSC_TSHR_REG_OFST (0x34) /**< (SSC_TSHR) Transmit Sync. Holding Register Offset */ +#define SSC_RC0R_REG_OFST (0x38) /**< (SSC_RC0R) Receive Compare 0 Register Offset */ +#define SSC_RC1R_REG_OFST (0x3C) /**< (SSC_RC1R) Receive Compare 1 Register Offset */ +#define SSC_SR_REG_OFST (0x40) /**< (SSC_SR) Status Register Offset */ +#define SSC_IER_REG_OFST (0x44) /**< (SSC_IER) Interrupt Enable Register Offset */ +#define SSC_IDR_REG_OFST (0x48) /**< (SSC_IDR) Interrupt Disable Register Offset */ +#define SSC_IMR_REG_OFST (0x4C) /**< (SSC_IMR) Interrupt Mask Register Offset */ +#define SSC_WPMR_REG_OFST (0xE4) /**< (SSC_WPMR) Write Protection Mode Register Offset */ +#define SSC_WPSR_REG_OFST (0xE8) /**< (SSC_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SSC register API structure */ +typedef struct +{ + __O uint32_t SSC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t SSC_CMR; /**< Offset: 0x04 (R/W 32) Clock Mode Register */ + __I uint8_t Reserved1[0x08]; + __IO uint32_t SSC_RCMR; /**< Offset: 0x10 (R/W 32) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< Offset: 0x14 (R/W 32) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< Offset: 0x18 (R/W 32) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< Offset: 0x1C (R/W 32) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< Offset: 0x20 (R/ 32) Receive Holding Register */ + __O uint32_t SSC_THR; /**< Offset: 0x24 ( /W 32) Transmit Holding Register */ + __I uint8_t Reserved2[0x08]; + __I uint32_t SSC_RSHR; /**< Offset: 0x30 (R/ 32) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< Offset: 0x34 (R/W 32) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< Offset: 0x38 (R/W 32) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< Offset: 0x3C (R/W 32) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< Offset: 0x40 (R/ 32) Status Register */ + __O uint32_t SSC_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ + __I uint8_t Reserved3[0x94]; + __IO uint32_t SSC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} ssc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SSC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/supc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/supc.h new file mode 100644 index 00000000..d3a3a2fb --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/supc.h @@ -0,0 +1,610 @@ +/** + * \brief Component description for SUPC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_SUPC_COMPONENT_H_ +#define _SAME70_SUPC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR SUPC */ +/* ************************************************************************** */ + +/* -------- SUPC_CR : (SUPC Offset: 0x00) ( /W 32) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF_Pos _U_(2) /**< (SUPC_CR) Voltage Regulator Off Position */ +#define SUPC_CR_VROFF_Msk (_U_(0x1) << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) Voltage Regulator Off Mask */ +#define SUPC_CR_VROFF(value) (SUPC_CR_VROFF_Msk & ((value) << SUPC_CR_VROFF_Pos)) +#define SUPC_CR_VROFF_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_VROFF_NO_EFFECT (SUPC_CR_VROFF_NO_EFFECT_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_VROFF_STOP_VREG (SUPC_CR_VROFF_STOP_VREG_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Position */ +#define SUPC_CR_XTALSEL_Pos _U_(3) /**< (SUPC_CR) Crystal Oscillator Select Position */ +#define SUPC_CR_XTALSEL_Msk (_U_(0x1) << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) Crystal Oscillator Select Mask */ +#define SUPC_CR_XTALSEL(value) (SUPC_CR_XTALSEL_Msk & ((value) << SUPC_CR_XTALSEL_Pos)) +#define SUPC_CR_XTALSEL_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_XTALSEL_NO_EFFECT (SUPC_CR_XTALSEL_NO_EFFECT_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) No effect. Position */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (SUPC_CR_XTALSEL_CRYSTAL_SEL_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Position */ +#define SUPC_CR_KEY_Pos _U_(24) /**< (SUPC_CR) Password Position */ +#define SUPC_CR_KEY_Msk (_U_(0xFF) << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Password Mask */ +#define SUPC_CR_KEY(value) (SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)) +#define SUPC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. */ +#define SUPC_CR_KEY_PASSWD (SUPC_CR_KEY_PASSWD_Val << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_CR_Msk _U_(0xFF00000C) /**< (SUPC_CR) Register Mask */ + + +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) (R/W 32) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos _U_(0) /**< (SUPC_SMMR) Supply Monitor Threshold Position */ +#define SUPC_SMMR_SMTH_Msk (_U_(0xF) << SUPC_SMMR_SMTH_Pos) /**< (SUPC_SMMR) Supply Monitor Threshold Mask */ +#define SUPC_SMMR_SMTH(value) (SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)) +#define SUPC_SMMR_SMSMPL_Pos _U_(8) /**< (SUPC_SMMR) Supply Monitor Sampling Period Position */ +#define SUPC_SMMR_SMSMPL_Msk (_U_(0x7) << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor Sampling Period Mask */ +#define SUPC_SMMR_SMSMPL(value) (SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)) +#define SUPC_SMMR_SMSMPL_SMD_Val _U_(0x0) /**< (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM_Val _U_(0x1) /**< (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK_Val _U_(0x2) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK_Val _U_(0x3) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK_Val _U_(0x4) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMSMPL_SMD (SUPC_SMMR_SMSMPL_SMD_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor disabled Position */ +#define SUPC_SMMR_SMSMPL_CSM (SUPC_SMMR_SMSMPL_CSM_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Continuous Supply Monitor Position */ +#define SUPC_SMMR_SMSMPL_32SLCK (SUPC_SMMR_SMSMPL_32SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_256SLCK (SUPC_SMMR_SMSMPL_256SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods Position */ +#define SUPC_SMMR_SMSMPL_2048SLCK (SUPC_SMMR_SMSMPL_2048SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods Position */ +#define SUPC_SMMR_SMRSTEN_Pos _U_(12) /**< (SUPC_SMMR) Supply Monitor Reset Enable Position */ +#define SUPC_SMMR_SMRSTEN_Msk (_U_(0x1) << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) Supply Monitor Reset Enable Mask */ +#define SUPC_SMMR_SMRSTEN(value) (SUPC_SMMR_SMRSTEN_Msk & ((value) << SUPC_SMMR_SMRSTEN_Pos)) +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMRSTEN_ENABLE (SUPC_SMMR_SMRSTEN_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_Pos _U_(13) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Position */ +#define SUPC_SMMR_SMIEN_Msk (_U_(0x1) << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Mask */ +#define SUPC_SMMR_SMIEN(value) (SUPC_SMMR_SMIEN_Msk & ((value) << SUPC_SMMR_SMIEN_Pos)) +#define SUPC_SMMR_SMIEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (SUPC_SMMR_SMIEN_NOT_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_SMIEN_ENABLE (SUPC_SMMR_SMIEN_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. Position */ +#define SUPC_SMMR_Msk _U_(0x0000370F) /**< (SUPC_SMMR) Register Mask */ + + +/* -------- SUPC_MR : (SUPC Offset: 0x08) (R/W 32) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN_Pos _U_(12) /**< (SUPC_MR) Brownout Detector Reset Enable Position */ +#define SUPC_MR_BODRSTEN_Msk (_U_(0x1) << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) Brownout Detector Reset Enable Mask */ +#define SUPC_MR_BODRSTEN(value) (SUPC_MR_BODRSTEN_Msk & ((value) << SUPC_MR_BODRSTEN_Pos)) +#define SUPC_MR_BODRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (SUPC_MR_BODRSTEN_NOT_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. Position */ +#define SUPC_MR_BODRSTEN_ENABLE (SUPC_MR_BODRSTEN_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Position */ +#define SUPC_MR_BODDIS_Pos _U_(13) /**< (SUPC_MR) Brownout Detector Disable Position */ +#define SUPC_MR_BODDIS_Msk (_U_(0x1) << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) Brownout Detector Disable Mask */ +#define SUPC_MR_BODDIS(value) (SUPC_MR_BODDIS_Msk & ((value) << SUPC_MR_BODDIS_Pos)) +#define SUPC_MR_BODDIS_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE_Val _U_(0x1) /**< (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_BODDIS_ENABLE (SUPC_MR_BODDIS_ENABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is enabled. Position */ +#define SUPC_MR_BODDIS_DISABLE (SUPC_MR_BODDIS_DISABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is disabled. Position */ +#define SUPC_MR_ONREG_Pos _U_(14) /**< (SUPC_MR) Voltage Regulator Enable Position */ +#define SUPC_MR_ONREG_Msk (_U_(0x1) << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Voltage Regulator Enable Mask */ +#define SUPC_MR_ONREG(value) (SUPC_MR_ONREG_Msk & ((value) << SUPC_MR_ONREG_Pos)) +#define SUPC_MR_ONREG_ONREG_UNUSED_Val _U_(0x0) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED_Val _U_(0x1) /**< (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_ONREG_ONREG_UNUSED (SUPC_MR_ONREG_ONREG_UNUSED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). Position */ +#define SUPC_MR_ONREG_ONREG_USED (SUPC_MR_ONREG_ONREG_USED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is used. Position */ +#define SUPC_MR_BKUPRETON_Pos _U_(17) /**< (SUPC_MR) SRAM On In Backup Mode Position */ +#define SUPC_MR_BKUPRETON_Msk (_U_(0x1) << SUPC_MR_BKUPRETON_Pos) /**< (SUPC_MR) SRAM On In Backup Mode Mask */ +#define SUPC_MR_BKUPRETON(value) (SUPC_MR_BKUPRETON_Msk & ((value) << SUPC_MR_BKUPRETON_Pos)) +#define SUPC_MR_OSCBYPASS_Pos _U_(20) /**< (SUPC_MR) Oscillator Bypass Position */ +#define SUPC_MR_OSCBYPASS_Msk (_U_(0x1) << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) Oscillator Bypass Mask */ +#define SUPC_MR_OSCBYPASS(value) (SUPC_MR_OSCBYPASS_Msk & ((value) << SUPC_MR_OSCBYPASS_Pos)) +#define SUPC_MR_OSCBYPASS_NO_EFFECT_Val _U_(0x0) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS_Val _U_(0x1) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (SUPC_MR_OSCBYPASS_NO_EFFECT_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). Position */ +#define SUPC_MR_OSCBYPASS_BYPASS (SUPC_MR_OSCBYPASS_BYPASS_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Position */ +#define SUPC_MR_KEY_Pos _U_(24) /**< (SUPC_MR) Password Key Position */ +#define SUPC_MR_KEY_Msk (_U_(0xFF) << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Password Key Mask */ +#define SUPC_MR_KEY(value) (SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)) +#define SUPC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. */ +#define SUPC_MR_KEY_PASSWD (SUPC_MR_KEY_PASSWD_Val << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. Position */ +#define SUPC_MR_Msk _U_(0xFF127000) /**< (SUPC_MR) Register Mask */ + + +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) (R/W 32) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN_Pos _U_(1) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Position */ +#define SUPC_WUMR_SMEN_Msk (_U_(0x1) << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) Supply Monitor Wake-up Enable Mask */ +#define SUPC_WUMR_SMEN(value) (SUPC_WUMR_SMEN_Msk & ((value) << SUPC_WUMR_SMEN_Pos)) +#define SUPC_WUMR_SMEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (SUPC_WUMR_SMEN_NOT_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection has no wake-up effect. Position */ +#define SUPC_WUMR_SMEN_ENABLE (SUPC_WUMR_SMEN_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTTEN_Pos _U_(2) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Position */ +#define SUPC_WUMR_RTTEN_Msk (_U_(0x1) << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) Real-time Timer Wake-up Enable Mask */ +#define SUPC_WUMR_RTTEN(value) (SUPC_WUMR_RTTEN_Msk & ((value) << SUPC_WUMR_RTTEN_Pos)) +#define SUPC_WUMR_RTTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (SUPC_WUMR_RTTEN_NOT_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTTEN_ENABLE (SUPC_WUMR_RTTEN_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_RTCEN_Pos _U_(3) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Position */ +#define SUPC_WUMR_RTCEN_Msk (_U_(0x1) << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) Real-time Clock Wake-up Enable Mask */ +#define SUPC_WUMR_RTCEN(value) (SUPC_WUMR_RTCEN_Msk & ((value) << SUPC_WUMR_RTCEN_Pos)) +#define SUPC_WUMR_RTCEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (SUPC_WUMR_RTCEN_NOT_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal has no wake-up effect. Position */ +#define SUPC_WUMR_RTCEN_ENABLE (SUPC_WUMR_RTCEN_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. Position */ +#define SUPC_WUMR_LPDBCEN0_Pos _U_(5) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Position */ +#define SUPC_WUMR_LPDBCEN0_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Mask */ +#define SUPC_WUMR_LPDBCEN0(value) (SUPC_WUMR_LPDBCEN0_Msk & ((value) << SUPC_WUMR_LPDBCEN0_Pos)) +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (SUPC_WUMR_LPDBCEN0_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCEN1_Pos _U_(6) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Position */ +#define SUPC_WUMR_LPDBCEN1_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Mask */ +#define SUPC_WUMR_LPDBCEN1(value) (SUPC_WUMR_LPDBCEN1_Msk & ((value) << SUPC_WUMR_LPDBCEN1_Pos)) +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. Position */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (SUPC_WUMR_LPDBCEN1_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. Position */ +#define SUPC_WUMR_LPDBCCLR_Pos _U_(7) /**< (SUPC_WUMR) Low-power Debouncer Clear Position */ +#define SUPC_WUMR_LPDBCCLR_Msk (_U_(0x1) << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) Low-power Debouncer Clear Mask */ +#define SUPC_WUMR_LPDBCCLR(value) (SUPC_WUMR_LPDBCCLR_Msk & ((value) << SUPC_WUMR_LPDBCCLR_Pos)) +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (SUPC_WUMR_LPDBCCLR_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. Position */ +#define SUPC_WUMR_WKUPDBC_Pos _U_(12) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Position */ +#define SUPC_WUMR_WKUPDBC_Msk (_U_(0x7) << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Wake-up Inputs Debouncer Period Mask */ +#define SUPC_WUMR_WKUPDBC(value) (SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE_Val _U_(0x0) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK_Val _U_(0x1) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK_Val _U_(0x2) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK_Val _U_(0x3) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK_Val _U_(0x4) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK_Val _U_(0x5) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (SUPC_WUMR_WKUPDBC_IMMEDIATE_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. Position */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (SUPC_WUMR_WKUPDBC_3_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (SUPC_WUMR_WKUPDBC_32_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (SUPC_WUMR_WKUPDBC_512_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (SUPC_WUMR_WKUPDBC_4096_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods Position */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (SUPC_WUMR_WKUPDBC_32768_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods Position */ +#define SUPC_WUMR_LPDBC_Pos _U_(16) /**< (SUPC_WUMR) Low-power Debouncer Period Position */ +#define SUPC_WUMR_LPDBC_Msk (_U_(0x7) << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Low-power Debouncer Period Mask */ +#define SUPC_WUMR_LPDBC(value) (SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)) +#define SUPC_WUMR_LPDBC_DISABLE_Val _U_(0x0) /**< (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT_Val _U_(0x1) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT_Val _U_(0x2) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT_Val _U_(0x3) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT_Val _U_(0x4) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT_Val _U_(0x5) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT_Val _U_(0x6) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT_Val _U_(0x7) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_DISABLE (SUPC_WUMR_LPDBC_DISABLE_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Disable the low-power debouncers. Position */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (SUPC_WUMR_LPDBC_2_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (SUPC_WUMR_LPDBC_3_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (SUPC_WUMR_LPDBC_4_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (SUPC_WUMR_LPDBC_5_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (SUPC_WUMR_LPDBC_6_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (SUPC_WUMR_LPDBC_7_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods Position */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (SUPC_WUMR_LPDBC_8_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods Position */ +#define SUPC_WUMR_Msk _U_(0x000770EE) /**< (SUPC_WUMR) Register Mask */ + +#define SUPC_WUMR_LPDBCEN_Pos _U_(5) /**< (SUPC_WUMR Position) Low-power Debouncer Enable WKUPx */ +#define SUPC_WUMR_LPDBCEN_Msk (_U_(0x3) << SUPC_WUMR_LPDBCEN_Pos) /**< (SUPC_WUMR Mask) LPDBCEN */ +#define SUPC_WUMR_LPDBCEN(value) (SUPC_WUMR_LPDBCEN_Msk & ((value) << SUPC_WUMR_LPDBCEN_Pos)) + +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) (R/W 32) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0_Pos _U_(0) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Position */ +#define SUPC_WUIR_WKUPEN0_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 0 Mask */ +#define SUPC_WUIR_WKUPEN0(value) (SUPC_WUIR_WKUPEN0_Msk & ((value) << SUPC_WUIR_WKUPEN0_Pos)) +#define SUPC_WUIR_WKUPEN0_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN0_DISABLE (SUPC_WUIR_WKUPEN0_DISABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN0_ENABLE (SUPC_WUIR_WKUPEN0_ENABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN1_Pos _U_(1) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Position */ +#define SUPC_WUIR_WKUPEN1_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 1 Mask */ +#define SUPC_WUIR_WKUPEN1(value) (SUPC_WUIR_WKUPEN1_Msk & ((value) << SUPC_WUIR_WKUPEN1_Pos)) +#define SUPC_WUIR_WKUPEN1_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1_DISABLE (SUPC_WUIR_WKUPEN1_DISABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN1_ENABLE (SUPC_WUIR_WKUPEN1_ENABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN2_Pos _U_(2) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Position */ +#define SUPC_WUIR_WKUPEN2_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 2 Mask */ +#define SUPC_WUIR_WKUPEN2(value) (SUPC_WUIR_WKUPEN2_Msk & ((value) << SUPC_WUIR_WKUPEN2_Pos)) +#define SUPC_WUIR_WKUPEN2_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2_DISABLE (SUPC_WUIR_WKUPEN2_DISABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN2_ENABLE (SUPC_WUIR_WKUPEN2_ENABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN3_Pos _U_(3) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Position */ +#define SUPC_WUIR_WKUPEN3_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 3 Mask */ +#define SUPC_WUIR_WKUPEN3(value) (SUPC_WUIR_WKUPEN3_Msk & ((value) << SUPC_WUIR_WKUPEN3_Pos)) +#define SUPC_WUIR_WKUPEN3_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3_DISABLE (SUPC_WUIR_WKUPEN3_DISABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN3_ENABLE (SUPC_WUIR_WKUPEN3_ENABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN4_Pos _U_(4) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Position */ +#define SUPC_WUIR_WKUPEN4_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 4 Mask */ +#define SUPC_WUIR_WKUPEN4(value) (SUPC_WUIR_WKUPEN4_Msk & ((value) << SUPC_WUIR_WKUPEN4_Pos)) +#define SUPC_WUIR_WKUPEN4_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4_DISABLE (SUPC_WUIR_WKUPEN4_DISABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN4_ENABLE (SUPC_WUIR_WKUPEN4_ENABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN5_Pos _U_(5) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Position */ +#define SUPC_WUIR_WKUPEN5_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 5 Mask */ +#define SUPC_WUIR_WKUPEN5(value) (SUPC_WUIR_WKUPEN5_Msk & ((value) << SUPC_WUIR_WKUPEN5_Pos)) +#define SUPC_WUIR_WKUPEN5_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5_DISABLE (SUPC_WUIR_WKUPEN5_DISABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN5_ENABLE (SUPC_WUIR_WKUPEN5_ENABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN6_Pos _U_(6) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Position */ +#define SUPC_WUIR_WKUPEN6_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 6 Mask */ +#define SUPC_WUIR_WKUPEN6(value) (SUPC_WUIR_WKUPEN6_Msk & ((value) << SUPC_WUIR_WKUPEN6_Pos)) +#define SUPC_WUIR_WKUPEN6_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6_DISABLE (SUPC_WUIR_WKUPEN6_DISABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN6_ENABLE (SUPC_WUIR_WKUPEN6_ENABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN7_Pos _U_(7) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Position */ +#define SUPC_WUIR_WKUPEN7_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 7 Mask */ +#define SUPC_WUIR_WKUPEN7(value) (SUPC_WUIR_WKUPEN7_Msk & ((value) << SUPC_WUIR_WKUPEN7_Pos)) +#define SUPC_WUIR_WKUPEN7_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7_DISABLE (SUPC_WUIR_WKUPEN7_DISABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN7_ENABLE (SUPC_WUIR_WKUPEN7_ENABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN8_Pos _U_(8) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Position */ +#define SUPC_WUIR_WKUPEN8_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 8 Mask */ +#define SUPC_WUIR_WKUPEN8(value) (SUPC_WUIR_WKUPEN8_Msk & ((value) << SUPC_WUIR_WKUPEN8_Pos)) +#define SUPC_WUIR_WKUPEN8_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8_DISABLE (SUPC_WUIR_WKUPEN8_DISABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN8_ENABLE (SUPC_WUIR_WKUPEN8_ENABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN9_Pos _U_(9) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Position */ +#define SUPC_WUIR_WKUPEN9_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 9 Mask */ +#define SUPC_WUIR_WKUPEN9(value) (SUPC_WUIR_WKUPEN9_Msk & ((value) << SUPC_WUIR_WKUPEN9_Pos)) +#define SUPC_WUIR_WKUPEN9_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9_DISABLE (SUPC_WUIR_WKUPEN9_DISABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN9_ENABLE (SUPC_WUIR_WKUPEN9_ENABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN10_Pos _U_(10) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Position */ +#define SUPC_WUIR_WKUPEN10_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 10 Mask */ +#define SUPC_WUIR_WKUPEN10(value) (SUPC_WUIR_WKUPEN10_Msk & ((value) << SUPC_WUIR_WKUPEN10_Pos)) +#define SUPC_WUIR_WKUPEN10_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10_DISABLE (SUPC_WUIR_WKUPEN10_DISABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN10_ENABLE (SUPC_WUIR_WKUPEN10_ENABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN11_Pos _U_(11) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Position */ +#define SUPC_WUIR_WKUPEN11_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 11 Mask */ +#define SUPC_WUIR_WKUPEN11(value) (SUPC_WUIR_WKUPEN11_Msk & ((value) << SUPC_WUIR_WKUPEN11_Pos)) +#define SUPC_WUIR_WKUPEN11_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11_DISABLE (SUPC_WUIR_WKUPEN11_DISABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN11_ENABLE (SUPC_WUIR_WKUPEN11_ENABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN12_Pos _U_(12) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Position */ +#define SUPC_WUIR_WKUPEN12_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 12 Mask */ +#define SUPC_WUIR_WKUPEN12(value) (SUPC_WUIR_WKUPEN12_Msk & ((value) << SUPC_WUIR_WKUPEN12_Pos)) +#define SUPC_WUIR_WKUPEN12_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12_DISABLE (SUPC_WUIR_WKUPEN12_DISABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN12_ENABLE (SUPC_WUIR_WKUPEN12_ENABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPEN13_Pos _U_(13) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Position */ +#define SUPC_WUIR_WKUPEN13_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) Wake-up Input Enable 0 to 13 Mask */ +#define SUPC_WUIR_WKUPEN13(value) (SUPC_WUIR_WKUPEN13_Msk & ((value) << SUPC_WUIR_WKUPEN13_Pos)) +#define SUPC_WUIR_WKUPEN13_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13_DISABLE (SUPC_WUIR_WKUPEN13_DISABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. Position */ +#define SUPC_WUIR_WKUPEN13_ENABLE (SUPC_WUIR_WKUPEN13_ENABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_Pos _U_(16) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Position */ +#define SUPC_WUIR_WKUPT0_Msk (_U_(0x1) << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 0 Mask */ +#define SUPC_WUIR_WKUPT0(value) (SUPC_WUIR_WKUPT0_Msk & ((value) << SUPC_WUIR_WKUPT0_Pos)) +#define SUPC_WUIR_WKUPT0_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW (SUPC_WUIR_WKUPT0_LOW_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT0_HIGH (SUPC_WUIR_WKUPT0_HIGH_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_Pos _U_(17) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Position */ +#define SUPC_WUIR_WKUPT1_Msk (_U_(0x1) << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 1 Mask */ +#define SUPC_WUIR_WKUPT1(value) (SUPC_WUIR_WKUPT1_Msk & ((value) << SUPC_WUIR_WKUPT1_Pos)) +#define SUPC_WUIR_WKUPT1_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW (SUPC_WUIR_WKUPT1_LOW_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT1_HIGH (SUPC_WUIR_WKUPT1_HIGH_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_Pos _U_(18) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Position */ +#define SUPC_WUIR_WKUPT2_Msk (_U_(0x1) << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 2 Mask */ +#define SUPC_WUIR_WKUPT2(value) (SUPC_WUIR_WKUPT2_Msk & ((value) << SUPC_WUIR_WKUPT2_Pos)) +#define SUPC_WUIR_WKUPT2_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW (SUPC_WUIR_WKUPT2_LOW_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT2_HIGH (SUPC_WUIR_WKUPT2_HIGH_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_Pos _U_(19) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Position */ +#define SUPC_WUIR_WKUPT3_Msk (_U_(0x1) << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 3 Mask */ +#define SUPC_WUIR_WKUPT3(value) (SUPC_WUIR_WKUPT3_Msk & ((value) << SUPC_WUIR_WKUPT3_Pos)) +#define SUPC_WUIR_WKUPT3_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW (SUPC_WUIR_WKUPT3_LOW_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT3_HIGH (SUPC_WUIR_WKUPT3_HIGH_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_Pos _U_(20) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Position */ +#define SUPC_WUIR_WKUPT4_Msk (_U_(0x1) << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 4 Mask */ +#define SUPC_WUIR_WKUPT4(value) (SUPC_WUIR_WKUPT4_Msk & ((value) << SUPC_WUIR_WKUPT4_Pos)) +#define SUPC_WUIR_WKUPT4_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW (SUPC_WUIR_WKUPT4_LOW_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT4_HIGH (SUPC_WUIR_WKUPT4_HIGH_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_Pos _U_(21) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Position */ +#define SUPC_WUIR_WKUPT5_Msk (_U_(0x1) << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 5 Mask */ +#define SUPC_WUIR_WKUPT5(value) (SUPC_WUIR_WKUPT5_Msk & ((value) << SUPC_WUIR_WKUPT5_Pos)) +#define SUPC_WUIR_WKUPT5_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW (SUPC_WUIR_WKUPT5_LOW_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT5_HIGH (SUPC_WUIR_WKUPT5_HIGH_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_Pos _U_(22) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Position */ +#define SUPC_WUIR_WKUPT6_Msk (_U_(0x1) << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 6 Mask */ +#define SUPC_WUIR_WKUPT6(value) (SUPC_WUIR_WKUPT6_Msk & ((value) << SUPC_WUIR_WKUPT6_Pos)) +#define SUPC_WUIR_WKUPT6_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW (SUPC_WUIR_WKUPT6_LOW_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT6_HIGH (SUPC_WUIR_WKUPT6_HIGH_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_Pos _U_(23) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Position */ +#define SUPC_WUIR_WKUPT7_Msk (_U_(0x1) << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 7 Mask */ +#define SUPC_WUIR_WKUPT7(value) (SUPC_WUIR_WKUPT7_Msk & ((value) << SUPC_WUIR_WKUPT7_Pos)) +#define SUPC_WUIR_WKUPT7_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW (SUPC_WUIR_WKUPT7_LOW_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT7_HIGH (SUPC_WUIR_WKUPT7_HIGH_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_Pos _U_(24) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Position */ +#define SUPC_WUIR_WKUPT8_Msk (_U_(0x1) << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 8 Mask */ +#define SUPC_WUIR_WKUPT8(value) (SUPC_WUIR_WKUPT8_Msk & ((value) << SUPC_WUIR_WKUPT8_Pos)) +#define SUPC_WUIR_WKUPT8_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW (SUPC_WUIR_WKUPT8_LOW_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT8_HIGH (SUPC_WUIR_WKUPT8_HIGH_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_Pos _U_(25) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Position */ +#define SUPC_WUIR_WKUPT9_Msk (_U_(0x1) << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 9 Mask */ +#define SUPC_WUIR_WKUPT9(value) (SUPC_WUIR_WKUPT9_Msk & ((value) << SUPC_WUIR_WKUPT9_Pos)) +#define SUPC_WUIR_WKUPT9_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW (SUPC_WUIR_WKUPT9_LOW_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT9_HIGH (SUPC_WUIR_WKUPT9_HIGH_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_Pos _U_(26) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Position */ +#define SUPC_WUIR_WKUPT10_Msk (_U_(0x1) << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 10 Mask */ +#define SUPC_WUIR_WKUPT10(value) (SUPC_WUIR_WKUPT10_Msk & ((value) << SUPC_WUIR_WKUPT10_Pos)) +#define SUPC_WUIR_WKUPT10_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW (SUPC_WUIR_WKUPT10_LOW_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT10_HIGH (SUPC_WUIR_WKUPT10_HIGH_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_Pos _U_(27) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Position */ +#define SUPC_WUIR_WKUPT11_Msk (_U_(0x1) << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 11 Mask */ +#define SUPC_WUIR_WKUPT11(value) (SUPC_WUIR_WKUPT11_Msk & ((value) << SUPC_WUIR_WKUPT11_Pos)) +#define SUPC_WUIR_WKUPT11_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW (SUPC_WUIR_WKUPT11_LOW_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT11_HIGH (SUPC_WUIR_WKUPT11_HIGH_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_Pos _U_(28) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Position */ +#define SUPC_WUIR_WKUPT12_Msk (_U_(0x1) << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 12 Mask */ +#define SUPC_WUIR_WKUPT12(value) (SUPC_WUIR_WKUPT12_Msk & ((value) << SUPC_WUIR_WKUPT12_Pos)) +#define SUPC_WUIR_WKUPT12_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW (SUPC_WUIR_WKUPT12_LOW_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT12_HIGH (SUPC_WUIR_WKUPT12_HIGH_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_Pos _U_(29) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Position */ +#define SUPC_WUIR_WKUPT13_Msk (_U_(0x1) << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) Wake-up Input Type 0 to 13 Mask */ +#define SUPC_WUIR_WKUPT13(value) (SUPC_WUIR_WKUPT13_Msk & ((value) << SUPC_WUIR_WKUPT13_Pos)) +#define SUPC_WUIR_WKUPT13_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW (SUPC_WUIR_WKUPT13_LOW_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_WKUPT13_HIGH (SUPC_WUIR_WKUPT13_HIGH_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. Position */ +#define SUPC_WUIR_Msk _U_(0x3FFF3FFF) /**< (SUPC_WUIR) Register Mask */ + +#define SUPC_WUIR_WKUPEN_Pos _U_(0) /**< (SUPC_WUIR Position) Wake-up Input Enable x to x */ +#define SUPC_WUIR_WKUPEN_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPEN_Pos) /**< (SUPC_WUIR Mask) WKUPEN */ +#define SUPC_WUIR_WKUPEN(value) (SUPC_WUIR_WKUPEN_Msk & ((value) << SUPC_WUIR_WKUPEN_Pos)) +#define SUPC_WUIR_WKUPT_Pos _U_(16) /**< (SUPC_WUIR Position) Wake-up Input Type x to x3 */ +#define SUPC_WUIR_WKUPT_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPT_Pos) /**< (SUPC_WUIR Mask) WKUPT */ +#define SUPC_WUIR_WKUPT(value) (SUPC_WUIR_WKUPT_Msk & ((value) << SUPC_WUIR_WKUPT_Pos)) + +/* -------- SUPC_SR : (SUPC Offset: 0x14) ( R/ 32) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS_Pos _U_(1) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Position */ +#define SUPC_SR_WKUPS_Msk (_U_(0x1) << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) WKUP Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_WKUPS(value) (SUPC_SR_WKUPS_Msk & ((value) << SUPC_SR_WKUPS_Pos)) +#define SUPC_SR_WKUPS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_NO (SUPC_SR_WKUPS_NO_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPS_PRESENT (SUPC_SR_WKUPS_PRESENT_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_Pos _U_(2) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Position */ +#define SUPC_SR_SMWS_Msk (_U_(0x1) << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) Mask */ +#define SUPC_SR_SMWS(value) (SUPC_SR_SMWS_Msk & ((value) << SUPC_SR_SMWS_Pos)) +#define SUPC_SR_SMWS_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_NO (SUPC_SR_SMWS_NO_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMWS_PRESENT (SUPC_SR_SMWS_PRESENT_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_Pos _U_(3) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Position */ +#define SUPC_SR_BODRSTS_Msk (_U_(0x1) << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Mask */ +#define SUPC_SR_BODRSTS(value) (SUPC_SR_BODRSTS_Msk & ((value) << SUPC_SR_BODRSTS_Pos)) +#define SUPC_SR_BODRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_NO (SUPC_SR_BODRSTS_NO_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_BODRSTS_PRESENT (SUPC_SR_BODRSTS_PRESENT_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_Pos _U_(4) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Position */ +#define SUPC_SR_SMRSTS_Msk (_U_(0x1) << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Mask */ +#define SUPC_SR_SMRSTS(value) (SUPC_SR_SMRSTS_Msk & ((value) << SUPC_SR_SMRSTS_Pos)) +#define SUPC_SR_SMRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_NO (SUPC_SR_SMRSTS_NO_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMRSTS_PRESENT (SUPC_SR_SMRSTS_PRESENT_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ +#define SUPC_SR_SMS_Pos _U_(5) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Position */ +#define SUPC_SR_SMS_Msk (_U_(0x1) << SUPC_SR_SMS_Pos) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Mask */ +#define SUPC_SR_SMS(value) (SUPC_SR_SMS_Msk & ((value) << SUPC_SR_SMS_Pos)) +#define SUPC_SR_SMS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_NO (SUPC_SR_SMS_NO_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMS_PRESENT (SUPC_SR_SMS_PRESENT_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. Position */ +#define SUPC_SR_SMOS_Pos _U_(6) /**< (SUPC_SR) Supply Monitor Output Status Position */ +#define SUPC_SR_SMOS_Msk (_U_(0x1) << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) Supply Monitor Output Status Mask */ +#define SUPC_SR_SMOS(value) (SUPC_SR_SMOS_Msk & ((value) << SUPC_SR_SMOS_Pos)) +#define SUPC_SR_SMOS_HIGH_Val _U_(0x0) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW_Val _U_(0x1) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_HIGH (SUPC_SR_SMOS_HIGH_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. Position */ +#define SUPC_SR_SMOS_LOW (SUPC_SR_SMOS_LOW_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. Position */ +#define SUPC_SR_OSCSEL_Pos _U_(7) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Position */ +#define SUPC_SR_OSCSEL_Msk (_U_(0x1) << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Mask */ +#define SUPC_SR_OSCSEL(value) (SUPC_SR_OSCSEL_Msk & ((value) << SUPC_SR_OSCSEL_Pos)) +#define SUPC_SR_OSCSEL_RC_Val _U_(0x0) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST_Val _U_(0x1) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_OSCSEL_RC (SUPC_SR_OSCSEL_RC_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. Position */ +#define SUPC_SR_OSCSEL_CRYST (SUPC_SR_OSCSEL_CRYST_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. Position */ +#define SUPC_SR_LPDBCS0_Pos _U_(13) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Position */ +#define SUPC_SR_LPDBCS0_Msk (_U_(0x1) << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS0(value) (SUPC_SR_LPDBCS0_Msk & ((value) << SUPC_SR_LPDBCS0_Pos)) +#define SUPC_SR_LPDBCS0_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_NO (SUPC_SR_LPDBCS0_NO_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS0_PRESENT (SUPC_SR_LPDBCS0_PRESENT_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_Pos _U_(14) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Position */ +#define SUPC_SR_LPDBCS1_Msk (_U_(0x1) << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) Mask */ +#define SUPC_SR_LPDBCS1(value) (SUPC_SR_LPDBCS1_Msk & ((value) << SUPC_SR_LPDBCS1_Pos)) +#define SUPC_SR_LPDBCS1_NO_Val _U_(0x0) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_NO (SUPC_SR_LPDBCS1_NO_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_LPDBCS1_PRESENT (SUPC_SR_LPDBCS1_PRESENT_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS0_Pos _U_(16) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS0_Msk (_U_(0x1) << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS0(value) (SUPC_SR_WKUPIS0_Msk & ((value) << SUPC_SR_WKUPIS0_Pos)) +#define SUPC_SR_WKUPIS0_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0_DIS (SUPC_SR_WKUPIS0_DIS_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS0_EN (SUPC_SR_WKUPIS0_EN_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS1_Pos _U_(17) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS1_Msk (_U_(0x1) << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS1(value) (SUPC_SR_WKUPIS1_Msk & ((value) << SUPC_SR_WKUPIS1_Pos)) +#define SUPC_SR_WKUPIS1_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1_DIS (SUPC_SR_WKUPIS1_DIS_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS1_EN (SUPC_SR_WKUPIS1_EN_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS2_Pos _U_(18) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS2_Msk (_U_(0x1) << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS2(value) (SUPC_SR_WKUPIS2_Msk & ((value) << SUPC_SR_WKUPIS2_Pos)) +#define SUPC_SR_WKUPIS2_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2_DIS (SUPC_SR_WKUPIS2_DIS_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS2_EN (SUPC_SR_WKUPIS2_EN_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS3_Pos _U_(19) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS3_Msk (_U_(0x1) << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS3(value) (SUPC_SR_WKUPIS3_Msk & ((value) << SUPC_SR_WKUPIS3_Pos)) +#define SUPC_SR_WKUPIS3_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3_DIS (SUPC_SR_WKUPIS3_DIS_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS3_EN (SUPC_SR_WKUPIS3_EN_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS4_Pos _U_(20) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS4_Msk (_U_(0x1) << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS4(value) (SUPC_SR_WKUPIS4_Msk & ((value) << SUPC_SR_WKUPIS4_Pos)) +#define SUPC_SR_WKUPIS4_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4_DIS (SUPC_SR_WKUPIS4_DIS_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS4_EN (SUPC_SR_WKUPIS4_EN_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS5_Pos _U_(21) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS5_Msk (_U_(0x1) << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS5(value) (SUPC_SR_WKUPIS5_Msk & ((value) << SUPC_SR_WKUPIS5_Pos)) +#define SUPC_SR_WKUPIS5_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5_DIS (SUPC_SR_WKUPIS5_DIS_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS5_EN (SUPC_SR_WKUPIS5_EN_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS6_Pos _U_(22) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS6_Msk (_U_(0x1) << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS6(value) (SUPC_SR_WKUPIS6_Msk & ((value) << SUPC_SR_WKUPIS6_Pos)) +#define SUPC_SR_WKUPIS6_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6_DIS (SUPC_SR_WKUPIS6_DIS_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS6_EN (SUPC_SR_WKUPIS6_EN_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS7_Pos _U_(23) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS7_Msk (_U_(0x1) << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS7(value) (SUPC_SR_WKUPIS7_Msk & ((value) << SUPC_SR_WKUPIS7_Pos)) +#define SUPC_SR_WKUPIS7_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7_DIS (SUPC_SR_WKUPIS7_DIS_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS7_EN (SUPC_SR_WKUPIS7_EN_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS8_Pos _U_(24) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS8_Msk (_U_(0x1) << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS8(value) (SUPC_SR_WKUPIS8_Msk & ((value) << SUPC_SR_WKUPIS8_Pos)) +#define SUPC_SR_WKUPIS8_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8_DIS (SUPC_SR_WKUPIS8_DIS_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS8_EN (SUPC_SR_WKUPIS8_EN_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS9_Pos _U_(25) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS9_Msk (_U_(0x1) << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS9(value) (SUPC_SR_WKUPIS9_Msk & ((value) << SUPC_SR_WKUPIS9_Pos)) +#define SUPC_SR_WKUPIS9_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9_DIS (SUPC_SR_WKUPIS9_DIS_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS9_EN (SUPC_SR_WKUPIS9_EN_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS10_Pos _U_(26) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS10_Msk (_U_(0x1) << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS10(value) (SUPC_SR_WKUPIS10_Msk & ((value) << SUPC_SR_WKUPIS10_Pos)) +#define SUPC_SR_WKUPIS10_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10_DIS (SUPC_SR_WKUPIS10_DIS_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS10_EN (SUPC_SR_WKUPIS10_EN_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS11_Pos _U_(27) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS11_Msk (_U_(0x1) << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS11(value) (SUPC_SR_WKUPIS11_Msk & ((value) << SUPC_SR_WKUPIS11_Pos)) +#define SUPC_SR_WKUPIS11_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11_DIS (SUPC_SR_WKUPIS11_DIS_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS11_EN (SUPC_SR_WKUPIS11_EN_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS12_Pos _U_(28) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS12_Msk (_U_(0x1) << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS12(value) (SUPC_SR_WKUPIS12_Msk & ((value) << SUPC_SR_WKUPIS12_Pos)) +#define SUPC_SR_WKUPIS12_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12_DIS (SUPC_SR_WKUPIS12_DIS_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS12_EN (SUPC_SR_WKUPIS12_EN_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_WKUPIS13_Pos _U_(29) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ +#define SUPC_SR_WKUPIS13_Msk (_U_(0x1) << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ +#define SUPC_SR_WKUPIS13(value) (SUPC_SR_WKUPIS13_Msk & ((value) << SUPC_SR_WKUPIS13_Pos)) +#define SUPC_SR_WKUPIS13_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13_DIS (SUPC_SR_WKUPIS13_DIS_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. Position */ +#define SUPC_SR_WKUPIS13_EN (SUPC_SR_WKUPIS13_EN_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. Position */ +#define SUPC_SR_Msk _U_(0x3FFF60FE) /**< (SUPC_SR) Register Mask */ + +#define SUPC_SR_LPDBCS_Pos _U_(13) /**< (SUPC_SR Position) Low-power Debouncer Wake-up Status on WKUPx (cleared on read) */ +#define SUPC_SR_LPDBCS_Msk (_U_(0x3) << SUPC_SR_LPDBCS_Pos) /**< (SUPC_SR Mask) LPDBCS */ +#define SUPC_SR_LPDBCS(value) (SUPC_SR_LPDBCS_Msk & ((value) << SUPC_SR_LPDBCS_Pos)) +#define SUPC_SR_WKUPIS_Pos _U_(16) /**< (SUPC_SR Position) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS_Msk (_U_(0x3FFF) << SUPC_SR_WKUPIS_Pos) /**< (SUPC_SR Mask) WKUPIS */ +#define SUPC_SR_WKUPIS(value) (SUPC_SR_WKUPIS_Msk & ((value) << SUPC_SR_WKUPIS_Pos)) + +/** \brief SUPC register offsets definitions */ +#define SUPC_CR_REG_OFST (0x00) /**< (SUPC_CR) Supply Controller Control Register Offset */ +#define SUPC_SMMR_REG_OFST (0x04) /**< (SUPC_SMMR) Supply Controller Supply Monitor Mode Register Offset */ +#define SUPC_MR_REG_OFST (0x08) /**< (SUPC_MR) Supply Controller Mode Register Offset */ +#define SUPC_WUMR_REG_OFST (0x0C) /**< (SUPC_WUMR) Supply Controller Wake-up Mode Register Offset */ +#define SUPC_WUIR_REG_OFST (0x10) /**< (SUPC_WUIR) Supply Controller Wake-up Inputs Register Offset */ +#define SUPC_SR_REG_OFST (0x14) /**< (SUPC_SR) Supply Controller Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SUPC register API structure */ +typedef struct +{ + __O uint32_t SUPC_CR; /**< Offset: 0x00 ( /W 32) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< Offset: 0x04 (R/W 32) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< Offset: 0x08 (R/W 32) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< Offset: 0x0C (R/W 32) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< Offset: 0x10 (R/W 32) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< Offset: 0x14 (R/ 32) Supply Controller Status Register */ +} supc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_SUPC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/tc.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/tc.h new file mode 100644 index 00000000..d4c205fa --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/tc.h @@ -0,0 +1,696 @@ +/** + * \brief Component description for TC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_TC_COMPONENT_H_ +#define _SAME70_TC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TC */ +/* ************************************************************************** */ + +/* -------- TC_CCR : (TC Offset: 0x00) ( /W 32) Channel Control Register (channel = 0) -------- */ +#define TC_CCR_CLKEN_Pos _U_(0) /**< (TC_CCR) Counter Clock Enable Command Position */ +#define TC_CCR_CLKEN_Msk (_U_(0x1) << TC_CCR_CLKEN_Pos) /**< (TC_CCR) Counter Clock Enable Command Mask */ +#define TC_CCR_CLKEN(value) (TC_CCR_CLKEN_Msk & ((value) << TC_CCR_CLKEN_Pos)) +#define TC_CCR_CLKDIS_Pos _U_(1) /**< (TC_CCR) Counter Clock Disable Command Position */ +#define TC_CCR_CLKDIS_Msk (_U_(0x1) << TC_CCR_CLKDIS_Pos) /**< (TC_CCR) Counter Clock Disable Command Mask */ +#define TC_CCR_CLKDIS(value) (TC_CCR_CLKDIS_Msk & ((value) << TC_CCR_CLKDIS_Pos)) +#define TC_CCR_SWTRG_Pos _U_(2) /**< (TC_CCR) Software Trigger Command Position */ +#define TC_CCR_SWTRG_Msk (_U_(0x1) << TC_CCR_SWTRG_Pos) /**< (TC_CCR) Software Trigger Command Mask */ +#define TC_CCR_SWTRG(value) (TC_CCR_SWTRG_Msk & ((value) << TC_CCR_SWTRG_Pos)) +#define TC_CCR_Msk _U_(0x00000007) /**< (TC_CCR) Register Mask */ + + +/* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) Channel Mode Register (channel = 0) -------- */ +#define TC_CMR_TCCLKS_Pos _U_(0) /**< (TC_CMR) Clock Selection Position */ +#define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock Selection Mask */ +#define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) +#define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) Position */ +#define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC0 Position */ +#define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC1 Position */ +#define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) /**< (TC_CMR) Clock selected: XC2 Position */ +#define TC_CMR_CLKI_Pos _U_(3) /**< (TC_CMR) Clock Invert Position */ +#define TC_CMR_CLKI_Msk (_U_(0x1) << TC_CMR_CLKI_Pos) /**< (TC_CMR) Clock Invert Mask */ +#define TC_CMR_CLKI(value) (TC_CMR_CLKI_Msk & ((value) << TC_CMR_CLKI_Pos)) +#define TC_CMR_BURST_Pos _U_(4) /**< (TC_CMR) Burst Signal Selection Position */ +#define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) /**< (TC_CMR) Burst Signal Selection Mask */ +#define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) +#define TC_CMR_BURST_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_BURST_NONE (TC_CMR_BURST_NONE_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ +#define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ +#define TC_CMR_WAVE_Pos _U_(15) /**< (TC_CMR) Waveform Mode Position */ +#define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ +#define TC_CMR_WAVE(value) (TC_CMR_WAVE_Msk & ((value) << TC_CMR_WAVE_Pos)) +#define TC_CMR_Msk _U_(0x0000803F) /**< (TC_CMR) Register Mask */ + +/* CAPTURE mode */ +#define TC_CMR_CAPTURE_LDBSTOP_Pos _U_(6) /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ +#define TC_CMR_CAPTURE_LDBSTOP_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ +#define TC_CMR_CAPTURE_LDBSTOP(value) (TC_CMR_CAPTURE_LDBSTOP_Msk & ((value) << TC_CMR_CAPTURE_LDBSTOP_Pos)) +#define TC_CMR_CAPTURE_LDBDIS_Pos _U_(7) /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ +#define TC_CMR_CAPTURE_LDBDIS_Msk (_U_(0x1) << TC_CMR_CAPTURE_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ +#define TC_CMR_CAPTURE_LDBDIS(value) (TC_CMR_CAPTURE_LDBDIS_Msk & ((value) << TC_CMR_CAPTURE_LDBDIS_Pos)) +#define TC_CMR_CAPTURE_ETRGEDG_Pos _U_(8) /**< (TC_CMR) External Trigger Edge Selection Position */ +#define TC_CMR_CAPTURE_ETRGEDG_Msk (_U_(0x3) << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ +#define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) +#define TC_CMR_CAPTURE_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_CAPTURE_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ +#define TC_CMR_CAPTURE_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ +#define TC_CMR_CAPTURE_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */ +#define TC_CMR_CAPTURE_ETRGEDG_NONE (TC_CMR_CAPTURE_ETRGEDG_NONE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_CAPTURE_ETRGEDG_RISING (TC_CMR_CAPTURE_ETRGEDG_RISING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_CAPTURE_ETRGEDG_FALLING (TC_CMR_CAPTURE_ETRGEDG_FALLING_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_CAPTURE_ETRGEDG_EDGE (TC_CMR_CAPTURE_ETRGEDG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ +#define TC_CMR_CAPTURE_ABETRG_Pos _U_(10) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ +#define TC_CMR_CAPTURE_ABETRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ +#define TC_CMR_CAPTURE_ABETRG(value) (TC_CMR_CAPTURE_ABETRG_Msk & ((value) << TC_CMR_CAPTURE_ABETRG_Pos)) +#define TC_CMR_CAPTURE_CPCTRG_Pos _U_(14) /**< (TC_CMR) RC Compare Trigger Enable Position */ +#define TC_CMR_CAPTURE_CPCTRG_Msk (_U_(0x1) << TC_CMR_CAPTURE_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ +#define TC_CMR_CAPTURE_CPCTRG(value) (TC_CMR_CAPTURE_CPCTRG_Msk & ((value) << TC_CMR_CAPTURE_CPCTRG_Pos)) +#define TC_CMR_CAPTURE_LDRA_Pos _U_(16) /**< (TC_CMR) RA Loading Edge Selection Position */ +#define TC_CMR_CAPTURE_LDRA_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) RA Loading Edge Selection Mask */ +#define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) +#define TC_CMR_CAPTURE_LDRA_NONE_Val _U_(0x0) /**< (TC_CMR) None */ +#define TC_CMR_CAPTURE_LDRA_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRA_NONE (TC_CMR_CAPTURE_LDRA_NONE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_CAPTURE_LDRA_RISING (TC_CMR_CAPTURE_LDRA_RISING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRA_FALLING (TC_CMR_CAPTURE_LDRA_FALLING_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRA_EDGE (TC_CMR_CAPTURE_LDRA_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_Pos _U_(18) /**< (TC_CMR) RB Loading Edge Selection Position */ +#define TC_CMR_CAPTURE_LDRB_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) RB Loading Edge Selection Mask */ +#define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) +#define TC_CMR_CAPTURE_LDRB_NONE_Val _U_(0x0) /**< (TC_CMR) None */ +#define TC_CMR_CAPTURE_LDRB_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge of TIOAx */ +#define TC_CMR_CAPTURE_LDRB_NONE (TC_CMR_CAPTURE_LDRB_NONE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_CAPTURE_LDRB_RISING (TC_CMR_CAPTURE_LDRB_RISING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Rising edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_FALLING (TC_CMR_CAPTURE_LDRB_FALLING_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Falling edge of TIOAx Position */ +#define TC_CMR_CAPTURE_LDRB_EDGE (TC_CMR_CAPTURE_LDRB_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) /**< (TC_CMR) Each edge of TIOAx Position */ +#define TC_CMR_CAPTURE_SBSMPLR_Pos _U_(20) /**< (TC_CMR) Loading Edge Subsampling Ratio Position */ +#define TC_CMR_CAPTURE_SBSMPLR_Msk (_U_(0x7) << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Loading Edge Subsampling Ratio Mask */ +#define TC_CMR_CAPTURE_SBSMPLR(value) (TC_CMR_CAPTURE_SBSMPLR_Msk & ((value) << TC_CMR_CAPTURE_SBSMPLR_Pos)) +#define TC_CMR_CAPTURE_SBSMPLR_ONE_Val _U_(0x0) /**< (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_CAPTURE_SBSMPLR_HALF_Val _U_(0x1) /**< (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val _U_(0x2) /**< (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val _U_(0x3) /**< (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val _U_(0x4) /**< (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CAPTURE_SBSMPLR_ONE (TC_CMR_CAPTURE_SBSMPLR_ONE_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register each selected edge Position */ +#define TC_CMR_CAPTURE_SBSMPLR_HALF (TC_CMR_CAPTURE_SBSMPLR_HALF_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 2 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_FOURTH (TC_CMR_CAPTURE_SBSMPLR_FOURTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 4 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_EIGHTH (TC_CMR_CAPTURE_SBSMPLR_EIGHTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 8 selected edges Position */ +#define TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH (TC_CMR_CAPTURE_SBSMPLR_SIXTEENTH_Val << TC_CMR_CAPTURE_SBSMPLR_Pos) /**< (TC_CMR) Load a Capture Register every 16 selected edges Position */ +#define TC_CMR_CAPTURE_Msk _U_(0x007F47C0) /**< (TC_CMR_CAPTURE) Register Mask */ + +/* WAVEFORM mode */ +#define TC_CMR_WAVEFORM_CPCSTOP_Pos _U_(6) /**< (TC_CMR) Counter Clock Stopped with RC Compare Position */ +#define TC_CMR_WAVEFORM_CPCSTOP_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RC Compare Mask */ +#define TC_CMR_WAVEFORM_CPCSTOP(value) (TC_CMR_WAVEFORM_CPCSTOP_Msk & ((value) << TC_CMR_WAVEFORM_CPCSTOP_Pos)) +#define TC_CMR_WAVEFORM_CPCDIS_Pos _U_(7) /**< (TC_CMR) Counter Clock Disable with RC Loading Position */ +#define TC_CMR_WAVEFORM_CPCDIS_Msk (_U_(0x1) << TC_CMR_WAVEFORM_CPCDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RC Loading Mask */ +#define TC_CMR_WAVEFORM_CPCDIS(value) (TC_CMR_WAVEFORM_CPCDIS_Msk & ((value) << TC_CMR_WAVEFORM_CPCDIS_Pos)) +#define TC_CMR_WAVEFORM_EEVTEDG_Pos _U_(8) /**< (TC_CMR) External Event Edge Selection Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) External Event Edge Selection Mask */ +#define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) +#define TC_CMR_WAVEFORM_EEVTEDG_NONE_Val _U_(0x0) /**< (TC_CMR) None */ +#define TC_CMR_WAVEFORM_EEVTEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ +#define TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ +#define TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edges */ +#define TC_CMR_WAVEFORM_EEVTEDG_NONE (TC_CMR_WAVEFORM_EEVTEDG_NONE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) None Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_RISING (TC_CMR_WAVEFORM_EEVTEDG_RISING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_FALLING (TC_CMR_WAVEFORM_EEVTEDG_FALLING_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_WAVEFORM_EEVTEDG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) /**< (TC_CMR) Each edges Position */ +#define TC_CMR_WAVEFORM_EEVT_Pos _U_(10) /**< (TC_CMR) External Event Selection Position */ +#define TC_CMR_WAVEFORM_EEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) External Event Selection Mask */ +#define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) +#define TC_CMR_WAVEFORM_EEVT_TIOB_Val _U_(0x0) /**< (TC_CMR) TIOB */ +#define TC_CMR_WAVEFORM_EEVT_XC0_Val _U_(0x1) /**< (TC_CMR) XC0 */ +#define TC_CMR_WAVEFORM_EEVT_XC1_Val _U_(0x2) /**< (TC_CMR) XC1 */ +#define TC_CMR_WAVEFORM_EEVT_XC2_Val _U_(0x3) /**< (TC_CMR) XC2 */ +#define TC_CMR_WAVEFORM_EEVT_TIOB (TC_CMR_WAVEFORM_EEVT_TIOB_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) TIOB Position */ +#define TC_CMR_WAVEFORM_EEVT_XC0 (TC_CMR_WAVEFORM_EEVT_XC0_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC0 Position */ +#define TC_CMR_WAVEFORM_EEVT_XC1 (TC_CMR_WAVEFORM_EEVT_XC1_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC1 Position */ +#define TC_CMR_WAVEFORM_EEVT_XC2 (TC_CMR_WAVEFORM_EEVT_XC2_Val << TC_CMR_WAVEFORM_EEVT_Pos) /**< (TC_CMR) XC2 Position */ +#define TC_CMR_WAVEFORM_ENETRG_Pos _U_(12) /**< (TC_CMR) External Event Trigger Enable Position */ +#define TC_CMR_WAVEFORM_ENETRG_Msk (_U_(0x1) << TC_CMR_WAVEFORM_ENETRG_Pos) /**< (TC_CMR) External Event Trigger Enable Mask */ +#define TC_CMR_WAVEFORM_ENETRG(value) (TC_CMR_WAVEFORM_ENETRG_Msk & ((value) << TC_CMR_WAVEFORM_ENETRG_Pos)) +#define TC_CMR_WAVEFORM_WAVSEL_Pos _U_(13) /**< (TC_CMR) Waveform Selection Position */ +#define TC_CMR_WAVEFORM_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) Waveform Selection Mask */ +#define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) +#define TC_CMR_WAVEFORM_WAVSEL_UP_Val _U_(0x0) /**< (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val _U_(0x1) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val _U_(0x2) /**< (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val _U_(0x3) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ +#define TC_CMR_WAVEFORM_ACPA_Pos _U_(16) /**< (TC_CMR) RA Compare Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ACPA_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) RA Compare Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) +#define TC_CMR_WAVEFORM_ACPA_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_ACPA_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_ACPA_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_ACPC_Pos _U_(18) /**< (TC_CMR) RC Compare Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ACPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) +#define TC_CMR_WAVEFORM_ACPC_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_ACPC_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_ACPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_AEEVT_Pos _U_(20) /**< (TC_CMR) External Event Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_AEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) +#define TC_CMR_WAVEFORM_AEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_AEEVT_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_ASWTRG_Pos _U_(22) /**< (TC_CMR) Software Trigger Effect on TIOAx Position */ +#define TC_CMR_WAVEFORM_ASWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOAx Mask */ +#define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) +#define TC_CMR_WAVEFORM_ASWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_ASWTRG_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BCPB_Pos _U_(24) /**< (TC_CMR) RB Compare Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BCPB_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) RB Compare Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) +#define TC_CMR_WAVEFORM_BCPB_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_BCPB_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_BCPB_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BCPC_Pos _U_(26) /**< (TC_CMR) RC Compare Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BCPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) RC Compare Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) +#define TC_CMR_WAVEFORM_BCPC_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_BCPC_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_BCPC_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BEEVT_Pos _U_(28) /**< (TC_CMR) External Event Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) External Event Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) +#define TC_CMR_WAVEFORM_BEEVT_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_BEEVT_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_BSWTRG_Pos _U_(30) /**< (TC_CMR) Software Trigger Effect on TIOBx Position */ +#define TC_CMR_WAVEFORM_BSWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) Software Trigger Effect on TIOBx Mask */ +#define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) +#define TC_CMR_WAVEFORM_BSWTRG_NONE_Val _U_(0x0) /**< (TC_CMR) NONE */ +#define TC_CMR_WAVEFORM_BSWTRG_SET_Val _U_(0x1) /**< (TC_CMR) SET */ +#define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val _U_(0x2) /**< (TC_CMR) CLEAR */ +#define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val _U_(0x3) /**< (TC_CMR) TOGGLE */ +#define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) NONE Position */ +#define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) SET Position */ +#define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) CLEAR Position */ +#define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) /**< (TC_CMR) TOGGLE Position */ +#define TC_CMR_WAVEFORM_Msk _U_(0xFFFF7FC0) /**< (TC_CMR_WAVEFORM) Register Mask */ + + +/* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) Stepper Motor Mode Register (channel = 0) -------- */ +#define TC_SMMR_GCEN_Pos _U_(0) /**< (TC_SMMR) Gray Count Enable Position */ +#define TC_SMMR_GCEN_Msk (_U_(0x1) << TC_SMMR_GCEN_Pos) /**< (TC_SMMR) Gray Count Enable Mask */ +#define TC_SMMR_GCEN(value) (TC_SMMR_GCEN_Msk & ((value) << TC_SMMR_GCEN_Pos)) +#define TC_SMMR_DOWN_Pos _U_(1) /**< (TC_SMMR) Down Count Position */ +#define TC_SMMR_DOWN_Msk (_U_(0x1) << TC_SMMR_DOWN_Pos) /**< (TC_SMMR) Down Count Mask */ +#define TC_SMMR_DOWN(value) (TC_SMMR_DOWN_Msk & ((value) << TC_SMMR_DOWN_Pos)) +#define TC_SMMR_Msk _U_(0x00000003) /**< (TC_SMMR) Register Mask */ + + +/* -------- TC_RAB : (TC Offset: 0x0C) ( R/ 32) Register AB (channel = 0) -------- */ +#define TC_RAB_RAB_Pos _U_(0) /**< (TC_RAB) Register A or Register B Position */ +#define TC_RAB_RAB_Msk (_U_(0xFFFFFFFF) << TC_RAB_RAB_Pos) /**< (TC_RAB) Register A or Register B Mask */ +#define TC_RAB_RAB(value) (TC_RAB_RAB_Msk & ((value) << TC_RAB_RAB_Pos)) +#define TC_RAB_Msk _U_(0xFFFFFFFF) /**< (TC_RAB) Register Mask */ + + +/* -------- TC_CV : (TC Offset: 0x10) ( R/ 32) Counter Value (channel = 0) -------- */ +#define TC_CV_CV_Pos _U_(0) /**< (TC_CV) Counter Value Position */ +#define TC_CV_CV_Msk (_U_(0xFFFFFFFF) << TC_CV_CV_Pos) /**< (TC_CV) Counter Value Mask */ +#define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) +#define TC_CV_Msk _U_(0xFFFFFFFF) /**< (TC_CV) Register Mask */ + + +/* -------- TC_RA : (TC Offset: 0x14) (R/W 32) Register A (channel = 0) -------- */ +#define TC_RA_RA_Pos _U_(0) /**< (TC_RA) Register A Position */ +#define TC_RA_RA_Msk (_U_(0xFFFFFFFF) << TC_RA_RA_Pos) /**< (TC_RA) Register A Mask */ +#define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) +#define TC_RA_Msk _U_(0xFFFFFFFF) /**< (TC_RA) Register Mask */ + + +/* -------- TC_RB : (TC Offset: 0x18) (R/W 32) Register B (channel = 0) -------- */ +#define TC_RB_RB_Pos _U_(0) /**< (TC_RB) Register B Position */ +#define TC_RB_RB_Msk (_U_(0xFFFFFFFF) << TC_RB_RB_Pos) /**< (TC_RB) Register B Mask */ +#define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) +#define TC_RB_Msk _U_(0xFFFFFFFF) /**< (TC_RB) Register Mask */ + + +/* -------- TC_RC : (TC Offset: 0x1C) (R/W 32) Register C (channel = 0) -------- */ +#define TC_RC_RC_Pos _U_(0) /**< (TC_RC) Register C Position */ +#define TC_RC_RC_Msk (_U_(0xFFFFFFFF) << TC_RC_RC_Pos) /**< (TC_RC) Register C Mask */ +#define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) +#define TC_RC_Msk _U_(0xFFFFFFFF) /**< (TC_RC) Register Mask */ + + +/* -------- TC_SR : (TC Offset: 0x20) ( R/ 32) Status Register (channel = 0) -------- */ +#define TC_SR_COVFS_Pos _U_(0) /**< (TC_SR) Counter Overflow Status (cleared on read) Position */ +#define TC_SR_COVFS_Msk (_U_(0x1) << TC_SR_COVFS_Pos) /**< (TC_SR) Counter Overflow Status (cleared on read) Mask */ +#define TC_SR_COVFS(value) (TC_SR_COVFS_Msk & ((value) << TC_SR_COVFS_Pos)) +#define TC_SR_LOVRS_Pos _U_(1) /**< (TC_SR) Load Overrun Status (cleared on read) Position */ +#define TC_SR_LOVRS_Msk (_U_(0x1) << TC_SR_LOVRS_Pos) /**< (TC_SR) Load Overrun Status (cleared on read) Mask */ +#define TC_SR_LOVRS(value) (TC_SR_LOVRS_Msk & ((value) << TC_SR_LOVRS_Pos)) +#define TC_SR_CPAS_Pos _U_(2) /**< (TC_SR) RA Compare Status (cleared on read) Position */ +#define TC_SR_CPAS_Msk (_U_(0x1) << TC_SR_CPAS_Pos) /**< (TC_SR) RA Compare Status (cleared on read) Mask */ +#define TC_SR_CPAS(value) (TC_SR_CPAS_Msk & ((value) << TC_SR_CPAS_Pos)) +#define TC_SR_CPBS_Pos _U_(3) /**< (TC_SR) RB Compare Status (cleared on read) Position */ +#define TC_SR_CPBS_Msk (_U_(0x1) << TC_SR_CPBS_Pos) /**< (TC_SR) RB Compare Status (cleared on read) Mask */ +#define TC_SR_CPBS(value) (TC_SR_CPBS_Msk & ((value) << TC_SR_CPBS_Pos)) +#define TC_SR_CPCS_Pos _U_(4) /**< (TC_SR) RC Compare Status (cleared on read) Position */ +#define TC_SR_CPCS_Msk (_U_(0x1) << TC_SR_CPCS_Pos) /**< (TC_SR) RC Compare Status (cleared on read) Mask */ +#define TC_SR_CPCS(value) (TC_SR_CPCS_Msk & ((value) << TC_SR_CPCS_Pos)) +#define TC_SR_LDRAS_Pos _U_(5) /**< (TC_SR) RA Loading Status (cleared on read) Position */ +#define TC_SR_LDRAS_Msk (_U_(0x1) << TC_SR_LDRAS_Pos) /**< (TC_SR) RA Loading Status (cleared on read) Mask */ +#define TC_SR_LDRAS(value) (TC_SR_LDRAS_Msk & ((value) << TC_SR_LDRAS_Pos)) +#define TC_SR_LDRBS_Pos _U_(6) /**< (TC_SR) RB Loading Status (cleared on read) Position */ +#define TC_SR_LDRBS_Msk (_U_(0x1) << TC_SR_LDRBS_Pos) /**< (TC_SR) RB Loading Status (cleared on read) Mask */ +#define TC_SR_LDRBS(value) (TC_SR_LDRBS_Msk & ((value) << TC_SR_LDRBS_Pos)) +#define TC_SR_ETRGS_Pos _U_(7) /**< (TC_SR) External Trigger Status (cleared on read) Position */ +#define TC_SR_ETRGS_Msk (_U_(0x1) << TC_SR_ETRGS_Pos) /**< (TC_SR) External Trigger Status (cleared on read) Mask */ +#define TC_SR_ETRGS(value) (TC_SR_ETRGS_Msk & ((value) << TC_SR_ETRGS_Pos)) +#define TC_SR_CLKSTA_Pos _U_(16) /**< (TC_SR) Clock Enabling Status Position */ +#define TC_SR_CLKSTA_Msk (_U_(0x1) << TC_SR_CLKSTA_Pos) /**< (TC_SR) Clock Enabling Status Mask */ +#define TC_SR_CLKSTA(value) (TC_SR_CLKSTA_Msk & ((value) << TC_SR_CLKSTA_Pos)) +#define TC_SR_MTIOA_Pos _U_(17) /**< (TC_SR) TIOAx Mirror Position */ +#define TC_SR_MTIOA_Msk (_U_(0x1) << TC_SR_MTIOA_Pos) /**< (TC_SR) TIOAx Mirror Mask */ +#define TC_SR_MTIOA(value) (TC_SR_MTIOA_Msk & ((value) << TC_SR_MTIOA_Pos)) +#define TC_SR_MTIOB_Pos _U_(18) /**< (TC_SR) TIOBx Mirror Position */ +#define TC_SR_MTIOB_Msk (_U_(0x1) << TC_SR_MTIOB_Pos) /**< (TC_SR) TIOBx Mirror Mask */ +#define TC_SR_MTIOB(value) (TC_SR_MTIOB_Msk & ((value) << TC_SR_MTIOB_Pos)) +#define TC_SR_Msk _U_(0x000700FF) /**< (TC_SR) Register Mask */ + + +/* -------- TC_IER : (TC Offset: 0x24) ( /W 32) Interrupt Enable Register (channel = 0) -------- */ +#define TC_IER_COVFS_Pos _U_(0) /**< (TC_IER) Counter Overflow Position */ +#define TC_IER_COVFS_Msk (_U_(0x1) << TC_IER_COVFS_Pos) /**< (TC_IER) Counter Overflow Mask */ +#define TC_IER_COVFS(value) (TC_IER_COVFS_Msk & ((value) << TC_IER_COVFS_Pos)) +#define TC_IER_LOVRS_Pos _U_(1) /**< (TC_IER) Load Overrun Position */ +#define TC_IER_LOVRS_Msk (_U_(0x1) << TC_IER_LOVRS_Pos) /**< (TC_IER) Load Overrun Mask */ +#define TC_IER_LOVRS(value) (TC_IER_LOVRS_Msk & ((value) << TC_IER_LOVRS_Pos)) +#define TC_IER_CPAS_Pos _U_(2) /**< (TC_IER) RA Compare Position */ +#define TC_IER_CPAS_Msk (_U_(0x1) << TC_IER_CPAS_Pos) /**< (TC_IER) RA Compare Mask */ +#define TC_IER_CPAS(value) (TC_IER_CPAS_Msk & ((value) << TC_IER_CPAS_Pos)) +#define TC_IER_CPBS_Pos _U_(3) /**< (TC_IER) RB Compare Position */ +#define TC_IER_CPBS_Msk (_U_(0x1) << TC_IER_CPBS_Pos) /**< (TC_IER) RB Compare Mask */ +#define TC_IER_CPBS(value) (TC_IER_CPBS_Msk & ((value) << TC_IER_CPBS_Pos)) +#define TC_IER_CPCS_Pos _U_(4) /**< (TC_IER) RC Compare Position */ +#define TC_IER_CPCS_Msk (_U_(0x1) << TC_IER_CPCS_Pos) /**< (TC_IER) RC Compare Mask */ +#define TC_IER_CPCS(value) (TC_IER_CPCS_Msk & ((value) << TC_IER_CPCS_Pos)) +#define TC_IER_LDRAS_Pos _U_(5) /**< (TC_IER) RA Loading Position */ +#define TC_IER_LDRAS_Msk (_U_(0x1) << TC_IER_LDRAS_Pos) /**< (TC_IER) RA Loading Mask */ +#define TC_IER_LDRAS(value) (TC_IER_LDRAS_Msk & ((value) << TC_IER_LDRAS_Pos)) +#define TC_IER_LDRBS_Pos _U_(6) /**< (TC_IER) RB Loading Position */ +#define TC_IER_LDRBS_Msk (_U_(0x1) << TC_IER_LDRBS_Pos) /**< (TC_IER) RB Loading Mask */ +#define TC_IER_LDRBS(value) (TC_IER_LDRBS_Msk & ((value) << TC_IER_LDRBS_Pos)) +#define TC_IER_ETRGS_Pos _U_(7) /**< (TC_IER) External Trigger Position */ +#define TC_IER_ETRGS_Msk (_U_(0x1) << TC_IER_ETRGS_Pos) /**< (TC_IER) External Trigger Mask */ +#define TC_IER_ETRGS(value) (TC_IER_ETRGS_Msk & ((value) << TC_IER_ETRGS_Pos)) +#define TC_IER_Msk _U_(0x000000FF) /**< (TC_IER) Register Mask */ + + +/* -------- TC_IDR : (TC Offset: 0x28) ( /W 32) Interrupt Disable Register (channel = 0) -------- */ +#define TC_IDR_COVFS_Pos _U_(0) /**< (TC_IDR) Counter Overflow Position */ +#define TC_IDR_COVFS_Msk (_U_(0x1) << TC_IDR_COVFS_Pos) /**< (TC_IDR) Counter Overflow Mask */ +#define TC_IDR_COVFS(value) (TC_IDR_COVFS_Msk & ((value) << TC_IDR_COVFS_Pos)) +#define TC_IDR_LOVRS_Pos _U_(1) /**< (TC_IDR) Load Overrun Position */ +#define TC_IDR_LOVRS_Msk (_U_(0x1) << TC_IDR_LOVRS_Pos) /**< (TC_IDR) Load Overrun Mask */ +#define TC_IDR_LOVRS(value) (TC_IDR_LOVRS_Msk & ((value) << TC_IDR_LOVRS_Pos)) +#define TC_IDR_CPAS_Pos _U_(2) /**< (TC_IDR) RA Compare Position */ +#define TC_IDR_CPAS_Msk (_U_(0x1) << TC_IDR_CPAS_Pos) /**< (TC_IDR) RA Compare Mask */ +#define TC_IDR_CPAS(value) (TC_IDR_CPAS_Msk & ((value) << TC_IDR_CPAS_Pos)) +#define TC_IDR_CPBS_Pos _U_(3) /**< (TC_IDR) RB Compare Position */ +#define TC_IDR_CPBS_Msk (_U_(0x1) << TC_IDR_CPBS_Pos) /**< (TC_IDR) RB Compare Mask */ +#define TC_IDR_CPBS(value) (TC_IDR_CPBS_Msk & ((value) << TC_IDR_CPBS_Pos)) +#define TC_IDR_CPCS_Pos _U_(4) /**< (TC_IDR) RC Compare Position */ +#define TC_IDR_CPCS_Msk (_U_(0x1) << TC_IDR_CPCS_Pos) /**< (TC_IDR) RC Compare Mask */ +#define TC_IDR_CPCS(value) (TC_IDR_CPCS_Msk & ((value) << TC_IDR_CPCS_Pos)) +#define TC_IDR_LDRAS_Pos _U_(5) /**< (TC_IDR) RA Loading Position */ +#define TC_IDR_LDRAS_Msk (_U_(0x1) << TC_IDR_LDRAS_Pos) /**< (TC_IDR) RA Loading Mask */ +#define TC_IDR_LDRAS(value) (TC_IDR_LDRAS_Msk & ((value) << TC_IDR_LDRAS_Pos)) +#define TC_IDR_LDRBS_Pos _U_(6) /**< (TC_IDR) RB Loading Position */ +#define TC_IDR_LDRBS_Msk (_U_(0x1) << TC_IDR_LDRBS_Pos) /**< (TC_IDR) RB Loading Mask */ +#define TC_IDR_LDRBS(value) (TC_IDR_LDRBS_Msk & ((value) << TC_IDR_LDRBS_Pos)) +#define TC_IDR_ETRGS_Pos _U_(7) /**< (TC_IDR) External Trigger Position */ +#define TC_IDR_ETRGS_Msk (_U_(0x1) << TC_IDR_ETRGS_Pos) /**< (TC_IDR) External Trigger Mask */ +#define TC_IDR_ETRGS(value) (TC_IDR_ETRGS_Msk & ((value) << TC_IDR_ETRGS_Pos)) +#define TC_IDR_Msk _U_(0x000000FF) /**< (TC_IDR) Register Mask */ + + +/* -------- TC_IMR : (TC Offset: 0x2C) ( R/ 32) Interrupt Mask Register (channel = 0) -------- */ +#define TC_IMR_COVFS_Pos _U_(0) /**< (TC_IMR) Counter Overflow Position */ +#define TC_IMR_COVFS_Msk (_U_(0x1) << TC_IMR_COVFS_Pos) /**< (TC_IMR) Counter Overflow Mask */ +#define TC_IMR_COVFS(value) (TC_IMR_COVFS_Msk & ((value) << TC_IMR_COVFS_Pos)) +#define TC_IMR_LOVRS_Pos _U_(1) /**< (TC_IMR) Load Overrun Position */ +#define TC_IMR_LOVRS_Msk (_U_(0x1) << TC_IMR_LOVRS_Pos) /**< (TC_IMR) Load Overrun Mask */ +#define TC_IMR_LOVRS(value) (TC_IMR_LOVRS_Msk & ((value) << TC_IMR_LOVRS_Pos)) +#define TC_IMR_CPAS_Pos _U_(2) /**< (TC_IMR) RA Compare Position */ +#define TC_IMR_CPAS_Msk (_U_(0x1) << TC_IMR_CPAS_Pos) /**< (TC_IMR) RA Compare Mask */ +#define TC_IMR_CPAS(value) (TC_IMR_CPAS_Msk & ((value) << TC_IMR_CPAS_Pos)) +#define TC_IMR_CPBS_Pos _U_(3) /**< (TC_IMR) RB Compare Position */ +#define TC_IMR_CPBS_Msk (_U_(0x1) << TC_IMR_CPBS_Pos) /**< (TC_IMR) RB Compare Mask */ +#define TC_IMR_CPBS(value) (TC_IMR_CPBS_Msk & ((value) << TC_IMR_CPBS_Pos)) +#define TC_IMR_CPCS_Pos _U_(4) /**< (TC_IMR) RC Compare Position */ +#define TC_IMR_CPCS_Msk (_U_(0x1) << TC_IMR_CPCS_Pos) /**< (TC_IMR) RC Compare Mask */ +#define TC_IMR_CPCS(value) (TC_IMR_CPCS_Msk & ((value) << TC_IMR_CPCS_Pos)) +#define TC_IMR_LDRAS_Pos _U_(5) /**< (TC_IMR) RA Loading Position */ +#define TC_IMR_LDRAS_Msk (_U_(0x1) << TC_IMR_LDRAS_Pos) /**< (TC_IMR) RA Loading Mask */ +#define TC_IMR_LDRAS(value) (TC_IMR_LDRAS_Msk & ((value) << TC_IMR_LDRAS_Pos)) +#define TC_IMR_LDRBS_Pos _U_(6) /**< (TC_IMR) RB Loading Position */ +#define TC_IMR_LDRBS_Msk (_U_(0x1) << TC_IMR_LDRBS_Pos) /**< (TC_IMR) RB Loading Mask */ +#define TC_IMR_LDRBS(value) (TC_IMR_LDRBS_Msk & ((value) << TC_IMR_LDRBS_Pos)) +#define TC_IMR_ETRGS_Pos _U_(7) /**< (TC_IMR) External Trigger Position */ +#define TC_IMR_ETRGS_Msk (_U_(0x1) << TC_IMR_ETRGS_Pos) /**< (TC_IMR) External Trigger Mask */ +#define TC_IMR_ETRGS(value) (TC_IMR_ETRGS_Msk & ((value) << TC_IMR_ETRGS_Pos)) +#define TC_IMR_Msk _U_(0x000000FF) /**< (TC_IMR) Register Mask */ + + +/* -------- TC_EMR : (TC Offset: 0x30) (R/W 32) Extended Mode Register (channel = 0) -------- */ +#define TC_EMR_TRIGSRCA_Pos _U_(0) /**< (TC_EMR) Trigger Source for Input A Position */ +#define TC_EMR_TRIGSRCA_Msk (_U_(0x3) << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) Trigger Source for Input A Mask */ +#define TC_EMR_TRIGSRCA(value) (TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx_Val _U_(0x1) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (TC_EMR_TRIGSRCA_EXTERNAL_TIOAx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven by external pin TIOAx Position */ +#define TC_EMR_TRIGSRCA_PWMx (TC_EMR_TRIGSRCA_PWMx_Val << TC_EMR_TRIGSRCA_Pos) /**< (TC_EMR) The trigger/capture input A is driven internally by PWMx Position */ +#define TC_EMR_TRIGSRCB_Pos _U_(4) /**< (TC_EMR) Trigger Source for Input B Position */ +#define TC_EMR_TRIGSRCB_Msk (_U_(0x3) << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) Trigger Source for Input B Mask */ +#define TC_EMR_TRIGSRCB(value) (TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val _U_(0x0) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx_Val _U_(0x1) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). */ +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (TC_EMR_TRIGSRCB_EXTERNAL_TIOBx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) The trigger/capture input B is driven by external pin TIOBx Position */ +#define TC_EMR_TRIGSRCB_PWMx (TC_EMR_TRIGSRCB_PWMx_Val << TC_EMR_TRIGSRCB_Pos) /**< (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). Position */ +#define TC_EMR_NODIVCLK_Pos _U_(8) /**< (TC_EMR) No Divided Clock Position */ +#define TC_EMR_NODIVCLK_Msk (_U_(0x1) << TC_EMR_NODIVCLK_Pos) /**< (TC_EMR) No Divided Clock Mask */ +#define TC_EMR_NODIVCLK(value) (TC_EMR_NODIVCLK_Msk & ((value) << TC_EMR_NODIVCLK_Pos)) +#define TC_EMR_Msk _U_(0x00000133) /**< (TC_EMR) Register Mask */ + + +/* -------- TC_BCR : (TC Offset: 0xC0) ( /W 32) Block Control Register -------- */ +#define TC_BCR_SYNC_Pos _U_(0) /**< (TC_BCR) Synchro Command Position */ +#define TC_BCR_SYNC_Msk (_U_(0x1) << TC_BCR_SYNC_Pos) /**< (TC_BCR) Synchro Command Mask */ +#define TC_BCR_SYNC(value) (TC_BCR_SYNC_Msk & ((value) << TC_BCR_SYNC_Pos)) +#define TC_BCR_Msk _U_(0x00000001) /**< (TC_BCR) Register Mask */ + + +/* -------- TC_BMR : (TC Offset: 0xC4) (R/W 32) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos _U_(0) /**< (TC_BMR) External Clock Signal 0 Selection Position */ +#define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) External Clock Signal 0 Selection Mask */ +#define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) +#define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TCLK0 Position */ +#define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA1 Position */ +#define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) /**< (TC_BMR) Signal connected to XC0: TIOA2 Position */ +#define TC_BMR_TC1XC1S_Pos _U_(2) /**< (TC_BMR) External Clock Signal 1 Selection Position */ +#define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) External Clock Signal 1 Selection Mask */ +#define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) +#define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TCLK1 Position */ +#define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA0 Position */ +#define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) /**< (TC_BMR) Signal connected to XC1: TIOA2 Position */ +#define TC_BMR_TC2XC2S_Pos _U_(4) /**< (TC_BMR) External Clock Signal 2 Selection Position */ +#define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) External Clock Signal 2 Selection Mask */ +#define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) +#define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TCLK2 Position */ +#define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA0 Position */ +#define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) /**< (TC_BMR) Signal connected to XC2: TIOA1 Position */ +#define TC_BMR_QDEN_Pos _U_(8) /**< (TC_BMR) Quadrature Decoder Enabled Position */ +#define TC_BMR_QDEN_Msk (_U_(0x1) << TC_BMR_QDEN_Pos) /**< (TC_BMR) Quadrature Decoder Enabled Mask */ +#define TC_BMR_QDEN(value) (TC_BMR_QDEN_Msk & ((value) << TC_BMR_QDEN_Pos)) +#define TC_BMR_POSEN_Pos _U_(9) /**< (TC_BMR) Position Enabled Position */ +#define TC_BMR_POSEN_Msk (_U_(0x1) << TC_BMR_POSEN_Pos) /**< (TC_BMR) Position Enabled Mask */ +#define TC_BMR_POSEN(value) (TC_BMR_POSEN_Msk & ((value) << TC_BMR_POSEN_Pos)) +#define TC_BMR_SPEEDEN_Pos _U_(10) /**< (TC_BMR) Speed Enabled Position */ +#define TC_BMR_SPEEDEN_Msk (_U_(0x1) << TC_BMR_SPEEDEN_Pos) /**< (TC_BMR) Speed Enabled Mask */ +#define TC_BMR_SPEEDEN(value) (TC_BMR_SPEEDEN_Msk & ((value) << TC_BMR_SPEEDEN_Pos)) +#define TC_BMR_QDTRANS_Pos _U_(11) /**< (TC_BMR) Quadrature Decoding Transparent Position */ +#define TC_BMR_QDTRANS_Msk (_U_(0x1) << TC_BMR_QDTRANS_Pos) /**< (TC_BMR) Quadrature Decoding Transparent Mask */ +#define TC_BMR_QDTRANS(value) (TC_BMR_QDTRANS_Msk & ((value) << TC_BMR_QDTRANS_Pos)) +#define TC_BMR_EDGPHA_Pos _U_(12) /**< (TC_BMR) Edge on PHA Count Mode Position */ +#define TC_BMR_EDGPHA_Msk (_U_(0x1) << TC_BMR_EDGPHA_Pos) /**< (TC_BMR) Edge on PHA Count Mode Mask */ +#define TC_BMR_EDGPHA(value) (TC_BMR_EDGPHA_Msk & ((value) << TC_BMR_EDGPHA_Pos)) +#define TC_BMR_INVA_Pos _U_(13) /**< (TC_BMR) Inverted PHA Position */ +#define TC_BMR_INVA_Msk (_U_(0x1) << TC_BMR_INVA_Pos) /**< (TC_BMR) Inverted PHA Mask */ +#define TC_BMR_INVA(value) (TC_BMR_INVA_Msk & ((value) << TC_BMR_INVA_Pos)) +#define TC_BMR_INVB_Pos _U_(14) /**< (TC_BMR) Inverted PHB Position */ +#define TC_BMR_INVB_Msk (_U_(0x1) << TC_BMR_INVB_Pos) /**< (TC_BMR) Inverted PHB Mask */ +#define TC_BMR_INVB(value) (TC_BMR_INVB_Msk & ((value) << TC_BMR_INVB_Pos)) +#define TC_BMR_INVIDX_Pos _U_(15) /**< (TC_BMR) Inverted Index Position */ +#define TC_BMR_INVIDX_Msk (_U_(0x1) << TC_BMR_INVIDX_Pos) /**< (TC_BMR) Inverted Index Mask */ +#define TC_BMR_INVIDX(value) (TC_BMR_INVIDX_Msk & ((value) << TC_BMR_INVIDX_Pos)) +#define TC_BMR_SWAP_Pos _U_(16) /**< (TC_BMR) Swap PHA and PHB Position */ +#define TC_BMR_SWAP_Msk (_U_(0x1) << TC_BMR_SWAP_Pos) /**< (TC_BMR) Swap PHA and PHB Mask */ +#define TC_BMR_SWAP(value) (TC_BMR_SWAP_Msk & ((value) << TC_BMR_SWAP_Pos)) +#define TC_BMR_IDXPHB_Pos _U_(17) /**< (TC_BMR) Index Pin is PHB Pin Position */ +#define TC_BMR_IDXPHB_Msk (_U_(0x1) << TC_BMR_IDXPHB_Pos) /**< (TC_BMR) Index Pin is PHB Pin Mask */ +#define TC_BMR_IDXPHB(value) (TC_BMR_IDXPHB_Msk & ((value) << TC_BMR_IDXPHB_Pos)) +#define TC_BMR_AUTOC_Pos _U_(18) /**< (TC_BMR) AutoCorrection of missing pulses Position */ +#define TC_BMR_AUTOC_Msk (_U_(0x1) << TC_BMR_AUTOC_Pos) /**< (TC_BMR) AutoCorrection of missing pulses Mask */ +#define TC_BMR_AUTOC(value) (TC_BMR_AUTOC_Msk & ((value) << TC_BMR_AUTOC_Pos)) +#define TC_BMR_MAXFILT_Pos _U_(20) /**< (TC_BMR) Maximum Filter Position */ +#define TC_BMR_MAXFILT_Msk (_U_(0x3F) << TC_BMR_MAXFILT_Pos) /**< (TC_BMR) Maximum Filter Mask */ +#define TC_BMR_MAXFILT(value) (TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)) +#define TC_BMR_MAXCMP_Pos _U_(26) /**< (TC_BMR) Maximum Consecutive Missing Pulses Position */ +#define TC_BMR_MAXCMP_Msk (_U_(0xF) << TC_BMR_MAXCMP_Pos) /**< (TC_BMR) Maximum Consecutive Missing Pulses Mask */ +#define TC_BMR_MAXCMP(value) (TC_BMR_MAXCMP_Msk & ((value) << TC_BMR_MAXCMP_Pos)) +#define TC_BMR_Msk _U_(0x3FF7FF3F) /**< (TC_BMR) Register Mask */ + + +/* -------- TC_QIER : (TC Offset: 0xC8) ( /W 32) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX_Pos _U_(0) /**< (TC_QIER) Index Position */ +#define TC_QIER_IDX_Msk (_U_(0x1) << TC_QIER_IDX_Pos) /**< (TC_QIER) Index Mask */ +#define TC_QIER_IDX(value) (TC_QIER_IDX_Msk & ((value) << TC_QIER_IDX_Pos)) +#define TC_QIER_DIRCHG_Pos _U_(1) /**< (TC_QIER) Direction Change Position */ +#define TC_QIER_DIRCHG_Msk (_U_(0x1) << TC_QIER_DIRCHG_Pos) /**< (TC_QIER) Direction Change Mask */ +#define TC_QIER_DIRCHG(value) (TC_QIER_DIRCHG_Msk & ((value) << TC_QIER_DIRCHG_Pos)) +#define TC_QIER_QERR_Pos _U_(2) /**< (TC_QIER) Quadrature Error Position */ +#define TC_QIER_QERR_Msk (_U_(0x1) << TC_QIER_QERR_Pos) /**< (TC_QIER) Quadrature Error Mask */ +#define TC_QIER_QERR(value) (TC_QIER_QERR_Msk & ((value) << TC_QIER_QERR_Pos)) +#define TC_QIER_MPE_Pos _U_(3) /**< (TC_QIER) Consecutive Missing Pulse Error Position */ +#define TC_QIER_MPE_Msk (_U_(0x1) << TC_QIER_MPE_Pos) /**< (TC_QIER) Consecutive Missing Pulse Error Mask */ +#define TC_QIER_MPE(value) (TC_QIER_MPE_Msk & ((value) << TC_QIER_MPE_Pos)) +#define TC_QIER_Msk _U_(0x0000000F) /**< (TC_QIER) Register Mask */ + + +/* -------- TC_QIDR : (TC Offset: 0xCC) ( /W 32) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX_Pos _U_(0) /**< (TC_QIDR) Index Position */ +#define TC_QIDR_IDX_Msk (_U_(0x1) << TC_QIDR_IDX_Pos) /**< (TC_QIDR) Index Mask */ +#define TC_QIDR_IDX(value) (TC_QIDR_IDX_Msk & ((value) << TC_QIDR_IDX_Pos)) +#define TC_QIDR_DIRCHG_Pos _U_(1) /**< (TC_QIDR) Direction Change Position */ +#define TC_QIDR_DIRCHG_Msk (_U_(0x1) << TC_QIDR_DIRCHG_Pos) /**< (TC_QIDR) Direction Change Mask */ +#define TC_QIDR_DIRCHG(value) (TC_QIDR_DIRCHG_Msk & ((value) << TC_QIDR_DIRCHG_Pos)) +#define TC_QIDR_QERR_Pos _U_(2) /**< (TC_QIDR) Quadrature Error Position */ +#define TC_QIDR_QERR_Msk (_U_(0x1) << TC_QIDR_QERR_Pos) /**< (TC_QIDR) Quadrature Error Mask */ +#define TC_QIDR_QERR(value) (TC_QIDR_QERR_Msk & ((value) << TC_QIDR_QERR_Pos)) +#define TC_QIDR_MPE_Pos _U_(3) /**< (TC_QIDR) Consecutive Missing Pulse Error Position */ +#define TC_QIDR_MPE_Msk (_U_(0x1) << TC_QIDR_MPE_Pos) /**< (TC_QIDR) Consecutive Missing Pulse Error Mask */ +#define TC_QIDR_MPE(value) (TC_QIDR_MPE_Msk & ((value) << TC_QIDR_MPE_Pos)) +#define TC_QIDR_Msk _U_(0x0000000F) /**< (TC_QIDR) Register Mask */ + + +/* -------- TC_QIMR : (TC Offset: 0xD0) ( R/ 32) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX_Pos _U_(0) /**< (TC_QIMR) Index Position */ +#define TC_QIMR_IDX_Msk (_U_(0x1) << TC_QIMR_IDX_Pos) /**< (TC_QIMR) Index Mask */ +#define TC_QIMR_IDX(value) (TC_QIMR_IDX_Msk & ((value) << TC_QIMR_IDX_Pos)) +#define TC_QIMR_DIRCHG_Pos _U_(1) /**< (TC_QIMR) Direction Change Position */ +#define TC_QIMR_DIRCHG_Msk (_U_(0x1) << TC_QIMR_DIRCHG_Pos) /**< (TC_QIMR) Direction Change Mask */ +#define TC_QIMR_DIRCHG(value) (TC_QIMR_DIRCHG_Msk & ((value) << TC_QIMR_DIRCHG_Pos)) +#define TC_QIMR_QERR_Pos _U_(2) /**< (TC_QIMR) Quadrature Error Position */ +#define TC_QIMR_QERR_Msk (_U_(0x1) << TC_QIMR_QERR_Pos) /**< (TC_QIMR) Quadrature Error Mask */ +#define TC_QIMR_QERR(value) (TC_QIMR_QERR_Msk & ((value) << TC_QIMR_QERR_Pos)) +#define TC_QIMR_MPE_Pos _U_(3) /**< (TC_QIMR) Consecutive Missing Pulse Error Position */ +#define TC_QIMR_MPE_Msk (_U_(0x1) << TC_QIMR_MPE_Pos) /**< (TC_QIMR) Consecutive Missing Pulse Error Mask */ +#define TC_QIMR_MPE(value) (TC_QIMR_MPE_Msk & ((value) << TC_QIMR_MPE_Pos)) +#define TC_QIMR_Msk _U_(0x0000000F) /**< (TC_QIMR) Register Mask */ + + +/* -------- TC_QISR : (TC Offset: 0xD4) ( R/ 32) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX_Pos _U_(0) /**< (TC_QISR) Index Position */ +#define TC_QISR_IDX_Msk (_U_(0x1) << TC_QISR_IDX_Pos) /**< (TC_QISR) Index Mask */ +#define TC_QISR_IDX(value) (TC_QISR_IDX_Msk & ((value) << TC_QISR_IDX_Pos)) +#define TC_QISR_DIRCHG_Pos _U_(1) /**< (TC_QISR) Direction Change Position */ +#define TC_QISR_DIRCHG_Msk (_U_(0x1) << TC_QISR_DIRCHG_Pos) /**< (TC_QISR) Direction Change Mask */ +#define TC_QISR_DIRCHG(value) (TC_QISR_DIRCHG_Msk & ((value) << TC_QISR_DIRCHG_Pos)) +#define TC_QISR_QERR_Pos _U_(2) /**< (TC_QISR) Quadrature Error Position */ +#define TC_QISR_QERR_Msk (_U_(0x1) << TC_QISR_QERR_Pos) /**< (TC_QISR) Quadrature Error Mask */ +#define TC_QISR_QERR(value) (TC_QISR_QERR_Msk & ((value) << TC_QISR_QERR_Pos)) +#define TC_QISR_MPE_Pos _U_(3) /**< (TC_QISR) Consecutive Missing Pulse Error Position */ +#define TC_QISR_MPE_Msk (_U_(0x1) << TC_QISR_MPE_Pos) /**< (TC_QISR) Consecutive Missing Pulse Error Mask */ +#define TC_QISR_MPE(value) (TC_QISR_MPE_Msk & ((value) << TC_QISR_MPE_Pos)) +#define TC_QISR_DIR_Pos _U_(8) /**< (TC_QISR) Direction Position */ +#define TC_QISR_DIR_Msk (_U_(0x1) << TC_QISR_DIR_Pos) /**< (TC_QISR) Direction Mask */ +#define TC_QISR_DIR(value) (TC_QISR_DIR_Msk & ((value) << TC_QISR_DIR_Pos)) +#define TC_QISR_Msk _U_(0x0000010F) /**< (TC_QISR) Register Mask */ + + +/* -------- TC_FMR : (TC Offset: 0xD8) (R/W 32) Fault Mode Register -------- */ +#define TC_FMR_ENCF0_Pos _U_(0) /**< (TC_FMR) Enable Compare Fault Channel 0 Position */ +#define TC_FMR_ENCF0_Msk (_U_(0x1) << TC_FMR_ENCF0_Pos) /**< (TC_FMR) Enable Compare Fault Channel 0 Mask */ +#define TC_FMR_ENCF0(value) (TC_FMR_ENCF0_Msk & ((value) << TC_FMR_ENCF0_Pos)) +#define TC_FMR_ENCF1_Pos _U_(1) /**< (TC_FMR) Enable Compare Fault Channel 1 Position */ +#define TC_FMR_ENCF1_Msk (_U_(0x1) << TC_FMR_ENCF1_Pos) /**< (TC_FMR) Enable Compare Fault Channel 1 Mask */ +#define TC_FMR_ENCF1(value) (TC_FMR_ENCF1_Msk & ((value) << TC_FMR_ENCF1_Pos)) +#define TC_FMR_Msk _U_(0x00000003) /**< (TC_FMR) Register Mask */ + +#define TC_FMR_ENCF_Pos _U_(0) /**< (TC_FMR Position) Enable Compare Fault Channel x */ +#define TC_FMR_ENCF_Msk (_U_(0x3) << TC_FMR_ENCF_Pos) /**< (TC_FMR Mask) ENCF */ +#define TC_FMR_ENCF(value) (TC_FMR_ENCF_Msk & ((value) << TC_FMR_ENCF_Pos)) + +/* -------- TC_WPMR : (TC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN_Pos _U_(0) /**< (TC_WPMR) Write Protection Enable Position */ +#define TC_WPMR_WPEN_Msk (_U_(0x1) << TC_WPMR_WPEN_Pos) /**< (TC_WPMR) Write Protection Enable Mask */ +#define TC_WPMR_WPEN(value) (TC_WPMR_WPEN_Msk & ((value) << TC_WPMR_WPEN_Pos)) +#define TC_WPMR_WPKEY_Pos _U_(8) /**< (TC_WPMR) Write Protection Key Position */ +#define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Write Protection Key Mask */ +#define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) +#define TC_WPMR_WPKEY_PASSWD_Val _U_(0x54494D) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +#define TC_WPMR_WPKEY_PASSWD (TC_WPMR_WPKEY_PASSWD_Val << TC_WPMR_WPKEY_Pos) /**< (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ +#define TC_WPMR_Msk _U_(0xFFFFFF01) /**< (TC_WPMR) Register Mask */ + + +/** \brief TC register offsets definitions */ +#define TC_CCR_REG_OFST (0x00) /**< (TC_CCR) Channel Control Register (channel = 0) Offset */ +#define TC_CMR_REG_OFST (0x04) /**< (TC_CMR) Channel Mode Register (channel = 0) Offset */ +#define TC_SMMR_REG_OFST (0x08) /**< (TC_SMMR) Stepper Motor Mode Register (channel = 0) Offset */ +#define TC_RAB_REG_OFST (0x0C) /**< (TC_RAB) Register AB (channel = 0) Offset */ +#define TC_CV_REG_OFST (0x10) /**< (TC_CV) Counter Value (channel = 0) Offset */ +#define TC_RA_REG_OFST (0x14) /**< (TC_RA) Register A (channel = 0) Offset */ +#define TC_RB_REG_OFST (0x18) /**< (TC_RB) Register B (channel = 0) Offset */ +#define TC_RC_REG_OFST (0x1C) /**< (TC_RC) Register C (channel = 0) Offset */ +#define TC_SR_REG_OFST (0x20) /**< (TC_SR) Status Register (channel = 0) Offset */ +#define TC_IER_REG_OFST (0x24) /**< (TC_IER) Interrupt Enable Register (channel = 0) Offset */ +#define TC_IDR_REG_OFST (0x28) /**< (TC_IDR) Interrupt Disable Register (channel = 0) Offset */ +#define TC_IMR_REG_OFST (0x2C) /**< (TC_IMR) Interrupt Mask Register (channel = 0) Offset */ +#define TC_EMR_REG_OFST (0x30) /**< (TC_EMR) Extended Mode Register (channel = 0) Offset */ +#define TC_BCR_REG_OFST (0xC0) /**< (TC_BCR) Block Control Register Offset */ +#define TC_BMR_REG_OFST (0xC4) /**< (TC_BMR) Block Mode Register Offset */ +#define TC_QIER_REG_OFST (0xC8) /**< (TC_QIER) QDEC Interrupt Enable Register Offset */ +#define TC_QIDR_REG_OFST (0xCC) /**< (TC_QIDR) QDEC Interrupt Disable Register Offset */ +#define TC_QIMR_REG_OFST (0xD0) /**< (TC_QIMR) QDEC Interrupt Mask Register Offset */ +#define TC_QISR_REG_OFST (0xD4) /**< (TC_QISR) QDEC Interrupt Status Register Offset */ +#define TC_FMR_REG_OFST (0xD8) /**< (TC_FMR) Fault Mode Register Offset */ +#define TC_WPMR_REG_OFST (0xE4) /**< (TC_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TC_CHANNEL register API structure */ +typedef struct +{ + __O uint32_t TC_CCR; /**< Offset: 0x00 ( /W 32) Channel Control Register (channel = 0) */ + __IO uint32_t TC_CMR; /**< Offset: 0x04 (R/W 32) Channel Mode Register (channel = 0) */ + __IO uint32_t TC_SMMR; /**< Offset: 0x08 (R/W 32) Stepper Motor Mode Register (channel = 0) */ + __I uint32_t TC_RAB; /**< Offset: 0x0C (R/ 32) Register AB (channel = 0) */ + __I uint32_t TC_CV; /**< Offset: 0x10 (R/ 32) Counter Value (channel = 0) */ + __IO uint32_t TC_RA; /**< Offset: 0x14 (R/W 32) Register A (channel = 0) */ + __IO uint32_t TC_RB; /**< Offset: 0x18 (R/W 32) Register B (channel = 0) */ + __IO uint32_t TC_RC; /**< Offset: 0x1C (R/W 32) Register C (channel = 0) */ + __I uint32_t TC_SR; /**< Offset: 0x20 (R/ 32) Status Register (channel = 0) */ + __O uint32_t TC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register (channel = 0) */ + __O uint32_t TC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register (channel = 0) */ + __I uint32_t TC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register (channel = 0) */ + __IO uint32_t TC_EMR; /**< Offset: 0x30 (R/W 32) Extended Mode Register (channel = 0) */ + __I uint8_t Reserved1[0x0C]; +} tc_channel_registers_t; + +#define TC_CHANNEL_NUMBER _U_(3) + +/** \brief TC register API structure */ +typedef struct +{ + tc_channel_registers_t TC_CHANNEL[TC_CHANNEL_NUMBER]; /**< Offset: 0x00 Channel Control Register (channel = 0) */ + __O uint32_t TC_BCR; /**< Offset: 0xC0 ( /W 32) Block Control Register */ + __IO uint32_t TC_BMR; /**< Offset: 0xC4 (R/W 32) Block Mode Register */ + __O uint32_t TC_QIER; /**< Offset: 0xC8 ( /W 32) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< Offset: 0xCC ( /W 32) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< Offset: 0xD0 (R/ 32) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< Offset: 0xD4 (R/ 32) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< Offset: 0xD8 (R/W 32) Fault Mode Register */ + __I uint8_t Reserved1[0x08]; + __IO uint32_t TC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} tc_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/trng.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/trng.h new file mode 100644 index 00000000..3f5ac269 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/trng.h @@ -0,0 +1,102 @@ +/** + * \brief Component description for TRNG + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_TRNG_COMPONENT_H_ +#define _SAME70_TRNG_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TRNG */ +/* ************************************************************************** */ + +/* -------- TRNG_CR : (TRNG Offset: 0x00) ( /W 32) Control Register -------- */ +#define TRNG_CR_ENABLE_Pos _U_(0) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Position */ +#define TRNG_CR_ENABLE_Msk (_U_(0x1) << TRNG_CR_ENABLE_Pos) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Mask */ +#define TRNG_CR_ENABLE(value) (TRNG_CR_ENABLE_Msk & ((value) << TRNG_CR_ENABLE_Pos)) +#define TRNG_CR_KEY_Pos _U_(8) /**< (TRNG_CR) Security Key Position */ +#define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Security Key Mask */ +#define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)) +#define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */ +#define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */ +#define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */ + + +/* -------- TRNG_IER : (TRNG Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY_Pos _U_(0) /**< (TRNG_IER) Data Ready Interrupt Enable Position */ +#define TRNG_IER_DATRDY_Msk (_U_(0x1) << TRNG_IER_DATRDY_Pos) /**< (TRNG_IER) Data Ready Interrupt Enable Mask */ +#define TRNG_IER_DATRDY(value) (TRNG_IER_DATRDY_Msk & ((value) << TRNG_IER_DATRDY_Pos)) +#define TRNG_IER_Msk _U_(0x00000001) /**< (TRNG_IER) Register Mask */ + + +/* -------- TRNG_IDR : (TRNG Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY_Pos _U_(0) /**< (TRNG_IDR) Data Ready Interrupt Disable Position */ +#define TRNG_IDR_DATRDY_Msk (_U_(0x1) << TRNG_IDR_DATRDY_Pos) /**< (TRNG_IDR) Data Ready Interrupt Disable Mask */ +#define TRNG_IDR_DATRDY(value) (TRNG_IDR_DATRDY_Msk & ((value) << TRNG_IDR_DATRDY_Pos)) +#define TRNG_IDR_Msk _U_(0x00000001) /**< (TRNG_IDR) Register Mask */ + + +/* -------- TRNG_IMR : (TRNG Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY_Pos _U_(0) /**< (TRNG_IMR) Data Ready Interrupt Mask Position */ +#define TRNG_IMR_DATRDY_Msk (_U_(0x1) << TRNG_IMR_DATRDY_Pos) /**< (TRNG_IMR) Data Ready Interrupt Mask Mask */ +#define TRNG_IMR_DATRDY(value) (TRNG_IMR_DATRDY_Msk & ((value) << TRNG_IMR_DATRDY_Pos)) +#define TRNG_IMR_Msk _U_(0x00000001) /**< (TRNG_IMR) Register Mask */ + + +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY_Pos _U_(0) /**< (TRNG_ISR) Data Ready Position */ +#define TRNG_ISR_DATRDY_Msk (_U_(0x1) << TRNG_ISR_DATRDY_Pos) /**< (TRNG_ISR) Data Ready Mask */ +#define TRNG_ISR_DATRDY(value) (TRNG_ISR_DATRDY_Msk & ((value) << TRNG_ISR_DATRDY_Pos)) +#define TRNG_ISR_Msk _U_(0x00000001) /**< (TRNG_ISR) Register Mask */ + + +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) ( R/ 32) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos _U_(0) /**< (TRNG_ODATA) Output Data Position */ +#define TRNG_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << TRNG_ODATA_ODATA_Pos) /**< (TRNG_ODATA) Output Data Mask */ +#define TRNG_ODATA_ODATA(value) (TRNG_ODATA_ODATA_Msk & ((value) << TRNG_ODATA_ODATA_Pos)) +#define TRNG_ODATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_ODATA) Register Mask */ + + +/** \brief TRNG register offsets definitions */ +#define TRNG_CR_REG_OFST (0x00) /**< (TRNG_CR) Control Register Offset */ +#define TRNG_IER_REG_OFST (0x10) /**< (TRNG_IER) Interrupt Enable Register Offset */ +#define TRNG_IDR_REG_OFST (0x14) /**< (TRNG_IDR) Interrupt Disable Register Offset */ +#define TRNG_IMR_REG_OFST (0x18) /**< (TRNG_IMR) Interrupt Mask Register Offset */ +#define TRNG_ISR_REG_OFST (0x1C) /**< (TRNG_ISR) Interrupt Status Register Offset */ +#define TRNG_ODATA_REG_OFST (0x50) /**< (TRNG_ODATA) Output Data Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TRNG register API structure */ +typedef struct +{ + __O uint32_t TRNG_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __I uint8_t Reserved1[0x0C]; + __O uint32_t TRNG_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ + __I uint8_t Reserved2[0x30]; + __I uint32_t TRNG_ODATA; /**< Offset: 0x50 (R/ 32) Output Data Register */ +} trng_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TRNG_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/twihs.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/twihs.h new file mode 100644 index 00000000..a846d09c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/twihs.h @@ -0,0 +1,526 @@ +/** + * \brief Component description for TWIHS + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_TWIHS_COMPONENT_H_ +#define _SAME70_TWIHS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR TWIHS */ +/* ************************************************************************** */ + +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) ( /W 32) Control Register -------- */ +#define TWIHS_CR_START_Pos _U_(0) /**< (TWIHS_CR) Send a START Condition Position */ +#define TWIHS_CR_START_Msk (_U_(0x1) << TWIHS_CR_START_Pos) /**< (TWIHS_CR) Send a START Condition Mask */ +#define TWIHS_CR_START(value) (TWIHS_CR_START_Msk & ((value) << TWIHS_CR_START_Pos)) +#define TWIHS_CR_STOP_Pos _U_(1) /**< (TWIHS_CR) Send a STOP Condition Position */ +#define TWIHS_CR_STOP_Msk (_U_(0x1) << TWIHS_CR_STOP_Pos) /**< (TWIHS_CR) Send a STOP Condition Mask */ +#define TWIHS_CR_STOP(value) (TWIHS_CR_STOP_Msk & ((value) << TWIHS_CR_STOP_Pos)) +#define TWIHS_CR_MSEN_Pos _U_(2) /**< (TWIHS_CR) TWIHS Master Mode Enabled Position */ +#define TWIHS_CR_MSEN_Msk (_U_(0x1) << TWIHS_CR_MSEN_Pos) /**< (TWIHS_CR) TWIHS Master Mode Enabled Mask */ +#define TWIHS_CR_MSEN(value) (TWIHS_CR_MSEN_Msk & ((value) << TWIHS_CR_MSEN_Pos)) +#define TWIHS_CR_MSDIS_Pos _U_(3) /**< (TWIHS_CR) TWIHS Master Mode Disabled Position */ +#define TWIHS_CR_MSDIS_Msk (_U_(0x1) << TWIHS_CR_MSDIS_Pos) /**< (TWIHS_CR) TWIHS Master Mode Disabled Mask */ +#define TWIHS_CR_MSDIS(value) (TWIHS_CR_MSDIS_Msk & ((value) << TWIHS_CR_MSDIS_Pos)) +#define TWIHS_CR_SVEN_Pos _U_(4) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Position */ +#define TWIHS_CR_SVEN_Msk (_U_(0x1) << TWIHS_CR_SVEN_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Enabled Mask */ +#define TWIHS_CR_SVEN(value) (TWIHS_CR_SVEN_Msk & ((value) << TWIHS_CR_SVEN_Pos)) +#define TWIHS_CR_SVDIS_Pos _U_(5) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Position */ +#define TWIHS_CR_SVDIS_Msk (_U_(0x1) << TWIHS_CR_SVDIS_Pos) /**< (TWIHS_CR) TWIHS Slave Mode Disabled Mask */ +#define TWIHS_CR_SVDIS(value) (TWIHS_CR_SVDIS_Msk & ((value) << TWIHS_CR_SVDIS_Pos)) +#define TWIHS_CR_QUICK_Pos _U_(6) /**< (TWIHS_CR) SMBus Quick Command Position */ +#define TWIHS_CR_QUICK_Msk (_U_(0x1) << TWIHS_CR_QUICK_Pos) /**< (TWIHS_CR) SMBus Quick Command Mask */ +#define TWIHS_CR_QUICK(value) (TWIHS_CR_QUICK_Msk & ((value) << TWIHS_CR_QUICK_Pos)) +#define TWIHS_CR_SWRST_Pos _U_(7) /**< (TWIHS_CR) Software Reset Position */ +#define TWIHS_CR_SWRST_Msk (_U_(0x1) << TWIHS_CR_SWRST_Pos) /**< (TWIHS_CR) Software Reset Mask */ +#define TWIHS_CR_SWRST(value) (TWIHS_CR_SWRST_Msk & ((value) << TWIHS_CR_SWRST_Pos)) +#define TWIHS_CR_HSEN_Pos _U_(8) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Position */ +#define TWIHS_CR_HSEN_Msk (_U_(0x1) << TWIHS_CR_HSEN_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Enabled Mask */ +#define TWIHS_CR_HSEN(value) (TWIHS_CR_HSEN_Msk & ((value) << TWIHS_CR_HSEN_Pos)) +#define TWIHS_CR_HSDIS_Pos _U_(9) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Position */ +#define TWIHS_CR_HSDIS_Msk (_U_(0x1) << TWIHS_CR_HSDIS_Pos) /**< (TWIHS_CR) TWIHS High-Speed Mode Disabled Mask */ +#define TWIHS_CR_HSDIS(value) (TWIHS_CR_HSDIS_Msk & ((value) << TWIHS_CR_HSDIS_Pos)) +#define TWIHS_CR_SMBEN_Pos _U_(10) /**< (TWIHS_CR) SMBus Mode Enabled Position */ +#define TWIHS_CR_SMBEN_Msk (_U_(0x1) << TWIHS_CR_SMBEN_Pos) /**< (TWIHS_CR) SMBus Mode Enabled Mask */ +#define TWIHS_CR_SMBEN(value) (TWIHS_CR_SMBEN_Msk & ((value) << TWIHS_CR_SMBEN_Pos)) +#define TWIHS_CR_SMBDIS_Pos _U_(11) /**< (TWIHS_CR) SMBus Mode Disabled Position */ +#define TWIHS_CR_SMBDIS_Msk (_U_(0x1) << TWIHS_CR_SMBDIS_Pos) /**< (TWIHS_CR) SMBus Mode Disabled Mask */ +#define TWIHS_CR_SMBDIS(value) (TWIHS_CR_SMBDIS_Msk & ((value) << TWIHS_CR_SMBDIS_Pos)) +#define TWIHS_CR_PECEN_Pos _U_(12) /**< (TWIHS_CR) Packet Error Checking Enable Position */ +#define TWIHS_CR_PECEN_Msk (_U_(0x1) << TWIHS_CR_PECEN_Pos) /**< (TWIHS_CR) Packet Error Checking Enable Mask */ +#define TWIHS_CR_PECEN(value) (TWIHS_CR_PECEN_Msk & ((value) << TWIHS_CR_PECEN_Pos)) +#define TWIHS_CR_PECDIS_Pos _U_(13) /**< (TWIHS_CR) Packet Error Checking Disable Position */ +#define TWIHS_CR_PECDIS_Msk (_U_(0x1) << TWIHS_CR_PECDIS_Pos) /**< (TWIHS_CR) Packet Error Checking Disable Mask */ +#define TWIHS_CR_PECDIS(value) (TWIHS_CR_PECDIS_Msk & ((value) << TWIHS_CR_PECDIS_Pos)) +#define TWIHS_CR_PECRQ_Pos _U_(14) /**< (TWIHS_CR) PEC Request Position */ +#define TWIHS_CR_PECRQ_Msk (_U_(0x1) << TWIHS_CR_PECRQ_Pos) /**< (TWIHS_CR) PEC Request Mask */ +#define TWIHS_CR_PECRQ(value) (TWIHS_CR_PECRQ_Msk & ((value) << TWIHS_CR_PECRQ_Pos)) +#define TWIHS_CR_CLEAR_Pos _U_(15) /**< (TWIHS_CR) Bus CLEAR Command Position */ +#define TWIHS_CR_CLEAR_Msk (_U_(0x1) << TWIHS_CR_CLEAR_Pos) /**< (TWIHS_CR) Bus CLEAR Command Mask */ +#define TWIHS_CR_CLEAR(value) (TWIHS_CR_CLEAR_Msk & ((value) << TWIHS_CR_CLEAR_Pos)) +#define TWIHS_CR_ACMEN_Pos _U_(16) /**< (TWIHS_CR) Alternative Command Mode Enable Position */ +#define TWIHS_CR_ACMEN_Msk (_U_(0x1) << TWIHS_CR_ACMEN_Pos) /**< (TWIHS_CR) Alternative Command Mode Enable Mask */ +#define TWIHS_CR_ACMEN(value) (TWIHS_CR_ACMEN_Msk & ((value) << TWIHS_CR_ACMEN_Pos)) +#define TWIHS_CR_ACMDIS_Pos _U_(17) /**< (TWIHS_CR) Alternative Command Mode Disable Position */ +#define TWIHS_CR_ACMDIS_Msk (_U_(0x1) << TWIHS_CR_ACMDIS_Pos) /**< (TWIHS_CR) Alternative Command Mode Disable Mask */ +#define TWIHS_CR_ACMDIS(value) (TWIHS_CR_ACMDIS_Msk & ((value) << TWIHS_CR_ACMDIS_Pos)) +#define TWIHS_CR_THRCLR_Pos _U_(24) /**< (TWIHS_CR) Transmit Holding Register Clear Position */ +#define TWIHS_CR_THRCLR_Msk (_U_(0x1) << TWIHS_CR_THRCLR_Pos) /**< (TWIHS_CR) Transmit Holding Register Clear Mask */ +#define TWIHS_CR_THRCLR(value) (TWIHS_CR_THRCLR_Msk & ((value) << TWIHS_CR_THRCLR_Pos)) +#define TWIHS_CR_LOCKCLR_Pos _U_(26) /**< (TWIHS_CR) Lock Clear Position */ +#define TWIHS_CR_LOCKCLR_Msk (_U_(0x1) << TWIHS_CR_LOCKCLR_Pos) /**< (TWIHS_CR) Lock Clear Mask */ +#define TWIHS_CR_LOCKCLR(value) (TWIHS_CR_LOCKCLR_Msk & ((value) << TWIHS_CR_LOCKCLR_Pos)) +#define TWIHS_CR_FIFOEN_Pos _U_(28) /**< (TWIHS_CR) FIFO Enable Position */ +#define TWIHS_CR_FIFOEN_Msk (_U_(0x1) << TWIHS_CR_FIFOEN_Pos) /**< (TWIHS_CR) FIFO Enable Mask */ +#define TWIHS_CR_FIFOEN(value) (TWIHS_CR_FIFOEN_Msk & ((value) << TWIHS_CR_FIFOEN_Pos)) +#define TWIHS_CR_FIFODIS_Pos _U_(29) /**< (TWIHS_CR) FIFO Disable Position */ +#define TWIHS_CR_FIFODIS_Msk (_U_(0x1) << TWIHS_CR_FIFODIS_Pos) /**< (TWIHS_CR) FIFO Disable Mask */ +#define TWIHS_CR_FIFODIS(value) (TWIHS_CR_FIFODIS_Msk & ((value) << TWIHS_CR_FIFODIS_Pos)) +#define TWIHS_CR_Msk _U_(0x3503FFFF) /**< (TWIHS_CR) Register Mask */ + + +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) (R/W 32) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos _U_(8) /**< (TWIHS_MMR) Internal Device Address Size Position */ +#define TWIHS_MMR_IADRSZ_Msk (_U_(0x3) << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Internal Device Address Size Mask */ +#define TWIHS_MMR_IADRSZ(value) (TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)) +#define TWIHS_MMR_IADRSZ_NONE_Val _U_(0x0) /**< (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE_Val _U_(0x1) /**< (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE_Val _U_(0x2) /**< (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE_Val _U_(0x3) /**< (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_IADRSZ_NONE (TWIHS_MMR_IADRSZ_NONE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) No internal device address Position */ +#define TWIHS_MMR_IADRSZ_1_BYTE (TWIHS_MMR_IADRSZ_1_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) One-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_2_BYTE (TWIHS_MMR_IADRSZ_2_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Two-byte internal device address Position */ +#define TWIHS_MMR_IADRSZ_3_BYTE (TWIHS_MMR_IADRSZ_3_BYTE_Val << TWIHS_MMR_IADRSZ_Pos) /**< (TWIHS_MMR) Three-byte internal device address Position */ +#define TWIHS_MMR_MREAD_Pos _U_(12) /**< (TWIHS_MMR) Master Read Direction Position */ +#define TWIHS_MMR_MREAD_Msk (_U_(0x1) << TWIHS_MMR_MREAD_Pos) /**< (TWIHS_MMR) Master Read Direction Mask */ +#define TWIHS_MMR_MREAD(value) (TWIHS_MMR_MREAD_Msk & ((value) << TWIHS_MMR_MREAD_Pos)) +#define TWIHS_MMR_DADR_Pos _U_(16) /**< (TWIHS_MMR) Device Address Position */ +#define TWIHS_MMR_DADR_Msk (_U_(0x7F) << TWIHS_MMR_DADR_Pos) /**< (TWIHS_MMR) Device Address Mask */ +#define TWIHS_MMR_DADR(value) (TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)) +#define TWIHS_MMR_Msk _U_(0x007F1300) /**< (TWIHS_MMR) Register Mask */ + + +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) (R/W 32) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN_Pos _U_(0) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Position */ +#define TWIHS_SMR_NACKEN_Msk (_U_(0x1) << TWIHS_SMR_NACKEN_Pos) /**< (TWIHS_SMR) Slave Receiver Data Phase NACK enable Mask */ +#define TWIHS_SMR_NACKEN(value) (TWIHS_SMR_NACKEN_Msk & ((value) << TWIHS_SMR_NACKEN_Pos)) +#define TWIHS_SMR_SMDA_Pos _U_(2) /**< (TWIHS_SMR) SMBus Default Address Position */ +#define TWIHS_SMR_SMDA_Msk (_U_(0x1) << TWIHS_SMR_SMDA_Pos) /**< (TWIHS_SMR) SMBus Default Address Mask */ +#define TWIHS_SMR_SMDA(value) (TWIHS_SMR_SMDA_Msk & ((value) << TWIHS_SMR_SMDA_Pos)) +#define TWIHS_SMR_SMHH_Pos _U_(3) /**< (TWIHS_SMR) SMBus Host Header Position */ +#define TWIHS_SMR_SMHH_Msk (_U_(0x1) << TWIHS_SMR_SMHH_Pos) /**< (TWIHS_SMR) SMBus Host Header Mask */ +#define TWIHS_SMR_SMHH(value) (TWIHS_SMR_SMHH_Msk & ((value) << TWIHS_SMR_SMHH_Pos)) +#define TWIHS_SMR_SCLWSDIS_Pos _U_(6) /**< (TWIHS_SMR) Clock Wait State Disable Position */ +#define TWIHS_SMR_SCLWSDIS_Msk (_U_(0x1) << TWIHS_SMR_SCLWSDIS_Pos) /**< (TWIHS_SMR) Clock Wait State Disable Mask */ +#define TWIHS_SMR_SCLWSDIS(value) (TWIHS_SMR_SCLWSDIS_Msk & ((value) << TWIHS_SMR_SCLWSDIS_Pos)) +#define TWIHS_SMR_MASK_Pos _U_(8) /**< (TWIHS_SMR) Slave Address Mask Position */ +#define TWIHS_SMR_MASK_Msk (_U_(0x7F) << TWIHS_SMR_MASK_Pos) /**< (TWIHS_SMR) Slave Address Mask Mask */ +#define TWIHS_SMR_MASK(value) (TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)) +#define TWIHS_SMR_SADR_Pos _U_(16) /**< (TWIHS_SMR) Slave Address Position */ +#define TWIHS_SMR_SADR_Msk (_U_(0x7F) << TWIHS_SMR_SADR_Pos) /**< (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_SADR(value) (TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)) +#define TWIHS_SMR_SADR1EN_Pos _U_(28) /**< (TWIHS_SMR) Slave Address 1 Enable Position */ +#define TWIHS_SMR_SADR1EN_Msk (_U_(0x1) << TWIHS_SMR_SADR1EN_Pos) /**< (TWIHS_SMR) Slave Address 1 Enable Mask */ +#define TWIHS_SMR_SADR1EN(value) (TWIHS_SMR_SADR1EN_Msk & ((value) << TWIHS_SMR_SADR1EN_Pos)) +#define TWIHS_SMR_SADR2EN_Pos _U_(29) /**< (TWIHS_SMR) Slave Address 2 Enable Position */ +#define TWIHS_SMR_SADR2EN_Msk (_U_(0x1) << TWIHS_SMR_SADR2EN_Pos) /**< (TWIHS_SMR) Slave Address 2 Enable Mask */ +#define TWIHS_SMR_SADR2EN(value) (TWIHS_SMR_SADR2EN_Msk & ((value) << TWIHS_SMR_SADR2EN_Pos)) +#define TWIHS_SMR_SADR3EN_Pos _U_(30) /**< (TWIHS_SMR) Slave Address 3 Enable Position */ +#define TWIHS_SMR_SADR3EN_Msk (_U_(0x1) << TWIHS_SMR_SADR3EN_Pos) /**< (TWIHS_SMR) Slave Address 3 Enable Mask */ +#define TWIHS_SMR_SADR3EN(value) (TWIHS_SMR_SADR3EN_Msk & ((value) << TWIHS_SMR_SADR3EN_Pos)) +#define TWIHS_SMR_DATAMEN_Pos _U_(31) /**< (TWIHS_SMR) Data Matching Enable Position */ +#define TWIHS_SMR_DATAMEN_Msk (_U_(0x1) << TWIHS_SMR_DATAMEN_Pos) /**< (TWIHS_SMR) Data Matching Enable Mask */ +#define TWIHS_SMR_DATAMEN(value) (TWIHS_SMR_DATAMEN_Msk & ((value) << TWIHS_SMR_DATAMEN_Pos)) +#define TWIHS_SMR_Msk _U_(0xF07F7F4D) /**< (TWIHS_SMR) Register Mask */ + + +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) (R/W 32) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos _U_(0) /**< (TWIHS_IADR) Internal Address Position */ +#define TWIHS_IADR_IADR_Msk (_U_(0xFFFFFF) << TWIHS_IADR_IADR_Pos) /**< (TWIHS_IADR) Internal Address Mask */ +#define TWIHS_IADR_IADR(value) (TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)) +#define TWIHS_IADR_Msk _U_(0x00FFFFFF) /**< (TWIHS_IADR) Register Mask */ + + +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) (R/W 32) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos _U_(0) /**< (TWIHS_CWGR) Clock Low Divider Position */ +#define TWIHS_CWGR_CLDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CLDIV_Pos) /**< (TWIHS_CWGR) Clock Low Divider Mask */ +#define TWIHS_CWGR_CLDIV(value) (TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)) +#define TWIHS_CWGR_CHDIV_Pos _U_(8) /**< (TWIHS_CWGR) Clock High Divider Position */ +#define TWIHS_CWGR_CHDIV_Msk (_U_(0xFF) << TWIHS_CWGR_CHDIV_Pos) /**< (TWIHS_CWGR) Clock High Divider Mask */ +#define TWIHS_CWGR_CHDIV(value) (TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)) +#define TWIHS_CWGR_CKDIV_Pos _U_(16) /**< (TWIHS_CWGR) Clock Divider Position */ +#define TWIHS_CWGR_CKDIV_Msk (_U_(0x7) << TWIHS_CWGR_CKDIV_Pos) /**< (TWIHS_CWGR) Clock Divider Mask */ +#define TWIHS_CWGR_CKDIV(value) (TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)) +#define TWIHS_CWGR_HOLD_Pos _U_(24) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Position */ +#define TWIHS_CWGR_HOLD_Msk (_U_(0x3F) << TWIHS_CWGR_HOLD_Pos) /**< (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling Mask */ +#define TWIHS_CWGR_HOLD(value) (TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)) +#define TWIHS_CWGR_Msk _U_(0x3F07FFFF) /**< (TWIHS_CWGR) Register Mask */ + + +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) ( R/ 32) Status Register -------- */ +#define TWIHS_SR_TXCOMP_Pos _U_(0) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXCOMP_Msk (_U_(0x1) << TWIHS_SR_TXCOMP_Pos) /**< (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXCOMP(value) (TWIHS_SR_TXCOMP_Msk & ((value) << TWIHS_SR_TXCOMP_Pos)) +#define TWIHS_SR_RXRDY_Pos _U_(1) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Position */ +#define TWIHS_SR_RXRDY_Msk (_U_(0x1) << TWIHS_SR_RXRDY_Pos) /**< (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) Mask */ +#define TWIHS_SR_RXRDY(value) (TWIHS_SR_RXRDY_Msk & ((value) << TWIHS_SR_RXRDY_Pos)) +#define TWIHS_SR_TXRDY_Pos _U_(2) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Position */ +#define TWIHS_SR_TXRDY_Msk (_U_(0x1) << TWIHS_SR_TXRDY_Pos) /**< (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) Mask */ +#define TWIHS_SR_TXRDY(value) (TWIHS_SR_TXRDY_Msk & ((value) << TWIHS_SR_TXRDY_Pos)) +#define TWIHS_SR_SVREAD_Pos _U_(3) /**< (TWIHS_SR) Slave Read Position */ +#define TWIHS_SR_SVREAD_Msk (_U_(0x1) << TWIHS_SR_SVREAD_Pos) /**< (TWIHS_SR) Slave Read Mask */ +#define TWIHS_SR_SVREAD(value) (TWIHS_SR_SVREAD_Msk & ((value) << TWIHS_SR_SVREAD_Pos)) +#define TWIHS_SR_SVACC_Pos _U_(4) /**< (TWIHS_SR) Slave Access Position */ +#define TWIHS_SR_SVACC_Msk (_U_(0x1) << TWIHS_SR_SVACC_Pos) /**< (TWIHS_SR) Slave Access Mask */ +#define TWIHS_SR_SVACC(value) (TWIHS_SR_SVACC_Msk & ((value) << TWIHS_SR_SVACC_Pos)) +#define TWIHS_SR_GACC_Pos _U_(5) /**< (TWIHS_SR) General Call Access (cleared on read) Position */ +#define TWIHS_SR_GACC_Msk (_U_(0x1) << TWIHS_SR_GACC_Pos) /**< (TWIHS_SR) General Call Access (cleared on read) Mask */ +#define TWIHS_SR_GACC(value) (TWIHS_SR_GACC_Msk & ((value) << TWIHS_SR_GACC_Pos)) +#define TWIHS_SR_OVRE_Pos _U_(6) /**< (TWIHS_SR) Overrun Error (cleared on read) Position */ +#define TWIHS_SR_OVRE_Msk (_U_(0x1) << TWIHS_SR_OVRE_Pos) /**< (TWIHS_SR) Overrun Error (cleared on read) Mask */ +#define TWIHS_SR_OVRE(value) (TWIHS_SR_OVRE_Msk & ((value) << TWIHS_SR_OVRE_Pos)) +#define TWIHS_SR_UNRE_Pos _U_(7) /**< (TWIHS_SR) Underrun Error (cleared on read) Position */ +#define TWIHS_SR_UNRE_Msk (_U_(0x1) << TWIHS_SR_UNRE_Pos) /**< (TWIHS_SR) Underrun Error (cleared on read) Mask */ +#define TWIHS_SR_UNRE(value) (TWIHS_SR_UNRE_Msk & ((value) << TWIHS_SR_UNRE_Pos)) +#define TWIHS_SR_NACK_Pos _U_(8) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Position */ +#define TWIHS_SR_NACK_Msk (_U_(0x1) << TWIHS_SR_NACK_Pos) /**< (TWIHS_SR) Not Acknowledged (cleared on read) Mask */ +#define TWIHS_SR_NACK(value) (TWIHS_SR_NACK_Msk & ((value) << TWIHS_SR_NACK_Pos)) +#define TWIHS_SR_ARBLST_Pos _U_(9) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Position */ +#define TWIHS_SR_ARBLST_Msk (_U_(0x1) << TWIHS_SR_ARBLST_Pos) /**< (TWIHS_SR) Arbitration Lost (cleared on read) Mask */ +#define TWIHS_SR_ARBLST(value) (TWIHS_SR_ARBLST_Msk & ((value) << TWIHS_SR_ARBLST_Pos)) +#define TWIHS_SR_SCLWS_Pos _U_(10) /**< (TWIHS_SR) Clock Wait State Position */ +#define TWIHS_SR_SCLWS_Msk (_U_(0x1) << TWIHS_SR_SCLWS_Pos) /**< (TWIHS_SR) Clock Wait State Mask */ +#define TWIHS_SR_SCLWS(value) (TWIHS_SR_SCLWS_Msk & ((value) << TWIHS_SR_SCLWS_Pos)) +#define TWIHS_SR_EOSACC_Pos _U_(11) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Position */ +#define TWIHS_SR_EOSACC_Msk (_U_(0x1) << TWIHS_SR_EOSACC_Pos) /**< (TWIHS_SR) End Of Slave Access (cleared on read) Mask */ +#define TWIHS_SR_EOSACC(value) (TWIHS_SR_EOSACC_Msk & ((value) << TWIHS_SR_EOSACC_Pos)) +#define TWIHS_SR_MCACK_Pos _U_(16) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Position */ +#define TWIHS_SR_MCACK_Msk (_U_(0x1) << TWIHS_SR_MCACK_Pos) /**< (TWIHS_SR) Master Code Acknowledge (cleared on read) Mask */ +#define TWIHS_SR_MCACK(value) (TWIHS_SR_MCACK_Msk & ((value) << TWIHS_SR_MCACK_Pos)) +#define TWIHS_SR_TOUT_Pos _U_(18) /**< (TWIHS_SR) Timeout Error (cleared on read) Position */ +#define TWIHS_SR_TOUT_Msk (_U_(0x1) << TWIHS_SR_TOUT_Pos) /**< (TWIHS_SR) Timeout Error (cleared on read) Mask */ +#define TWIHS_SR_TOUT(value) (TWIHS_SR_TOUT_Msk & ((value) << TWIHS_SR_TOUT_Pos)) +#define TWIHS_SR_PECERR_Pos _U_(19) /**< (TWIHS_SR) PEC Error (cleared on read) Position */ +#define TWIHS_SR_PECERR_Msk (_U_(0x1) << TWIHS_SR_PECERR_Pos) /**< (TWIHS_SR) PEC Error (cleared on read) Mask */ +#define TWIHS_SR_PECERR(value) (TWIHS_SR_PECERR_Msk & ((value) << TWIHS_SR_PECERR_Pos)) +#define TWIHS_SR_SMBDAM_Pos _U_(20) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBDAM_Msk (_U_(0x1) << TWIHS_SR_SMBDAM_Pos) /**< (TWIHS_SR) SMBus Default Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBDAM(value) (TWIHS_SR_SMBDAM_Msk & ((value) << TWIHS_SR_SMBDAM_Pos)) +#define TWIHS_SR_SMBHHM_Pos _U_(21) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Position */ +#define TWIHS_SR_SMBHHM_Msk (_U_(0x1) << TWIHS_SR_SMBHHM_Pos) /**< (TWIHS_SR) SMBus Host Header Address Match (cleared on read) Mask */ +#define TWIHS_SR_SMBHHM(value) (TWIHS_SR_SMBHHM_Msk & ((value) << TWIHS_SR_SMBHHM_Pos)) +#define TWIHS_SR_SCL_Pos _U_(24) /**< (TWIHS_SR) SCL Line Value Position */ +#define TWIHS_SR_SCL_Msk (_U_(0x1) << TWIHS_SR_SCL_Pos) /**< (TWIHS_SR) SCL Line Value Mask */ +#define TWIHS_SR_SCL(value) (TWIHS_SR_SCL_Msk & ((value) << TWIHS_SR_SCL_Pos)) +#define TWIHS_SR_SDA_Pos _U_(25) /**< (TWIHS_SR) SDA Line Value Position */ +#define TWIHS_SR_SDA_Msk (_U_(0x1) << TWIHS_SR_SDA_Pos) /**< (TWIHS_SR) SDA Line Value Mask */ +#define TWIHS_SR_SDA(value) (TWIHS_SR_SDA_Msk & ((value) << TWIHS_SR_SDA_Pos)) +#define TWIHS_SR_Msk _U_(0x033D0FFF) /**< (TWIHS_SR) Register Mask */ + + +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP_Pos _U_(0) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Position */ +#define TWIHS_IER_TXCOMP_Msk (_U_(0x1) << TWIHS_IER_TXCOMP_Pos) /**< (TWIHS_IER) Transmission Completed Interrupt Enable Mask */ +#define TWIHS_IER_TXCOMP(value) (TWIHS_IER_TXCOMP_Msk & ((value) << TWIHS_IER_TXCOMP_Pos)) +#define TWIHS_IER_RXRDY_Pos _U_(1) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_RXRDY_Msk (_U_(0x1) << TWIHS_IER_RXRDY_Pos) /**< (TWIHS_IER) Receive Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_RXRDY(value) (TWIHS_IER_RXRDY_Msk & ((value) << TWIHS_IER_RXRDY_Pos)) +#define TWIHS_IER_TXRDY_Pos _U_(2) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Position */ +#define TWIHS_IER_TXRDY_Msk (_U_(0x1) << TWIHS_IER_TXRDY_Pos) /**< (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable Mask */ +#define TWIHS_IER_TXRDY(value) (TWIHS_IER_TXRDY_Msk & ((value) << TWIHS_IER_TXRDY_Pos)) +#define TWIHS_IER_SVACC_Pos _U_(4) /**< (TWIHS_IER) Slave Access Interrupt Enable Position */ +#define TWIHS_IER_SVACC_Msk (_U_(0x1) << TWIHS_IER_SVACC_Pos) /**< (TWIHS_IER) Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_SVACC(value) (TWIHS_IER_SVACC_Msk & ((value) << TWIHS_IER_SVACC_Pos)) +#define TWIHS_IER_GACC_Pos _U_(5) /**< (TWIHS_IER) General Call Access Interrupt Enable Position */ +#define TWIHS_IER_GACC_Msk (_U_(0x1) << TWIHS_IER_GACC_Pos) /**< (TWIHS_IER) General Call Access Interrupt Enable Mask */ +#define TWIHS_IER_GACC(value) (TWIHS_IER_GACC_Msk & ((value) << TWIHS_IER_GACC_Pos)) +#define TWIHS_IER_OVRE_Pos _U_(6) /**< (TWIHS_IER) Overrun Error Interrupt Enable Position */ +#define TWIHS_IER_OVRE_Msk (_U_(0x1) << TWIHS_IER_OVRE_Pos) /**< (TWIHS_IER) Overrun Error Interrupt Enable Mask */ +#define TWIHS_IER_OVRE(value) (TWIHS_IER_OVRE_Msk & ((value) << TWIHS_IER_OVRE_Pos)) +#define TWIHS_IER_UNRE_Pos _U_(7) /**< (TWIHS_IER) Underrun Error Interrupt Enable Position */ +#define TWIHS_IER_UNRE_Msk (_U_(0x1) << TWIHS_IER_UNRE_Pos) /**< (TWIHS_IER) Underrun Error Interrupt Enable Mask */ +#define TWIHS_IER_UNRE(value) (TWIHS_IER_UNRE_Msk & ((value) << TWIHS_IER_UNRE_Pos)) +#define TWIHS_IER_NACK_Pos _U_(8) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_NACK_Msk (_U_(0x1) << TWIHS_IER_NACK_Pos) /**< (TWIHS_IER) Not Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_NACK(value) (TWIHS_IER_NACK_Msk & ((value) << TWIHS_IER_NACK_Pos)) +#define TWIHS_IER_ARBLST_Pos _U_(9) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Position */ +#define TWIHS_IER_ARBLST_Msk (_U_(0x1) << TWIHS_IER_ARBLST_Pos) /**< (TWIHS_IER) Arbitration Lost Interrupt Enable Mask */ +#define TWIHS_IER_ARBLST(value) (TWIHS_IER_ARBLST_Msk & ((value) << TWIHS_IER_ARBLST_Pos)) +#define TWIHS_IER_SCL_WS_Pos _U_(10) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Position */ +#define TWIHS_IER_SCL_WS_Msk (_U_(0x1) << TWIHS_IER_SCL_WS_Pos) /**< (TWIHS_IER) Clock Wait State Interrupt Enable Mask */ +#define TWIHS_IER_SCL_WS(value) (TWIHS_IER_SCL_WS_Msk & ((value) << TWIHS_IER_SCL_WS_Pos)) +#define TWIHS_IER_EOSACC_Pos _U_(11) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Position */ +#define TWIHS_IER_EOSACC_Msk (_U_(0x1) << TWIHS_IER_EOSACC_Pos) /**< (TWIHS_IER) End Of Slave Access Interrupt Enable Mask */ +#define TWIHS_IER_EOSACC(value) (TWIHS_IER_EOSACC_Msk & ((value) << TWIHS_IER_EOSACC_Pos)) +#define TWIHS_IER_MCACK_Pos _U_(16) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Position */ +#define TWIHS_IER_MCACK_Msk (_U_(0x1) << TWIHS_IER_MCACK_Pos) /**< (TWIHS_IER) Master Code Acknowledge Interrupt Enable Mask */ +#define TWIHS_IER_MCACK(value) (TWIHS_IER_MCACK_Msk & ((value) << TWIHS_IER_MCACK_Pos)) +#define TWIHS_IER_TOUT_Pos _U_(18) /**< (TWIHS_IER) Timeout Error Interrupt Enable Position */ +#define TWIHS_IER_TOUT_Msk (_U_(0x1) << TWIHS_IER_TOUT_Pos) /**< (TWIHS_IER) Timeout Error Interrupt Enable Mask */ +#define TWIHS_IER_TOUT(value) (TWIHS_IER_TOUT_Msk & ((value) << TWIHS_IER_TOUT_Pos)) +#define TWIHS_IER_PECERR_Pos _U_(19) /**< (TWIHS_IER) PEC Error Interrupt Enable Position */ +#define TWIHS_IER_PECERR_Msk (_U_(0x1) << TWIHS_IER_PECERR_Pos) /**< (TWIHS_IER) PEC Error Interrupt Enable Mask */ +#define TWIHS_IER_PECERR(value) (TWIHS_IER_PECERR_Msk & ((value) << TWIHS_IER_PECERR_Pos)) +#define TWIHS_IER_SMBDAM_Pos _U_(20) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBDAM_Msk (_U_(0x1) << TWIHS_IER_SMBDAM_Pos) /**< (TWIHS_IER) SMBus Default Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBDAM(value) (TWIHS_IER_SMBDAM_Msk & ((value) << TWIHS_IER_SMBDAM_Pos)) +#define TWIHS_IER_SMBHHM_Pos _U_(21) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Position */ +#define TWIHS_IER_SMBHHM_Msk (_U_(0x1) << TWIHS_IER_SMBHHM_Pos) /**< (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable Mask */ +#define TWIHS_IER_SMBHHM(value) (TWIHS_IER_SMBHHM_Msk & ((value) << TWIHS_IER_SMBHHM_Pos)) +#define TWIHS_IER_Msk _U_(0x003D0FF7) /**< (TWIHS_IER) Register Mask */ + + +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP_Pos _U_(0) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Position */ +#define TWIHS_IDR_TXCOMP_Msk (_U_(0x1) << TWIHS_IDR_TXCOMP_Pos) /**< (TWIHS_IDR) Transmission Completed Interrupt Disable Mask */ +#define TWIHS_IDR_TXCOMP(value) (TWIHS_IDR_TXCOMP_Msk & ((value) << TWIHS_IDR_TXCOMP_Pos)) +#define TWIHS_IDR_RXRDY_Pos _U_(1) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_RXRDY_Msk (_U_(0x1) << TWIHS_IDR_RXRDY_Pos) /**< (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_RXRDY(value) (TWIHS_IDR_RXRDY_Msk & ((value) << TWIHS_IDR_RXRDY_Pos)) +#define TWIHS_IDR_TXRDY_Pos _U_(2) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Position */ +#define TWIHS_IDR_TXRDY_Msk (_U_(0x1) << TWIHS_IDR_TXRDY_Pos) /**< (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable Mask */ +#define TWIHS_IDR_TXRDY(value) (TWIHS_IDR_TXRDY_Msk & ((value) << TWIHS_IDR_TXRDY_Pos)) +#define TWIHS_IDR_SVACC_Pos _U_(4) /**< (TWIHS_IDR) Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_SVACC_Msk (_U_(0x1) << TWIHS_IDR_SVACC_Pos) /**< (TWIHS_IDR) Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_SVACC(value) (TWIHS_IDR_SVACC_Msk & ((value) << TWIHS_IDR_SVACC_Pos)) +#define TWIHS_IDR_GACC_Pos _U_(5) /**< (TWIHS_IDR) General Call Access Interrupt Disable Position */ +#define TWIHS_IDR_GACC_Msk (_U_(0x1) << TWIHS_IDR_GACC_Pos) /**< (TWIHS_IDR) General Call Access Interrupt Disable Mask */ +#define TWIHS_IDR_GACC(value) (TWIHS_IDR_GACC_Msk & ((value) << TWIHS_IDR_GACC_Pos)) +#define TWIHS_IDR_OVRE_Pos _U_(6) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Position */ +#define TWIHS_IDR_OVRE_Msk (_U_(0x1) << TWIHS_IDR_OVRE_Pos) /**< (TWIHS_IDR) Overrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_OVRE(value) (TWIHS_IDR_OVRE_Msk & ((value) << TWIHS_IDR_OVRE_Pos)) +#define TWIHS_IDR_UNRE_Pos _U_(7) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Position */ +#define TWIHS_IDR_UNRE_Msk (_U_(0x1) << TWIHS_IDR_UNRE_Pos) /**< (TWIHS_IDR) Underrun Error Interrupt Disable Mask */ +#define TWIHS_IDR_UNRE(value) (TWIHS_IDR_UNRE_Msk & ((value) << TWIHS_IDR_UNRE_Pos)) +#define TWIHS_IDR_NACK_Pos _U_(8) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_NACK_Msk (_U_(0x1) << TWIHS_IDR_NACK_Pos) /**< (TWIHS_IDR) Not Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_NACK(value) (TWIHS_IDR_NACK_Msk & ((value) << TWIHS_IDR_NACK_Pos)) +#define TWIHS_IDR_ARBLST_Pos _U_(9) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Position */ +#define TWIHS_IDR_ARBLST_Msk (_U_(0x1) << TWIHS_IDR_ARBLST_Pos) /**< (TWIHS_IDR) Arbitration Lost Interrupt Disable Mask */ +#define TWIHS_IDR_ARBLST(value) (TWIHS_IDR_ARBLST_Msk & ((value) << TWIHS_IDR_ARBLST_Pos)) +#define TWIHS_IDR_SCL_WS_Pos _U_(10) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Position */ +#define TWIHS_IDR_SCL_WS_Msk (_U_(0x1) << TWIHS_IDR_SCL_WS_Pos) /**< (TWIHS_IDR) Clock Wait State Interrupt Disable Mask */ +#define TWIHS_IDR_SCL_WS(value) (TWIHS_IDR_SCL_WS_Msk & ((value) << TWIHS_IDR_SCL_WS_Pos)) +#define TWIHS_IDR_EOSACC_Pos _U_(11) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Position */ +#define TWIHS_IDR_EOSACC_Msk (_U_(0x1) << TWIHS_IDR_EOSACC_Pos) /**< (TWIHS_IDR) End Of Slave Access Interrupt Disable Mask */ +#define TWIHS_IDR_EOSACC(value) (TWIHS_IDR_EOSACC_Msk & ((value) << TWIHS_IDR_EOSACC_Pos)) +#define TWIHS_IDR_MCACK_Pos _U_(16) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Position */ +#define TWIHS_IDR_MCACK_Msk (_U_(0x1) << TWIHS_IDR_MCACK_Pos) /**< (TWIHS_IDR) Master Code Acknowledge Interrupt Disable Mask */ +#define TWIHS_IDR_MCACK(value) (TWIHS_IDR_MCACK_Msk & ((value) << TWIHS_IDR_MCACK_Pos)) +#define TWIHS_IDR_TOUT_Pos _U_(18) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Position */ +#define TWIHS_IDR_TOUT_Msk (_U_(0x1) << TWIHS_IDR_TOUT_Pos) /**< (TWIHS_IDR) Timeout Error Interrupt Disable Mask */ +#define TWIHS_IDR_TOUT(value) (TWIHS_IDR_TOUT_Msk & ((value) << TWIHS_IDR_TOUT_Pos)) +#define TWIHS_IDR_PECERR_Pos _U_(19) /**< (TWIHS_IDR) PEC Error Interrupt Disable Position */ +#define TWIHS_IDR_PECERR_Msk (_U_(0x1) << TWIHS_IDR_PECERR_Pos) /**< (TWIHS_IDR) PEC Error Interrupt Disable Mask */ +#define TWIHS_IDR_PECERR(value) (TWIHS_IDR_PECERR_Msk & ((value) << TWIHS_IDR_PECERR_Pos)) +#define TWIHS_IDR_SMBDAM_Pos _U_(20) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBDAM_Msk (_U_(0x1) << TWIHS_IDR_SMBDAM_Pos) /**< (TWIHS_IDR) SMBus Default Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBDAM(value) (TWIHS_IDR_SMBDAM_Msk & ((value) << TWIHS_IDR_SMBDAM_Pos)) +#define TWIHS_IDR_SMBHHM_Pos _U_(21) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Position */ +#define TWIHS_IDR_SMBHHM_Msk (_U_(0x1) << TWIHS_IDR_SMBHHM_Pos) /**< (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable Mask */ +#define TWIHS_IDR_SMBHHM(value) (TWIHS_IDR_SMBHHM_Msk & ((value) << TWIHS_IDR_SMBHHM_Pos)) +#define TWIHS_IDR_Msk _U_(0x003D0FF7) /**< (TWIHS_IDR) Register Mask */ + + +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP_Pos _U_(0) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Position */ +#define TWIHS_IMR_TXCOMP_Msk (_U_(0x1) << TWIHS_IMR_TXCOMP_Pos) /**< (TWIHS_IMR) Transmission Completed Interrupt Mask Mask */ +#define TWIHS_IMR_TXCOMP(value) (TWIHS_IMR_TXCOMP_Msk & ((value) << TWIHS_IMR_TXCOMP_Pos)) +#define TWIHS_IMR_RXRDY_Pos _U_(1) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_RXRDY_Msk (_U_(0x1) << TWIHS_IMR_RXRDY_Pos) /**< (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_RXRDY(value) (TWIHS_IMR_RXRDY_Msk & ((value) << TWIHS_IMR_RXRDY_Pos)) +#define TWIHS_IMR_TXRDY_Pos _U_(2) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Position */ +#define TWIHS_IMR_TXRDY_Msk (_U_(0x1) << TWIHS_IMR_TXRDY_Pos) /**< (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask Mask */ +#define TWIHS_IMR_TXRDY(value) (TWIHS_IMR_TXRDY_Msk & ((value) << TWIHS_IMR_TXRDY_Pos)) +#define TWIHS_IMR_SVACC_Pos _U_(4) /**< (TWIHS_IMR) Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_SVACC_Msk (_U_(0x1) << TWIHS_IMR_SVACC_Pos) /**< (TWIHS_IMR) Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_SVACC(value) (TWIHS_IMR_SVACC_Msk & ((value) << TWIHS_IMR_SVACC_Pos)) +#define TWIHS_IMR_GACC_Pos _U_(5) /**< (TWIHS_IMR) General Call Access Interrupt Mask Position */ +#define TWIHS_IMR_GACC_Msk (_U_(0x1) << TWIHS_IMR_GACC_Pos) /**< (TWIHS_IMR) General Call Access Interrupt Mask Mask */ +#define TWIHS_IMR_GACC(value) (TWIHS_IMR_GACC_Msk & ((value) << TWIHS_IMR_GACC_Pos)) +#define TWIHS_IMR_OVRE_Pos _U_(6) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Position */ +#define TWIHS_IMR_OVRE_Msk (_U_(0x1) << TWIHS_IMR_OVRE_Pos) /**< (TWIHS_IMR) Overrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_OVRE(value) (TWIHS_IMR_OVRE_Msk & ((value) << TWIHS_IMR_OVRE_Pos)) +#define TWIHS_IMR_UNRE_Pos _U_(7) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Position */ +#define TWIHS_IMR_UNRE_Msk (_U_(0x1) << TWIHS_IMR_UNRE_Pos) /**< (TWIHS_IMR) Underrun Error Interrupt Mask Mask */ +#define TWIHS_IMR_UNRE(value) (TWIHS_IMR_UNRE_Msk & ((value) << TWIHS_IMR_UNRE_Pos)) +#define TWIHS_IMR_NACK_Pos _U_(8) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_NACK_Msk (_U_(0x1) << TWIHS_IMR_NACK_Pos) /**< (TWIHS_IMR) Not Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_NACK(value) (TWIHS_IMR_NACK_Msk & ((value) << TWIHS_IMR_NACK_Pos)) +#define TWIHS_IMR_ARBLST_Pos _U_(9) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Position */ +#define TWIHS_IMR_ARBLST_Msk (_U_(0x1) << TWIHS_IMR_ARBLST_Pos) /**< (TWIHS_IMR) Arbitration Lost Interrupt Mask Mask */ +#define TWIHS_IMR_ARBLST(value) (TWIHS_IMR_ARBLST_Msk & ((value) << TWIHS_IMR_ARBLST_Pos)) +#define TWIHS_IMR_SCL_WS_Pos _U_(10) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Position */ +#define TWIHS_IMR_SCL_WS_Msk (_U_(0x1) << TWIHS_IMR_SCL_WS_Pos) /**< (TWIHS_IMR) Clock Wait State Interrupt Mask Mask */ +#define TWIHS_IMR_SCL_WS(value) (TWIHS_IMR_SCL_WS_Msk & ((value) << TWIHS_IMR_SCL_WS_Pos)) +#define TWIHS_IMR_EOSACC_Pos _U_(11) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Position */ +#define TWIHS_IMR_EOSACC_Msk (_U_(0x1) << TWIHS_IMR_EOSACC_Pos) /**< (TWIHS_IMR) End Of Slave Access Interrupt Mask Mask */ +#define TWIHS_IMR_EOSACC(value) (TWIHS_IMR_EOSACC_Msk & ((value) << TWIHS_IMR_EOSACC_Pos)) +#define TWIHS_IMR_MCACK_Pos _U_(16) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Position */ +#define TWIHS_IMR_MCACK_Msk (_U_(0x1) << TWIHS_IMR_MCACK_Pos) /**< (TWIHS_IMR) Master Code Acknowledge Interrupt Mask Mask */ +#define TWIHS_IMR_MCACK(value) (TWIHS_IMR_MCACK_Msk & ((value) << TWIHS_IMR_MCACK_Pos)) +#define TWIHS_IMR_TOUT_Pos _U_(18) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Position */ +#define TWIHS_IMR_TOUT_Msk (_U_(0x1) << TWIHS_IMR_TOUT_Pos) /**< (TWIHS_IMR) Timeout Error Interrupt Mask Mask */ +#define TWIHS_IMR_TOUT(value) (TWIHS_IMR_TOUT_Msk & ((value) << TWIHS_IMR_TOUT_Pos)) +#define TWIHS_IMR_PECERR_Pos _U_(19) /**< (TWIHS_IMR) PEC Error Interrupt Mask Position */ +#define TWIHS_IMR_PECERR_Msk (_U_(0x1) << TWIHS_IMR_PECERR_Pos) /**< (TWIHS_IMR) PEC Error Interrupt Mask Mask */ +#define TWIHS_IMR_PECERR(value) (TWIHS_IMR_PECERR_Msk & ((value) << TWIHS_IMR_PECERR_Pos)) +#define TWIHS_IMR_SMBDAM_Pos _U_(20) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBDAM_Msk (_U_(0x1) << TWIHS_IMR_SMBDAM_Pos) /**< (TWIHS_IMR) SMBus Default Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBDAM(value) (TWIHS_IMR_SMBDAM_Msk & ((value) << TWIHS_IMR_SMBDAM_Pos)) +#define TWIHS_IMR_SMBHHM_Pos _U_(21) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Position */ +#define TWIHS_IMR_SMBHHM_Msk (_U_(0x1) << TWIHS_IMR_SMBHHM_Pos) /**< (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask Mask */ +#define TWIHS_IMR_SMBHHM(value) (TWIHS_IMR_SMBHHM_Msk & ((value) << TWIHS_IMR_SMBHHM_Pos)) +#define TWIHS_IMR_Msk _U_(0x003D0FF7) /**< (TWIHS_IMR) Register Mask */ + + +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) ( R/ 32) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos _U_(0) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Position */ +#define TWIHS_RHR_RXDATA_Msk (_U_(0xFF) << TWIHS_RHR_RXDATA_Pos) /**< (TWIHS_RHR) Master or Slave Receive Holding Data Mask */ +#define TWIHS_RHR_RXDATA(value) (TWIHS_RHR_RXDATA_Msk & ((value) << TWIHS_RHR_RXDATA_Pos)) +#define TWIHS_RHR_Msk _U_(0x000000FF) /**< (TWIHS_RHR) Register Mask */ + + +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) ( /W 32) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos _U_(0) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Position */ +#define TWIHS_THR_TXDATA_Msk (_U_(0xFF) << TWIHS_THR_TXDATA_Pos) /**< (TWIHS_THR) Master or Slave Transmit Holding Data Mask */ +#define TWIHS_THR_TXDATA(value) (TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)) +#define TWIHS_THR_Msk _U_(0x000000FF) /**< (TWIHS_THR) Register Mask */ + + +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) (R/W 32) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos _U_(0) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Position */ +#define TWIHS_SMBTR_PRESC_Msk (_U_(0xF) << TWIHS_SMBTR_PRESC_Pos) /**< (TWIHS_SMBTR) SMBus Clock Prescaler Mask */ +#define TWIHS_SMBTR_PRESC(value) (TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)) +#define TWIHS_SMBTR_TLOWS_Pos _U_(8) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWS_Pos) /**< (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWS(value) (TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)) +#define TWIHS_SMBTR_TLOWM_Pos _U_(16) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Position */ +#define TWIHS_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIHS_SMBTR_TLOWM_Pos) /**< (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles Mask */ +#define TWIHS_SMBTR_TLOWM(value) (TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)) +#define TWIHS_SMBTR_THMAX_Pos _U_(24) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Position */ +#define TWIHS_SMBTR_THMAX_Msk (_U_(0xFF) << TWIHS_SMBTR_THMAX_Pos) /**< (TWIHS_SMBTR) Clock High Maximum Cycles Mask */ +#define TWIHS_SMBTR_THMAX(value) (TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)) +#define TWIHS_SMBTR_Msk _U_(0xFFFFFF0F) /**< (TWIHS_SMBTR) Register Mask */ + + +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) (R/W 32) Filter Register -------- */ +#define TWIHS_FILTR_FILT_Pos _U_(0) /**< (TWIHS_FILTR) RX Digital Filter Position */ +#define TWIHS_FILTR_FILT_Msk (_U_(0x1) << TWIHS_FILTR_FILT_Pos) /**< (TWIHS_FILTR) RX Digital Filter Mask */ +#define TWIHS_FILTR_FILT(value) (TWIHS_FILTR_FILT_Msk & ((value) << TWIHS_FILTR_FILT_Pos)) +#define TWIHS_FILTR_PADFEN_Pos _U_(1) /**< (TWIHS_FILTR) PAD Filter Enable Position */ +#define TWIHS_FILTR_PADFEN_Msk (_U_(0x1) << TWIHS_FILTR_PADFEN_Pos) /**< (TWIHS_FILTR) PAD Filter Enable Mask */ +#define TWIHS_FILTR_PADFEN(value) (TWIHS_FILTR_PADFEN_Msk & ((value) << TWIHS_FILTR_PADFEN_Pos)) +#define TWIHS_FILTR_PADFCFG_Pos _U_(2) /**< (TWIHS_FILTR) PAD Filter Config Position */ +#define TWIHS_FILTR_PADFCFG_Msk (_U_(0x1) << TWIHS_FILTR_PADFCFG_Pos) /**< (TWIHS_FILTR) PAD Filter Config Mask */ +#define TWIHS_FILTR_PADFCFG(value) (TWIHS_FILTR_PADFCFG_Msk & ((value) << TWIHS_FILTR_PADFCFG_Pos)) +#define TWIHS_FILTR_THRES_Pos _U_(8) /**< (TWIHS_FILTR) Digital Filter Threshold Position */ +#define TWIHS_FILTR_THRES_Msk (_U_(0x7) << TWIHS_FILTR_THRES_Pos) /**< (TWIHS_FILTR) Digital Filter Threshold Mask */ +#define TWIHS_FILTR_THRES(value) (TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)) +#define TWIHS_FILTR_Msk _U_(0x00000707) /**< (TWIHS_FILTR) Register Mask */ + + +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) (R/W 32) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos _U_(0) /**< (TWIHS_SWMR) Slave Address 1 Position */ +#define TWIHS_SWMR_SADR1_Msk (_U_(0x7F) << TWIHS_SWMR_SADR1_Pos) /**< (TWIHS_SWMR) Slave Address 1 Mask */ +#define TWIHS_SWMR_SADR1(value) (TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)) +#define TWIHS_SWMR_SADR2_Pos _U_(8) /**< (TWIHS_SWMR) Slave Address 2 Position */ +#define TWIHS_SWMR_SADR2_Msk (_U_(0x7F) << TWIHS_SWMR_SADR2_Pos) /**< (TWIHS_SWMR) Slave Address 2 Mask */ +#define TWIHS_SWMR_SADR2(value) (TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)) +#define TWIHS_SWMR_SADR3_Pos _U_(16) /**< (TWIHS_SWMR) Slave Address 3 Position */ +#define TWIHS_SWMR_SADR3_Msk (_U_(0x7F) << TWIHS_SWMR_SADR3_Pos) /**< (TWIHS_SWMR) Slave Address 3 Mask */ +#define TWIHS_SWMR_SADR3(value) (TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)) +#define TWIHS_SWMR_DATAM_Pos _U_(24) /**< (TWIHS_SWMR) Data Match Position */ +#define TWIHS_SWMR_DATAM_Msk (_U_(0xFF) << TWIHS_SWMR_DATAM_Pos) /**< (TWIHS_SWMR) Data Match Mask */ +#define TWIHS_SWMR_DATAM(value) (TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)) +#define TWIHS_SWMR_Msk _U_(0xFF7F7F7F) /**< (TWIHS_SWMR) Register Mask */ + + +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN_Pos _U_(0) /**< (TWIHS_WPMR) Write Protection Enable Position */ +#define TWIHS_WPMR_WPEN_Msk (_U_(0x1) << TWIHS_WPMR_WPEN_Pos) /**< (TWIHS_WPMR) Write Protection Enable Mask */ +#define TWIHS_WPMR_WPEN(value) (TWIHS_WPMR_WPEN_Msk & ((value) << TWIHS_WPMR_WPEN_Pos)) +#define TWIHS_WPMR_WPKEY_Pos _U_(8) /**< (TWIHS_WPMR) Write Protection Key Position */ +#define TWIHS_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Write Protection Key Mask */ +#define TWIHS_WPMR_WPKEY(value) (TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)) +#define TWIHS_WPMR_WPKEY_PASSWD_Val _U_(0x545749) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +#define TWIHS_WPMR_WPKEY_PASSWD (TWIHS_WPMR_WPKEY_PASSWD_Val << TWIHS_WPMR_WPKEY_Pos) /**< (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 Position */ +#define TWIHS_WPMR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPMR) Register Mask */ + + +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS_Pos _U_(0) /**< (TWIHS_WPSR) Write Protection Violation Status Position */ +#define TWIHS_WPSR_WPVS_Msk (_U_(0x1) << TWIHS_WPSR_WPVS_Pos) /**< (TWIHS_WPSR) Write Protection Violation Status Mask */ +#define TWIHS_WPSR_WPVS(value) (TWIHS_WPSR_WPVS_Msk & ((value) << TWIHS_WPSR_WPVS_Pos)) +#define TWIHS_WPSR_WPVSRC_Pos _U_(8) /**< (TWIHS_WPSR) Write Protection Violation Source Position */ +#define TWIHS_WPSR_WPVSRC_Msk (_U_(0xFFFFFF) << TWIHS_WPSR_WPVSRC_Pos) /**< (TWIHS_WPSR) Write Protection Violation Source Mask */ +#define TWIHS_WPSR_WPVSRC(value) (TWIHS_WPSR_WPVSRC_Msk & ((value) << TWIHS_WPSR_WPVSRC_Pos)) +#define TWIHS_WPSR_Msk _U_(0xFFFFFF01) /**< (TWIHS_WPSR) Register Mask */ + + +/** \brief TWIHS register offsets definitions */ +#define TWIHS_CR_REG_OFST (0x00) /**< (TWIHS_CR) Control Register Offset */ +#define TWIHS_MMR_REG_OFST (0x04) /**< (TWIHS_MMR) Master Mode Register Offset */ +#define TWIHS_SMR_REG_OFST (0x08) /**< (TWIHS_SMR) Slave Mode Register Offset */ +#define TWIHS_IADR_REG_OFST (0x0C) /**< (TWIHS_IADR) Internal Address Register Offset */ +#define TWIHS_CWGR_REG_OFST (0x10) /**< (TWIHS_CWGR) Clock Waveform Generator Register Offset */ +#define TWIHS_SR_REG_OFST (0x20) /**< (TWIHS_SR) Status Register Offset */ +#define TWIHS_IER_REG_OFST (0x24) /**< (TWIHS_IER) Interrupt Enable Register Offset */ +#define TWIHS_IDR_REG_OFST (0x28) /**< (TWIHS_IDR) Interrupt Disable Register Offset */ +#define TWIHS_IMR_REG_OFST (0x2C) /**< (TWIHS_IMR) Interrupt Mask Register Offset */ +#define TWIHS_RHR_REG_OFST (0x30) /**< (TWIHS_RHR) Receive Holding Register Offset */ +#define TWIHS_THR_REG_OFST (0x34) /**< (TWIHS_THR) Transmit Holding Register Offset */ +#define TWIHS_SMBTR_REG_OFST (0x38) /**< (TWIHS_SMBTR) SMBus Timing Register Offset */ +#define TWIHS_FILTR_REG_OFST (0x44) /**< (TWIHS_FILTR) Filter Register Offset */ +#define TWIHS_SWMR_REG_OFST (0x4C) /**< (TWIHS_SWMR) SleepWalking Matching Register Offset */ +#define TWIHS_WPMR_REG_OFST (0xE4) /**< (TWIHS_WPMR) Write Protection Mode Register Offset */ +#define TWIHS_WPSR_REG_OFST (0xE8) /**< (TWIHS_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TWIHS register API structure */ +typedef struct +{ + __O uint32_t TWIHS_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t TWIHS_MMR; /**< Offset: 0x04 (R/W 32) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< Offset: 0x08 (R/W 32) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< Offset: 0x0C (R/W 32) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< Offset: 0x10 (R/W 32) Clock Waveform Generator Register */ + __I uint8_t Reserved1[0x0C]; + __I uint32_t TWIHS_SR; /**< Offset: 0x20 (R/ 32) Status Register */ + __O uint32_t TWIHS_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< Offset: 0x30 (R/ 32) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< Offset: 0x34 ( /W 32) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< Offset: 0x38 (R/W 32) SMBus Timing Register */ + __I uint8_t Reserved2[0x08]; + __IO uint32_t TWIHS_FILTR; /**< Offset: 0x44 (R/W 32) Filter Register */ + __I uint8_t Reserved3[0x04]; + __IO uint32_t TWIHS_SWMR; /**< Offset: 0x4C (R/W 32) SleepWalking Matching Register */ + __I uint8_t Reserved4[0x94]; + __IO uint32_t TWIHS_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} twihs_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_TWIHS_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/uart.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/uart.h new file mode 100644 index 00000000..4d706a16 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/uart.h @@ -0,0 +1,287 @@ +/** + * \brief Component description for UART + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_UART_COMPONENT_H_ +#define _SAME70_UART_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR UART */ +/* ************************************************************************** */ + +/* -------- UART_CR : (UART Offset: 0x00) ( /W 32) Control Register -------- */ +#define UART_CR_RSTRX_Pos _U_(2) /**< (UART_CR) Reset Receiver Position */ +#define UART_CR_RSTRX_Msk (_U_(0x1) << UART_CR_RSTRX_Pos) /**< (UART_CR) Reset Receiver Mask */ +#define UART_CR_RSTRX(value) (UART_CR_RSTRX_Msk & ((value) << UART_CR_RSTRX_Pos)) +#define UART_CR_RSTTX_Pos _U_(3) /**< (UART_CR) Reset Transmitter Position */ +#define UART_CR_RSTTX_Msk (_U_(0x1) << UART_CR_RSTTX_Pos) /**< (UART_CR) Reset Transmitter Mask */ +#define UART_CR_RSTTX(value) (UART_CR_RSTTX_Msk & ((value) << UART_CR_RSTTX_Pos)) +#define UART_CR_RXEN_Pos _U_(4) /**< (UART_CR) Receiver Enable Position */ +#define UART_CR_RXEN_Msk (_U_(0x1) << UART_CR_RXEN_Pos) /**< (UART_CR) Receiver Enable Mask */ +#define UART_CR_RXEN(value) (UART_CR_RXEN_Msk & ((value) << UART_CR_RXEN_Pos)) +#define UART_CR_RXDIS_Pos _U_(5) /**< (UART_CR) Receiver Disable Position */ +#define UART_CR_RXDIS_Msk (_U_(0x1) << UART_CR_RXDIS_Pos) /**< (UART_CR) Receiver Disable Mask */ +#define UART_CR_RXDIS(value) (UART_CR_RXDIS_Msk & ((value) << UART_CR_RXDIS_Pos)) +#define UART_CR_TXEN_Pos _U_(6) /**< (UART_CR) Transmitter Enable Position */ +#define UART_CR_TXEN_Msk (_U_(0x1) << UART_CR_TXEN_Pos) /**< (UART_CR) Transmitter Enable Mask */ +#define UART_CR_TXEN(value) (UART_CR_TXEN_Msk & ((value) << UART_CR_TXEN_Pos)) +#define UART_CR_TXDIS_Pos _U_(7) /**< (UART_CR) Transmitter Disable Position */ +#define UART_CR_TXDIS_Msk (_U_(0x1) << UART_CR_TXDIS_Pos) /**< (UART_CR) Transmitter Disable Mask */ +#define UART_CR_TXDIS(value) (UART_CR_TXDIS_Msk & ((value) << UART_CR_TXDIS_Pos)) +#define UART_CR_RSTSTA_Pos _U_(8) /**< (UART_CR) Reset Status Position */ +#define UART_CR_RSTSTA_Msk (_U_(0x1) << UART_CR_RSTSTA_Pos) /**< (UART_CR) Reset Status Mask */ +#define UART_CR_RSTSTA(value) (UART_CR_RSTSTA_Msk & ((value) << UART_CR_RSTSTA_Pos)) +#define UART_CR_REQCLR_Pos _U_(12) /**< (UART_CR) Request Clear Position */ +#define UART_CR_REQCLR_Msk (_U_(0x1) << UART_CR_REQCLR_Pos) /**< (UART_CR) Request Clear Mask */ +#define UART_CR_REQCLR(value) (UART_CR_REQCLR_Msk & ((value) << UART_CR_REQCLR_Pos)) +#define UART_CR_Msk _U_(0x000011FC) /**< (UART_CR) Register Mask */ + + +/* -------- UART_MR : (UART Offset: 0x04) (R/W 32) Mode Register -------- */ +#define UART_MR_FILTER_Pos _U_(4) /**< (UART_MR) Receiver Digital Filter Position */ +#define UART_MR_FILTER_Msk (_U_(0x1) << UART_MR_FILTER_Pos) /**< (UART_MR) Receiver Digital Filter Mask */ +#define UART_MR_FILTER(value) (UART_MR_FILTER_Msk & ((value) << UART_MR_FILTER_Pos)) +#define UART_MR_FILTER_DISABLED_Val _U_(0x0) /**< (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED_Val _U_(0x1) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_FILTER_DISABLED (UART_MR_FILTER_DISABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART does not filter the receive line. Position */ +#define UART_MR_FILTER_ENABLED (UART_MR_FILTER_ENABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). Position */ +#define UART_MR_PAR_Pos _U_(9) /**< (UART_MR) Parity Type Position */ +#define UART_MR_PAR_Msk (_U_(0x7) << UART_MR_PAR_Pos) /**< (UART_MR) Parity Type Mask */ +#define UART_MR_PAR(value) (UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)) +#define UART_MR_PAR_EVEN_Val _U_(0x0) /**< (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD_Val _U_(0x1) /**< (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE_Val _U_(0x2) /**< (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK_Val _U_(0x3) /**< (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO_Val _U_(0x4) /**< (UART_MR) No parity */ +#define UART_MR_PAR_EVEN (UART_MR_PAR_EVEN_Val << UART_MR_PAR_Pos) /**< (UART_MR) Even Parity Position */ +#define UART_MR_PAR_ODD (UART_MR_PAR_ODD_Val << UART_MR_PAR_Pos) /**< (UART_MR) Odd Parity Position */ +#define UART_MR_PAR_SPACE (UART_MR_PAR_SPACE_Val << UART_MR_PAR_Pos) /**< (UART_MR) Space: parity forced to 0 Position */ +#define UART_MR_PAR_MARK (UART_MR_PAR_MARK_Val << UART_MR_PAR_Pos) /**< (UART_MR) Mark: parity forced to 1 Position */ +#define UART_MR_PAR_NO (UART_MR_PAR_NO_Val << UART_MR_PAR_Pos) /**< (UART_MR) No parity Position */ +#define UART_MR_BRSRCCK_Pos _U_(12) /**< (UART_MR) Baud Rate Source Clock Position */ +#define UART_MR_BRSRCCK_Msk (_U_(0x1) << UART_MR_BRSRCCK_Pos) /**< (UART_MR) Baud Rate Source Clock Mask */ +#define UART_MR_BRSRCCK(value) (UART_MR_BRSRCCK_Msk & ((value) << UART_MR_BRSRCCK_Pos)) +#define UART_MR_BRSRCCK_PERIPH_CLK_Val _U_(0x0) /**< (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK_Val _U_(0x1) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_BRSRCCK_PERIPH_CLK (UART_MR_BRSRCCK_PERIPH_CLK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by the peripheral clock Position */ +#define UART_MR_BRSRCCK_PMC_PCK (UART_MR_BRSRCCK_PMC_PCK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). Position */ +#define UART_MR_CHMODE_Pos _U_(14) /**< (UART_MR) Channel Mode Position */ +#define UART_MR_CHMODE_Msk (_U_(0x3) << UART_MR_CHMODE_Pos) /**< (UART_MR) Channel Mode Mask */ +#define UART_MR_CHMODE(value) (UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)) +#define UART_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (UART_MR) Remote loopback */ +#define UART_MR_CHMODE_NORMAL (UART_MR_CHMODE_NORMAL_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Normal mode Position */ +#define UART_MR_CHMODE_AUTOMATIC (UART_MR_CHMODE_AUTOMATIC_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Automatic echo Position */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (UART_MR_CHMODE_LOCAL_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Local loopback Position */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (UART_MR_CHMODE_REMOTE_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Remote loopback Position */ +#define UART_MR_Msk _U_(0x0000DE10) /**< (UART_MR) Register Mask */ + + +/* -------- UART_IER : (UART Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY_Pos _U_(0) /**< (UART_IER) Enable RXRDY Interrupt Position */ +#define UART_IER_RXRDY_Msk (_U_(0x1) << UART_IER_RXRDY_Pos) /**< (UART_IER) Enable RXRDY Interrupt Mask */ +#define UART_IER_RXRDY(value) (UART_IER_RXRDY_Msk & ((value) << UART_IER_RXRDY_Pos)) +#define UART_IER_TXRDY_Pos _U_(1) /**< (UART_IER) Enable TXRDY Interrupt Position */ +#define UART_IER_TXRDY_Msk (_U_(0x1) << UART_IER_TXRDY_Pos) /**< (UART_IER) Enable TXRDY Interrupt Mask */ +#define UART_IER_TXRDY(value) (UART_IER_TXRDY_Msk & ((value) << UART_IER_TXRDY_Pos)) +#define UART_IER_OVRE_Pos _U_(5) /**< (UART_IER) Enable Overrun Error Interrupt Position */ +#define UART_IER_OVRE_Msk (_U_(0x1) << UART_IER_OVRE_Pos) /**< (UART_IER) Enable Overrun Error Interrupt Mask */ +#define UART_IER_OVRE(value) (UART_IER_OVRE_Msk & ((value) << UART_IER_OVRE_Pos)) +#define UART_IER_FRAME_Pos _U_(6) /**< (UART_IER) Enable Framing Error Interrupt Position */ +#define UART_IER_FRAME_Msk (_U_(0x1) << UART_IER_FRAME_Pos) /**< (UART_IER) Enable Framing Error Interrupt Mask */ +#define UART_IER_FRAME(value) (UART_IER_FRAME_Msk & ((value) << UART_IER_FRAME_Pos)) +#define UART_IER_PARE_Pos _U_(7) /**< (UART_IER) Enable Parity Error Interrupt Position */ +#define UART_IER_PARE_Msk (_U_(0x1) << UART_IER_PARE_Pos) /**< (UART_IER) Enable Parity Error Interrupt Mask */ +#define UART_IER_PARE(value) (UART_IER_PARE_Msk & ((value) << UART_IER_PARE_Pos)) +#define UART_IER_TXEMPTY_Pos _U_(9) /**< (UART_IER) Enable TXEMPTY Interrupt Position */ +#define UART_IER_TXEMPTY_Msk (_U_(0x1) << UART_IER_TXEMPTY_Pos) /**< (UART_IER) Enable TXEMPTY Interrupt Mask */ +#define UART_IER_TXEMPTY(value) (UART_IER_TXEMPTY_Msk & ((value) << UART_IER_TXEMPTY_Pos)) +#define UART_IER_CMP_Pos _U_(15) /**< (UART_IER) Enable Comparison Interrupt Position */ +#define UART_IER_CMP_Msk (_U_(0x1) << UART_IER_CMP_Pos) /**< (UART_IER) Enable Comparison Interrupt Mask */ +#define UART_IER_CMP(value) (UART_IER_CMP_Msk & ((value) << UART_IER_CMP_Pos)) +#define UART_IER_Msk _U_(0x000082E3) /**< (UART_IER) Register Mask */ + + +/* -------- UART_IDR : (UART Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY_Pos _U_(0) /**< (UART_IDR) Disable RXRDY Interrupt Position */ +#define UART_IDR_RXRDY_Msk (_U_(0x1) << UART_IDR_RXRDY_Pos) /**< (UART_IDR) Disable RXRDY Interrupt Mask */ +#define UART_IDR_RXRDY(value) (UART_IDR_RXRDY_Msk & ((value) << UART_IDR_RXRDY_Pos)) +#define UART_IDR_TXRDY_Pos _U_(1) /**< (UART_IDR) Disable TXRDY Interrupt Position */ +#define UART_IDR_TXRDY_Msk (_U_(0x1) << UART_IDR_TXRDY_Pos) /**< (UART_IDR) Disable TXRDY Interrupt Mask */ +#define UART_IDR_TXRDY(value) (UART_IDR_TXRDY_Msk & ((value) << UART_IDR_TXRDY_Pos)) +#define UART_IDR_OVRE_Pos _U_(5) /**< (UART_IDR) Disable Overrun Error Interrupt Position */ +#define UART_IDR_OVRE_Msk (_U_(0x1) << UART_IDR_OVRE_Pos) /**< (UART_IDR) Disable Overrun Error Interrupt Mask */ +#define UART_IDR_OVRE(value) (UART_IDR_OVRE_Msk & ((value) << UART_IDR_OVRE_Pos)) +#define UART_IDR_FRAME_Pos _U_(6) /**< (UART_IDR) Disable Framing Error Interrupt Position */ +#define UART_IDR_FRAME_Msk (_U_(0x1) << UART_IDR_FRAME_Pos) /**< (UART_IDR) Disable Framing Error Interrupt Mask */ +#define UART_IDR_FRAME(value) (UART_IDR_FRAME_Msk & ((value) << UART_IDR_FRAME_Pos)) +#define UART_IDR_PARE_Pos _U_(7) /**< (UART_IDR) Disable Parity Error Interrupt Position */ +#define UART_IDR_PARE_Msk (_U_(0x1) << UART_IDR_PARE_Pos) /**< (UART_IDR) Disable Parity Error Interrupt Mask */ +#define UART_IDR_PARE(value) (UART_IDR_PARE_Msk & ((value) << UART_IDR_PARE_Pos)) +#define UART_IDR_TXEMPTY_Pos _U_(9) /**< (UART_IDR) Disable TXEMPTY Interrupt Position */ +#define UART_IDR_TXEMPTY_Msk (_U_(0x1) << UART_IDR_TXEMPTY_Pos) /**< (UART_IDR) Disable TXEMPTY Interrupt Mask */ +#define UART_IDR_TXEMPTY(value) (UART_IDR_TXEMPTY_Msk & ((value) << UART_IDR_TXEMPTY_Pos)) +#define UART_IDR_CMP_Pos _U_(15) /**< (UART_IDR) Disable Comparison Interrupt Position */ +#define UART_IDR_CMP_Msk (_U_(0x1) << UART_IDR_CMP_Pos) /**< (UART_IDR) Disable Comparison Interrupt Mask */ +#define UART_IDR_CMP(value) (UART_IDR_CMP_Msk & ((value) << UART_IDR_CMP_Pos)) +#define UART_IDR_Msk _U_(0x000082E3) /**< (UART_IDR) Register Mask */ + + +/* -------- UART_IMR : (UART Offset: 0x10) ( R/ 32) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY_Pos _U_(0) /**< (UART_IMR) Mask RXRDY Interrupt Position */ +#define UART_IMR_RXRDY_Msk (_U_(0x1) << UART_IMR_RXRDY_Pos) /**< (UART_IMR) Mask RXRDY Interrupt Mask */ +#define UART_IMR_RXRDY(value) (UART_IMR_RXRDY_Msk & ((value) << UART_IMR_RXRDY_Pos)) +#define UART_IMR_TXRDY_Pos _U_(1) /**< (UART_IMR) Disable TXRDY Interrupt Position */ +#define UART_IMR_TXRDY_Msk (_U_(0x1) << UART_IMR_TXRDY_Pos) /**< (UART_IMR) Disable TXRDY Interrupt Mask */ +#define UART_IMR_TXRDY(value) (UART_IMR_TXRDY_Msk & ((value) << UART_IMR_TXRDY_Pos)) +#define UART_IMR_OVRE_Pos _U_(5) /**< (UART_IMR) Mask Overrun Error Interrupt Position */ +#define UART_IMR_OVRE_Msk (_U_(0x1) << UART_IMR_OVRE_Pos) /**< (UART_IMR) Mask Overrun Error Interrupt Mask */ +#define UART_IMR_OVRE(value) (UART_IMR_OVRE_Msk & ((value) << UART_IMR_OVRE_Pos)) +#define UART_IMR_FRAME_Pos _U_(6) /**< (UART_IMR) Mask Framing Error Interrupt Position */ +#define UART_IMR_FRAME_Msk (_U_(0x1) << UART_IMR_FRAME_Pos) /**< (UART_IMR) Mask Framing Error Interrupt Mask */ +#define UART_IMR_FRAME(value) (UART_IMR_FRAME_Msk & ((value) << UART_IMR_FRAME_Pos)) +#define UART_IMR_PARE_Pos _U_(7) /**< (UART_IMR) Mask Parity Error Interrupt Position */ +#define UART_IMR_PARE_Msk (_U_(0x1) << UART_IMR_PARE_Pos) /**< (UART_IMR) Mask Parity Error Interrupt Mask */ +#define UART_IMR_PARE(value) (UART_IMR_PARE_Msk & ((value) << UART_IMR_PARE_Pos)) +#define UART_IMR_TXEMPTY_Pos _U_(9) /**< (UART_IMR) Mask TXEMPTY Interrupt Position */ +#define UART_IMR_TXEMPTY_Msk (_U_(0x1) << UART_IMR_TXEMPTY_Pos) /**< (UART_IMR) Mask TXEMPTY Interrupt Mask */ +#define UART_IMR_TXEMPTY(value) (UART_IMR_TXEMPTY_Msk & ((value) << UART_IMR_TXEMPTY_Pos)) +#define UART_IMR_CMP_Pos _U_(15) /**< (UART_IMR) Mask Comparison Interrupt Position */ +#define UART_IMR_CMP_Msk (_U_(0x1) << UART_IMR_CMP_Pos) /**< (UART_IMR) Mask Comparison Interrupt Mask */ +#define UART_IMR_CMP(value) (UART_IMR_CMP_Msk & ((value) << UART_IMR_CMP_Pos)) +#define UART_IMR_Msk _U_(0x000082E3) /**< (UART_IMR) Register Mask */ + + +/* -------- UART_SR : (UART Offset: 0x14) ( R/ 32) Status Register -------- */ +#define UART_SR_RXRDY_Pos _U_(0) /**< (UART_SR) Receiver Ready Position */ +#define UART_SR_RXRDY_Msk (_U_(0x1) << UART_SR_RXRDY_Pos) /**< (UART_SR) Receiver Ready Mask */ +#define UART_SR_RXRDY(value) (UART_SR_RXRDY_Msk & ((value) << UART_SR_RXRDY_Pos)) +#define UART_SR_TXRDY_Pos _U_(1) /**< (UART_SR) Transmitter Ready Position */ +#define UART_SR_TXRDY_Msk (_U_(0x1) << UART_SR_TXRDY_Pos) /**< (UART_SR) Transmitter Ready Mask */ +#define UART_SR_TXRDY(value) (UART_SR_TXRDY_Msk & ((value) << UART_SR_TXRDY_Pos)) +#define UART_SR_OVRE_Pos _U_(5) /**< (UART_SR) Overrun Error Position */ +#define UART_SR_OVRE_Msk (_U_(0x1) << UART_SR_OVRE_Pos) /**< (UART_SR) Overrun Error Mask */ +#define UART_SR_OVRE(value) (UART_SR_OVRE_Msk & ((value) << UART_SR_OVRE_Pos)) +#define UART_SR_FRAME_Pos _U_(6) /**< (UART_SR) Framing Error Position */ +#define UART_SR_FRAME_Msk (_U_(0x1) << UART_SR_FRAME_Pos) /**< (UART_SR) Framing Error Mask */ +#define UART_SR_FRAME(value) (UART_SR_FRAME_Msk & ((value) << UART_SR_FRAME_Pos)) +#define UART_SR_PARE_Pos _U_(7) /**< (UART_SR) Parity Error Position */ +#define UART_SR_PARE_Msk (_U_(0x1) << UART_SR_PARE_Pos) /**< (UART_SR) Parity Error Mask */ +#define UART_SR_PARE(value) (UART_SR_PARE_Msk & ((value) << UART_SR_PARE_Pos)) +#define UART_SR_TXEMPTY_Pos _U_(9) /**< (UART_SR) Transmitter Empty Position */ +#define UART_SR_TXEMPTY_Msk (_U_(0x1) << UART_SR_TXEMPTY_Pos) /**< (UART_SR) Transmitter Empty Mask */ +#define UART_SR_TXEMPTY(value) (UART_SR_TXEMPTY_Msk & ((value) << UART_SR_TXEMPTY_Pos)) +#define UART_SR_CMP_Pos _U_(15) /**< (UART_SR) Comparison Match Position */ +#define UART_SR_CMP_Msk (_U_(0x1) << UART_SR_CMP_Pos) /**< (UART_SR) Comparison Match Mask */ +#define UART_SR_CMP(value) (UART_SR_CMP_Msk & ((value) << UART_SR_CMP_Pos)) +#define UART_SR_Msk _U_(0x000082E3) /**< (UART_SR) Register Mask */ + + +/* -------- UART_RHR : (UART Offset: 0x18) ( R/ 32) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos _U_(0) /**< (UART_RHR) Received Character Position */ +#define UART_RHR_RXCHR_Msk (_U_(0xFF) << UART_RHR_RXCHR_Pos) /**< (UART_RHR) Received Character Mask */ +#define UART_RHR_RXCHR(value) (UART_RHR_RXCHR_Msk & ((value) << UART_RHR_RXCHR_Pos)) +#define UART_RHR_Msk _U_(0x000000FF) /**< (UART_RHR) Register Mask */ + + +/* -------- UART_THR : (UART Offset: 0x1C) ( /W 32) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos _U_(0) /**< (UART_THR) Character to be Transmitted Position */ +#define UART_THR_TXCHR_Msk (_U_(0xFF) << UART_THR_TXCHR_Pos) /**< (UART_THR) Character to be Transmitted Mask */ +#define UART_THR_TXCHR(value) (UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)) +#define UART_THR_Msk _U_(0x000000FF) /**< (UART_THR) Register Mask */ + + +/* -------- UART_BRGR : (UART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos _U_(0) /**< (UART_BRGR) Clock Divisor Position */ +#define UART_BRGR_CD_Msk (_U_(0xFFFF) << UART_BRGR_CD_Pos) /**< (UART_BRGR) Clock Divisor Mask */ +#define UART_BRGR_CD(value) (UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)) +#define UART_BRGR_Msk _U_(0x0000FFFF) /**< (UART_BRGR) Register Mask */ + + +/* -------- UART_CMPR : (UART Offset: 0x24) (R/W 32) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos _U_(0) /**< (UART_CMPR) First Comparison Value for Received Character Position */ +#define UART_CMPR_VAL1_Msk (_U_(0xFF) << UART_CMPR_VAL1_Pos) /**< (UART_CMPR) First Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL1(value) (UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)) +#define UART_CMPR_CMPMODE_Pos _U_(12) /**< (UART_CMPR) Comparison Mode Position */ +#define UART_CMPR_CMPMODE_Msk (_U_(0x1) << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison Mode Mask */ +#define UART_CMPR_CMPMODE(value) (UART_CMPR_CMPMODE_Msk & ((value) << UART_CMPR_CMPMODE_Pos)) +#define UART_CMPR_CMPMODE_FLAG_ONLY_Val _U_(0x0) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION_Val _U_(0x1) /**< (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (UART_CMPR_CMPMODE_FLAG_ONLY_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. Position */ +#define UART_CMPR_CMPMODE_START_CONDITION (UART_CMPR_CMPMODE_START_CONDITION_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison condition must be met to start reception. Position */ +#define UART_CMPR_CMPPAR_Pos _U_(14) /**< (UART_CMPR) Compare Parity Position */ +#define UART_CMPR_CMPPAR_Msk (_U_(0x1) << UART_CMPR_CMPPAR_Pos) /**< (UART_CMPR) Compare Parity Mask */ +#define UART_CMPR_CMPPAR(value) (UART_CMPR_CMPPAR_Msk & ((value) << UART_CMPR_CMPPAR_Pos)) +#define UART_CMPR_VAL2_Pos _U_(16) /**< (UART_CMPR) Second Comparison Value for Received Character Position */ +#define UART_CMPR_VAL2_Msk (_U_(0xFF) << UART_CMPR_VAL2_Pos) /**< (UART_CMPR) Second Comparison Value for Received Character Mask */ +#define UART_CMPR_VAL2(value) (UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)) +#define UART_CMPR_Msk _U_(0x00FF50FF) /**< (UART_CMPR) Register Mask */ + + +/* -------- UART_WPMR : (UART Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN_Pos _U_(0) /**< (UART_WPMR) Write Protection Enable Position */ +#define UART_WPMR_WPEN_Msk (_U_(0x1) << UART_WPMR_WPEN_Pos) /**< (UART_WPMR) Write Protection Enable Mask */ +#define UART_WPMR_WPEN(value) (UART_WPMR_WPEN_Msk & ((value) << UART_WPMR_WPEN_Pos)) +#define UART_WPMR_WPKEY_Pos _U_(8) /**< (UART_WPMR) Write Protection Key Position */ +#define UART_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Write Protection Key Mask */ +#define UART_WPMR_WPKEY(value) (UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)) +#define UART_WPMR_WPKEY_PASSWD_Val _U_(0x554152) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define UART_WPMR_WPKEY_PASSWD (UART_WPMR_WPKEY_PASSWD_Val << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ +#define UART_WPMR_Msk _U_(0xFFFFFF01) /**< (UART_WPMR) Register Mask */ + + +/** \brief UART register offsets definitions */ +#define UART_CR_REG_OFST (0x00) /**< (UART_CR) Control Register Offset */ +#define UART_MR_REG_OFST (0x04) /**< (UART_MR) Mode Register Offset */ +#define UART_IER_REG_OFST (0x08) /**< (UART_IER) Interrupt Enable Register Offset */ +#define UART_IDR_REG_OFST (0x0C) /**< (UART_IDR) Interrupt Disable Register Offset */ +#define UART_IMR_REG_OFST (0x10) /**< (UART_IMR) Interrupt Mask Register Offset */ +#define UART_SR_REG_OFST (0x14) /**< (UART_SR) Status Register Offset */ +#define UART_RHR_REG_OFST (0x18) /**< (UART_RHR) Receive Holding Register Offset */ +#define UART_THR_REG_OFST (0x1C) /**< (UART_THR) Transmit Holding Register Offset */ +#define UART_BRGR_REG_OFST (0x20) /**< (UART_BRGR) Baud Rate Generator Register Offset */ +#define UART_CMPR_REG_OFST (0x24) /**< (UART_CMPR) Comparison Register Offset */ +#define UART_WPMR_REG_OFST (0xE4) /**< (UART_WPMR) Write Protection Mode Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UART register API structure */ +typedef struct +{ + __O uint32_t UART_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t UART_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O uint32_t UART_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< Offset: 0x14 (R/ 32) Status Register */ + __I uint32_t UART_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O uint32_t UART_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< Offset: 0x24 (R/W 32) Comparison Register */ + __I uint8_t Reserved1[0xBC]; + __IO uint32_t UART_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ +} uart_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_UART_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/usart.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/usart.h new file mode 100644 index 00000000..3bb47196 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/usart.h @@ -0,0 +1,1419 @@ +/** + * \brief Component description for USART + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_USART_COMPONENT_H_ +#define _SAME70_USART_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USART */ +/* ************************************************************************** */ + +/* -------- US_CR : (USART Offset: 0x00) ( /W 32) Control Register -------- */ +#define US_CR_Msk _U_(0x00000000) /**< (US_CR) Register Mask */ + +/* USART mode */ +#define US_CR_USART_RSTRX_Pos _U_(2) /**< (US_CR) Reset Receiver Position */ +#define US_CR_USART_RSTRX_Msk (_U_(0x1) << US_CR_USART_RSTRX_Pos) /**< (US_CR) Reset Receiver Mask */ +#define US_CR_USART_RSTRX(value) (US_CR_USART_RSTRX_Msk & ((value) << US_CR_USART_RSTRX_Pos)) +#define US_CR_USART_RSTTX_Pos _U_(3) /**< (US_CR) Reset Transmitter Position */ +#define US_CR_USART_RSTTX_Msk (_U_(0x1) << US_CR_USART_RSTTX_Pos) /**< (US_CR) Reset Transmitter Mask */ +#define US_CR_USART_RSTTX(value) (US_CR_USART_RSTTX_Msk & ((value) << US_CR_USART_RSTTX_Pos)) +#define US_CR_USART_RXEN_Pos _U_(4) /**< (US_CR) Receiver Enable Position */ +#define US_CR_USART_RXEN_Msk (_U_(0x1) << US_CR_USART_RXEN_Pos) /**< (US_CR) Receiver Enable Mask */ +#define US_CR_USART_RXEN(value) (US_CR_USART_RXEN_Msk & ((value) << US_CR_USART_RXEN_Pos)) +#define US_CR_USART_RXDIS_Pos _U_(5) /**< (US_CR) Receiver Disable Position */ +#define US_CR_USART_RXDIS_Msk (_U_(0x1) << US_CR_USART_RXDIS_Pos) /**< (US_CR) Receiver Disable Mask */ +#define US_CR_USART_RXDIS(value) (US_CR_USART_RXDIS_Msk & ((value) << US_CR_USART_RXDIS_Pos)) +#define US_CR_USART_TXEN_Pos _U_(6) /**< (US_CR) Transmitter Enable Position */ +#define US_CR_USART_TXEN_Msk (_U_(0x1) << US_CR_USART_TXEN_Pos) /**< (US_CR) Transmitter Enable Mask */ +#define US_CR_USART_TXEN(value) (US_CR_USART_TXEN_Msk & ((value) << US_CR_USART_TXEN_Pos)) +#define US_CR_USART_TXDIS_Pos _U_(7) /**< (US_CR) Transmitter Disable Position */ +#define US_CR_USART_TXDIS_Msk (_U_(0x1) << US_CR_USART_TXDIS_Pos) /**< (US_CR) Transmitter Disable Mask */ +#define US_CR_USART_TXDIS(value) (US_CR_USART_TXDIS_Msk & ((value) << US_CR_USART_TXDIS_Pos)) +#define US_CR_USART_RSTSTA_Pos _U_(8) /**< (US_CR) Reset Status Bits Position */ +#define US_CR_USART_RSTSTA_Msk (_U_(0x1) << US_CR_USART_RSTSTA_Pos) /**< (US_CR) Reset Status Bits Mask */ +#define US_CR_USART_RSTSTA(value) (US_CR_USART_RSTSTA_Msk & ((value) << US_CR_USART_RSTSTA_Pos)) +#define US_CR_USART_STTBRK_Pos _U_(9) /**< (US_CR) Start Break Position */ +#define US_CR_USART_STTBRK_Msk (_U_(0x1) << US_CR_USART_STTBRK_Pos) /**< (US_CR) Start Break Mask */ +#define US_CR_USART_STTBRK(value) (US_CR_USART_STTBRK_Msk & ((value) << US_CR_USART_STTBRK_Pos)) +#define US_CR_USART_STPBRK_Pos _U_(10) /**< (US_CR) Stop Break Position */ +#define US_CR_USART_STPBRK_Msk (_U_(0x1) << US_CR_USART_STPBRK_Pos) /**< (US_CR) Stop Break Mask */ +#define US_CR_USART_STPBRK(value) (US_CR_USART_STPBRK_Msk & ((value) << US_CR_USART_STPBRK_Pos)) +#define US_CR_USART_STTTO_Pos _U_(11) /**< (US_CR) Clear TIMEOUT Flag and Start Timeout After Next Character Received Position */ +#define US_CR_USART_STTTO_Msk (_U_(0x1) << US_CR_USART_STTTO_Pos) /**< (US_CR) Clear TIMEOUT Flag and Start Timeout After Next Character Received Mask */ +#define US_CR_USART_STTTO(value) (US_CR_USART_STTTO_Msk & ((value) << US_CR_USART_STTTO_Pos)) +#define US_CR_USART_SENDA_Pos _U_(12) /**< (US_CR) Send Address Position */ +#define US_CR_USART_SENDA_Msk (_U_(0x1) << US_CR_USART_SENDA_Pos) /**< (US_CR) Send Address Mask */ +#define US_CR_USART_SENDA(value) (US_CR_USART_SENDA_Msk & ((value) << US_CR_USART_SENDA_Pos)) +#define US_CR_USART_RSTIT_Pos _U_(13) /**< (US_CR) Reset Iterations Position */ +#define US_CR_USART_RSTIT_Msk (_U_(0x1) << US_CR_USART_RSTIT_Pos) /**< (US_CR) Reset Iterations Mask */ +#define US_CR_USART_RSTIT(value) (US_CR_USART_RSTIT_Msk & ((value) << US_CR_USART_RSTIT_Pos)) +#define US_CR_USART_RSTNACK_Pos _U_(14) /**< (US_CR) Reset Non Acknowledge Position */ +#define US_CR_USART_RSTNACK_Msk (_U_(0x1) << US_CR_USART_RSTNACK_Pos) /**< (US_CR) Reset Non Acknowledge Mask */ +#define US_CR_USART_RSTNACK(value) (US_CR_USART_RSTNACK_Msk & ((value) << US_CR_USART_RSTNACK_Pos)) +#define US_CR_USART_RETTO_Pos _U_(15) /**< (US_CR) Start Timeout Immediately Position */ +#define US_CR_USART_RETTO_Msk (_U_(0x1) << US_CR_USART_RETTO_Pos) /**< (US_CR) Start Timeout Immediately Mask */ +#define US_CR_USART_RETTO(value) (US_CR_USART_RETTO_Msk & ((value) << US_CR_USART_RETTO_Pos)) +#define US_CR_USART_DTREN_Pos _U_(16) /**< (US_CR) Data Terminal Ready Enable Position */ +#define US_CR_USART_DTREN_Msk (_U_(0x1) << US_CR_USART_DTREN_Pos) /**< (US_CR) Data Terminal Ready Enable Mask */ +#define US_CR_USART_DTREN(value) (US_CR_USART_DTREN_Msk & ((value) << US_CR_USART_DTREN_Pos)) +#define US_CR_USART_DTRDIS_Pos _U_(17) /**< (US_CR) Data Terminal Ready Disable Position */ +#define US_CR_USART_DTRDIS_Msk (_U_(0x1) << US_CR_USART_DTRDIS_Pos) /**< (US_CR) Data Terminal Ready Disable Mask */ +#define US_CR_USART_DTRDIS(value) (US_CR_USART_DTRDIS_Msk & ((value) << US_CR_USART_DTRDIS_Pos)) +#define US_CR_USART_RTSEN_Pos _U_(18) /**< (US_CR) Request to Send Enable Position */ +#define US_CR_USART_RTSEN_Msk (_U_(0x1) << US_CR_USART_RTSEN_Pos) /**< (US_CR) Request to Send Enable Mask */ +#define US_CR_USART_RTSEN(value) (US_CR_USART_RTSEN_Msk & ((value) << US_CR_USART_RTSEN_Pos)) +#define US_CR_USART_RTSDIS_Pos _U_(19) /**< (US_CR) Request to Send Disable Position */ +#define US_CR_USART_RTSDIS_Msk (_U_(0x1) << US_CR_USART_RTSDIS_Pos) /**< (US_CR) Request to Send Disable Mask */ +#define US_CR_USART_RTSDIS(value) (US_CR_USART_RTSDIS_Msk & ((value) << US_CR_USART_RTSDIS_Pos)) +#define US_CR_USART_Msk _U_(0x000FFFFC) /**< (US_CR_USART) Register Mask */ + +/* SPI mode */ +#define US_CR_SPI_RSTRX_Pos _U_(2) /**< (US_CR) Reset Receiver Position */ +#define US_CR_SPI_RSTRX_Msk (_U_(0x1) << US_CR_SPI_RSTRX_Pos) /**< (US_CR) Reset Receiver Mask */ +#define US_CR_SPI_RSTRX(value) (US_CR_SPI_RSTRX_Msk & ((value) << US_CR_SPI_RSTRX_Pos)) +#define US_CR_SPI_RSTTX_Pos _U_(3) /**< (US_CR) Reset Transmitter Position */ +#define US_CR_SPI_RSTTX_Msk (_U_(0x1) << US_CR_SPI_RSTTX_Pos) /**< (US_CR) Reset Transmitter Mask */ +#define US_CR_SPI_RSTTX(value) (US_CR_SPI_RSTTX_Msk & ((value) << US_CR_SPI_RSTTX_Pos)) +#define US_CR_SPI_RXEN_Pos _U_(4) /**< (US_CR) Receiver Enable Position */ +#define US_CR_SPI_RXEN_Msk (_U_(0x1) << US_CR_SPI_RXEN_Pos) /**< (US_CR) Receiver Enable Mask */ +#define US_CR_SPI_RXEN(value) (US_CR_SPI_RXEN_Msk & ((value) << US_CR_SPI_RXEN_Pos)) +#define US_CR_SPI_RXDIS_Pos _U_(5) /**< (US_CR) Receiver Disable Position */ +#define US_CR_SPI_RXDIS_Msk (_U_(0x1) << US_CR_SPI_RXDIS_Pos) /**< (US_CR) Receiver Disable Mask */ +#define US_CR_SPI_RXDIS(value) (US_CR_SPI_RXDIS_Msk & ((value) << US_CR_SPI_RXDIS_Pos)) +#define US_CR_SPI_TXEN_Pos _U_(6) /**< (US_CR) Transmitter Enable Position */ +#define US_CR_SPI_TXEN_Msk (_U_(0x1) << US_CR_SPI_TXEN_Pos) /**< (US_CR) Transmitter Enable Mask */ +#define US_CR_SPI_TXEN(value) (US_CR_SPI_TXEN_Msk & ((value) << US_CR_SPI_TXEN_Pos)) +#define US_CR_SPI_TXDIS_Pos _U_(7) /**< (US_CR) Transmitter Disable Position */ +#define US_CR_SPI_TXDIS_Msk (_U_(0x1) << US_CR_SPI_TXDIS_Pos) /**< (US_CR) Transmitter Disable Mask */ +#define US_CR_SPI_TXDIS(value) (US_CR_SPI_TXDIS_Msk & ((value) << US_CR_SPI_TXDIS_Pos)) +#define US_CR_SPI_RSTSTA_Pos _U_(8) /**< (US_CR) Reset Status Bits Position */ +#define US_CR_SPI_RSTSTA_Msk (_U_(0x1) << US_CR_SPI_RSTSTA_Pos) /**< (US_CR) Reset Status Bits Mask */ +#define US_CR_SPI_RSTSTA(value) (US_CR_SPI_RSTSTA_Msk & ((value) << US_CR_SPI_RSTSTA_Pos)) +#define US_CR_SPI_FCS_Pos _U_(18) /**< (US_CR) Force SPI Chip Select Position */ +#define US_CR_SPI_FCS_Msk (_U_(0x1) << US_CR_SPI_FCS_Pos) /**< (US_CR) Force SPI Chip Select Mask */ +#define US_CR_SPI_FCS(value) (US_CR_SPI_FCS_Msk & ((value) << US_CR_SPI_FCS_Pos)) +#define US_CR_SPI_RCS_Pos _U_(19) /**< (US_CR) Release SPI Chip Select Position */ +#define US_CR_SPI_RCS_Msk (_U_(0x1) << US_CR_SPI_RCS_Pos) /**< (US_CR) Release SPI Chip Select Mask */ +#define US_CR_SPI_RCS(value) (US_CR_SPI_RCS_Msk & ((value) << US_CR_SPI_RCS_Pos)) +#define US_CR_SPI_Msk _U_(0x000C01FC) /**< (US_CR_SPI) Register Mask */ + +/* LIN mode */ +#define US_CR_LIN_RSTRX_Pos _U_(2) /**< (US_CR) Reset Receiver Position */ +#define US_CR_LIN_RSTRX_Msk (_U_(0x1) << US_CR_LIN_RSTRX_Pos) /**< (US_CR) Reset Receiver Mask */ +#define US_CR_LIN_RSTRX(value) (US_CR_LIN_RSTRX_Msk & ((value) << US_CR_LIN_RSTRX_Pos)) +#define US_CR_LIN_RSTTX_Pos _U_(3) /**< (US_CR) Reset Transmitter Position */ +#define US_CR_LIN_RSTTX_Msk (_U_(0x1) << US_CR_LIN_RSTTX_Pos) /**< (US_CR) Reset Transmitter Mask */ +#define US_CR_LIN_RSTTX(value) (US_CR_LIN_RSTTX_Msk & ((value) << US_CR_LIN_RSTTX_Pos)) +#define US_CR_LIN_RXEN_Pos _U_(4) /**< (US_CR) Receiver Enable Position */ +#define US_CR_LIN_RXEN_Msk (_U_(0x1) << US_CR_LIN_RXEN_Pos) /**< (US_CR) Receiver Enable Mask */ +#define US_CR_LIN_RXEN(value) (US_CR_LIN_RXEN_Msk & ((value) << US_CR_LIN_RXEN_Pos)) +#define US_CR_LIN_RXDIS_Pos _U_(5) /**< (US_CR) Receiver Disable Position */ +#define US_CR_LIN_RXDIS_Msk (_U_(0x1) << US_CR_LIN_RXDIS_Pos) /**< (US_CR) Receiver Disable Mask */ +#define US_CR_LIN_RXDIS(value) (US_CR_LIN_RXDIS_Msk & ((value) << US_CR_LIN_RXDIS_Pos)) +#define US_CR_LIN_TXEN_Pos _U_(6) /**< (US_CR) Transmitter Enable Position */ +#define US_CR_LIN_TXEN_Msk (_U_(0x1) << US_CR_LIN_TXEN_Pos) /**< (US_CR) Transmitter Enable Mask */ +#define US_CR_LIN_TXEN(value) (US_CR_LIN_TXEN_Msk & ((value) << US_CR_LIN_TXEN_Pos)) +#define US_CR_LIN_TXDIS_Pos _U_(7) /**< (US_CR) Transmitter Disable Position */ +#define US_CR_LIN_TXDIS_Msk (_U_(0x1) << US_CR_LIN_TXDIS_Pos) /**< (US_CR) Transmitter Disable Mask */ +#define US_CR_LIN_TXDIS(value) (US_CR_LIN_TXDIS_Msk & ((value) << US_CR_LIN_TXDIS_Pos)) +#define US_CR_LIN_RSTSTA_Pos _U_(8) /**< (US_CR) Reset Status Bits Position */ +#define US_CR_LIN_RSTSTA_Msk (_U_(0x1) << US_CR_LIN_RSTSTA_Pos) /**< (US_CR) Reset Status Bits Mask */ +#define US_CR_LIN_RSTSTA(value) (US_CR_LIN_RSTSTA_Msk & ((value) << US_CR_LIN_RSTSTA_Pos)) +#define US_CR_LIN_LINABT_Pos _U_(20) /**< (US_CR) Abort LIN Transmission Position */ +#define US_CR_LIN_LINABT_Msk (_U_(0x1) << US_CR_LIN_LINABT_Pos) /**< (US_CR) Abort LIN Transmission Mask */ +#define US_CR_LIN_LINABT(value) (US_CR_LIN_LINABT_Msk & ((value) << US_CR_LIN_LINABT_Pos)) +#define US_CR_LIN_LINWKUP_Pos _U_(21) /**< (US_CR) Send LIN Wakeup Signal Position */ +#define US_CR_LIN_LINWKUP_Msk (_U_(0x1) << US_CR_LIN_LINWKUP_Pos) /**< (US_CR) Send LIN Wakeup Signal Mask */ +#define US_CR_LIN_LINWKUP(value) (US_CR_LIN_LINWKUP_Msk & ((value) << US_CR_LIN_LINWKUP_Pos)) +#define US_CR_LIN_Msk _U_(0x003001FC) /**< (US_CR_LIN) Register Mask */ + + +/* -------- US_MR : (USART Offset: 0x04) (R/W 32) Mode Register -------- */ +#define US_MR_Msk _U_(0x00000000) /**< (US_MR) Register Mask */ + +/* USART mode */ +#define US_MR_USART_MODE_Pos _U_(0) /**< (US_MR) USART Mode of Operation Position */ +#define US_MR_USART_MODE_Msk (_U_(0xF) << US_MR_USART_MODE_Pos) /**< (US_MR) USART Mode of Operation Mask */ +#define US_MR_USART_MODE(value) (US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)) +#define US_MR_USART_MODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485_Val _U_(0x1) /**< (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING_Val _U_(0x2) /**< (US_MR) Hardware handshaking */ +#define US_MR_USART_MODE_MODEM_Val _U_(0x3) /**< (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0_Val _U_(0x4) /**< (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1_Val _U_(0x6) /**< (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA_Val _U_(0x8) /**< (US_MR) IrDA */ +#define US_MR_USART_MODE_LON_Val _U_(0x9) /**< (US_MR) LON */ +#define US_MR_USART_MODE_LIN_MASTER_Val _U_(0xA) /**< (US_MR) LIN Master mode */ +#define US_MR_USART_MODE_LIN_SLAVE_Val _U_(0xB) /**< (US_MR) LIN Slave mode */ +#define US_MR_USART_MODE_SPI_MASTER_Val _U_(0xE) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) */ +#define US_MR_USART_MODE_SPI_SLAVE_Val _U_(0xF) /**< (US_MR) SPI Slave mode */ +#define US_MR_USART_MODE_NORMAL (US_MR_USART_MODE_NORMAL_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_USART_MODE_RS485 (US_MR_USART_MODE_RS485_Val << US_MR_USART_MODE_Pos) /**< (US_MR) RS485 Position */ +#define US_MR_USART_MODE_HW_HANDSHAKING (US_MR_USART_MODE_HW_HANDSHAKING_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Hardware handshaking Position */ +#define US_MR_USART_MODE_MODEM (US_MR_USART_MODE_MODEM_Val << US_MR_USART_MODE_Pos) /**< (US_MR) Modem Position */ +#define US_MR_USART_MODE_IS07816_T_0 (US_MR_USART_MODE_IS07816_T_0_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 0 Position */ +#define US_MR_USART_MODE_IS07816_T_1 (US_MR_USART_MODE_IS07816_T_1_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 1 Position */ +#define US_MR_USART_MODE_IRDA (US_MR_USART_MODE_IRDA_Val << US_MR_USART_MODE_Pos) /**< (US_MR) IrDA Position */ +#define US_MR_USART_MODE_LON (US_MR_USART_MODE_LON_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LON Position */ +#define US_MR_USART_MODE_LIN_MASTER (US_MR_USART_MODE_LIN_MASTER_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LIN Master mode Position */ +#define US_MR_USART_MODE_LIN_SLAVE (US_MR_USART_MODE_LIN_SLAVE_Val << US_MR_USART_MODE_Pos) /**< (US_MR) LIN Slave mode Position */ +#define US_MR_USART_MODE_SPI_MASTER (US_MR_USART_MODE_SPI_MASTER_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) Position */ +#define US_MR_USART_MODE_SPI_SLAVE (US_MR_USART_MODE_SPI_SLAVE_Val << US_MR_USART_MODE_Pos) /**< (US_MR) SPI Slave mode Position */ +#define US_MR_USART_USCLKS_Pos _U_(4) /**< (US_MR) Clock Selection Position */ +#define US_MR_USART_USCLKS_Msk (_U_(0x3) << US_MR_USART_USCLKS_Pos) /**< (US_MR) Clock Selection Mask */ +#define US_MR_USART_USCLKS(value) (US_MR_USART_USCLKS_Msk & ((value) << US_MR_USART_USCLKS_Pos)) +#define US_MR_USART_USCLKS_MCK_Val _U_(0x0) /**< (US_MR) Peripheral clock is selected */ +#define US_MR_USART_USCLKS_DIV_Val _U_(0x1) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected */ +#define US_MR_USART_USCLKS_PCK_Val _U_(0x2) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USART_USCLKS_SCK_Val _U_(0x3) /**< (US_MR) Serial clock (SCK) is selected */ +#define US_MR_USART_USCLKS_MCK (US_MR_USART_USCLKS_MCK_Val << US_MR_USART_USCLKS_Pos) /**< (US_MR) Peripheral clock is selected Position */ +#define US_MR_USART_USCLKS_DIV (US_MR_USART_USCLKS_DIV_Val << US_MR_USART_USCLKS_Pos) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected Position */ +#define US_MR_USART_USCLKS_PCK (US_MR_USART_USCLKS_PCK_Val << US_MR_USART_USCLKS_Pos) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. Position */ +#define US_MR_USART_USCLKS_SCK (US_MR_USART_USCLKS_SCK_Val << US_MR_USART_USCLKS_Pos) /**< (US_MR) Serial clock (SCK) is selected Position */ +#define US_MR_USART_CHRL_Pos _U_(6) /**< (US_MR) Character Length Position */ +#define US_MR_USART_CHRL_Msk (_U_(0x3) << US_MR_USART_CHRL_Pos) /**< (US_MR) Character Length Mask */ +#define US_MR_USART_CHRL(value) (US_MR_USART_CHRL_Msk & ((value) << US_MR_USART_CHRL_Pos)) +#define US_MR_USART_CHRL_5_BIT_Val _U_(0x0) /**< (US_MR) Character length is 5 bits */ +#define US_MR_USART_CHRL_6_BIT_Val _U_(0x1) /**< (US_MR) Character length is 6 bits */ +#define US_MR_USART_CHRL_7_BIT_Val _U_(0x2) /**< (US_MR) Character length is 7 bits */ +#define US_MR_USART_CHRL_8_BIT_Val _U_(0x3) /**< (US_MR) Character length is 8 bits */ +#define US_MR_USART_CHRL_5_BIT (US_MR_USART_CHRL_5_BIT_Val << US_MR_USART_CHRL_Pos) /**< (US_MR) Character length is 5 bits Position */ +#define US_MR_USART_CHRL_6_BIT (US_MR_USART_CHRL_6_BIT_Val << US_MR_USART_CHRL_Pos) /**< (US_MR) Character length is 6 bits Position */ +#define US_MR_USART_CHRL_7_BIT (US_MR_USART_CHRL_7_BIT_Val << US_MR_USART_CHRL_Pos) /**< (US_MR) Character length is 7 bits Position */ +#define US_MR_USART_CHRL_8_BIT (US_MR_USART_CHRL_8_BIT_Val << US_MR_USART_CHRL_Pos) /**< (US_MR) Character length is 8 bits Position */ +#define US_MR_USART_SYNC_Pos _U_(8) /**< (US_MR) Synchronous Mode Select Position */ +#define US_MR_USART_SYNC_Msk (_U_(0x1) << US_MR_USART_SYNC_Pos) /**< (US_MR) Synchronous Mode Select Mask */ +#define US_MR_USART_SYNC(value) (US_MR_USART_SYNC_Msk & ((value) << US_MR_USART_SYNC_Pos)) +#define US_MR_USART_PAR_Pos _U_(9) /**< (US_MR) Parity Type Position */ +#define US_MR_USART_PAR_Msk (_U_(0x7) << US_MR_USART_PAR_Pos) /**< (US_MR) Parity Type Mask */ +#define US_MR_USART_PAR(value) (US_MR_USART_PAR_Msk & ((value) << US_MR_USART_PAR_Pos)) +#define US_MR_USART_PAR_EVEN_Val _U_(0x0) /**< (US_MR) Even parity */ +#define US_MR_USART_PAR_ODD_Val _U_(0x1) /**< (US_MR) Odd parity */ +#define US_MR_USART_PAR_SPACE_Val _U_(0x2) /**< (US_MR) Parity forced to 0 (Space) */ +#define US_MR_USART_PAR_MARK_Val _U_(0x3) /**< (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_USART_PAR_NO_Val _U_(0x4) /**< (US_MR) No parity */ +#define US_MR_USART_PAR_MULTIDROP_Val _U_(0x6) /**< (US_MR) Multidrop mode */ +#define US_MR_USART_PAR_EVEN (US_MR_USART_PAR_EVEN_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Even parity Position */ +#define US_MR_USART_PAR_ODD (US_MR_USART_PAR_ODD_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Odd parity Position */ +#define US_MR_USART_PAR_SPACE (US_MR_USART_PAR_SPACE_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Parity forced to 0 (Space) Position */ +#define US_MR_USART_PAR_MARK (US_MR_USART_PAR_MARK_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Parity forced to 1 (Mark) Position */ +#define US_MR_USART_PAR_NO (US_MR_USART_PAR_NO_Val << US_MR_USART_PAR_Pos) /**< (US_MR) No parity Position */ +#define US_MR_USART_PAR_MULTIDROP (US_MR_USART_PAR_MULTIDROP_Val << US_MR_USART_PAR_Pos) /**< (US_MR) Multidrop mode Position */ +#define US_MR_USART_NBSTOP_Pos _U_(12) /**< (US_MR) Number of Stop Bits Position */ +#define US_MR_USART_NBSTOP_Msk (_U_(0x3) << US_MR_USART_NBSTOP_Pos) /**< (US_MR) Number of Stop Bits Mask */ +#define US_MR_USART_NBSTOP(value) (US_MR_USART_NBSTOP_Msk & ((value) << US_MR_USART_NBSTOP_Pos)) +#define US_MR_USART_NBSTOP_1_BIT_Val _U_(0x0) /**< (US_MR) 1 stop bit */ +#define US_MR_USART_NBSTOP_1_5_BIT_Val _U_(0x1) /**< (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_USART_NBSTOP_2_BIT_Val _U_(0x2) /**< (US_MR) 2 stop bits */ +#define US_MR_USART_NBSTOP_1_BIT (US_MR_USART_NBSTOP_1_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 1 stop bit Position */ +#define US_MR_USART_NBSTOP_1_5_BIT (US_MR_USART_NBSTOP_1_5_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) Position */ +#define US_MR_USART_NBSTOP_2_BIT (US_MR_USART_NBSTOP_2_BIT_Val << US_MR_USART_NBSTOP_Pos) /**< (US_MR) 2 stop bits Position */ +#define US_MR_USART_CHMODE_Pos _U_(14) /**< (US_MR) Channel Mode Position */ +#define US_MR_USART_CHMODE_Msk (_U_(0x3) << US_MR_USART_CHMODE_Pos) /**< (US_MR) Channel Mode Mask */ +#define US_MR_USART_CHMODE(value) (US_MR_USART_CHMODE_Msk & ((value) << US_MR_USART_CHMODE_Pos)) +#define US_MR_USART_CHMODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_USART_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_USART_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_USART_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_USART_CHMODE_NORMAL (US_MR_USART_CHMODE_NORMAL_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_USART_CHMODE_AUTOMATIC (US_MR_USART_CHMODE_AUTOMATIC_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. Position */ +#define US_MR_USART_CHMODE_LOCAL_LOOPBACK (US_MR_USART_CHMODE_LOCAL_LOOPBACK_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. Position */ +#define US_MR_USART_CHMODE_REMOTE_LOOPBACK (US_MR_USART_CHMODE_REMOTE_LOOPBACK_Val << US_MR_USART_CHMODE_Pos) /**< (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. Position */ +#define US_MR_USART_MSBF_Pos _U_(16) /**< (US_MR) Bit Order Position */ +#define US_MR_USART_MSBF_Msk (_U_(0x1) << US_MR_USART_MSBF_Pos) /**< (US_MR) Bit Order Mask */ +#define US_MR_USART_MSBF(value) (US_MR_USART_MSBF_Msk & ((value) << US_MR_USART_MSBF_Pos)) +#define US_MR_USART_MODE9_Pos _U_(17) /**< (US_MR) 9-bit Character Length Position */ +#define US_MR_USART_MODE9_Msk (_U_(0x1) << US_MR_USART_MODE9_Pos) /**< (US_MR) 9-bit Character Length Mask */ +#define US_MR_USART_MODE9(value) (US_MR_USART_MODE9_Msk & ((value) << US_MR_USART_MODE9_Pos)) +#define US_MR_USART_CLKO_Pos _U_(18) /**< (US_MR) Clock Output Select Position */ +#define US_MR_USART_CLKO_Msk (_U_(0x1) << US_MR_USART_CLKO_Pos) /**< (US_MR) Clock Output Select Mask */ +#define US_MR_USART_CLKO(value) (US_MR_USART_CLKO_Msk & ((value) << US_MR_USART_CLKO_Pos)) +#define US_MR_USART_OVER_Pos _U_(19) /**< (US_MR) Oversampling Mode Position */ +#define US_MR_USART_OVER_Msk (_U_(0x1) << US_MR_USART_OVER_Pos) /**< (US_MR) Oversampling Mode Mask */ +#define US_MR_USART_OVER(value) (US_MR_USART_OVER_Msk & ((value) << US_MR_USART_OVER_Pos)) +#define US_MR_USART_INACK_Pos _U_(20) /**< (US_MR) Inhibit Non Acknowledge Position */ +#define US_MR_USART_INACK_Msk (_U_(0x1) << US_MR_USART_INACK_Pos) /**< (US_MR) Inhibit Non Acknowledge Mask */ +#define US_MR_USART_INACK(value) (US_MR_USART_INACK_Msk & ((value) << US_MR_USART_INACK_Pos)) +#define US_MR_USART_DSNACK_Pos _U_(21) /**< (US_MR) Disable Successive NACK Position */ +#define US_MR_USART_DSNACK_Msk (_U_(0x1) << US_MR_USART_DSNACK_Pos) /**< (US_MR) Disable Successive NACK Mask */ +#define US_MR_USART_DSNACK(value) (US_MR_USART_DSNACK_Msk & ((value) << US_MR_USART_DSNACK_Pos)) +#define US_MR_USART_VAR_SYNC_Pos _U_(22) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Position */ +#define US_MR_USART_VAR_SYNC_Msk (_U_(0x1) << US_MR_USART_VAR_SYNC_Pos) /**< (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter Mask */ +#define US_MR_USART_VAR_SYNC(value) (US_MR_USART_VAR_SYNC_Msk & ((value) << US_MR_USART_VAR_SYNC_Pos)) +#define US_MR_USART_INVDATA_Pos _U_(23) /**< (US_MR) Inverted Data Position */ +#define US_MR_USART_INVDATA_Msk (_U_(0x1) << US_MR_USART_INVDATA_Pos) /**< (US_MR) Inverted Data Mask */ +#define US_MR_USART_INVDATA(value) (US_MR_USART_INVDATA_Msk & ((value) << US_MR_USART_INVDATA_Pos)) +#define US_MR_USART_MAX_ITERATION_Pos _U_(24) /**< (US_MR) Maximum Number of Automatic Iteration Position */ +#define US_MR_USART_MAX_ITERATION_Msk (_U_(0x7) << US_MR_USART_MAX_ITERATION_Pos) /**< (US_MR) Maximum Number of Automatic Iteration Mask */ +#define US_MR_USART_MAX_ITERATION(value) (US_MR_USART_MAX_ITERATION_Msk & ((value) << US_MR_USART_MAX_ITERATION_Pos)) +#define US_MR_USART_FILTER_Pos _U_(28) /**< (US_MR) Receive Line Filter Position */ +#define US_MR_USART_FILTER_Msk (_U_(0x1) << US_MR_USART_FILTER_Pos) /**< (US_MR) Receive Line Filter Mask */ +#define US_MR_USART_FILTER(value) (US_MR_USART_FILTER_Msk & ((value) << US_MR_USART_FILTER_Pos)) +#define US_MR_USART_MAN_Pos _U_(29) /**< (US_MR) Manchester Encoder/Decoder Enable Position */ +#define US_MR_USART_MAN_Msk (_U_(0x1) << US_MR_USART_MAN_Pos) /**< (US_MR) Manchester Encoder/Decoder Enable Mask */ +#define US_MR_USART_MAN(value) (US_MR_USART_MAN_Msk & ((value) << US_MR_USART_MAN_Pos)) +#define US_MR_USART_MODSYNC_Pos _U_(30) /**< (US_MR) Manchester Synchronization Mode Position */ +#define US_MR_USART_MODSYNC_Msk (_U_(0x1) << US_MR_USART_MODSYNC_Pos) /**< (US_MR) Manchester Synchronization Mode Mask */ +#define US_MR_USART_MODSYNC(value) (US_MR_USART_MODSYNC_Msk & ((value) << US_MR_USART_MODSYNC_Pos)) +#define US_MR_USART_ONEBIT_Pos _U_(31) /**< (US_MR) Start Frame Delimiter Selector Position */ +#define US_MR_USART_ONEBIT_Msk (_U_(0x1) << US_MR_USART_ONEBIT_Pos) /**< (US_MR) Start Frame Delimiter Selector Mask */ +#define US_MR_USART_ONEBIT(value) (US_MR_USART_ONEBIT_Msk & ((value) << US_MR_USART_ONEBIT_Pos)) +#define US_MR_USART_Msk _U_(0xF7FFFFFF) /**< (US_MR_USART) Register Mask */ + +/* SPI mode */ +#define US_MR_SPI_USART_MODE_Pos _U_(0) /**< (US_MR) USART Mode of Operation Position */ +#define US_MR_SPI_USART_MODE_Msk (_U_(0xF) << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) USART Mode of Operation Mask */ +#define US_MR_SPI_USART_MODE(value) (US_MR_SPI_USART_MODE_Msk & ((value) << US_MR_SPI_USART_MODE_Pos)) +#define US_MR_SPI_USART_MODE_NORMAL_Val _U_(0x0) /**< (US_MR) Normal mode */ +#define US_MR_SPI_USART_MODE_RS485_Val _U_(0x1) /**< (US_MR) RS485 */ +#define US_MR_SPI_USART_MODE_HW_HANDSHAKING_Val _U_(0x2) /**< (US_MR) Hardware handshaking */ +#define US_MR_SPI_USART_MODE_MODEM_Val _U_(0x3) /**< (US_MR) Modem */ +#define US_MR_SPI_USART_MODE_IS07816_T_0_Val _U_(0x4) /**< (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_SPI_USART_MODE_IS07816_T_1_Val _U_(0x6) /**< (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_SPI_USART_MODE_IRDA_Val _U_(0x8) /**< (US_MR) IrDA */ +#define US_MR_SPI_USART_MODE_LON_Val _U_(0x9) /**< (US_MR) LON */ +#define US_MR_SPI_USART_MODE_LIN_MASTER_Val _U_(0xA) /**< (US_MR) LIN Master mode */ +#define US_MR_SPI_USART_MODE_LIN_SLAVE_Val _U_(0xB) /**< (US_MR) LIN Slave mode */ +#define US_MR_SPI_USART_MODE_SPI_MASTER_Val _U_(0xE) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) */ +#define US_MR_SPI_USART_MODE_SPI_SLAVE_Val _U_(0xF) /**< (US_MR) SPI Slave mode */ +#define US_MR_SPI_USART_MODE_NORMAL (US_MR_SPI_USART_MODE_NORMAL_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) Normal mode Position */ +#define US_MR_SPI_USART_MODE_RS485 (US_MR_SPI_USART_MODE_RS485_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) RS485 Position */ +#define US_MR_SPI_USART_MODE_HW_HANDSHAKING (US_MR_SPI_USART_MODE_HW_HANDSHAKING_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) Hardware handshaking Position */ +#define US_MR_SPI_USART_MODE_MODEM (US_MR_SPI_USART_MODE_MODEM_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) Modem Position */ +#define US_MR_SPI_USART_MODE_IS07816_T_0 (US_MR_SPI_USART_MODE_IS07816_T_0_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 0 Position */ +#define US_MR_SPI_USART_MODE_IS07816_T_1 (US_MR_SPI_USART_MODE_IS07816_T_1_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) IS07816 Protocol: T = 1 Position */ +#define US_MR_SPI_USART_MODE_IRDA (US_MR_SPI_USART_MODE_IRDA_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) IrDA Position */ +#define US_MR_SPI_USART_MODE_LON (US_MR_SPI_USART_MODE_LON_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) LON Position */ +#define US_MR_SPI_USART_MODE_LIN_MASTER (US_MR_SPI_USART_MODE_LIN_MASTER_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) LIN Master mode Position */ +#define US_MR_SPI_USART_MODE_LIN_SLAVE (US_MR_SPI_USART_MODE_LIN_SLAVE_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) LIN Slave mode Position */ +#define US_MR_SPI_USART_MODE_SPI_MASTER (US_MR_SPI_USART_MODE_SPI_MASTER_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) Position */ +#define US_MR_SPI_USART_MODE_SPI_SLAVE (US_MR_SPI_USART_MODE_SPI_SLAVE_Val << US_MR_SPI_USART_MODE_Pos) /**< (US_MR) SPI Slave mode Position */ +#define US_MR_SPI_USCLKS_Pos _U_(4) /**< (US_MR) Clock Selection Position */ +#define US_MR_SPI_USCLKS_Msk (_U_(0x3) << US_MR_SPI_USCLKS_Pos) /**< (US_MR) Clock Selection Mask */ +#define US_MR_SPI_USCLKS(value) (US_MR_SPI_USCLKS_Msk & ((value) << US_MR_SPI_USCLKS_Pos)) +#define US_MR_SPI_USCLKS_MCK_Val _U_(0x0) /**< (US_MR) Peripheral clock is selected */ +#define US_MR_SPI_USCLKS_DIV_Val _U_(0x1) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected */ +#define US_MR_SPI_USCLKS_PCK_Val _U_(0x2) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_SPI_USCLKS_SCK_Val _U_(0x3) /**< (US_MR) Serial clock (SCK) is selected */ +#define US_MR_SPI_USCLKS_MCK (US_MR_SPI_USCLKS_MCK_Val << US_MR_SPI_USCLKS_Pos) /**< (US_MR) Peripheral clock is selected Position */ +#define US_MR_SPI_USCLKS_DIV (US_MR_SPI_USCLKS_DIV_Val << US_MR_SPI_USCLKS_Pos) /**< (US_MR) Peripheral clock divided (DIV = 8) is selected Position */ +#define US_MR_SPI_USCLKS_PCK (US_MR_SPI_USCLKS_PCK_Val << US_MR_SPI_USCLKS_Pos) /**< (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. Position */ +#define US_MR_SPI_USCLKS_SCK (US_MR_SPI_USCLKS_SCK_Val << US_MR_SPI_USCLKS_Pos) /**< (US_MR) Serial clock (SCK) is selected Position */ +#define US_MR_SPI_CHRL_Pos _U_(6) /**< (US_MR) Character Length Position */ +#define US_MR_SPI_CHRL_Msk (_U_(0x3) << US_MR_SPI_CHRL_Pos) /**< (US_MR) Character Length Mask */ +#define US_MR_SPI_CHRL(value) (US_MR_SPI_CHRL_Msk & ((value) << US_MR_SPI_CHRL_Pos)) +#define US_MR_SPI_CHRL_5_BIT_Val _U_(0x0) /**< (US_MR) Character length is 5 bits */ +#define US_MR_SPI_CHRL_6_BIT_Val _U_(0x1) /**< (US_MR) Character length is 6 bits */ +#define US_MR_SPI_CHRL_7_BIT_Val _U_(0x2) /**< (US_MR) Character length is 7 bits */ +#define US_MR_SPI_CHRL_8_BIT_Val _U_(0x3) /**< (US_MR) Character length is 8 bits */ +#define US_MR_SPI_CHRL_5_BIT (US_MR_SPI_CHRL_5_BIT_Val << US_MR_SPI_CHRL_Pos) /**< (US_MR) Character length is 5 bits Position */ +#define US_MR_SPI_CHRL_6_BIT (US_MR_SPI_CHRL_6_BIT_Val << US_MR_SPI_CHRL_Pos) /**< (US_MR) Character length is 6 bits Position */ +#define US_MR_SPI_CHRL_7_BIT (US_MR_SPI_CHRL_7_BIT_Val << US_MR_SPI_CHRL_Pos) /**< (US_MR) Character length is 7 bits Position */ +#define US_MR_SPI_CHRL_8_BIT (US_MR_SPI_CHRL_8_BIT_Val << US_MR_SPI_CHRL_Pos) /**< (US_MR) Character length is 8 bits Position */ +#define US_MR_SPI_CPHA_Pos _U_(8) /**< (US_MR) SPI Clock Phase Position */ +#define US_MR_SPI_CPHA_Msk (_U_(0x1) << US_MR_SPI_CPHA_Pos) /**< (US_MR) SPI Clock Phase Mask */ +#define US_MR_SPI_CPHA(value) (US_MR_SPI_CPHA_Msk & ((value) << US_MR_SPI_CPHA_Pos)) +#define US_MR_SPI_CPOL_Pos _U_(16) /**< (US_MR) SPI Clock Polarity Position */ +#define US_MR_SPI_CPOL_Msk (_U_(0x1) << US_MR_SPI_CPOL_Pos) /**< (US_MR) SPI Clock Polarity Mask */ +#define US_MR_SPI_CPOL(value) (US_MR_SPI_CPOL_Msk & ((value) << US_MR_SPI_CPOL_Pos)) +#define US_MR_SPI_CLKO_Pos _U_(18) /**< (US_MR) Clock Output Select Position */ +#define US_MR_SPI_CLKO_Msk (_U_(0x1) << US_MR_SPI_CLKO_Pos) /**< (US_MR) Clock Output Select Mask */ +#define US_MR_SPI_CLKO(value) (US_MR_SPI_CLKO_Msk & ((value) << US_MR_SPI_CLKO_Pos)) +#define US_MR_SPI_WRDBT_Pos _U_(20) /**< (US_MR) Wait Read Data Before Transfer Position */ +#define US_MR_SPI_WRDBT_Msk (_U_(0x1) << US_MR_SPI_WRDBT_Pos) /**< (US_MR) Wait Read Data Before Transfer Mask */ +#define US_MR_SPI_WRDBT(value) (US_MR_SPI_WRDBT_Msk & ((value) << US_MR_SPI_WRDBT_Pos)) +#define US_MR_SPI_Msk _U_(0x001501FF) /**< (US_MR_SPI) Register Mask */ + + +/* -------- US_IER : (USART Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */ +#define US_IER_Msk _U_(0x00000000) /**< (US_IER) Register Mask */ + +/* USART mode */ +#define US_IER_USART_RXRDY_Pos _U_(0) /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_USART_RXRDY_Msk (_U_(0x1) << US_IER_USART_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_USART_RXRDY(value) (US_IER_USART_RXRDY_Msk & ((value) << US_IER_USART_RXRDY_Pos)) +#define US_IER_USART_TXRDY_Pos _U_(1) /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_USART_TXRDY_Msk (_U_(0x1) << US_IER_USART_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_USART_TXRDY(value) (US_IER_USART_TXRDY_Msk & ((value) << US_IER_USART_TXRDY_Pos)) +#define US_IER_USART_RXBRK_Pos _U_(2) /**< (US_IER) Receiver Break Interrupt Enable Position */ +#define US_IER_USART_RXBRK_Msk (_U_(0x1) << US_IER_USART_RXBRK_Pos) /**< (US_IER) Receiver Break Interrupt Enable Mask */ +#define US_IER_USART_RXBRK(value) (US_IER_USART_RXBRK_Msk & ((value) << US_IER_USART_RXBRK_Pos)) +#define US_IER_USART_OVRE_Pos _U_(5) /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_USART_OVRE_Msk (_U_(0x1) << US_IER_USART_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_USART_OVRE(value) (US_IER_USART_OVRE_Msk & ((value) << US_IER_USART_OVRE_Pos)) +#define US_IER_USART_FRAME_Pos _U_(6) /**< (US_IER) Framing Error Interrupt Enable Position */ +#define US_IER_USART_FRAME_Msk (_U_(0x1) << US_IER_USART_FRAME_Pos) /**< (US_IER) Framing Error Interrupt Enable Mask */ +#define US_IER_USART_FRAME(value) (US_IER_USART_FRAME_Msk & ((value) << US_IER_USART_FRAME_Pos)) +#define US_IER_USART_PARE_Pos _U_(7) /**< (US_IER) Parity Error Interrupt Enable Position */ +#define US_IER_USART_PARE_Msk (_U_(0x1) << US_IER_USART_PARE_Pos) /**< (US_IER) Parity Error Interrupt Enable Mask */ +#define US_IER_USART_PARE(value) (US_IER_USART_PARE_Msk & ((value) << US_IER_USART_PARE_Pos)) +#define US_IER_USART_TIMEOUT_Pos _U_(8) /**< (US_IER) Timeout Interrupt Enable Position */ +#define US_IER_USART_TIMEOUT_Msk (_U_(0x1) << US_IER_USART_TIMEOUT_Pos) /**< (US_IER) Timeout Interrupt Enable Mask */ +#define US_IER_USART_TIMEOUT(value) (US_IER_USART_TIMEOUT_Msk & ((value) << US_IER_USART_TIMEOUT_Pos)) +#define US_IER_USART_TXEMPTY_Pos _U_(9) /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_USART_TXEMPTY_Msk (_U_(0x1) << US_IER_USART_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_USART_TXEMPTY(value) (US_IER_USART_TXEMPTY_Msk & ((value) << US_IER_USART_TXEMPTY_Pos)) +#define US_IER_USART_ITER_Pos _U_(10) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Position */ +#define US_IER_USART_ITER_Msk (_U_(0x1) << US_IER_USART_ITER_Pos) /**< (US_IER) Max number of Repetitions Reached Interrupt Enable Mask */ +#define US_IER_USART_ITER(value) (US_IER_USART_ITER_Msk & ((value) << US_IER_USART_ITER_Pos)) +#define US_IER_USART_NACK_Pos _U_(13) /**< (US_IER) Non Acknowledge Interrupt Enable Position */ +#define US_IER_USART_NACK_Msk (_U_(0x1) << US_IER_USART_NACK_Pos) /**< (US_IER) Non Acknowledge Interrupt Enable Mask */ +#define US_IER_USART_NACK(value) (US_IER_USART_NACK_Msk & ((value) << US_IER_USART_NACK_Pos)) +#define US_IER_USART_RIIC_Pos _U_(16) /**< (US_IER) Ring Indicator Input Change Enable Position */ +#define US_IER_USART_RIIC_Msk (_U_(0x1) << US_IER_USART_RIIC_Pos) /**< (US_IER) Ring Indicator Input Change Enable Mask */ +#define US_IER_USART_RIIC(value) (US_IER_USART_RIIC_Msk & ((value) << US_IER_USART_RIIC_Pos)) +#define US_IER_USART_DSRIC_Pos _U_(17) /**< (US_IER) Data Set Ready Input Change Enable Position */ +#define US_IER_USART_DSRIC_Msk (_U_(0x1) << US_IER_USART_DSRIC_Pos) /**< (US_IER) Data Set Ready Input Change Enable Mask */ +#define US_IER_USART_DSRIC(value) (US_IER_USART_DSRIC_Msk & ((value) << US_IER_USART_DSRIC_Pos)) +#define US_IER_USART_DCDIC_Pos _U_(18) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Position */ +#define US_IER_USART_DCDIC_Msk (_U_(0x1) << US_IER_USART_DCDIC_Pos) /**< (US_IER) Data Carrier Detect Input Change Interrupt Enable Mask */ +#define US_IER_USART_DCDIC(value) (US_IER_USART_DCDIC_Msk & ((value) << US_IER_USART_DCDIC_Pos)) +#define US_IER_USART_CTSIC_Pos _U_(19) /**< (US_IER) Clear to Send Input Change Interrupt Enable Position */ +#define US_IER_USART_CTSIC_Msk (_U_(0x1) << US_IER_USART_CTSIC_Pos) /**< (US_IER) Clear to Send Input Change Interrupt Enable Mask */ +#define US_IER_USART_CTSIC(value) (US_IER_USART_CTSIC_Msk & ((value) << US_IER_USART_CTSIC_Pos)) +#define US_IER_USART_MANE_Pos _U_(24) /**< (US_IER) Manchester Error Interrupt Enable Position */ +#define US_IER_USART_MANE_Msk (_U_(0x1) << US_IER_USART_MANE_Pos) /**< (US_IER) Manchester Error Interrupt Enable Mask */ +#define US_IER_USART_MANE(value) (US_IER_USART_MANE_Msk & ((value) << US_IER_USART_MANE_Pos)) +#define US_IER_USART_Msk _U_(0x010F27E7) /**< (US_IER_USART) Register Mask */ + +/* SPI mode */ +#define US_IER_SPI_RXRDY_Pos _U_(0) /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_SPI_RXRDY_Msk (_U_(0x1) << US_IER_SPI_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_SPI_RXRDY(value) (US_IER_SPI_RXRDY_Msk & ((value) << US_IER_SPI_RXRDY_Pos)) +#define US_IER_SPI_TXRDY_Pos _U_(1) /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_SPI_TXRDY_Msk (_U_(0x1) << US_IER_SPI_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_SPI_TXRDY(value) (US_IER_SPI_TXRDY_Msk & ((value) << US_IER_SPI_TXRDY_Pos)) +#define US_IER_SPI_OVRE_Pos _U_(5) /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_SPI_OVRE_Msk (_U_(0x1) << US_IER_SPI_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_SPI_OVRE(value) (US_IER_SPI_OVRE_Msk & ((value) << US_IER_SPI_OVRE_Pos)) +#define US_IER_SPI_TXEMPTY_Pos _U_(9) /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_SPI_TXEMPTY_Msk (_U_(0x1) << US_IER_SPI_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_SPI_TXEMPTY(value) (US_IER_SPI_TXEMPTY_Msk & ((value) << US_IER_SPI_TXEMPTY_Pos)) +#define US_IER_SPI_UNRE_Pos _U_(10) /**< (US_IER) Underrun Error Interrupt Enable Position */ +#define US_IER_SPI_UNRE_Msk (_U_(0x1) << US_IER_SPI_UNRE_Pos) /**< (US_IER) Underrun Error Interrupt Enable Mask */ +#define US_IER_SPI_UNRE(value) (US_IER_SPI_UNRE_Msk & ((value) << US_IER_SPI_UNRE_Pos)) +#define US_IER_SPI_NSSE_Pos _U_(19) /**< (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IER_SPI_NSSE_Msk (_U_(0x1) << US_IER_SPI_NSSE_Pos) /**< (US_IER) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IER_SPI_NSSE(value) (US_IER_SPI_NSSE_Msk & ((value) << US_IER_SPI_NSSE_Pos)) +#define US_IER_SPI_Msk _U_(0x00080623) /**< (US_IER_SPI) Register Mask */ + +/* LIN mode */ +#define US_IER_LIN_RXRDY_Pos _U_(0) /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_LIN_RXRDY_Msk (_U_(0x1) << US_IER_LIN_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_LIN_RXRDY(value) (US_IER_LIN_RXRDY_Msk & ((value) << US_IER_LIN_RXRDY_Pos)) +#define US_IER_LIN_TXRDY_Pos _U_(1) /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_LIN_TXRDY_Msk (_U_(0x1) << US_IER_LIN_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_LIN_TXRDY(value) (US_IER_LIN_TXRDY_Msk & ((value) << US_IER_LIN_TXRDY_Pos)) +#define US_IER_LIN_OVRE_Pos _U_(5) /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_LIN_OVRE_Msk (_U_(0x1) << US_IER_LIN_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_LIN_OVRE(value) (US_IER_LIN_OVRE_Msk & ((value) << US_IER_LIN_OVRE_Pos)) +#define US_IER_LIN_FRAME_Pos _U_(6) /**< (US_IER) Framing Error Interrupt Enable Position */ +#define US_IER_LIN_FRAME_Msk (_U_(0x1) << US_IER_LIN_FRAME_Pos) /**< (US_IER) Framing Error Interrupt Enable Mask */ +#define US_IER_LIN_FRAME(value) (US_IER_LIN_FRAME_Msk & ((value) << US_IER_LIN_FRAME_Pos)) +#define US_IER_LIN_PARE_Pos _U_(7) /**< (US_IER) Parity Error Interrupt Enable Position */ +#define US_IER_LIN_PARE_Msk (_U_(0x1) << US_IER_LIN_PARE_Pos) /**< (US_IER) Parity Error Interrupt Enable Mask */ +#define US_IER_LIN_PARE(value) (US_IER_LIN_PARE_Msk & ((value) << US_IER_LIN_PARE_Pos)) +#define US_IER_LIN_TIMEOUT_Pos _U_(8) /**< (US_IER) Timeout Interrupt Enable Position */ +#define US_IER_LIN_TIMEOUT_Msk (_U_(0x1) << US_IER_LIN_TIMEOUT_Pos) /**< (US_IER) Timeout Interrupt Enable Mask */ +#define US_IER_LIN_TIMEOUT(value) (US_IER_LIN_TIMEOUT_Msk & ((value) << US_IER_LIN_TIMEOUT_Pos)) +#define US_IER_LIN_TXEMPTY_Pos _U_(9) /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_LIN_TXEMPTY_Msk (_U_(0x1) << US_IER_LIN_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_LIN_TXEMPTY(value) (US_IER_LIN_TXEMPTY_Msk & ((value) << US_IER_LIN_TXEMPTY_Pos)) +#define US_IER_LIN_LINBK_Pos _U_(13) /**< (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable Position */ +#define US_IER_LIN_LINBK_Msk (_U_(0x1) << US_IER_LIN_LINBK_Pos) /**< (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable Mask */ +#define US_IER_LIN_LINBK(value) (US_IER_LIN_LINBK_Msk & ((value) << US_IER_LIN_LINBK_Pos)) +#define US_IER_LIN_LINID_Pos _U_(14) /**< (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable Position */ +#define US_IER_LIN_LINID_Msk (_U_(0x1) << US_IER_LIN_LINID_Pos) /**< (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable Mask */ +#define US_IER_LIN_LINID(value) (US_IER_LIN_LINID_Msk & ((value) << US_IER_LIN_LINID_Pos)) +#define US_IER_LIN_LINTC_Pos _U_(15) /**< (US_IER) LIN Transfer Completed Interrupt Enable Position */ +#define US_IER_LIN_LINTC_Msk (_U_(0x1) << US_IER_LIN_LINTC_Pos) /**< (US_IER) LIN Transfer Completed Interrupt Enable Mask */ +#define US_IER_LIN_LINTC(value) (US_IER_LIN_LINTC_Msk & ((value) << US_IER_LIN_LINTC_Pos)) +#define US_IER_LIN_LINBE_Pos _U_(25) /**< (US_IER) LIN Bus Error Interrupt Enable Position */ +#define US_IER_LIN_LINBE_Msk (_U_(0x1) << US_IER_LIN_LINBE_Pos) /**< (US_IER) LIN Bus Error Interrupt Enable Mask */ +#define US_IER_LIN_LINBE(value) (US_IER_LIN_LINBE_Msk & ((value) << US_IER_LIN_LINBE_Pos)) +#define US_IER_LIN_LINISFE_Pos _U_(26) /**< (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable Position */ +#define US_IER_LIN_LINISFE_Msk (_U_(0x1) << US_IER_LIN_LINISFE_Pos) /**< (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable Mask */ +#define US_IER_LIN_LINISFE(value) (US_IER_LIN_LINISFE_Msk & ((value) << US_IER_LIN_LINISFE_Pos)) +#define US_IER_LIN_LINIPE_Pos _U_(27) /**< (US_IER) LIN Identifier Parity Interrupt Enable Position */ +#define US_IER_LIN_LINIPE_Msk (_U_(0x1) << US_IER_LIN_LINIPE_Pos) /**< (US_IER) LIN Identifier Parity Interrupt Enable Mask */ +#define US_IER_LIN_LINIPE(value) (US_IER_LIN_LINIPE_Msk & ((value) << US_IER_LIN_LINIPE_Pos)) +#define US_IER_LIN_LINCE_Pos _U_(28) /**< (US_IER) LIN Checksum Error Interrupt Enable Position */ +#define US_IER_LIN_LINCE_Msk (_U_(0x1) << US_IER_LIN_LINCE_Pos) /**< (US_IER) LIN Checksum Error Interrupt Enable Mask */ +#define US_IER_LIN_LINCE(value) (US_IER_LIN_LINCE_Msk & ((value) << US_IER_LIN_LINCE_Pos)) +#define US_IER_LIN_LINSNRE_Pos _U_(29) /**< (US_IER) LIN Slave Not Responding Error Interrupt Enable Position */ +#define US_IER_LIN_LINSNRE_Msk (_U_(0x1) << US_IER_LIN_LINSNRE_Pos) /**< (US_IER) LIN Slave Not Responding Error Interrupt Enable Mask */ +#define US_IER_LIN_LINSNRE(value) (US_IER_LIN_LINSNRE_Msk & ((value) << US_IER_LIN_LINSNRE_Pos)) +#define US_IER_LIN_LINSTE_Pos _U_(30) /**< (US_IER) LIN Synch Tolerance Error Interrupt Enable Position */ +#define US_IER_LIN_LINSTE_Msk (_U_(0x1) << US_IER_LIN_LINSTE_Pos) /**< (US_IER) LIN Synch Tolerance Error Interrupt Enable Mask */ +#define US_IER_LIN_LINSTE(value) (US_IER_LIN_LINSTE_Msk & ((value) << US_IER_LIN_LINSTE_Pos)) +#define US_IER_LIN_LINHTE_Pos _U_(31) /**< (US_IER) LIN Header Timeout Error Interrupt Enable Position */ +#define US_IER_LIN_LINHTE_Msk (_U_(0x1) << US_IER_LIN_LINHTE_Pos) /**< (US_IER) LIN Header Timeout Error Interrupt Enable Mask */ +#define US_IER_LIN_LINHTE(value) (US_IER_LIN_LINHTE_Msk & ((value) << US_IER_LIN_LINHTE_Pos)) +#define US_IER_LIN_Msk _U_(0xFE00E3E3) /**< (US_IER_LIN) Register Mask */ + +/* LON mode */ +#define US_IER_LON_RXRDY_Pos _U_(0) /**< (US_IER) RXRDY Interrupt Enable Position */ +#define US_IER_LON_RXRDY_Msk (_U_(0x1) << US_IER_LON_RXRDY_Pos) /**< (US_IER) RXRDY Interrupt Enable Mask */ +#define US_IER_LON_RXRDY(value) (US_IER_LON_RXRDY_Msk & ((value) << US_IER_LON_RXRDY_Pos)) +#define US_IER_LON_TXRDY_Pos _U_(1) /**< (US_IER) TXRDY Interrupt Enable Position */ +#define US_IER_LON_TXRDY_Msk (_U_(0x1) << US_IER_LON_TXRDY_Pos) /**< (US_IER) TXRDY Interrupt Enable Mask */ +#define US_IER_LON_TXRDY(value) (US_IER_LON_TXRDY_Msk & ((value) << US_IER_LON_TXRDY_Pos)) +#define US_IER_LON_OVRE_Pos _U_(5) /**< (US_IER) Overrun Error Interrupt Enable Position */ +#define US_IER_LON_OVRE_Msk (_U_(0x1) << US_IER_LON_OVRE_Pos) /**< (US_IER) Overrun Error Interrupt Enable Mask */ +#define US_IER_LON_OVRE(value) (US_IER_LON_OVRE_Msk & ((value) << US_IER_LON_OVRE_Pos)) +#define US_IER_LON_LSFE_Pos _U_(6) /**< (US_IER) LON Short Frame Error Interrupt Enable Position */ +#define US_IER_LON_LSFE_Msk (_U_(0x1) << US_IER_LON_LSFE_Pos) /**< (US_IER) LON Short Frame Error Interrupt Enable Mask */ +#define US_IER_LON_LSFE(value) (US_IER_LON_LSFE_Msk & ((value) << US_IER_LON_LSFE_Pos)) +#define US_IER_LON_LCRCE_Pos _U_(7) /**< (US_IER) LON CRC Error Interrupt Enable Position */ +#define US_IER_LON_LCRCE_Msk (_U_(0x1) << US_IER_LON_LCRCE_Pos) /**< (US_IER) LON CRC Error Interrupt Enable Mask */ +#define US_IER_LON_LCRCE(value) (US_IER_LON_LCRCE_Msk & ((value) << US_IER_LON_LCRCE_Pos)) +#define US_IER_LON_TXEMPTY_Pos _U_(9) /**< (US_IER) TXEMPTY Interrupt Enable Position */ +#define US_IER_LON_TXEMPTY_Msk (_U_(0x1) << US_IER_LON_TXEMPTY_Pos) /**< (US_IER) TXEMPTY Interrupt Enable Mask */ +#define US_IER_LON_TXEMPTY(value) (US_IER_LON_TXEMPTY_Msk & ((value) << US_IER_LON_TXEMPTY_Pos)) +#define US_IER_LON_UNRE_Pos _U_(10) /**< (US_IER) Underrun Error Interrupt Enable Position */ +#define US_IER_LON_UNRE_Msk (_U_(0x1) << US_IER_LON_UNRE_Pos) /**< (US_IER) Underrun Error Interrupt Enable Mask */ +#define US_IER_LON_UNRE(value) (US_IER_LON_UNRE_Msk & ((value) << US_IER_LON_UNRE_Pos)) +#define US_IER_LON_LTXD_Pos _U_(24) /**< (US_IER) LON Transmission Done Interrupt Enable Position */ +#define US_IER_LON_LTXD_Msk (_U_(0x1) << US_IER_LON_LTXD_Pos) /**< (US_IER) LON Transmission Done Interrupt Enable Mask */ +#define US_IER_LON_LTXD(value) (US_IER_LON_LTXD_Msk & ((value) << US_IER_LON_LTXD_Pos)) +#define US_IER_LON_LCOL_Pos _U_(25) /**< (US_IER) LON Collision Interrupt Enable Position */ +#define US_IER_LON_LCOL_Msk (_U_(0x1) << US_IER_LON_LCOL_Pos) /**< (US_IER) LON Collision Interrupt Enable Mask */ +#define US_IER_LON_LCOL(value) (US_IER_LON_LCOL_Msk & ((value) << US_IER_LON_LCOL_Pos)) +#define US_IER_LON_LFET_Pos _U_(26) /**< (US_IER) LON Frame Early Termination Interrupt Enable Position */ +#define US_IER_LON_LFET_Msk (_U_(0x1) << US_IER_LON_LFET_Pos) /**< (US_IER) LON Frame Early Termination Interrupt Enable Mask */ +#define US_IER_LON_LFET(value) (US_IER_LON_LFET_Msk & ((value) << US_IER_LON_LFET_Pos)) +#define US_IER_LON_LRXD_Pos _U_(27) /**< (US_IER) LON Reception Done Interrupt Enable Position */ +#define US_IER_LON_LRXD_Msk (_U_(0x1) << US_IER_LON_LRXD_Pos) /**< (US_IER) LON Reception Done Interrupt Enable Mask */ +#define US_IER_LON_LRXD(value) (US_IER_LON_LRXD_Msk & ((value) << US_IER_LON_LRXD_Pos)) +#define US_IER_LON_LBLOVFE_Pos _U_(28) /**< (US_IER) LON Backlog Overflow Error Interrupt Enable Position */ +#define US_IER_LON_LBLOVFE_Msk (_U_(0x1) << US_IER_LON_LBLOVFE_Pos) /**< (US_IER) LON Backlog Overflow Error Interrupt Enable Mask */ +#define US_IER_LON_LBLOVFE(value) (US_IER_LON_LBLOVFE_Msk & ((value) << US_IER_LON_LBLOVFE_Pos)) +#define US_IER_LON_Msk _U_(0x1F0006E3) /**< (US_IER_LON) Register Mask */ + + +/* -------- US_IDR : (USART Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */ +#define US_IDR_Msk _U_(0x00000000) /**< (US_IDR) Register Mask */ + +/* USART mode */ +#define US_IDR_USART_RXRDY_Pos _U_(0) /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_USART_RXRDY_Msk (_U_(0x1) << US_IDR_USART_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_USART_RXRDY(value) (US_IDR_USART_RXRDY_Msk & ((value) << US_IDR_USART_RXRDY_Pos)) +#define US_IDR_USART_TXRDY_Pos _U_(1) /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_USART_TXRDY_Msk (_U_(0x1) << US_IDR_USART_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_USART_TXRDY(value) (US_IDR_USART_TXRDY_Msk & ((value) << US_IDR_USART_TXRDY_Pos)) +#define US_IDR_USART_RXBRK_Pos _U_(2) /**< (US_IDR) Receiver Break Interrupt Disable Position */ +#define US_IDR_USART_RXBRK_Msk (_U_(0x1) << US_IDR_USART_RXBRK_Pos) /**< (US_IDR) Receiver Break Interrupt Disable Mask */ +#define US_IDR_USART_RXBRK(value) (US_IDR_USART_RXBRK_Msk & ((value) << US_IDR_USART_RXBRK_Pos)) +#define US_IDR_USART_OVRE_Pos _U_(5) /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_USART_OVRE_Msk (_U_(0x1) << US_IDR_USART_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_USART_OVRE(value) (US_IDR_USART_OVRE_Msk & ((value) << US_IDR_USART_OVRE_Pos)) +#define US_IDR_USART_FRAME_Pos _U_(6) /**< (US_IDR) Framing Error Interrupt Disable Position */ +#define US_IDR_USART_FRAME_Msk (_U_(0x1) << US_IDR_USART_FRAME_Pos) /**< (US_IDR) Framing Error Interrupt Disable Mask */ +#define US_IDR_USART_FRAME(value) (US_IDR_USART_FRAME_Msk & ((value) << US_IDR_USART_FRAME_Pos)) +#define US_IDR_USART_PARE_Pos _U_(7) /**< (US_IDR) Parity Error Interrupt Disable Position */ +#define US_IDR_USART_PARE_Msk (_U_(0x1) << US_IDR_USART_PARE_Pos) /**< (US_IDR) Parity Error Interrupt Disable Mask */ +#define US_IDR_USART_PARE(value) (US_IDR_USART_PARE_Msk & ((value) << US_IDR_USART_PARE_Pos)) +#define US_IDR_USART_TIMEOUT_Pos _U_(8) /**< (US_IDR) Timeout Interrupt Disable Position */ +#define US_IDR_USART_TIMEOUT_Msk (_U_(0x1) << US_IDR_USART_TIMEOUT_Pos) /**< (US_IDR) Timeout Interrupt Disable Mask */ +#define US_IDR_USART_TIMEOUT(value) (US_IDR_USART_TIMEOUT_Msk & ((value) << US_IDR_USART_TIMEOUT_Pos)) +#define US_IDR_USART_TXEMPTY_Pos _U_(9) /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_USART_TXEMPTY_Msk (_U_(0x1) << US_IDR_USART_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_USART_TXEMPTY(value) (US_IDR_USART_TXEMPTY_Msk & ((value) << US_IDR_USART_TXEMPTY_Pos)) +#define US_IDR_USART_ITER_Pos _U_(10) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Position */ +#define US_IDR_USART_ITER_Msk (_U_(0x1) << US_IDR_USART_ITER_Pos) /**< (US_IDR) Max Number of Repetitions Reached Interrupt Disable Mask */ +#define US_IDR_USART_ITER(value) (US_IDR_USART_ITER_Msk & ((value) << US_IDR_USART_ITER_Pos)) +#define US_IDR_USART_NACK_Pos _U_(13) /**< (US_IDR) Non Acknowledge Interrupt Disable Position */ +#define US_IDR_USART_NACK_Msk (_U_(0x1) << US_IDR_USART_NACK_Pos) /**< (US_IDR) Non Acknowledge Interrupt Disable Mask */ +#define US_IDR_USART_NACK(value) (US_IDR_USART_NACK_Msk & ((value) << US_IDR_USART_NACK_Pos)) +#define US_IDR_USART_RIIC_Pos _U_(16) /**< (US_IDR) Ring Indicator Input Change Disable Position */ +#define US_IDR_USART_RIIC_Msk (_U_(0x1) << US_IDR_USART_RIIC_Pos) /**< (US_IDR) Ring Indicator Input Change Disable Mask */ +#define US_IDR_USART_RIIC(value) (US_IDR_USART_RIIC_Msk & ((value) << US_IDR_USART_RIIC_Pos)) +#define US_IDR_USART_DSRIC_Pos _U_(17) /**< (US_IDR) Data Set Ready Input Change Disable Position */ +#define US_IDR_USART_DSRIC_Msk (_U_(0x1) << US_IDR_USART_DSRIC_Pos) /**< (US_IDR) Data Set Ready Input Change Disable Mask */ +#define US_IDR_USART_DSRIC(value) (US_IDR_USART_DSRIC_Msk & ((value) << US_IDR_USART_DSRIC_Pos)) +#define US_IDR_USART_DCDIC_Pos _U_(18) /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Position */ +#define US_IDR_USART_DCDIC_Msk (_U_(0x1) << US_IDR_USART_DCDIC_Pos) /**< (US_IDR) Data Carrier Detect Input Change Interrupt Disable Mask */ +#define US_IDR_USART_DCDIC(value) (US_IDR_USART_DCDIC_Msk & ((value) << US_IDR_USART_DCDIC_Pos)) +#define US_IDR_USART_CTSIC_Pos _U_(19) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Position */ +#define US_IDR_USART_CTSIC_Msk (_U_(0x1) << US_IDR_USART_CTSIC_Pos) /**< (US_IDR) Clear to Send Input Change Interrupt Disable Mask */ +#define US_IDR_USART_CTSIC(value) (US_IDR_USART_CTSIC_Msk & ((value) << US_IDR_USART_CTSIC_Pos)) +#define US_IDR_USART_MANE_Pos _U_(24) /**< (US_IDR) Manchester Error Interrupt Disable Position */ +#define US_IDR_USART_MANE_Msk (_U_(0x1) << US_IDR_USART_MANE_Pos) /**< (US_IDR) Manchester Error Interrupt Disable Mask */ +#define US_IDR_USART_MANE(value) (US_IDR_USART_MANE_Msk & ((value) << US_IDR_USART_MANE_Pos)) +#define US_IDR_USART_Msk _U_(0x010F27E7) /**< (US_IDR_USART) Register Mask */ + +/* SPI mode */ +#define US_IDR_SPI_RXRDY_Pos _U_(0) /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_SPI_RXRDY_Msk (_U_(0x1) << US_IDR_SPI_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_SPI_RXRDY(value) (US_IDR_SPI_RXRDY_Msk & ((value) << US_IDR_SPI_RXRDY_Pos)) +#define US_IDR_SPI_TXRDY_Pos _U_(1) /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_SPI_TXRDY_Msk (_U_(0x1) << US_IDR_SPI_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_SPI_TXRDY(value) (US_IDR_SPI_TXRDY_Msk & ((value) << US_IDR_SPI_TXRDY_Pos)) +#define US_IDR_SPI_OVRE_Pos _U_(5) /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_SPI_OVRE_Msk (_U_(0x1) << US_IDR_SPI_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_SPI_OVRE(value) (US_IDR_SPI_OVRE_Msk & ((value) << US_IDR_SPI_OVRE_Pos)) +#define US_IDR_SPI_TXEMPTY_Pos _U_(9) /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_SPI_TXEMPTY_Msk (_U_(0x1) << US_IDR_SPI_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_SPI_TXEMPTY(value) (US_IDR_SPI_TXEMPTY_Msk & ((value) << US_IDR_SPI_TXEMPTY_Pos)) +#define US_IDR_SPI_UNRE_Pos _U_(10) /**< (US_IDR) SPI Underrun Error Interrupt Disable Position */ +#define US_IDR_SPI_UNRE_Msk (_U_(0x1) << US_IDR_SPI_UNRE_Pos) /**< (US_IDR) SPI Underrun Error Interrupt Disable Mask */ +#define US_IDR_SPI_UNRE(value) (US_IDR_SPI_UNRE_Msk & ((value) << US_IDR_SPI_UNRE_Pos)) +#define US_IDR_SPI_NSSE_Pos _U_(19) /**< (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IDR_SPI_NSSE_Msk (_U_(0x1) << US_IDR_SPI_NSSE_Pos) /**< (US_IDR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IDR_SPI_NSSE(value) (US_IDR_SPI_NSSE_Msk & ((value) << US_IDR_SPI_NSSE_Pos)) +#define US_IDR_SPI_Msk _U_(0x00080623) /**< (US_IDR_SPI) Register Mask */ + +/* LIN mode */ +#define US_IDR_LIN_RXRDY_Pos _U_(0) /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_LIN_RXRDY_Msk (_U_(0x1) << US_IDR_LIN_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_LIN_RXRDY(value) (US_IDR_LIN_RXRDY_Msk & ((value) << US_IDR_LIN_RXRDY_Pos)) +#define US_IDR_LIN_TXRDY_Pos _U_(1) /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_LIN_TXRDY_Msk (_U_(0x1) << US_IDR_LIN_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_LIN_TXRDY(value) (US_IDR_LIN_TXRDY_Msk & ((value) << US_IDR_LIN_TXRDY_Pos)) +#define US_IDR_LIN_OVRE_Pos _U_(5) /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_LIN_OVRE_Msk (_U_(0x1) << US_IDR_LIN_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_LIN_OVRE(value) (US_IDR_LIN_OVRE_Msk & ((value) << US_IDR_LIN_OVRE_Pos)) +#define US_IDR_LIN_FRAME_Pos _U_(6) /**< (US_IDR) Framing Error Interrupt Disable Position */ +#define US_IDR_LIN_FRAME_Msk (_U_(0x1) << US_IDR_LIN_FRAME_Pos) /**< (US_IDR) Framing Error Interrupt Disable Mask */ +#define US_IDR_LIN_FRAME(value) (US_IDR_LIN_FRAME_Msk & ((value) << US_IDR_LIN_FRAME_Pos)) +#define US_IDR_LIN_PARE_Pos _U_(7) /**< (US_IDR) Parity Error Interrupt Disable Position */ +#define US_IDR_LIN_PARE_Msk (_U_(0x1) << US_IDR_LIN_PARE_Pos) /**< (US_IDR) Parity Error Interrupt Disable Mask */ +#define US_IDR_LIN_PARE(value) (US_IDR_LIN_PARE_Msk & ((value) << US_IDR_LIN_PARE_Pos)) +#define US_IDR_LIN_TIMEOUT_Pos _U_(8) /**< (US_IDR) Timeout Interrupt Disable Position */ +#define US_IDR_LIN_TIMEOUT_Msk (_U_(0x1) << US_IDR_LIN_TIMEOUT_Pos) /**< (US_IDR) Timeout Interrupt Disable Mask */ +#define US_IDR_LIN_TIMEOUT(value) (US_IDR_LIN_TIMEOUT_Msk & ((value) << US_IDR_LIN_TIMEOUT_Pos)) +#define US_IDR_LIN_TXEMPTY_Pos _U_(9) /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_LIN_TXEMPTY_Msk (_U_(0x1) << US_IDR_LIN_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_LIN_TXEMPTY(value) (US_IDR_LIN_TXEMPTY_Msk & ((value) << US_IDR_LIN_TXEMPTY_Pos)) +#define US_IDR_LIN_LINBK_Pos _U_(13) /**< (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable Position */ +#define US_IDR_LIN_LINBK_Msk (_U_(0x1) << US_IDR_LIN_LINBK_Pos) /**< (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable Mask */ +#define US_IDR_LIN_LINBK(value) (US_IDR_LIN_LINBK_Msk & ((value) << US_IDR_LIN_LINBK_Pos)) +#define US_IDR_LIN_LINID_Pos _U_(14) /**< (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable Position */ +#define US_IDR_LIN_LINID_Msk (_U_(0x1) << US_IDR_LIN_LINID_Pos) /**< (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable Mask */ +#define US_IDR_LIN_LINID(value) (US_IDR_LIN_LINID_Msk & ((value) << US_IDR_LIN_LINID_Pos)) +#define US_IDR_LIN_LINTC_Pos _U_(15) /**< (US_IDR) LIN Transfer Completed Interrupt Disable Position */ +#define US_IDR_LIN_LINTC_Msk (_U_(0x1) << US_IDR_LIN_LINTC_Pos) /**< (US_IDR) LIN Transfer Completed Interrupt Disable Mask */ +#define US_IDR_LIN_LINTC(value) (US_IDR_LIN_LINTC_Msk & ((value) << US_IDR_LIN_LINTC_Pos)) +#define US_IDR_LIN_LINBE_Pos _U_(25) /**< (US_IDR) LIN Bus Error Interrupt Disable Position */ +#define US_IDR_LIN_LINBE_Msk (_U_(0x1) << US_IDR_LIN_LINBE_Pos) /**< (US_IDR) LIN Bus Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINBE(value) (US_IDR_LIN_LINBE_Msk & ((value) << US_IDR_LIN_LINBE_Pos)) +#define US_IDR_LIN_LINISFE_Pos _U_(26) /**< (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable Position */ +#define US_IDR_LIN_LINISFE_Msk (_U_(0x1) << US_IDR_LIN_LINISFE_Pos) /**< (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINISFE(value) (US_IDR_LIN_LINISFE_Msk & ((value) << US_IDR_LIN_LINISFE_Pos)) +#define US_IDR_LIN_LINIPE_Pos _U_(27) /**< (US_IDR) LIN Identifier Parity Interrupt Disable Position */ +#define US_IDR_LIN_LINIPE_Msk (_U_(0x1) << US_IDR_LIN_LINIPE_Pos) /**< (US_IDR) LIN Identifier Parity Interrupt Disable Mask */ +#define US_IDR_LIN_LINIPE(value) (US_IDR_LIN_LINIPE_Msk & ((value) << US_IDR_LIN_LINIPE_Pos)) +#define US_IDR_LIN_LINCE_Pos _U_(28) /**< (US_IDR) LIN Checksum Error Interrupt Disable Position */ +#define US_IDR_LIN_LINCE_Msk (_U_(0x1) << US_IDR_LIN_LINCE_Pos) /**< (US_IDR) LIN Checksum Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINCE(value) (US_IDR_LIN_LINCE_Msk & ((value) << US_IDR_LIN_LINCE_Pos)) +#define US_IDR_LIN_LINSNRE_Pos _U_(29) /**< (US_IDR) LIN Slave Not Responding Error Interrupt Disable Position */ +#define US_IDR_LIN_LINSNRE_Msk (_U_(0x1) << US_IDR_LIN_LINSNRE_Pos) /**< (US_IDR) LIN Slave Not Responding Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINSNRE(value) (US_IDR_LIN_LINSNRE_Msk & ((value) << US_IDR_LIN_LINSNRE_Pos)) +#define US_IDR_LIN_LINSTE_Pos _U_(30) /**< (US_IDR) LIN Synch Tolerance Error Interrupt Disable Position */ +#define US_IDR_LIN_LINSTE_Msk (_U_(0x1) << US_IDR_LIN_LINSTE_Pos) /**< (US_IDR) LIN Synch Tolerance Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINSTE(value) (US_IDR_LIN_LINSTE_Msk & ((value) << US_IDR_LIN_LINSTE_Pos)) +#define US_IDR_LIN_LINHTE_Pos _U_(31) /**< (US_IDR) LIN Header Timeout Error Interrupt Disable Position */ +#define US_IDR_LIN_LINHTE_Msk (_U_(0x1) << US_IDR_LIN_LINHTE_Pos) /**< (US_IDR) LIN Header Timeout Error Interrupt Disable Mask */ +#define US_IDR_LIN_LINHTE(value) (US_IDR_LIN_LINHTE_Msk & ((value) << US_IDR_LIN_LINHTE_Pos)) +#define US_IDR_LIN_Msk _U_(0xFE00E3E3) /**< (US_IDR_LIN) Register Mask */ + +/* LON mode */ +#define US_IDR_LON_RXRDY_Pos _U_(0) /**< (US_IDR) RXRDY Interrupt Disable Position */ +#define US_IDR_LON_RXRDY_Msk (_U_(0x1) << US_IDR_LON_RXRDY_Pos) /**< (US_IDR) RXRDY Interrupt Disable Mask */ +#define US_IDR_LON_RXRDY(value) (US_IDR_LON_RXRDY_Msk & ((value) << US_IDR_LON_RXRDY_Pos)) +#define US_IDR_LON_TXRDY_Pos _U_(1) /**< (US_IDR) TXRDY Interrupt Disable Position */ +#define US_IDR_LON_TXRDY_Msk (_U_(0x1) << US_IDR_LON_TXRDY_Pos) /**< (US_IDR) TXRDY Interrupt Disable Mask */ +#define US_IDR_LON_TXRDY(value) (US_IDR_LON_TXRDY_Msk & ((value) << US_IDR_LON_TXRDY_Pos)) +#define US_IDR_LON_OVRE_Pos _U_(5) /**< (US_IDR) Overrun Error Interrupt Enable Position */ +#define US_IDR_LON_OVRE_Msk (_U_(0x1) << US_IDR_LON_OVRE_Pos) /**< (US_IDR) Overrun Error Interrupt Enable Mask */ +#define US_IDR_LON_OVRE(value) (US_IDR_LON_OVRE_Msk & ((value) << US_IDR_LON_OVRE_Pos)) +#define US_IDR_LON_LSFE_Pos _U_(6) /**< (US_IDR) LON Short Frame Error Interrupt Disable Position */ +#define US_IDR_LON_LSFE_Msk (_U_(0x1) << US_IDR_LON_LSFE_Pos) /**< (US_IDR) LON Short Frame Error Interrupt Disable Mask */ +#define US_IDR_LON_LSFE(value) (US_IDR_LON_LSFE_Msk & ((value) << US_IDR_LON_LSFE_Pos)) +#define US_IDR_LON_LCRCE_Pos _U_(7) /**< (US_IDR) LON CRC Error Interrupt Disable Position */ +#define US_IDR_LON_LCRCE_Msk (_U_(0x1) << US_IDR_LON_LCRCE_Pos) /**< (US_IDR) LON CRC Error Interrupt Disable Mask */ +#define US_IDR_LON_LCRCE(value) (US_IDR_LON_LCRCE_Msk & ((value) << US_IDR_LON_LCRCE_Pos)) +#define US_IDR_LON_TXEMPTY_Pos _U_(9) /**< (US_IDR) TXEMPTY Interrupt Disable Position */ +#define US_IDR_LON_TXEMPTY_Msk (_U_(0x1) << US_IDR_LON_TXEMPTY_Pos) /**< (US_IDR) TXEMPTY Interrupt Disable Mask */ +#define US_IDR_LON_TXEMPTY(value) (US_IDR_LON_TXEMPTY_Msk & ((value) << US_IDR_LON_TXEMPTY_Pos)) +#define US_IDR_LON_UNRE_Pos _U_(10) /**< (US_IDR) SPI Underrun Error Interrupt Disable Position */ +#define US_IDR_LON_UNRE_Msk (_U_(0x1) << US_IDR_LON_UNRE_Pos) /**< (US_IDR) SPI Underrun Error Interrupt Disable Mask */ +#define US_IDR_LON_UNRE(value) (US_IDR_LON_UNRE_Msk & ((value) << US_IDR_LON_UNRE_Pos)) +#define US_IDR_LON_LTXD_Pos _U_(24) /**< (US_IDR) LON Transmission Done Interrupt Disable Position */ +#define US_IDR_LON_LTXD_Msk (_U_(0x1) << US_IDR_LON_LTXD_Pos) /**< (US_IDR) LON Transmission Done Interrupt Disable Mask */ +#define US_IDR_LON_LTXD(value) (US_IDR_LON_LTXD_Msk & ((value) << US_IDR_LON_LTXD_Pos)) +#define US_IDR_LON_LCOL_Pos _U_(25) /**< (US_IDR) LON Collision Interrupt Disable Position */ +#define US_IDR_LON_LCOL_Msk (_U_(0x1) << US_IDR_LON_LCOL_Pos) /**< (US_IDR) LON Collision Interrupt Disable Mask */ +#define US_IDR_LON_LCOL(value) (US_IDR_LON_LCOL_Msk & ((value) << US_IDR_LON_LCOL_Pos)) +#define US_IDR_LON_LFET_Pos _U_(26) /**< (US_IDR) LON Frame Early Termination Interrupt Disable Position */ +#define US_IDR_LON_LFET_Msk (_U_(0x1) << US_IDR_LON_LFET_Pos) /**< (US_IDR) LON Frame Early Termination Interrupt Disable Mask */ +#define US_IDR_LON_LFET(value) (US_IDR_LON_LFET_Msk & ((value) << US_IDR_LON_LFET_Pos)) +#define US_IDR_LON_LRXD_Pos _U_(27) /**< (US_IDR) LON Reception Done Interrupt Disable Position */ +#define US_IDR_LON_LRXD_Msk (_U_(0x1) << US_IDR_LON_LRXD_Pos) /**< (US_IDR) LON Reception Done Interrupt Disable Mask */ +#define US_IDR_LON_LRXD(value) (US_IDR_LON_LRXD_Msk & ((value) << US_IDR_LON_LRXD_Pos)) +#define US_IDR_LON_LBLOVFE_Pos _U_(28) /**< (US_IDR) LON Backlog Overflow Error Interrupt Disable Position */ +#define US_IDR_LON_LBLOVFE_Msk (_U_(0x1) << US_IDR_LON_LBLOVFE_Pos) /**< (US_IDR) LON Backlog Overflow Error Interrupt Disable Mask */ +#define US_IDR_LON_LBLOVFE(value) (US_IDR_LON_LBLOVFE_Msk & ((value) << US_IDR_LON_LBLOVFE_Pos)) +#define US_IDR_LON_Msk _U_(0x1F0006E3) /**< (US_IDR_LON) Register Mask */ + + +/* -------- US_IMR : (USART Offset: 0x10) ( R/ 32) Interrupt Mask Register -------- */ +#define US_IMR_Msk _U_(0x00000000) /**< (US_IMR) Register Mask */ + +/* USART mode */ +#define US_IMR_USART_RXRDY_Pos _U_(0) /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_USART_RXRDY_Msk (_U_(0x1) << US_IMR_USART_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_USART_RXRDY(value) (US_IMR_USART_RXRDY_Msk & ((value) << US_IMR_USART_RXRDY_Pos)) +#define US_IMR_USART_TXRDY_Pos _U_(1) /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_USART_TXRDY_Msk (_U_(0x1) << US_IMR_USART_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_USART_TXRDY(value) (US_IMR_USART_TXRDY_Msk & ((value) << US_IMR_USART_TXRDY_Pos)) +#define US_IMR_USART_RXBRK_Pos _U_(2) /**< (US_IMR) Receiver Break Interrupt Mask Position */ +#define US_IMR_USART_RXBRK_Msk (_U_(0x1) << US_IMR_USART_RXBRK_Pos) /**< (US_IMR) Receiver Break Interrupt Mask Mask */ +#define US_IMR_USART_RXBRK(value) (US_IMR_USART_RXBRK_Msk & ((value) << US_IMR_USART_RXBRK_Pos)) +#define US_IMR_USART_OVRE_Pos _U_(5) /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_USART_OVRE_Msk (_U_(0x1) << US_IMR_USART_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_USART_OVRE(value) (US_IMR_USART_OVRE_Msk & ((value) << US_IMR_USART_OVRE_Pos)) +#define US_IMR_USART_FRAME_Pos _U_(6) /**< (US_IMR) Framing Error Interrupt Mask Position */ +#define US_IMR_USART_FRAME_Msk (_U_(0x1) << US_IMR_USART_FRAME_Pos) /**< (US_IMR) Framing Error Interrupt Mask Mask */ +#define US_IMR_USART_FRAME(value) (US_IMR_USART_FRAME_Msk & ((value) << US_IMR_USART_FRAME_Pos)) +#define US_IMR_USART_PARE_Pos _U_(7) /**< (US_IMR) Parity Error Interrupt Mask Position */ +#define US_IMR_USART_PARE_Msk (_U_(0x1) << US_IMR_USART_PARE_Pos) /**< (US_IMR) Parity Error Interrupt Mask Mask */ +#define US_IMR_USART_PARE(value) (US_IMR_USART_PARE_Msk & ((value) << US_IMR_USART_PARE_Pos)) +#define US_IMR_USART_TIMEOUT_Pos _U_(8) /**< (US_IMR) Timeout Interrupt Mask Position */ +#define US_IMR_USART_TIMEOUT_Msk (_U_(0x1) << US_IMR_USART_TIMEOUT_Pos) /**< (US_IMR) Timeout Interrupt Mask Mask */ +#define US_IMR_USART_TIMEOUT(value) (US_IMR_USART_TIMEOUT_Msk & ((value) << US_IMR_USART_TIMEOUT_Pos)) +#define US_IMR_USART_TXEMPTY_Pos _U_(9) /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_USART_TXEMPTY_Msk (_U_(0x1) << US_IMR_USART_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_USART_TXEMPTY(value) (US_IMR_USART_TXEMPTY_Msk & ((value) << US_IMR_USART_TXEMPTY_Pos)) +#define US_IMR_USART_ITER_Pos _U_(10) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Position */ +#define US_IMR_USART_ITER_Msk (_U_(0x1) << US_IMR_USART_ITER_Pos) /**< (US_IMR) Max Number of Repetitions Reached Interrupt Mask Mask */ +#define US_IMR_USART_ITER(value) (US_IMR_USART_ITER_Msk & ((value) << US_IMR_USART_ITER_Pos)) +#define US_IMR_USART_NACK_Pos _U_(13) /**< (US_IMR) Non Acknowledge Interrupt Mask Position */ +#define US_IMR_USART_NACK_Msk (_U_(0x1) << US_IMR_USART_NACK_Pos) /**< (US_IMR) Non Acknowledge Interrupt Mask Mask */ +#define US_IMR_USART_NACK(value) (US_IMR_USART_NACK_Msk & ((value) << US_IMR_USART_NACK_Pos)) +#define US_IMR_USART_RIIC_Pos _U_(16) /**< (US_IMR) Ring Indicator Input Change Mask Position */ +#define US_IMR_USART_RIIC_Msk (_U_(0x1) << US_IMR_USART_RIIC_Pos) /**< (US_IMR) Ring Indicator Input Change Mask Mask */ +#define US_IMR_USART_RIIC(value) (US_IMR_USART_RIIC_Msk & ((value) << US_IMR_USART_RIIC_Pos)) +#define US_IMR_USART_DSRIC_Pos _U_(17) /**< (US_IMR) Data Set Ready Input Change Mask Position */ +#define US_IMR_USART_DSRIC_Msk (_U_(0x1) << US_IMR_USART_DSRIC_Pos) /**< (US_IMR) Data Set Ready Input Change Mask Mask */ +#define US_IMR_USART_DSRIC(value) (US_IMR_USART_DSRIC_Msk & ((value) << US_IMR_USART_DSRIC_Pos)) +#define US_IMR_USART_DCDIC_Pos _U_(18) /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Position */ +#define US_IMR_USART_DCDIC_Msk (_U_(0x1) << US_IMR_USART_DCDIC_Pos) /**< (US_IMR) Data Carrier Detect Input Change Interrupt Mask Mask */ +#define US_IMR_USART_DCDIC(value) (US_IMR_USART_DCDIC_Msk & ((value) << US_IMR_USART_DCDIC_Pos)) +#define US_IMR_USART_CTSIC_Pos _U_(19) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Position */ +#define US_IMR_USART_CTSIC_Msk (_U_(0x1) << US_IMR_USART_CTSIC_Pos) /**< (US_IMR) Clear to Send Input Change Interrupt Mask Mask */ +#define US_IMR_USART_CTSIC(value) (US_IMR_USART_CTSIC_Msk & ((value) << US_IMR_USART_CTSIC_Pos)) +#define US_IMR_USART_MANE_Pos _U_(24) /**< (US_IMR) Manchester Error Interrupt Mask Position */ +#define US_IMR_USART_MANE_Msk (_U_(0x1) << US_IMR_USART_MANE_Pos) /**< (US_IMR) Manchester Error Interrupt Mask Mask */ +#define US_IMR_USART_MANE(value) (US_IMR_USART_MANE_Msk & ((value) << US_IMR_USART_MANE_Pos)) +#define US_IMR_USART_Msk _U_(0x010F27E7) /**< (US_IMR_USART) Register Mask */ + +/* SPI mode */ +#define US_IMR_SPI_RXRDY_Pos _U_(0) /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_SPI_RXRDY_Msk (_U_(0x1) << US_IMR_SPI_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_SPI_RXRDY(value) (US_IMR_SPI_RXRDY_Msk & ((value) << US_IMR_SPI_RXRDY_Pos)) +#define US_IMR_SPI_TXRDY_Pos _U_(1) /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_SPI_TXRDY_Msk (_U_(0x1) << US_IMR_SPI_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_SPI_TXRDY(value) (US_IMR_SPI_TXRDY_Msk & ((value) << US_IMR_SPI_TXRDY_Pos)) +#define US_IMR_SPI_OVRE_Pos _U_(5) /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_SPI_OVRE_Msk (_U_(0x1) << US_IMR_SPI_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_SPI_OVRE(value) (US_IMR_SPI_OVRE_Msk & ((value) << US_IMR_SPI_OVRE_Pos)) +#define US_IMR_SPI_TXEMPTY_Pos _U_(9) /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_SPI_TXEMPTY_Msk (_U_(0x1) << US_IMR_SPI_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_SPI_TXEMPTY(value) (US_IMR_SPI_TXEMPTY_Msk & ((value) << US_IMR_SPI_TXEMPTY_Pos)) +#define US_IMR_SPI_UNRE_Pos _U_(10) /**< (US_IMR) SPI Underrun Error Interrupt Mask Position */ +#define US_IMR_SPI_UNRE_Msk (_U_(0x1) << US_IMR_SPI_UNRE_Pos) /**< (US_IMR) SPI Underrun Error Interrupt Mask Mask */ +#define US_IMR_SPI_UNRE(value) (US_IMR_SPI_UNRE_Msk & ((value) << US_IMR_SPI_UNRE_Pos)) +#define US_IMR_SPI_NSSE_Pos _U_(19) /**< (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_IMR_SPI_NSSE_Msk (_U_(0x1) << US_IMR_SPI_NSSE_Pos) /**< (US_IMR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_IMR_SPI_NSSE(value) (US_IMR_SPI_NSSE_Msk & ((value) << US_IMR_SPI_NSSE_Pos)) +#define US_IMR_SPI_Msk _U_(0x00080623) /**< (US_IMR_SPI) Register Mask */ + +/* LIN mode */ +#define US_IMR_LIN_RXRDY_Pos _U_(0) /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_LIN_RXRDY_Msk (_U_(0x1) << US_IMR_LIN_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_LIN_RXRDY(value) (US_IMR_LIN_RXRDY_Msk & ((value) << US_IMR_LIN_RXRDY_Pos)) +#define US_IMR_LIN_TXRDY_Pos _U_(1) /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_LIN_TXRDY_Msk (_U_(0x1) << US_IMR_LIN_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_LIN_TXRDY(value) (US_IMR_LIN_TXRDY_Msk & ((value) << US_IMR_LIN_TXRDY_Pos)) +#define US_IMR_LIN_OVRE_Pos _U_(5) /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_LIN_OVRE_Msk (_U_(0x1) << US_IMR_LIN_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_LIN_OVRE(value) (US_IMR_LIN_OVRE_Msk & ((value) << US_IMR_LIN_OVRE_Pos)) +#define US_IMR_LIN_FRAME_Pos _U_(6) /**< (US_IMR) Framing Error Interrupt Mask Position */ +#define US_IMR_LIN_FRAME_Msk (_U_(0x1) << US_IMR_LIN_FRAME_Pos) /**< (US_IMR) Framing Error Interrupt Mask Mask */ +#define US_IMR_LIN_FRAME(value) (US_IMR_LIN_FRAME_Msk & ((value) << US_IMR_LIN_FRAME_Pos)) +#define US_IMR_LIN_PARE_Pos _U_(7) /**< (US_IMR) Parity Error Interrupt Mask Position */ +#define US_IMR_LIN_PARE_Msk (_U_(0x1) << US_IMR_LIN_PARE_Pos) /**< (US_IMR) Parity Error Interrupt Mask Mask */ +#define US_IMR_LIN_PARE(value) (US_IMR_LIN_PARE_Msk & ((value) << US_IMR_LIN_PARE_Pos)) +#define US_IMR_LIN_TIMEOUT_Pos _U_(8) /**< (US_IMR) Timeout Interrupt Mask Position */ +#define US_IMR_LIN_TIMEOUT_Msk (_U_(0x1) << US_IMR_LIN_TIMEOUT_Pos) /**< (US_IMR) Timeout Interrupt Mask Mask */ +#define US_IMR_LIN_TIMEOUT(value) (US_IMR_LIN_TIMEOUT_Msk & ((value) << US_IMR_LIN_TIMEOUT_Pos)) +#define US_IMR_LIN_TXEMPTY_Pos _U_(9) /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_LIN_TXEMPTY_Msk (_U_(0x1) << US_IMR_LIN_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_LIN_TXEMPTY(value) (US_IMR_LIN_TXEMPTY_Msk & ((value) << US_IMR_LIN_TXEMPTY_Pos)) +#define US_IMR_LIN_LINBK_Pos _U_(13) /**< (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask Position */ +#define US_IMR_LIN_LINBK_Msk (_U_(0x1) << US_IMR_LIN_LINBK_Pos) /**< (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask Mask */ +#define US_IMR_LIN_LINBK(value) (US_IMR_LIN_LINBK_Msk & ((value) << US_IMR_LIN_LINBK_Pos)) +#define US_IMR_LIN_LINID_Pos _U_(14) /**< (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask Position */ +#define US_IMR_LIN_LINID_Msk (_U_(0x1) << US_IMR_LIN_LINID_Pos) /**< (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask Mask */ +#define US_IMR_LIN_LINID(value) (US_IMR_LIN_LINID_Msk & ((value) << US_IMR_LIN_LINID_Pos)) +#define US_IMR_LIN_LINTC_Pos _U_(15) /**< (US_IMR) LIN Transfer Completed Interrupt Mask Position */ +#define US_IMR_LIN_LINTC_Msk (_U_(0x1) << US_IMR_LIN_LINTC_Pos) /**< (US_IMR) LIN Transfer Completed Interrupt Mask Mask */ +#define US_IMR_LIN_LINTC(value) (US_IMR_LIN_LINTC_Msk & ((value) << US_IMR_LIN_LINTC_Pos)) +#define US_IMR_LIN_LINBE_Pos _U_(25) /**< (US_IMR) LIN Bus Error Interrupt Mask Position */ +#define US_IMR_LIN_LINBE_Msk (_U_(0x1) << US_IMR_LIN_LINBE_Pos) /**< (US_IMR) LIN Bus Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINBE(value) (US_IMR_LIN_LINBE_Msk & ((value) << US_IMR_LIN_LINBE_Pos)) +#define US_IMR_LIN_LINISFE_Pos _U_(26) /**< (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask Position */ +#define US_IMR_LIN_LINISFE_Msk (_U_(0x1) << US_IMR_LIN_LINISFE_Pos) /**< (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINISFE(value) (US_IMR_LIN_LINISFE_Msk & ((value) << US_IMR_LIN_LINISFE_Pos)) +#define US_IMR_LIN_LINIPE_Pos _U_(27) /**< (US_IMR) LIN Identifier Parity Interrupt Mask Position */ +#define US_IMR_LIN_LINIPE_Msk (_U_(0x1) << US_IMR_LIN_LINIPE_Pos) /**< (US_IMR) LIN Identifier Parity Interrupt Mask Mask */ +#define US_IMR_LIN_LINIPE(value) (US_IMR_LIN_LINIPE_Msk & ((value) << US_IMR_LIN_LINIPE_Pos)) +#define US_IMR_LIN_LINCE_Pos _U_(28) /**< (US_IMR) LIN Checksum Error Interrupt Mask Position */ +#define US_IMR_LIN_LINCE_Msk (_U_(0x1) << US_IMR_LIN_LINCE_Pos) /**< (US_IMR) LIN Checksum Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINCE(value) (US_IMR_LIN_LINCE_Msk & ((value) << US_IMR_LIN_LINCE_Pos)) +#define US_IMR_LIN_LINSNRE_Pos _U_(29) /**< (US_IMR) LIN Slave Not Responding Error Interrupt Mask Position */ +#define US_IMR_LIN_LINSNRE_Msk (_U_(0x1) << US_IMR_LIN_LINSNRE_Pos) /**< (US_IMR) LIN Slave Not Responding Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINSNRE(value) (US_IMR_LIN_LINSNRE_Msk & ((value) << US_IMR_LIN_LINSNRE_Pos)) +#define US_IMR_LIN_LINSTE_Pos _U_(30) /**< (US_IMR) LIN Synch Tolerance Error Interrupt Mask Position */ +#define US_IMR_LIN_LINSTE_Msk (_U_(0x1) << US_IMR_LIN_LINSTE_Pos) /**< (US_IMR) LIN Synch Tolerance Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINSTE(value) (US_IMR_LIN_LINSTE_Msk & ((value) << US_IMR_LIN_LINSTE_Pos)) +#define US_IMR_LIN_LINHTE_Pos _U_(31) /**< (US_IMR) LIN Header Timeout Error Interrupt Mask Position */ +#define US_IMR_LIN_LINHTE_Msk (_U_(0x1) << US_IMR_LIN_LINHTE_Pos) /**< (US_IMR) LIN Header Timeout Error Interrupt Mask Mask */ +#define US_IMR_LIN_LINHTE(value) (US_IMR_LIN_LINHTE_Msk & ((value) << US_IMR_LIN_LINHTE_Pos)) +#define US_IMR_LIN_Msk _U_(0xFE00E3E3) /**< (US_IMR_LIN) Register Mask */ + +/* LON mode */ +#define US_IMR_LON_RXRDY_Pos _U_(0) /**< (US_IMR) RXRDY Interrupt Mask Position */ +#define US_IMR_LON_RXRDY_Msk (_U_(0x1) << US_IMR_LON_RXRDY_Pos) /**< (US_IMR) RXRDY Interrupt Mask Mask */ +#define US_IMR_LON_RXRDY(value) (US_IMR_LON_RXRDY_Msk & ((value) << US_IMR_LON_RXRDY_Pos)) +#define US_IMR_LON_TXRDY_Pos _U_(1) /**< (US_IMR) TXRDY Interrupt Mask Position */ +#define US_IMR_LON_TXRDY_Msk (_U_(0x1) << US_IMR_LON_TXRDY_Pos) /**< (US_IMR) TXRDY Interrupt Mask Mask */ +#define US_IMR_LON_TXRDY(value) (US_IMR_LON_TXRDY_Msk & ((value) << US_IMR_LON_TXRDY_Pos)) +#define US_IMR_LON_OVRE_Pos _U_(5) /**< (US_IMR) Overrun Error Interrupt Mask Position */ +#define US_IMR_LON_OVRE_Msk (_U_(0x1) << US_IMR_LON_OVRE_Pos) /**< (US_IMR) Overrun Error Interrupt Mask Mask */ +#define US_IMR_LON_OVRE(value) (US_IMR_LON_OVRE_Msk & ((value) << US_IMR_LON_OVRE_Pos)) +#define US_IMR_LON_LSFE_Pos _U_(6) /**< (US_IMR) LON Short Frame Error Interrupt Mask Position */ +#define US_IMR_LON_LSFE_Msk (_U_(0x1) << US_IMR_LON_LSFE_Pos) /**< (US_IMR) LON Short Frame Error Interrupt Mask Mask */ +#define US_IMR_LON_LSFE(value) (US_IMR_LON_LSFE_Msk & ((value) << US_IMR_LON_LSFE_Pos)) +#define US_IMR_LON_LCRCE_Pos _U_(7) /**< (US_IMR) LON CRC Error Interrupt Mask Position */ +#define US_IMR_LON_LCRCE_Msk (_U_(0x1) << US_IMR_LON_LCRCE_Pos) /**< (US_IMR) LON CRC Error Interrupt Mask Mask */ +#define US_IMR_LON_LCRCE(value) (US_IMR_LON_LCRCE_Msk & ((value) << US_IMR_LON_LCRCE_Pos)) +#define US_IMR_LON_TXEMPTY_Pos _U_(9) /**< (US_IMR) TXEMPTY Interrupt Mask Position */ +#define US_IMR_LON_TXEMPTY_Msk (_U_(0x1) << US_IMR_LON_TXEMPTY_Pos) /**< (US_IMR) TXEMPTY Interrupt Mask Mask */ +#define US_IMR_LON_TXEMPTY(value) (US_IMR_LON_TXEMPTY_Msk & ((value) << US_IMR_LON_TXEMPTY_Pos)) +#define US_IMR_LON_UNRE_Pos _U_(10) /**< (US_IMR) SPI Underrun Error Interrupt Mask Position */ +#define US_IMR_LON_UNRE_Msk (_U_(0x1) << US_IMR_LON_UNRE_Pos) /**< (US_IMR) SPI Underrun Error Interrupt Mask Mask */ +#define US_IMR_LON_UNRE(value) (US_IMR_LON_UNRE_Msk & ((value) << US_IMR_LON_UNRE_Pos)) +#define US_IMR_LON_LTXD_Pos _U_(24) /**< (US_IMR) LON Transmission Done Interrupt Mask Position */ +#define US_IMR_LON_LTXD_Msk (_U_(0x1) << US_IMR_LON_LTXD_Pos) /**< (US_IMR) LON Transmission Done Interrupt Mask Mask */ +#define US_IMR_LON_LTXD(value) (US_IMR_LON_LTXD_Msk & ((value) << US_IMR_LON_LTXD_Pos)) +#define US_IMR_LON_LCOL_Pos _U_(25) /**< (US_IMR) LON Collision Interrupt Mask Position */ +#define US_IMR_LON_LCOL_Msk (_U_(0x1) << US_IMR_LON_LCOL_Pos) /**< (US_IMR) LON Collision Interrupt Mask Mask */ +#define US_IMR_LON_LCOL(value) (US_IMR_LON_LCOL_Msk & ((value) << US_IMR_LON_LCOL_Pos)) +#define US_IMR_LON_LFET_Pos _U_(26) /**< (US_IMR) LON Frame Early Termination Interrupt Mask Position */ +#define US_IMR_LON_LFET_Msk (_U_(0x1) << US_IMR_LON_LFET_Pos) /**< (US_IMR) LON Frame Early Termination Interrupt Mask Mask */ +#define US_IMR_LON_LFET(value) (US_IMR_LON_LFET_Msk & ((value) << US_IMR_LON_LFET_Pos)) +#define US_IMR_LON_LRXD_Pos _U_(27) /**< (US_IMR) LON Reception Done Interrupt Mask Position */ +#define US_IMR_LON_LRXD_Msk (_U_(0x1) << US_IMR_LON_LRXD_Pos) /**< (US_IMR) LON Reception Done Interrupt Mask Mask */ +#define US_IMR_LON_LRXD(value) (US_IMR_LON_LRXD_Msk & ((value) << US_IMR_LON_LRXD_Pos)) +#define US_IMR_LON_LBLOVFE_Pos _U_(28) /**< (US_IMR) LON Backlog Overflow Error Interrupt Mask Position */ +#define US_IMR_LON_LBLOVFE_Msk (_U_(0x1) << US_IMR_LON_LBLOVFE_Pos) /**< (US_IMR) LON Backlog Overflow Error Interrupt Mask Mask */ +#define US_IMR_LON_LBLOVFE(value) (US_IMR_LON_LBLOVFE_Msk & ((value) << US_IMR_LON_LBLOVFE_Pos)) +#define US_IMR_LON_Msk _U_(0x1F0006E3) /**< (US_IMR_LON) Register Mask */ + + +/* -------- US_CSR : (USART Offset: 0x14) ( R/ 32) Channel Status Register -------- */ +#define US_CSR_Msk _U_(0x00000000) /**< (US_CSR) Register Mask */ + +/* USART mode */ +#define US_CSR_USART_RXRDY_Pos _U_(0) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_USART_RXRDY_Msk (_U_(0x1) << US_CSR_USART_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_USART_RXRDY(value) (US_CSR_USART_RXRDY_Msk & ((value) << US_CSR_USART_RXRDY_Pos)) +#define US_CSR_USART_TXRDY_Pos _U_(1) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_USART_TXRDY_Msk (_U_(0x1) << US_CSR_USART_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_USART_TXRDY(value) (US_CSR_USART_TXRDY_Msk & ((value) << US_CSR_USART_TXRDY_Pos)) +#define US_CSR_USART_RXBRK_Pos _U_(2) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_RXBRK_Msk (_U_(0x1) << US_CSR_USART_RXBRK_Pos) /**< (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_RXBRK(value) (US_CSR_USART_RXBRK_Msk & ((value) << US_CSR_USART_RXBRK_Pos)) +#define US_CSR_USART_OVRE_Pos _U_(5) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_OVRE_Msk (_U_(0x1) << US_CSR_USART_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_OVRE(value) (US_CSR_USART_OVRE_Msk & ((value) << US_CSR_USART_OVRE_Pos)) +#define US_CSR_USART_FRAME_Pos _U_(6) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_FRAME_Msk (_U_(0x1) << US_CSR_USART_FRAME_Pos) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_FRAME(value) (US_CSR_USART_FRAME_Msk & ((value) << US_CSR_USART_FRAME_Pos)) +#define US_CSR_USART_PARE_Pos _U_(7) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_PARE_Msk (_U_(0x1) << US_CSR_USART_PARE_Pos) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_PARE(value) (US_CSR_USART_PARE_Msk & ((value) << US_CSR_USART_PARE_Pos)) +#define US_CSR_USART_TIMEOUT_Pos _U_(8) /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Position */ +#define US_CSR_USART_TIMEOUT_Msk (_U_(0x1) << US_CSR_USART_TIMEOUT_Pos) /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Mask */ +#define US_CSR_USART_TIMEOUT(value) (US_CSR_USART_TIMEOUT_Msk & ((value) << US_CSR_USART_TIMEOUT_Pos)) +#define US_CSR_USART_TXEMPTY_Pos _U_(9) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_USART_TXEMPTY_Msk (_U_(0x1) << US_CSR_USART_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_USART_TXEMPTY(value) (US_CSR_USART_TXEMPTY_Msk & ((value) << US_CSR_USART_TXEMPTY_Pos)) +#define US_CSR_USART_ITER_Pos _U_(10) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Position */ +#define US_CSR_USART_ITER_Msk (_U_(0x1) << US_CSR_USART_ITER_Pos) /**< (US_CSR) Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) Mask */ +#define US_CSR_USART_ITER(value) (US_CSR_USART_ITER_Msk & ((value) << US_CSR_USART_ITER_Pos)) +#define US_CSR_USART_NACK_Pos _U_(13) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Position */ +#define US_CSR_USART_NACK_Msk (_U_(0x1) << US_CSR_USART_NACK_Pos) /**< (US_CSR) Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) Mask */ +#define US_CSR_USART_NACK(value) (US_CSR_USART_NACK_Msk & ((value) << US_CSR_USART_NACK_Pos)) +#define US_CSR_USART_RIIC_Pos _U_(16) /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Position */ +#define US_CSR_USART_RIIC_Msk (_U_(0x1) << US_CSR_USART_RIIC_Pos) /**< (US_CSR) Ring Indicator Input Change Flag (cleared on read) Mask */ +#define US_CSR_USART_RIIC(value) (US_CSR_USART_RIIC_Msk & ((value) << US_CSR_USART_RIIC_Pos)) +#define US_CSR_USART_DSRIC_Pos _U_(17) /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Position */ +#define US_CSR_USART_DSRIC_Msk (_U_(0x1) << US_CSR_USART_DSRIC_Pos) /**< (US_CSR) Data Set Ready Input Change Flag (cleared on read) Mask */ +#define US_CSR_USART_DSRIC(value) (US_CSR_USART_DSRIC_Msk & ((value) << US_CSR_USART_DSRIC_Pos)) +#define US_CSR_USART_DCDIC_Pos _U_(18) /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Position */ +#define US_CSR_USART_DCDIC_Msk (_U_(0x1) << US_CSR_USART_DCDIC_Pos) /**< (US_CSR) Data Carrier Detect Input Change Flag (cleared on read) Mask */ +#define US_CSR_USART_DCDIC(value) (US_CSR_USART_DCDIC_Msk & ((value) << US_CSR_USART_DCDIC_Pos)) +#define US_CSR_USART_CTSIC_Pos _U_(19) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Position */ +#define US_CSR_USART_CTSIC_Msk (_U_(0x1) << US_CSR_USART_CTSIC_Pos) /**< (US_CSR) Clear to Send Input Change Flag (cleared on read) Mask */ +#define US_CSR_USART_CTSIC(value) (US_CSR_USART_CTSIC_Msk & ((value) << US_CSR_USART_CTSIC_Pos)) +#define US_CSR_USART_RI_Pos _U_(20) /**< (US_CSR) Image of RI Input Position */ +#define US_CSR_USART_RI_Msk (_U_(0x1) << US_CSR_USART_RI_Pos) /**< (US_CSR) Image of RI Input Mask */ +#define US_CSR_USART_RI(value) (US_CSR_USART_RI_Msk & ((value) << US_CSR_USART_RI_Pos)) +#define US_CSR_USART_DSR_Pos _U_(21) /**< (US_CSR) Image of DSR Input Position */ +#define US_CSR_USART_DSR_Msk (_U_(0x1) << US_CSR_USART_DSR_Pos) /**< (US_CSR) Image of DSR Input Mask */ +#define US_CSR_USART_DSR(value) (US_CSR_USART_DSR_Msk & ((value) << US_CSR_USART_DSR_Pos)) +#define US_CSR_USART_DCD_Pos _U_(22) /**< (US_CSR) Image of DCD Input Position */ +#define US_CSR_USART_DCD_Msk (_U_(0x1) << US_CSR_USART_DCD_Pos) /**< (US_CSR) Image of DCD Input Mask */ +#define US_CSR_USART_DCD(value) (US_CSR_USART_DCD_Msk & ((value) << US_CSR_USART_DCD_Pos)) +#define US_CSR_USART_CTS_Pos _U_(23) /**< (US_CSR) Image of CTS Input Position */ +#define US_CSR_USART_CTS_Msk (_U_(0x1) << US_CSR_USART_CTS_Pos) /**< (US_CSR) Image of CTS Input Mask */ +#define US_CSR_USART_CTS(value) (US_CSR_USART_CTS_Msk & ((value) << US_CSR_USART_CTS_Pos)) +#define US_CSR_USART_MANERR_Pos _U_(24) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Position */ +#define US_CSR_USART_MANERR_Msk (_U_(0x1) << US_CSR_USART_MANERR_Pos) /**< (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) Mask */ +#define US_CSR_USART_MANERR(value) (US_CSR_USART_MANERR_Msk & ((value) << US_CSR_USART_MANERR_Pos)) +#define US_CSR_USART_Msk _U_(0x01FF27E7) /**< (US_CSR_USART) Register Mask */ + +/* SPI mode */ +#define US_CSR_SPI_RXRDY_Pos _U_(0) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_SPI_RXRDY_Msk (_U_(0x1) << US_CSR_SPI_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_SPI_RXRDY(value) (US_CSR_SPI_RXRDY_Msk & ((value) << US_CSR_SPI_RXRDY_Pos)) +#define US_CSR_SPI_TXRDY_Pos _U_(1) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_SPI_TXRDY_Msk (_U_(0x1) << US_CSR_SPI_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_SPI_TXRDY(value) (US_CSR_SPI_TXRDY_Msk & ((value) << US_CSR_SPI_TXRDY_Pos)) +#define US_CSR_SPI_OVRE_Pos _U_(5) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_SPI_OVRE_Msk (_U_(0x1) << US_CSR_SPI_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_SPI_OVRE(value) (US_CSR_SPI_OVRE_Msk & ((value) << US_CSR_SPI_OVRE_Pos)) +#define US_CSR_SPI_TXEMPTY_Pos _U_(9) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_SPI_TXEMPTY_Msk (_U_(0x1) << US_CSR_SPI_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_SPI_TXEMPTY(value) (US_CSR_SPI_TXEMPTY_Msk & ((value) << US_CSR_SPI_TXEMPTY_Pos)) +#define US_CSR_SPI_UNRE_Pos _U_(10) /**< (US_CSR) SPI Underrun Error Position */ +#define US_CSR_SPI_UNRE_Msk (_U_(0x1) << US_CSR_SPI_UNRE_Pos) /**< (US_CSR) SPI Underrun Error Mask */ +#define US_CSR_SPI_UNRE(value) (US_CSR_SPI_UNRE_Msk & ((value) << US_CSR_SPI_UNRE_Pos)) +#define US_CSR_SPI_NSSE_Pos _U_(19) /**< (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Position */ +#define US_CSR_SPI_NSSE_Msk (_U_(0x1) << US_CSR_SPI_NSSE_Pos) /**< (US_CSR) NSS Line (Driving CTS Pin) Rising or Falling Edge Event Mask */ +#define US_CSR_SPI_NSSE(value) (US_CSR_SPI_NSSE_Msk & ((value) << US_CSR_SPI_NSSE_Pos)) +#define US_CSR_SPI_NSS_Pos _U_(23) /**< (US_CSR) Image of NSS Line Position */ +#define US_CSR_SPI_NSS_Msk (_U_(0x1) << US_CSR_SPI_NSS_Pos) /**< (US_CSR) Image of NSS Line Mask */ +#define US_CSR_SPI_NSS(value) (US_CSR_SPI_NSS_Msk & ((value) << US_CSR_SPI_NSS_Pos)) +#define US_CSR_SPI_Msk _U_(0x00880623) /**< (US_CSR_SPI) Register Mask */ + +/* LIN mode */ +#define US_CSR_LIN_RXRDY_Pos _U_(0) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_LIN_RXRDY_Msk (_U_(0x1) << US_CSR_LIN_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_LIN_RXRDY(value) (US_CSR_LIN_RXRDY_Msk & ((value) << US_CSR_LIN_RXRDY_Pos)) +#define US_CSR_LIN_TXRDY_Pos _U_(1) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_LIN_TXRDY_Msk (_U_(0x1) << US_CSR_LIN_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_LIN_TXRDY(value) (US_CSR_LIN_TXRDY_Msk & ((value) << US_CSR_LIN_TXRDY_Pos)) +#define US_CSR_LIN_OVRE_Pos _U_(5) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_LIN_OVRE_Msk (_U_(0x1) << US_CSR_LIN_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_LIN_OVRE(value) (US_CSR_LIN_OVRE_Msk & ((value) << US_CSR_LIN_OVRE_Pos)) +#define US_CSR_LIN_FRAME_Pos _U_(6) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_LIN_FRAME_Msk (_U_(0x1) << US_CSR_LIN_FRAME_Pos) /**< (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_LIN_FRAME(value) (US_CSR_LIN_FRAME_Msk & ((value) << US_CSR_LIN_FRAME_Pos)) +#define US_CSR_LIN_PARE_Pos _U_(7) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_LIN_PARE_Msk (_U_(0x1) << US_CSR_LIN_PARE_Pos) /**< (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_LIN_PARE(value) (US_CSR_LIN_PARE_Msk & ((value) << US_CSR_LIN_PARE_Pos)) +#define US_CSR_LIN_TIMEOUT_Pos _U_(8) /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Position */ +#define US_CSR_LIN_TIMEOUT_Msk (_U_(0x1) << US_CSR_LIN_TIMEOUT_Pos) /**< (US_CSR) Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) Mask */ +#define US_CSR_LIN_TIMEOUT(value) (US_CSR_LIN_TIMEOUT_Msk & ((value) << US_CSR_LIN_TIMEOUT_Pos)) +#define US_CSR_LIN_TXEMPTY_Pos _U_(9) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_LIN_TXEMPTY_Msk (_U_(0x1) << US_CSR_LIN_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_LIN_TXEMPTY(value) (US_CSR_LIN_TXEMPTY_Msk & ((value) << US_CSR_LIN_TXEMPTY_Pos)) +#define US_CSR_LIN_LINBK_Pos _U_(13) /**< (US_CSR) LIN Break Sent or LIN Break Received Position */ +#define US_CSR_LIN_LINBK_Msk (_U_(0x1) << US_CSR_LIN_LINBK_Pos) /**< (US_CSR) LIN Break Sent or LIN Break Received Mask */ +#define US_CSR_LIN_LINBK(value) (US_CSR_LIN_LINBK_Msk & ((value) << US_CSR_LIN_LINBK_Pos)) +#define US_CSR_LIN_LINID_Pos _U_(14) /**< (US_CSR) LIN Identifier Sent or LIN Identifier Received Position */ +#define US_CSR_LIN_LINID_Msk (_U_(0x1) << US_CSR_LIN_LINID_Pos) /**< (US_CSR) LIN Identifier Sent or LIN Identifier Received Mask */ +#define US_CSR_LIN_LINID(value) (US_CSR_LIN_LINID_Msk & ((value) << US_CSR_LIN_LINID_Pos)) +#define US_CSR_LIN_LINTC_Pos _U_(15) /**< (US_CSR) LIN Transfer Completed Position */ +#define US_CSR_LIN_LINTC_Msk (_U_(0x1) << US_CSR_LIN_LINTC_Pos) /**< (US_CSR) LIN Transfer Completed Mask */ +#define US_CSR_LIN_LINTC(value) (US_CSR_LIN_LINTC_Msk & ((value) << US_CSR_LIN_LINTC_Pos)) +#define US_CSR_LIN_LINBLS_Pos _U_(23) /**< (US_CSR) LIN Bus Line Status Position */ +#define US_CSR_LIN_LINBLS_Msk (_U_(0x1) << US_CSR_LIN_LINBLS_Pos) /**< (US_CSR) LIN Bus Line Status Mask */ +#define US_CSR_LIN_LINBLS(value) (US_CSR_LIN_LINBLS_Msk & ((value) << US_CSR_LIN_LINBLS_Pos)) +#define US_CSR_LIN_LINBE_Pos _U_(25) /**< (US_CSR) LIN Bus Error Position */ +#define US_CSR_LIN_LINBE_Msk (_U_(0x1) << US_CSR_LIN_LINBE_Pos) /**< (US_CSR) LIN Bus Error Mask */ +#define US_CSR_LIN_LINBE(value) (US_CSR_LIN_LINBE_Msk & ((value) << US_CSR_LIN_LINBE_Pos)) +#define US_CSR_LIN_LINISFE_Pos _U_(26) /**< (US_CSR) LIN Inconsistent Synch Field Error Position */ +#define US_CSR_LIN_LINISFE_Msk (_U_(0x1) << US_CSR_LIN_LINISFE_Pos) /**< (US_CSR) LIN Inconsistent Synch Field Error Mask */ +#define US_CSR_LIN_LINISFE(value) (US_CSR_LIN_LINISFE_Msk & ((value) << US_CSR_LIN_LINISFE_Pos)) +#define US_CSR_LIN_LINIPE_Pos _U_(27) /**< (US_CSR) LIN Identifier Parity Error Position */ +#define US_CSR_LIN_LINIPE_Msk (_U_(0x1) << US_CSR_LIN_LINIPE_Pos) /**< (US_CSR) LIN Identifier Parity Error Mask */ +#define US_CSR_LIN_LINIPE(value) (US_CSR_LIN_LINIPE_Msk & ((value) << US_CSR_LIN_LINIPE_Pos)) +#define US_CSR_LIN_LINCE_Pos _U_(28) /**< (US_CSR) LIN Checksum Error Position */ +#define US_CSR_LIN_LINCE_Msk (_U_(0x1) << US_CSR_LIN_LINCE_Pos) /**< (US_CSR) LIN Checksum Error Mask */ +#define US_CSR_LIN_LINCE(value) (US_CSR_LIN_LINCE_Msk & ((value) << US_CSR_LIN_LINCE_Pos)) +#define US_CSR_LIN_LINSNRE_Pos _U_(29) /**< (US_CSR) LIN Slave Not Responding Error Interrupt Mask Position */ +#define US_CSR_LIN_LINSNRE_Msk (_U_(0x1) << US_CSR_LIN_LINSNRE_Pos) /**< (US_CSR) LIN Slave Not Responding Error Interrupt Mask Mask */ +#define US_CSR_LIN_LINSNRE(value) (US_CSR_LIN_LINSNRE_Msk & ((value) << US_CSR_LIN_LINSNRE_Pos)) +#define US_CSR_LIN_LINSTE_Pos _U_(30) /**< (US_CSR) LIN Synch Tolerance Error Position */ +#define US_CSR_LIN_LINSTE_Msk (_U_(0x1) << US_CSR_LIN_LINSTE_Pos) /**< (US_CSR) LIN Synch Tolerance Error Mask */ +#define US_CSR_LIN_LINSTE(value) (US_CSR_LIN_LINSTE_Msk & ((value) << US_CSR_LIN_LINSTE_Pos)) +#define US_CSR_LIN_LINHTE_Pos _U_(31) /**< (US_CSR) LIN Header Timeout Error Position */ +#define US_CSR_LIN_LINHTE_Msk (_U_(0x1) << US_CSR_LIN_LINHTE_Pos) /**< (US_CSR) LIN Header Timeout Error Mask */ +#define US_CSR_LIN_LINHTE(value) (US_CSR_LIN_LINHTE_Msk & ((value) << US_CSR_LIN_LINHTE_Pos)) +#define US_CSR_LIN_Msk _U_(0xFE80E3E3) /**< (US_CSR_LIN) Register Mask */ + +/* LON mode */ +#define US_CSR_LON_RXRDY_Pos _U_(0) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Position */ +#define US_CSR_LON_RXRDY_Msk (_U_(0x1) << US_CSR_LON_RXRDY_Pos) /**< (US_CSR) Receiver Ready (cleared by reading US_RHR) Mask */ +#define US_CSR_LON_RXRDY(value) (US_CSR_LON_RXRDY_Msk & ((value) << US_CSR_LON_RXRDY_Pos)) +#define US_CSR_LON_TXRDY_Pos _U_(1) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Position */ +#define US_CSR_LON_TXRDY_Msk (_U_(0x1) << US_CSR_LON_TXRDY_Pos) /**< (US_CSR) Transmitter Ready (cleared by writing US_THR) Mask */ +#define US_CSR_LON_TXRDY(value) (US_CSR_LON_TXRDY_Msk & ((value) << US_CSR_LON_TXRDY_Pos)) +#define US_CSR_LON_OVRE_Pos _U_(5) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Position */ +#define US_CSR_LON_OVRE_Msk (_U_(0x1) << US_CSR_LON_OVRE_Pos) /**< (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) Mask */ +#define US_CSR_LON_OVRE(value) (US_CSR_LON_OVRE_Msk & ((value) << US_CSR_LON_OVRE_Pos)) +#define US_CSR_LON_LSFE_Pos _U_(6) /**< (US_CSR) LON Short Frame Error Position */ +#define US_CSR_LON_LSFE_Msk (_U_(0x1) << US_CSR_LON_LSFE_Pos) /**< (US_CSR) LON Short Frame Error Mask */ +#define US_CSR_LON_LSFE(value) (US_CSR_LON_LSFE_Msk & ((value) << US_CSR_LON_LSFE_Pos)) +#define US_CSR_LON_LCRCE_Pos _U_(7) /**< (US_CSR) LON CRC Error Position */ +#define US_CSR_LON_LCRCE_Msk (_U_(0x1) << US_CSR_LON_LCRCE_Pos) /**< (US_CSR) LON CRC Error Mask */ +#define US_CSR_LON_LCRCE(value) (US_CSR_LON_LCRCE_Msk & ((value) << US_CSR_LON_LCRCE_Pos)) +#define US_CSR_LON_TXEMPTY_Pos _U_(9) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Position */ +#define US_CSR_LON_TXEMPTY_Msk (_U_(0x1) << US_CSR_LON_TXEMPTY_Pos) /**< (US_CSR) Transmitter Empty (cleared by writing US_THR) Mask */ +#define US_CSR_LON_TXEMPTY(value) (US_CSR_LON_TXEMPTY_Msk & ((value) << US_CSR_LON_TXEMPTY_Pos)) +#define US_CSR_LON_UNRE_Pos _U_(10) /**< (US_CSR) Underrun Error Position */ +#define US_CSR_LON_UNRE_Msk (_U_(0x1) << US_CSR_LON_UNRE_Pos) /**< (US_CSR) Underrun Error Mask */ +#define US_CSR_LON_UNRE(value) (US_CSR_LON_UNRE_Msk & ((value) << US_CSR_LON_UNRE_Pos)) +#define US_CSR_LON_LTXD_Pos _U_(24) /**< (US_CSR) LON Transmission End Flag Position */ +#define US_CSR_LON_LTXD_Msk (_U_(0x1) << US_CSR_LON_LTXD_Pos) /**< (US_CSR) LON Transmission End Flag Mask */ +#define US_CSR_LON_LTXD(value) (US_CSR_LON_LTXD_Msk & ((value) << US_CSR_LON_LTXD_Pos)) +#define US_CSR_LON_LCOL_Pos _U_(25) /**< (US_CSR) LON Collision Detected Flag Position */ +#define US_CSR_LON_LCOL_Msk (_U_(0x1) << US_CSR_LON_LCOL_Pos) /**< (US_CSR) LON Collision Detected Flag Mask */ +#define US_CSR_LON_LCOL(value) (US_CSR_LON_LCOL_Msk & ((value) << US_CSR_LON_LCOL_Pos)) +#define US_CSR_LON_LFET_Pos _U_(26) /**< (US_CSR) LON Frame Early Termination Position */ +#define US_CSR_LON_LFET_Msk (_U_(0x1) << US_CSR_LON_LFET_Pos) /**< (US_CSR) LON Frame Early Termination Mask */ +#define US_CSR_LON_LFET(value) (US_CSR_LON_LFET_Msk & ((value) << US_CSR_LON_LFET_Pos)) +#define US_CSR_LON_LRXD_Pos _U_(27) /**< (US_CSR) LON Reception End Flag Position */ +#define US_CSR_LON_LRXD_Msk (_U_(0x1) << US_CSR_LON_LRXD_Pos) /**< (US_CSR) LON Reception End Flag Mask */ +#define US_CSR_LON_LRXD(value) (US_CSR_LON_LRXD_Msk & ((value) << US_CSR_LON_LRXD_Pos)) +#define US_CSR_LON_LBLOVFE_Pos _U_(28) /**< (US_CSR) LON Backlog Overflow Error Position */ +#define US_CSR_LON_LBLOVFE_Msk (_U_(0x1) << US_CSR_LON_LBLOVFE_Pos) /**< (US_CSR) LON Backlog Overflow Error Mask */ +#define US_CSR_LON_LBLOVFE(value) (US_CSR_LON_LBLOVFE_Msk & ((value) << US_CSR_LON_LBLOVFE_Pos)) +#define US_CSR_LON_Msk _U_(0x1F0006E3) /**< (US_CSR_LON) Register Mask */ + + +/* -------- US_RHR : (USART Offset: 0x18) ( R/ 32) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos _U_(0) /**< (US_RHR) Received Character Position */ +#define US_RHR_RXCHR_Msk (_U_(0x1FF) << US_RHR_RXCHR_Pos) /**< (US_RHR) Received Character Mask */ +#define US_RHR_RXCHR(value) (US_RHR_RXCHR_Msk & ((value) << US_RHR_RXCHR_Pos)) +#define US_RHR_RXSYNH_Pos _U_(15) /**< (US_RHR) Received Sync Position */ +#define US_RHR_RXSYNH_Msk (_U_(0x1) << US_RHR_RXSYNH_Pos) /**< (US_RHR) Received Sync Mask */ +#define US_RHR_RXSYNH(value) (US_RHR_RXSYNH_Msk & ((value) << US_RHR_RXSYNH_Pos)) +#define US_RHR_Msk _U_(0x000081FF) /**< (US_RHR) Register Mask */ + + +/* -------- US_THR : (USART Offset: 0x1C) ( /W 32) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos _U_(0) /**< (US_THR) Character to be Transmitted Position */ +#define US_THR_TXCHR_Msk (_U_(0x1FF) << US_THR_TXCHR_Pos) /**< (US_THR) Character to be Transmitted Mask */ +#define US_THR_TXCHR(value) (US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)) +#define US_THR_TXSYNH_Pos _U_(15) /**< (US_THR) Sync Field to be Transmitted Position */ +#define US_THR_TXSYNH_Msk (_U_(0x1) << US_THR_TXSYNH_Pos) /**< (US_THR) Sync Field to be Transmitted Mask */ +#define US_THR_TXSYNH(value) (US_THR_TXSYNH_Msk & ((value) << US_THR_TXSYNH_Pos)) +#define US_THR_Msk _U_(0x000081FF) /**< (US_THR) Register Mask */ + + +/* -------- US_BRGR : (USART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos _U_(0) /**< (US_BRGR) Clock Divider Position */ +#define US_BRGR_CD_Msk (_U_(0xFFFF) << US_BRGR_CD_Pos) /**< (US_BRGR) Clock Divider Mask */ +#define US_BRGR_CD(value) (US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)) +#define US_BRGR_FP_Pos _U_(16) /**< (US_BRGR) Fractional Part Position */ +#define US_BRGR_FP_Msk (_U_(0x7) << US_BRGR_FP_Pos) /**< (US_BRGR) Fractional Part Mask */ +#define US_BRGR_FP(value) (US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)) +#define US_BRGR_Msk _U_(0x0007FFFF) /**< (US_BRGR) Register Mask */ + + +/* -------- US_RTOR : (USART Offset: 0x24) (R/W 32) Receiver Timeout Register -------- */ +#define US_RTOR_TO_Pos _U_(0) /**< (US_RTOR) Timeout Value Position */ +#define US_RTOR_TO_Msk (_U_(0x1FFFF) << US_RTOR_TO_Pos) /**< (US_RTOR) Timeout Value Mask */ +#define US_RTOR_TO(value) (US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)) +#define US_RTOR_Msk _U_(0x0001FFFF) /**< (US_RTOR) Register Mask */ + + +/* -------- US_TTGR : (USART Offset: 0x28) (R/W 32) Transmitter Timeguard Register -------- */ +#define US_TTGR_Msk _U_(0x00000000) /**< (US_TTGR) Register Mask */ + +/* USART mode */ +#define US_TTGR_USART_TG_Pos _U_(0) /**< (US_TTGR) Timeguard Value Position */ +#define US_TTGR_USART_TG_Msk (_U_(0xFF) << US_TTGR_USART_TG_Pos) /**< (US_TTGR) Timeguard Value Mask */ +#define US_TTGR_USART_TG(value) (US_TTGR_USART_TG_Msk & ((value) << US_TTGR_USART_TG_Pos)) +#define US_TTGR_USART_Msk _U_(0x000000FF) /**< (US_TTGR_USART) Register Mask */ + +/* LON mode */ +#define US_TTGR_LON_PCYCLE_Pos _U_(0) /**< (US_TTGR) LON PCYCLE Length Position */ +#define US_TTGR_LON_PCYCLE_Msk (_U_(0xFFFFFF) << US_TTGR_LON_PCYCLE_Pos) /**< (US_TTGR) LON PCYCLE Length Mask */ +#define US_TTGR_LON_PCYCLE(value) (US_TTGR_LON_PCYCLE_Msk & ((value) << US_TTGR_LON_PCYCLE_Pos)) +#define US_TTGR_LON_Msk _U_(0x00FFFFFF) /**< (US_TTGR_LON) Register Mask */ + + +/* -------- US_FIDI : (USART Offset: 0x40) (R/W 32) FI DI Ratio Register -------- */ +#define US_FIDI_Msk _U_(0x00000000) /**< (US_FIDI) Register Mask */ + +/* USART mode */ +#define US_FIDI_USART_FI_DI_RATIO_Pos _U_(0) /**< (US_FIDI) FI Over DI Ratio Value Position */ +#define US_FIDI_USART_FI_DI_RATIO_Msk (_U_(0xFFFF) << US_FIDI_USART_FI_DI_RATIO_Pos) /**< (US_FIDI) FI Over DI Ratio Value Mask */ +#define US_FIDI_USART_FI_DI_RATIO(value) (US_FIDI_USART_FI_DI_RATIO_Msk & ((value) << US_FIDI_USART_FI_DI_RATIO_Pos)) +#define US_FIDI_USART_Msk _U_(0x0000FFFF) /**< (US_FIDI_USART) Register Mask */ + +/* LON mode */ +#define US_FIDI_LON_BETA2_Pos _U_(0) /**< (US_FIDI) LON BETA2 Length Position */ +#define US_FIDI_LON_BETA2_Msk (_U_(0xFFFFFF) << US_FIDI_LON_BETA2_Pos) /**< (US_FIDI) LON BETA2 Length Mask */ +#define US_FIDI_LON_BETA2(value) (US_FIDI_LON_BETA2_Msk & ((value) << US_FIDI_LON_BETA2_Pos)) +#define US_FIDI_LON_Msk _U_(0x00FFFFFF) /**< (US_FIDI_LON) Register Mask */ + + +/* -------- US_NER : (USART Offset: 0x44) ( R/ 32) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos _U_(0) /**< (US_NER) Number of Errors Position */ +#define US_NER_NB_ERRORS_Msk (_U_(0xFF) << US_NER_NB_ERRORS_Pos) /**< (US_NER) Number of Errors Mask */ +#define US_NER_NB_ERRORS(value) (US_NER_NB_ERRORS_Msk & ((value) << US_NER_NB_ERRORS_Pos)) +#define US_NER_Msk _U_(0x000000FF) /**< (US_NER) Register Mask */ + + +/* -------- US_IF : (USART Offset: 0x4C) (R/W 32) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos _U_(0) /**< (US_IF) IrDA Filter Position */ +#define US_IF_IRDA_FILTER_Msk (_U_(0xFF) << US_IF_IRDA_FILTER_Pos) /**< (US_IF) IrDA Filter Mask */ +#define US_IF_IRDA_FILTER(value) (US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)) +#define US_IF_Msk _U_(0x000000FF) /**< (US_IF) Register Mask */ + + +/* -------- US_MAN : (USART Offset: 0x50) (R/W 32) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos _U_(0) /**< (US_MAN) Transmitter Preamble Length Position */ +#define US_MAN_TX_PL_Msk (_U_(0xF) << US_MAN_TX_PL_Pos) /**< (US_MAN) Transmitter Preamble Length Mask */ +#define US_MAN_TX_PL(value) (US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)) +#define US_MAN_TX_PP_Pos _U_(8) /**< (US_MAN) Transmitter Preamble Pattern Position */ +#define US_MAN_TX_PP_Msk (_U_(0x3) << US_MAN_TX_PP_Pos) /**< (US_MAN) Transmitter Preamble Pattern Mask */ +#define US_MAN_TX_PP(value) (US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)) +#define US_MAN_TX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_PP_ALL_ONE (US_MAN_TX_PP_ALL_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_TX_PP_ALL_ZERO (US_MAN_TX_PP_ALL_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_TX_PP_ZERO_ONE (US_MAN_TX_PP_ZERO_ONE_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_TX_PP_ONE_ZERO (US_MAN_TX_PP_ONE_ZERO_Val << US_MAN_TX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_TX_MPOL_Pos _U_(12) /**< (US_MAN) Transmitter Manchester Polarity Position */ +#define US_MAN_TX_MPOL_Msk (_U_(0x1) << US_MAN_TX_MPOL_Pos) /**< (US_MAN) Transmitter Manchester Polarity Mask */ +#define US_MAN_TX_MPOL(value) (US_MAN_TX_MPOL_Msk & ((value) << US_MAN_TX_MPOL_Pos)) +#define US_MAN_RX_PL_Pos _U_(16) /**< (US_MAN) Receiver Preamble Length Position */ +#define US_MAN_RX_PL_Msk (_U_(0xF) << US_MAN_RX_PL_Pos) /**< (US_MAN) Receiver Preamble Length Mask */ +#define US_MAN_RX_PL(value) (US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)) +#define US_MAN_RX_PP_Pos _U_(24) /**< (US_MAN) Receiver Preamble Pattern detected Position */ +#define US_MAN_RX_PP_Msk (_U_(0x3) << US_MAN_RX_PP_Pos) /**< (US_MAN) Receiver Preamble Pattern detected Mask */ +#define US_MAN_RX_PP(value) (US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)) +#define US_MAN_RX_PP_ALL_ONE_Val _U_(0x0) /**< (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO_Val _U_(0x1) /**< (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE_Val _U_(0x2) /**< (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO_Val _U_(0x3) /**< (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_PP_ALL_ONE (US_MAN_RX_PP_ALL_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '1's Position */ +#define US_MAN_RX_PP_ALL_ZERO (US_MAN_RX_PP_ALL_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '0's Position */ +#define US_MAN_RX_PP_ZERO_ONE (US_MAN_RX_PP_ZERO_ONE_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '01's Position */ +#define US_MAN_RX_PP_ONE_ZERO (US_MAN_RX_PP_ONE_ZERO_Val << US_MAN_RX_PP_Pos) /**< (US_MAN) The preamble is composed of '10's Position */ +#define US_MAN_RX_MPOL_Pos _U_(28) /**< (US_MAN) Receiver Manchester Polarity Position */ +#define US_MAN_RX_MPOL_Msk (_U_(0x1) << US_MAN_RX_MPOL_Pos) /**< (US_MAN) Receiver Manchester Polarity Mask */ +#define US_MAN_RX_MPOL(value) (US_MAN_RX_MPOL_Msk & ((value) << US_MAN_RX_MPOL_Pos)) +#define US_MAN_ONE_Pos _U_(29) /**< (US_MAN) Must Be Set to 1 Position */ +#define US_MAN_ONE_Msk (_U_(0x1) << US_MAN_ONE_Pos) /**< (US_MAN) Must Be Set to 1 Mask */ +#define US_MAN_ONE(value) (US_MAN_ONE_Msk & ((value) << US_MAN_ONE_Pos)) +#define US_MAN_DRIFT_Pos _U_(30) /**< (US_MAN) Drift Compensation Position */ +#define US_MAN_DRIFT_Msk (_U_(0x1) << US_MAN_DRIFT_Pos) /**< (US_MAN) Drift Compensation Mask */ +#define US_MAN_DRIFT(value) (US_MAN_DRIFT_Msk & ((value) << US_MAN_DRIFT_Pos)) +#define US_MAN_RXIDLEV_Pos _U_(31) /**< (US_MAN) Receiver Idle Value Position */ +#define US_MAN_RXIDLEV_Msk (_U_(0x1) << US_MAN_RXIDLEV_Pos) /**< (US_MAN) Receiver Idle Value Mask */ +#define US_MAN_RXIDLEV(value) (US_MAN_RXIDLEV_Msk & ((value) << US_MAN_RXIDLEV_Pos)) +#define US_MAN_Msk _U_(0xF30F130F) /**< (US_MAN) Register Mask */ + + +/* -------- US_LINMR : (USART Offset: 0x54) (R/W 32) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos _U_(0) /**< (US_LINMR) LIN Node Action Position */ +#define US_LINMR_NACT_Msk (_U_(0x3) << US_LINMR_NACT_Pos) /**< (US_LINMR) LIN Node Action Mask */ +#define US_LINMR_NACT(value) (US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)) +#define US_LINMR_NACT_PUBLISH_Val _U_(0x0) /**< (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE_Val _U_(0x1) /**< (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE_Val _U_(0x2) /**< (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_NACT_PUBLISH (US_LINMR_NACT_PUBLISH_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART transmits the response. Position */ +#define US_LINMR_NACT_SUBSCRIBE (US_LINMR_NACT_SUBSCRIBE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART receives the response. Position */ +#define US_LINMR_NACT_IGNORE (US_LINMR_NACT_IGNORE_Val << US_LINMR_NACT_Pos) /**< (US_LINMR) The USART does not transmit and does not receive the response. Position */ +#define US_LINMR_PARDIS_Pos _U_(2) /**< (US_LINMR) Parity Disable Position */ +#define US_LINMR_PARDIS_Msk (_U_(0x1) << US_LINMR_PARDIS_Pos) /**< (US_LINMR) Parity Disable Mask */ +#define US_LINMR_PARDIS(value) (US_LINMR_PARDIS_Msk & ((value) << US_LINMR_PARDIS_Pos)) +#define US_LINMR_CHKDIS_Pos _U_(3) /**< (US_LINMR) Checksum Disable Position */ +#define US_LINMR_CHKDIS_Msk (_U_(0x1) << US_LINMR_CHKDIS_Pos) /**< (US_LINMR) Checksum Disable Mask */ +#define US_LINMR_CHKDIS(value) (US_LINMR_CHKDIS_Msk & ((value) << US_LINMR_CHKDIS_Pos)) +#define US_LINMR_CHKTYP_Pos _U_(4) /**< (US_LINMR) Checksum Type Position */ +#define US_LINMR_CHKTYP_Msk (_U_(0x1) << US_LINMR_CHKTYP_Pos) /**< (US_LINMR) Checksum Type Mask */ +#define US_LINMR_CHKTYP(value) (US_LINMR_CHKTYP_Msk & ((value) << US_LINMR_CHKTYP_Pos)) +#define US_LINMR_DLM_Pos _U_(5) /**< (US_LINMR) Data Length Mode Position */ +#define US_LINMR_DLM_Msk (_U_(0x1) << US_LINMR_DLM_Pos) /**< (US_LINMR) Data Length Mode Mask */ +#define US_LINMR_DLM(value) (US_LINMR_DLM_Msk & ((value) << US_LINMR_DLM_Pos)) +#define US_LINMR_FSDIS_Pos _U_(6) /**< (US_LINMR) Frame Slot Mode Disable Position */ +#define US_LINMR_FSDIS_Msk (_U_(0x1) << US_LINMR_FSDIS_Pos) /**< (US_LINMR) Frame Slot Mode Disable Mask */ +#define US_LINMR_FSDIS(value) (US_LINMR_FSDIS_Msk & ((value) << US_LINMR_FSDIS_Pos)) +#define US_LINMR_WKUPTYP_Pos _U_(7) /**< (US_LINMR) Wakeup Signal Type Position */ +#define US_LINMR_WKUPTYP_Msk (_U_(0x1) << US_LINMR_WKUPTYP_Pos) /**< (US_LINMR) Wakeup Signal Type Mask */ +#define US_LINMR_WKUPTYP(value) (US_LINMR_WKUPTYP_Msk & ((value) << US_LINMR_WKUPTYP_Pos)) +#define US_LINMR_DLC_Pos _U_(8) /**< (US_LINMR) Data Length Control Position */ +#define US_LINMR_DLC_Msk (_U_(0xFF) << US_LINMR_DLC_Pos) /**< (US_LINMR) Data Length Control Mask */ +#define US_LINMR_DLC(value) (US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)) +#define US_LINMR_PDCM_Pos _U_(16) /**< (US_LINMR) DMAC Mode Position */ +#define US_LINMR_PDCM_Msk (_U_(0x1) << US_LINMR_PDCM_Pos) /**< (US_LINMR) DMAC Mode Mask */ +#define US_LINMR_PDCM(value) (US_LINMR_PDCM_Msk & ((value) << US_LINMR_PDCM_Pos)) +#define US_LINMR_SYNCDIS_Pos _U_(17) /**< (US_LINMR) Synchronization Disable Position */ +#define US_LINMR_SYNCDIS_Msk (_U_(0x1) << US_LINMR_SYNCDIS_Pos) /**< (US_LINMR) Synchronization Disable Mask */ +#define US_LINMR_SYNCDIS(value) (US_LINMR_SYNCDIS_Msk & ((value) << US_LINMR_SYNCDIS_Pos)) +#define US_LINMR_Msk _U_(0x0003FFFF) /**< (US_LINMR) Register Mask */ + + +/* -------- US_LINIR : (USART Offset: 0x58) (R/W 32) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos _U_(0) /**< (US_LINIR) Identifier Character Position */ +#define US_LINIR_IDCHR_Msk (_U_(0xFF) << US_LINIR_IDCHR_Pos) /**< (US_LINIR) Identifier Character Mask */ +#define US_LINIR_IDCHR(value) (US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)) +#define US_LINIR_Msk _U_(0x000000FF) /**< (US_LINIR) Register Mask */ + + +/* -------- US_LINBRR : (USART Offset: 0x5C) ( R/ 32) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos _U_(0) /**< (US_LINBRR) Clock Divider after Synchronization Position */ +#define US_LINBRR_LINCD_Msk (_U_(0xFFFF) << US_LINBRR_LINCD_Pos) /**< (US_LINBRR) Clock Divider after Synchronization Mask */ +#define US_LINBRR_LINCD(value) (US_LINBRR_LINCD_Msk & ((value) << US_LINBRR_LINCD_Pos)) +#define US_LINBRR_LINFP_Pos _U_(16) /**< (US_LINBRR) Fractional Part after Synchronization Position */ +#define US_LINBRR_LINFP_Msk (_U_(0x7) << US_LINBRR_LINFP_Pos) /**< (US_LINBRR) Fractional Part after Synchronization Mask */ +#define US_LINBRR_LINFP(value) (US_LINBRR_LINFP_Msk & ((value) << US_LINBRR_LINFP_Pos)) +#define US_LINBRR_Msk _U_(0x0007FFFF) /**< (US_LINBRR) Register Mask */ + + +/* -------- US_LONMR : (USART Offset: 0x60) (R/W 32) LON Mode Register -------- */ +#define US_LONMR_COMMT_Pos _U_(0) /**< (US_LONMR) LON comm_type Parameter Value Position */ +#define US_LONMR_COMMT_Msk (_U_(0x1) << US_LONMR_COMMT_Pos) /**< (US_LONMR) LON comm_type Parameter Value Mask */ +#define US_LONMR_COMMT(value) (US_LONMR_COMMT_Msk & ((value) << US_LONMR_COMMT_Pos)) +#define US_LONMR_COLDET_Pos _U_(1) /**< (US_LONMR) LON Collision Detection Feature Position */ +#define US_LONMR_COLDET_Msk (_U_(0x1) << US_LONMR_COLDET_Pos) /**< (US_LONMR) LON Collision Detection Feature Mask */ +#define US_LONMR_COLDET(value) (US_LONMR_COLDET_Msk & ((value) << US_LONMR_COLDET_Pos)) +#define US_LONMR_TCOL_Pos _U_(2) /**< (US_LONMR) Terminate Frame upon Collision Notification Position */ +#define US_LONMR_TCOL_Msk (_U_(0x1) << US_LONMR_TCOL_Pos) /**< (US_LONMR) Terminate Frame upon Collision Notification Mask */ +#define US_LONMR_TCOL(value) (US_LONMR_TCOL_Msk & ((value) << US_LONMR_TCOL_Pos)) +#define US_LONMR_CDTAIL_Pos _U_(3) /**< (US_LONMR) LON Collision Detection on Frame Tail Position */ +#define US_LONMR_CDTAIL_Msk (_U_(0x1) << US_LONMR_CDTAIL_Pos) /**< (US_LONMR) LON Collision Detection on Frame Tail Mask */ +#define US_LONMR_CDTAIL(value) (US_LONMR_CDTAIL_Msk & ((value) << US_LONMR_CDTAIL_Pos)) +#define US_LONMR_DMAM_Pos _U_(4) /**< (US_LONMR) LON DMA Mode Position */ +#define US_LONMR_DMAM_Msk (_U_(0x1) << US_LONMR_DMAM_Pos) /**< (US_LONMR) LON DMA Mode Mask */ +#define US_LONMR_DMAM(value) (US_LONMR_DMAM_Msk & ((value) << US_LONMR_DMAM_Pos)) +#define US_LONMR_LCDS_Pos _U_(5) /**< (US_LONMR) LON Collision Detection Source Position */ +#define US_LONMR_LCDS_Msk (_U_(0x1) << US_LONMR_LCDS_Pos) /**< (US_LONMR) LON Collision Detection Source Mask */ +#define US_LONMR_LCDS(value) (US_LONMR_LCDS_Msk & ((value) << US_LONMR_LCDS_Pos)) +#define US_LONMR_EOFS_Pos _U_(16) /**< (US_LONMR) End of Frame Condition Size Position */ +#define US_LONMR_EOFS_Msk (_U_(0xFF) << US_LONMR_EOFS_Pos) /**< (US_LONMR) End of Frame Condition Size Mask */ +#define US_LONMR_EOFS(value) (US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)) +#define US_LONMR_Msk _U_(0x00FF003F) /**< (US_LONMR) Register Mask */ + + +/* -------- US_LONPR : (USART Offset: 0x64) (R/W 32) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos _U_(0) /**< (US_LONPR) LON Preamble Length Position */ +#define US_LONPR_LONPL_Msk (_U_(0x3FFF) << US_LONPR_LONPL_Pos) /**< (US_LONPR) LON Preamble Length Mask */ +#define US_LONPR_LONPL(value) (US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)) +#define US_LONPR_Msk _U_(0x00003FFF) /**< (US_LONPR) Register Mask */ + + +/* -------- US_LONDL : (USART Offset: 0x68) (R/W 32) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos _U_(0) /**< (US_LONDL) LON Data Length Position */ +#define US_LONDL_LONDL_Msk (_U_(0xFF) << US_LONDL_LONDL_Pos) /**< (US_LONDL) LON Data Length Mask */ +#define US_LONDL_LONDL(value) (US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)) +#define US_LONDL_Msk _U_(0x000000FF) /**< (US_LONDL) Register Mask */ + + +/* -------- US_LONL2HDR : (USART Offset: 0x6C) (R/W 32) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos _U_(0) /**< (US_LONL2HDR) LON Backlog Increment Position */ +#define US_LONL2HDR_BLI_Msk (_U_(0x3F) << US_LONL2HDR_BLI_Pos) /**< (US_LONL2HDR) LON Backlog Increment Mask */ +#define US_LONL2HDR_BLI(value) (US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)) +#define US_LONL2HDR_ALTP_Pos _U_(6) /**< (US_LONL2HDR) LON Alternate Path Bit Position */ +#define US_LONL2HDR_ALTP_Msk (_U_(0x1) << US_LONL2HDR_ALTP_Pos) /**< (US_LONL2HDR) LON Alternate Path Bit Mask */ +#define US_LONL2HDR_ALTP(value) (US_LONL2HDR_ALTP_Msk & ((value) << US_LONL2HDR_ALTP_Pos)) +#define US_LONL2HDR_PB_Pos _U_(7) /**< (US_LONL2HDR) LON Priority Bit Position */ +#define US_LONL2HDR_PB_Msk (_U_(0x1) << US_LONL2HDR_PB_Pos) /**< (US_LONL2HDR) LON Priority Bit Mask */ +#define US_LONL2HDR_PB(value) (US_LONL2HDR_PB_Msk & ((value) << US_LONL2HDR_PB_Pos)) +#define US_LONL2HDR_Msk _U_(0x000000FF) /**< (US_LONL2HDR) Register Mask */ + + +/* -------- US_LONBL : (USART Offset: 0x70) ( R/ 32) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos _U_(0) /**< (US_LONBL) LON Node Backlog Value Position */ +#define US_LONBL_LONBL_Msk (_U_(0x3F) << US_LONBL_LONBL_Pos) /**< (US_LONBL) LON Node Backlog Value Mask */ +#define US_LONBL_LONBL(value) (US_LONBL_LONBL_Msk & ((value) << US_LONBL_LONBL_Pos)) +#define US_LONBL_Msk _U_(0x0000003F) /**< (US_LONBL) Register Mask */ + + +/* -------- US_LONB1TX : (USART Offset: 0x74) (R/W 32) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos _U_(0) /**< (US_LONB1TX) LON Beta1 Length after Transmission Position */ +#define US_LONB1TX_BETA1TX_Msk (_U_(0xFFFFFF) << US_LONB1TX_BETA1TX_Pos) /**< (US_LONB1TX) LON Beta1 Length after Transmission Mask */ +#define US_LONB1TX_BETA1TX(value) (US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)) +#define US_LONB1TX_Msk _U_(0x00FFFFFF) /**< (US_LONB1TX) Register Mask */ + + +/* -------- US_LONB1RX : (USART Offset: 0x78) (R/W 32) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos _U_(0) /**< (US_LONB1RX) LON Beta1 Length after Reception Position */ +#define US_LONB1RX_BETA1RX_Msk (_U_(0xFFFFFF) << US_LONB1RX_BETA1RX_Pos) /**< (US_LONB1RX) LON Beta1 Length after Reception Mask */ +#define US_LONB1RX_BETA1RX(value) (US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)) +#define US_LONB1RX_Msk _U_(0x00FFFFFF) /**< (US_LONB1RX) Register Mask */ + + +/* -------- US_LONPRIO : (USART Offset: 0x7C) (R/W 32) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos _U_(0) /**< (US_LONPRIO) LON Priority Slot Number Position */ +#define US_LONPRIO_PSNB_Msk (_U_(0x7F) << US_LONPRIO_PSNB_Pos) /**< (US_LONPRIO) LON Priority Slot Number Mask */ +#define US_LONPRIO_PSNB(value) (US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)) +#define US_LONPRIO_NPS_Pos _U_(8) /**< (US_LONPRIO) LON Node Priority Slot Position */ +#define US_LONPRIO_NPS_Msk (_U_(0x7F) << US_LONPRIO_NPS_Pos) /**< (US_LONPRIO) LON Node Priority Slot Mask */ +#define US_LONPRIO_NPS(value) (US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)) +#define US_LONPRIO_Msk _U_(0x00007F7F) /**< (US_LONPRIO) Register Mask */ + + +/* -------- US_IDTTX : (USART Offset: 0x80) (R/W 32) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos _U_(0) /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Position */ +#define US_IDTTX_IDTTX_Msk (_U_(0xFFFFFF) << US_IDTTX_IDTTX_Pos) /**< (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) Mask */ +#define US_IDTTX_IDTTX(value) (US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)) +#define US_IDTTX_Msk _U_(0x00FFFFFF) /**< (US_IDTTX) Register Mask */ + + +/* -------- US_IDTRX : (USART Offset: 0x84) (R/W 32) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos _U_(0) /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Position */ +#define US_IDTRX_IDTRX_Msk (_U_(0xFFFFFF) << US_IDTRX_IDTRX_Pos) /**< (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) Mask */ +#define US_IDTRX_IDTRX(value) (US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)) +#define US_IDTRX_Msk _U_(0x00FFFFFF) /**< (US_IDTRX) Register Mask */ + + +/* -------- US_ICDIFF : (USART Offset: 0x88) (R/W 32) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos _U_(0) /**< (US_ICDIFF) IC Differentiator Number Position */ +#define US_ICDIFF_ICDIFF_Msk (_U_(0xF) << US_ICDIFF_ICDIFF_Pos) /**< (US_ICDIFF) IC Differentiator Number Mask */ +#define US_ICDIFF_ICDIFF(value) (US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)) +#define US_ICDIFF_Msk _U_(0x0000000F) /**< (US_ICDIFF) Register Mask */ + + +/* -------- US_WPMR : (USART Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN_Pos _U_(0) /**< (US_WPMR) Write Protection Enable Position */ +#define US_WPMR_WPEN_Msk (_U_(0x1) << US_WPMR_WPEN_Pos) /**< (US_WPMR) Write Protection Enable Mask */ +#define US_WPMR_WPEN(value) (US_WPMR_WPEN_Msk & ((value) << US_WPMR_WPEN_Pos)) +#define US_WPMR_WPKEY_Pos _U_(8) /**< (US_WPMR) Write Protection Key Position */ +#define US_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Write Protection Key Mask */ +#define US_WPMR_WPKEY(value) (US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)) +#define US_WPMR_WPKEY_PASSWD_Val _U_(0x555341) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +#define US_WPMR_WPKEY_PASSWD (US_WPMR_WPKEY_PASSWD_Val << US_WPMR_WPKEY_Pos) /**< (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ +#define US_WPMR_Msk _U_(0xFFFFFF01) /**< (US_WPMR) Register Mask */ + + +/* -------- US_WPSR : (USART Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */ +#define US_WPSR_WPVS_Pos _U_(0) /**< (US_WPSR) Write Protection Violation Status Position */ +#define US_WPSR_WPVS_Msk (_U_(0x1) << US_WPSR_WPVS_Pos) /**< (US_WPSR) Write Protection Violation Status Mask */ +#define US_WPSR_WPVS(value) (US_WPSR_WPVS_Msk & ((value) << US_WPSR_WPVS_Pos)) +#define US_WPSR_WPVSRC_Pos _U_(8) /**< (US_WPSR) Write Protection Violation Source Position */ +#define US_WPSR_WPVSRC_Msk (_U_(0xFFFF) << US_WPSR_WPVSRC_Pos) /**< (US_WPSR) Write Protection Violation Source Mask */ +#define US_WPSR_WPVSRC(value) (US_WPSR_WPVSRC_Msk & ((value) << US_WPSR_WPVSRC_Pos)) +#define US_WPSR_Msk _U_(0x00FFFF01) /**< (US_WPSR) Register Mask */ + + +/** \brief USART register offsets definitions */ +#define US_CR_REG_OFST (0x00) /**< (US_CR) Control Register Offset */ +#define US_MR_REG_OFST (0x04) /**< (US_MR) Mode Register Offset */ +#define US_IER_REG_OFST (0x08) /**< (US_IER) Interrupt Enable Register Offset */ +#define US_IDR_REG_OFST (0x0C) /**< (US_IDR) Interrupt Disable Register Offset */ +#define US_IMR_REG_OFST (0x10) /**< (US_IMR) Interrupt Mask Register Offset */ +#define US_CSR_REG_OFST (0x14) /**< (US_CSR) Channel Status Register Offset */ +#define US_RHR_REG_OFST (0x18) /**< (US_RHR) Receive Holding Register Offset */ +#define US_THR_REG_OFST (0x1C) /**< (US_THR) Transmit Holding Register Offset */ +#define US_BRGR_REG_OFST (0x20) /**< (US_BRGR) Baud Rate Generator Register Offset */ +#define US_RTOR_REG_OFST (0x24) /**< (US_RTOR) Receiver Timeout Register Offset */ +#define US_TTGR_REG_OFST (0x28) /**< (US_TTGR) Transmitter Timeguard Register Offset */ +#define US_FIDI_REG_OFST (0x40) /**< (US_FIDI) FI DI Ratio Register Offset */ +#define US_NER_REG_OFST (0x44) /**< (US_NER) Number of Errors Register Offset */ +#define US_IF_REG_OFST (0x4C) /**< (US_IF) IrDA Filter Register Offset */ +#define US_MAN_REG_OFST (0x50) /**< (US_MAN) Manchester Configuration Register Offset */ +#define US_LINMR_REG_OFST (0x54) /**< (US_LINMR) LIN Mode Register Offset */ +#define US_LINIR_REG_OFST (0x58) /**< (US_LINIR) LIN Identifier Register Offset */ +#define US_LINBRR_REG_OFST (0x5C) /**< (US_LINBRR) LIN Baud Rate Register Offset */ +#define US_LONMR_REG_OFST (0x60) /**< (US_LONMR) LON Mode Register Offset */ +#define US_LONPR_REG_OFST (0x64) /**< (US_LONPR) LON Preamble Register Offset */ +#define US_LONDL_REG_OFST (0x68) /**< (US_LONDL) LON Data Length Register Offset */ +#define US_LONL2HDR_REG_OFST (0x6C) /**< (US_LONL2HDR) LON L2HDR Register Offset */ +#define US_LONBL_REG_OFST (0x70) /**< (US_LONBL) LON Backlog Register Offset */ +#define US_LONB1TX_REG_OFST (0x74) /**< (US_LONB1TX) LON Beta1 Tx Register Offset */ +#define US_LONB1RX_REG_OFST (0x78) /**< (US_LONB1RX) LON Beta1 Rx Register Offset */ +#define US_LONPRIO_REG_OFST (0x7C) /**< (US_LONPRIO) LON Priority Register Offset */ +#define US_IDTTX_REG_OFST (0x80) /**< (US_IDTTX) LON IDT Tx Register Offset */ +#define US_IDTRX_REG_OFST (0x84) /**< (US_IDTRX) LON IDT Rx Register Offset */ +#define US_ICDIFF_REG_OFST (0x88) /**< (US_ICDIFF) IC DIFF Register Offset */ +#define US_WPMR_REG_OFST (0xE4) /**< (US_WPMR) Write Protection Mode Register Offset */ +#define US_WPSR_REG_OFST (0xE8) /**< (US_WPSR) Write Protection Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief USART register API structure */ +typedef struct +{ + __O uint32_t US_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t US_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __O uint32_t US_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< Offset: 0x14 (R/ 32) Channel Status Register */ + __I uint32_t US_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ + __O uint32_t US_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< Offset: 0x24 (R/W 32) Receiver Timeout Register */ + __IO uint32_t US_TTGR; /**< Offset: 0x28 (R/W 32) Transmitter Timeguard Register */ + __I uint8_t Reserved1[0x14]; + __IO uint32_t US_FIDI; /**< Offset: 0x40 (R/W 32) FI DI Ratio Register */ + __I uint32_t US_NER; /**< Offset: 0x44 (R/ 32) Number of Errors Register */ + __I uint8_t Reserved2[0x04]; + __IO uint32_t US_IF; /**< Offset: 0x4C (R/W 32) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< Offset: 0x50 (R/W 32) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< Offset: 0x54 (R/W 32) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< Offset: 0x58 (R/W 32) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< Offset: 0x5C (R/ 32) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< Offset: 0x60 (R/W 32) LON Mode Register */ + __IO uint32_t US_LONPR; /**< Offset: 0x64 (R/W 32) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< Offset: 0x68 (R/W 32) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< Offset: 0x6C (R/W 32) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< Offset: 0x70 (R/ 32) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< Offset: 0x74 (R/W 32) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< Offset: 0x78 (R/W 32) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< Offset: 0x7C (R/W 32) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< Offset: 0x80 (R/W 32) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< Offset: 0x84 (R/W 32) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< Offset: 0x88 (R/W 32) IC DIFF Register */ + __I uint8_t Reserved3[0x58]; + __IO uint32_t US_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ +} usart_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_USART_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/usbhs.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/usbhs.h new file mode 100644 index 00000000..71404122 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/usbhs.h @@ -0,0 +1,2672 @@ +/** + * \brief Component description for USBHS + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_USBHS_COMPONENT_H_ +#define _SAME70_USBHS_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR USBHS */ +/* ************************************************************************** */ + +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos _U_(0) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) (USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMANXTDSC) Register Mask */ + + +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos _U_(0) /**< (USBHS_DEVDMAADDRESS) Buffer Address Position */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_DEVDMAADDRESS) Buffer Address Mask */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) (USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMAADDRESS) Register Mask */ + + +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB_Pos _U_(0) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Position */ +#define USBHS_DEVDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Mask */ +#define USBHS_DEVDMACONTROL_CHANN_ENB(value) (USBHS_DEVDMACONTROL_CHANN_ENB_Msk & ((value) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos)) +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Pos _U_(1) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC(value) (USBHS_DEVDMACONTROL_LDNXT_DSC_Msk & ((value) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos)) +#define USBHS_DEVDMACONTROL_END_TR_EN_Pos _U_(2) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_DEVDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_DEVDMACONTROL_END_TR_EN(value) (USBHS_DEVDMACONTROL_END_TR_EN_Msk & ((value) << USBHS_DEVDMACONTROL_END_TR_EN_Pos)) +#define USBHS_DEVDMACONTROL_END_B_EN_Pos _U_(3) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_DEVDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_B_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_DEVDMACONTROL_END_B_EN(value) (USBHS_DEVDMACONTROL_END_B_EN_Msk & ((value) << USBHS_DEVDMACONTROL_END_B_EN_Pos)) +#define USBHS_DEVDMACONTROL_END_TR_IT_Pos _U_(4) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_IT_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_TR_IT(value) (USBHS_DEVDMACONTROL_END_TR_IT_Msk & ((value) << USBHS_DEVDMACONTROL_END_TR_IT_Pos)) +#define USBHS_DEVDMACONTROL_END_BUFFIT_Pos _U_(5) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_END_BUFFIT(value) (USBHS_DEVDMACONTROL_END_BUFFIT_Msk & ((value) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos)) +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Pos _U_(6) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT(value) (USBHS_DEVDMACONTROL_DESC_LD_IT_Msk & ((value) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos)) +#define USBHS_DEVDMACONTROL_BURST_LCK_Pos _U_(7) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Position */ +#define USBHS_DEVDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_BURST_LCK_Pos) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_DEVDMACONTROL_BURST_LCK(value) (USBHS_DEVDMACONTROL_BURST_LCK_Msk & ((value) << USBHS_DEVDMACONTROL_BURST_LCK_Pos)) +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos _U_(16) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) (USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_DEVDMACONTROL) Register Mask */ + + +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: 0x0C) (R/W 32) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB_Pos _U_(0) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ENB(value) (USBHS_DEVDMASTATUS_CHANN_ENB_Msk & ((value) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos)) +#define USBHS_DEVDMASTATUS_CHANN_ACT_Pos _U_(1) /**< (USBHS_DEVDMASTATUS) Channel Active Status Position */ +#define USBHS_DEVDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_DEVDMASTATUS) Channel Active Status Mask */ +#define USBHS_DEVDMASTATUS_CHANN_ACT(value) (USBHS_DEVDMASTATUS_CHANN_ACT_Msk & ((value) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos)) +#define USBHS_DEVDMASTATUS_END_TR_ST_Pos _U_(4) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_DEVDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_TR_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_DEVDMASTATUS_END_TR_ST(value) (USBHS_DEVDMASTATUS_END_TR_ST_Msk & ((value) << USBHS_DEVDMASTATUS_END_TR_ST_Pos)) +#define USBHS_DEVDMASTATUS_END_BF_ST_Pos _U_(5) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_DEVDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_BF_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_DEVDMASTATUS_END_BF_ST(value) (USBHS_DEVDMASTATUS_END_BF_ST_Msk & ((value) << USBHS_DEVDMASTATUS_END_BF_ST_Pos)) +#define USBHS_DEVDMASTATUS_DESC_LDST_Pos _U_(6) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_DEVDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_DESC_LDST_Pos) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_DEVDMASTATUS_DESC_LDST(value) (USBHS_DEVDMASTATUS_DESC_LDST_Msk & ((value) << USBHS_DEVDMASTATUS_DESC_LDST_Pos)) +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos _U_(16) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Position */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) (USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_DEVDMASTATUS) Register Mask */ + + +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos _U_(0) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Position */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Mask */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) (USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)) +#define USBHS_HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMANXTDSC) Register Mask */ + + +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos _U_(0) /**< (USBHS_HSTDMAADDRESS) Buffer Address Position */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_HSTDMAADDRESS) Buffer Address Mask */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) (USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)) +#define USBHS_HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMAADDRESS) Register Mask */ + + +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB_Pos _U_(0) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Position */ +#define USBHS_HSTDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Mask */ +#define USBHS_HSTDMACONTROL_CHANN_ENB(value) (USBHS_HSTDMACONTROL_CHANN_ENB_Msk & ((value) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos)) +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Pos _U_(1) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC(value) (USBHS_HSTDMACONTROL_LDNXT_DSC_Msk & ((value) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos)) +#define USBHS_HSTDMACONTROL_END_TR_EN_Pos _U_(2) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ +#define USBHS_HSTDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ +#define USBHS_HSTDMACONTROL_END_TR_EN(value) (USBHS_HSTDMACONTROL_END_TR_EN_Msk & ((value) << USBHS_HSTDMACONTROL_END_TR_EN_Pos)) +#define USBHS_HSTDMACONTROL_END_B_EN_Pos _U_(3) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Position */ +#define USBHS_HSTDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_B_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Mask */ +#define USBHS_HSTDMACONTROL_END_B_EN(value) (USBHS_HSTDMACONTROL_END_B_EN_Msk & ((value) << USBHS_HSTDMACONTROL_END_B_EN_Pos)) +#define USBHS_HSTDMACONTROL_END_TR_IT_Pos _U_(4) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_IT_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_TR_IT(value) (USBHS_HSTDMACONTROL_END_TR_IT_Msk & ((value) << USBHS_HSTDMACONTROL_END_TR_IT_Pos)) +#define USBHS_HSTDMACONTROL_END_BUFFIT_Pos _U_(5) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_END_BUFFIT(value) (USBHS_HSTDMACONTROL_END_BUFFIT_Msk & ((value) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos)) +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Pos _U_(6) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT(value) (USBHS_HSTDMACONTROL_DESC_LD_IT_Msk & ((value) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos)) +#define USBHS_HSTDMACONTROL_BURST_LCK_Pos _U_(7) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Position */ +#define USBHS_HSTDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_BURST_LCK_Pos) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Mask */ +#define USBHS_HSTDMACONTROL_BURST_LCK(value) (USBHS_HSTDMACONTROL_BURST_LCK_Msk & ((value) << USBHS_HSTDMACONTROL_BURST_LCK_Pos)) +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos _U_(16) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) (USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)) +#define USBHS_HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_HSTDMACONTROL) Register Mask */ + + +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: 0x0C) (R/W 32) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB_Pos _U_(0) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ENB(value) (USBHS_HSTDMASTATUS_CHANN_ENB_Msk & ((value) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos)) +#define USBHS_HSTDMASTATUS_CHANN_ACT_Pos _U_(1) /**< (USBHS_HSTDMASTATUS) Channel Active Status Position */ +#define USBHS_HSTDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_HSTDMASTATUS) Channel Active Status Mask */ +#define USBHS_HSTDMASTATUS_CHANN_ACT(value) (USBHS_HSTDMASTATUS_CHANN_ACT_Msk & ((value) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos)) +#define USBHS_HSTDMASTATUS_END_TR_ST_Pos _U_(4) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Position */ +#define USBHS_HSTDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_TR_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Mask */ +#define USBHS_HSTDMASTATUS_END_TR_ST(value) (USBHS_HSTDMASTATUS_END_TR_ST_Msk & ((value) << USBHS_HSTDMASTATUS_END_TR_ST_Pos)) +#define USBHS_HSTDMASTATUS_END_BF_ST_Pos _U_(5) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Position */ +#define USBHS_HSTDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_BF_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Mask */ +#define USBHS_HSTDMASTATUS_END_BF_ST(value) (USBHS_HSTDMASTATUS_END_BF_ST_Msk & ((value) << USBHS_HSTDMASTATUS_END_BF_ST_Pos)) +#define USBHS_HSTDMASTATUS_DESC_LDST_Pos _U_(6) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Position */ +#define USBHS_HSTDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_DESC_LDST_Pos) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Mask */ +#define USBHS_HSTDMASTATUS_DESC_LDST(value) (USBHS_HSTDMASTATUS_DESC_LDST_Msk & ((value) << USBHS_HSTDMASTATUS_DESC_LDST_Pos)) +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos _U_(16) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Position */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Mask */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) (USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)) +#define USBHS_HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_HSTDMASTATUS) Register Mask */ + + +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos _U_(0) /**< (USBHS_DEVCTRL) USB Address Position */ +#define USBHS_DEVCTRL_UADD_Msk (_U_(0x7F) << USBHS_DEVCTRL_UADD_Pos) /**< (USBHS_DEVCTRL) USB Address Mask */ +#define USBHS_DEVCTRL_UADD(value) (USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)) +#define USBHS_DEVCTRL_ADDEN_Pos _U_(7) /**< (USBHS_DEVCTRL) Address Enable Position */ +#define USBHS_DEVCTRL_ADDEN_Msk (_U_(0x1) << USBHS_DEVCTRL_ADDEN_Pos) /**< (USBHS_DEVCTRL) Address Enable Mask */ +#define USBHS_DEVCTRL_ADDEN(value) (USBHS_DEVCTRL_ADDEN_Msk & ((value) << USBHS_DEVCTRL_ADDEN_Pos)) +#define USBHS_DEVCTRL_DETACH_Pos _U_(8) /**< (USBHS_DEVCTRL) Detach Position */ +#define USBHS_DEVCTRL_DETACH_Msk (_U_(0x1) << USBHS_DEVCTRL_DETACH_Pos) /**< (USBHS_DEVCTRL) Detach Mask */ +#define USBHS_DEVCTRL_DETACH(value) (USBHS_DEVCTRL_DETACH_Msk & ((value) << USBHS_DEVCTRL_DETACH_Pos)) +#define USBHS_DEVCTRL_RMWKUP_Pos _U_(9) /**< (USBHS_DEVCTRL) Remote Wake-Up Position */ +#define USBHS_DEVCTRL_RMWKUP_Msk (_U_(0x1) << USBHS_DEVCTRL_RMWKUP_Pos) /**< (USBHS_DEVCTRL) Remote Wake-Up Mask */ +#define USBHS_DEVCTRL_RMWKUP(value) (USBHS_DEVCTRL_RMWKUP_Msk & ((value) << USBHS_DEVCTRL_RMWKUP_Pos)) +#define USBHS_DEVCTRL_SPDCONF_Pos _U_(10) /**< (USBHS_DEVCTRL) Mode Configuration Position */ +#define USBHS_DEVCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Mode Configuration Mask */ +#define USBHS_DEVCTRL_SPDCONF(value) (USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)) +#define USBHS_DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_SPDCONF_NORMAL (USBHS_DEVCTRL_SPDCONF_NORMAL_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Forced high speed. Position */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ +#define USBHS_DEVCTRL_LS_Pos _U_(12) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Position */ +#define USBHS_DEVCTRL_LS_Msk (_U_(0x1) << USBHS_DEVCTRL_LS_Pos) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Mask */ +#define USBHS_DEVCTRL_LS(value) (USBHS_DEVCTRL_LS_Msk & ((value) << USBHS_DEVCTRL_LS_Pos)) +#define USBHS_DEVCTRL_TSTJ_Pos _U_(13) /**< (USBHS_DEVCTRL) Test mode J Position */ +#define USBHS_DEVCTRL_TSTJ_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTJ_Pos) /**< (USBHS_DEVCTRL) Test mode J Mask */ +#define USBHS_DEVCTRL_TSTJ(value) (USBHS_DEVCTRL_TSTJ_Msk & ((value) << USBHS_DEVCTRL_TSTJ_Pos)) +#define USBHS_DEVCTRL_TSTK_Pos _U_(14) /**< (USBHS_DEVCTRL) Test mode K Position */ +#define USBHS_DEVCTRL_TSTK_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTK_Pos) /**< (USBHS_DEVCTRL) Test mode K Mask */ +#define USBHS_DEVCTRL_TSTK(value) (USBHS_DEVCTRL_TSTK_Msk & ((value) << USBHS_DEVCTRL_TSTK_Pos)) +#define USBHS_DEVCTRL_TSTPCKT_Pos _U_(15) /**< (USBHS_DEVCTRL) Test packet mode Position */ +#define USBHS_DEVCTRL_TSTPCKT_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTPCKT_Pos) /**< (USBHS_DEVCTRL) Test packet mode Mask */ +#define USBHS_DEVCTRL_TSTPCKT(value) (USBHS_DEVCTRL_TSTPCKT_Msk & ((value) << USBHS_DEVCTRL_TSTPCKT_Pos)) +#define USBHS_DEVCTRL_OPMODE2_Pos _U_(16) /**< (USBHS_DEVCTRL) Specific Operational mode Position */ +#define USBHS_DEVCTRL_OPMODE2_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE2_Pos) /**< (USBHS_DEVCTRL) Specific Operational mode Mask */ +#define USBHS_DEVCTRL_OPMODE2(value) (USBHS_DEVCTRL_OPMODE2_Msk & ((value) << USBHS_DEVCTRL_OPMODE2_Pos)) +#define USBHS_DEVCTRL_Msk _U_(0x0001FFFF) /**< (USBHS_DEVCTRL) Register Mask */ + +#define USBHS_DEVCTRL_OPMODE_Pos _U_(16) /**< (USBHS_DEVCTRL Position) Specific Operational mode */ +#define USBHS_DEVCTRL_OPMODE_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE_Pos) /**< (USBHS_DEVCTRL Mask) OPMODE */ +#define USBHS_DEVCTRL_OPMODE(value) (USBHS_DEVCTRL_OPMODE_Msk & ((value) << USBHS_DEVCTRL_OPMODE_Pos)) + +/* -------- USBHS_DEVISR : (USBHS Offset: 0x04) ( R/ 32) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP_Pos _U_(0) /**< (USBHS_DEVISR) Suspend Interrupt Position */ +#define USBHS_DEVISR_SUSP_Msk (_U_(0x1) << USBHS_DEVISR_SUSP_Pos) /**< (USBHS_DEVISR) Suspend Interrupt Mask */ +#define USBHS_DEVISR_SUSP(value) (USBHS_DEVISR_SUSP_Msk & ((value) << USBHS_DEVISR_SUSP_Pos)) +#define USBHS_DEVISR_MSOF_Pos _U_(1) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Position */ +#define USBHS_DEVISR_MSOF_Msk (_U_(0x1) << USBHS_DEVISR_MSOF_Pos) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_MSOF(value) (USBHS_DEVISR_MSOF_Msk & ((value) << USBHS_DEVISR_MSOF_Pos)) +#define USBHS_DEVISR_SOF_Pos _U_(2) /**< (USBHS_DEVISR) Start of Frame Interrupt Position */ +#define USBHS_DEVISR_SOF_Msk (_U_(0x1) << USBHS_DEVISR_SOF_Pos) /**< (USBHS_DEVISR) Start of Frame Interrupt Mask */ +#define USBHS_DEVISR_SOF(value) (USBHS_DEVISR_SOF_Msk & ((value) << USBHS_DEVISR_SOF_Pos)) +#define USBHS_DEVISR_EORST_Pos _U_(3) /**< (USBHS_DEVISR) End of Reset Interrupt Position */ +#define USBHS_DEVISR_EORST_Msk (_U_(0x1) << USBHS_DEVISR_EORST_Pos) /**< (USBHS_DEVISR) End of Reset Interrupt Mask */ +#define USBHS_DEVISR_EORST(value) (USBHS_DEVISR_EORST_Msk & ((value) << USBHS_DEVISR_EORST_Pos)) +#define USBHS_DEVISR_WAKEUP_Pos _U_(4) /**< (USBHS_DEVISR) Wake-Up Interrupt Position */ +#define USBHS_DEVISR_WAKEUP_Msk (_U_(0x1) << USBHS_DEVISR_WAKEUP_Pos) /**< (USBHS_DEVISR) Wake-Up Interrupt Mask */ +#define USBHS_DEVISR_WAKEUP(value) (USBHS_DEVISR_WAKEUP_Msk & ((value) << USBHS_DEVISR_WAKEUP_Pos)) +#define USBHS_DEVISR_EORSM_Pos _U_(5) /**< (USBHS_DEVISR) End of Resume Interrupt Position */ +#define USBHS_DEVISR_EORSM_Msk (_U_(0x1) << USBHS_DEVISR_EORSM_Pos) /**< (USBHS_DEVISR) End of Resume Interrupt Mask */ +#define USBHS_DEVISR_EORSM(value) (USBHS_DEVISR_EORSM_Msk & ((value) << USBHS_DEVISR_EORSM_Pos)) +#define USBHS_DEVISR_UPRSM_Pos _U_(6) /**< (USBHS_DEVISR) Upstream Resume Interrupt Position */ +#define USBHS_DEVISR_UPRSM_Msk (_U_(0x1) << USBHS_DEVISR_UPRSM_Pos) /**< (USBHS_DEVISR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVISR_UPRSM(value) (USBHS_DEVISR_UPRSM_Msk & ((value) << USBHS_DEVISR_UPRSM_Pos)) +#define USBHS_DEVISR_PEP_0_Pos _U_(12) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Position */ +#define USBHS_DEVISR_PEP_0_Msk (_U_(0x1) << USBHS_DEVISR_PEP_0_Pos) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVISR_PEP_0(value) (USBHS_DEVISR_PEP_0_Msk & ((value) << USBHS_DEVISR_PEP_0_Pos)) +#define USBHS_DEVISR_PEP_1_Pos _U_(13) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Position */ +#define USBHS_DEVISR_PEP_1_Msk (_U_(0x1) << USBHS_DEVISR_PEP_1_Pos) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVISR_PEP_1(value) (USBHS_DEVISR_PEP_1_Msk & ((value) << USBHS_DEVISR_PEP_1_Pos)) +#define USBHS_DEVISR_PEP_2_Pos _U_(14) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Position */ +#define USBHS_DEVISR_PEP_2_Msk (_U_(0x1) << USBHS_DEVISR_PEP_2_Pos) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVISR_PEP_2(value) (USBHS_DEVISR_PEP_2_Msk & ((value) << USBHS_DEVISR_PEP_2_Pos)) +#define USBHS_DEVISR_PEP_3_Pos _U_(15) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Position */ +#define USBHS_DEVISR_PEP_3_Msk (_U_(0x1) << USBHS_DEVISR_PEP_3_Pos) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVISR_PEP_3(value) (USBHS_DEVISR_PEP_3_Msk & ((value) << USBHS_DEVISR_PEP_3_Pos)) +#define USBHS_DEVISR_PEP_4_Pos _U_(16) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Position */ +#define USBHS_DEVISR_PEP_4_Msk (_U_(0x1) << USBHS_DEVISR_PEP_4_Pos) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVISR_PEP_4(value) (USBHS_DEVISR_PEP_4_Msk & ((value) << USBHS_DEVISR_PEP_4_Pos)) +#define USBHS_DEVISR_PEP_5_Pos _U_(17) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Position */ +#define USBHS_DEVISR_PEP_5_Msk (_U_(0x1) << USBHS_DEVISR_PEP_5_Pos) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVISR_PEP_5(value) (USBHS_DEVISR_PEP_5_Msk & ((value) << USBHS_DEVISR_PEP_5_Pos)) +#define USBHS_DEVISR_PEP_6_Pos _U_(18) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Position */ +#define USBHS_DEVISR_PEP_6_Msk (_U_(0x1) << USBHS_DEVISR_PEP_6_Pos) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVISR_PEP_6(value) (USBHS_DEVISR_PEP_6_Msk & ((value) << USBHS_DEVISR_PEP_6_Pos)) +#define USBHS_DEVISR_PEP_7_Pos _U_(19) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Position */ +#define USBHS_DEVISR_PEP_7_Msk (_U_(0x1) << USBHS_DEVISR_PEP_7_Pos) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVISR_PEP_7(value) (USBHS_DEVISR_PEP_7_Msk & ((value) << USBHS_DEVISR_PEP_7_Pos)) +#define USBHS_DEVISR_PEP_8_Pos _U_(20) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Position */ +#define USBHS_DEVISR_PEP_8_Msk (_U_(0x1) << USBHS_DEVISR_PEP_8_Pos) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVISR_PEP_8(value) (USBHS_DEVISR_PEP_8_Msk & ((value) << USBHS_DEVISR_PEP_8_Pos)) +#define USBHS_DEVISR_PEP_9_Pos _U_(21) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Position */ +#define USBHS_DEVISR_PEP_9_Msk (_U_(0x1) << USBHS_DEVISR_PEP_9_Pos) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVISR_PEP_9(value) (USBHS_DEVISR_PEP_9_Msk & ((value) << USBHS_DEVISR_PEP_9_Pos)) +#define USBHS_DEVISR_DMA_1_Pos _U_(25) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Position */ +#define USBHS_DEVISR_DMA_1_Msk (_U_(0x1) << USBHS_DEVISR_DMA_1_Pos) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVISR_DMA_1(value) (USBHS_DEVISR_DMA_1_Msk & ((value) << USBHS_DEVISR_DMA_1_Pos)) +#define USBHS_DEVISR_DMA_2_Pos _U_(26) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Position */ +#define USBHS_DEVISR_DMA_2_Msk (_U_(0x1) << USBHS_DEVISR_DMA_2_Pos) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVISR_DMA_2(value) (USBHS_DEVISR_DMA_2_Msk & ((value) << USBHS_DEVISR_DMA_2_Pos)) +#define USBHS_DEVISR_DMA_3_Pos _U_(27) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Position */ +#define USBHS_DEVISR_DMA_3_Msk (_U_(0x1) << USBHS_DEVISR_DMA_3_Pos) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVISR_DMA_3(value) (USBHS_DEVISR_DMA_3_Msk & ((value) << USBHS_DEVISR_DMA_3_Pos)) +#define USBHS_DEVISR_DMA_4_Pos _U_(28) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Position */ +#define USBHS_DEVISR_DMA_4_Msk (_U_(0x1) << USBHS_DEVISR_DMA_4_Pos) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVISR_DMA_4(value) (USBHS_DEVISR_DMA_4_Msk & ((value) << USBHS_DEVISR_DMA_4_Pos)) +#define USBHS_DEVISR_DMA_5_Pos _U_(29) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Position */ +#define USBHS_DEVISR_DMA_5_Msk (_U_(0x1) << USBHS_DEVISR_DMA_5_Pos) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVISR_DMA_5(value) (USBHS_DEVISR_DMA_5_Msk & ((value) << USBHS_DEVISR_DMA_5_Pos)) +#define USBHS_DEVISR_DMA_6_Pos _U_(30) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Position */ +#define USBHS_DEVISR_DMA_6_Msk (_U_(0x1) << USBHS_DEVISR_DMA_6_Pos) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVISR_DMA_6(value) (USBHS_DEVISR_DMA_6_Msk & ((value) << USBHS_DEVISR_DMA_6_Pos)) +#define USBHS_DEVISR_DMA_7_Pos _U_(31) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Position */ +#define USBHS_DEVISR_DMA_7_Msk (_U_(0x1) << USBHS_DEVISR_DMA_7_Pos) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVISR_DMA_7(value) (USBHS_DEVISR_DMA_7_Msk & ((value) << USBHS_DEVISR_DMA_7_Pos)) +#define USBHS_DEVISR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVISR) Register Mask */ + +#define USBHS_DEVISR_PEP__Pos _U_(12) /**< (USBHS_DEVISR Position) Endpoint x Interrupt */ +#define USBHS_DEVISR_PEP__Msk (_U_(0x3FF) << USBHS_DEVISR_PEP__Pos) /**< (USBHS_DEVISR Mask) PEP_ */ +#define USBHS_DEVISR_PEP_(value) (USBHS_DEVISR_PEP__Msk & ((value) << USBHS_DEVISR_PEP__Pos)) +#define USBHS_DEVISR_DMA__Pos _U_(25) /**< (USBHS_DEVISR Position) DMA Channel 7 Interrupt */ +#define USBHS_DEVISR_DMA__Msk (_U_(0x7F) << USBHS_DEVISR_DMA__Pos) /**< (USBHS_DEVISR Mask) DMA_ */ +#define USBHS_DEVISR_DMA_(value) (USBHS_DEVISR_DMA__Msk & ((value) << USBHS_DEVISR_DMA__Pos)) + +/* -------- USBHS_DEVICR : (USBHS Offset: 0x08) ( /W 32) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC_Pos _U_(0) /**< (USBHS_DEVICR) Suspend Interrupt Clear Position */ +#define USBHS_DEVICR_SUSPC_Msk (_U_(0x1) << USBHS_DEVICR_SUSPC_Pos) /**< (USBHS_DEVICR) Suspend Interrupt Clear Mask */ +#define USBHS_DEVICR_SUSPC(value) (USBHS_DEVICR_SUSPC_Msk & ((value) << USBHS_DEVICR_SUSPC_Pos)) +#define USBHS_DEVICR_MSOFC_Pos _U_(1) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_MSOFC_Msk (_U_(0x1) << USBHS_DEVICR_MSOFC_Pos) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_MSOFC(value) (USBHS_DEVICR_MSOFC_Msk & ((value) << USBHS_DEVICR_MSOFC_Pos)) +#define USBHS_DEVICR_SOFC_Pos _U_(2) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Position */ +#define USBHS_DEVICR_SOFC_Msk (_U_(0x1) << USBHS_DEVICR_SOFC_Pos) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Mask */ +#define USBHS_DEVICR_SOFC(value) (USBHS_DEVICR_SOFC_Msk & ((value) << USBHS_DEVICR_SOFC_Pos)) +#define USBHS_DEVICR_EORSTC_Pos _U_(3) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Position */ +#define USBHS_DEVICR_EORSTC_Msk (_U_(0x1) << USBHS_DEVICR_EORSTC_Pos) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSTC(value) (USBHS_DEVICR_EORSTC_Msk & ((value) << USBHS_DEVICR_EORSTC_Pos)) +#define USBHS_DEVICR_WAKEUPC_Pos _U_(4) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Position */ +#define USBHS_DEVICR_WAKEUPC_Msk (_U_(0x1) << USBHS_DEVICR_WAKEUPC_Pos) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Mask */ +#define USBHS_DEVICR_WAKEUPC(value) (USBHS_DEVICR_WAKEUPC_Msk & ((value) << USBHS_DEVICR_WAKEUPC_Pos)) +#define USBHS_DEVICR_EORSMC_Pos _U_(5) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Position */ +#define USBHS_DEVICR_EORSMC_Msk (_U_(0x1) << USBHS_DEVICR_EORSMC_Pos) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_EORSMC(value) (USBHS_DEVICR_EORSMC_Msk & ((value) << USBHS_DEVICR_EORSMC_Pos)) +#define USBHS_DEVICR_UPRSMC_Pos _U_(6) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Position */ +#define USBHS_DEVICR_UPRSMC_Msk (_U_(0x1) << USBHS_DEVICR_UPRSMC_Pos) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Mask */ +#define USBHS_DEVICR_UPRSMC(value) (USBHS_DEVICR_UPRSMC_Msk & ((value) << USBHS_DEVICR_UPRSMC_Pos)) +#define USBHS_DEVICR_Msk _U_(0x0000007F) /**< (USBHS_DEVICR) Register Mask */ + + +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x0C) ( /W 32) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS_Pos _U_(0) /**< (USBHS_DEVIFR) Suspend Interrupt Set Position */ +#define USBHS_DEVIFR_SUSPS_Msk (_U_(0x1) << USBHS_DEVIFR_SUSPS_Pos) /**< (USBHS_DEVIFR) Suspend Interrupt Set Mask */ +#define USBHS_DEVIFR_SUSPS(value) (USBHS_DEVIFR_SUSPS_Msk & ((value) << USBHS_DEVIFR_SUSPS_Pos)) +#define USBHS_DEVIFR_MSOFS_Pos _U_(1) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_MSOFS_Msk (_U_(0x1) << USBHS_DEVIFR_MSOFS_Pos) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_MSOFS(value) (USBHS_DEVIFR_MSOFS_Msk & ((value) << USBHS_DEVIFR_MSOFS_Pos)) +#define USBHS_DEVIFR_SOFS_Pos _U_(2) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Position */ +#define USBHS_DEVIFR_SOFS_Msk (_U_(0x1) << USBHS_DEVIFR_SOFS_Pos) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Mask */ +#define USBHS_DEVIFR_SOFS(value) (USBHS_DEVIFR_SOFS_Msk & ((value) << USBHS_DEVIFR_SOFS_Pos)) +#define USBHS_DEVIFR_EORSTS_Pos _U_(3) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Position */ +#define USBHS_DEVIFR_EORSTS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSTS_Pos) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSTS(value) (USBHS_DEVIFR_EORSTS_Msk & ((value) << USBHS_DEVIFR_EORSTS_Pos)) +#define USBHS_DEVIFR_WAKEUPS_Pos _U_(4) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Position */ +#define USBHS_DEVIFR_WAKEUPS_Msk (_U_(0x1) << USBHS_DEVIFR_WAKEUPS_Pos) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Mask */ +#define USBHS_DEVIFR_WAKEUPS(value) (USBHS_DEVIFR_WAKEUPS_Msk & ((value) << USBHS_DEVIFR_WAKEUPS_Pos)) +#define USBHS_DEVIFR_EORSMS_Pos _U_(5) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Position */ +#define USBHS_DEVIFR_EORSMS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSMS_Pos) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_EORSMS(value) (USBHS_DEVIFR_EORSMS_Msk & ((value) << USBHS_DEVIFR_EORSMS_Pos)) +#define USBHS_DEVIFR_UPRSMS_Pos _U_(6) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Position */ +#define USBHS_DEVIFR_UPRSMS_Msk (_U_(0x1) << USBHS_DEVIFR_UPRSMS_Pos) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Mask */ +#define USBHS_DEVIFR_UPRSMS(value) (USBHS_DEVIFR_UPRSMS_Msk & ((value) << USBHS_DEVIFR_UPRSMS_Pos)) +#define USBHS_DEVIFR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_1_Pos) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_1(value) (USBHS_DEVIFR_DMA_1_Msk & ((value) << USBHS_DEVIFR_DMA_1_Pos)) +#define USBHS_DEVIFR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_2_Pos) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_2(value) (USBHS_DEVIFR_DMA_2_Msk & ((value) << USBHS_DEVIFR_DMA_2_Pos)) +#define USBHS_DEVIFR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_3_Pos) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_3(value) (USBHS_DEVIFR_DMA_3_Msk & ((value) << USBHS_DEVIFR_DMA_3_Pos)) +#define USBHS_DEVIFR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_4_Pos) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_4(value) (USBHS_DEVIFR_DMA_4_Msk & ((value) << USBHS_DEVIFR_DMA_4_Pos)) +#define USBHS_DEVIFR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_5_Pos) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_5(value) (USBHS_DEVIFR_DMA_5_Msk & ((value) << USBHS_DEVIFR_DMA_5_Pos)) +#define USBHS_DEVIFR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_6_Pos) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_6(value) (USBHS_DEVIFR_DMA_6_Msk & ((value) << USBHS_DEVIFR_DMA_6_Pos)) +#define USBHS_DEVIFR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Position */ +#define USBHS_DEVIFR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_7_Pos) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Mask */ +#define USBHS_DEVIFR_DMA_7(value) (USBHS_DEVIFR_DMA_7_Msk & ((value) << USBHS_DEVIFR_DMA_7_Pos)) +#define USBHS_DEVIFR_Msk _U_(0xFE00007F) /**< (USBHS_DEVIFR) Register Mask */ + +#define USBHS_DEVIFR_DMA__Pos _U_(25) /**< (USBHS_DEVIFR Position) DMA Channel 7 Interrupt Set */ +#define USBHS_DEVIFR_DMA__Msk (_U_(0x7F) << USBHS_DEVIFR_DMA__Pos) /**< (USBHS_DEVIFR Mask) DMA_ */ +#define USBHS_DEVIFR_DMA_(value) (USBHS_DEVIFR_DMA__Msk & ((value) << USBHS_DEVIFR_DMA__Pos)) + +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x10) ( R/ 32) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE_Pos _U_(0) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Position */ +#define USBHS_DEVIMR_SUSPE_Msk (_U_(0x1) << USBHS_DEVIMR_SUSPE_Pos) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Mask */ +#define USBHS_DEVIMR_SUSPE(value) (USBHS_DEVIMR_SUSPE_Msk & ((value) << USBHS_DEVIMR_SUSPE_Pos)) +#define USBHS_DEVIMR_MSOFE_Pos _U_(1) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_MSOFE_Msk (_U_(0x1) << USBHS_DEVIMR_MSOFE_Pos) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_MSOFE(value) (USBHS_DEVIMR_MSOFE_Msk & ((value) << USBHS_DEVIMR_MSOFE_Pos)) +#define USBHS_DEVIMR_SOFE_Pos _U_(2) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Position */ +#define USBHS_DEVIMR_SOFE_Msk (_U_(0x1) << USBHS_DEVIMR_SOFE_Pos) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Mask */ +#define USBHS_DEVIMR_SOFE(value) (USBHS_DEVIMR_SOFE_Msk & ((value) << USBHS_DEVIMR_SOFE_Pos)) +#define USBHS_DEVIMR_EORSTE_Pos _U_(3) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSTE_Msk (_U_(0x1) << USBHS_DEVIMR_EORSTE_Pos) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSTE(value) (USBHS_DEVIMR_EORSTE_Msk & ((value) << USBHS_DEVIMR_EORSTE_Pos)) +#define USBHS_DEVIMR_WAKEUPE_Pos _U_(4) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Position */ +#define USBHS_DEVIMR_WAKEUPE_Msk (_U_(0x1) << USBHS_DEVIMR_WAKEUPE_Pos) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Mask */ +#define USBHS_DEVIMR_WAKEUPE(value) (USBHS_DEVIMR_WAKEUPE_Msk & ((value) << USBHS_DEVIMR_WAKEUPE_Pos)) +#define USBHS_DEVIMR_EORSME_Pos _U_(5) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_EORSME_Msk (_U_(0x1) << USBHS_DEVIMR_EORSME_Pos) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_EORSME(value) (USBHS_DEVIMR_EORSME_Msk & ((value) << USBHS_DEVIMR_EORSME_Pos)) +#define USBHS_DEVIMR_UPRSME_Pos _U_(6) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Position */ +#define USBHS_DEVIMR_UPRSME_Msk (_U_(0x1) << USBHS_DEVIMR_UPRSME_Pos) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Mask */ +#define USBHS_DEVIMR_UPRSME(value) (USBHS_DEVIMR_UPRSME_Msk & ((value) << USBHS_DEVIMR_UPRSME_Pos)) +#define USBHS_DEVIMR_PEP_0_Pos _U_(12) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_0_Pos) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_0(value) (USBHS_DEVIMR_PEP_0_Msk & ((value) << USBHS_DEVIMR_PEP_0_Pos)) +#define USBHS_DEVIMR_PEP_1_Pos _U_(13) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_1_Pos) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_1(value) (USBHS_DEVIMR_PEP_1_Msk & ((value) << USBHS_DEVIMR_PEP_1_Pos)) +#define USBHS_DEVIMR_PEP_2_Pos _U_(14) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_2_Pos) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_2(value) (USBHS_DEVIMR_PEP_2_Msk & ((value) << USBHS_DEVIMR_PEP_2_Pos)) +#define USBHS_DEVIMR_PEP_3_Pos _U_(15) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_3_Pos) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_3(value) (USBHS_DEVIMR_PEP_3_Msk & ((value) << USBHS_DEVIMR_PEP_3_Pos)) +#define USBHS_DEVIMR_PEP_4_Pos _U_(16) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_4_Pos) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_4(value) (USBHS_DEVIMR_PEP_4_Msk & ((value) << USBHS_DEVIMR_PEP_4_Pos)) +#define USBHS_DEVIMR_PEP_5_Pos _U_(17) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_5_Pos) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_5(value) (USBHS_DEVIMR_PEP_5_Msk & ((value) << USBHS_DEVIMR_PEP_5_Pos)) +#define USBHS_DEVIMR_PEP_6_Pos _U_(18) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_6_Pos) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_6(value) (USBHS_DEVIMR_PEP_6_Msk & ((value) << USBHS_DEVIMR_PEP_6_Pos)) +#define USBHS_DEVIMR_PEP_7_Pos _U_(19) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_7_Pos) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_7(value) (USBHS_DEVIMR_PEP_7_Msk & ((value) << USBHS_DEVIMR_PEP_7_Pos)) +#define USBHS_DEVIMR_PEP_8_Pos _U_(20) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_8_Pos) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_8(value) (USBHS_DEVIMR_PEP_8_Msk & ((value) << USBHS_DEVIMR_PEP_8_Pos)) +#define USBHS_DEVIMR_PEP_9_Pos _U_(21) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Position */ +#define USBHS_DEVIMR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_9_Pos) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Mask */ +#define USBHS_DEVIMR_PEP_9(value) (USBHS_DEVIMR_PEP_9_Msk & ((value) << USBHS_DEVIMR_PEP_9_Pos)) +#define USBHS_DEVIMR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_1_Pos) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_1(value) (USBHS_DEVIMR_DMA_1_Msk & ((value) << USBHS_DEVIMR_DMA_1_Pos)) +#define USBHS_DEVIMR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_2_Pos) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_2(value) (USBHS_DEVIMR_DMA_2_Msk & ((value) << USBHS_DEVIMR_DMA_2_Pos)) +#define USBHS_DEVIMR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_3_Pos) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_3(value) (USBHS_DEVIMR_DMA_3_Msk & ((value) << USBHS_DEVIMR_DMA_3_Pos)) +#define USBHS_DEVIMR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_4_Pos) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_4(value) (USBHS_DEVIMR_DMA_4_Msk & ((value) << USBHS_DEVIMR_DMA_4_Pos)) +#define USBHS_DEVIMR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_5_Pos) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_5(value) (USBHS_DEVIMR_DMA_5_Msk & ((value) << USBHS_DEVIMR_DMA_5_Pos)) +#define USBHS_DEVIMR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_6_Pos) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_6(value) (USBHS_DEVIMR_DMA_6_Msk & ((value) << USBHS_DEVIMR_DMA_6_Pos)) +#define USBHS_DEVIMR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Position */ +#define USBHS_DEVIMR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_7_Pos) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Mask */ +#define USBHS_DEVIMR_DMA_7(value) (USBHS_DEVIMR_DMA_7_Msk & ((value) << USBHS_DEVIMR_DMA_7_Pos)) +#define USBHS_DEVIMR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIMR) Register Mask */ + +#define USBHS_DEVIMR_PEP__Pos _U_(12) /**< (USBHS_DEVIMR Position) Endpoint x Interrupt Mask */ +#define USBHS_DEVIMR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIMR_PEP__Pos) /**< (USBHS_DEVIMR Mask) PEP_ */ +#define USBHS_DEVIMR_PEP_(value) (USBHS_DEVIMR_PEP__Msk & ((value) << USBHS_DEVIMR_PEP__Pos)) +#define USBHS_DEVIMR_DMA__Pos _U_(25) /**< (USBHS_DEVIMR Position) DMA Channel 7 Interrupt Mask */ +#define USBHS_DEVIMR_DMA__Msk (_U_(0x7F) << USBHS_DEVIMR_DMA__Pos) /**< (USBHS_DEVIMR Mask) DMA_ */ +#define USBHS_DEVIMR_DMA_(value) (USBHS_DEVIMR_DMA__Msk & ((value) << USBHS_DEVIMR_DMA__Pos)) + +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x14) ( /W 32) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC_Pos _U_(0) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Position */ +#define USBHS_DEVIDR_SUSPEC_Msk (_U_(0x1) << USBHS_DEVIDR_SUSPEC_Pos) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Mask */ +#define USBHS_DEVIDR_SUSPEC(value) (USBHS_DEVIDR_SUSPEC_Msk & ((value) << USBHS_DEVIDR_SUSPEC_Pos)) +#define USBHS_DEVIDR_MSOFEC_Pos _U_(1) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_MSOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_MSOFEC_Pos) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_MSOFEC(value) (USBHS_DEVIDR_MSOFEC_Msk & ((value) << USBHS_DEVIDR_MSOFEC_Pos)) +#define USBHS_DEVIDR_SOFEC_Pos _U_(2) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Position */ +#define USBHS_DEVIDR_SOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_SOFEC_Pos) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Mask */ +#define USBHS_DEVIDR_SOFEC(value) (USBHS_DEVIDR_SOFEC_Msk & ((value) << USBHS_DEVIDR_SOFEC_Pos)) +#define USBHS_DEVIDR_EORSTEC_Pos _U_(3) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSTEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSTEC_Pos) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSTEC(value) (USBHS_DEVIDR_EORSTEC_Msk & ((value) << USBHS_DEVIDR_EORSTEC_Pos)) +#define USBHS_DEVIDR_WAKEUPEC_Pos _U_(4) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Position */ +#define USBHS_DEVIDR_WAKEUPEC_Msk (_U_(0x1) << USBHS_DEVIDR_WAKEUPEC_Pos) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Mask */ +#define USBHS_DEVIDR_WAKEUPEC(value) (USBHS_DEVIDR_WAKEUPEC_Msk & ((value) << USBHS_DEVIDR_WAKEUPEC_Pos)) +#define USBHS_DEVIDR_EORSMEC_Pos _U_(5) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_EORSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSMEC_Pos) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_EORSMEC(value) (USBHS_DEVIDR_EORSMEC_Msk & ((value) << USBHS_DEVIDR_EORSMEC_Pos)) +#define USBHS_DEVIDR_UPRSMEC_Pos _U_(6) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Position */ +#define USBHS_DEVIDR_UPRSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_UPRSMEC_Pos) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Mask */ +#define USBHS_DEVIDR_UPRSMEC(value) (USBHS_DEVIDR_UPRSMEC_Msk & ((value) << USBHS_DEVIDR_UPRSMEC_Pos)) +#define USBHS_DEVIDR_PEP_0_Pos _U_(12) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_0_Pos) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_0(value) (USBHS_DEVIDR_PEP_0_Msk & ((value) << USBHS_DEVIDR_PEP_0_Pos)) +#define USBHS_DEVIDR_PEP_1_Pos _U_(13) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_1_Pos) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_1(value) (USBHS_DEVIDR_PEP_1_Msk & ((value) << USBHS_DEVIDR_PEP_1_Pos)) +#define USBHS_DEVIDR_PEP_2_Pos _U_(14) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_2_Pos) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_2(value) (USBHS_DEVIDR_PEP_2_Msk & ((value) << USBHS_DEVIDR_PEP_2_Pos)) +#define USBHS_DEVIDR_PEP_3_Pos _U_(15) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_3_Pos) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_3(value) (USBHS_DEVIDR_PEP_3_Msk & ((value) << USBHS_DEVIDR_PEP_3_Pos)) +#define USBHS_DEVIDR_PEP_4_Pos _U_(16) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_4_Pos) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_4(value) (USBHS_DEVIDR_PEP_4_Msk & ((value) << USBHS_DEVIDR_PEP_4_Pos)) +#define USBHS_DEVIDR_PEP_5_Pos _U_(17) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_5_Pos) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_5(value) (USBHS_DEVIDR_PEP_5_Msk & ((value) << USBHS_DEVIDR_PEP_5_Pos)) +#define USBHS_DEVIDR_PEP_6_Pos _U_(18) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_6_Pos) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_6(value) (USBHS_DEVIDR_PEP_6_Msk & ((value) << USBHS_DEVIDR_PEP_6_Pos)) +#define USBHS_DEVIDR_PEP_7_Pos _U_(19) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_7_Pos) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_7(value) (USBHS_DEVIDR_PEP_7_Msk & ((value) << USBHS_DEVIDR_PEP_7_Pos)) +#define USBHS_DEVIDR_PEP_8_Pos _U_(20) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_8_Pos) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_8(value) (USBHS_DEVIDR_PEP_8_Msk & ((value) << USBHS_DEVIDR_PEP_8_Pos)) +#define USBHS_DEVIDR_PEP_9_Pos _U_(21) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Position */ +#define USBHS_DEVIDR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_9_Pos) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Mask */ +#define USBHS_DEVIDR_PEP_9(value) (USBHS_DEVIDR_PEP_9_Msk & ((value) << USBHS_DEVIDR_PEP_9_Pos)) +#define USBHS_DEVIDR_DMA_1_Pos _U_(25) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_1_Pos) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_1(value) (USBHS_DEVIDR_DMA_1_Msk & ((value) << USBHS_DEVIDR_DMA_1_Pos)) +#define USBHS_DEVIDR_DMA_2_Pos _U_(26) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_2_Pos) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_2(value) (USBHS_DEVIDR_DMA_2_Msk & ((value) << USBHS_DEVIDR_DMA_2_Pos)) +#define USBHS_DEVIDR_DMA_3_Pos _U_(27) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_3_Pos) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_3(value) (USBHS_DEVIDR_DMA_3_Msk & ((value) << USBHS_DEVIDR_DMA_3_Pos)) +#define USBHS_DEVIDR_DMA_4_Pos _U_(28) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_4_Pos) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_4(value) (USBHS_DEVIDR_DMA_4_Msk & ((value) << USBHS_DEVIDR_DMA_4_Pos)) +#define USBHS_DEVIDR_DMA_5_Pos _U_(29) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_5_Pos) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_5(value) (USBHS_DEVIDR_DMA_5_Msk & ((value) << USBHS_DEVIDR_DMA_5_Pos)) +#define USBHS_DEVIDR_DMA_6_Pos _U_(30) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_6_Pos) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_6(value) (USBHS_DEVIDR_DMA_6_Msk & ((value) << USBHS_DEVIDR_DMA_6_Pos)) +#define USBHS_DEVIDR_DMA_7_Pos _U_(31) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Position */ +#define USBHS_DEVIDR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_7_Pos) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Mask */ +#define USBHS_DEVIDR_DMA_7(value) (USBHS_DEVIDR_DMA_7_Msk & ((value) << USBHS_DEVIDR_DMA_7_Pos)) +#define USBHS_DEVIDR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIDR) Register Mask */ + +#define USBHS_DEVIDR_PEP__Pos _U_(12) /**< (USBHS_DEVIDR Position) Endpoint x Interrupt Disable */ +#define USBHS_DEVIDR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIDR_PEP__Pos) /**< (USBHS_DEVIDR Mask) PEP_ */ +#define USBHS_DEVIDR_PEP_(value) (USBHS_DEVIDR_PEP__Msk & ((value) << USBHS_DEVIDR_PEP__Pos)) +#define USBHS_DEVIDR_DMA__Pos _U_(25) /**< (USBHS_DEVIDR Position) DMA Channel 7 Interrupt Disable */ +#define USBHS_DEVIDR_DMA__Msk (_U_(0x7F) << USBHS_DEVIDR_DMA__Pos) /**< (USBHS_DEVIDR Mask) DMA_ */ +#define USBHS_DEVIDR_DMA_(value) (USBHS_DEVIDR_DMA__Msk & ((value) << USBHS_DEVIDR_DMA__Pos)) + +/* -------- USBHS_DEVIER : (USBHS Offset: 0x18) ( /W 32) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES_Pos _U_(0) /**< (USBHS_DEVIER) Suspend Interrupt Enable Position */ +#define USBHS_DEVIER_SUSPES_Msk (_U_(0x1) << USBHS_DEVIER_SUSPES_Pos) /**< (USBHS_DEVIER) Suspend Interrupt Enable Mask */ +#define USBHS_DEVIER_SUSPES(value) (USBHS_DEVIER_SUSPES_Msk & ((value) << USBHS_DEVIER_SUSPES_Pos)) +#define USBHS_DEVIER_MSOFES_Pos _U_(1) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_MSOFES_Msk (_U_(0x1) << USBHS_DEVIER_MSOFES_Pos) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_MSOFES(value) (USBHS_DEVIER_MSOFES_Msk & ((value) << USBHS_DEVIER_MSOFES_Pos)) +#define USBHS_DEVIER_SOFES_Pos _U_(2) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Position */ +#define USBHS_DEVIER_SOFES_Msk (_U_(0x1) << USBHS_DEVIER_SOFES_Pos) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Mask */ +#define USBHS_DEVIER_SOFES(value) (USBHS_DEVIER_SOFES_Msk & ((value) << USBHS_DEVIER_SOFES_Pos)) +#define USBHS_DEVIER_EORSTES_Pos _U_(3) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Position */ +#define USBHS_DEVIER_EORSTES_Msk (_U_(0x1) << USBHS_DEVIER_EORSTES_Pos) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSTES(value) (USBHS_DEVIER_EORSTES_Msk & ((value) << USBHS_DEVIER_EORSTES_Pos)) +#define USBHS_DEVIER_WAKEUPES_Pos _U_(4) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Position */ +#define USBHS_DEVIER_WAKEUPES_Msk (_U_(0x1) << USBHS_DEVIER_WAKEUPES_Pos) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Mask */ +#define USBHS_DEVIER_WAKEUPES(value) (USBHS_DEVIER_WAKEUPES_Msk & ((value) << USBHS_DEVIER_WAKEUPES_Pos)) +#define USBHS_DEVIER_EORSMES_Pos _U_(5) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Position */ +#define USBHS_DEVIER_EORSMES_Msk (_U_(0x1) << USBHS_DEVIER_EORSMES_Pos) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_EORSMES(value) (USBHS_DEVIER_EORSMES_Msk & ((value) << USBHS_DEVIER_EORSMES_Pos)) +#define USBHS_DEVIER_UPRSMES_Pos _U_(6) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Position */ +#define USBHS_DEVIER_UPRSMES_Msk (_U_(0x1) << USBHS_DEVIER_UPRSMES_Pos) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Mask */ +#define USBHS_DEVIER_UPRSMES(value) (USBHS_DEVIER_UPRSMES_Msk & ((value) << USBHS_DEVIER_UPRSMES_Pos)) +#define USBHS_DEVIER_PEP_0_Pos _U_(12) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_0_Msk (_U_(0x1) << USBHS_DEVIER_PEP_0_Pos) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_0(value) (USBHS_DEVIER_PEP_0_Msk & ((value) << USBHS_DEVIER_PEP_0_Pos)) +#define USBHS_DEVIER_PEP_1_Pos _U_(13) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_1_Msk (_U_(0x1) << USBHS_DEVIER_PEP_1_Pos) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_1(value) (USBHS_DEVIER_PEP_1_Msk & ((value) << USBHS_DEVIER_PEP_1_Pos)) +#define USBHS_DEVIER_PEP_2_Pos _U_(14) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_2_Msk (_U_(0x1) << USBHS_DEVIER_PEP_2_Pos) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_2(value) (USBHS_DEVIER_PEP_2_Msk & ((value) << USBHS_DEVIER_PEP_2_Pos)) +#define USBHS_DEVIER_PEP_3_Pos _U_(15) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_3_Msk (_U_(0x1) << USBHS_DEVIER_PEP_3_Pos) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_3(value) (USBHS_DEVIER_PEP_3_Msk & ((value) << USBHS_DEVIER_PEP_3_Pos)) +#define USBHS_DEVIER_PEP_4_Pos _U_(16) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_4_Msk (_U_(0x1) << USBHS_DEVIER_PEP_4_Pos) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_4(value) (USBHS_DEVIER_PEP_4_Msk & ((value) << USBHS_DEVIER_PEP_4_Pos)) +#define USBHS_DEVIER_PEP_5_Pos _U_(17) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_5_Msk (_U_(0x1) << USBHS_DEVIER_PEP_5_Pos) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_5(value) (USBHS_DEVIER_PEP_5_Msk & ((value) << USBHS_DEVIER_PEP_5_Pos)) +#define USBHS_DEVIER_PEP_6_Pos _U_(18) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_6_Msk (_U_(0x1) << USBHS_DEVIER_PEP_6_Pos) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_6(value) (USBHS_DEVIER_PEP_6_Msk & ((value) << USBHS_DEVIER_PEP_6_Pos)) +#define USBHS_DEVIER_PEP_7_Pos _U_(19) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_7_Msk (_U_(0x1) << USBHS_DEVIER_PEP_7_Pos) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_7(value) (USBHS_DEVIER_PEP_7_Msk & ((value) << USBHS_DEVIER_PEP_7_Pos)) +#define USBHS_DEVIER_PEP_8_Pos _U_(20) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_8_Msk (_U_(0x1) << USBHS_DEVIER_PEP_8_Pos) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_8(value) (USBHS_DEVIER_PEP_8_Msk & ((value) << USBHS_DEVIER_PEP_8_Pos)) +#define USBHS_DEVIER_PEP_9_Pos _U_(21) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Position */ +#define USBHS_DEVIER_PEP_9_Msk (_U_(0x1) << USBHS_DEVIER_PEP_9_Pos) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Mask */ +#define USBHS_DEVIER_PEP_9(value) (USBHS_DEVIER_PEP_9_Msk & ((value) << USBHS_DEVIER_PEP_9_Pos)) +#define USBHS_DEVIER_DMA_1_Pos _U_(25) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_1_Msk (_U_(0x1) << USBHS_DEVIER_DMA_1_Pos) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_1(value) (USBHS_DEVIER_DMA_1_Msk & ((value) << USBHS_DEVIER_DMA_1_Pos)) +#define USBHS_DEVIER_DMA_2_Pos _U_(26) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_2_Msk (_U_(0x1) << USBHS_DEVIER_DMA_2_Pos) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_2(value) (USBHS_DEVIER_DMA_2_Msk & ((value) << USBHS_DEVIER_DMA_2_Pos)) +#define USBHS_DEVIER_DMA_3_Pos _U_(27) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_3_Msk (_U_(0x1) << USBHS_DEVIER_DMA_3_Pos) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_3(value) (USBHS_DEVIER_DMA_3_Msk & ((value) << USBHS_DEVIER_DMA_3_Pos)) +#define USBHS_DEVIER_DMA_4_Pos _U_(28) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_4_Msk (_U_(0x1) << USBHS_DEVIER_DMA_4_Pos) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_4(value) (USBHS_DEVIER_DMA_4_Msk & ((value) << USBHS_DEVIER_DMA_4_Pos)) +#define USBHS_DEVIER_DMA_5_Pos _U_(29) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_5_Msk (_U_(0x1) << USBHS_DEVIER_DMA_5_Pos) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_5(value) (USBHS_DEVIER_DMA_5_Msk & ((value) << USBHS_DEVIER_DMA_5_Pos)) +#define USBHS_DEVIER_DMA_6_Pos _U_(30) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_6_Msk (_U_(0x1) << USBHS_DEVIER_DMA_6_Pos) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_6(value) (USBHS_DEVIER_DMA_6_Msk & ((value) << USBHS_DEVIER_DMA_6_Pos)) +#define USBHS_DEVIER_DMA_7_Pos _U_(31) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Position */ +#define USBHS_DEVIER_DMA_7_Msk (_U_(0x1) << USBHS_DEVIER_DMA_7_Pos) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Mask */ +#define USBHS_DEVIER_DMA_7(value) (USBHS_DEVIER_DMA_7_Msk & ((value) << USBHS_DEVIER_DMA_7_Pos)) +#define USBHS_DEVIER_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIER) Register Mask */ + +#define USBHS_DEVIER_PEP__Pos _U_(12) /**< (USBHS_DEVIER Position) Endpoint x Interrupt Enable */ +#define USBHS_DEVIER_PEP__Msk (_U_(0x3FF) << USBHS_DEVIER_PEP__Pos) /**< (USBHS_DEVIER Mask) PEP_ */ +#define USBHS_DEVIER_PEP_(value) (USBHS_DEVIER_PEP__Msk & ((value) << USBHS_DEVIER_PEP__Pos)) +#define USBHS_DEVIER_DMA__Pos _U_(25) /**< (USBHS_DEVIER Position) DMA Channel 7 Interrupt Enable */ +#define USBHS_DEVIER_DMA__Msk (_U_(0x7F) << USBHS_DEVIER_DMA__Pos) /**< (USBHS_DEVIER Mask) DMA_ */ +#define USBHS_DEVIER_DMA_(value) (USBHS_DEVIER_DMA__Msk & ((value) << USBHS_DEVIER_DMA__Pos)) + +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x1C) (R/W 32) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0_Pos _U_(0) /**< (USBHS_DEVEPT) Endpoint 0 Enable Position */ +#define USBHS_DEVEPT_EPEN0_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Enable Mask */ +#define USBHS_DEVEPT_EPEN0(value) (USBHS_DEVEPT_EPEN0_Msk & ((value) << USBHS_DEVEPT_EPEN0_Pos)) +#define USBHS_DEVEPT_EPEN1_Pos _U_(1) /**< (USBHS_DEVEPT) Endpoint 1 Enable Position */ +#define USBHS_DEVEPT_EPEN1_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Enable Mask */ +#define USBHS_DEVEPT_EPEN1(value) (USBHS_DEVEPT_EPEN1_Msk & ((value) << USBHS_DEVEPT_EPEN1_Pos)) +#define USBHS_DEVEPT_EPEN2_Pos _U_(2) /**< (USBHS_DEVEPT) Endpoint 2 Enable Position */ +#define USBHS_DEVEPT_EPEN2_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Enable Mask */ +#define USBHS_DEVEPT_EPEN2(value) (USBHS_DEVEPT_EPEN2_Msk & ((value) << USBHS_DEVEPT_EPEN2_Pos)) +#define USBHS_DEVEPT_EPEN3_Pos _U_(3) /**< (USBHS_DEVEPT) Endpoint 3 Enable Position */ +#define USBHS_DEVEPT_EPEN3_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Enable Mask */ +#define USBHS_DEVEPT_EPEN3(value) (USBHS_DEVEPT_EPEN3_Msk & ((value) << USBHS_DEVEPT_EPEN3_Pos)) +#define USBHS_DEVEPT_EPEN4_Pos _U_(4) /**< (USBHS_DEVEPT) Endpoint 4 Enable Position */ +#define USBHS_DEVEPT_EPEN4_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Enable Mask */ +#define USBHS_DEVEPT_EPEN4(value) (USBHS_DEVEPT_EPEN4_Msk & ((value) << USBHS_DEVEPT_EPEN4_Pos)) +#define USBHS_DEVEPT_EPEN5_Pos _U_(5) /**< (USBHS_DEVEPT) Endpoint 5 Enable Position */ +#define USBHS_DEVEPT_EPEN5_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Enable Mask */ +#define USBHS_DEVEPT_EPEN5(value) (USBHS_DEVEPT_EPEN5_Msk & ((value) << USBHS_DEVEPT_EPEN5_Pos)) +#define USBHS_DEVEPT_EPEN6_Pos _U_(6) /**< (USBHS_DEVEPT) Endpoint 6 Enable Position */ +#define USBHS_DEVEPT_EPEN6_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Enable Mask */ +#define USBHS_DEVEPT_EPEN6(value) (USBHS_DEVEPT_EPEN6_Msk & ((value) << USBHS_DEVEPT_EPEN6_Pos)) +#define USBHS_DEVEPT_EPEN7_Pos _U_(7) /**< (USBHS_DEVEPT) Endpoint 7 Enable Position */ +#define USBHS_DEVEPT_EPEN7_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Enable Mask */ +#define USBHS_DEVEPT_EPEN7(value) (USBHS_DEVEPT_EPEN7_Msk & ((value) << USBHS_DEVEPT_EPEN7_Pos)) +#define USBHS_DEVEPT_EPEN8_Pos _U_(8) /**< (USBHS_DEVEPT) Endpoint 8 Enable Position */ +#define USBHS_DEVEPT_EPEN8_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Enable Mask */ +#define USBHS_DEVEPT_EPEN8(value) (USBHS_DEVEPT_EPEN8_Msk & ((value) << USBHS_DEVEPT_EPEN8_Pos)) +#define USBHS_DEVEPT_EPEN9_Pos _U_(9) /**< (USBHS_DEVEPT) Endpoint 9 Enable Position */ +#define USBHS_DEVEPT_EPEN9_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Enable Mask */ +#define USBHS_DEVEPT_EPEN9(value) (USBHS_DEVEPT_EPEN9_Msk & ((value) << USBHS_DEVEPT_EPEN9_Pos)) +#define USBHS_DEVEPT_EPRST0_Pos _U_(16) /**< (USBHS_DEVEPT) Endpoint 0 Reset Position */ +#define USBHS_DEVEPT_EPRST0_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Reset Mask */ +#define USBHS_DEVEPT_EPRST0(value) (USBHS_DEVEPT_EPRST0_Msk & ((value) << USBHS_DEVEPT_EPRST0_Pos)) +#define USBHS_DEVEPT_EPRST1_Pos _U_(17) /**< (USBHS_DEVEPT) Endpoint 1 Reset Position */ +#define USBHS_DEVEPT_EPRST1_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Reset Mask */ +#define USBHS_DEVEPT_EPRST1(value) (USBHS_DEVEPT_EPRST1_Msk & ((value) << USBHS_DEVEPT_EPRST1_Pos)) +#define USBHS_DEVEPT_EPRST2_Pos _U_(18) /**< (USBHS_DEVEPT) Endpoint 2 Reset Position */ +#define USBHS_DEVEPT_EPRST2_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Reset Mask */ +#define USBHS_DEVEPT_EPRST2(value) (USBHS_DEVEPT_EPRST2_Msk & ((value) << USBHS_DEVEPT_EPRST2_Pos)) +#define USBHS_DEVEPT_EPRST3_Pos _U_(19) /**< (USBHS_DEVEPT) Endpoint 3 Reset Position */ +#define USBHS_DEVEPT_EPRST3_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Reset Mask */ +#define USBHS_DEVEPT_EPRST3(value) (USBHS_DEVEPT_EPRST3_Msk & ((value) << USBHS_DEVEPT_EPRST3_Pos)) +#define USBHS_DEVEPT_EPRST4_Pos _U_(20) /**< (USBHS_DEVEPT) Endpoint 4 Reset Position */ +#define USBHS_DEVEPT_EPRST4_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Reset Mask */ +#define USBHS_DEVEPT_EPRST4(value) (USBHS_DEVEPT_EPRST4_Msk & ((value) << USBHS_DEVEPT_EPRST4_Pos)) +#define USBHS_DEVEPT_EPRST5_Pos _U_(21) /**< (USBHS_DEVEPT) Endpoint 5 Reset Position */ +#define USBHS_DEVEPT_EPRST5_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Reset Mask */ +#define USBHS_DEVEPT_EPRST5(value) (USBHS_DEVEPT_EPRST5_Msk & ((value) << USBHS_DEVEPT_EPRST5_Pos)) +#define USBHS_DEVEPT_EPRST6_Pos _U_(22) /**< (USBHS_DEVEPT) Endpoint 6 Reset Position */ +#define USBHS_DEVEPT_EPRST6_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Reset Mask */ +#define USBHS_DEVEPT_EPRST6(value) (USBHS_DEVEPT_EPRST6_Msk & ((value) << USBHS_DEVEPT_EPRST6_Pos)) +#define USBHS_DEVEPT_EPRST7_Pos _U_(23) /**< (USBHS_DEVEPT) Endpoint 7 Reset Position */ +#define USBHS_DEVEPT_EPRST7_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Reset Mask */ +#define USBHS_DEVEPT_EPRST7(value) (USBHS_DEVEPT_EPRST7_Msk & ((value) << USBHS_DEVEPT_EPRST7_Pos)) +#define USBHS_DEVEPT_EPRST8_Pos _U_(24) /**< (USBHS_DEVEPT) Endpoint 8 Reset Position */ +#define USBHS_DEVEPT_EPRST8_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Reset Mask */ +#define USBHS_DEVEPT_EPRST8(value) (USBHS_DEVEPT_EPRST8_Msk & ((value) << USBHS_DEVEPT_EPRST8_Pos)) +#define USBHS_DEVEPT_EPRST9_Pos _U_(25) /**< (USBHS_DEVEPT) Endpoint 9 Reset Position */ +#define USBHS_DEVEPT_EPRST9_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Reset Mask */ +#define USBHS_DEVEPT_EPRST9(value) (USBHS_DEVEPT_EPRST9_Msk & ((value) << USBHS_DEVEPT_EPRST9_Pos)) +#define USBHS_DEVEPT_Msk _U_(0x03FF03FF) /**< (USBHS_DEVEPT) Register Mask */ + +#define USBHS_DEVEPT_EPEN_Pos _U_(0) /**< (USBHS_DEVEPT Position) Endpoint x Enable */ +#define USBHS_DEVEPT_EPEN_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPEN_Pos) /**< (USBHS_DEVEPT Mask) EPEN */ +#define USBHS_DEVEPT_EPEN(value) (USBHS_DEVEPT_EPEN_Msk & ((value) << USBHS_DEVEPT_EPEN_Pos)) +#define USBHS_DEVEPT_EPRST_Pos _U_(16) /**< (USBHS_DEVEPT Position) Endpoint 9 Reset */ +#define USBHS_DEVEPT_EPRST_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPRST_Pos) /**< (USBHS_DEVEPT Mask) EPRST */ +#define USBHS_DEVEPT_EPRST(value) (USBHS_DEVEPT_EPRST_Msk & ((value) << USBHS_DEVEPT_EPRST_Pos)) + +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x20) ( R/ 32) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos _U_(0) /**< (USBHS_DEVFNUM) Micro Frame Number Position */ +#define USBHS_DEVFNUM_MFNUM_Msk (_U_(0x7) << USBHS_DEVFNUM_MFNUM_Pos) /**< (USBHS_DEVFNUM) Micro Frame Number Mask */ +#define USBHS_DEVFNUM_MFNUM(value) (USBHS_DEVFNUM_MFNUM_Msk & ((value) << USBHS_DEVFNUM_MFNUM_Pos)) +#define USBHS_DEVFNUM_FNUM_Pos _U_(3) /**< (USBHS_DEVFNUM) Frame Number Position */ +#define USBHS_DEVFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_DEVFNUM_FNUM_Pos) /**< (USBHS_DEVFNUM) Frame Number Mask */ +#define USBHS_DEVFNUM_FNUM(value) (USBHS_DEVFNUM_FNUM_Msk & ((value) << USBHS_DEVFNUM_FNUM_Pos)) +#define USBHS_DEVFNUM_FNCERR_Pos _U_(15) /**< (USBHS_DEVFNUM) Frame Number CRC Error Position */ +#define USBHS_DEVFNUM_FNCERR_Msk (_U_(0x1) << USBHS_DEVFNUM_FNCERR_Pos) /**< (USBHS_DEVFNUM) Frame Number CRC Error Mask */ +#define USBHS_DEVFNUM_FNCERR(value) (USBHS_DEVFNUM_FNCERR_Msk & ((value) << USBHS_DEVFNUM_FNCERR_Pos)) +#define USBHS_DEVFNUM_Msk _U_(0x0000BFFF) /**< (USBHS_DEVFNUM) Register Mask */ + + +/* -------- USBHS_DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ +#define USBHS_DEVEPTCFG_ALLOC_Pos _U_(1) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Position */ +#define USBHS_DEVEPTCFG_ALLOC_Msk (_U_(0x1) << USBHS_DEVEPTCFG_ALLOC_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Mask */ +#define USBHS_DEVEPTCFG_ALLOC(value) (USBHS_DEVEPTCFG_ALLOC_Msk & ((value) << USBHS_DEVEPTCFG_ALLOC_Pos)) +#define USBHS_DEVEPTCFG_EPBK_Pos _U_(2) /**< (USBHS_DEVEPTCFG) Endpoint Banks Position */ +#define USBHS_DEVEPTCFG_EPBK_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Banks Mask */ +#define USBHS_DEVEPTCFG_EPBK(value) (USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)) +#define USBHS_DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_1_BANK (USBHS_DEVEPTCFG_EPBK_1_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Single-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (USBHS_DEVEPTCFG_EPBK_2_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Double-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (USBHS_DEVEPTCFG_EPBK_3_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos _U_(4) /**< (USBHS_DEVEPTCFG) Endpoint Size Position */ +#define USBHS_DEVEPTCFG_EPSIZE_Msk (_U_(0x7) << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Size Mask */ +#define USBHS_DEVEPTCFG_EPSIZE(value) (USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_DEVEPTCFG) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_DEVEPTCFG) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_DEVEPTCFG) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_DEVEPTCFG) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 8 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 16 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 32 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 64 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 128 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 256 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 512 bytes Position */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 1024 bytes Position */ +#define USBHS_DEVEPTCFG_EPDIR_Pos _U_(8) /**< (USBHS_DEVEPTCFG) Endpoint Direction Position */ +#define USBHS_DEVEPTCFG_EPDIR_Msk (_U_(0x1) << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Direction Mask */ +#define USBHS_DEVEPTCFG_EPDIR(value) (USBHS_DEVEPTCFG_EPDIR_Msk & ((value) << USBHS_DEVEPTCFG_EPDIR_Pos)) +#define USBHS_DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (USBHS_DEVEPTCFG_EPDIR_OUT_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. Position */ +#define USBHS_DEVEPTCFG_EPDIR_IN (USBHS_DEVEPTCFG_EPDIR_IN_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Pos _U_(9) /**< (USBHS_DEVEPTCFG) Automatic Switch Position */ +#define USBHS_DEVEPTCFG_AUTOSW_Msk (_U_(0x1) << USBHS_DEVEPTCFG_AUTOSW_Pos) /**< (USBHS_DEVEPTCFG) Automatic Switch Mask */ +#define USBHS_DEVEPTCFG_AUTOSW(value) (USBHS_DEVEPTCFG_AUTOSW_Msk & ((value) << USBHS_DEVEPTCFG_AUTOSW_Pos)) +#define USBHS_DEVEPTCFG_EPTYPE_Pos _U_(11) /**< (USBHS_DEVEPTCFG) Endpoint Type Position */ +#define USBHS_DEVEPTCFG_EPTYPE_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Type Mask */ +#define USBHS_DEVEPTCFG_EPTYPE(value) (USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Interrupt */ +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (USBHS_DEVEPTCFG_EPTYPE_CTRL_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Control Position */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (USBHS_DEVEPTCFG_EPTYPE_ISO_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Isochronous Position */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (USBHS_DEVEPTCFG_EPTYPE_BLK_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Bulk Position */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Interrupt Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos _U_(13) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ +#define USBHS_DEVEPTCFG_NBTRANS_Msk (_U_(0x3) << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ +#define USBHS_DEVEPTCFG_NBTRANS(value) (USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ +#define USBHS_DEVEPTCFG_Msk _U_(0x00007B7E) /**< (USBHS_DEVEPTCFG) Register Mask */ + + +/* -------- USBHS_DEVEPTISR : (USBHS Offset: 0x130) ( R/ 32) Device Endpoint Interrupt Status Register -------- */ +#define USBHS_DEVEPTISR_TXINI_Pos _U_(0) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTISR_TXINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_TXINI_Pos) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTISR_TXINI(value) (USBHS_DEVEPTISR_TXINI_Msk & ((value) << USBHS_DEVEPTISR_TXINI_Pos)) +#define USBHS_DEVEPTISR_RXOUTI_Pos _U_(1) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTISR_RXOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_RXOUTI_Pos) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTISR_RXOUTI(value) (USBHS_DEVEPTISR_RXOUTI_Msk & ((value) << USBHS_DEVEPTISR_RXOUTI_Pos)) +#define USBHS_DEVEPTISR_OVERFI_Pos _U_(5) /**< (USBHS_DEVEPTISR) Overflow Interrupt Position */ +#define USBHS_DEVEPTISR_OVERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_OVERFI_Pos) /**< (USBHS_DEVEPTISR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTISR_OVERFI(value) (USBHS_DEVEPTISR_OVERFI_Msk & ((value) << USBHS_DEVEPTISR_OVERFI_Pos)) +#define USBHS_DEVEPTISR_SHORTPACKET_Pos _U_(7) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTISR_SHORTPACKET_Msk (_U_(0x1) << USBHS_DEVEPTISR_SHORTPACKET_Pos) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTISR_SHORTPACKET(value) (USBHS_DEVEPTISR_SHORTPACKET_Msk & ((value) << USBHS_DEVEPTISR_SHORTPACKET_Pos)) +#define USBHS_DEVEPTISR_DTSEQ_Pos _U_(8) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_Msk (_U_(0x3) << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Mask */ +#define USBHS_DEVEPTISR_DTSEQ(value) (USBHS_DEVEPTISR_DTSEQ_Msk & ((value) << USBHS_DEVEPTISR_DTSEQ_Pos)) +#define USBHS_DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (USBHS_DEVEPTISR_DTSEQ_DATA0_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data0 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (USBHS_DEVEPTISR_DTSEQ_DATA1_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data1 toggle sequence Position */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (USBHS_DEVEPTISR_DTSEQ_DATA2_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (USBHS_DEVEPTISR_DTSEQ_MDATA_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos _U_(12) /**< (USBHS_DEVEPTISR) Number of Busy Banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) Number of Busy Banks Mask */ +#define USBHS_DEVEPTISR_NBUSYBK(value) (USBHS_DEVEPTISR_NBUSYBK_Msk & ((value) << USBHS_DEVEPTISR_NBUSYBK_Pos)) +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_DEVEPTISR) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_DEVEPTISR) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_DEVEPTISR) 3 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) Position */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 1 busy bank Position */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 2 busy banks Position */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 3 busy banks Position */ +#define USBHS_DEVEPTISR_CURRBK_Pos _U_(14) /**< (USBHS_DEVEPTISR) Current Bank Position */ +#define USBHS_DEVEPTISR_CURRBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current Bank Mask */ +#define USBHS_DEVEPTISR_CURRBK(value) (USBHS_DEVEPTISR_CURRBK_Msk & ((value) << USBHS_DEVEPTISR_CURRBK_Pos)) +#define USBHS_DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Current bank is bank2 */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (USBHS_DEVEPTISR_CURRBK_BANK0_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank0 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (USBHS_DEVEPTISR_CURRBK_BANK1_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank1 Position */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (USBHS_DEVEPTISR_CURRBK_BANK2_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank2 Position */ +#define USBHS_DEVEPTISR_RWALL_Pos _U_(16) /**< (USBHS_DEVEPTISR) Read/Write Allowed Position */ +#define USBHS_DEVEPTISR_RWALL_Msk (_U_(0x1) << USBHS_DEVEPTISR_RWALL_Pos) /**< (USBHS_DEVEPTISR) Read/Write Allowed Mask */ +#define USBHS_DEVEPTISR_RWALL(value) (USBHS_DEVEPTISR_RWALL_Msk & ((value) << USBHS_DEVEPTISR_RWALL_Pos)) +#define USBHS_DEVEPTISR_CFGOK_Pos _U_(18) /**< (USBHS_DEVEPTISR) Configuration OK Status Position */ +#define USBHS_DEVEPTISR_CFGOK_Msk (_U_(0x1) << USBHS_DEVEPTISR_CFGOK_Pos) /**< (USBHS_DEVEPTISR) Configuration OK Status Mask */ +#define USBHS_DEVEPTISR_CFGOK(value) (USBHS_DEVEPTISR_CFGOK_Msk & ((value) << USBHS_DEVEPTISR_CFGOK_Pos)) +#define USBHS_DEVEPTISR_BYCT_Pos _U_(20) /**< (USBHS_DEVEPTISR) Byte Count Position */ +#define USBHS_DEVEPTISR_BYCT_Msk (_U_(0x7FF) << USBHS_DEVEPTISR_BYCT_Pos) /**< (USBHS_DEVEPTISR) Byte Count Mask */ +#define USBHS_DEVEPTISR_BYCT(value) (USBHS_DEVEPTISR_BYCT_Msk & ((value) << USBHS_DEVEPTISR_BYCT_Pos)) +#define USBHS_DEVEPTISR_Msk _U_(0x7FF5F3A3) /**< (USBHS_DEVEPTISR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI_Pos _U_(2) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_RXSTPI(value) (USBHS_DEVEPTISR_CTRL_RXSTPI_Msk & ((value) << USBHS_DEVEPTISR_CTRL_RXSTPI_Pos)) +#define USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos _U_(3) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_NAKOUTI(value) (USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk & ((value) << USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos)) +#define USBHS_DEVEPTISR_CTRL_NAKINI_Pos _U_(4) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_NAKINI(value) (USBHS_DEVEPTISR_CTRL_NAKINI_Msk & ((value) << USBHS_DEVEPTISR_CTRL_NAKINI_Pos)) +#define USBHS_DEVEPTISR_CTRL_STALLEDI_Pos _U_(6) /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_CTRL_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_CTRL_STALLEDI(value) (USBHS_DEVEPTISR_CTRL_STALLEDI_Msk & ((value) << USBHS_DEVEPTISR_CTRL_STALLEDI_Pos)) +#define USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos _U_(17) /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_CTRL_CTRLDIR(value) (USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk & ((value) << USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos)) +#define USBHS_DEVEPTISR_CTRL_Msk _U_(0x0002005C) /**< (USBHS_DEVEPTISR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTISR_ISO_UNDERFI_Pos _U_(2) /**< (USBHS_DEVEPTISR) Underflow Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_UNDERFI_Pos) /**< (USBHS_DEVEPTISR) Underflow Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_UNDERFI(value) (USBHS_DEVEPTISR_ISO_UNDERFI_Msk & ((value) << USBHS_DEVEPTISR_ISO_UNDERFI_Pos)) +#define USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos _U_(3) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_HBISOINERRI(value) (USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk & ((value) << USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos)) +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos _U_(4) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_HBISOFLUSHI(value) (USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk & ((value) << USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos)) +#define USBHS_DEVEPTISR_ISO_CRCERRI_Pos _U_(6) /**< (USBHS_DEVEPTISR) CRC Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_CRCERRI_Pos) /**< (USBHS_DEVEPTISR) CRC Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_CRCERRI(value) (USBHS_DEVEPTISR_ISO_CRCERRI_Msk & ((value) << USBHS_DEVEPTISR_ISO_CRCERRI_Pos)) +#define USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos _U_(10) /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ +#define USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos) /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ +#define USBHS_DEVEPTISR_ISO_ERRORTRANS(value) (USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk & ((value) << USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos)) +#define USBHS_DEVEPTISR_ISO_Msk _U_(0x0000045C) /**< (USBHS_DEVEPTISR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTISR_BLK_RXSTPI_Pos _U_(2) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_RXSTPI(value) (USBHS_DEVEPTISR_BLK_RXSTPI_Msk & ((value) << USBHS_DEVEPTISR_BLK_RXSTPI_Pos)) +#define USBHS_DEVEPTISR_BLK_NAKOUTI_Pos _U_(3) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_NAKOUTI(value) (USBHS_DEVEPTISR_BLK_NAKOUTI_Msk & ((value) << USBHS_DEVEPTISR_BLK_NAKOUTI_Pos)) +#define USBHS_DEVEPTISR_BLK_NAKINI_Pos _U_(4) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_NAKINI(value) (USBHS_DEVEPTISR_BLK_NAKINI_Msk & ((value) << USBHS_DEVEPTISR_BLK_NAKINI_Pos)) +#define USBHS_DEVEPTISR_BLK_STALLEDI_Pos _U_(6) /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_BLK_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_BLK_STALLEDI(value) (USBHS_DEVEPTISR_BLK_STALLEDI_Msk & ((value) << USBHS_DEVEPTISR_BLK_STALLEDI_Pos)) +#define USBHS_DEVEPTISR_BLK_CTRLDIR_Pos _U_(17) /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_BLK_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_BLK_CTRLDIR(value) (USBHS_DEVEPTISR_BLK_CTRLDIR_Msk & ((value) << USBHS_DEVEPTISR_BLK_CTRLDIR_Pos)) +#define USBHS_DEVEPTISR_BLK_Msk _U_(0x0002005C) /**< (USBHS_DEVEPTISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos _U_(2) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_RXSTPI(value) (USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk & ((value) << USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos)) +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos _U_(3) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_NAKOUTI(value) (USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk & ((value) << USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos)) +#define USBHS_DEVEPTISR_INTRPT_NAKINI_Pos _U_(4) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_NAKINI(value) (USBHS_DEVEPTISR_INTRPT_NAKINI_Msk & ((value) << USBHS_DEVEPTISR_INTRPT_NAKINI_Pos)) +#define USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos _U_(6) /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ +#define USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTISR_INTRPT_STALLEDI(value) (USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk & ((value) << USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos)) +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos _U_(17) /**< (USBHS_DEVEPTISR) Control Direction Position */ +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ +#define USBHS_DEVEPTISR_INTRPT_CTRLDIR(value) (USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk & ((value) << USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos)) +#define USBHS_DEVEPTISR_INTRPT_Msk _U_(0x0002005C) /**< (USBHS_DEVEPTISR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTICR : (USBHS Offset: 0x160) ( /W 32) Device Endpoint Interrupt Clear Register -------- */ +#define USBHS_DEVEPTICR_TXINIC_Pos _U_(0) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_TXINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_TXINIC_Pos) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_TXINIC(value) (USBHS_DEVEPTICR_TXINIC_Msk & ((value) << USBHS_DEVEPTICR_TXINIC_Pos)) +#define USBHS_DEVEPTICR_RXOUTIC_Pos _U_(1) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTICR_RXOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_RXOUTIC_Pos) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_RXOUTIC(value) (USBHS_DEVEPTICR_RXOUTIC_Msk & ((value) << USBHS_DEVEPTICR_RXOUTIC_Pos)) +#define USBHS_DEVEPTICR_OVERFIC_Pos _U_(5) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTICR_OVERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_OVERFIC_Pos) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_OVERFIC(value) (USBHS_DEVEPTICR_OVERFIC_Msk & ((value) << USBHS_DEVEPTICR_OVERFIC_Pos)) +#define USBHS_DEVEPTICR_SHORTPACKETC_Pos _U_(7) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Position */ +#define USBHS_DEVEPTICR_SHORTPACKETC_Msk (_U_(0x1) << USBHS_DEVEPTICR_SHORTPACKETC_Pos) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_SHORTPACKETC(value) (USBHS_DEVEPTICR_SHORTPACKETC_Msk & ((value) << USBHS_DEVEPTICR_SHORTPACKETC_Pos)) +#define USBHS_DEVEPTICR_Msk _U_(0x000000A3) /**< (USBHS_DEVEPTICR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos _U_(2) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_RXSTPIC(value) (USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk & ((value) << USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos)) +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos _U_(3) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_NAKOUTIC(value) (USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk & ((value) << USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos)) +#define USBHS_DEVEPTICR_CTRL_NAKINIC_Pos _U_(4) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_NAKINIC(value) (USBHS_DEVEPTICR_CTRL_NAKINIC_Msk & ((value) << USBHS_DEVEPTICR_CTRL_NAKINIC_Pos)) +#define USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos _U_(6) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_CTRL_STALLEDIC(value) (USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk & ((value) << USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos)) +#define USBHS_DEVEPTICR_CTRL_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTICR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC_Pos _U_(2) /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_UNDERFIC_Pos) /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_UNDERFIC(value) (USBHS_DEVEPTICR_ISO_UNDERFIC_Msk & ((value) << USBHS_DEVEPTICR_ISO_UNDERFIC_Pos)) +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos _U_(3) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_HBISOINERRIC(value) (USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk & ((value) << USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos)) +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos _U_(4) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC(value) (USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk & ((value) << USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos)) +#define USBHS_DEVEPTICR_ISO_CRCERRIC_Pos _U_(6) /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Position */ +#define USBHS_DEVEPTICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_CRCERRIC_Pos) /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_ISO_CRCERRIC(value) (USBHS_DEVEPTICR_ISO_CRCERRIC_Msk & ((value) << USBHS_DEVEPTICR_ISO_CRCERRIC_Pos)) +#define USBHS_DEVEPTICR_ISO_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTICR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC_Pos _U_(2) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_RXSTPIC(value) (USBHS_DEVEPTICR_BLK_RXSTPIC_Msk & ((value) << USBHS_DEVEPTICR_BLK_RXSTPIC_Pos)) +#define USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos _U_(3) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_NAKOUTIC(value) (USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk & ((value) << USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos)) +#define USBHS_DEVEPTICR_BLK_NAKINIC_Pos _U_(4) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_NAKINIC(value) (USBHS_DEVEPTICR_BLK_NAKINIC_Msk & ((value) << USBHS_DEVEPTICR_BLK_NAKINIC_Pos)) +#define USBHS_DEVEPTICR_BLK_STALLEDIC_Pos _U_(6) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_BLK_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_BLK_STALLEDIC(value) (USBHS_DEVEPTICR_BLK_STALLEDIC_Msk & ((value) << USBHS_DEVEPTICR_BLK_STALLEDIC_Pos)) +#define USBHS_DEVEPTICR_BLK_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos _U_(2) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_RXSTPIC(value) (USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk & ((value) << USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos)) +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos _U_(3) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_NAKOUTIC(value) (USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk & ((value) << USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos)) +#define USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos _U_(4) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_NAKINIC(value) (USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk & ((value) << USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos)) +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos _U_(6) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTICR_INTRPT_STALLEDIC(value) (USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk & ((value) << USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos)) +#define USBHS_DEVEPTICR_INTRPT_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTICR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIFR : (USBHS Offset: 0x190) ( /W 32) Device Endpoint Interrupt Set Register -------- */ +#define USBHS_DEVEPTIFR_TXINIS_Pos _U_(0) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_TXINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_TXINIS_Pos) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_TXINIS(value) (USBHS_DEVEPTIFR_TXINIS_Msk & ((value) << USBHS_DEVEPTIFR_TXINIS_Pos)) +#define USBHS_DEVEPTIFR_RXOUTIS_Pos _U_(1) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Position */ +#define USBHS_DEVEPTIFR_RXOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_RXOUTIS_Pos) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_RXOUTIS(value) (USBHS_DEVEPTIFR_RXOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_RXOUTIS_Pos)) +#define USBHS_DEVEPTIFR_OVERFIS_Pos _U_(5) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Position */ +#define USBHS_DEVEPTIFR_OVERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_OVERFIS_Pos) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_OVERFIS(value) (USBHS_DEVEPTIFR_OVERFIS_Msk & ((value) << USBHS_DEVEPTIFR_OVERFIS_Pos)) +#define USBHS_DEVEPTIFR_SHORTPACKETS_Pos _U_(7) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Position */ +#define USBHS_DEVEPTIFR_SHORTPACKETS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_SHORTPACKETS(value) (USBHS_DEVEPTIFR_SHORTPACKETS_Msk & ((value) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos)) +#define USBHS_DEVEPTIFR_NBUSYBKS_Pos _U_(12) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ +#define USBHS_DEVEPTIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NBUSYBKS_Pos) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_NBUSYBKS(value) (USBHS_DEVEPTIFR_NBUSYBKS_Msk & ((value) << USBHS_DEVEPTIFR_NBUSYBKS_Pos)) +#define USBHS_DEVEPTIFR_Msk _U_(0x000010A3) /**< (USBHS_DEVEPTIFR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos _U_(2) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_RXSTPIS(value) (USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk & ((value) << USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos)) +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos _U_(3) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_NAKOUTIS(value) (USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos)) +#define USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos _U_(4) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_NAKINIS(value) (USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk & ((value) << USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos)) +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos _U_(6) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_CTRL_STALLEDIS(value) (USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk & ((value) << USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos)) +#define USBHS_DEVEPTIFR_CTRL_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos _U_(2) /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos) /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_UNDERFIS(value) (USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk & ((value) << USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos)) +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos _U_(3) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_HBISOINERRIS(value) (USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk & ((value) << USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos)) +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos _U_(4) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS(value) (USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk & ((value) << USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos)) +#define USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos _U_(6) /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Position */ +#define USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos) /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_ISO_CRCERRIS(value) (USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk & ((value) << USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos)) +#define USBHS_DEVEPTIFR_ISO_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTIFR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos _U_(2) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_RXSTPIS(value) (USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk & ((value) << USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos)) +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos _U_(3) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_NAKOUTIS(value) (USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos)) +#define USBHS_DEVEPTIFR_BLK_NAKINIS_Pos _U_(4) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_NAKINIS(value) (USBHS_DEVEPTIFR_BLK_NAKINIS_Msk & ((value) << USBHS_DEVEPTIFR_BLK_NAKINIS_Pos)) +#define USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos _U_(6) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_BLK_STALLEDIS(value) (USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk & ((value) << USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos)) +#define USBHS_DEVEPTIFR_BLK_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos _U_(2) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_RXSTPIS(value) (USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk & ((value) << USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos)) +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos _U_(3) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS(value) (USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk & ((value) << USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos)) +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos _U_(4) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_NAKINIS(value) (USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk & ((value) << USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos)) +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos _U_(6) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ +#define USBHS_DEVEPTIFR_INTRPT_STALLEDIS(value) (USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk & ((value) << USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos)) +#define USBHS_DEVEPTIFR_INTRPT_Msk _U_(0x0000005C) /**< (USBHS_DEVEPTIFR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIMR : (USBHS Offset: 0x1C0) ( R/ 32) Device Endpoint Interrupt Mask Register -------- */ +#define USBHS_DEVEPTIMR_TXINE_Pos _U_(0) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Position */ +#define USBHS_DEVEPTIMR_TXINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_TXINE_Pos) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_TXINE(value) (USBHS_DEVEPTIMR_TXINE_Msk & ((value) << USBHS_DEVEPTIMR_TXINE_Pos)) +#define USBHS_DEVEPTIMR_RXOUTE_Pos _U_(1) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Position */ +#define USBHS_DEVEPTIMR_RXOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RXOUTE_Pos) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Mask */ +#define USBHS_DEVEPTIMR_RXOUTE(value) (USBHS_DEVEPTIMR_RXOUTE_Msk & ((value) << USBHS_DEVEPTIMR_RXOUTE_Pos)) +#define USBHS_DEVEPTIMR_OVERFE_Pos _U_(5) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Position */ +#define USBHS_DEVEPTIMR_OVERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_OVERFE_Pos) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Mask */ +#define USBHS_DEVEPTIMR_OVERFE(value) (USBHS_DEVEPTIMR_OVERFE_Msk & ((value) << USBHS_DEVEPTIMR_OVERFE_Pos)) +#define USBHS_DEVEPTIMR_SHORTPACKETE_Pos _U_(7) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Position */ +#define USBHS_DEVEPTIMR_SHORTPACKETE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Mask */ +#define USBHS_DEVEPTIMR_SHORTPACKETE(value) (USBHS_DEVEPTIMR_SHORTPACKETE_Msk & ((value) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos)) +#define USBHS_DEVEPTIMR_NBUSYBKE_Pos _U_(12) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Position */ +#define USBHS_DEVEPTIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NBUSYBKE_Pos) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Mask */ +#define USBHS_DEVEPTIMR_NBUSYBKE(value) (USBHS_DEVEPTIMR_NBUSYBKE_Msk & ((value) << USBHS_DEVEPTIMR_NBUSYBKE_Pos)) +#define USBHS_DEVEPTIMR_KILLBK_Pos _U_(13) /**< (USBHS_DEVEPTIMR) Kill IN Bank Position */ +#define USBHS_DEVEPTIMR_KILLBK_Msk (_U_(0x1) << USBHS_DEVEPTIMR_KILLBK_Pos) /**< (USBHS_DEVEPTIMR) Kill IN Bank Mask */ +#define USBHS_DEVEPTIMR_KILLBK(value) (USBHS_DEVEPTIMR_KILLBK_Msk & ((value) << USBHS_DEVEPTIMR_KILLBK_Pos)) +#define USBHS_DEVEPTIMR_FIFOCON_Pos _U_(14) /**< (USBHS_DEVEPTIMR) FIFO Control Position */ +#define USBHS_DEVEPTIMR_FIFOCON_Msk (_U_(0x1) << USBHS_DEVEPTIMR_FIFOCON_Pos) /**< (USBHS_DEVEPTIMR) FIFO Control Mask */ +#define USBHS_DEVEPTIMR_FIFOCON(value) (USBHS_DEVEPTIMR_FIFOCON_Msk & ((value) << USBHS_DEVEPTIMR_FIFOCON_Pos)) +#define USBHS_DEVEPTIMR_EPDISHDMA_Pos _U_(16) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ +#define USBHS_DEVEPTIMR_EPDISHDMA_Msk (_U_(0x1) << USBHS_DEVEPTIMR_EPDISHDMA_Pos) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ +#define USBHS_DEVEPTIMR_EPDISHDMA(value) (USBHS_DEVEPTIMR_EPDISHDMA_Msk & ((value) << USBHS_DEVEPTIMR_EPDISHDMA_Pos)) +#define USBHS_DEVEPTIMR_RSTDT_Pos _U_(18) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Position */ +#define USBHS_DEVEPTIMR_RSTDT_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RSTDT_Pos) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Mask */ +#define USBHS_DEVEPTIMR_RSTDT(value) (USBHS_DEVEPTIMR_RSTDT_Msk & ((value) << USBHS_DEVEPTIMR_RSTDT_Pos)) +#define USBHS_DEVEPTIMR_Msk _U_(0x000570A3) /**< (USBHS_DEVEPTIMR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos _U_(2) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_RXSTPE(value) (USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos)) +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos _U_(3) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_NAKOUTE(value) (USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos)) +#define USBHS_DEVEPTIMR_CTRL_NAKINE_Pos _U_(4) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_NAKINE(value) (USBHS_DEVEPTIMR_CTRL_NAKINE_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_NAKINE_Pos)) +#define USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos _U_(6) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_CTRL_STALLEDE(value) (USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos)) +#define USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos _U_(17) /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_CTRL_NYETDIS(value) (USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos)) +#define USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos _U_(19) /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_CTRL_STALLRQ(value) (USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk & ((value) << USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos)) +#define USBHS_DEVEPTIMR_CTRL_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE_Pos _U_(2) /**< (USBHS_DEVEPTIMR) Underflow Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_UNDERFE_Pos) /**< (USBHS_DEVEPTIMR) Underflow Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_UNDERFE(value) (USBHS_DEVEPTIMR_ISO_UNDERFE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_UNDERFE_Pos)) +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos _U_(3) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_HBISOINERRE(value) (USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos)) +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos _U_(4) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE(value) (USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos)) +#define USBHS_DEVEPTIMR_ISO_CRCERRE_Pos _U_(6) /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_CRCERRE_Pos) /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_CRCERRE(value) (USBHS_DEVEPTIMR_ISO_CRCERRE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_CRCERRE_Pos)) +#define USBHS_DEVEPTIMR_ISO_MDATAE_Pos _U_(8) /**< (USBHS_DEVEPTIMR) MData Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_MDATAE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_MDATAE_Pos) /**< (USBHS_DEVEPTIMR) MData Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_MDATAE(value) (USBHS_DEVEPTIMR_ISO_MDATAE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_MDATAE_Pos)) +#define USBHS_DEVEPTIMR_ISO_DATAXE_Pos _U_(9) /**< (USBHS_DEVEPTIMR) DataX Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_DATAXE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_DATAXE_Pos) /**< (USBHS_DEVEPTIMR) DataX Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_DATAXE(value) (USBHS_DEVEPTIMR_ISO_DATAXE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_DATAXE_Pos)) +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos _U_(10) /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Position */ +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos) /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Mask */ +#define USBHS_DEVEPTIMR_ISO_ERRORTRANSE(value) (USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk & ((value) << USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos)) +#define USBHS_DEVEPTIMR_ISO_Msk _U_(0x0000075C) /**< (USBHS_DEVEPTIMR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE_Pos _U_(2) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_RXSTPE(value) (USBHS_DEVEPTIMR_BLK_RXSTPE_Msk & ((value) << USBHS_DEVEPTIMR_BLK_RXSTPE_Pos)) +#define USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos _U_(3) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_NAKOUTE(value) (USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk & ((value) << USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos)) +#define USBHS_DEVEPTIMR_BLK_NAKINE_Pos _U_(4) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_NAKINE(value) (USBHS_DEVEPTIMR_BLK_NAKINE_Msk & ((value) << USBHS_DEVEPTIMR_BLK_NAKINE_Pos)) +#define USBHS_DEVEPTIMR_BLK_STALLEDE_Pos _U_(6) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_BLK_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_BLK_STALLEDE(value) (USBHS_DEVEPTIMR_BLK_STALLEDE_Msk & ((value) << USBHS_DEVEPTIMR_BLK_STALLEDE_Pos)) +#define USBHS_DEVEPTIMR_BLK_NYETDIS_Pos _U_(17) /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_BLK_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_BLK_NYETDIS(value) (USBHS_DEVEPTIMR_BLK_NYETDIS_Msk & ((value) << USBHS_DEVEPTIMR_BLK_NYETDIS_Pos)) +#define USBHS_DEVEPTIMR_BLK_STALLRQ_Pos _U_(19) /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_BLK_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_BLK_STALLRQ(value) (USBHS_DEVEPTIMR_BLK_STALLRQ_Msk & ((value) << USBHS_DEVEPTIMR_BLK_STALLRQ_Pos)) +#define USBHS_DEVEPTIMR_BLK_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos _U_(2) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_RXSTPE(value) (USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos _U_(3) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NAKOUTE(value) (USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos _U_(4) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NAKINE(value) (USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos _U_(6) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ +#define USBHS_DEVEPTIMR_INTRPT_STALLEDE(value) (USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos _U_(17) /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ +#define USBHS_DEVEPTIMR_INTRPT_NYETDIS(value) (USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos _U_(19) /**< (USBHS_DEVEPTIMR) STALL Request Position */ +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ +#define USBHS_DEVEPTIMR_INTRPT_STALLRQ(value) (USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk & ((value) << USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos)) +#define USBHS_DEVEPTIMR_INTRPT_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIMR_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIER : (USBHS Offset: 0x1F0) ( /W 32) Device Endpoint Interrupt Enable Register -------- */ +#define USBHS_DEVEPTIER_TXINES_Pos _U_(0) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_TXINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_TXINES_Pos) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_TXINES(value) (USBHS_DEVEPTIER_TXINES_Msk & ((value) << USBHS_DEVEPTIER_TXINES_Pos)) +#define USBHS_DEVEPTIER_RXOUTES_Pos _U_(1) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Position */ +#define USBHS_DEVEPTIER_RXOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_RXOUTES_Pos) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_RXOUTES(value) (USBHS_DEVEPTIER_RXOUTES_Msk & ((value) << USBHS_DEVEPTIER_RXOUTES_Pos)) +#define USBHS_DEVEPTIER_OVERFES_Pos _U_(5) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Position */ +#define USBHS_DEVEPTIER_OVERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_OVERFES_Pos) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_OVERFES(value) (USBHS_DEVEPTIER_OVERFES_Msk & ((value) << USBHS_DEVEPTIER_OVERFES_Pos)) +#define USBHS_DEVEPTIER_SHORTPACKETES_Pos _U_(7) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Position */ +#define USBHS_DEVEPTIER_SHORTPACKETES_Msk (_U_(0x1) << USBHS_DEVEPTIER_SHORTPACKETES_Pos) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_SHORTPACKETES(value) (USBHS_DEVEPTIER_SHORTPACKETES_Msk & ((value) << USBHS_DEVEPTIER_SHORTPACKETES_Pos)) +#define USBHS_DEVEPTIER_NBUSYBKES_Pos _U_(12) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_DEVEPTIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NBUSYBKES_Pos) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_NBUSYBKES(value) (USBHS_DEVEPTIER_NBUSYBKES_Msk & ((value) << USBHS_DEVEPTIER_NBUSYBKES_Pos)) +#define USBHS_DEVEPTIER_KILLBKS_Pos _U_(13) /**< (USBHS_DEVEPTIER) Kill IN Bank Position */ +#define USBHS_DEVEPTIER_KILLBKS_Msk (_U_(0x1) << USBHS_DEVEPTIER_KILLBKS_Pos) /**< (USBHS_DEVEPTIER) Kill IN Bank Mask */ +#define USBHS_DEVEPTIER_KILLBKS(value) (USBHS_DEVEPTIER_KILLBKS_Msk & ((value) << USBHS_DEVEPTIER_KILLBKS_Pos)) +#define USBHS_DEVEPTIER_FIFOCONS_Pos _U_(14) /**< (USBHS_DEVEPTIER) FIFO Control Position */ +#define USBHS_DEVEPTIER_FIFOCONS_Msk (_U_(0x1) << USBHS_DEVEPTIER_FIFOCONS_Pos) /**< (USBHS_DEVEPTIER) FIFO Control Mask */ +#define USBHS_DEVEPTIER_FIFOCONS(value) (USBHS_DEVEPTIER_FIFOCONS_Msk & ((value) << USBHS_DEVEPTIER_FIFOCONS_Pos)) +#define USBHS_DEVEPTIER_EPDISHDMAS_Pos _U_(16) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ +#define USBHS_DEVEPTIER_EPDISHDMAS_Msk (_U_(0x1) << USBHS_DEVEPTIER_EPDISHDMAS_Pos) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_DEVEPTIER_EPDISHDMAS(value) (USBHS_DEVEPTIER_EPDISHDMAS_Msk & ((value) << USBHS_DEVEPTIER_EPDISHDMAS_Pos)) +#define USBHS_DEVEPTIER_RSTDTS_Pos _U_(18) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Position */ +#define USBHS_DEVEPTIER_RSTDTS_Msk (_U_(0x1) << USBHS_DEVEPTIER_RSTDTS_Pos) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Mask */ +#define USBHS_DEVEPTIER_RSTDTS(value) (USBHS_DEVEPTIER_RSTDTS_Msk & ((value) << USBHS_DEVEPTIER_RSTDTS_Pos)) +#define USBHS_DEVEPTIER_Msk _U_(0x000570A3) /**< (USBHS_DEVEPTIER) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES_Pos _U_(2) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_RXSTPES(value) (USBHS_DEVEPTIER_CTRL_RXSTPES_Msk & ((value) << USBHS_DEVEPTIER_CTRL_RXSTPES_Pos)) +#define USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos _U_(3) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NAKOUTES(value) (USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk & ((value) << USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos)) +#define USBHS_DEVEPTIER_CTRL_NAKINES_Pos _U_(4) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NAKINES(value) (USBHS_DEVEPTIER_CTRL_NAKINES_Msk & ((value) << USBHS_DEVEPTIER_CTRL_NAKINES_Pos)) +#define USBHS_DEVEPTIER_CTRL_STALLEDES_Pos _U_(6) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_CTRL_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_STALLEDES(value) (USBHS_DEVEPTIER_CTRL_STALLEDES_Msk & ((value) << USBHS_DEVEPTIER_CTRL_STALLEDES_Pos)) +#define USBHS_DEVEPTIER_CTRL_NYETDISS_Pos _U_(17) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_CTRL_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_NYETDISS(value) (USBHS_DEVEPTIER_CTRL_NYETDISS_Msk & ((value) << USBHS_DEVEPTIER_CTRL_NYETDISS_Pos)) +#define USBHS_DEVEPTIER_CTRL_STALLRQS_Pos _U_(19) /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_CTRL_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_CTRL_STALLRQS(value) (USBHS_DEVEPTIER_CTRL_STALLRQS_Msk & ((value) << USBHS_DEVEPTIER_CTRL_STALLRQS_Pos)) +#define USBHS_DEVEPTIER_CTRL_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIER_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIER_ISO_UNDERFES_Pos _U_(2) /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_UNDERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_UNDERFES_Pos) /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_UNDERFES(value) (USBHS_DEVEPTIER_ISO_UNDERFES_Msk & ((value) << USBHS_DEVEPTIER_ISO_UNDERFES_Pos)) +#define USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos _U_(3) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_HBISOINERRES(value) (USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk & ((value) << USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos)) +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos _U_(4) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_HBISOFLUSHES(value) (USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk & ((value) << USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos)) +#define USBHS_DEVEPTIER_ISO_CRCERRES_Pos _U_(6) /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_CRCERRES_Pos) /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_CRCERRES(value) (USBHS_DEVEPTIER_ISO_CRCERRES_Msk & ((value) << USBHS_DEVEPTIER_ISO_CRCERRES_Pos)) +#define USBHS_DEVEPTIER_ISO_MDATAES_Pos _U_(8) /**< (USBHS_DEVEPTIER) MData Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_MDATAES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_MDATAES_Pos) /**< (USBHS_DEVEPTIER) MData Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_MDATAES(value) (USBHS_DEVEPTIER_ISO_MDATAES_Msk & ((value) << USBHS_DEVEPTIER_ISO_MDATAES_Pos)) +#define USBHS_DEVEPTIER_ISO_DATAXES_Pos _U_(9) /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_DATAXES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_DATAXES_Pos) /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_DATAXES(value) (USBHS_DEVEPTIER_ISO_DATAXES_Msk & ((value) << USBHS_DEVEPTIER_ISO_DATAXES_Pos)) +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos _U_(10) /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Position */ +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos) /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_ISO_ERRORTRANSES(value) (USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk & ((value) << USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos)) +#define USBHS_DEVEPTIER_ISO_Msk _U_(0x0000075C) /**< (USBHS_DEVEPTIER_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIER_BLK_RXSTPES_Pos _U_(2) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_RXSTPES(value) (USBHS_DEVEPTIER_BLK_RXSTPES_Msk & ((value) << USBHS_DEVEPTIER_BLK_RXSTPES_Pos)) +#define USBHS_DEVEPTIER_BLK_NAKOUTES_Pos _U_(3) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NAKOUTES(value) (USBHS_DEVEPTIER_BLK_NAKOUTES_Msk & ((value) << USBHS_DEVEPTIER_BLK_NAKOUTES_Pos)) +#define USBHS_DEVEPTIER_BLK_NAKINES_Pos _U_(4) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NAKINES(value) (USBHS_DEVEPTIER_BLK_NAKINES_Msk & ((value) << USBHS_DEVEPTIER_BLK_NAKINES_Pos)) +#define USBHS_DEVEPTIER_BLK_STALLEDES_Pos _U_(6) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_BLK_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_BLK_STALLEDES(value) (USBHS_DEVEPTIER_BLK_STALLEDES_Msk & ((value) << USBHS_DEVEPTIER_BLK_STALLEDES_Pos)) +#define USBHS_DEVEPTIER_BLK_NYETDISS_Pos _U_(17) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_BLK_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_BLK_NYETDISS(value) (USBHS_DEVEPTIER_BLK_NYETDISS_Msk & ((value) << USBHS_DEVEPTIER_BLK_NYETDISS_Pos)) +#define USBHS_DEVEPTIER_BLK_STALLRQS_Pos _U_(19) /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_BLK_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_BLK_STALLRQS(value) (USBHS_DEVEPTIER_BLK_STALLRQS_Msk & ((value) << USBHS_DEVEPTIER_BLK_STALLRQS_Pos)) +#define USBHS_DEVEPTIER_BLK_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos _U_(2) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_RXSTPES(value) (USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos)) +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos _U_(3) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NAKOUTES(value) (USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos)) +#define USBHS_DEVEPTIER_INTRPT_NAKINES_Pos _U_(4) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NAKINES(value) (USBHS_DEVEPTIER_INTRPT_NAKINES_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_NAKINES_Pos)) +#define USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos _U_(6) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_STALLEDES(value) (USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos)) +#define USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos _U_(17) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_NYETDISS(value) (USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos)) +#define USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos _U_(19) /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ +#define USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ +#define USBHS_DEVEPTIER_INTRPT_STALLRQS(value) (USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk & ((value) << USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos)) +#define USBHS_DEVEPTIER_INTRPT_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIER_INTRPT) Register Mask */ + + +/* -------- USBHS_DEVEPTIDR : (USBHS Offset: 0x220) ( /W 32) Device Endpoint Interrupt Disable Register -------- */ +#define USBHS_DEVEPTIDR_TXINEC_Pos _U_(0) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_TXINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_TXINEC_Pos) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_TXINEC(value) (USBHS_DEVEPTIDR_TXINEC_Msk & ((value) << USBHS_DEVEPTIDR_TXINEC_Pos)) +#define USBHS_DEVEPTIDR_RXOUTEC_Pos _U_(1) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_RXOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_RXOUTEC_Pos) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_RXOUTEC(value) (USBHS_DEVEPTIDR_RXOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_RXOUTEC_Pos)) +#define USBHS_DEVEPTIDR_OVERFEC_Pos _U_(5) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_OVERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_OVERFEC_Pos) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_OVERFEC(value) (USBHS_DEVEPTIDR_OVERFEC_Msk & ((value) << USBHS_DEVEPTIDR_OVERFEC_Pos)) +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Pos _U_(7) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC(value) (USBHS_DEVEPTIDR_SHORTPACKETEC_Msk & ((value) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos)) +#define USBHS_DEVEPTIDR_NBUSYBKEC_Pos _U_(12) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_NBUSYBKEC(value) (USBHS_DEVEPTIDR_NBUSYBKEC_Msk & ((value) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos)) +#define USBHS_DEVEPTIDR_FIFOCONC_Pos _U_(14) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Position */ +#define USBHS_DEVEPTIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_FIFOCONC_Pos) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Mask */ +#define USBHS_DEVEPTIDR_FIFOCONC(value) (USBHS_DEVEPTIDR_FIFOCONC_Msk & ((value) << USBHS_DEVEPTIDR_FIFOCONC_Pos)) +#define USBHS_DEVEPTIDR_EPDISHDMAC_Pos _U_(16) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ +#define USBHS_DEVEPTIDR_EPDISHDMAC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ +#define USBHS_DEVEPTIDR_EPDISHDMAC(value) (USBHS_DEVEPTIDR_EPDISHDMAC_Msk & ((value) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos)) +#define USBHS_DEVEPTIDR_Msk _U_(0x000150A3) /**< (USBHS_DEVEPTIDR) Register Mask */ + +/* CTRL mode */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos _U_(2) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_RXSTPEC(value) (USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos _U_(3) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NAKOUTEC(value) (USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos _U_(4) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NAKINEC(value) (USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos _U_(6) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_STALLEDEC(value) (USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos _U_(17) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_NYETDISC(value) (USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos _U_(19) /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_CTRL_STALLRQC(value) (USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk & ((value) << USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos)) +#define USBHS_DEVEPTIDR_CTRL_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos _U_(2) /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos) /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_UNDERFEC(value) (USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos)) +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos _U_(3) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_HBISOINERREC(value) (USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos)) +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos _U_(4) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC(value) (USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos)) +#define USBHS_DEVEPTIDR_ISO_MDATAEC_Pos _U_(8) /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_MDATAEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_MDATAEC_Pos) /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_MDATAEC(value) (USBHS_DEVEPTIDR_ISO_MDATAEC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_MDATAEC_Pos)) +#define USBHS_DEVEPTIDR_ISO_DATAXEC_Pos _U_(9) /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_DATAXEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_DATAXEC_Pos) /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_DATAXEC(value) (USBHS_DEVEPTIDR_ISO_DATAXEC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_DATAXEC_Pos)) +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos _U_(10) /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos) /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC(value) (USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk & ((value) << USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos)) +#define USBHS_DEVEPTIDR_ISO_Msk _U_(0x0000071C) /**< (USBHS_DEVEPTIDR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos _U_(2) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_RXSTPEC(value) (USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos)) +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos _U_(3) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NAKOUTEC(value) (USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos)) +#define USBHS_DEVEPTIDR_BLK_NAKINEC_Pos _U_(4) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NAKINEC(value) (USBHS_DEVEPTIDR_BLK_NAKINEC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_NAKINEC_Pos)) +#define USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos _U_(6) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_STALLEDEC(value) (USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos)) +#define USBHS_DEVEPTIDR_BLK_NYETDISC_Pos _U_(17) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_BLK_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_NYETDISC(value) (USBHS_DEVEPTIDR_BLK_NYETDISC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_NYETDISC_Pos)) +#define USBHS_DEVEPTIDR_BLK_STALLRQC_Pos _U_(19) /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_BLK_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_BLK_STALLRQC(value) (USBHS_DEVEPTIDR_BLK_STALLRQC_Msk & ((value) << USBHS_DEVEPTIDR_BLK_STALLRQC_Pos)) +#define USBHS_DEVEPTIDR_BLK_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos _U_(2) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_RXSTPEC(value) (USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos _U_(3) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC(value) (USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos _U_(4) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NAKINEC(value) (USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos _U_(6) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_STALLEDEC(value) (USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos _U_(17) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_NYETDISC(value) (USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos _U_(19) /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ +#define USBHS_DEVEPTIDR_INTRPT_STALLRQC(value) (USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk & ((value) << USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos)) +#define USBHS_DEVEPTIDR_INTRPT_Msk _U_(0x000A005C) /**< (USBHS_DEVEPTIDR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE_Pos _U_(8) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Position */ +#define USBHS_HSTCTRL_SOFE_Msk (_U_(0x1) << USBHS_HSTCTRL_SOFE_Pos) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Mask */ +#define USBHS_HSTCTRL_SOFE(value) (USBHS_HSTCTRL_SOFE_Msk & ((value) << USBHS_HSTCTRL_SOFE_Pos)) +#define USBHS_HSTCTRL_RESET_Pos _U_(9) /**< (USBHS_HSTCTRL) Send USB Reset Position */ +#define USBHS_HSTCTRL_RESET_Msk (_U_(0x1) << USBHS_HSTCTRL_RESET_Pos) /**< (USBHS_HSTCTRL) Send USB Reset Mask */ +#define USBHS_HSTCTRL_RESET(value) (USBHS_HSTCTRL_RESET_Msk & ((value) << USBHS_HSTCTRL_RESET_Pos)) +#define USBHS_HSTCTRL_RESUME_Pos _U_(10) /**< (USBHS_HSTCTRL) Send USB Resume Position */ +#define USBHS_HSTCTRL_RESUME_Msk (_U_(0x1) << USBHS_HSTCTRL_RESUME_Pos) /**< (USBHS_HSTCTRL) Send USB Resume Mask */ +#define USBHS_HSTCTRL_RESUME(value) (USBHS_HSTCTRL_RESUME_Msk & ((value) << USBHS_HSTCTRL_RESUME_Pos)) +#define USBHS_HSTCTRL_SPDCONF_Pos _U_(12) /**< (USBHS_HSTCTRL) Mode Configuration Position */ +#define USBHS_HSTCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Mode Configuration Mask */ +#define USBHS_HSTCTRL_SPDCONF(value) (USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)) +#define USBHS_HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +#define USBHS_HSTCTRL_SPDCONF_NORMAL (USBHS_HSTCTRL_SPDCONF_NORMAL_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. Position */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Forced high speed. Position */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ +#define USBHS_HSTCTRL_Msk _U_(0x00003700) /**< (USBHS_HSTCTRL) Register Mask */ + + +/* -------- USBHS_HSTISR : (USBHS Offset: 0x404) ( R/ 32) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI_Pos _U_(0) /**< (USBHS_HSTISR) Device Connection Interrupt Position */ +#define USBHS_HSTISR_DCONNI_Msk (_U_(0x1) << USBHS_HSTISR_DCONNI_Pos) /**< (USBHS_HSTISR) Device Connection Interrupt Mask */ +#define USBHS_HSTISR_DCONNI(value) (USBHS_HSTISR_DCONNI_Msk & ((value) << USBHS_HSTISR_DCONNI_Pos)) +#define USBHS_HSTISR_DDISCI_Pos _U_(1) /**< (USBHS_HSTISR) Device Disconnection Interrupt Position */ +#define USBHS_HSTISR_DDISCI_Msk (_U_(0x1) << USBHS_HSTISR_DDISCI_Pos) /**< (USBHS_HSTISR) Device Disconnection Interrupt Mask */ +#define USBHS_HSTISR_DDISCI(value) (USBHS_HSTISR_DDISCI_Msk & ((value) << USBHS_HSTISR_DDISCI_Pos)) +#define USBHS_HSTISR_RSTI_Pos _U_(2) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Position */ +#define USBHS_HSTISR_RSTI_Msk (_U_(0x1) << USBHS_HSTISR_RSTI_Pos) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Mask */ +#define USBHS_HSTISR_RSTI(value) (USBHS_HSTISR_RSTI_Msk & ((value) << USBHS_HSTISR_RSTI_Pos)) +#define USBHS_HSTISR_RSMEDI_Pos _U_(3) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Position */ +#define USBHS_HSTISR_RSMEDI_Msk (_U_(0x1) << USBHS_HSTISR_RSMEDI_Pos) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Mask */ +#define USBHS_HSTISR_RSMEDI(value) (USBHS_HSTISR_RSMEDI_Msk & ((value) << USBHS_HSTISR_RSMEDI_Pos)) +#define USBHS_HSTISR_RXRSMI_Pos _U_(4) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Position */ +#define USBHS_HSTISR_RXRSMI_Msk (_U_(0x1) << USBHS_HSTISR_RXRSMI_Pos) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Mask */ +#define USBHS_HSTISR_RXRSMI(value) (USBHS_HSTISR_RXRSMI_Msk & ((value) << USBHS_HSTISR_RXRSMI_Pos)) +#define USBHS_HSTISR_HSOFI_Pos _U_(5) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Position */ +#define USBHS_HSTISR_HSOFI_Msk (_U_(0x1) << USBHS_HSTISR_HSOFI_Pos) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Mask */ +#define USBHS_HSTISR_HSOFI(value) (USBHS_HSTISR_HSOFI_Msk & ((value) << USBHS_HSTISR_HSOFI_Pos)) +#define USBHS_HSTISR_HWUPI_Pos _U_(6) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Position */ +#define USBHS_HSTISR_HWUPI_Msk (_U_(0x1) << USBHS_HSTISR_HWUPI_Pos) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Mask */ +#define USBHS_HSTISR_HWUPI(value) (USBHS_HSTISR_HWUPI_Msk & ((value) << USBHS_HSTISR_HWUPI_Pos)) +#define USBHS_HSTISR_PEP_0_Pos _U_(8) /**< (USBHS_HSTISR) Pipe 0 Interrupt Position */ +#define USBHS_HSTISR_PEP_0_Msk (_U_(0x1) << USBHS_HSTISR_PEP_0_Pos) /**< (USBHS_HSTISR) Pipe 0 Interrupt Mask */ +#define USBHS_HSTISR_PEP_0(value) (USBHS_HSTISR_PEP_0_Msk & ((value) << USBHS_HSTISR_PEP_0_Pos)) +#define USBHS_HSTISR_PEP_1_Pos _U_(9) /**< (USBHS_HSTISR) Pipe 1 Interrupt Position */ +#define USBHS_HSTISR_PEP_1_Msk (_U_(0x1) << USBHS_HSTISR_PEP_1_Pos) /**< (USBHS_HSTISR) Pipe 1 Interrupt Mask */ +#define USBHS_HSTISR_PEP_1(value) (USBHS_HSTISR_PEP_1_Msk & ((value) << USBHS_HSTISR_PEP_1_Pos)) +#define USBHS_HSTISR_PEP_2_Pos _U_(10) /**< (USBHS_HSTISR) Pipe 2 Interrupt Position */ +#define USBHS_HSTISR_PEP_2_Msk (_U_(0x1) << USBHS_HSTISR_PEP_2_Pos) /**< (USBHS_HSTISR) Pipe 2 Interrupt Mask */ +#define USBHS_HSTISR_PEP_2(value) (USBHS_HSTISR_PEP_2_Msk & ((value) << USBHS_HSTISR_PEP_2_Pos)) +#define USBHS_HSTISR_PEP_3_Pos _U_(11) /**< (USBHS_HSTISR) Pipe 3 Interrupt Position */ +#define USBHS_HSTISR_PEP_3_Msk (_U_(0x1) << USBHS_HSTISR_PEP_3_Pos) /**< (USBHS_HSTISR) Pipe 3 Interrupt Mask */ +#define USBHS_HSTISR_PEP_3(value) (USBHS_HSTISR_PEP_3_Msk & ((value) << USBHS_HSTISR_PEP_3_Pos)) +#define USBHS_HSTISR_PEP_4_Pos _U_(12) /**< (USBHS_HSTISR) Pipe 4 Interrupt Position */ +#define USBHS_HSTISR_PEP_4_Msk (_U_(0x1) << USBHS_HSTISR_PEP_4_Pos) /**< (USBHS_HSTISR) Pipe 4 Interrupt Mask */ +#define USBHS_HSTISR_PEP_4(value) (USBHS_HSTISR_PEP_4_Msk & ((value) << USBHS_HSTISR_PEP_4_Pos)) +#define USBHS_HSTISR_PEP_5_Pos _U_(13) /**< (USBHS_HSTISR) Pipe 5 Interrupt Position */ +#define USBHS_HSTISR_PEP_5_Msk (_U_(0x1) << USBHS_HSTISR_PEP_5_Pos) /**< (USBHS_HSTISR) Pipe 5 Interrupt Mask */ +#define USBHS_HSTISR_PEP_5(value) (USBHS_HSTISR_PEP_5_Msk & ((value) << USBHS_HSTISR_PEP_5_Pos)) +#define USBHS_HSTISR_PEP_6_Pos _U_(14) /**< (USBHS_HSTISR) Pipe 6 Interrupt Position */ +#define USBHS_HSTISR_PEP_6_Msk (_U_(0x1) << USBHS_HSTISR_PEP_6_Pos) /**< (USBHS_HSTISR) Pipe 6 Interrupt Mask */ +#define USBHS_HSTISR_PEP_6(value) (USBHS_HSTISR_PEP_6_Msk & ((value) << USBHS_HSTISR_PEP_6_Pos)) +#define USBHS_HSTISR_PEP_7_Pos _U_(15) /**< (USBHS_HSTISR) Pipe 7 Interrupt Position */ +#define USBHS_HSTISR_PEP_7_Msk (_U_(0x1) << USBHS_HSTISR_PEP_7_Pos) /**< (USBHS_HSTISR) Pipe 7 Interrupt Mask */ +#define USBHS_HSTISR_PEP_7(value) (USBHS_HSTISR_PEP_7_Msk & ((value) << USBHS_HSTISR_PEP_7_Pos)) +#define USBHS_HSTISR_PEP_8_Pos _U_(16) /**< (USBHS_HSTISR) Pipe 8 Interrupt Position */ +#define USBHS_HSTISR_PEP_8_Msk (_U_(0x1) << USBHS_HSTISR_PEP_8_Pos) /**< (USBHS_HSTISR) Pipe 8 Interrupt Mask */ +#define USBHS_HSTISR_PEP_8(value) (USBHS_HSTISR_PEP_8_Msk & ((value) << USBHS_HSTISR_PEP_8_Pos)) +#define USBHS_HSTISR_PEP_9_Pos _U_(17) /**< (USBHS_HSTISR) Pipe 9 Interrupt Position */ +#define USBHS_HSTISR_PEP_9_Msk (_U_(0x1) << USBHS_HSTISR_PEP_9_Pos) /**< (USBHS_HSTISR) Pipe 9 Interrupt Mask */ +#define USBHS_HSTISR_PEP_9(value) (USBHS_HSTISR_PEP_9_Msk & ((value) << USBHS_HSTISR_PEP_9_Pos)) +#define USBHS_HSTISR_DMA_1_Pos _U_(25) /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Position */ +#define USBHS_HSTISR_DMA_1_Msk (_U_(0x1) << USBHS_HSTISR_DMA_1_Pos) /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Mask */ +#define USBHS_HSTISR_DMA_1(value) (USBHS_HSTISR_DMA_1_Msk & ((value) << USBHS_HSTISR_DMA_1_Pos)) +#define USBHS_HSTISR_DMA_2_Pos _U_(26) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Position */ +#define USBHS_HSTISR_DMA_2_Msk (_U_(0x1) << USBHS_HSTISR_DMA_2_Pos) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Mask */ +#define USBHS_HSTISR_DMA_2(value) (USBHS_HSTISR_DMA_2_Msk & ((value) << USBHS_HSTISR_DMA_2_Pos)) +#define USBHS_HSTISR_DMA_3_Pos _U_(27) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Position */ +#define USBHS_HSTISR_DMA_3_Msk (_U_(0x1) << USBHS_HSTISR_DMA_3_Pos) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Mask */ +#define USBHS_HSTISR_DMA_3(value) (USBHS_HSTISR_DMA_3_Msk & ((value) << USBHS_HSTISR_DMA_3_Pos)) +#define USBHS_HSTISR_DMA_4_Pos _U_(28) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Position */ +#define USBHS_HSTISR_DMA_4_Msk (_U_(0x1) << USBHS_HSTISR_DMA_4_Pos) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Mask */ +#define USBHS_HSTISR_DMA_4(value) (USBHS_HSTISR_DMA_4_Msk & ((value) << USBHS_HSTISR_DMA_4_Pos)) +#define USBHS_HSTISR_DMA_5_Pos _U_(29) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Position */ +#define USBHS_HSTISR_DMA_5_Msk (_U_(0x1) << USBHS_HSTISR_DMA_5_Pos) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Mask */ +#define USBHS_HSTISR_DMA_5(value) (USBHS_HSTISR_DMA_5_Msk & ((value) << USBHS_HSTISR_DMA_5_Pos)) +#define USBHS_HSTISR_DMA_6_Pos _U_(30) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Position */ +#define USBHS_HSTISR_DMA_6_Msk (_U_(0x1) << USBHS_HSTISR_DMA_6_Pos) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Mask */ +#define USBHS_HSTISR_DMA_6(value) (USBHS_HSTISR_DMA_6_Msk & ((value) << USBHS_HSTISR_DMA_6_Pos)) +#define USBHS_HSTISR_DMA_7_Pos _U_(31) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Position */ +#define USBHS_HSTISR_DMA_7_Msk (_U_(0x1) << USBHS_HSTISR_DMA_7_Pos) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Mask */ +#define USBHS_HSTISR_DMA_7(value) (USBHS_HSTISR_DMA_7_Msk & ((value) << USBHS_HSTISR_DMA_7_Pos)) +#define USBHS_HSTISR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTISR) Register Mask */ + +#define USBHS_HSTISR_PEP__Pos _U_(8) /**< (USBHS_HSTISR Position) Pipe x Interrupt */ +#define USBHS_HSTISR_PEP__Msk (_U_(0x3FF) << USBHS_HSTISR_PEP__Pos) /**< (USBHS_HSTISR Mask) PEP_ */ +#define USBHS_HSTISR_PEP_(value) (USBHS_HSTISR_PEP__Msk & ((value) << USBHS_HSTISR_PEP__Pos)) +#define USBHS_HSTISR_DMA__Pos _U_(25) /**< (USBHS_HSTISR Position) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA__Msk (_U_(0x7F) << USBHS_HSTISR_DMA__Pos) /**< (USBHS_HSTISR Mask) DMA_ */ +#define USBHS_HSTISR_DMA_(value) (USBHS_HSTISR_DMA__Msk & ((value) << USBHS_HSTISR_DMA__Pos)) + +/* -------- USBHS_HSTICR : (USBHS Offset: 0x408) ( /W 32) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC_Pos _U_(0) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Position */ +#define USBHS_HSTICR_DCONNIC_Msk (_U_(0x1) << USBHS_HSTICR_DCONNIC_Pos) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Mask */ +#define USBHS_HSTICR_DCONNIC(value) (USBHS_HSTICR_DCONNIC_Msk & ((value) << USBHS_HSTICR_DCONNIC_Pos)) +#define USBHS_HSTICR_DDISCIC_Pos _U_(1) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Position */ +#define USBHS_HSTICR_DDISCIC_Msk (_U_(0x1) << USBHS_HSTICR_DDISCIC_Pos) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Mask */ +#define USBHS_HSTICR_DDISCIC(value) (USBHS_HSTICR_DDISCIC_Msk & ((value) << USBHS_HSTICR_DDISCIC_Pos)) +#define USBHS_HSTICR_RSTIC_Pos _U_(2) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSTIC_Msk (_U_(0x1) << USBHS_HSTICR_RSTIC_Pos) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSTIC(value) (USBHS_HSTICR_RSTIC_Msk & ((value) << USBHS_HSTICR_RSTIC_Pos)) +#define USBHS_HSTICR_RSMEDIC_Pos _U_(3) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Position */ +#define USBHS_HSTICR_RSMEDIC_Msk (_U_(0x1) << USBHS_HSTICR_RSMEDIC_Pos) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Mask */ +#define USBHS_HSTICR_RSMEDIC(value) (USBHS_HSTICR_RSMEDIC_Msk & ((value) << USBHS_HSTICR_RSMEDIC_Pos)) +#define USBHS_HSTICR_RXRSMIC_Pos _U_(4) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Position */ +#define USBHS_HSTICR_RXRSMIC_Msk (_U_(0x1) << USBHS_HSTICR_RXRSMIC_Pos) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Mask */ +#define USBHS_HSTICR_RXRSMIC(value) (USBHS_HSTICR_RXRSMIC_Msk & ((value) << USBHS_HSTICR_RXRSMIC_Pos)) +#define USBHS_HSTICR_HSOFIC_Pos _U_(5) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Position */ +#define USBHS_HSTICR_HSOFIC_Msk (_U_(0x1) << USBHS_HSTICR_HSOFIC_Pos) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Mask */ +#define USBHS_HSTICR_HSOFIC(value) (USBHS_HSTICR_HSOFIC_Msk & ((value) << USBHS_HSTICR_HSOFIC_Pos)) +#define USBHS_HSTICR_HWUPIC_Pos _U_(6) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Position */ +#define USBHS_HSTICR_HWUPIC_Msk (_U_(0x1) << USBHS_HSTICR_HWUPIC_Pos) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Mask */ +#define USBHS_HSTICR_HWUPIC(value) (USBHS_HSTICR_HWUPIC_Msk & ((value) << USBHS_HSTICR_HWUPIC_Pos)) +#define USBHS_HSTICR_Msk _U_(0x0000007F) /**< (USBHS_HSTICR) Register Mask */ + + +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x40C) ( /W 32) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS_Pos _U_(0) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Position */ +#define USBHS_HSTIFR_DCONNIS_Msk (_U_(0x1) << USBHS_HSTIFR_DCONNIS_Pos) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Mask */ +#define USBHS_HSTIFR_DCONNIS(value) (USBHS_HSTIFR_DCONNIS_Msk & ((value) << USBHS_HSTIFR_DCONNIS_Pos)) +#define USBHS_HSTIFR_DDISCIS_Pos _U_(1) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Position */ +#define USBHS_HSTIFR_DDISCIS_Msk (_U_(0x1) << USBHS_HSTIFR_DDISCIS_Pos) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Mask */ +#define USBHS_HSTIFR_DDISCIS(value) (USBHS_HSTIFR_DDISCIS_Msk & ((value) << USBHS_HSTIFR_DDISCIS_Pos)) +#define USBHS_HSTIFR_RSTIS_Pos _U_(2) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSTIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSTIS_Pos) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSTIS(value) (USBHS_HSTIFR_RSTIS_Msk & ((value) << USBHS_HSTIFR_RSTIS_Pos)) +#define USBHS_HSTIFR_RSMEDIS_Pos _U_(3) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Position */ +#define USBHS_HSTIFR_RSMEDIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSMEDIS_Pos) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Mask */ +#define USBHS_HSTIFR_RSMEDIS(value) (USBHS_HSTIFR_RSMEDIS_Msk & ((value) << USBHS_HSTIFR_RSMEDIS_Pos)) +#define USBHS_HSTIFR_RXRSMIS_Pos _U_(4) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Position */ +#define USBHS_HSTIFR_RXRSMIS_Msk (_U_(0x1) << USBHS_HSTIFR_RXRSMIS_Pos) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Mask */ +#define USBHS_HSTIFR_RXRSMIS(value) (USBHS_HSTIFR_RXRSMIS_Msk & ((value) << USBHS_HSTIFR_RXRSMIS_Pos)) +#define USBHS_HSTIFR_HSOFIS_Pos _U_(5) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Position */ +#define USBHS_HSTIFR_HSOFIS_Msk (_U_(0x1) << USBHS_HSTIFR_HSOFIS_Pos) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Mask */ +#define USBHS_HSTIFR_HSOFIS(value) (USBHS_HSTIFR_HSOFIS_Msk & ((value) << USBHS_HSTIFR_HSOFIS_Pos)) +#define USBHS_HSTIFR_HWUPIS_Pos _U_(6) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Position */ +#define USBHS_HSTIFR_HWUPIS_Msk (_U_(0x1) << USBHS_HSTIFR_HWUPIS_Pos) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Mask */ +#define USBHS_HSTIFR_HWUPIS(value) (USBHS_HSTIFR_HWUPIS_Msk & ((value) << USBHS_HSTIFR_HWUPIS_Pos)) +#define USBHS_HSTIFR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_1_Pos) /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_1(value) (USBHS_HSTIFR_DMA_1_Msk & ((value) << USBHS_HSTIFR_DMA_1_Pos)) +#define USBHS_HSTIFR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_2_Pos) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_2(value) (USBHS_HSTIFR_DMA_2_Msk & ((value) << USBHS_HSTIFR_DMA_2_Pos)) +#define USBHS_HSTIFR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_3_Pos) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_3(value) (USBHS_HSTIFR_DMA_3_Msk & ((value) << USBHS_HSTIFR_DMA_3_Pos)) +#define USBHS_HSTIFR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_4_Pos) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_4(value) (USBHS_HSTIFR_DMA_4_Msk & ((value) << USBHS_HSTIFR_DMA_4_Pos)) +#define USBHS_HSTIFR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_5_Pos) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_5(value) (USBHS_HSTIFR_DMA_5_Msk & ((value) << USBHS_HSTIFR_DMA_5_Pos)) +#define USBHS_HSTIFR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_6_Pos) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_6(value) (USBHS_HSTIFR_DMA_6_Msk & ((value) << USBHS_HSTIFR_DMA_6_Pos)) +#define USBHS_HSTIFR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Position */ +#define USBHS_HSTIFR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_7_Pos) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Mask */ +#define USBHS_HSTIFR_DMA_7(value) (USBHS_HSTIFR_DMA_7_Msk & ((value) << USBHS_HSTIFR_DMA_7_Pos)) +#define USBHS_HSTIFR_Msk _U_(0xFE00007F) /**< (USBHS_HSTIFR) Register Mask */ + +#define USBHS_HSTIFR_DMA__Pos _U_(25) /**< (USBHS_HSTIFR Position) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA__Msk (_U_(0x7F) << USBHS_HSTIFR_DMA__Pos) /**< (USBHS_HSTIFR Mask) DMA_ */ +#define USBHS_HSTIFR_DMA_(value) (USBHS_HSTIFR_DMA__Msk & ((value) << USBHS_HSTIFR_DMA__Pos)) + +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x410) ( R/ 32) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE_Pos _U_(0) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIMR_DCONNIE_Msk (_U_(0x1) << USBHS_HSTIMR_DCONNIE_Pos) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DCONNIE(value) (USBHS_HSTIMR_DCONNIE_Msk & ((value) << USBHS_HSTIMR_DCONNIE_Pos)) +#define USBHS_HSTIMR_DDISCIE_Pos _U_(1) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIMR_DDISCIE_Msk (_U_(0x1) << USBHS_HSTIMR_DDISCIE_Pos) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIMR_DDISCIE(value) (USBHS_HSTIMR_DDISCIE_Msk & ((value) << USBHS_HSTIMR_DDISCIE_Pos)) +#define USBHS_HSTIMR_RSTIE_Pos _U_(2) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSTIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSTIE_Pos) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSTIE(value) (USBHS_HSTIMR_RSTIE_Msk & ((value) << USBHS_HSTIMR_RSTIE_Pos)) +#define USBHS_HSTIMR_RSMEDIE_Pos _U_(3) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIMR_RSMEDIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSMEDIE_Pos) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIMR_RSMEDIE(value) (USBHS_HSTIMR_RSMEDIE_Msk & ((value) << USBHS_HSTIMR_RSMEDIE_Pos)) +#define USBHS_HSTIMR_RXRSMIE_Pos _U_(4) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIMR_RXRSMIE_Msk (_U_(0x1) << USBHS_HSTIMR_RXRSMIE_Pos) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIMR_RXRSMIE(value) (USBHS_HSTIMR_RXRSMIE_Msk & ((value) << USBHS_HSTIMR_RXRSMIE_Pos)) +#define USBHS_HSTIMR_HSOFIE_Pos _U_(5) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIMR_HSOFIE_Msk (_U_(0x1) << USBHS_HSTIMR_HSOFIE_Pos) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIMR_HSOFIE(value) (USBHS_HSTIMR_HSOFIE_Msk & ((value) << USBHS_HSTIMR_HSOFIE_Pos)) +#define USBHS_HSTIMR_HWUPIE_Pos _U_(6) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIMR_HWUPIE_Msk (_U_(0x1) << USBHS_HSTIMR_HWUPIE_Pos) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIMR_HWUPIE(value) (USBHS_HSTIMR_HWUPIE_Msk & ((value) << USBHS_HSTIMR_HWUPIE_Pos)) +#define USBHS_HSTIMR_PEP_0_Pos _U_(8) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_0_Pos) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_0(value) (USBHS_HSTIMR_PEP_0_Msk & ((value) << USBHS_HSTIMR_PEP_0_Pos)) +#define USBHS_HSTIMR_PEP_1_Pos _U_(9) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_1_Pos) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_1(value) (USBHS_HSTIMR_PEP_1_Msk & ((value) << USBHS_HSTIMR_PEP_1_Pos)) +#define USBHS_HSTIMR_PEP_2_Pos _U_(10) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_2_Pos) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_2(value) (USBHS_HSTIMR_PEP_2_Msk & ((value) << USBHS_HSTIMR_PEP_2_Pos)) +#define USBHS_HSTIMR_PEP_3_Pos _U_(11) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_3_Pos) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_3(value) (USBHS_HSTIMR_PEP_3_Msk & ((value) << USBHS_HSTIMR_PEP_3_Pos)) +#define USBHS_HSTIMR_PEP_4_Pos _U_(12) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_4_Pos) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_4(value) (USBHS_HSTIMR_PEP_4_Msk & ((value) << USBHS_HSTIMR_PEP_4_Pos)) +#define USBHS_HSTIMR_PEP_5_Pos _U_(13) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_5_Pos) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_5(value) (USBHS_HSTIMR_PEP_5_Msk & ((value) << USBHS_HSTIMR_PEP_5_Pos)) +#define USBHS_HSTIMR_PEP_6_Pos _U_(14) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_6_Pos) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_6(value) (USBHS_HSTIMR_PEP_6_Msk & ((value) << USBHS_HSTIMR_PEP_6_Pos)) +#define USBHS_HSTIMR_PEP_7_Pos _U_(15) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_7_Pos) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_7(value) (USBHS_HSTIMR_PEP_7_Msk & ((value) << USBHS_HSTIMR_PEP_7_Pos)) +#define USBHS_HSTIMR_PEP_8_Pos _U_(16) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_8_Pos) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_8(value) (USBHS_HSTIMR_PEP_8_Msk & ((value) << USBHS_HSTIMR_PEP_8_Pos)) +#define USBHS_HSTIMR_PEP_9_Pos _U_(17) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIMR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_9_Pos) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIMR_PEP_9(value) (USBHS_HSTIMR_PEP_9_Msk & ((value) << USBHS_HSTIMR_PEP_9_Pos)) +#define USBHS_HSTIMR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_1_Pos) /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_1(value) (USBHS_HSTIMR_DMA_1_Msk & ((value) << USBHS_HSTIMR_DMA_1_Pos)) +#define USBHS_HSTIMR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_2_Pos) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_2(value) (USBHS_HSTIMR_DMA_2_Msk & ((value) << USBHS_HSTIMR_DMA_2_Pos)) +#define USBHS_HSTIMR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_3_Pos) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_3(value) (USBHS_HSTIMR_DMA_3_Msk & ((value) << USBHS_HSTIMR_DMA_3_Pos)) +#define USBHS_HSTIMR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_4_Pos) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_4(value) (USBHS_HSTIMR_DMA_4_Msk & ((value) << USBHS_HSTIMR_DMA_4_Pos)) +#define USBHS_HSTIMR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_5_Pos) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_5(value) (USBHS_HSTIMR_DMA_5_Msk & ((value) << USBHS_HSTIMR_DMA_5_Pos)) +#define USBHS_HSTIMR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_6_Pos) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_6(value) (USBHS_HSTIMR_DMA_6_Msk & ((value) << USBHS_HSTIMR_DMA_6_Pos)) +#define USBHS_HSTIMR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIMR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_7_Pos) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIMR_DMA_7(value) (USBHS_HSTIMR_DMA_7_Msk & ((value) << USBHS_HSTIMR_DMA_7_Pos)) +#define USBHS_HSTIMR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIMR) Register Mask */ + +#define USBHS_HSTIMR_PEP__Pos _U_(8) /**< (USBHS_HSTIMR Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIMR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIMR_PEP__Pos) /**< (USBHS_HSTIMR Mask) PEP_ */ +#define USBHS_HSTIMR_PEP_(value) (USBHS_HSTIMR_PEP__Msk & ((value) << USBHS_HSTIMR_PEP__Pos)) +#define USBHS_HSTIMR_DMA__Pos _U_(25) /**< (USBHS_HSTIMR Position) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA__Msk (_U_(0x7F) << USBHS_HSTIMR_DMA__Pos) /**< (USBHS_HSTIMR Mask) DMA_ */ +#define USBHS_HSTIMR_DMA_(value) (USBHS_HSTIMR_DMA__Msk & ((value) << USBHS_HSTIMR_DMA__Pos)) + +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x414) ( /W 32) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC_Pos _U_(0) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Position */ +#define USBHS_HSTIDR_DCONNIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DCONNIEC_Pos) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DCONNIEC(value) (USBHS_HSTIDR_DCONNIEC_Msk & ((value) << USBHS_HSTIDR_DCONNIEC_Pos)) +#define USBHS_HSTIDR_DDISCIEC_Pos _U_(1) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Position */ +#define USBHS_HSTIDR_DDISCIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DDISCIEC_Pos) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Mask */ +#define USBHS_HSTIDR_DDISCIEC(value) (USBHS_HSTIDR_DDISCIEC_Msk & ((value) << USBHS_HSTIDR_DDISCIEC_Pos)) +#define USBHS_HSTIDR_RSTIEC_Pos _U_(2) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSTIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSTIEC_Pos) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSTIEC(value) (USBHS_HSTIDR_RSTIEC_Msk & ((value) << USBHS_HSTIDR_RSTIEC_Pos)) +#define USBHS_HSTIDR_RSMEDIEC_Pos _U_(3) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Position */ +#define USBHS_HSTIDR_RSMEDIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSMEDIEC_Pos) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ +#define USBHS_HSTIDR_RSMEDIEC(value) (USBHS_HSTIDR_RSMEDIEC_Msk & ((value) << USBHS_HSTIDR_RSMEDIEC_Pos)) +#define USBHS_HSTIDR_RXRSMIEC_Pos _U_(4) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Position */ +#define USBHS_HSTIDR_RXRSMIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RXRSMIEC_Pos) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Mask */ +#define USBHS_HSTIDR_RXRSMIEC(value) (USBHS_HSTIDR_RXRSMIEC_Msk & ((value) << USBHS_HSTIDR_RXRSMIEC_Pos)) +#define USBHS_HSTIDR_HSOFIEC_Pos _U_(5) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Position */ +#define USBHS_HSTIDR_HSOFIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HSOFIEC_Pos) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Mask */ +#define USBHS_HSTIDR_HSOFIEC(value) (USBHS_HSTIDR_HSOFIEC_Msk & ((value) << USBHS_HSTIDR_HSOFIEC_Pos)) +#define USBHS_HSTIDR_HWUPIEC_Pos _U_(6) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Position */ +#define USBHS_HSTIDR_HWUPIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HWUPIEC_Pos) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Mask */ +#define USBHS_HSTIDR_HWUPIEC(value) (USBHS_HSTIDR_HWUPIEC_Msk & ((value) << USBHS_HSTIDR_HWUPIEC_Pos)) +#define USBHS_HSTIDR_PEP_0_Pos _U_(8) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_0_Pos) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_0(value) (USBHS_HSTIDR_PEP_0_Msk & ((value) << USBHS_HSTIDR_PEP_0_Pos)) +#define USBHS_HSTIDR_PEP_1_Pos _U_(9) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_1_Pos) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_1(value) (USBHS_HSTIDR_PEP_1_Msk & ((value) << USBHS_HSTIDR_PEP_1_Pos)) +#define USBHS_HSTIDR_PEP_2_Pos _U_(10) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_2_Pos) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_2(value) (USBHS_HSTIDR_PEP_2_Msk & ((value) << USBHS_HSTIDR_PEP_2_Pos)) +#define USBHS_HSTIDR_PEP_3_Pos _U_(11) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_3_Pos) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_3(value) (USBHS_HSTIDR_PEP_3_Msk & ((value) << USBHS_HSTIDR_PEP_3_Pos)) +#define USBHS_HSTIDR_PEP_4_Pos _U_(12) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_4_Pos) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_4(value) (USBHS_HSTIDR_PEP_4_Msk & ((value) << USBHS_HSTIDR_PEP_4_Pos)) +#define USBHS_HSTIDR_PEP_5_Pos _U_(13) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_5_Pos) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_5(value) (USBHS_HSTIDR_PEP_5_Msk & ((value) << USBHS_HSTIDR_PEP_5_Pos)) +#define USBHS_HSTIDR_PEP_6_Pos _U_(14) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_6_Pos) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_6(value) (USBHS_HSTIDR_PEP_6_Msk & ((value) << USBHS_HSTIDR_PEP_6_Pos)) +#define USBHS_HSTIDR_PEP_7_Pos _U_(15) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_7_Pos) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_7(value) (USBHS_HSTIDR_PEP_7_Msk & ((value) << USBHS_HSTIDR_PEP_7_Pos)) +#define USBHS_HSTIDR_PEP_8_Pos _U_(16) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_8_Pos) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_8(value) (USBHS_HSTIDR_PEP_8_Msk & ((value) << USBHS_HSTIDR_PEP_8_Pos)) +#define USBHS_HSTIDR_PEP_9_Pos _U_(17) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Position */ +#define USBHS_HSTIDR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_9_Pos) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Mask */ +#define USBHS_HSTIDR_PEP_9(value) (USBHS_HSTIDR_PEP_9_Msk & ((value) << USBHS_HSTIDR_PEP_9_Pos)) +#define USBHS_HSTIDR_DMA_1_Pos _U_(25) /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_1_Pos) /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_1(value) (USBHS_HSTIDR_DMA_1_Msk & ((value) << USBHS_HSTIDR_DMA_1_Pos)) +#define USBHS_HSTIDR_DMA_2_Pos _U_(26) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_2_Pos) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_2(value) (USBHS_HSTIDR_DMA_2_Msk & ((value) << USBHS_HSTIDR_DMA_2_Pos)) +#define USBHS_HSTIDR_DMA_3_Pos _U_(27) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_3_Pos) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_3(value) (USBHS_HSTIDR_DMA_3_Msk & ((value) << USBHS_HSTIDR_DMA_3_Pos)) +#define USBHS_HSTIDR_DMA_4_Pos _U_(28) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_4_Pos) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_4(value) (USBHS_HSTIDR_DMA_4_Msk & ((value) << USBHS_HSTIDR_DMA_4_Pos)) +#define USBHS_HSTIDR_DMA_5_Pos _U_(29) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_5_Pos) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_5(value) (USBHS_HSTIDR_DMA_5_Msk & ((value) << USBHS_HSTIDR_DMA_5_Pos)) +#define USBHS_HSTIDR_DMA_6_Pos _U_(30) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_6_Pos) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_6(value) (USBHS_HSTIDR_DMA_6_Msk & ((value) << USBHS_HSTIDR_DMA_6_Pos)) +#define USBHS_HSTIDR_DMA_7_Pos _U_(31) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Position */ +#define USBHS_HSTIDR_DMA_7_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_7_Pos) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Mask */ +#define USBHS_HSTIDR_DMA_7(value) (USBHS_HSTIDR_DMA_7_Msk & ((value) << USBHS_HSTIDR_DMA_7_Pos)) +#define USBHS_HSTIDR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIDR) Register Mask */ + +#define USBHS_HSTIDR_PEP__Pos _U_(8) /**< (USBHS_HSTIDR Position) Pipe x Interrupt Disable */ +#define USBHS_HSTIDR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIDR_PEP__Pos) /**< (USBHS_HSTIDR Mask) PEP_ */ +#define USBHS_HSTIDR_PEP_(value) (USBHS_HSTIDR_PEP__Msk & ((value) << USBHS_HSTIDR_PEP__Pos)) +#define USBHS_HSTIDR_DMA__Pos _U_(25) /**< (USBHS_HSTIDR Position) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA__Msk (_U_(0x7F) << USBHS_HSTIDR_DMA__Pos) /**< (USBHS_HSTIDR Mask) DMA_ */ +#define USBHS_HSTIDR_DMA_(value) (USBHS_HSTIDR_DMA__Msk & ((value) << USBHS_HSTIDR_DMA__Pos)) + +/* -------- USBHS_HSTIER : (USBHS Offset: 0x418) ( /W 32) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES_Pos _U_(0) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Position */ +#define USBHS_HSTIER_DCONNIES_Msk (_U_(0x1) << USBHS_HSTIER_DCONNIES_Pos) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Mask */ +#define USBHS_HSTIER_DCONNIES(value) (USBHS_HSTIER_DCONNIES_Msk & ((value) << USBHS_HSTIER_DCONNIES_Pos)) +#define USBHS_HSTIER_DDISCIES_Pos _U_(1) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Position */ +#define USBHS_HSTIER_DDISCIES_Msk (_U_(0x1) << USBHS_HSTIER_DDISCIES_Pos) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Mask */ +#define USBHS_HSTIER_DDISCIES(value) (USBHS_HSTIER_DDISCIES_Msk & ((value) << USBHS_HSTIER_DDISCIES_Pos)) +#define USBHS_HSTIER_RSTIES_Pos _U_(2) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSTIES_Msk (_U_(0x1) << USBHS_HSTIER_RSTIES_Pos) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSTIES(value) (USBHS_HSTIER_RSTIES_Msk & ((value) << USBHS_HSTIER_RSTIES_Pos)) +#define USBHS_HSTIER_RSMEDIES_Pos _U_(3) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Position */ +#define USBHS_HSTIER_RSMEDIES_Msk (_U_(0x1) << USBHS_HSTIER_RSMEDIES_Pos) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Mask */ +#define USBHS_HSTIER_RSMEDIES(value) (USBHS_HSTIER_RSMEDIES_Msk & ((value) << USBHS_HSTIER_RSMEDIES_Pos)) +#define USBHS_HSTIER_RXRSMIES_Pos _U_(4) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Position */ +#define USBHS_HSTIER_RXRSMIES_Msk (_U_(0x1) << USBHS_HSTIER_RXRSMIES_Pos) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Mask */ +#define USBHS_HSTIER_RXRSMIES(value) (USBHS_HSTIER_RXRSMIES_Msk & ((value) << USBHS_HSTIER_RXRSMIES_Pos)) +#define USBHS_HSTIER_HSOFIES_Pos _U_(5) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Position */ +#define USBHS_HSTIER_HSOFIES_Msk (_U_(0x1) << USBHS_HSTIER_HSOFIES_Pos) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Mask */ +#define USBHS_HSTIER_HSOFIES(value) (USBHS_HSTIER_HSOFIES_Msk & ((value) << USBHS_HSTIER_HSOFIES_Pos)) +#define USBHS_HSTIER_HWUPIES_Pos _U_(6) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Position */ +#define USBHS_HSTIER_HWUPIES_Msk (_U_(0x1) << USBHS_HSTIER_HWUPIES_Pos) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Mask */ +#define USBHS_HSTIER_HWUPIES(value) (USBHS_HSTIER_HWUPIES_Msk & ((value) << USBHS_HSTIER_HWUPIES_Pos)) +#define USBHS_HSTIER_PEP_0_Pos _U_(8) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_0_Msk (_U_(0x1) << USBHS_HSTIER_PEP_0_Pos) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_0(value) (USBHS_HSTIER_PEP_0_Msk & ((value) << USBHS_HSTIER_PEP_0_Pos)) +#define USBHS_HSTIER_PEP_1_Pos _U_(9) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_1_Msk (_U_(0x1) << USBHS_HSTIER_PEP_1_Pos) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_1(value) (USBHS_HSTIER_PEP_1_Msk & ((value) << USBHS_HSTIER_PEP_1_Pos)) +#define USBHS_HSTIER_PEP_2_Pos _U_(10) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_2_Msk (_U_(0x1) << USBHS_HSTIER_PEP_2_Pos) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_2(value) (USBHS_HSTIER_PEP_2_Msk & ((value) << USBHS_HSTIER_PEP_2_Pos)) +#define USBHS_HSTIER_PEP_3_Pos _U_(11) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_3_Msk (_U_(0x1) << USBHS_HSTIER_PEP_3_Pos) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_3(value) (USBHS_HSTIER_PEP_3_Msk & ((value) << USBHS_HSTIER_PEP_3_Pos)) +#define USBHS_HSTIER_PEP_4_Pos _U_(12) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_4_Msk (_U_(0x1) << USBHS_HSTIER_PEP_4_Pos) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_4(value) (USBHS_HSTIER_PEP_4_Msk & ((value) << USBHS_HSTIER_PEP_4_Pos)) +#define USBHS_HSTIER_PEP_5_Pos _U_(13) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_5_Msk (_U_(0x1) << USBHS_HSTIER_PEP_5_Pos) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_5(value) (USBHS_HSTIER_PEP_5_Msk & ((value) << USBHS_HSTIER_PEP_5_Pos)) +#define USBHS_HSTIER_PEP_6_Pos _U_(14) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_6_Msk (_U_(0x1) << USBHS_HSTIER_PEP_6_Pos) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_6(value) (USBHS_HSTIER_PEP_6_Msk & ((value) << USBHS_HSTIER_PEP_6_Pos)) +#define USBHS_HSTIER_PEP_7_Pos _U_(15) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_7_Msk (_U_(0x1) << USBHS_HSTIER_PEP_7_Pos) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_7(value) (USBHS_HSTIER_PEP_7_Msk & ((value) << USBHS_HSTIER_PEP_7_Pos)) +#define USBHS_HSTIER_PEP_8_Pos _U_(16) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_8_Msk (_U_(0x1) << USBHS_HSTIER_PEP_8_Pos) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_8(value) (USBHS_HSTIER_PEP_8_Msk & ((value) << USBHS_HSTIER_PEP_8_Pos)) +#define USBHS_HSTIER_PEP_9_Pos _U_(17) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Position */ +#define USBHS_HSTIER_PEP_9_Msk (_U_(0x1) << USBHS_HSTIER_PEP_9_Pos) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Mask */ +#define USBHS_HSTIER_PEP_9(value) (USBHS_HSTIER_PEP_9_Msk & ((value) << USBHS_HSTIER_PEP_9_Pos)) +#define USBHS_HSTIER_DMA_1_Pos _U_(25) /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_1_Msk (_U_(0x1) << USBHS_HSTIER_DMA_1_Pos) /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_1(value) (USBHS_HSTIER_DMA_1_Msk & ((value) << USBHS_HSTIER_DMA_1_Pos)) +#define USBHS_HSTIER_DMA_2_Pos _U_(26) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_2_Msk (_U_(0x1) << USBHS_HSTIER_DMA_2_Pos) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_2(value) (USBHS_HSTIER_DMA_2_Msk & ((value) << USBHS_HSTIER_DMA_2_Pos)) +#define USBHS_HSTIER_DMA_3_Pos _U_(27) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_3_Msk (_U_(0x1) << USBHS_HSTIER_DMA_3_Pos) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_3(value) (USBHS_HSTIER_DMA_3_Msk & ((value) << USBHS_HSTIER_DMA_3_Pos)) +#define USBHS_HSTIER_DMA_4_Pos _U_(28) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_4_Msk (_U_(0x1) << USBHS_HSTIER_DMA_4_Pos) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_4(value) (USBHS_HSTIER_DMA_4_Msk & ((value) << USBHS_HSTIER_DMA_4_Pos)) +#define USBHS_HSTIER_DMA_5_Pos _U_(29) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_5_Msk (_U_(0x1) << USBHS_HSTIER_DMA_5_Pos) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_5(value) (USBHS_HSTIER_DMA_5_Msk & ((value) << USBHS_HSTIER_DMA_5_Pos)) +#define USBHS_HSTIER_DMA_6_Pos _U_(30) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_6_Msk (_U_(0x1) << USBHS_HSTIER_DMA_6_Pos) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_6(value) (USBHS_HSTIER_DMA_6_Msk & ((value) << USBHS_HSTIER_DMA_6_Pos)) +#define USBHS_HSTIER_DMA_7_Pos _U_(31) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Position */ +#define USBHS_HSTIER_DMA_7_Msk (_U_(0x1) << USBHS_HSTIER_DMA_7_Pos) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Mask */ +#define USBHS_HSTIER_DMA_7(value) (USBHS_HSTIER_DMA_7_Msk & ((value) << USBHS_HSTIER_DMA_7_Pos)) +#define USBHS_HSTIER_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIER) Register Mask */ + +#define USBHS_HSTIER_PEP__Pos _U_(8) /**< (USBHS_HSTIER Position) Pipe x Interrupt Enable */ +#define USBHS_HSTIER_PEP__Msk (_U_(0x3FF) << USBHS_HSTIER_PEP__Pos) /**< (USBHS_HSTIER Mask) PEP_ */ +#define USBHS_HSTIER_PEP_(value) (USBHS_HSTIER_PEP__Msk & ((value) << USBHS_HSTIER_PEP__Pos)) +#define USBHS_HSTIER_DMA__Pos _U_(25) /**< (USBHS_HSTIER Position) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA__Msk (_U_(0x7F) << USBHS_HSTIER_DMA__Pos) /**< (USBHS_HSTIER Mask) DMA_ */ +#define USBHS_HSTIER_DMA_(value) (USBHS_HSTIER_DMA__Msk & ((value) << USBHS_HSTIER_DMA__Pos)) + +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x41C) (R/W 32) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0_Pos _U_(0) /**< (USBHS_HSTPIP) Pipe 0 Enable Position */ +#define USBHS_HSTPIP_PEN0_Msk (_U_(0x1) << USBHS_HSTPIP_PEN0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Enable Mask */ +#define USBHS_HSTPIP_PEN0(value) (USBHS_HSTPIP_PEN0_Msk & ((value) << USBHS_HSTPIP_PEN0_Pos)) +#define USBHS_HSTPIP_PEN1_Pos _U_(1) /**< (USBHS_HSTPIP) Pipe 1 Enable Position */ +#define USBHS_HSTPIP_PEN1_Msk (_U_(0x1) << USBHS_HSTPIP_PEN1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Enable Mask */ +#define USBHS_HSTPIP_PEN1(value) (USBHS_HSTPIP_PEN1_Msk & ((value) << USBHS_HSTPIP_PEN1_Pos)) +#define USBHS_HSTPIP_PEN2_Pos _U_(2) /**< (USBHS_HSTPIP) Pipe 2 Enable Position */ +#define USBHS_HSTPIP_PEN2_Msk (_U_(0x1) << USBHS_HSTPIP_PEN2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Enable Mask */ +#define USBHS_HSTPIP_PEN2(value) (USBHS_HSTPIP_PEN2_Msk & ((value) << USBHS_HSTPIP_PEN2_Pos)) +#define USBHS_HSTPIP_PEN3_Pos _U_(3) /**< (USBHS_HSTPIP) Pipe 3 Enable Position */ +#define USBHS_HSTPIP_PEN3_Msk (_U_(0x1) << USBHS_HSTPIP_PEN3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Enable Mask */ +#define USBHS_HSTPIP_PEN3(value) (USBHS_HSTPIP_PEN3_Msk & ((value) << USBHS_HSTPIP_PEN3_Pos)) +#define USBHS_HSTPIP_PEN4_Pos _U_(4) /**< (USBHS_HSTPIP) Pipe 4 Enable Position */ +#define USBHS_HSTPIP_PEN4_Msk (_U_(0x1) << USBHS_HSTPIP_PEN4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Enable Mask */ +#define USBHS_HSTPIP_PEN4(value) (USBHS_HSTPIP_PEN4_Msk & ((value) << USBHS_HSTPIP_PEN4_Pos)) +#define USBHS_HSTPIP_PEN5_Pos _U_(5) /**< (USBHS_HSTPIP) Pipe 5 Enable Position */ +#define USBHS_HSTPIP_PEN5_Msk (_U_(0x1) << USBHS_HSTPIP_PEN5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Enable Mask */ +#define USBHS_HSTPIP_PEN5(value) (USBHS_HSTPIP_PEN5_Msk & ((value) << USBHS_HSTPIP_PEN5_Pos)) +#define USBHS_HSTPIP_PEN6_Pos _U_(6) /**< (USBHS_HSTPIP) Pipe 6 Enable Position */ +#define USBHS_HSTPIP_PEN6_Msk (_U_(0x1) << USBHS_HSTPIP_PEN6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Enable Mask */ +#define USBHS_HSTPIP_PEN6(value) (USBHS_HSTPIP_PEN6_Msk & ((value) << USBHS_HSTPIP_PEN6_Pos)) +#define USBHS_HSTPIP_PEN7_Pos _U_(7) /**< (USBHS_HSTPIP) Pipe 7 Enable Position */ +#define USBHS_HSTPIP_PEN7_Msk (_U_(0x1) << USBHS_HSTPIP_PEN7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Enable Mask */ +#define USBHS_HSTPIP_PEN7(value) (USBHS_HSTPIP_PEN7_Msk & ((value) << USBHS_HSTPIP_PEN7_Pos)) +#define USBHS_HSTPIP_PEN8_Pos _U_(8) /**< (USBHS_HSTPIP) Pipe 8 Enable Position */ +#define USBHS_HSTPIP_PEN8_Msk (_U_(0x1) << USBHS_HSTPIP_PEN8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Enable Mask */ +#define USBHS_HSTPIP_PEN8(value) (USBHS_HSTPIP_PEN8_Msk & ((value) << USBHS_HSTPIP_PEN8_Pos)) +#define USBHS_HSTPIP_PRST0_Pos _U_(16) /**< (USBHS_HSTPIP) Pipe 0 Reset Position */ +#define USBHS_HSTPIP_PRST0_Msk (_U_(0x1) << USBHS_HSTPIP_PRST0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Reset Mask */ +#define USBHS_HSTPIP_PRST0(value) (USBHS_HSTPIP_PRST0_Msk & ((value) << USBHS_HSTPIP_PRST0_Pos)) +#define USBHS_HSTPIP_PRST1_Pos _U_(17) /**< (USBHS_HSTPIP) Pipe 1 Reset Position */ +#define USBHS_HSTPIP_PRST1_Msk (_U_(0x1) << USBHS_HSTPIP_PRST1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Reset Mask */ +#define USBHS_HSTPIP_PRST1(value) (USBHS_HSTPIP_PRST1_Msk & ((value) << USBHS_HSTPIP_PRST1_Pos)) +#define USBHS_HSTPIP_PRST2_Pos _U_(18) /**< (USBHS_HSTPIP) Pipe 2 Reset Position */ +#define USBHS_HSTPIP_PRST2_Msk (_U_(0x1) << USBHS_HSTPIP_PRST2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Reset Mask */ +#define USBHS_HSTPIP_PRST2(value) (USBHS_HSTPIP_PRST2_Msk & ((value) << USBHS_HSTPIP_PRST2_Pos)) +#define USBHS_HSTPIP_PRST3_Pos _U_(19) /**< (USBHS_HSTPIP) Pipe 3 Reset Position */ +#define USBHS_HSTPIP_PRST3_Msk (_U_(0x1) << USBHS_HSTPIP_PRST3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Reset Mask */ +#define USBHS_HSTPIP_PRST3(value) (USBHS_HSTPIP_PRST3_Msk & ((value) << USBHS_HSTPIP_PRST3_Pos)) +#define USBHS_HSTPIP_PRST4_Pos _U_(20) /**< (USBHS_HSTPIP) Pipe 4 Reset Position */ +#define USBHS_HSTPIP_PRST4_Msk (_U_(0x1) << USBHS_HSTPIP_PRST4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Reset Mask */ +#define USBHS_HSTPIP_PRST4(value) (USBHS_HSTPIP_PRST4_Msk & ((value) << USBHS_HSTPIP_PRST4_Pos)) +#define USBHS_HSTPIP_PRST5_Pos _U_(21) /**< (USBHS_HSTPIP) Pipe 5 Reset Position */ +#define USBHS_HSTPIP_PRST5_Msk (_U_(0x1) << USBHS_HSTPIP_PRST5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Reset Mask */ +#define USBHS_HSTPIP_PRST5(value) (USBHS_HSTPIP_PRST5_Msk & ((value) << USBHS_HSTPIP_PRST5_Pos)) +#define USBHS_HSTPIP_PRST6_Pos _U_(22) /**< (USBHS_HSTPIP) Pipe 6 Reset Position */ +#define USBHS_HSTPIP_PRST6_Msk (_U_(0x1) << USBHS_HSTPIP_PRST6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Reset Mask */ +#define USBHS_HSTPIP_PRST6(value) (USBHS_HSTPIP_PRST6_Msk & ((value) << USBHS_HSTPIP_PRST6_Pos)) +#define USBHS_HSTPIP_PRST7_Pos _U_(23) /**< (USBHS_HSTPIP) Pipe 7 Reset Position */ +#define USBHS_HSTPIP_PRST7_Msk (_U_(0x1) << USBHS_HSTPIP_PRST7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Reset Mask */ +#define USBHS_HSTPIP_PRST7(value) (USBHS_HSTPIP_PRST7_Msk & ((value) << USBHS_HSTPIP_PRST7_Pos)) +#define USBHS_HSTPIP_PRST8_Pos _U_(24) /**< (USBHS_HSTPIP) Pipe 8 Reset Position */ +#define USBHS_HSTPIP_PRST8_Msk (_U_(0x1) << USBHS_HSTPIP_PRST8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Reset Mask */ +#define USBHS_HSTPIP_PRST8(value) (USBHS_HSTPIP_PRST8_Msk & ((value) << USBHS_HSTPIP_PRST8_Pos)) +#define USBHS_HSTPIP_Msk _U_(0x01FF01FF) /**< (USBHS_HSTPIP) Register Mask */ + +#define USBHS_HSTPIP_PEN_Pos _U_(0) /**< (USBHS_HSTPIP Position) Pipe x Enable */ +#define USBHS_HSTPIP_PEN_Msk (_U_(0x1FF) << USBHS_HSTPIP_PEN_Pos) /**< (USBHS_HSTPIP Mask) PEN */ +#define USBHS_HSTPIP_PEN(value) (USBHS_HSTPIP_PEN_Msk & ((value) << USBHS_HSTPIP_PEN_Pos)) +#define USBHS_HSTPIP_PRST_Pos _U_(16) /**< (USBHS_HSTPIP Position) Pipe 8 Reset */ +#define USBHS_HSTPIP_PRST_Msk (_U_(0x1FF) << USBHS_HSTPIP_PRST_Pos) /**< (USBHS_HSTPIP Mask) PRST */ +#define USBHS_HSTPIP_PRST(value) (USBHS_HSTPIP_PRST_Msk & ((value) << USBHS_HSTPIP_PRST_Pos)) + +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos _U_(0) /**< (USBHS_HSTFNUM) Micro Frame Number Position */ +#define USBHS_HSTFNUM_MFNUM_Msk (_U_(0x7) << USBHS_HSTFNUM_MFNUM_Pos) /**< (USBHS_HSTFNUM) Micro Frame Number Mask */ +#define USBHS_HSTFNUM_MFNUM(value) (USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)) +#define USBHS_HSTFNUM_FNUM_Pos _U_(3) /**< (USBHS_HSTFNUM) Frame Number Position */ +#define USBHS_HSTFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_HSTFNUM_FNUM_Pos) /**< (USBHS_HSTFNUM) Frame Number Mask */ +#define USBHS_HSTFNUM_FNUM(value) (USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)) +#define USBHS_HSTFNUM_FLENHIGH_Pos _U_(16) /**< (USBHS_HSTFNUM) Frame Length Position */ +#define USBHS_HSTFNUM_FLENHIGH_Msk (_U_(0xFF) << USBHS_HSTFNUM_FLENHIGH_Pos) /**< (USBHS_HSTFNUM) Frame Length Mask */ +#define USBHS_HSTFNUM_FLENHIGH(value) (USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)) +#define USBHS_HSTFNUM_Msk _U_(0x00FF3FFF) /**< (USBHS_HSTFNUM) Register Mask */ + + +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos _U_(0) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP0_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP0(value) (USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)) +#define USBHS_HSTADDR1_HSTADDRP1_Pos _U_(8) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP1_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP1(value) (USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)) +#define USBHS_HSTADDR1_HSTADDRP2_Pos _U_(16) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP2_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP2(value) (USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)) +#define USBHS_HSTADDR1_HSTADDRP3_Pos _U_(24) /**< (USBHS_HSTADDR1) USB Host Address Position */ +#define USBHS_HSTADDR1_HSTADDRP3_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ +#define USBHS_HSTADDR1_HSTADDRP3(value) (USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)) +#define USBHS_HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR1) Register Mask */ + + +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos _U_(0) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP4_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP4(value) (USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)) +#define USBHS_HSTADDR2_HSTADDRP5_Pos _U_(8) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP5_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP5(value) (USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)) +#define USBHS_HSTADDR2_HSTADDRP6_Pos _U_(16) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP6_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP6(value) (USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)) +#define USBHS_HSTADDR2_HSTADDRP7_Pos _U_(24) /**< (USBHS_HSTADDR2) USB Host Address Position */ +#define USBHS_HSTADDR2_HSTADDRP7_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ +#define USBHS_HSTADDR2_HSTADDRP7(value) (USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)) +#define USBHS_HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR2) Register Mask */ + + +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x42C) (R/W 32) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos _U_(0) /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP8_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP8(value) (USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)) +#define USBHS_HSTADDR3_HSTADDRP9_Pos _U_(8) /**< (USBHS_HSTADDR3) USB Host Address Position */ +#define USBHS_HSTADDR3_HSTADDRP9_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ +#define USBHS_HSTADDR3_HSTADDRP9(value) (USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)) +#define USBHS_HSTADDR3_Msk _U_(0x00007F7F) /**< (USBHS_HSTADDR3) Register Mask */ + + +/* -------- USBHS_HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ +#define USBHS_HSTPIPCFG_ALLOC_Pos _U_(1) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Position */ +#define USBHS_HSTPIPCFG_ALLOC_Msk (_U_(0x1) << USBHS_HSTPIPCFG_ALLOC_Pos) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Mask */ +#define USBHS_HSTPIPCFG_ALLOC(value) (USBHS_HSTPIPCFG_ALLOC_Msk & ((value) << USBHS_HSTPIPCFG_ALLOC_Pos)) +#define USBHS_HSTPIPCFG_PBK_Pos _U_(2) /**< (USBHS_HSTPIPCFG) Pipe Banks Position */ +#define USBHS_HSTPIPCFG_PBK_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Pipe Banks Mask */ +#define USBHS_HSTPIPCFG_PBK(value) (USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)) +#define USBHS_HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_1_BANK (USBHS_HSTPIPCFG_PBK_1_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Single-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (USBHS_HSTPIPCFG_PBK_2_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Double-bank pipe Position */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (USBHS_HSTPIPCFG_PBK_3_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Triple-bank pipe Position */ +#define USBHS_HSTPIPCFG_PSIZE_Pos _U_(4) /**< (USBHS_HSTPIPCFG) Pipe Size Position */ +#define USBHS_HSTPIPCFG_PSIZE_Msk (_U_(0x7) << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Size Mask */ +#define USBHS_HSTPIPCFG_PSIZE(value) (USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_HSTPIPCFG) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_HSTPIPCFG) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_HSTPIPCFG) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_HSTPIPCFG) 1024 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 8 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 16 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 32 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 64 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 128 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 256 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 512 bytes Position */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 1024 bytes Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos _U_(8) /**< (USBHS_HSTPIPCFG) Pipe Token Position */ +#define USBHS_HSTPIPCFG_PTOKEN_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) Pipe Token Mask */ +#define USBHS_HSTPIPCFG_PTOKEN(value) (USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) OUT */ +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (USBHS_HSTPIPCFG_PTOKEN_SETUP_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) SETUP Position */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (USBHS_HSTPIPCFG_PTOKEN_IN_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) IN Position */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (USBHS_HSTPIPCFG_PTOKEN_OUT_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) OUT Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Pos _U_(10) /**< (USBHS_HSTPIPCFG) Automatic Switch Position */ +#define USBHS_HSTPIPCFG_AUTOSW_Msk (_U_(0x1) << USBHS_HSTPIPCFG_AUTOSW_Pos) /**< (USBHS_HSTPIPCFG) Automatic Switch Mask */ +#define USBHS_HSTPIPCFG_AUTOSW(value) (USBHS_HSTPIPCFG_AUTOSW_Msk & ((value) << USBHS_HSTPIPCFG_AUTOSW_Pos)) +#define USBHS_HSTPIPCFG_PTYPE_Pos _U_(12) /**< (USBHS_HSTPIPCFG) Pipe Type Position */ +#define USBHS_HSTPIPCFG_PTYPE_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Type Mask */ +#define USBHS_HSTPIPCFG_PTYPE(value) (USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)) +#define USBHS_HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) Interrupt */ +#define USBHS_HSTPIPCFG_PTYPE_CTRL (USBHS_HSTPIPCFG_PTYPE_CTRL_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Control Position */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (USBHS_HSTPIPCFG_PTYPE_ISO_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Isochronous Position */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (USBHS_HSTPIPCFG_PTYPE_BLK_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Bulk Position */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (USBHS_HSTPIPCFG_PTYPE_INTRPT_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Interrupt Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos _U_(16) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Position */ +#define USBHS_HSTPIPCFG_PEPNUM_Msk (_U_(0xF) << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Mask */ +#define USBHS_HSTPIPCFG_PEPNUM(value) (USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)) +#define USBHS_HSTPIPCFG_INTFRQ_Pos _U_(24) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Position */ +#define USBHS_HSTPIPCFG_INTFRQ_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ +#define USBHS_HSTPIPCFG_INTFRQ(value) (USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)) +#define USBHS_HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (USBHS_HSTPIPCFG) Register Mask */ + +/* CTRL_BULK mode */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos _U_(20) /**< (USBHS_HSTPIPCFG) Ping Enable Position */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk (_U_(0x1) << USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos) /**< (USBHS_HSTPIPCFG) Ping Enable Mask */ +#define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN(value) (USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk & ((value) << USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos)) +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos _U_(24) /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ +#define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(value) (USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos)) +#define USBHS_HSTPIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (USBHS_HSTPIPCFG_CTRL_BULK) Register Mask */ + + +/* -------- USBHS_HSTPIPISR : (USBHS Offset: 0x530) ( R/ 32) Host Pipe Status Register -------- */ +#define USBHS_HSTPIPISR_RXINI_Pos _U_(0) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Position */ +#define USBHS_HSTPIPISR_RXINI_Msk (_U_(0x1) << USBHS_HSTPIPISR_RXINI_Pos) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Mask */ +#define USBHS_HSTPIPISR_RXINI(value) (USBHS_HSTPIPISR_RXINI_Msk & ((value) << USBHS_HSTPIPISR_RXINI_Pos)) +#define USBHS_HSTPIPISR_TXOUTI_Pos _U_(1) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Position */ +#define USBHS_HSTPIPISR_TXOUTI_Msk (_U_(0x1) << USBHS_HSTPIPISR_TXOUTI_Pos) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Mask */ +#define USBHS_HSTPIPISR_TXOUTI(value) (USBHS_HSTPIPISR_TXOUTI_Msk & ((value) << USBHS_HSTPIPISR_TXOUTI_Pos)) +#define USBHS_HSTPIPISR_PERRI_Pos _U_(3) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Position */ +#define USBHS_HSTPIPISR_PERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_PERRI_Pos) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Mask */ +#define USBHS_HSTPIPISR_PERRI(value) (USBHS_HSTPIPISR_PERRI_Msk & ((value) << USBHS_HSTPIPISR_PERRI_Pos)) +#define USBHS_HSTPIPISR_NAKEDI_Pos _U_(4) /**< (USBHS_HSTPIPISR) NAKed Interrupt Position */ +#define USBHS_HSTPIPISR_NAKEDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_NAKEDI_Pos) /**< (USBHS_HSTPIPISR) NAKed Interrupt Mask */ +#define USBHS_HSTPIPISR_NAKEDI(value) (USBHS_HSTPIPISR_NAKEDI_Msk & ((value) << USBHS_HSTPIPISR_NAKEDI_Pos)) +#define USBHS_HSTPIPISR_OVERFI_Pos _U_(5) /**< (USBHS_HSTPIPISR) Overflow Interrupt Position */ +#define USBHS_HSTPIPISR_OVERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_OVERFI_Pos) /**< (USBHS_HSTPIPISR) Overflow Interrupt Mask */ +#define USBHS_HSTPIPISR_OVERFI(value) (USBHS_HSTPIPISR_OVERFI_Msk & ((value) << USBHS_HSTPIPISR_OVERFI_Pos)) +#define USBHS_HSTPIPISR_SHORTPACKETI_Pos _U_(7) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Position */ +#define USBHS_HSTPIPISR_SHORTPACKETI_Msk (_U_(0x1) << USBHS_HSTPIPISR_SHORTPACKETI_Pos) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Mask */ +#define USBHS_HSTPIPISR_SHORTPACKETI(value) (USBHS_HSTPIPISR_SHORTPACKETI_Msk & ((value) << USBHS_HSTPIPISR_SHORTPACKETI_Pos)) +#define USBHS_HSTPIPISR_DTSEQ_Pos _U_(8) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_Msk (_U_(0x3) << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Mask */ +#define USBHS_HSTPIPISR_DTSEQ(value) (USBHS_HSTPIPISR_DTSEQ_Msk & ((value) << USBHS_HSTPIPISR_DTSEQ_Pos)) +#define USBHS_HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (USBHS_HSTPIPISR_DTSEQ_DATA0_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data0 toggle sequence Position */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (USBHS_HSTPIPISR_DTSEQ_DATA1_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data1 toggle sequence Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos _U_(12) /**< (USBHS_HSTPIPISR) Number of Busy Banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) Number of Busy Banks Mask */ +#define USBHS_HSTPIPISR_NBUSYBK(value) (USBHS_HSTPIPISR_NBUSYBK_Msk & ((value) << USBHS_HSTPIPISR_NBUSYBK_Pos)) +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_HSTPIPISR) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_HSTPIPISR) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_HSTPIPISR) 3 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) Position */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 1 busy bank Position */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 2 busy banks Position */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 3 busy banks Position */ +#define USBHS_HSTPIPISR_CURRBK_Pos _U_(14) /**< (USBHS_HSTPIPISR) Current Bank Position */ +#define USBHS_HSTPIPISR_CURRBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current Bank Mask */ +#define USBHS_HSTPIPISR_CURRBK(value) (USBHS_HSTPIPISR_CURRBK_Msk & ((value) << USBHS_HSTPIPISR_CURRBK_Pos)) +#define USBHS_HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_HSTPIPISR) Current bank is bank2 */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (USBHS_HSTPIPISR_CURRBK_BANK0_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank0 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (USBHS_HSTPIPISR_CURRBK_BANK1_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank1 Position */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (USBHS_HSTPIPISR_CURRBK_BANK2_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank2 Position */ +#define USBHS_HSTPIPISR_RWALL_Pos _U_(16) /**< (USBHS_HSTPIPISR) Read/Write Allowed Position */ +#define USBHS_HSTPIPISR_RWALL_Msk (_U_(0x1) << USBHS_HSTPIPISR_RWALL_Pos) /**< (USBHS_HSTPIPISR) Read/Write Allowed Mask */ +#define USBHS_HSTPIPISR_RWALL(value) (USBHS_HSTPIPISR_RWALL_Msk & ((value) << USBHS_HSTPIPISR_RWALL_Pos)) +#define USBHS_HSTPIPISR_CFGOK_Pos _U_(18) /**< (USBHS_HSTPIPISR) Configuration OK Status Position */ +#define USBHS_HSTPIPISR_CFGOK_Msk (_U_(0x1) << USBHS_HSTPIPISR_CFGOK_Pos) /**< (USBHS_HSTPIPISR) Configuration OK Status Mask */ +#define USBHS_HSTPIPISR_CFGOK(value) (USBHS_HSTPIPISR_CFGOK_Msk & ((value) << USBHS_HSTPIPISR_CFGOK_Pos)) +#define USBHS_HSTPIPISR_PBYCT_Pos _U_(20) /**< (USBHS_HSTPIPISR) Pipe Byte Count Position */ +#define USBHS_HSTPIPISR_PBYCT_Msk (_U_(0x7FF) << USBHS_HSTPIPISR_PBYCT_Pos) /**< (USBHS_HSTPIPISR) Pipe Byte Count Mask */ +#define USBHS_HSTPIPISR_PBYCT(value) (USBHS_HSTPIPISR_PBYCT_Msk & ((value) << USBHS_HSTPIPISR_PBYCT_Pos)) +#define USBHS_HSTPIPISR_Msk _U_(0x7FF5F3BB) /**< (USBHS_HSTPIPISR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI_Pos _U_(2) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_CTRL_TXSTPI(value) (USBHS_HSTPIPISR_CTRL_TXSTPI_Msk & ((value) << USBHS_HSTPIPISR_CTRL_TXSTPI_Pos)) +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos _U_(6) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_CTRL_RXSTALLDI(value) (USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk & ((value) << USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos)) +#define USBHS_HSTPIPISR_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPISR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPISR_ISO_UNDERFI_Pos _U_(2) /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ +#define USBHS_HSTPIPISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ +#define USBHS_HSTPIPISR_ISO_UNDERFI(value) (USBHS_HSTPIPISR_ISO_UNDERFI_Msk & ((value) << USBHS_HSTPIPISR_ISO_UNDERFI_Pos)) +#define USBHS_HSTPIPISR_ISO_CRCERRI_Pos _U_(6) /**< (USBHS_HSTPIPISR) CRC Error Interrupt Position */ +#define USBHS_HSTPIPISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_CRCERRI_Pos) /**< (USBHS_HSTPIPISR) CRC Error Interrupt Mask */ +#define USBHS_HSTPIPISR_ISO_CRCERRI(value) (USBHS_HSTPIPISR_ISO_CRCERRI_Msk & ((value) << USBHS_HSTPIPISR_ISO_CRCERRI_Pos)) +#define USBHS_HSTPIPISR_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPISR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPISR_BLK_TXSTPI_Pos _U_(2) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ +#define USBHS_HSTPIPISR_BLK_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ +#define USBHS_HSTPIPISR_BLK_TXSTPI(value) (USBHS_HSTPIPISR_BLK_TXSTPI_Msk & ((value) << USBHS_HSTPIPISR_BLK_TXSTPI_Pos)) +#define USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos _U_(6) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_BLK_RXSTALLDI(value) (USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk & ((value) << USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos)) +#define USBHS_HSTPIPISR_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPISR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos _U_(2) /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ +#define USBHS_HSTPIPISR_INTRPT_UNDERFI(value) (USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk & ((value) << USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos)) +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos _U_(6) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ +#define USBHS_HSTPIPISR_INTRPT_RXSTALLDI(value) (USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk & ((value) << USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos)) +#define USBHS_HSTPIPISR_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPISR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPICR : (USBHS Offset: 0x560) ( /W 32) Host Pipe Clear Register -------- */ +#define USBHS_HSTPIPICR_RXINIC_Pos _U_(0) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_RXINIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_RXINIC_Pos) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_RXINIC(value) (USBHS_HSTPIPICR_RXINIC_Msk & ((value) << USBHS_HSTPIPICR_RXINIC_Pos)) +#define USBHS_HSTPIPICR_TXOUTIC_Pos _U_(1) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ +#define USBHS_HSTPIPICR_TXOUTIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_TXOUTIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_TXOUTIC(value) (USBHS_HSTPIPICR_TXOUTIC_Msk & ((value) << USBHS_HSTPIPICR_TXOUTIC_Pos)) +#define USBHS_HSTPIPICR_NAKEDIC_Pos _U_(4) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_NAKEDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_NAKEDIC_Pos) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_NAKEDIC(value) (USBHS_HSTPIPICR_NAKEDIC_Msk & ((value) << USBHS_HSTPIPICR_NAKEDIC_Pos)) +#define USBHS_HSTPIPICR_OVERFIC_Pos _U_(5) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_OVERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_OVERFIC_Pos) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_OVERFIC(value) (USBHS_HSTPIPICR_OVERFIC_Msk & ((value) << USBHS_HSTPIPICR_OVERFIC_Pos)) +#define USBHS_HSTPIPICR_SHORTPACKETIC_Pos _U_(7) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Position */ +#define USBHS_HSTPIPICR_SHORTPACKETIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_SHORTPACKETIC(value) (USBHS_HSTPIPICR_SHORTPACKETIC_Msk & ((value) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos)) +#define USBHS_HSTPIPICR_Msk _U_(0x000000B3) /**< (USBHS_HSTPIPICR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos _U_(2) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_CTRL_TXSTPIC(value) (USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk & ((value) << USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos)) +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos _U_(6) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_CTRL_RXSTALLDIC(value) (USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk & ((value) << USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos)) +#define USBHS_HSTPIPICR_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPICR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC_Pos _U_(2) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_ISO_UNDERFIC(value) (USBHS_HSTPIPICR_ISO_UNDERFIC_Msk & ((value) << USBHS_HSTPIPICR_ISO_UNDERFIC_Pos)) +#define USBHS_HSTPIPICR_ISO_CRCERRIC_Pos _U_(6) /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Position */ +#define USBHS_HSTPIPICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_CRCERRIC_Pos) /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_ISO_CRCERRIC(value) (USBHS_HSTPIPICR_ISO_CRCERRIC_Msk & ((value) << USBHS_HSTPIPICR_ISO_CRCERRIC_Pos)) +#define USBHS_HSTPIPICR_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPICR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC_Pos _U_(2) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_BLK_TXSTPIC(value) (USBHS_HSTPIPICR_BLK_TXSTPIC_Msk & ((value) << USBHS_HSTPIPICR_BLK_TXSTPIC_Pos)) +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos _U_(6) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_BLK_RXSTALLDIC(value) (USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk & ((value) << USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos)) +#define USBHS_HSTPIPICR_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPICR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos _U_(2) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_INTRPT_UNDERFIC(value) (USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk & ((value) << USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos)) +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos _U_(6) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ +#define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC(value) (USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk & ((value) << USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos)) +#define USBHS_HSTPIPICR_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPICR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIFR : (USBHS Offset: 0x590) ( /W 32) Host Pipe Set Register -------- */ +#define USBHS_HSTPIPIFR_RXINIS_Pos _U_(0) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_RXINIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_RXINIS_Pos) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_RXINIS(value) (USBHS_HSTPIPIFR_RXINIS_Msk & ((value) << USBHS_HSTPIPIFR_RXINIS_Pos)) +#define USBHS_HSTPIPIFR_TXOUTIS_Pos _U_(1) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ +#define USBHS_HSTPIPIFR_TXOUTIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_TXOUTIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_TXOUTIS(value) (USBHS_HSTPIPIFR_TXOUTIS_Msk & ((value) << USBHS_HSTPIPIFR_TXOUTIS_Pos)) +#define USBHS_HSTPIPIFR_PERRIS_Pos _U_(3) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Position */ +#define USBHS_HSTPIPIFR_PERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_PERRIS_Pos) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_PERRIS(value) (USBHS_HSTPIPIFR_PERRIS_Msk & ((value) << USBHS_HSTPIPIFR_PERRIS_Pos)) +#define USBHS_HSTPIPIFR_NAKEDIS_Pos _U_(4) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_NAKEDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NAKEDIS_Pos) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_NAKEDIS(value) (USBHS_HSTPIPIFR_NAKEDIS_Msk & ((value) << USBHS_HSTPIPIFR_NAKEDIS_Pos)) +#define USBHS_HSTPIPIFR_OVERFIS_Pos _U_(5) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_OVERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_OVERFIS_Pos) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_OVERFIS(value) (USBHS_HSTPIPIFR_OVERFIS_Msk & ((value) << USBHS_HSTPIPIFR_OVERFIS_Pos)) +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Pos _U_(7) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Position */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS(value) (USBHS_HSTPIPIFR_SHORTPACKETIS_Msk & ((value) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos)) +#define USBHS_HSTPIPIFR_NBUSYBKS_Pos _U_(12) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Position */ +#define USBHS_HSTPIPIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NBUSYBKS_Pos) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Mask */ +#define USBHS_HSTPIPIFR_NBUSYBKS(value) (USBHS_HSTPIPIFR_NBUSYBKS_Msk & ((value) << USBHS_HSTPIPIFR_NBUSYBKS_Pos)) +#define USBHS_HSTPIPIFR_Msk _U_(0x000010BB) /**< (USBHS_HSTPIPIFR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos _U_(2) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_CTRL_TXSTPIS(value) (USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk & ((value) << USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos)) +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos _U_(6) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS(value) (USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk & ((value) << USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos)) +#define USBHS_HSTPIPIFR_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIFR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos _U_(2) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_ISO_UNDERFIS(value) (USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk & ((value) << USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos)) +#define USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos _U_(6) /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Position */ +#define USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos) /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_ISO_CRCERRIS(value) (USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk & ((value) << USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos)) +#define USBHS_HSTPIPIFR_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIFR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos _U_(2) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_BLK_TXSTPIS(value) (USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk & ((value) << USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos)) +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos _U_(6) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_BLK_RXSTALLDIS(value) (USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk & ((value) << USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos)) +#define USBHS_HSTPIPIFR_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIFR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos _U_(2) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_INTRPT_UNDERFIS(value) (USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk & ((value) << USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos)) +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos _U_(6) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ +#define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS(value) (USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk & ((value) << USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos)) +#define USBHS_HSTPIPIFR_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIFR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIMR : (USBHS Offset: 0x5C0) ( R/ 32) Host Pipe Mask Register -------- */ +#define USBHS_HSTPIPIMR_RXINE_Pos _U_(0) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_RXINE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RXINE_Pos) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_RXINE(value) (USBHS_HSTPIPIMR_RXINE_Msk & ((value) << USBHS_HSTPIPIMR_RXINE_Pos)) +#define USBHS_HSTPIPIMR_TXOUTE_Pos _U_(1) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_TXOUTE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_TXOUTE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_TXOUTE(value) (USBHS_HSTPIPIMR_TXOUTE_Msk & ((value) << USBHS_HSTPIPIMR_TXOUTE_Pos)) +#define USBHS_HSTPIPIMR_PERRE_Pos _U_(3) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_PERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PERRE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_PERRE(value) (USBHS_HSTPIPIMR_PERRE_Msk & ((value) << USBHS_HSTPIPIMR_PERRE_Pos)) +#define USBHS_HSTPIPIMR_NAKEDE_Pos _U_(4) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NAKEDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NAKEDE_Pos) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NAKEDE(value) (USBHS_HSTPIPIMR_NAKEDE_Msk & ((value) << USBHS_HSTPIPIMR_NAKEDE_Pos)) +#define USBHS_HSTPIPIMR_OVERFIE_Pos _U_(5) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_OVERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_OVERFIE_Pos) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_OVERFIE(value) (USBHS_HSTPIPIMR_OVERFIE_Msk & ((value) << USBHS_HSTPIPIMR_OVERFIE_Pos)) +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Pos _U_(7) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE(value) (USBHS_HSTPIPIMR_SHORTPACKETIE_Msk & ((value) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos)) +#define USBHS_HSTPIPIMR_NBUSYBKE_Pos _U_(12) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NBUSYBKE_Pos) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_NBUSYBKE(value) (USBHS_HSTPIPIMR_NBUSYBKE_Msk & ((value) << USBHS_HSTPIPIMR_NBUSYBKE_Pos)) +#define USBHS_HSTPIPIMR_FIFOCON_Pos _U_(14) /**< (USBHS_HSTPIPIMR) FIFO Control Position */ +#define USBHS_HSTPIPIMR_FIFOCON_Msk (_U_(0x1) << USBHS_HSTPIPIMR_FIFOCON_Pos) /**< (USBHS_HSTPIPIMR) FIFO Control Mask */ +#define USBHS_HSTPIPIMR_FIFOCON(value) (USBHS_HSTPIPIMR_FIFOCON_Msk & ((value) << USBHS_HSTPIPIMR_FIFOCON_Pos)) +#define USBHS_HSTPIPIMR_PDISHDMA_Pos _U_(16) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIMR_PDISHDMA_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PDISHDMA_Pos) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIMR_PDISHDMA(value) (USBHS_HSTPIPIMR_PDISHDMA_Msk & ((value) << USBHS_HSTPIPIMR_PDISHDMA_Pos)) +#define USBHS_HSTPIPIMR_PFREEZE_Pos _U_(17) /**< (USBHS_HSTPIPIMR) Pipe Freeze Position */ +#define USBHS_HSTPIPIMR_PFREEZE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PFREEZE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Freeze Mask */ +#define USBHS_HSTPIPIMR_PFREEZE(value) (USBHS_HSTPIPIMR_PFREEZE_Msk & ((value) << USBHS_HSTPIPIMR_PFREEZE_Pos)) +#define USBHS_HSTPIPIMR_RSTDT_Pos _U_(18) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Position */ +#define USBHS_HSTPIPIMR_RSTDT_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RSTDT_Pos) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Mask */ +#define USBHS_HSTPIPIMR_RSTDT(value) (USBHS_HSTPIPIMR_RSTDT_Msk & ((value) << USBHS_HSTPIPIMR_RSTDT_Pos)) +#define USBHS_HSTPIPIMR_Msk _U_(0x000750BB) /**< (USBHS_HSTPIPIMR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos _U_(2) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_CTRL_TXSTPE(value) (USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk & ((value) << USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos)) +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos _U_(6) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_CTRL_RXSTALLDE(value) (USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk & ((value) << USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos)) +#define USBHS_HSTPIPIMR_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIMR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos _U_(2) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_ISO_UNDERFIE(value) (USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk & ((value) << USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos)) +#define USBHS_HSTPIPIMR_ISO_CRCERRE_Pos _U_(6) /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_CRCERRE_Pos) /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_ISO_CRCERRE(value) (USBHS_HSTPIPIMR_ISO_CRCERRE_Msk & ((value) << USBHS_HSTPIPIMR_ISO_CRCERRE_Pos)) +#define USBHS_HSTPIPIMR_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIMR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE_Pos _U_(2) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_BLK_TXSTPE(value) (USBHS_HSTPIPIMR_BLK_TXSTPE_Msk & ((value) << USBHS_HSTPIPIMR_BLK_TXSTPE_Pos)) +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos _U_(6) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_BLK_RXSTALLDE(value) (USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk & ((value) << USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos)) +#define USBHS_HSTPIPIMR_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIMR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos _U_(2) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_INTRPT_UNDERFIE(value) (USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk & ((value) << USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos)) +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos _U_(6) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE(value) (USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk & ((value) << USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos)) +#define USBHS_HSTPIPIMR_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIMR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIER : (USBHS Offset: 0x5F0) ( /W 32) Host Pipe Enable Register -------- */ +#define USBHS_HSTPIPIER_RXINES_Pos _U_(0) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_RXINES_Msk (_U_(0x1) << USBHS_HSTPIPIER_RXINES_Pos) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_RXINES(value) (USBHS_HSTPIPIER_RXINES_Msk & ((value) << USBHS_HSTPIPIER_RXINES_Pos)) +#define USBHS_HSTPIPIER_TXOUTES_Pos _U_(1) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ +#define USBHS_HSTPIPIER_TXOUTES_Msk (_U_(0x1) << USBHS_HSTPIPIER_TXOUTES_Pos) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_TXOUTES(value) (USBHS_HSTPIPIER_TXOUTES_Msk & ((value) << USBHS_HSTPIPIER_TXOUTES_Pos)) +#define USBHS_HSTPIPIER_PERRES_Pos _U_(3) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Position */ +#define USBHS_HSTPIPIER_PERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PERRES_Pos) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_PERRES(value) (USBHS_HSTPIPIER_PERRES_Msk & ((value) << USBHS_HSTPIPIER_PERRES_Pos)) +#define USBHS_HSTPIPIER_NAKEDES_Pos _U_(4) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_NAKEDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NAKEDES_Pos) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_NAKEDES(value) (USBHS_HSTPIPIER_NAKEDES_Msk & ((value) << USBHS_HSTPIPIER_NAKEDES_Pos)) +#define USBHS_HSTPIPIER_OVERFIES_Pos _U_(5) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_OVERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_OVERFIES_Pos) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_OVERFIES(value) (USBHS_HSTPIPIER_OVERFIES_Msk & ((value) << USBHS_HSTPIPIER_OVERFIES_Pos)) +#define USBHS_HSTPIPIER_SHORTPACKETIES_Pos _U_(7) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Position */ +#define USBHS_HSTPIPIER_SHORTPACKETIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_SHORTPACKETIES(value) (USBHS_HSTPIPIER_SHORTPACKETIES_Msk & ((value) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos)) +#define USBHS_HSTPIPIER_NBUSYBKES_Pos _U_(12) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Position */ +#define USBHS_HSTPIPIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NBUSYBKES_Pos) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Mask */ +#define USBHS_HSTPIPIER_NBUSYBKES(value) (USBHS_HSTPIPIER_NBUSYBKES_Msk & ((value) << USBHS_HSTPIPIER_NBUSYBKES_Pos)) +#define USBHS_HSTPIPIER_PDISHDMAS_Pos _U_(16) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ +#define USBHS_HSTPIPIER_PDISHDMAS_Msk (_U_(0x1) << USBHS_HSTPIPIER_PDISHDMAS_Pos) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ +#define USBHS_HSTPIPIER_PDISHDMAS(value) (USBHS_HSTPIPIER_PDISHDMAS_Msk & ((value) << USBHS_HSTPIPIER_PDISHDMAS_Pos)) +#define USBHS_HSTPIPIER_PFREEZES_Pos _U_(17) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Position */ +#define USBHS_HSTPIPIER_PFREEZES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PFREEZES_Pos) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Mask */ +#define USBHS_HSTPIPIER_PFREEZES(value) (USBHS_HSTPIPIER_PFREEZES_Msk & ((value) << USBHS_HSTPIPIER_PFREEZES_Pos)) +#define USBHS_HSTPIPIER_RSTDTS_Pos _U_(18) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Position */ +#define USBHS_HSTPIPIER_RSTDTS_Msk (_U_(0x1) << USBHS_HSTPIPIER_RSTDTS_Pos) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Mask */ +#define USBHS_HSTPIPIER_RSTDTS(value) (USBHS_HSTPIPIER_RSTDTS_Msk & ((value) << USBHS_HSTPIPIER_RSTDTS_Pos)) +#define USBHS_HSTPIPIER_Msk _U_(0x000710BB) /**< (USBHS_HSTPIPIER) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES_Pos _U_(2) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_CTRL_TXSTPES(value) (USBHS_HSTPIPIER_CTRL_TXSTPES_Msk & ((value) << USBHS_HSTPIPIER_CTRL_TXSTPES_Pos)) +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos _U_(6) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_CTRL_RXSTALLDES(value) (USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk & ((value) << USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos)) +#define USBHS_HSTPIPIER_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIER_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES_Pos _U_(2) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_ISO_UNDERFIES(value) (USBHS_HSTPIPIER_ISO_UNDERFIES_Msk & ((value) << USBHS_HSTPIPIER_ISO_UNDERFIES_Pos)) +#define USBHS_HSTPIPIER_ISO_CRCERRES_Pos _U_(6) /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Position */ +#define USBHS_HSTPIPIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_CRCERRES_Pos) /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_ISO_CRCERRES(value) (USBHS_HSTPIPIER_ISO_CRCERRES_Msk & ((value) << USBHS_HSTPIPIER_ISO_CRCERRES_Pos)) +#define USBHS_HSTPIPIER_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIER_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIER_BLK_TXSTPES_Pos _U_(2) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ +#define USBHS_HSTPIPIER_BLK_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_BLK_TXSTPES(value) (USBHS_HSTPIPIER_BLK_TXSTPES_Msk & ((value) << USBHS_HSTPIPIER_BLK_TXSTPES_Pos)) +#define USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos _U_(6) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_BLK_RXSTALLDES(value) (USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk & ((value) << USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos)) +#define USBHS_HSTPIPIER_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIER_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos _U_(2) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_INTRPT_UNDERFIES(value) (USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk & ((value) << USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos)) +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos _U_(6) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ +#define USBHS_HSTPIPIER_INTRPT_RXSTALLDES(value) (USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk & ((value) << USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos)) +#define USBHS_HSTPIPIER_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIER_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPIDR : (USBHS Offset: 0x620) ( /W 32) Host Pipe Disable Register -------- */ +#define USBHS_HSTPIPIDR_RXINEC_Pos _U_(0) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_RXINEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_RXINEC_Pos) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_RXINEC(value) (USBHS_HSTPIPIDR_RXINEC_Msk & ((value) << USBHS_HSTPIPIDR_RXINEC_Pos)) +#define USBHS_HSTPIPIDR_TXOUTEC_Pos _U_(1) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_TXOUTEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_TXOUTEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_TXOUTEC(value) (USBHS_HSTPIPIDR_TXOUTEC_Msk & ((value) << USBHS_HSTPIPIDR_TXOUTEC_Pos)) +#define USBHS_HSTPIPIDR_PERREC_Pos _U_(3) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_PERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PERREC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_PERREC(value) (USBHS_HSTPIPIDR_PERREC_Msk & ((value) << USBHS_HSTPIPIDR_PERREC_Pos)) +#define USBHS_HSTPIPIDR_NAKEDEC_Pos _U_(4) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_NAKEDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NAKEDEC_Pos) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_NAKEDEC(value) (USBHS_HSTPIPIDR_NAKEDEC_Msk & ((value) << USBHS_HSTPIPIDR_NAKEDEC_Pos)) +#define USBHS_HSTPIPIDR_OVERFIEC_Pos _U_(5) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_OVERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_OVERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_OVERFIEC(value) (USBHS_HSTPIPIDR_OVERFIEC_Msk & ((value) << USBHS_HSTPIPIDR_OVERFIEC_Pos)) +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos _U_(7) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC(value) (USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk & ((value) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos)) +#define USBHS_HSTPIPIDR_NBUSYBKEC_Pos _U_(12) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Position */ +#define USBHS_HSTPIPIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Mask */ +#define USBHS_HSTPIPIDR_NBUSYBKEC(value) (USBHS_HSTPIPIDR_NBUSYBKEC_Msk & ((value) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos)) +#define USBHS_HSTPIPIDR_FIFOCONC_Pos _U_(14) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Position */ +#define USBHS_HSTPIPIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_FIFOCONC_Pos) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Mask */ +#define USBHS_HSTPIPIDR_FIFOCONC(value) (USBHS_HSTPIPIDR_FIFOCONC_Msk & ((value) << USBHS_HSTPIPIDR_FIFOCONC_Pos)) +#define USBHS_HSTPIPIDR_PDISHDMAC_Pos _U_(16) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ +#define USBHS_HSTPIPIDR_PDISHDMAC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PDISHDMAC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ +#define USBHS_HSTPIPIDR_PDISHDMAC(value) (USBHS_HSTPIPIDR_PDISHDMAC_Msk & ((value) << USBHS_HSTPIPIDR_PDISHDMAC_Pos)) +#define USBHS_HSTPIPIDR_PFREEZEC_Pos _U_(17) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Position */ +#define USBHS_HSTPIPIDR_PFREEZEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PFREEZEC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Mask */ +#define USBHS_HSTPIPIDR_PFREEZEC(value) (USBHS_HSTPIPIDR_PFREEZEC_Msk & ((value) << USBHS_HSTPIPIDR_PFREEZEC_Pos)) +#define USBHS_HSTPIPIDR_Msk _U_(0x000350BB) /**< (USBHS_HSTPIPIDR) Register Mask */ + +/* CTRL mode */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos _U_(2) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_CTRL_TXSTPEC(value) (USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk & ((value) << USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos)) +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos _U_(6) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC(value) (USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk & ((value) << USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos)) +#define USBHS_HSTPIPIDR_CTRL_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIDR_CTRL) Register Mask */ + +/* ISO mode */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos _U_(2) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_ISO_UNDERFIEC(value) (USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk & ((value) << USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos)) +#define USBHS_HSTPIPIDR_ISO_CRCERREC_Pos _U_(6) /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_ISO_CRCERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_CRCERREC_Pos) /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_ISO_CRCERREC(value) (USBHS_HSTPIPIDR_ISO_CRCERREC_Msk & ((value) << USBHS_HSTPIPIDR_ISO_CRCERREC_Pos)) +#define USBHS_HSTPIPIDR_ISO_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIDR_ISO) Register Mask */ + +/* BLK mode */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos _U_(2) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_BLK_TXSTPEC(value) (USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk & ((value) << USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos)) +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos _U_(6) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_BLK_RXSTALLDEC(value) (USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk & ((value) << USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos)) +#define USBHS_HSTPIPIDR_BLK_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIDR_BLK) Register Mask */ + +/* INTRPT mode */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos _U_(2) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC(value) (USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk & ((value) << USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos)) +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos _U_(6) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ +#define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC(value) (USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk & ((value) << USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos)) +#define USBHS_HSTPIPIDR_INTRPT_Msk _U_(0x00000044) /**< (USBHS_HSTPIPIDR_INTRPT) Register Mask */ + + +/* -------- USBHS_HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos _U_(0) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Position */ +#define USBHS_HSTPIPINRQ_INRQ_Msk (_U_(0xFF) << USBHS_HSTPIPINRQ_INRQ_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Mask */ +#define USBHS_HSTPIPINRQ_INRQ(value) (USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)) +#define USBHS_HSTPIPINRQ_INMODE_Pos _U_(8) /**< (USBHS_HSTPIPINRQ) IN Request Mode Position */ +#define USBHS_HSTPIPINRQ_INMODE_Msk (_U_(0x1) << USBHS_HSTPIPINRQ_INMODE_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Mode Mask */ +#define USBHS_HSTPIPINRQ_INMODE(value) (USBHS_HSTPIPINRQ_INMODE_Msk & ((value) << USBHS_HSTPIPINRQ_INMODE_Pos)) +#define USBHS_HSTPIPINRQ_Msk _U_(0x000001FF) /**< (USBHS_HSTPIPINRQ) Register Mask */ + + +/* -------- USBHS_HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ +#define USBHS_HSTPIPERR_DATATGL_Pos _U_(0) /**< (USBHS_HSTPIPERR) Data Toggle Error Position */ +#define USBHS_HSTPIPERR_DATATGL_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATATGL_Pos) /**< (USBHS_HSTPIPERR) Data Toggle Error Mask */ +#define USBHS_HSTPIPERR_DATATGL(value) (USBHS_HSTPIPERR_DATATGL_Msk & ((value) << USBHS_HSTPIPERR_DATATGL_Pos)) +#define USBHS_HSTPIPERR_DATAPID_Pos _U_(1) /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_DATAPID_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATAPID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_DATAPID(value) (USBHS_HSTPIPERR_DATAPID_Msk & ((value) << USBHS_HSTPIPERR_DATAPID_Pos)) +#define USBHS_HSTPIPERR_PID_Pos _U_(2) /**< (USBHS_HSTPIPERR) Data PID Error Position */ +#define USBHS_HSTPIPERR_PID_Msk (_U_(0x1) << USBHS_HSTPIPERR_PID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ +#define USBHS_HSTPIPERR_PID(value) (USBHS_HSTPIPERR_PID_Msk & ((value) << USBHS_HSTPIPERR_PID_Pos)) +#define USBHS_HSTPIPERR_TIMEOUT_Pos _U_(3) /**< (USBHS_HSTPIPERR) Time-Out Error Position */ +#define USBHS_HSTPIPERR_TIMEOUT_Msk (_U_(0x1) << USBHS_HSTPIPERR_TIMEOUT_Pos) /**< (USBHS_HSTPIPERR) Time-Out Error Mask */ +#define USBHS_HSTPIPERR_TIMEOUT(value) (USBHS_HSTPIPERR_TIMEOUT_Msk & ((value) << USBHS_HSTPIPERR_TIMEOUT_Pos)) +#define USBHS_HSTPIPERR_CRC16_Pos _U_(4) /**< (USBHS_HSTPIPERR) CRC16 Error Position */ +#define USBHS_HSTPIPERR_CRC16_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC16_Pos) /**< (USBHS_HSTPIPERR) CRC16 Error Mask */ +#define USBHS_HSTPIPERR_CRC16(value) (USBHS_HSTPIPERR_CRC16_Msk & ((value) << USBHS_HSTPIPERR_CRC16_Pos)) +#define USBHS_HSTPIPERR_COUNTER_Pos _U_(5) /**< (USBHS_HSTPIPERR) Error Counter Position */ +#define USBHS_HSTPIPERR_COUNTER_Msk (_U_(0x3) << USBHS_HSTPIPERR_COUNTER_Pos) /**< (USBHS_HSTPIPERR) Error Counter Mask */ +#define USBHS_HSTPIPERR_COUNTER(value) (USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)) +#define USBHS_HSTPIPERR_Msk _U_(0x0000007F) /**< (USBHS_HSTPIPERR) Register Mask */ + +#define USBHS_HSTPIPERR_CRC_Pos _U_(4) /**< (USBHS_HSTPIPERR Position) CRCx6 Error */ +#define USBHS_HSTPIPERR_CRC_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC_Pos) /**< (USBHS_HSTPIPERR Mask) CRC */ +#define USBHS_HSTPIPERR_CRC(value) (USBHS_HSTPIPERR_CRC_Msk & ((value) << USBHS_HSTPIPERR_CRC_Pos)) + +/* -------- USBHS_CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ +#define USBHS_CTRL_RDERRE_Pos _U_(4) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Position */ +#define USBHS_CTRL_RDERRE_Msk (_U_(0x1) << USBHS_CTRL_RDERRE_Pos) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Mask */ +#define USBHS_CTRL_RDERRE(value) (USBHS_CTRL_RDERRE_Msk & ((value) << USBHS_CTRL_RDERRE_Pos)) +#define USBHS_CTRL_VBUSHWC_Pos _U_(8) /**< (USBHS_CTRL) VBUS Hardware Control Position */ +#define USBHS_CTRL_VBUSHWC_Msk (_U_(0x1) << USBHS_CTRL_VBUSHWC_Pos) /**< (USBHS_CTRL) VBUS Hardware Control Mask */ +#define USBHS_CTRL_VBUSHWC(value) (USBHS_CTRL_VBUSHWC_Msk & ((value) << USBHS_CTRL_VBUSHWC_Pos)) +#define USBHS_CTRL_FRZCLK_Pos _U_(14) /**< (USBHS_CTRL) Freeze USB Clock Position */ +#define USBHS_CTRL_FRZCLK_Msk (_U_(0x1) << USBHS_CTRL_FRZCLK_Pos) /**< (USBHS_CTRL) Freeze USB Clock Mask */ +#define USBHS_CTRL_FRZCLK(value) (USBHS_CTRL_FRZCLK_Msk & ((value) << USBHS_CTRL_FRZCLK_Pos)) +#define USBHS_CTRL_USBE_Pos _U_(15) /**< (USBHS_CTRL) USBHS Enable Position */ +#define USBHS_CTRL_USBE_Msk (_U_(0x1) << USBHS_CTRL_USBE_Pos) /**< (USBHS_CTRL) USBHS Enable Mask */ +#define USBHS_CTRL_USBE(value) (USBHS_CTRL_USBE_Msk & ((value) << USBHS_CTRL_USBE_Pos)) +#define USBHS_CTRL_UID_Pos _U_(24) /**< (USBHS_CTRL) UID Pin Enable Position */ +#define USBHS_CTRL_UID_Msk (_U_(0x1) << USBHS_CTRL_UID_Pos) /**< (USBHS_CTRL) UID Pin Enable Mask */ +#define USBHS_CTRL_UID(value) (USBHS_CTRL_UID_Msk & ((value) << USBHS_CTRL_UID_Pos)) +#define USBHS_CTRL_UIMOD_Pos _U_(25) /**< (USBHS_CTRL) USBHS Mode Position */ +#define USBHS_CTRL_UIMOD_Msk (_U_(0x1) << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) USBHS Mode Mask */ +#define USBHS_CTRL_UIMOD(value) (USBHS_CTRL_UIMOD_Msk & ((value) << USBHS_CTRL_UIMOD_Pos)) +#define USBHS_CTRL_UIMOD_HOST_Val _U_(0x0) /**< (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (USBHS_CTRL) The module is in USB Device mode. */ +#define USBHS_CTRL_UIMOD_HOST (USBHS_CTRL_UIMOD_HOST_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Host mode. Position */ +#define USBHS_CTRL_UIMOD_DEVICE (USBHS_CTRL_UIMOD_DEVICE_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Device mode. Position */ +#define USBHS_CTRL_Msk _U_(0x0300C110) /**< (USBHS_CTRL) Register Mask */ + + +/* -------- USBHS_SR : (USBHS Offset: 0x804) ( R/ 32) General Status Register -------- */ +#define USBHS_SR_RDERRI_Pos _U_(4) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Position */ +#define USBHS_SR_RDERRI_Msk (_U_(0x1) << USBHS_SR_RDERRI_Pos) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ +#define USBHS_SR_RDERRI(value) (USBHS_SR_RDERRI_Msk & ((value) << USBHS_SR_RDERRI_Pos)) +#define USBHS_SR_SPEED_Pos _U_(12) /**< (USBHS_SR) Speed Status (Device mode only) Position */ +#define USBHS_SR_SPEED_Msk (_U_(0x3) << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Speed Status (Device mode only) Mask */ +#define USBHS_SR_SPEED(value) (USBHS_SR_SPEED_Msk & ((value) << USBHS_SR_SPEED_Pos)) +#define USBHS_SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_SPEED_FULL_SPEED (USBHS_SR_SPEED_FULL_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Full-Speed mode Position */ +#define USBHS_SR_SPEED_HIGH_SPEED (USBHS_SR_SPEED_HIGH_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) High-Speed mode Position */ +#define USBHS_SR_SPEED_LOW_SPEED (USBHS_SR_SPEED_LOW_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Low-Speed mode Position */ +#define USBHS_SR_CLKUSABLE_Pos _U_(14) /**< (USBHS_SR) UTMI Clock Usable Position */ +#define USBHS_SR_CLKUSABLE_Msk (_U_(0x1) << USBHS_SR_CLKUSABLE_Pos) /**< (USBHS_SR) UTMI Clock Usable Mask */ +#define USBHS_SR_CLKUSABLE(value) (USBHS_SR_CLKUSABLE_Msk & ((value) << USBHS_SR_CLKUSABLE_Pos)) +#define USBHS_SR_Msk _U_(0x00007010) /**< (USBHS_SR) Register Mask */ + + +/* -------- USBHS_SCR : (USBHS Offset: 0x808) ( /W 32) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC_Pos _U_(4) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Position */ +#define USBHS_SCR_RDERRIC_Msk (_U_(0x1) << USBHS_SCR_RDERRIC_Pos) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Mask */ +#define USBHS_SCR_RDERRIC(value) (USBHS_SCR_RDERRIC_Msk & ((value) << USBHS_SCR_RDERRIC_Pos)) +#define USBHS_SCR_Msk _U_(0x00000010) /**< (USBHS_SCR) Register Mask */ + + +/* -------- USBHS_SFR : (USBHS Offset: 0x80C) ( /W 32) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS_Pos _U_(4) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Position */ +#define USBHS_SFR_RDERRIS_Msk (_U_(0x1) << USBHS_SFR_RDERRIS_Pos) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Mask */ +#define USBHS_SFR_RDERRIS(value) (USBHS_SFR_RDERRIS_Msk & ((value) << USBHS_SFR_RDERRIS_Pos)) +#define USBHS_SFR_VBUSRQS_Pos _U_(9) /**< (USBHS_SFR) VBUS Request Set Position */ +#define USBHS_SFR_VBUSRQS_Msk (_U_(0x1) << USBHS_SFR_VBUSRQS_Pos) /**< (USBHS_SFR) VBUS Request Set Mask */ +#define USBHS_SFR_VBUSRQS(value) (USBHS_SFR_VBUSRQS_Msk & ((value) << USBHS_SFR_VBUSRQS_Pos)) +#define USBHS_SFR_Msk _U_(0x00000210) /**< (USBHS_SFR) Register Mask */ + + +/** \brief USBHS register offsets definitions */ +#define USBHS_DEVDMANXTDSC_REG_OFST (0x00) /**< (USBHS_DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ +#define USBHS_DEVDMAADDRESS_REG_OFST (0x04) /**< (USBHS_DEVDMAADDRESS) Device DMA Channel Address Register Offset */ +#define USBHS_DEVDMACONTROL_REG_OFST (0x08) /**< (USBHS_DEVDMACONTROL) Device DMA Channel Control Register Offset */ +#define USBHS_DEVDMASTATUS_REG_OFST (0x0C) /**< (USBHS_DEVDMASTATUS) Device DMA Channel Status Register Offset */ +#define USBHS_HSTDMANXTDSC_REG_OFST (0x00) /**< (USBHS_HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ +#define USBHS_HSTDMAADDRESS_REG_OFST (0x04) /**< (USBHS_HSTDMAADDRESS) Host DMA Channel Address Register Offset */ +#define USBHS_HSTDMACONTROL_REG_OFST (0x08) /**< (USBHS_HSTDMACONTROL) Host DMA Channel Control Register Offset */ +#define USBHS_HSTDMASTATUS_REG_OFST (0x0C) /**< (USBHS_HSTDMASTATUS) Host DMA Channel Status Register Offset */ +#define USBHS_DEVCTRL_REG_OFST (0x00) /**< (USBHS_DEVCTRL) Device General Control Register Offset */ +#define USBHS_DEVISR_REG_OFST (0x04) /**< (USBHS_DEVISR) Device Global Interrupt Status Register Offset */ +#define USBHS_DEVICR_REG_OFST (0x08) /**< (USBHS_DEVICR) Device Global Interrupt Clear Register Offset */ +#define USBHS_DEVIFR_REG_OFST (0x0C) /**< (USBHS_DEVIFR) Device Global Interrupt Set Register Offset */ +#define USBHS_DEVIMR_REG_OFST (0x10) /**< (USBHS_DEVIMR) Device Global Interrupt Mask Register Offset */ +#define USBHS_DEVIDR_REG_OFST (0x14) /**< (USBHS_DEVIDR) Device Global Interrupt Disable Register Offset */ +#define USBHS_DEVIER_REG_OFST (0x18) /**< (USBHS_DEVIER) Device Global Interrupt Enable Register Offset */ +#define USBHS_DEVEPT_REG_OFST (0x1C) /**< (USBHS_DEVEPT) Device Endpoint Register Offset */ +#define USBHS_DEVFNUM_REG_OFST (0x20) /**< (USBHS_DEVFNUM) Device Frame Number Register Offset */ +#define USBHS_DEVEPTCFG_REG_OFST (0x100) /**< (USBHS_DEVEPTCFG) Device Endpoint Configuration Register Offset */ +#define USBHS_DEVEPTISR_REG_OFST (0x130) /**< (USBHS_DEVEPTISR) Device Endpoint Interrupt Status Register Offset */ +#define USBHS_DEVEPTICR_REG_OFST (0x160) /**< (USBHS_DEVEPTICR) Device Endpoint Interrupt Clear Register Offset */ +#define USBHS_DEVEPTIFR_REG_OFST (0x190) /**< (USBHS_DEVEPTIFR) Device Endpoint Interrupt Set Register Offset */ +#define USBHS_DEVEPTIMR_REG_OFST (0x1C0) /**< (USBHS_DEVEPTIMR) Device Endpoint Interrupt Mask Register Offset */ +#define USBHS_DEVEPTIER_REG_OFST (0x1F0) /**< (USBHS_DEVEPTIER) Device Endpoint Interrupt Enable Register Offset */ +#define USBHS_DEVEPTIDR_REG_OFST (0x220) /**< (USBHS_DEVEPTIDR) Device Endpoint Interrupt Disable Register Offset */ +#define USBHS_HSTCTRL_REG_OFST (0x400) /**< (USBHS_HSTCTRL) Host General Control Register Offset */ +#define USBHS_HSTISR_REG_OFST (0x404) /**< (USBHS_HSTISR) Host Global Interrupt Status Register Offset */ +#define USBHS_HSTICR_REG_OFST (0x408) /**< (USBHS_HSTICR) Host Global Interrupt Clear Register Offset */ +#define USBHS_HSTIFR_REG_OFST (0x40C) /**< (USBHS_HSTIFR) Host Global Interrupt Set Register Offset */ +#define USBHS_HSTIMR_REG_OFST (0x410) /**< (USBHS_HSTIMR) Host Global Interrupt Mask Register Offset */ +#define USBHS_HSTIDR_REG_OFST (0x414) /**< (USBHS_HSTIDR) Host Global Interrupt Disable Register Offset */ +#define USBHS_HSTIER_REG_OFST (0x418) /**< (USBHS_HSTIER) Host Global Interrupt Enable Register Offset */ +#define USBHS_HSTPIP_REG_OFST (0x41C) /**< (USBHS_HSTPIP) Host Pipe Register Offset */ +#define USBHS_HSTFNUM_REG_OFST (0x420) /**< (USBHS_HSTFNUM) Host Frame Number Register Offset */ +#define USBHS_HSTADDR1_REG_OFST (0x424) /**< (USBHS_HSTADDR1) Host Address 1 Register Offset */ +#define USBHS_HSTADDR2_REG_OFST (0x428) /**< (USBHS_HSTADDR2) Host Address 2 Register Offset */ +#define USBHS_HSTADDR3_REG_OFST (0x42C) /**< (USBHS_HSTADDR3) Host Address 3 Register Offset */ +#define USBHS_HSTPIPCFG_REG_OFST (0x500) /**< (USBHS_HSTPIPCFG) Host Pipe Configuration Register Offset */ +#define USBHS_HSTPIPISR_REG_OFST (0x530) /**< (USBHS_HSTPIPISR) Host Pipe Status Register Offset */ +#define USBHS_HSTPIPICR_REG_OFST (0x560) /**< (USBHS_HSTPIPICR) Host Pipe Clear Register Offset */ +#define USBHS_HSTPIPIFR_REG_OFST (0x590) /**< (USBHS_HSTPIPIFR) Host Pipe Set Register Offset */ +#define USBHS_HSTPIPIMR_REG_OFST (0x5C0) /**< (USBHS_HSTPIPIMR) Host Pipe Mask Register Offset */ +#define USBHS_HSTPIPIER_REG_OFST (0x5F0) /**< (USBHS_HSTPIPIER) Host Pipe Enable Register Offset */ +#define USBHS_HSTPIPIDR_REG_OFST (0x620) /**< (USBHS_HSTPIPIDR) Host Pipe Disable Register Offset */ +#define USBHS_HSTPIPINRQ_REG_OFST (0x650) /**< (USBHS_HSTPIPINRQ) Host Pipe IN Request Register Offset */ +#define USBHS_HSTPIPERR_REG_OFST (0x680) /**< (USBHS_HSTPIPERR) Host Pipe Error Register Offset */ +#define USBHS_CTRL_REG_OFST (0x800) /**< (USBHS_CTRL) General Control Register Offset */ +#define USBHS_SR_REG_OFST (0x804) /**< (USBHS_SR) General Status Register Offset */ +#define USBHS_SCR_REG_OFST (0x808) /**< (USBHS_SCR) General Status Clear Register Offset */ +#define USBHS_SFR_REG_OFST (0x80C) /**< (USBHS_SFR) General Status Set Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief USBHS_DEVDMA register API structure */ +typedef struct +{ + __IO uint32_t USBHS_DEVDMANXTDSC; /**< Offset: 0x00 (R/W 32) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< Offset: 0x04 (R/W 32) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< Offset: 0x08 (R/W 32) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< Offset: 0x0C (R/W 32) Device DMA Channel Status Register */ +} usbhs_devdma_registers_t; + +/** \brief USBHS_HSTDMA register API structure */ +typedef struct +{ + __IO uint32_t USBHS_HSTDMANXTDSC; /**< Offset: 0x00 (R/W 32) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< Offset: 0x04 (R/W 32) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< Offset: 0x08 (R/W 32) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< Offset: 0x0C (R/W 32) Host DMA Channel Status Register */ +} usbhs_hstdma_registers_t; + +#define USBHS_DEVDMA_NUMBER _U_(7) + +#define USBHS_HSTDMA_NUMBER _U_(7) + +/** \brief USBHS register API structure */ +typedef struct +{ + __IO uint32_t USBHS_DEVCTRL; /**< Offset: 0x00 (R/W 32) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< Offset: 0x04 (R/ 32) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< Offset: 0x08 ( /W 32) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< Offset: 0x0C ( /W 32) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< Offset: 0x10 (R/ 32) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< Offset: 0x14 ( /W 32) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< Offset: 0x18 ( /W 32) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< Offset: 0x1C (R/W 32) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< Offset: 0x20 (R/ 32) Device Frame Number Register */ + __I uint8_t Reserved1[0xDC]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< Offset: 0x100 (R/W 32) Device Endpoint Configuration Register */ + __I uint8_t Reserved2[0x08]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< Offset: 0x130 (R/ 32) Device Endpoint Interrupt Status Register */ + __I uint8_t Reserved3[0x08]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< Offset: 0x160 ( /W 32) Device Endpoint Interrupt Clear Register */ + __I uint8_t Reserved4[0x08]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< Offset: 0x190 ( /W 32) Device Endpoint Interrupt Set Register */ + __I uint8_t Reserved5[0x08]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< Offset: 0x1C0 (R/ 32) Device Endpoint Interrupt Mask Register */ + __I uint8_t Reserved6[0x08]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< Offset: 0x1F0 ( /W 32) Device Endpoint Interrupt Enable Register */ + __I uint8_t Reserved7[0x08]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< Offset: 0x220 ( /W 32) Device Endpoint Interrupt Disable Register */ + __I uint8_t Reserved8[0xC8]; + usbhs_devdma_registers_t USBHS_DEVDMA[USBHS_DEVDMA_NUMBER]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved9[0x80]; + __IO uint32_t USBHS_HSTCTRL; /**< Offset: 0x400 (R/W 32) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< Offset: 0x404 (R/ 32) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< Offset: 0x408 ( /W 32) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< Offset: 0x40C ( /W 32) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< Offset: 0x410 (R/ 32) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< Offset: 0x414 ( /W 32) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< Offset: 0x418 ( /W 32) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< Offset: 0x41C (R/W 32) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< Offset: 0x420 (R/W 32) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< Offset: 0x424 (R/W 32) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< Offset: 0x428 (R/W 32) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< Offset: 0x42C (R/W 32) Host Address 3 Register */ + __I uint8_t Reserved10[0xD0]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< Offset: 0x500 (R/W 32) Host Pipe Configuration Register */ + __I uint8_t Reserved11[0x08]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< Offset: 0x530 (R/ 32) Host Pipe Status Register */ + __I uint8_t Reserved12[0x08]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< Offset: 0x560 ( /W 32) Host Pipe Clear Register */ + __I uint8_t Reserved13[0x08]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< Offset: 0x590 ( /W 32) Host Pipe Set Register */ + __I uint8_t Reserved14[0x08]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< Offset: 0x5C0 (R/ 32) Host Pipe Mask Register */ + __I uint8_t Reserved15[0x08]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< Offset: 0x5F0 ( /W 32) Host Pipe Enable Register */ + __I uint8_t Reserved16[0x08]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< Offset: 0x620 ( /W 32) Host Pipe Disable Register */ + __I uint8_t Reserved17[0x08]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< Offset: 0x650 (R/W 32) Host Pipe IN Request Register */ + __I uint8_t Reserved18[0x08]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< Offset: 0x680 (R/W 32) Host Pipe Error Register */ + __I uint8_t Reserved19[0x68]; + usbhs_hstdma_registers_t USBHS_HSTDMA[USBHS_HSTDMA_NUMBER]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ + __I uint8_t Reserved20[0x80]; + __IO uint32_t USBHS_CTRL; /**< Offset: 0x800 (R/W 32) General Control Register */ + __I uint32_t USBHS_SR; /**< Offset: 0x804 (R/ 32) General Status Register */ + __O uint32_t USBHS_SCR; /**< Offset: 0x808 ( /W 32) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< Offset: 0x80C ( /W 32) General Status Set Register */ +} usbhs_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_USBHS_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/utmi.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/utmi.h new file mode 100644 index 00000000..f56d0dcf --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/utmi.h @@ -0,0 +1,77 @@ +/** + * \brief Component description for UTMI + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_UTMI_COMPONENT_H_ +#define _SAME70_UTMI_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR UTMI */ +/* ************************************************************************** */ + +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) (R/W 32) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0_Pos _U_(0) /**< (UTMI_OHCIICR) USB PORTx Reset Position */ +#define UTMI_OHCIICR_RES0_Msk (_U_(0x1) << UTMI_OHCIICR_RES0_Pos) /**< (UTMI_OHCIICR) USB PORTx Reset Mask */ +#define UTMI_OHCIICR_RES0(value) (UTMI_OHCIICR_RES0_Msk & ((value) << UTMI_OHCIICR_RES0_Pos)) +#define UTMI_OHCIICR_ARIE_Pos _U_(4) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Position */ +#define UTMI_OHCIICR_ARIE_Msk (_U_(0x1) << UTMI_OHCIICR_ARIE_Pos) /**< (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable Mask */ +#define UTMI_OHCIICR_ARIE(value) (UTMI_OHCIICR_ARIE_Msk & ((value) << UTMI_OHCIICR_ARIE_Pos)) +#define UTMI_OHCIICR_APPSTART_Pos _U_(5) /**< (UTMI_OHCIICR) Reserved Position */ +#define UTMI_OHCIICR_APPSTART_Msk (_U_(0x1) << UTMI_OHCIICR_APPSTART_Pos) /**< (UTMI_OHCIICR) Reserved Mask */ +#define UTMI_OHCIICR_APPSTART(value) (UTMI_OHCIICR_APPSTART_Msk & ((value) << UTMI_OHCIICR_APPSTART_Pos)) +#define UTMI_OHCIICR_UDPPUDIS_Pos _U_(23) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Position */ +#define UTMI_OHCIICR_UDPPUDIS_Msk (_U_(0x1) << UTMI_OHCIICR_UDPPUDIS_Pos) /**< (UTMI_OHCIICR) USB Device Pull-up Disable Mask */ +#define UTMI_OHCIICR_UDPPUDIS(value) (UTMI_OHCIICR_UDPPUDIS_Msk & ((value) << UTMI_OHCIICR_UDPPUDIS_Pos)) +#define UTMI_OHCIICR_Msk _U_(0x00800031) /**< (UTMI_OHCIICR) Register Mask */ + +#define UTMI_OHCIICR_RES_Pos _U_(0) /**< (UTMI_OHCIICR Position) USB PORTx Reset */ +#define UTMI_OHCIICR_RES_Msk (_U_(0x1) << UTMI_OHCIICR_RES_Pos) /**< (UTMI_OHCIICR Mask) RES */ +#define UTMI_OHCIICR_RES(value) (UTMI_OHCIICR_RES_Msk & ((value) << UTMI_OHCIICR_RES_Pos)) + +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) (R/W 32) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos _U_(0) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Position */ +#define UTMI_CKTRIM_FREQ_Msk (_U_(0x3) << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) UTMI Reference Clock Frequency Mask */ +#define UTMI_CKTRIM_FREQ(value) (UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)) +#define UTMI_CKTRIM_FREQ_XTAL12_Val _U_(0x0) /**< (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16_Val _U_(0x1) /**< (UTMI_CKTRIM) 16 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL12 (UTMI_CKTRIM_FREQ_XTAL12_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 12 MHz reference clock Position */ +#define UTMI_CKTRIM_FREQ_XTAL16 (UTMI_CKTRIM_FREQ_XTAL16_Val << UTMI_CKTRIM_FREQ_Pos) /**< (UTMI_CKTRIM) 16 MHz reference clock Position */ +#define UTMI_CKTRIM_Msk _U_(0x00000003) /**< (UTMI_CKTRIM) Register Mask */ + + +/** \brief UTMI register offsets definitions */ +#define UTMI_OHCIICR_REG_OFST (0x10) /**< (UTMI_OHCIICR) OHCI Interrupt Configuration Register Offset */ +#define UTMI_CKTRIM_REG_OFST (0x30) /**< (UTMI_CKTRIM) UTMI Clock Trimming Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UTMI register API structure */ +typedef struct +{ + __I uint8_t Reserved1[0x10]; + __IO uint32_t UTMI_OHCIICR; /**< Offset: 0x10 (R/W 32) OHCI Interrupt Configuration Register */ + __I uint8_t Reserved2[0x1C]; + __IO uint32_t UTMI_CKTRIM; /**< Offset: 0x30 (R/W 32) UTMI Clock Trimming Register */ +} utmi_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_UTMI_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/wdt.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/wdt.h new file mode 100644 index 00000000..2bddfc71 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/wdt.h @@ -0,0 +1,94 @@ +/** + * \brief Component description for WDT + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_WDT_COMPONENT_H_ +#define _SAME70_WDT_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR WDT */ +/* ************************************************************************** */ + +/* -------- WDT_CR : (WDT Offset: 0x00) ( /W 32) Control Register -------- */ +#define WDT_CR_WDRSTT_Pos _U_(0) /**< (WDT_CR) Watchdog Restart Position */ +#define WDT_CR_WDRSTT_Msk (_U_(0x1) << WDT_CR_WDRSTT_Pos) /**< (WDT_CR) Watchdog Restart Mask */ +#define WDT_CR_WDRSTT(value) (WDT_CR_WDRSTT_Msk & ((value) << WDT_CR_WDRSTT_Pos)) +#define WDT_CR_KEY_Pos _U_(24) /**< (WDT_CR) Password Position */ +#define WDT_CR_KEY_Msk (_U_(0xFF) << WDT_CR_KEY_Pos) /**< (WDT_CR) Password Mask */ +#define WDT_CR_KEY(value) (WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)) +#define WDT_CR_KEY_PASSWD_Val _U_(0xA5) /**< (WDT_CR) Writing any other value in this field aborts the write operation. */ +#define WDT_CR_KEY_PASSWD (WDT_CR_KEY_PASSWD_Val << WDT_CR_KEY_Pos) /**< (WDT_CR) Writing any other value in this field aborts the write operation. Position */ +#define WDT_CR_Msk _U_(0xFF000001) /**< (WDT_CR) Register Mask */ + + +/* -------- WDT_MR : (WDT Offset: 0x04) (R/W 32) Mode Register -------- */ +#define WDT_MR_WDV_Pos _U_(0) /**< (WDT_MR) Watchdog Counter Value Position */ +#define WDT_MR_WDV_Msk (_U_(0xFFF) << WDT_MR_WDV_Pos) /**< (WDT_MR) Watchdog Counter Value Mask */ +#define WDT_MR_WDV(value) (WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)) +#define WDT_MR_WDFIEN_Pos _U_(12) /**< (WDT_MR) Watchdog Fault Interrupt Enable Position */ +#define WDT_MR_WDFIEN_Msk (_U_(0x1) << WDT_MR_WDFIEN_Pos) /**< (WDT_MR) Watchdog Fault Interrupt Enable Mask */ +#define WDT_MR_WDFIEN(value) (WDT_MR_WDFIEN_Msk & ((value) << WDT_MR_WDFIEN_Pos)) +#define WDT_MR_WDRSTEN_Pos _U_(13) /**< (WDT_MR) Watchdog Reset Enable Position */ +#define WDT_MR_WDRSTEN_Msk (_U_(0x1) << WDT_MR_WDRSTEN_Pos) /**< (WDT_MR) Watchdog Reset Enable Mask */ +#define WDT_MR_WDRSTEN(value) (WDT_MR_WDRSTEN_Msk & ((value) << WDT_MR_WDRSTEN_Pos)) +#define WDT_MR_WDDIS_Pos _U_(15) /**< (WDT_MR) Watchdog Disable Position */ +#define WDT_MR_WDDIS_Msk (_U_(0x1) << WDT_MR_WDDIS_Pos) /**< (WDT_MR) Watchdog Disable Mask */ +#define WDT_MR_WDDIS(value) (WDT_MR_WDDIS_Msk & ((value) << WDT_MR_WDDIS_Pos)) +#define WDT_MR_WDD_Pos _U_(16) /**< (WDT_MR) Watchdog Delta Value Position */ +#define WDT_MR_WDD_Msk (_U_(0xFFF) << WDT_MR_WDD_Pos) /**< (WDT_MR) Watchdog Delta Value Mask */ +#define WDT_MR_WDD(value) (WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)) +#define WDT_MR_WDDBGHLT_Pos _U_(28) /**< (WDT_MR) Watchdog Debug Halt Position */ +#define WDT_MR_WDDBGHLT_Msk (_U_(0x1) << WDT_MR_WDDBGHLT_Pos) /**< (WDT_MR) Watchdog Debug Halt Mask */ +#define WDT_MR_WDDBGHLT(value) (WDT_MR_WDDBGHLT_Msk & ((value) << WDT_MR_WDDBGHLT_Pos)) +#define WDT_MR_WDIDLEHLT_Pos _U_(29) /**< (WDT_MR) Watchdog Idle Halt Position */ +#define WDT_MR_WDIDLEHLT_Msk (_U_(0x1) << WDT_MR_WDIDLEHLT_Pos) /**< (WDT_MR) Watchdog Idle Halt Mask */ +#define WDT_MR_WDIDLEHLT(value) (WDT_MR_WDIDLEHLT_Msk & ((value) << WDT_MR_WDIDLEHLT_Pos)) +#define WDT_MR_Msk _U_(0x3FFFBFFF) /**< (WDT_MR) Register Mask */ + + +/* -------- WDT_SR : (WDT Offset: 0x08) ( R/ 32) Status Register -------- */ +#define WDT_SR_WDUNF_Pos _U_(0) /**< (WDT_SR) Watchdog Underflow (cleared on read) Position */ +#define WDT_SR_WDUNF_Msk (_U_(0x1) << WDT_SR_WDUNF_Pos) /**< (WDT_SR) Watchdog Underflow (cleared on read) Mask */ +#define WDT_SR_WDUNF(value) (WDT_SR_WDUNF_Msk & ((value) << WDT_SR_WDUNF_Pos)) +#define WDT_SR_WDERR_Pos _U_(1) /**< (WDT_SR) Watchdog Error (cleared on read) Position */ +#define WDT_SR_WDERR_Msk (_U_(0x1) << WDT_SR_WDERR_Pos) /**< (WDT_SR) Watchdog Error (cleared on read) Mask */ +#define WDT_SR_WDERR(value) (WDT_SR_WDERR_Msk & ((value) << WDT_SR_WDERR_Pos)) +#define WDT_SR_Msk _U_(0x00000003) /**< (WDT_SR) Register Mask */ + + +/** \brief WDT register offsets definitions */ +#define WDT_CR_REG_OFST (0x00) /**< (WDT_CR) Control Register Offset */ +#define WDT_MR_REG_OFST (0x04) /**< (WDT_MR) Mode Register Offset */ +#define WDT_SR_REG_OFST (0x08) /**< (WDT_SR) Status Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief WDT register API structure */ +typedef struct +{ + __O uint32_t WDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ + __IO uint32_t WDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ + __I uint32_t WDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ +} wdt_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_WDT_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/component/xdmac.h b/arch/arm/SAME70/SAME70B/mcu/inc/component/xdmac.h new file mode 100644 index 00000000..37b56e37 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/component/xdmac.h @@ -0,0 +1,1694 @@ +/** + * \brief Component description for XDMAC + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70_XDMAC_COMPONENT_H_ +#define _SAME70_XDMAC_COMPONENT_H_ + +/* ************************************************************************** */ +/* SOFTWARE API DEFINITION FOR XDMAC */ +/* ************************************************************************** */ + +/* -------- XDMAC_CIE : (XDMAC Offset: 0x00) ( /W 32) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE_Pos _U_(0) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Position */ +#define XDMAC_CIE_BIE_Msk (_U_(0x1) << XDMAC_CIE_BIE_Pos) /**< (XDMAC_CIE) End of Block Interrupt Enable Bit Mask */ +#define XDMAC_CIE_BIE(value) (XDMAC_CIE_BIE_Msk & ((value) << XDMAC_CIE_BIE_Pos)) +#define XDMAC_CIE_LIE_Pos _U_(1) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Position */ +#define XDMAC_CIE_LIE_Msk (_U_(0x1) << XDMAC_CIE_LIE_Pos) /**< (XDMAC_CIE) End of Linked List Interrupt Enable Bit Mask */ +#define XDMAC_CIE_LIE(value) (XDMAC_CIE_LIE_Msk & ((value) << XDMAC_CIE_LIE_Pos)) +#define XDMAC_CIE_DIE_Pos _U_(2) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Position */ +#define XDMAC_CIE_DIE_Msk (_U_(0x1) << XDMAC_CIE_DIE_Pos) /**< (XDMAC_CIE) End of Disable Interrupt Enable Bit Mask */ +#define XDMAC_CIE_DIE(value) (XDMAC_CIE_DIE_Msk & ((value) << XDMAC_CIE_DIE_Pos)) +#define XDMAC_CIE_FIE_Pos _U_(3) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Position */ +#define XDMAC_CIE_FIE_Msk (_U_(0x1) << XDMAC_CIE_FIE_Pos) /**< (XDMAC_CIE) End of Flush Interrupt Enable Bit Mask */ +#define XDMAC_CIE_FIE(value) (XDMAC_CIE_FIE_Msk & ((value) << XDMAC_CIE_FIE_Pos)) +#define XDMAC_CIE_RBIE_Pos _U_(4) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_RBIE_Msk (_U_(0x1) << XDMAC_CIE_RBIE_Pos) /**< (XDMAC_CIE) Read Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_RBIE(value) (XDMAC_CIE_RBIE_Msk & ((value) << XDMAC_CIE_RBIE_Pos)) +#define XDMAC_CIE_WBIE_Pos _U_(5) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_WBIE_Msk (_U_(0x1) << XDMAC_CIE_WBIE_Pos) /**< (XDMAC_CIE) Write Bus Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_WBIE(value) (XDMAC_CIE_WBIE_Msk & ((value) << XDMAC_CIE_WBIE_Pos)) +#define XDMAC_CIE_ROIE_Pos _U_(6) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Position */ +#define XDMAC_CIE_ROIE_Msk (_U_(0x1) << XDMAC_CIE_ROIE_Pos) /**< (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit Mask */ +#define XDMAC_CIE_ROIE(value) (XDMAC_CIE_ROIE_Msk & ((value) << XDMAC_CIE_ROIE_Pos)) +#define XDMAC_CIE_Msk _U_(0x0000007F) /**< (XDMAC_CIE) Register Mask */ + + +/* -------- XDMAC_CID : (XDMAC Offset: 0x04) ( /W 32) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID_Pos _U_(0) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Position */ +#define XDMAC_CID_BID_Msk (_U_(0x1) << XDMAC_CID_BID_Pos) /**< (XDMAC_CID) End of Block Interrupt Disable Bit Mask */ +#define XDMAC_CID_BID(value) (XDMAC_CID_BID_Msk & ((value) << XDMAC_CID_BID_Pos)) +#define XDMAC_CID_LID_Pos _U_(1) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Position */ +#define XDMAC_CID_LID_Msk (_U_(0x1) << XDMAC_CID_LID_Pos) /**< (XDMAC_CID) End of Linked List Interrupt Disable Bit Mask */ +#define XDMAC_CID_LID(value) (XDMAC_CID_LID_Msk & ((value) << XDMAC_CID_LID_Pos)) +#define XDMAC_CID_DID_Pos _U_(2) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Position */ +#define XDMAC_CID_DID_Msk (_U_(0x1) << XDMAC_CID_DID_Pos) /**< (XDMAC_CID) End of Disable Interrupt Disable Bit Mask */ +#define XDMAC_CID_DID(value) (XDMAC_CID_DID_Msk & ((value) << XDMAC_CID_DID_Pos)) +#define XDMAC_CID_FID_Pos _U_(3) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Position */ +#define XDMAC_CID_FID_Msk (_U_(0x1) << XDMAC_CID_FID_Pos) /**< (XDMAC_CID) End of Flush Interrupt Disable Bit Mask */ +#define XDMAC_CID_FID(value) (XDMAC_CID_FID_Msk & ((value) << XDMAC_CID_FID_Pos)) +#define XDMAC_CID_RBEID_Pos _U_(4) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_RBEID_Msk (_U_(0x1) << XDMAC_CID_RBEID_Pos) /**< (XDMAC_CID) Read Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_RBEID(value) (XDMAC_CID_RBEID_Msk & ((value) << XDMAC_CID_RBEID_Pos)) +#define XDMAC_CID_WBEID_Pos _U_(5) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Position */ +#define XDMAC_CID_WBEID_Msk (_U_(0x1) << XDMAC_CID_WBEID_Pos) /**< (XDMAC_CID) Write Bus Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_WBEID(value) (XDMAC_CID_WBEID_Msk & ((value) << XDMAC_CID_WBEID_Pos)) +#define XDMAC_CID_ROID_Pos _U_(6) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Position */ +#define XDMAC_CID_ROID_Msk (_U_(0x1) << XDMAC_CID_ROID_Pos) /**< (XDMAC_CID) Request Overflow Error Interrupt Disable Bit Mask */ +#define XDMAC_CID_ROID(value) (XDMAC_CID_ROID_Msk & ((value) << XDMAC_CID_ROID_Pos)) +#define XDMAC_CID_Msk _U_(0x0000007F) /**< (XDMAC_CID) Register Mask */ + + +/* -------- XDMAC_CIM : (XDMAC Offset: 0x08) ( R/ 32) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM_Pos _U_(0) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Position */ +#define XDMAC_CIM_BIM_Msk (_U_(0x1) << XDMAC_CIM_BIM_Pos) /**< (XDMAC_CIM) End of Block Interrupt Mask Bit Mask */ +#define XDMAC_CIM_BIM(value) (XDMAC_CIM_BIM_Msk & ((value) << XDMAC_CIM_BIM_Pos)) +#define XDMAC_CIM_LIM_Pos _U_(1) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Position */ +#define XDMAC_CIM_LIM_Msk (_U_(0x1) << XDMAC_CIM_LIM_Pos) /**< (XDMAC_CIM) End of Linked List Interrupt Mask Bit Mask */ +#define XDMAC_CIM_LIM(value) (XDMAC_CIM_LIM_Msk & ((value) << XDMAC_CIM_LIM_Pos)) +#define XDMAC_CIM_DIM_Pos _U_(2) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Position */ +#define XDMAC_CIM_DIM_Msk (_U_(0x1) << XDMAC_CIM_DIM_Pos) /**< (XDMAC_CIM) End of Disable Interrupt Mask Bit Mask */ +#define XDMAC_CIM_DIM(value) (XDMAC_CIM_DIM_Msk & ((value) << XDMAC_CIM_DIM_Pos)) +#define XDMAC_CIM_FIM_Pos _U_(3) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Position */ +#define XDMAC_CIM_FIM_Msk (_U_(0x1) << XDMAC_CIM_FIM_Pos) /**< (XDMAC_CIM) End of Flush Interrupt Mask Bit Mask */ +#define XDMAC_CIM_FIM(value) (XDMAC_CIM_FIM_Msk & ((value) << XDMAC_CIM_FIM_Pos)) +#define XDMAC_CIM_RBEIM_Pos _U_(4) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_RBEIM_Msk (_U_(0x1) << XDMAC_CIM_RBEIM_Pos) /**< (XDMAC_CIM) Read Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_RBEIM(value) (XDMAC_CIM_RBEIM_Msk & ((value) << XDMAC_CIM_RBEIM_Pos)) +#define XDMAC_CIM_WBEIM_Pos _U_(5) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_WBEIM_Msk (_U_(0x1) << XDMAC_CIM_WBEIM_Pos) /**< (XDMAC_CIM) Write Bus Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_WBEIM(value) (XDMAC_CIM_WBEIM_Msk & ((value) << XDMAC_CIM_WBEIM_Pos)) +#define XDMAC_CIM_ROIM_Pos _U_(6) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Position */ +#define XDMAC_CIM_ROIM_Msk (_U_(0x1) << XDMAC_CIM_ROIM_Pos) /**< (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit Mask */ +#define XDMAC_CIM_ROIM(value) (XDMAC_CIM_ROIM_Msk & ((value) << XDMAC_CIM_ROIM_Pos)) +#define XDMAC_CIM_Msk _U_(0x0000007F) /**< (XDMAC_CIM) Register Mask */ + + +/* -------- XDMAC_CIS : (XDMAC Offset: 0x0C) ( R/ 32) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS_Pos _U_(0) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Position */ +#define XDMAC_CIS_BIS_Msk (_U_(0x1) << XDMAC_CIS_BIS_Pos) /**< (XDMAC_CIS) End of Block Interrupt Status Bit Mask */ +#define XDMAC_CIS_BIS(value) (XDMAC_CIS_BIS_Msk & ((value) << XDMAC_CIS_BIS_Pos)) +#define XDMAC_CIS_LIS_Pos _U_(1) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Position */ +#define XDMAC_CIS_LIS_Msk (_U_(0x1) << XDMAC_CIS_LIS_Pos) /**< (XDMAC_CIS) End of Linked List Interrupt Status Bit Mask */ +#define XDMAC_CIS_LIS(value) (XDMAC_CIS_LIS_Msk & ((value) << XDMAC_CIS_LIS_Pos)) +#define XDMAC_CIS_DIS_Pos _U_(2) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Position */ +#define XDMAC_CIS_DIS_Msk (_U_(0x1) << XDMAC_CIS_DIS_Pos) /**< (XDMAC_CIS) End of Disable Interrupt Status Bit Mask */ +#define XDMAC_CIS_DIS(value) (XDMAC_CIS_DIS_Msk & ((value) << XDMAC_CIS_DIS_Pos)) +#define XDMAC_CIS_FIS_Pos _U_(3) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Position */ +#define XDMAC_CIS_FIS_Msk (_U_(0x1) << XDMAC_CIS_FIS_Pos) /**< (XDMAC_CIS) End of Flush Interrupt Status Bit Mask */ +#define XDMAC_CIS_FIS(value) (XDMAC_CIS_FIS_Msk & ((value) << XDMAC_CIS_FIS_Pos)) +#define XDMAC_CIS_RBEIS_Pos _U_(4) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_RBEIS_Msk (_U_(0x1) << XDMAC_CIS_RBEIS_Pos) /**< (XDMAC_CIS) Read Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_RBEIS(value) (XDMAC_CIS_RBEIS_Msk & ((value) << XDMAC_CIS_RBEIS_Pos)) +#define XDMAC_CIS_WBEIS_Pos _U_(5) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Position */ +#define XDMAC_CIS_WBEIS_Msk (_U_(0x1) << XDMAC_CIS_WBEIS_Pos) /**< (XDMAC_CIS) Write Bus Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_WBEIS(value) (XDMAC_CIS_WBEIS_Msk & ((value) << XDMAC_CIS_WBEIS_Pos)) +#define XDMAC_CIS_ROIS_Pos _U_(6) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Position */ +#define XDMAC_CIS_ROIS_Msk (_U_(0x1) << XDMAC_CIS_ROIS_Pos) /**< (XDMAC_CIS) Request Overflow Error Interrupt Status Bit Mask */ +#define XDMAC_CIS_ROIS(value) (XDMAC_CIS_ROIS_Msk & ((value) << XDMAC_CIS_ROIS_Pos)) +#define XDMAC_CIS_Msk _U_(0x0000007F) /**< (XDMAC_CIS) Register Mask */ + + +/* -------- XDMAC_CSA : (XDMAC Offset: 0x10) (R/W 32) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos _U_(0) /**< (XDMAC_CSA) Channel x Source Address Position */ +#define XDMAC_CSA_SA_Msk (_U_(0xFFFFFFFF) << XDMAC_CSA_SA_Pos) /**< (XDMAC_CSA) Channel x Source Address Mask */ +#define XDMAC_CSA_SA(value) (XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)) +#define XDMAC_CSA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CSA) Register Mask */ + + +/* -------- XDMAC_CDA : (XDMAC Offset: 0x14) (R/W 32) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos _U_(0) /**< (XDMAC_CDA) Channel x Destination Address Position */ +#define XDMAC_CDA_DA_Msk (_U_(0xFFFFFFFF) << XDMAC_CDA_DA_Pos) /**< (XDMAC_CDA) Channel x Destination Address Mask */ +#define XDMAC_CDA_DA(value) (XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)) +#define XDMAC_CDA_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDA) Register Mask */ + + +/* -------- XDMAC_CNDA : (XDMAC Offset: 0x18) (R/W 32) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF_Pos _U_(0) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Position */ +#define XDMAC_CNDA_NDAIF_Msk (_U_(0x1) << XDMAC_CNDA_NDAIF_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Interface Mask */ +#define XDMAC_CNDA_NDAIF(value) (XDMAC_CNDA_NDAIF_Msk & ((value) << XDMAC_CNDA_NDAIF_Pos)) +#define XDMAC_CNDA_NDA_Pos _U_(2) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Position */ +#define XDMAC_CNDA_NDA_Msk (_U_(0x3FFFFFFF) << XDMAC_CNDA_NDA_Pos) /**< (XDMAC_CNDA) Channel x Next Descriptor Address Mask */ +#define XDMAC_CNDA_NDA(value) (XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)) +#define XDMAC_CNDA_Msk _U_(0xFFFFFFFD) /**< (XDMAC_CNDA) Register Mask */ + + +/* -------- XDMAC_CNDC : (XDMAC Offset: 0x1C) (R/W 32) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE_Pos _U_(0) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Position */ +#define XDMAC_CNDC_NDE_Msk (_U_(0x1) << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Enable Mask */ +#define XDMAC_CNDC_NDE(value) (XDMAC_CNDC_NDE_Msk & ((value) << XDMAC_CNDC_NDE_Pos)) +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val _U_(0x0) /**< (XDMAC_CNDC) Descriptor fetch is disabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val _U_(0x1) /**< (XDMAC_CNDC) Descriptor fetch is enabled. */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (XDMAC_CNDC_NDE_DSCR_FETCH_DIS_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is disabled. Position */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (XDMAC_CNDC_NDE_DSCR_FETCH_EN_Val << XDMAC_CNDC_NDE_Pos) /**< (XDMAC_CNDC) Descriptor fetch is enabled. Position */ +#define XDMAC_CNDC_NDSUP_Pos _U_(1) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Position */ +#define XDMAC_CNDC_NDSUP_Msk (_U_(0x1) << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Source Update Mask */ +#define XDMAC_CNDC_NDSUP(value) (XDMAC_CNDC_NDSUP_Msk & ((value) << XDMAC_CNDC_NDSUP_Pos)) +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED_Val << XDMAC_CNDC_NDSUP_Pos) /**< (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDDUP_Pos _U_(2) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Position */ +#define XDMAC_CNDC_NDDUP_Msk (_U_(0x1) << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor Destination Update Mask */ +#define XDMAC_CNDC_NDDUP(value) (XDMAC_CNDC_NDDUP_Msk & ((value) << XDMAC_CNDC_NDDUP_Pos)) +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val _U_(0x0) /**< (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val _U_(0x1) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters remain unchanged. Position */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED_Val << XDMAC_CNDC_NDDUP_Pos) /**< (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. Position */ +#define XDMAC_CNDC_NDVIEW_Pos _U_(3) /**< (XDMAC_CNDC) Channel x Next Descriptor View Position */ +#define XDMAC_CNDC_NDVIEW_Msk (_U_(0x3) << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Channel x Next Descriptor View Mask */ +#define XDMAC_CNDC_NDVIEW(value) (XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)) +#define XDMAC_CNDC_NDVIEW_NDV0_Val _U_(0x0) /**< (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1_Val _U_(0x1) /**< (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2_Val _U_(0x2) /**< (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3_Val _U_(0x3) /**< (XDMAC_CNDC) Next Descriptor View 3 */ +#define XDMAC_CNDC_NDVIEW_NDV0 (XDMAC_CNDC_NDVIEW_NDV0_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 0 Position */ +#define XDMAC_CNDC_NDVIEW_NDV1 (XDMAC_CNDC_NDVIEW_NDV1_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 1 Position */ +#define XDMAC_CNDC_NDVIEW_NDV2 (XDMAC_CNDC_NDVIEW_NDV2_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 2 Position */ +#define XDMAC_CNDC_NDVIEW_NDV3 (XDMAC_CNDC_NDVIEW_NDV3_Val << XDMAC_CNDC_NDVIEW_Pos) /**< (XDMAC_CNDC) Next Descriptor View 3 Position */ +#define XDMAC_CNDC_Msk _U_(0x0000001F) /**< (XDMAC_CNDC) Register Mask */ + + +/* -------- XDMAC_CUBC : (XDMAC Offset: 0x20) (R/W 32) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos _U_(0) /**< (XDMAC_CUBC) Channel x Microblock Length Position */ +#define XDMAC_CUBC_UBLEN_Msk (_U_(0xFFFFFF) << XDMAC_CUBC_UBLEN_Pos) /**< (XDMAC_CUBC) Channel x Microblock Length Mask */ +#define XDMAC_CUBC_UBLEN(value) (XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)) +#define XDMAC_CUBC_Msk _U_(0x00FFFFFF) /**< (XDMAC_CUBC) Register Mask */ + + +/* -------- XDMAC_CBC : (XDMAC Offset: 0x24) (R/W 32) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos _U_(0) /**< (XDMAC_CBC) Channel x Block Length Position */ +#define XDMAC_CBC_BLEN_Msk (_U_(0xFFF) << XDMAC_CBC_BLEN_Pos) /**< (XDMAC_CBC) Channel x Block Length Mask */ +#define XDMAC_CBC_BLEN(value) (XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)) +#define XDMAC_CBC_Msk _U_(0x00000FFF) /**< (XDMAC_CBC) Register Mask */ + + +/* -------- XDMAC_CC : (XDMAC Offset: 0x28) (R/W 32) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE_Pos _U_(0) /**< (XDMAC_CC) Channel x Transfer Type Position */ +#define XDMAC_CC_TYPE_Msk (_U_(0x1) << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Channel x Transfer Type Mask */ +#define XDMAC_CC_TYPE(value) (XDMAC_CC_TYPE_Msk & ((value) << XDMAC_CC_TYPE_Pos)) +#define XDMAC_CC_TYPE_MEM_TRAN_Val _U_(0x0) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN_Val _U_(0x1) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). */ +#define XDMAC_CC_TYPE_MEM_TRAN (XDMAC_CC_TYPE_MEM_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Self-triggered mode (memory-to-memory transfer). Position */ +#define XDMAC_CC_TYPE_PER_TRAN (XDMAC_CC_TYPE_PER_TRAN_Val << XDMAC_CC_TYPE_Pos) /**< (XDMAC_CC) Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer). Position */ +#define XDMAC_CC_MBSIZE_Pos _U_(1) /**< (XDMAC_CC) Channel x Memory Burst Size Position */ +#define XDMAC_CC_MBSIZE_Msk (_U_(0x3) << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) Channel x Memory Burst Size Mask */ +#define XDMAC_CC_MBSIZE(value) (XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)) +#define XDMAC_CC_MBSIZE_SINGLE_Val _U_(0x0) /**< (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR_Val _U_(0x1) /**< (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT_Val _U_(0x2) /**< (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN_Val _U_(0x3) /**< (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_MBSIZE_SINGLE (XDMAC_CC_MBSIZE_SINGLE_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to one. Position */ +#define XDMAC_CC_MBSIZE_FOUR (XDMAC_CC_MBSIZE_FOUR_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to four. Position */ +#define XDMAC_CC_MBSIZE_EIGHT (XDMAC_CC_MBSIZE_EIGHT_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to eight. Position */ +#define XDMAC_CC_MBSIZE_SIXTEEN (XDMAC_CC_MBSIZE_SIXTEEN_Val << XDMAC_CC_MBSIZE_Pos) /**< (XDMAC_CC) The memory burst size is set to sixteen. Position */ +#define XDMAC_CC_DSYNC_Pos _U_(4) /**< (XDMAC_CC) Channel x Synchronization Position */ +#define XDMAC_CC_DSYNC_Msk (_U_(0x1) << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Channel x Synchronization Mask */ +#define XDMAC_CC_DSYNC(value) (XDMAC_CC_DSYNC_Msk & ((value) << XDMAC_CC_DSYNC_Pos)) +#define XDMAC_CC_DSYNC_PER2MEM_Val _U_(0x0) /**< (XDMAC_CC) Peripheral-to-memory transfer. */ +#define XDMAC_CC_DSYNC_MEM2PER_Val _U_(0x1) /**< (XDMAC_CC) Memory-to-peripheral transfer. */ +#define XDMAC_CC_DSYNC_PER2MEM (XDMAC_CC_DSYNC_PER2MEM_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Peripheral-to-memory transfer. Position */ +#define XDMAC_CC_DSYNC_MEM2PER (XDMAC_CC_DSYNC_MEM2PER_Val << XDMAC_CC_DSYNC_Pos) /**< (XDMAC_CC) Memory-to-peripheral transfer. Position */ +#define XDMAC_CC_SWREQ_Pos _U_(6) /**< (XDMAC_CC) Channel x Software Request Trigger Position */ +#define XDMAC_CC_SWREQ_Msk (_U_(0x1) << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Channel x Software Request Trigger Mask */ +#define XDMAC_CC_SWREQ(value) (XDMAC_CC_SWREQ_Msk & ((value) << XDMAC_CC_SWREQ_Pos)) +#define XDMAC_CC_SWREQ_HWR_CONNECTED_Val _U_(0x0) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED_Val _U_(0x1) /**< (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (XDMAC_CC_SWREQ_HWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Hardware request line is connected to the peripheral request line. Position */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (XDMAC_CC_SWREQ_SWR_CONNECTED_Val << XDMAC_CC_SWREQ_Pos) /**< (XDMAC_CC) Software request is connected to the peripheral request line. Position */ +#define XDMAC_CC_MEMSET_Pos _U_(7) /**< (XDMAC_CC) Channel x Fill Block of memory Position */ +#define XDMAC_CC_MEMSET_Msk (_U_(0x1) << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Channel x Fill Block of memory Mask */ +#define XDMAC_CC_MEMSET(value) (XDMAC_CC_MEMSET_Msk & ((value) << XDMAC_CC_MEMSET_Pos)) +#define XDMAC_CC_MEMSET_NORMAL_MODE_Val _U_(0x0) /**< (XDMAC_CC) Memset is not activated. */ +#define XDMAC_CC_MEMSET_HW_MODE_Val _U_(0x1) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (XDMAC_CC_MEMSET_NORMAL_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Memset is not activated. Position */ +#define XDMAC_CC_MEMSET_HW_MODE (XDMAC_CC_MEMSET_HW_MODE_Val << XDMAC_CC_MEMSET_Pos) /**< (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. Position */ +#define XDMAC_CC_CSIZE_Pos _U_(8) /**< (XDMAC_CC) Channel x Chunk Size Position */ +#define XDMAC_CC_CSIZE_Msk (_U_(0x7) << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) Channel x Chunk Size Mask */ +#define XDMAC_CC_CSIZE(value) (XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)) +#define XDMAC_CC_CSIZE_CHK_1_Val _U_(0x0) /**< (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2_Val _U_(0x1) /**< (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4_Val _U_(0x2) /**< (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8_Val _U_(0x3) /**< (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16_Val _U_(0x4) /**< (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_CSIZE_CHK_1 (XDMAC_CC_CSIZE_CHK_1_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 1 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_2 (XDMAC_CC_CSIZE_CHK_2_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 2 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_4 (XDMAC_CC_CSIZE_CHK_4_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 4 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_8 (XDMAC_CC_CSIZE_CHK_8_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 8 data transferred Position */ +#define XDMAC_CC_CSIZE_CHK_16 (XDMAC_CC_CSIZE_CHK_16_Val << XDMAC_CC_CSIZE_Pos) /**< (XDMAC_CC) 16 data transferred Position */ +#define XDMAC_CC_DWIDTH_Pos _U_(11) /**< (XDMAC_CC) Channel x Data Width Position */ +#define XDMAC_CC_DWIDTH_Msk (_U_(0x3) << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) Channel x Data Width Mask */ +#define XDMAC_CC_DWIDTH(value) (XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)) +#define XDMAC_CC_DWIDTH_BYTE_Val _U_(0x0) /**< (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD_Val _U_(0x1) /**< (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD_Val _U_(0x2) /**< (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_DWIDTH_BYTE (XDMAC_CC_DWIDTH_BYTE_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 8 bits Position */ +#define XDMAC_CC_DWIDTH_HALFWORD (XDMAC_CC_DWIDTH_HALFWORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 16 bits Position */ +#define XDMAC_CC_DWIDTH_WORD (XDMAC_CC_DWIDTH_WORD_Val << XDMAC_CC_DWIDTH_Pos) /**< (XDMAC_CC) The data size is set to 32 bits Position */ +#define XDMAC_CC_SIF_Pos _U_(13) /**< (XDMAC_CC) Channel x Source Interface Identifier Position */ +#define XDMAC_CC_SIF_Msk (_U_(0x1) << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) Channel x Source Interface Identifier Mask */ +#define XDMAC_CC_SIF(value) (XDMAC_CC_SIF_Msk & ((value) << XDMAC_CC_SIF_Pos)) +#define XDMAC_CC_SIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is read through the system bus interface 0. */ +#define XDMAC_CC_SIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is read through the system bus interface 1. */ +#define XDMAC_CC_SIF_AHB_IF0 (XDMAC_CC_SIF_AHB_IF0_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 0. Position */ +#define XDMAC_CC_SIF_AHB_IF1 (XDMAC_CC_SIF_AHB_IF1_Val << XDMAC_CC_SIF_Pos) /**< (XDMAC_CC) The data is read through the system bus interface 1. Position */ +#define XDMAC_CC_DIF_Pos _U_(14) /**< (XDMAC_CC) Channel x Destination Interface Identifier Position */ +#define XDMAC_CC_DIF_Msk (_U_(0x1) << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) Channel x Destination Interface Identifier Mask */ +#define XDMAC_CC_DIF(value) (XDMAC_CC_DIF_Msk & ((value) << XDMAC_CC_DIF_Pos)) +#define XDMAC_CC_DIF_AHB_IF0_Val _U_(0x0) /**< (XDMAC_CC) The data is written through the system bus interface 0. */ +#define XDMAC_CC_DIF_AHB_IF1_Val _U_(0x1) /**< (XDMAC_CC) The data is written though the system bus interface 1. */ +#define XDMAC_CC_DIF_AHB_IF0 (XDMAC_CC_DIF_AHB_IF0_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written through the system bus interface 0. Position */ +#define XDMAC_CC_DIF_AHB_IF1 (XDMAC_CC_DIF_AHB_IF1_Val << XDMAC_CC_DIF_Pos) /**< (XDMAC_CC) The data is written though the system bus interface 1. Position */ +#define XDMAC_CC_SAM_Pos _U_(16) /**< (XDMAC_CC) Channel x Source Addressing Mode Position */ +#define XDMAC_CC_SAM_Msk (_U_(0x3) << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) Channel x Source Addressing Mode Mask */ +#define XDMAC_CC_SAM(value) (XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)) +#define XDMAC_CC_SAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_SAM_FIXED_AM (XDMAC_CC_SAM_FIXED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_SAM_INCREMENTED_AM (XDMAC_CC_SAM_INCREMENTED_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_SAM_UBS_AM (XDMAC_CC_SAM_UBS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_SAM_UBS_DS_AM (XDMAC_CC_SAM_UBS_DS_AM_Val << XDMAC_CC_SAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. Position */ +#define XDMAC_CC_DAM_Pos _U_(18) /**< (XDMAC_CC) Channel x Destination Addressing Mode Position */ +#define XDMAC_CC_DAM_Msk (_U_(0x3) << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) Channel x Destination Addressing Mode Mask */ +#define XDMAC_CC_DAM(value) (XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)) +#define XDMAC_CC_DAM_FIXED_AM_Val _U_(0x0) /**< (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM_Val _U_(0x1) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM_Val _U_(0x2) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM_Val _U_(0x3) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_FIXED_AM (XDMAC_CC_DAM_FIXED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The address remains unchanged. Position */ +#define XDMAC_CC_DAM_INCREMENTED_AM (XDMAC_CC_DAM_INCREMENTED_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). Position */ +#define XDMAC_CC_DAM_UBS_AM (XDMAC_CC_DAM_UBS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary. Position */ +#define XDMAC_CC_DAM_UBS_DS_AM (XDMAC_CC_DAM_UBS_DS_AM_Val << XDMAC_CC_DAM_Pos) /**< (XDMAC_CC) The microblock stride is added at the microblock boundary; the data stride is added at the data boundary. Position */ +#define XDMAC_CC_INITD_Pos _U_(21) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Position */ +#define XDMAC_CC_INITD_Msk (_U_(0x1) << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) Mask */ +#define XDMAC_CC_INITD(value) (XDMAC_CC_INITD_Msk & ((value) << XDMAC_CC_INITD_Pos)) +#define XDMAC_CC_INITD_IN_PROGRESS_Val _U_(0x0) /**< (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_TERMINATED_Val _U_(0x1) /**< (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_INITD_IN_PROGRESS (XDMAC_CC_INITD_IN_PROGRESS_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is in progress. Position */ +#define XDMAC_CC_INITD_TERMINATED (XDMAC_CC_INITD_TERMINATED_Val << XDMAC_CC_INITD_Pos) /**< (XDMAC_CC) Channel initialization is completed. Position */ +#define XDMAC_CC_RDIP_Pos _U_(22) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Position */ +#define XDMAC_CC_RDIP_Msk (_U_(0x1) << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) Read in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_RDIP(value) (XDMAC_CC_RDIP_Msk & ((value) << XDMAC_CC_RDIP_Pos)) +#define XDMAC_CC_RDIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_RDIP_DONE (XDMAC_CC_RDIP_DONE_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) No active read transaction on the bus. Position */ +#define XDMAC_CC_RDIP_IN_PROGRESS (XDMAC_CC_RDIP_IN_PROGRESS_Val << XDMAC_CC_RDIP_Pos) /**< (XDMAC_CC) A read transaction is in progress. Position */ +#define XDMAC_CC_WRIP_Pos _U_(23) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Position */ +#define XDMAC_CC_WRIP_Msk (_U_(0x1) << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) Write in Progress (this bit is read-only) Mask */ +#define XDMAC_CC_WRIP(value) (XDMAC_CC_WRIP_Msk & ((value) << XDMAC_CC_WRIP_Pos)) +#define XDMAC_CC_WRIP_DONE_Val _U_(0x0) /**< (XDMAC_CC) No active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS_Val _U_(0x1) /**< (XDMAC_CC) A write transaction is in progress. */ +#define XDMAC_CC_WRIP_DONE (XDMAC_CC_WRIP_DONE_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) No active write transaction on the bus. Position */ +#define XDMAC_CC_WRIP_IN_PROGRESS (XDMAC_CC_WRIP_IN_PROGRESS_Val << XDMAC_CC_WRIP_Pos) /**< (XDMAC_CC) A write transaction is in progress. Position */ +#define XDMAC_CC_PERID_Pos _U_(24) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Position */ +#define XDMAC_CC_PERID_Msk (_U_(0x7F) << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) Channel x Peripheral Hardware Request Line Identifier Mask */ +#define XDMAC_CC_PERID(value) (XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)) +#define XDMAC_CC_PERID_HSMCI_Val _U_(0x0) /**< (XDMAC_CC) HSMCI */ +#define XDMAC_CC_PERID_SPI0_TX_Val _U_(0x1) /**< (XDMAC_CC) SPI0_TX */ +#define XDMAC_CC_PERID_SPI0_RX_Val _U_(0x2) /**< (XDMAC_CC) SPI0_RX */ +#define XDMAC_CC_PERID_SPI1_TX_Val _U_(0x3) /**< (XDMAC_CC) SPI1_TX */ +#define XDMAC_CC_PERID_SPI1_RX_Val _U_(0x4) /**< (XDMAC_CC) SPI1_RX */ +#define XDMAC_CC_PERID_QSPI_TX_Val _U_(0x5) /**< (XDMAC_CC) QSPI_TX */ +#define XDMAC_CC_PERID_QSPI_RX_Val _U_(0x6) /**< (XDMAC_CC) QSPI_RX */ +#define XDMAC_CC_PERID_USART0_TX_Val _U_(0x7) /**< (XDMAC_CC) USART0_TX */ +#define XDMAC_CC_PERID_USART0_RX_Val _U_(0x8) /**< (XDMAC_CC) USART0_RX */ +#define XDMAC_CC_PERID_USART1_TX_Val _U_(0x9) /**< (XDMAC_CC) USART1_TX */ +#define XDMAC_CC_PERID_USART1_RX_Val _U_(0xA) /**< (XDMAC_CC) USART1_RX */ +#define XDMAC_CC_PERID_USART2_TX_Val _U_(0xB) /**< (XDMAC_CC) USART2_TX */ +#define XDMAC_CC_PERID_USART2_RX_Val _U_(0xC) /**< (XDMAC_CC) USART2_RX */ +#define XDMAC_CC_PERID_PWM0_Val _U_(0xD) /**< (XDMAC_CC) PWM0 */ +#define XDMAC_CC_PERID_TWIHS0_TX_Val _U_(0xE) /**< (XDMAC_CC) TWIHS0_TX */ +#define XDMAC_CC_PERID_TWIHS0_RX_Val _U_(0xF) /**< (XDMAC_CC) TWIHS0_RX */ +#define XDMAC_CC_PERID_TWIHS1_TX_Val _U_(0x10) /**< (XDMAC_CC) TWIHS1_TX */ +#define XDMAC_CC_PERID_TWIHS1_RX_Val _U_(0x11) /**< (XDMAC_CC) TWIHS1_RX */ +#define XDMAC_CC_PERID_TWIHS2_TX_Val _U_(0x12) /**< (XDMAC_CC) TWIHS2_TX */ +#define XDMAC_CC_PERID_TWIHS2_RX_Val _U_(0x13) /**< (XDMAC_CC) TWIHS2_RX */ +#define XDMAC_CC_PERID_UART0_TX_Val _U_(0x14) /**< (XDMAC_CC) UART0_TX */ +#define XDMAC_CC_PERID_UART0_RX_Val _U_(0x15) /**< (XDMAC_CC) UART0_RX */ +#define XDMAC_CC_PERID_UART1_TX_Val _U_(0x16) /**< (XDMAC_CC) UART1_TX */ +#define XDMAC_CC_PERID_UART1_RX_Val _U_(0x17) /**< (XDMAC_CC) UART1_RX */ +#define XDMAC_CC_PERID_UART2_TX_Val _U_(0x18) /**< (XDMAC_CC) UART2_TX */ +#define XDMAC_CC_PERID_UART2_RX_Val _U_(0x19) /**< (XDMAC_CC) UART2_RX */ +#define XDMAC_CC_PERID_UART3_TX_Val _U_(0x1A) /**< (XDMAC_CC) UART3_TX */ +#define XDMAC_CC_PERID_UART3_RX_Val _U_(0x1B) /**< (XDMAC_CC) UART3_RX */ +#define XDMAC_CC_PERID_UART4_TX_Val _U_(0x1C) /**< (XDMAC_CC) UART4_TX */ +#define XDMAC_CC_PERID_UART4_RX_Val _U_(0x1D) /**< (XDMAC_CC) UART4_RX */ +#define XDMAC_CC_PERID_DACC0_Val _U_(0x1E) /**< (XDMAC_CC) DACC0 */ +#define XDMAC_CC_PERID_DACC1_Val _U_(0x1F) /**< (XDMAC_CC) DACC1 */ +#define XDMAC_CC_PERID_SSC_TX_Val _U_(0x20) /**< (XDMAC_CC) SSC_TX */ +#define XDMAC_CC_PERID_SSC_RX_Val _U_(0x21) /**< (XDMAC_CC) SSC_RX */ +#define XDMAC_CC_PERID_PIOA_Val _U_(0x22) /**< (XDMAC_CC) PIOA */ +#define XDMAC_CC_PERID_AFEC0_Val _U_(0x23) /**< (XDMAC_CC) AFEC0 */ +#define XDMAC_CC_PERID_AFEC1_Val _U_(0x24) /**< (XDMAC_CC) AFEC1 */ +#define XDMAC_CC_PERID_AES_TX_Val _U_(0x25) /**< (XDMAC_CC) AES_TX */ +#define XDMAC_CC_PERID_AES_RX_Val _U_(0x26) /**< (XDMAC_CC) AES_RX */ +#define XDMAC_CC_PERID_PWM1_Val _U_(0x27) /**< (XDMAC_CC) PWM1 */ +#define XDMAC_CC_PERID_TC0_Val _U_(0x28) /**< (XDMAC_CC) TC0 */ +#define XDMAC_CC_PERID_TC3_Val _U_(0x29) /**< (XDMAC_CC) TC3 */ +#define XDMAC_CC_PERID_TC6_Val _U_(0x2A) /**< (XDMAC_CC) TC6 */ +#define XDMAC_CC_PERID_TC9_Val _U_(0x2B) /**< (XDMAC_CC) TC9 */ +#define XDMAC_CC_PERID_I2SC0_TX_LEFT_Val _U_(0x2C) /**< (XDMAC_CC) I2SC0_TX_LEFT */ +#define XDMAC_CC_PERID_I2SC0_RX_LEFT_Val _U_(0x2D) /**< (XDMAC_CC) I2SC0_RX_LEFT */ +#define XDMAC_CC_PERID_I2SC1_TX_LEFT_Val _U_(0x2E) /**< (XDMAC_CC) I2SC1_TX_LEFT */ +#define XDMAC_CC_PERID_I2SC1_RX_LEFT_Val _U_(0x2F) /**< (XDMAC_CC) I2SC1_RX_LEFT */ +#define XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val _U_(0x30) /**< (XDMAC_CC) I2SC0_TX_RIGHT */ +#define XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val _U_(0x31) /**< (XDMAC_CC) I2SC0_RX_RIGHT */ +#define XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val _U_(0x32) /**< (XDMAC_CC) I2SC1_TX_RIGHT */ +#define XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val _U_(0x33) /**< (XDMAC_CC) I2SC1_RX_RIGHT */ +#define XDMAC_CC_PERID_HSMCI (XDMAC_CC_PERID_HSMCI_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) HSMCI Position */ +#define XDMAC_CC_PERID_SPI0_TX (XDMAC_CC_PERID_SPI0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_TX Position */ +#define XDMAC_CC_PERID_SPI0_RX (XDMAC_CC_PERID_SPI0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI0_RX Position */ +#define XDMAC_CC_PERID_SPI1_TX (XDMAC_CC_PERID_SPI1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_TX Position */ +#define XDMAC_CC_PERID_SPI1_RX (XDMAC_CC_PERID_SPI1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SPI1_RX Position */ +#define XDMAC_CC_PERID_QSPI_TX (XDMAC_CC_PERID_QSPI_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_TX Position */ +#define XDMAC_CC_PERID_QSPI_RX (XDMAC_CC_PERID_QSPI_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) QSPI_RX Position */ +#define XDMAC_CC_PERID_USART0_TX (XDMAC_CC_PERID_USART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_TX Position */ +#define XDMAC_CC_PERID_USART0_RX (XDMAC_CC_PERID_USART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART0_RX Position */ +#define XDMAC_CC_PERID_USART1_TX (XDMAC_CC_PERID_USART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_TX Position */ +#define XDMAC_CC_PERID_USART1_RX (XDMAC_CC_PERID_USART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART1_RX Position */ +#define XDMAC_CC_PERID_USART2_TX (XDMAC_CC_PERID_USART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_TX Position */ +#define XDMAC_CC_PERID_USART2_RX (XDMAC_CC_PERID_USART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) USART2_RX Position */ +#define XDMAC_CC_PERID_PWM0 (XDMAC_CC_PERID_PWM0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM0 Position */ +#define XDMAC_CC_PERID_TWIHS0_TX (XDMAC_CC_PERID_TWIHS0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_TX Position */ +#define XDMAC_CC_PERID_TWIHS0_RX (XDMAC_CC_PERID_TWIHS0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS0_RX Position */ +#define XDMAC_CC_PERID_TWIHS1_TX (XDMAC_CC_PERID_TWIHS1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_TX Position */ +#define XDMAC_CC_PERID_TWIHS1_RX (XDMAC_CC_PERID_TWIHS1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS1_RX Position */ +#define XDMAC_CC_PERID_TWIHS2_TX (XDMAC_CC_PERID_TWIHS2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_TX Position */ +#define XDMAC_CC_PERID_TWIHS2_RX (XDMAC_CC_PERID_TWIHS2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TWIHS2_RX Position */ +#define XDMAC_CC_PERID_UART0_TX (XDMAC_CC_PERID_UART0_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_TX Position */ +#define XDMAC_CC_PERID_UART0_RX (XDMAC_CC_PERID_UART0_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART0_RX Position */ +#define XDMAC_CC_PERID_UART1_TX (XDMAC_CC_PERID_UART1_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_TX Position */ +#define XDMAC_CC_PERID_UART1_RX (XDMAC_CC_PERID_UART1_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART1_RX Position */ +#define XDMAC_CC_PERID_UART2_TX (XDMAC_CC_PERID_UART2_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_TX Position */ +#define XDMAC_CC_PERID_UART2_RX (XDMAC_CC_PERID_UART2_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART2_RX Position */ +#define XDMAC_CC_PERID_UART3_TX (XDMAC_CC_PERID_UART3_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_TX Position */ +#define XDMAC_CC_PERID_UART3_RX (XDMAC_CC_PERID_UART3_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART3_RX Position */ +#define XDMAC_CC_PERID_UART4_TX (XDMAC_CC_PERID_UART4_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_TX Position */ +#define XDMAC_CC_PERID_UART4_RX (XDMAC_CC_PERID_UART4_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) UART4_RX Position */ +#define XDMAC_CC_PERID_DACC0 (XDMAC_CC_PERID_DACC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC0 Position */ +#define XDMAC_CC_PERID_DACC1 (XDMAC_CC_PERID_DACC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) DACC1 Position */ +#define XDMAC_CC_PERID_SSC_TX (XDMAC_CC_PERID_SSC_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_TX Position */ +#define XDMAC_CC_PERID_SSC_RX (XDMAC_CC_PERID_SSC_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) SSC_RX Position */ +#define XDMAC_CC_PERID_PIOA (XDMAC_CC_PERID_PIOA_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PIOA Position */ +#define XDMAC_CC_PERID_AFEC0 (XDMAC_CC_PERID_AFEC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC0 Position */ +#define XDMAC_CC_PERID_AFEC1 (XDMAC_CC_PERID_AFEC1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AFEC1 Position */ +#define XDMAC_CC_PERID_AES_TX (XDMAC_CC_PERID_AES_TX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_TX Position */ +#define XDMAC_CC_PERID_AES_RX (XDMAC_CC_PERID_AES_RX_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) AES_RX Position */ +#define XDMAC_CC_PERID_PWM1 (XDMAC_CC_PERID_PWM1_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) PWM1 Position */ +#define XDMAC_CC_PERID_TC0 (XDMAC_CC_PERID_TC0_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC0 Position */ +#define XDMAC_CC_PERID_TC3 (XDMAC_CC_PERID_TC3_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC3 Position */ +#define XDMAC_CC_PERID_TC6 (XDMAC_CC_PERID_TC6_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC6 Position */ +#define XDMAC_CC_PERID_TC9 (XDMAC_CC_PERID_TC9_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) TC9 Position */ +#define XDMAC_CC_PERID_I2SC0_TX_LEFT (XDMAC_CC_PERID_I2SC0_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC0_RX_LEFT (XDMAC_CC_PERID_I2SC0_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC1_TX_LEFT (XDMAC_CC_PERID_I2SC1_TX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC1_RX_LEFT (XDMAC_CC_PERID_I2SC1_RX_LEFT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_LEFT Position */ +#define XDMAC_CC_PERID_I2SC0_TX_RIGHT (XDMAC_CC_PERID_I2SC0_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_TX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC0_RX_RIGHT (XDMAC_CC_PERID_I2SC0_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC0_RX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC1_TX_RIGHT (XDMAC_CC_PERID_I2SC1_TX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_TX_RIGHT Position */ +#define XDMAC_CC_PERID_I2SC1_RX_RIGHT (XDMAC_CC_PERID_I2SC1_RX_RIGHT_Val << XDMAC_CC_PERID_Pos) /**< (XDMAC_CC) I2SC1_RX_RIGHT Position */ +#define XDMAC_CC_Msk _U_(0x7FEF7FD7) /**< (XDMAC_CC) Register Mask */ + + +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: 0x2C) (R/W 32) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos _U_(0) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_SDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_SDS_MSP(value) (XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)) +#define XDMAC_CDS_MSP_DDS_MSP_Pos _U_(16) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Position */ +#define XDMAC_CDS_MSP_DDS_MSP_Msk (_U_(0xFFFF) << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern Mask */ +#define XDMAC_CDS_MSP_DDS_MSP(value) (XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)) +#define XDMAC_CDS_MSP_Msk _U_(0xFFFFFFFF) /**< (XDMAC_CDS_MSP) Register Mask */ + + +/* -------- XDMAC_CSUS : (XDMAC Offset: 0x30) (R/W 32) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos _U_(0) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Position */ +#define XDMAC_CSUS_SUBS_Msk (_U_(0xFFFFFF) << XDMAC_CSUS_SUBS_Pos) /**< (XDMAC_CSUS) Channel x Source Microblock Stride Mask */ +#define XDMAC_CSUS_SUBS(value) (XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)) +#define XDMAC_CSUS_Msk _U_(0x00FFFFFF) /**< (XDMAC_CSUS) Register Mask */ + + +/* -------- XDMAC_CDUS : (XDMAC Offset: 0x34) (R/W 32) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos _U_(0) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Position */ +#define XDMAC_CDUS_DUBS_Msk (_U_(0xFFFFFF) << XDMAC_CDUS_DUBS_Pos) /**< (XDMAC_CDUS) Channel x Destination Microblock Stride Mask */ +#define XDMAC_CDUS_DUBS(value) (XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)) +#define XDMAC_CDUS_Msk _U_(0x00FFFFFF) /**< (XDMAC_CDUS) Register Mask */ + + +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) ( R/ 32) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos _U_(0) /**< (XDMAC_GTYPE) Number of Channels Minus One Position */ +#define XDMAC_GTYPE_NB_CH_Msk (_U_(0x1F) << XDMAC_GTYPE_NB_CH_Pos) /**< (XDMAC_GTYPE) Number of Channels Minus One Mask */ +#define XDMAC_GTYPE_NB_CH(value) (XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)) +#define XDMAC_GTYPE_FIFO_SZ_Pos _U_(5) /**< (XDMAC_GTYPE) Number of Bytes Position */ +#define XDMAC_GTYPE_FIFO_SZ_Msk (_U_(0x7FF) << XDMAC_GTYPE_FIFO_SZ_Pos) /**< (XDMAC_GTYPE) Number of Bytes Mask */ +#define XDMAC_GTYPE_FIFO_SZ(value) (XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)) +#define XDMAC_GTYPE_NB_REQ_Pos _U_(16) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Position */ +#define XDMAC_GTYPE_NB_REQ_Msk (_U_(0x7F) << XDMAC_GTYPE_NB_REQ_Pos) /**< (XDMAC_GTYPE) Number of Peripheral Requests Minus One Mask */ +#define XDMAC_GTYPE_NB_REQ(value) (XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)) +#define XDMAC_GTYPE_Msk _U_(0x007FFFFF) /**< (XDMAC_GTYPE) Register Mask */ + + +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) (R/W 32) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG_Pos _U_(0) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISREG_Msk (_U_(0x1) << XDMAC_GCFG_CGDISREG_Pos) /**< (XDMAC_GCFG) Configuration Registers Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISREG(value) (XDMAC_GCFG_CGDISREG_Msk & ((value) << XDMAC_GCFG_CGDISREG_Pos)) +#define XDMAC_GCFG_CGDISPIPE_Pos _U_(1) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISPIPE_Msk (_U_(0x1) << XDMAC_GCFG_CGDISPIPE_Pos) /**< (XDMAC_GCFG) Pipeline Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISPIPE(value) (XDMAC_GCFG_CGDISPIPE_Msk & ((value) << XDMAC_GCFG_CGDISPIPE_Pos)) +#define XDMAC_GCFG_CGDISFIFO_Pos _U_(2) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISFIFO_Msk (_U_(0x1) << XDMAC_GCFG_CGDISFIFO_Pos) /**< (XDMAC_GCFG) FIFO Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISFIFO(value) (XDMAC_GCFG_CGDISFIFO_Msk & ((value) << XDMAC_GCFG_CGDISFIFO_Pos)) +#define XDMAC_GCFG_CGDISIF_Pos _U_(3) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Position */ +#define XDMAC_GCFG_CGDISIF_Msk (_U_(0x1) << XDMAC_GCFG_CGDISIF_Pos) /**< (XDMAC_GCFG) Bus Interface Clock Gating Disable Mask */ +#define XDMAC_GCFG_CGDISIF(value) (XDMAC_GCFG_CGDISIF_Msk & ((value) << XDMAC_GCFG_CGDISIF_Pos)) +#define XDMAC_GCFG_BXKBEN_Pos _U_(8) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Position */ +#define XDMAC_GCFG_BXKBEN_Msk (_U_(0x1) << XDMAC_GCFG_BXKBEN_Pos) /**< (XDMAC_GCFG) Boundary X Kilobyte Enable Mask */ +#define XDMAC_GCFG_BXKBEN(value) (XDMAC_GCFG_BXKBEN_Msk & ((value) << XDMAC_GCFG_BXKBEN_Pos)) +#define XDMAC_GCFG_Msk _U_(0x0000010F) /**< (XDMAC_GCFG) Register Mask */ + + +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) (R/W 32) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos _U_(0) /**< (XDMAC_GWAC) Pool Weight 0 Position */ +#define XDMAC_GWAC_PW0_Msk (_U_(0xF) << XDMAC_GWAC_PW0_Pos) /**< (XDMAC_GWAC) Pool Weight 0 Mask */ +#define XDMAC_GWAC_PW0(value) (XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)) +#define XDMAC_GWAC_PW1_Pos _U_(4) /**< (XDMAC_GWAC) Pool Weight 1 Position */ +#define XDMAC_GWAC_PW1_Msk (_U_(0xF) << XDMAC_GWAC_PW1_Pos) /**< (XDMAC_GWAC) Pool Weight 1 Mask */ +#define XDMAC_GWAC_PW1(value) (XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)) +#define XDMAC_GWAC_PW2_Pos _U_(8) /**< (XDMAC_GWAC) Pool Weight 2 Position */ +#define XDMAC_GWAC_PW2_Msk (_U_(0xF) << XDMAC_GWAC_PW2_Pos) /**< (XDMAC_GWAC) Pool Weight 2 Mask */ +#define XDMAC_GWAC_PW2(value) (XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)) +#define XDMAC_GWAC_PW3_Pos _U_(12) /**< (XDMAC_GWAC) Pool Weight 3 Position */ +#define XDMAC_GWAC_PW3_Msk (_U_(0xF) << XDMAC_GWAC_PW3_Pos) /**< (XDMAC_GWAC) Pool Weight 3 Mask */ +#define XDMAC_GWAC_PW3(value) (XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)) +#define XDMAC_GWAC_Msk _U_(0x0000FFFF) /**< (XDMAC_GWAC) Register Mask */ + + +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) ( /W 32) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0_Pos _U_(0) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE0_Msk (_U_(0x1) << XDMAC_GIE_IE0_Pos) /**< (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE0(value) (XDMAC_GIE_IE0_Msk & ((value) << XDMAC_GIE_IE0_Pos)) +#define XDMAC_GIE_IE1_Pos _U_(1) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE1_Msk (_U_(0x1) << XDMAC_GIE_IE1_Pos) /**< (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE1(value) (XDMAC_GIE_IE1_Msk & ((value) << XDMAC_GIE_IE1_Pos)) +#define XDMAC_GIE_IE2_Pos _U_(2) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE2_Msk (_U_(0x1) << XDMAC_GIE_IE2_Pos) /**< (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE2(value) (XDMAC_GIE_IE2_Msk & ((value) << XDMAC_GIE_IE2_Pos)) +#define XDMAC_GIE_IE3_Pos _U_(3) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE3_Msk (_U_(0x1) << XDMAC_GIE_IE3_Pos) /**< (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE3(value) (XDMAC_GIE_IE3_Msk & ((value) << XDMAC_GIE_IE3_Pos)) +#define XDMAC_GIE_IE4_Pos _U_(4) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE4_Msk (_U_(0x1) << XDMAC_GIE_IE4_Pos) /**< (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE4(value) (XDMAC_GIE_IE4_Msk & ((value) << XDMAC_GIE_IE4_Pos)) +#define XDMAC_GIE_IE5_Pos _U_(5) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE5_Msk (_U_(0x1) << XDMAC_GIE_IE5_Pos) /**< (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE5(value) (XDMAC_GIE_IE5_Msk & ((value) << XDMAC_GIE_IE5_Pos)) +#define XDMAC_GIE_IE6_Pos _U_(6) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE6_Msk (_U_(0x1) << XDMAC_GIE_IE6_Pos) /**< (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE6(value) (XDMAC_GIE_IE6_Msk & ((value) << XDMAC_GIE_IE6_Pos)) +#define XDMAC_GIE_IE7_Pos _U_(7) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE7_Msk (_U_(0x1) << XDMAC_GIE_IE7_Pos) /**< (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE7(value) (XDMAC_GIE_IE7_Msk & ((value) << XDMAC_GIE_IE7_Pos)) +#define XDMAC_GIE_IE8_Pos _U_(8) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE8_Msk (_U_(0x1) << XDMAC_GIE_IE8_Pos) /**< (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE8(value) (XDMAC_GIE_IE8_Msk & ((value) << XDMAC_GIE_IE8_Pos)) +#define XDMAC_GIE_IE9_Pos _U_(9) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE9_Msk (_U_(0x1) << XDMAC_GIE_IE9_Pos) /**< (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE9(value) (XDMAC_GIE_IE9_Msk & ((value) << XDMAC_GIE_IE9_Pos)) +#define XDMAC_GIE_IE10_Pos _U_(10) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE10_Msk (_U_(0x1) << XDMAC_GIE_IE10_Pos) /**< (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE10(value) (XDMAC_GIE_IE10_Msk & ((value) << XDMAC_GIE_IE10_Pos)) +#define XDMAC_GIE_IE11_Pos _U_(11) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE11_Msk (_U_(0x1) << XDMAC_GIE_IE11_Pos) /**< (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE11(value) (XDMAC_GIE_IE11_Msk & ((value) << XDMAC_GIE_IE11_Pos)) +#define XDMAC_GIE_IE12_Pos _U_(12) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE12_Msk (_U_(0x1) << XDMAC_GIE_IE12_Pos) /**< (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE12(value) (XDMAC_GIE_IE12_Msk & ((value) << XDMAC_GIE_IE12_Pos)) +#define XDMAC_GIE_IE13_Pos _U_(13) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE13_Msk (_U_(0x1) << XDMAC_GIE_IE13_Pos) /**< (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE13(value) (XDMAC_GIE_IE13_Msk & ((value) << XDMAC_GIE_IE13_Pos)) +#define XDMAC_GIE_IE14_Pos _U_(14) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE14_Msk (_U_(0x1) << XDMAC_GIE_IE14_Pos) /**< (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE14(value) (XDMAC_GIE_IE14_Msk & ((value) << XDMAC_GIE_IE14_Pos)) +#define XDMAC_GIE_IE15_Pos _U_(15) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE15_Msk (_U_(0x1) << XDMAC_GIE_IE15_Pos) /**< (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE15(value) (XDMAC_GIE_IE15_Msk & ((value) << XDMAC_GIE_IE15_Pos)) +#define XDMAC_GIE_IE16_Pos _U_(16) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE16_Msk (_U_(0x1) << XDMAC_GIE_IE16_Pos) /**< (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE16(value) (XDMAC_GIE_IE16_Msk & ((value) << XDMAC_GIE_IE16_Pos)) +#define XDMAC_GIE_IE17_Pos _U_(17) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE17_Msk (_U_(0x1) << XDMAC_GIE_IE17_Pos) /**< (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE17(value) (XDMAC_GIE_IE17_Msk & ((value) << XDMAC_GIE_IE17_Pos)) +#define XDMAC_GIE_IE18_Pos _U_(18) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE18_Msk (_U_(0x1) << XDMAC_GIE_IE18_Pos) /**< (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE18(value) (XDMAC_GIE_IE18_Msk & ((value) << XDMAC_GIE_IE18_Pos)) +#define XDMAC_GIE_IE19_Pos _U_(19) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE19_Msk (_U_(0x1) << XDMAC_GIE_IE19_Pos) /**< (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE19(value) (XDMAC_GIE_IE19_Msk & ((value) << XDMAC_GIE_IE19_Pos)) +#define XDMAC_GIE_IE20_Pos _U_(20) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE20_Msk (_U_(0x1) << XDMAC_GIE_IE20_Pos) /**< (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE20(value) (XDMAC_GIE_IE20_Msk & ((value) << XDMAC_GIE_IE20_Pos)) +#define XDMAC_GIE_IE21_Pos _U_(21) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE21_Msk (_U_(0x1) << XDMAC_GIE_IE21_Pos) /**< (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE21(value) (XDMAC_GIE_IE21_Msk & ((value) << XDMAC_GIE_IE21_Pos)) +#define XDMAC_GIE_IE22_Pos _U_(22) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE22_Msk (_U_(0x1) << XDMAC_GIE_IE22_Pos) /**< (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE22(value) (XDMAC_GIE_IE22_Msk & ((value) << XDMAC_GIE_IE22_Pos)) +#define XDMAC_GIE_IE23_Pos _U_(23) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Position */ +#define XDMAC_GIE_IE23_Msk (_U_(0x1) << XDMAC_GIE_IE23_Pos) /**< (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit Mask */ +#define XDMAC_GIE_IE23(value) (XDMAC_GIE_IE23_Msk & ((value) << XDMAC_GIE_IE23_Pos)) +#define XDMAC_GIE_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIE) Register Mask */ + +#define XDMAC_GIE_IE_Pos _U_(0) /**< (XDMAC_GIE Position) XDMAC Channel 23 Interrupt Enable Bit */ +#define XDMAC_GIE_IE_Msk (_U_(0xFFFFFF) << XDMAC_GIE_IE_Pos) /**< (XDMAC_GIE Mask) IE */ +#define XDMAC_GIE_IE(value) (XDMAC_GIE_IE_Msk & ((value) << XDMAC_GIE_IE_Pos)) + +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) ( /W 32) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0_Pos _U_(0) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID0_Msk (_U_(0x1) << XDMAC_GID_ID0_Pos) /**< (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID0(value) (XDMAC_GID_ID0_Msk & ((value) << XDMAC_GID_ID0_Pos)) +#define XDMAC_GID_ID1_Pos _U_(1) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID1_Msk (_U_(0x1) << XDMAC_GID_ID1_Pos) /**< (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID1(value) (XDMAC_GID_ID1_Msk & ((value) << XDMAC_GID_ID1_Pos)) +#define XDMAC_GID_ID2_Pos _U_(2) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID2_Msk (_U_(0x1) << XDMAC_GID_ID2_Pos) /**< (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID2(value) (XDMAC_GID_ID2_Msk & ((value) << XDMAC_GID_ID2_Pos)) +#define XDMAC_GID_ID3_Pos _U_(3) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID3_Msk (_U_(0x1) << XDMAC_GID_ID3_Pos) /**< (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID3(value) (XDMAC_GID_ID3_Msk & ((value) << XDMAC_GID_ID3_Pos)) +#define XDMAC_GID_ID4_Pos _U_(4) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID4_Msk (_U_(0x1) << XDMAC_GID_ID4_Pos) /**< (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID4(value) (XDMAC_GID_ID4_Msk & ((value) << XDMAC_GID_ID4_Pos)) +#define XDMAC_GID_ID5_Pos _U_(5) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID5_Msk (_U_(0x1) << XDMAC_GID_ID5_Pos) /**< (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID5(value) (XDMAC_GID_ID5_Msk & ((value) << XDMAC_GID_ID5_Pos)) +#define XDMAC_GID_ID6_Pos _U_(6) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID6_Msk (_U_(0x1) << XDMAC_GID_ID6_Pos) /**< (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID6(value) (XDMAC_GID_ID6_Msk & ((value) << XDMAC_GID_ID6_Pos)) +#define XDMAC_GID_ID7_Pos _U_(7) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID7_Msk (_U_(0x1) << XDMAC_GID_ID7_Pos) /**< (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID7(value) (XDMAC_GID_ID7_Msk & ((value) << XDMAC_GID_ID7_Pos)) +#define XDMAC_GID_ID8_Pos _U_(8) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID8_Msk (_U_(0x1) << XDMAC_GID_ID8_Pos) /**< (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID8(value) (XDMAC_GID_ID8_Msk & ((value) << XDMAC_GID_ID8_Pos)) +#define XDMAC_GID_ID9_Pos _U_(9) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID9_Msk (_U_(0x1) << XDMAC_GID_ID9_Pos) /**< (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID9(value) (XDMAC_GID_ID9_Msk & ((value) << XDMAC_GID_ID9_Pos)) +#define XDMAC_GID_ID10_Pos _U_(10) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID10_Msk (_U_(0x1) << XDMAC_GID_ID10_Pos) /**< (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID10(value) (XDMAC_GID_ID10_Msk & ((value) << XDMAC_GID_ID10_Pos)) +#define XDMAC_GID_ID11_Pos _U_(11) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID11_Msk (_U_(0x1) << XDMAC_GID_ID11_Pos) /**< (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID11(value) (XDMAC_GID_ID11_Msk & ((value) << XDMAC_GID_ID11_Pos)) +#define XDMAC_GID_ID12_Pos _U_(12) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID12_Msk (_U_(0x1) << XDMAC_GID_ID12_Pos) /**< (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID12(value) (XDMAC_GID_ID12_Msk & ((value) << XDMAC_GID_ID12_Pos)) +#define XDMAC_GID_ID13_Pos _U_(13) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID13_Msk (_U_(0x1) << XDMAC_GID_ID13_Pos) /**< (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID13(value) (XDMAC_GID_ID13_Msk & ((value) << XDMAC_GID_ID13_Pos)) +#define XDMAC_GID_ID14_Pos _U_(14) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID14_Msk (_U_(0x1) << XDMAC_GID_ID14_Pos) /**< (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID14(value) (XDMAC_GID_ID14_Msk & ((value) << XDMAC_GID_ID14_Pos)) +#define XDMAC_GID_ID15_Pos _U_(15) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID15_Msk (_U_(0x1) << XDMAC_GID_ID15_Pos) /**< (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID15(value) (XDMAC_GID_ID15_Msk & ((value) << XDMAC_GID_ID15_Pos)) +#define XDMAC_GID_ID16_Pos _U_(16) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID16_Msk (_U_(0x1) << XDMAC_GID_ID16_Pos) /**< (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID16(value) (XDMAC_GID_ID16_Msk & ((value) << XDMAC_GID_ID16_Pos)) +#define XDMAC_GID_ID17_Pos _U_(17) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID17_Msk (_U_(0x1) << XDMAC_GID_ID17_Pos) /**< (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID17(value) (XDMAC_GID_ID17_Msk & ((value) << XDMAC_GID_ID17_Pos)) +#define XDMAC_GID_ID18_Pos _U_(18) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID18_Msk (_U_(0x1) << XDMAC_GID_ID18_Pos) /**< (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID18(value) (XDMAC_GID_ID18_Msk & ((value) << XDMAC_GID_ID18_Pos)) +#define XDMAC_GID_ID19_Pos _U_(19) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID19_Msk (_U_(0x1) << XDMAC_GID_ID19_Pos) /**< (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID19(value) (XDMAC_GID_ID19_Msk & ((value) << XDMAC_GID_ID19_Pos)) +#define XDMAC_GID_ID20_Pos _U_(20) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID20_Msk (_U_(0x1) << XDMAC_GID_ID20_Pos) /**< (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID20(value) (XDMAC_GID_ID20_Msk & ((value) << XDMAC_GID_ID20_Pos)) +#define XDMAC_GID_ID21_Pos _U_(21) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID21_Msk (_U_(0x1) << XDMAC_GID_ID21_Pos) /**< (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID21(value) (XDMAC_GID_ID21_Msk & ((value) << XDMAC_GID_ID21_Pos)) +#define XDMAC_GID_ID22_Pos _U_(22) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID22_Msk (_U_(0x1) << XDMAC_GID_ID22_Pos) /**< (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID22(value) (XDMAC_GID_ID22_Msk & ((value) << XDMAC_GID_ID22_Pos)) +#define XDMAC_GID_ID23_Pos _U_(23) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Position */ +#define XDMAC_GID_ID23_Msk (_U_(0x1) << XDMAC_GID_ID23_Pos) /**< (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit Mask */ +#define XDMAC_GID_ID23(value) (XDMAC_GID_ID23_Msk & ((value) << XDMAC_GID_ID23_Pos)) +#define XDMAC_GID_Msk _U_(0x00FFFFFF) /**< (XDMAC_GID) Register Mask */ + +#define XDMAC_GID_ID_Pos _U_(0) /**< (XDMAC_GID Position) XDMAC Channel 23 Interrupt Disable Bit */ +#define XDMAC_GID_ID_Msk (_U_(0xFFFFFF) << XDMAC_GID_ID_Pos) /**< (XDMAC_GID Mask) ID */ +#define XDMAC_GID_ID(value) (XDMAC_GID_ID_Msk & ((value) << XDMAC_GID_ID_Pos)) + +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) ( R/ 32) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0_Pos _U_(0) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM0_Msk (_U_(0x1) << XDMAC_GIM_IM0_Pos) /**< (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM0(value) (XDMAC_GIM_IM0_Msk & ((value) << XDMAC_GIM_IM0_Pos)) +#define XDMAC_GIM_IM1_Pos _U_(1) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM1_Msk (_U_(0x1) << XDMAC_GIM_IM1_Pos) /**< (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM1(value) (XDMAC_GIM_IM1_Msk & ((value) << XDMAC_GIM_IM1_Pos)) +#define XDMAC_GIM_IM2_Pos _U_(2) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM2_Msk (_U_(0x1) << XDMAC_GIM_IM2_Pos) /**< (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM2(value) (XDMAC_GIM_IM2_Msk & ((value) << XDMAC_GIM_IM2_Pos)) +#define XDMAC_GIM_IM3_Pos _U_(3) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM3_Msk (_U_(0x1) << XDMAC_GIM_IM3_Pos) /**< (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM3(value) (XDMAC_GIM_IM3_Msk & ((value) << XDMAC_GIM_IM3_Pos)) +#define XDMAC_GIM_IM4_Pos _U_(4) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM4_Msk (_U_(0x1) << XDMAC_GIM_IM4_Pos) /**< (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM4(value) (XDMAC_GIM_IM4_Msk & ((value) << XDMAC_GIM_IM4_Pos)) +#define XDMAC_GIM_IM5_Pos _U_(5) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM5_Msk (_U_(0x1) << XDMAC_GIM_IM5_Pos) /**< (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM5(value) (XDMAC_GIM_IM5_Msk & ((value) << XDMAC_GIM_IM5_Pos)) +#define XDMAC_GIM_IM6_Pos _U_(6) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM6_Msk (_U_(0x1) << XDMAC_GIM_IM6_Pos) /**< (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM6(value) (XDMAC_GIM_IM6_Msk & ((value) << XDMAC_GIM_IM6_Pos)) +#define XDMAC_GIM_IM7_Pos _U_(7) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM7_Msk (_U_(0x1) << XDMAC_GIM_IM7_Pos) /**< (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM7(value) (XDMAC_GIM_IM7_Msk & ((value) << XDMAC_GIM_IM7_Pos)) +#define XDMAC_GIM_IM8_Pos _U_(8) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM8_Msk (_U_(0x1) << XDMAC_GIM_IM8_Pos) /**< (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM8(value) (XDMAC_GIM_IM8_Msk & ((value) << XDMAC_GIM_IM8_Pos)) +#define XDMAC_GIM_IM9_Pos _U_(9) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM9_Msk (_U_(0x1) << XDMAC_GIM_IM9_Pos) /**< (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM9(value) (XDMAC_GIM_IM9_Msk & ((value) << XDMAC_GIM_IM9_Pos)) +#define XDMAC_GIM_IM10_Pos _U_(10) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM10_Msk (_U_(0x1) << XDMAC_GIM_IM10_Pos) /**< (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM10(value) (XDMAC_GIM_IM10_Msk & ((value) << XDMAC_GIM_IM10_Pos)) +#define XDMAC_GIM_IM11_Pos _U_(11) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM11_Msk (_U_(0x1) << XDMAC_GIM_IM11_Pos) /**< (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM11(value) (XDMAC_GIM_IM11_Msk & ((value) << XDMAC_GIM_IM11_Pos)) +#define XDMAC_GIM_IM12_Pos _U_(12) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM12_Msk (_U_(0x1) << XDMAC_GIM_IM12_Pos) /**< (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM12(value) (XDMAC_GIM_IM12_Msk & ((value) << XDMAC_GIM_IM12_Pos)) +#define XDMAC_GIM_IM13_Pos _U_(13) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM13_Msk (_U_(0x1) << XDMAC_GIM_IM13_Pos) /**< (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM13(value) (XDMAC_GIM_IM13_Msk & ((value) << XDMAC_GIM_IM13_Pos)) +#define XDMAC_GIM_IM14_Pos _U_(14) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM14_Msk (_U_(0x1) << XDMAC_GIM_IM14_Pos) /**< (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM14(value) (XDMAC_GIM_IM14_Msk & ((value) << XDMAC_GIM_IM14_Pos)) +#define XDMAC_GIM_IM15_Pos _U_(15) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM15_Msk (_U_(0x1) << XDMAC_GIM_IM15_Pos) /**< (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM15(value) (XDMAC_GIM_IM15_Msk & ((value) << XDMAC_GIM_IM15_Pos)) +#define XDMAC_GIM_IM16_Pos _U_(16) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM16_Msk (_U_(0x1) << XDMAC_GIM_IM16_Pos) /**< (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM16(value) (XDMAC_GIM_IM16_Msk & ((value) << XDMAC_GIM_IM16_Pos)) +#define XDMAC_GIM_IM17_Pos _U_(17) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM17_Msk (_U_(0x1) << XDMAC_GIM_IM17_Pos) /**< (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM17(value) (XDMAC_GIM_IM17_Msk & ((value) << XDMAC_GIM_IM17_Pos)) +#define XDMAC_GIM_IM18_Pos _U_(18) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM18_Msk (_U_(0x1) << XDMAC_GIM_IM18_Pos) /**< (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM18(value) (XDMAC_GIM_IM18_Msk & ((value) << XDMAC_GIM_IM18_Pos)) +#define XDMAC_GIM_IM19_Pos _U_(19) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM19_Msk (_U_(0x1) << XDMAC_GIM_IM19_Pos) /**< (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM19(value) (XDMAC_GIM_IM19_Msk & ((value) << XDMAC_GIM_IM19_Pos)) +#define XDMAC_GIM_IM20_Pos _U_(20) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM20_Msk (_U_(0x1) << XDMAC_GIM_IM20_Pos) /**< (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM20(value) (XDMAC_GIM_IM20_Msk & ((value) << XDMAC_GIM_IM20_Pos)) +#define XDMAC_GIM_IM21_Pos _U_(21) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM21_Msk (_U_(0x1) << XDMAC_GIM_IM21_Pos) /**< (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM21(value) (XDMAC_GIM_IM21_Msk & ((value) << XDMAC_GIM_IM21_Pos)) +#define XDMAC_GIM_IM22_Pos _U_(22) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM22_Msk (_U_(0x1) << XDMAC_GIM_IM22_Pos) /**< (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM22(value) (XDMAC_GIM_IM22_Msk & ((value) << XDMAC_GIM_IM22_Pos)) +#define XDMAC_GIM_IM23_Pos _U_(23) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Position */ +#define XDMAC_GIM_IM23_Msk (_U_(0x1) << XDMAC_GIM_IM23_Pos) /**< (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit Mask */ +#define XDMAC_GIM_IM23(value) (XDMAC_GIM_IM23_Msk & ((value) << XDMAC_GIM_IM23_Pos)) +#define XDMAC_GIM_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIM) Register Mask */ + +#define XDMAC_GIM_IM_Pos _U_(0) /**< (XDMAC_GIM Position) XDMAC Channel 23 Interrupt Mask Bit */ +#define XDMAC_GIM_IM_Msk (_U_(0xFFFFFF) << XDMAC_GIM_IM_Pos) /**< (XDMAC_GIM Mask) IM */ +#define XDMAC_GIM_IM(value) (XDMAC_GIM_IM_Msk & ((value) << XDMAC_GIM_IM_Pos)) + +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) ( R/ 32) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0_Pos _U_(0) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS0_Msk (_U_(0x1) << XDMAC_GIS_IS0_Pos) /**< (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS0(value) (XDMAC_GIS_IS0_Msk & ((value) << XDMAC_GIS_IS0_Pos)) +#define XDMAC_GIS_IS1_Pos _U_(1) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS1_Msk (_U_(0x1) << XDMAC_GIS_IS1_Pos) /**< (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS1(value) (XDMAC_GIS_IS1_Msk & ((value) << XDMAC_GIS_IS1_Pos)) +#define XDMAC_GIS_IS2_Pos _U_(2) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS2_Msk (_U_(0x1) << XDMAC_GIS_IS2_Pos) /**< (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS2(value) (XDMAC_GIS_IS2_Msk & ((value) << XDMAC_GIS_IS2_Pos)) +#define XDMAC_GIS_IS3_Pos _U_(3) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS3_Msk (_U_(0x1) << XDMAC_GIS_IS3_Pos) /**< (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS3(value) (XDMAC_GIS_IS3_Msk & ((value) << XDMAC_GIS_IS3_Pos)) +#define XDMAC_GIS_IS4_Pos _U_(4) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS4_Msk (_U_(0x1) << XDMAC_GIS_IS4_Pos) /**< (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS4(value) (XDMAC_GIS_IS4_Msk & ((value) << XDMAC_GIS_IS4_Pos)) +#define XDMAC_GIS_IS5_Pos _U_(5) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS5_Msk (_U_(0x1) << XDMAC_GIS_IS5_Pos) /**< (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS5(value) (XDMAC_GIS_IS5_Msk & ((value) << XDMAC_GIS_IS5_Pos)) +#define XDMAC_GIS_IS6_Pos _U_(6) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS6_Msk (_U_(0x1) << XDMAC_GIS_IS6_Pos) /**< (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS6(value) (XDMAC_GIS_IS6_Msk & ((value) << XDMAC_GIS_IS6_Pos)) +#define XDMAC_GIS_IS7_Pos _U_(7) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS7_Msk (_U_(0x1) << XDMAC_GIS_IS7_Pos) /**< (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS7(value) (XDMAC_GIS_IS7_Msk & ((value) << XDMAC_GIS_IS7_Pos)) +#define XDMAC_GIS_IS8_Pos _U_(8) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS8_Msk (_U_(0x1) << XDMAC_GIS_IS8_Pos) /**< (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS8(value) (XDMAC_GIS_IS8_Msk & ((value) << XDMAC_GIS_IS8_Pos)) +#define XDMAC_GIS_IS9_Pos _U_(9) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS9_Msk (_U_(0x1) << XDMAC_GIS_IS9_Pos) /**< (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS9(value) (XDMAC_GIS_IS9_Msk & ((value) << XDMAC_GIS_IS9_Pos)) +#define XDMAC_GIS_IS10_Pos _U_(10) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS10_Msk (_U_(0x1) << XDMAC_GIS_IS10_Pos) /**< (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS10(value) (XDMAC_GIS_IS10_Msk & ((value) << XDMAC_GIS_IS10_Pos)) +#define XDMAC_GIS_IS11_Pos _U_(11) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS11_Msk (_U_(0x1) << XDMAC_GIS_IS11_Pos) /**< (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS11(value) (XDMAC_GIS_IS11_Msk & ((value) << XDMAC_GIS_IS11_Pos)) +#define XDMAC_GIS_IS12_Pos _U_(12) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS12_Msk (_U_(0x1) << XDMAC_GIS_IS12_Pos) /**< (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS12(value) (XDMAC_GIS_IS12_Msk & ((value) << XDMAC_GIS_IS12_Pos)) +#define XDMAC_GIS_IS13_Pos _U_(13) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS13_Msk (_U_(0x1) << XDMAC_GIS_IS13_Pos) /**< (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS13(value) (XDMAC_GIS_IS13_Msk & ((value) << XDMAC_GIS_IS13_Pos)) +#define XDMAC_GIS_IS14_Pos _U_(14) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS14_Msk (_U_(0x1) << XDMAC_GIS_IS14_Pos) /**< (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS14(value) (XDMAC_GIS_IS14_Msk & ((value) << XDMAC_GIS_IS14_Pos)) +#define XDMAC_GIS_IS15_Pos _U_(15) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS15_Msk (_U_(0x1) << XDMAC_GIS_IS15_Pos) /**< (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS15(value) (XDMAC_GIS_IS15_Msk & ((value) << XDMAC_GIS_IS15_Pos)) +#define XDMAC_GIS_IS16_Pos _U_(16) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS16_Msk (_U_(0x1) << XDMAC_GIS_IS16_Pos) /**< (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS16(value) (XDMAC_GIS_IS16_Msk & ((value) << XDMAC_GIS_IS16_Pos)) +#define XDMAC_GIS_IS17_Pos _U_(17) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS17_Msk (_U_(0x1) << XDMAC_GIS_IS17_Pos) /**< (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS17(value) (XDMAC_GIS_IS17_Msk & ((value) << XDMAC_GIS_IS17_Pos)) +#define XDMAC_GIS_IS18_Pos _U_(18) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS18_Msk (_U_(0x1) << XDMAC_GIS_IS18_Pos) /**< (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS18(value) (XDMAC_GIS_IS18_Msk & ((value) << XDMAC_GIS_IS18_Pos)) +#define XDMAC_GIS_IS19_Pos _U_(19) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS19_Msk (_U_(0x1) << XDMAC_GIS_IS19_Pos) /**< (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS19(value) (XDMAC_GIS_IS19_Msk & ((value) << XDMAC_GIS_IS19_Pos)) +#define XDMAC_GIS_IS20_Pos _U_(20) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS20_Msk (_U_(0x1) << XDMAC_GIS_IS20_Pos) /**< (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS20(value) (XDMAC_GIS_IS20_Msk & ((value) << XDMAC_GIS_IS20_Pos)) +#define XDMAC_GIS_IS21_Pos _U_(21) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS21_Msk (_U_(0x1) << XDMAC_GIS_IS21_Pos) /**< (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS21(value) (XDMAC_GIS_IS21_Msk & ((value) << XDMAC_GIS_IS21_Pos)) +#define XDMAC_GIS_IS22_Pos _U_(22) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS22_Msk (_U_(0x1) << XDMAC_GIS_IS22_Pos) /**< (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS22(value) (XDMAC_GIS_IS22_Msk & ((value) << XDMAC_GIS_IS22_Pos)) +#define XDMAC_GIS_IS23_Pos _U_(23) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Position */ +#define XDMAC_GIS_IS23_Msk (_U_(0x1) << XDMAC_GIS_IS23_Pos) /**< (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit Mask */ +#define XDMAC_GIS_IS23(value) (XDMAC_GIS_IS23_Msk & ((value) << XDMAC_GIS_IS23_Pos)) +#define XDMAC_GIS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GIS) Register Mask */ + +#define XDMAC_GIS_IS_Pos _U_(0) /**< (XDMAC_GIS Position) XDMAC Channel 23 Interrupt Status Bit */ +#define XDMAC_GIS_IS_Msk (_U_(0xFFFFFF) << XDMAC_GIS_IS_Pos) /**< (XDMAC_GIS Mask) IS */ +#define XDMAC_GIS_IS(value) (XDMAC_GIS_IS_Msk & ((value) << XDMAC_GIS_IS_Pos)) + +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) ( /W 32) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0_Pos _U_(0) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Position */ +#define XDMAC_GE_EN0_Msk (_U_(0x1) << XDMAC_GE_EN0_Pos) /**< (XDMAC_GE) XDMAC Channel 0 Enable Bit Mask */ +#define XDMAC_GE_EN0(value) (XDMAC_GE_EN0_Msk & ((value) << XDMAC_GE_EN0_Pos)) +#define XDMAC_GE_EN1_Pos _U_(1) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Position */ +#define XDMAC_GE_EN1_Msk (_U_(0x1) << XDMAC_GE_EN1_Pos) /**< (XDMAC_GE) XDMAC Channel 1 Enable Bit Mask */ +#define XDMAC_GE_EN1(value) (XDMAC_GE_EN1_Msk & ((value) << XDMAC_GE_EN1_Pos)) +#define XDMAC_GE_EN2_Pos _U_(2) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Position */ +#define XDMAC_GE_EN2_Msk (_U_(0x1) << XDMAC_GE_EN2_Pos) /**< (XDMAC_GE) XDMAC Channel 2 Enable Bit Mask */ +#define XDMAC_GE_EN2(value) (XDMAC_GE_EN2_Msk & ((value) << XDMAC_GE_EN2_Pos)) +#define XDMAC_GE_EN3_Pos _U_(3) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Position */ +#define XDMAC_GE_EN3_Msk (_U_(0x1) << XDMAC_GE_EN3_Pos) /**< (XDMAC_GE) XDMAC Channel 3 Enable Bit Mask */ +#define XDMAC_GE_EN3(value) (XDMAC_GE_EN3_Msk & ((value) << XDMAC_GE_EN3_Pos)) +#define XDMAC_GE_EN4_Pos _U_(4) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Position */ +#define XDMAC_GE_EN4_Msk (_U_(0x1) << XDMAC_GE_EN4_Pos) /**< (XDMAC_GE) XDMAC Channel 4 Enable Bit Mask */ +#define XDMAC_GE_EN4(value) (XDMAC_GE_EN4_Msk & ((value) << XDMAC_GE_EN4_Pos)) +#define XDMAC_GE_EN5_Pos _U_(5) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Position */ +#define XDMAC_GE_EN5_Msk (_U_(0x1) << XDMAC_GE_EN5_Pos) /**< (XDMAC_GE) XDMAC Channel 5 Enable Bit Mask */ +#define XDMAC_GE_EN5(value) (XDMAC_GE_EN5_Msk & ((value) << XDMAC_GE_EN5_Pos)) +#define XDMAC_GE_EN6_Pos _U_(6) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Position */ +#define XDMAC_GE_EN6_Msk (_U_(0x1) << XDMAC_GE_EN6_Pos) /**< (XDMAC_GE) XDMAC Channel 6 Enable Bit Mask */ +#define XDMAC_GE_EN6(value) (XDMAC_GE_EN6_Msk & ((value) << XDMAC_GE_EN6_Pos)) +#define XDMAC_GE_EN7_Pos _U_(7) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Position */ +#define XDMAC_GE_EN7_Msk (_U_(0x1) << XDMAC_GE_EN7_Pos) /**< (XDMAC_GE) XDMAC Channel 7 Enable Bit Mask */ +#define XDMAC_GE_EN7(value) (XDMAC_GE_EN7_Msk & ((value) << XDMAC_GE_EN7_Pos)) +#define XDMAC_GE_EN8_Pos _U_(8) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Position */ +#define XDMAC_GE_EN8_Msk (_U_(0x1) << XDMAC_GE_EN8_Pos) /**< (XDMAC_GE) XDMAC Channel 8 Enable Bit Mask */ +#define XDMAC_GE_EN8(value) (XDMAC_GE_EN8_Msk & ((value) << XDMAC_GE_EN8_Pos)) +#define XDMAC_GE_EN9_Pos _U_(9) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Position */ +#define XDMAC_GE_EN9_Msk (_U_(0x1) << XDMAC_GE_EN9_Pos) /**< (XDMAC_GE) XDMAC Channel 9 Enable Bit Mask */ +#define XDMAC_GE_EN9(value) (XDMAC_GE_EN9_Msk & ((value) << XDMAC_GE_EN9_Pos)) +#define XDMAC_GE_EN10_Pos _U_(10) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Position */ +#define XDMAC_GE_EN10_Msk (_U_(0x1) << XDMAC_GE_EN10_Pos) /**< (XDMAC_GE) XDMAC Channel 10 Enable Bit Mask */ +#define XDMAC_GE_EN10(value) (XDMAC_GE_EN10_Msk & ((value) << XDMAC_GE_EN10_Pos)) +#define XDMAC_GE_EN11_Pos _U_(11) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Position */ +#define XDMAC_GE_EN11_Msk (_U_(0x1) << XDMAC_GE_EN11_Pos) /**< (XDMAC_GE) XDMAC Channel 11 Enable Bit Mask */ +#define XDMAC_GE_EN11(value) (XDMAC_GE_EN11_Msk & ((value) << XDMAC_GE_EN11_Pos)) +#define XDMAC_GE_EN12_Pos _U_(12) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Position */ +#define XDMAC_GE_EN12_Msk (_U_(0x1) << XDMAC_GE_EN12_Pos) /**< (XDMAC_GE) XDMAC Channel 12 Enable Bit Mask */ +#define XDMAC_GE_EN12(value) (XDMAC_GE_EN12_Msk & ((value) << XDMAC_GE_EN12_Pos)) +#define XDMAC_GE_EN13_Pos _U_(13) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Position */ +#define XDMAC_GE_EN13_Msk (_U_(0x1) << XDMAC_GE_EN13_Pos) /**< (XDMAC_GE) XDMAC Channel 13 Enable Bit Mask */ +#define XDMAC_GE_EN13(value) (XDMAC_GE_EN13_Msk & ((value) << XDMAC_GE_EN13_Pos)) +#define XDMAC_GE_EN14_Pos _U_(14) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Position */ +#define XDMAC_GE_EN14_Msk (_U_(0x1) << XDMAC_GE_EN14_Pos) /**< (XDMAC_GE) XDMAC Channel 14 Enable Bit Mask */ +#define XDMAC_GE_EN14(value) (XDMAC_GE_EN14_Msk & ((value) << XDMAC_GE_EN14_Pos)) +#define XDMAC_GE_EN15_Pos _U_(15) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Position */ +#define XDMAC_GE_EN15_Msk (_U_(0x1) << XDMAC_GE_EN15_Pos) /**< (XDMAC_GE) XDMAC Channel 15 Enable Bit Mask */ +#define XDMAC_GE_EN15(value) (XDMAC_GE_EN15_Msk & ((value) << XDMAC_GE_EN15_Pos)) +#define XDMAC_GE_EN16_Pos _U_(16) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Position */ +#define XDMAC_GE_EN16_Msk (_U_(0x1) << XDMAC_GE_EN16_Pos) /**< (XDMAC_GE) XDMAC Channel 16 Enable Bit Mask */ +#define XDMAC_GE_EN16(value) (XDMAC_GE_EN16_Msk & ((value) << XDMAC_GE_EN16_Pos)) +#define XDMAC_GE_EN17_Pos _U_(17) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Position */ +#define XDMAC_GE_EN17_Msk (_U_(0x1) << XDMAC_GE_EN17_Pos) /**< (XDMAC_GE) XDMAC Channel 17 Enable Bit Mask */ +#define XDMAC_GE_EN17(value) (XDMAC_GE_EN17_Msk & ((value) << XDMAC_GE_EN17_Pos)) +#define XDMAC_GE_EN18_Pos _U_(18) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Position */ +#define XDMAC_GE_EN18_Msk (_U_(0x1) << XDMAC_GE_EN18_Pos) /**< (XDMAC_GE) XDMAC Channel 18 Enable Bit Mask */ +#define XDMAC_GE_EN18(value) (XDMAC_GE_EN18_Msk & ((value) << XDMAC_GE_EN18_Pos)) +#define XDMAC_GE_EN19_Pos _U_(19) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Position */ +#define XDMAC_GE_EN19_Msk (_U_(0x1) << XDMAC_GE_EN19_Pos) /**< (XDMAC_GE) XDMAC Channel 19 Enable Bit Mask */ +#define XDMAC_GE_EN19(value) (XDMAC_GE_EN19_Msk & ((value) << XDMAC_GE_EN19_Pos)) +#define XDMAC_GE_EN20_Pos _U_(20) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Position */ +#define XDMAC_GE_EN20_Msk (_U_(0x1) << XDMAC_GE_EN20_Pos) /**< (XDMAC_GE) XDMAC Channel 20 Enable Bit Mask */ +#define XDMAC_GE_EN20(value) (XDMAC_GE_EN20_Msk & ((value) << XDMAC_GE_EN20_Pos)) +#define XDMAC_GE_EN21_Pos _U_(21) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Position */ +#define XDMAC_GE_EN21_Msk (_U_(0x1) << XDMAC_GE_EN21_Pos) /**< (XDMAC_GE) XDMAC Channel 21 Enable Bit Mask */ +#define XDMAC_GE_EN21(value) (XDMAC_GE_EN21_Msk & ((value) << XDMAC_GE_EN21_Pos)) +#define XDMAC_GE_EN22_Pos _U_(22) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Position */ +#define XDMAC_GE_EN22_Msk (_U_(0x1) << XDMAC_GE_EN22_Pos) /**< (XDMAC_GE) XDMAC Channel 22 Enable Bit Mask */ +#define XDMAC_GE_EN22(value) (XDMAC_GE_EN22_Msk & ((value) << XDMAC_GE_EN22_Pos)) +#define XDMAC_GE_EN23_Pos _U_(23) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Position */ +#define XDMAC_GE_EN23_Msk (_U_(0x1) << XDMAC_GE_EN23_Pos) /**< (XDMAC_GE) XDMAC Channel 23 Enable Bit Mask */ +#define XDMAC_GE_EN23(value) (XDMAC_GE_EN23_Msk & ((value) << XDMAC_GE_EN23_Pos)) +#define XDMAC_GE_Msk _U_(0x00FFFFFF) /**< (XDMAC_GE) Register Mask */ + +#define XDMAC_GE_EN_Pos _U_(0) /**< (XDMAC_GE Position) XDMAC Channel 23 Enable Bit */ +#define XDMAC_GE_EN_Msk (_U_(0xFFFFFF) << XDMAC_GE_EN_Pos) /**< (XDMAC_GE Mask) EN */ +#define XDMAC_GE_EN(value) (XDMAC_GE_EN_Msk & ((value) << XDMAC_GE_EN_Pos)) + +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) ( /W 32) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0_Pos _U_(0) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Position */ +#define XDMAC_GD_DI0_Msk (_U_(0x1) << XDMAC_GD_DI0_Pos) /**< (XDMAC_GD) XDMAC Channel 0 Disable Bit Mask */ +#define XDMAC_GD_DI0(value) (XDMAC_GD_DI0_Msk & ((value) << XDMAC_GD_DI0_Pos)) +#define XDMAC_GD_DI1_Pos _U_(1) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Position */ +#define XDMAC_GD_DI1_Msk (_U_(0x1) << XDMAC_GD_DI1_Pos) /**< (XDMAC_GD) XDMAC Channel 1 Disable Bit Mask */ +#define XDMAC_GD_DI1(value) (XDMAC_GD_DI1_Msk & ((value) << XDMAC_GD_DI1_Pos)) +#define XDMAC_GD_DI2_Pos _U_(2) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Position */ +#define XDMAC_GD_DI2_Msk (_U_(0x1) << XDMAC_GD_DI2_Pos) /**< (XDMAC_GD) XDMAC Channel 2 Disable Bit Mask */ +#define XDMAC_GD_DI2(value) (XDMAC_GD_DI2_Msk & ((value) << XDMAC_GD_DI2_Pos)) +#define XDMAC_GD_DI3_Pos _U_(3) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Position */ +#define XDMAC_GD_DI3_Msk (_U_(0x1) << XDMAC_GD_DI3_Pos) /**< (XDMAC_GD) XDMAC Channel 3 Disable Bit Mask */ +#define XDMAC_GD_DI3(value) (XDMAC_GD_DI3_Msk & ((value) << XDMAC_GD_DI3_Pos)) +#define XDMAC_GD_DI4_Pos _U_(4) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Position */ +#define XDMAC_GD_DI4_Msk (_U_(0x1) << XDMAC_GD_DI4_Pos) /**< (XDMAC_GD) XDMAC Channel 4 Disable Bit Mask */ +#define XDMAC_GD_DI4(value) (XDMAC_GD_DI4_Msk & ((value) << XDMAC_GD_DI4_Pos)) +#define XDMAC_GD_DI5_Pos _U_(5) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Position */ +#define XDMAC_GD_DI5_Msk (_U_(0x1) << XDMAC_GD_DI5_Pos) /**< (XDMAC_GD) XDMAC Channel 5 Disable Bit Mask */ +#define XDMAC_GD_DI5(value) (XDMAC_GD_DI5_Msk & ((value) << XDMAC_GD_DI5_Pos)) +#define XDMAC_GD_DI6_Pos _U_(6) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Position */ +#define XDMAC_GD_DI6_Msk (_U_(0x1) << XDMAC_GD_DI6_Pos) /**< (XDMAC_GD) XDMAC Channel 6 Disable Bit Mask */ +#define XDMAC_GD_DI6(value) (XDMAC_GD_DI6_Msk & ((value) << XDMAC_GD_DI6_Pos)) +#define XDMAC_GD_DI7_Pos _U_(7) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Position */ +#define XDMAC_GD_DI7_Msk (_U_(0x1) << XDMAC_GD_DI7_Pos) /**< (XDMAC_GD) XDMAC Channel 7 Disable Bit Mask */ +#define XDMAC_GD_DI7(value) (XDMAC_GD_DI7_Msk & ((value) << XDMAC_GD_DI7_Pos)) +#define XDMAC_GD_DI8_Pos _U_(8) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Position */ +#define XDMAC_GD_DI8_Msk (_U_(0x1) << XDMAC_GD_DI8_Pos) /**< (XDMAC_GD) XDMAC Channel 8 Disable Bit Mask */ +#define XDMAC_GD_DI8(value) (XDMAC_GD_DI8_Msk & ((value) << XDMAC_GD_DI8_Pos)) +#define XDMAC_GD_DI9_Pos _U_(9) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Position */ +#define XDMAC_GD_DI9_Msk (_U_(0x1) << XDMAC_GD_DI9_Pos) /**< (XDMAC_GD) XDMAC Channel 9 Disable Bit Mask */ +#define XDMAC_GD_DI9(value) (XDMAC_GD_DI9_Msk & ((value) << XDMAC_GD_DI9_Pos)) +#define XDMAC_GD_DI10_Pos _U_(10) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Position */ +#define XDMAC_GD_DI10_Msk (_U_(0x1) << XDMAC_GD_DI10_Pos) /**< (XDMAC_GD) XDMAC Channel 10 Disable Bit Mask */ +#define XDMAC_GD_DI10(value) (XDMAC_GD_DI10_Msk & ((value) << XDMAC_GD_DI10_Pos)) +#define XDMAC_GD_DI11_Pos _U_(11) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Position */ +#define XDMAC_GD_DI11_Msk (_U_(0x1) << XDMAC_GD_DI11_Pos) /**< (XDMAC_GD) XDMAC Channel 11 Disable Bit Mask */ +#define XDMAC_GD_DI11(value) (XDMAC_GD_DI11_Msk & ((value) << XDMAC_GD_DI11_Pos)) +#define XDMAC_GD_DI12_Pos _U_(12) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Position */ +#define XDMAC_GD_DI12_Msk (_U_(0x1) << XDMAC_GD_DI12_Pos) /**< (XDMAC_GD) XDMAC Channel 12 Disable Bit Mask */ +#define XDMAC_GD_DI12(value) (XDMAC_GD_DI12_Msk & ((value) << XDMAC_GD_DI12_Pos)) +#define XDMAC_GD_DI13_Pos _U_(13) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Position */ +#define XDMAC_GD_DI13_Msk (_U_(0x1) << XDMAC_GD_DI13_Pos) /**< (XDMAC_GD) XDMAC Channel 13 Disable Bit Mask */ +#define XDMAC_GD_DI13(value) (XDMAC_GD_DI13_Msk & ((value) << XDMAC_GD_DI13_Pos)) +#define XDMAC_GD_DI14_Pos _U_(14) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Position */ +#define XDMAC_GD_DI14_Msk (_U_(0x1) << XDMAC_GD_DI14_Pos) /**< (XDMAC_GD) XDMAC Channel 14 Disable Bit Mask */ +#define XDMAC_GD_DI14(value) (XDMAC_GD_DI14_Msk & ((value) << XDMAC_GD_DI14_Pos)) +#define XDMAC_GD_DI15_Pos _U_(15) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Position */ +#define XDMAC_GD_DI15_Msk (_U_(0x1) << XDMAC_GD_DI15_Pos) /**< (XDMAC_GD) XDMAC Channel 15 Disable Bit Mask */ +#define XDMAC_GD_DI15(value) (XDMAC_GD_DI15_Msk & ((value) << XDMAC_GD_DI15_Pos)) +#define XDMAC_GD_DI16_Pos _U_(16) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Position */ +#define XDMAC_GD_DI16_Msk (_U_(0x1) << XDMAC_GD_DI16_Pos) /**< (XDMAC_GD) XDMAC Channel 16 Disable Bit Mask */ +#define XDMAC_GD_DI16(value) (XDMAC_GD_DI16_Msk & ((value) << XDMAC_GD_DI16_Pos)) +#define XDMAC_GD_DI17_Pos _U_(17) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Position */ +#define XDMAC_GD_DI17_Msk (_U_(0x1) << XDMAC_GD_DI17_Pos) /**< (XDMAC_GD) XDMAC Channel 17 Disable Bit Mask */ +#define XDMAC_GD_DI17(value) (XDMAC_GD_DI17_Msk & ((value) << XDMAC_GD_DI17_Pos)) +#define XDMAC_GD_DI18_Pos _U_(18) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Position */ +#define XDMAC_GD_DI18_Msk (_U_(0x1) << XDMAC_GD_DI18_Pos) /**< (XDMAC_GD) XDMAC Channel 18 Disable Bit Mask */ +#define XDMAC_GD_DI18(value) (XDMAC_GD_DI18_Msk & ((value) << XDMAC_GD_DI18_Pos)) +#define XDMAC_GD_DI19_Pos _U_(19) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Position */ +#define XDMAC_GD_DI19_Msk (_U_(0x1) << XDMAC_GD_DI19_Pos) /**< (XDMAC_GD) XDMAC Channel 19 Disable Bit Mask */ +#define XDMAC_GD_DI19(value) (XDMAC_GD_DI19_Msk & ((value) << XDMAC_GD_DI19_Pos)) +#define XDMAC_GD_DI20_Pos _U_(20) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Position */ +#define XDMAC_GD_DI20_Msk (_U_(0x1) << XDMAC_GD_DI20_Pos) /**< (XDMAC_GD) XDMAC Channel 20 Disable Bit Mask */ +#define XDMAC_GD_DI20(value) (XDMAC_GD_DI20_Msk & ((value) << XDMAC_GD_DI20_Pos)) +#define XDMAC_GD_DI21_Pos _U_(21) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Position */ +#define XDMAC_GD_DI21_Msk (_U_(0x1) << XDMAC_GD_DI21_Pos) /**< (XDMAC_GD) XDMAC Channel 21 Disable Bit Mask */ +#define XDMAC_GD_DI21(value) (XDMAC_GD_DI21_Msk & ((value) << XDMAC_GD_DI21_Pos)) +#define XDMAC_GD_DI22_Pos _U_(22) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Position */ +#define XDMAC_GD_DI22_Msk (_U_(0x1) << XDMAC_GD_DI22_Pos) /**< (XDMAC_GD) XDMAC Channel 22 Disable Bit Mask */ +#define XDMAC_GD_DI22(value) (XDMAC_GD_DI22_Msk & ((value) << XDMAC_GD_DI22_Pos)) +#define XDMAC_GD_DI23_Pos _U_(23) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Position */ +#define XDMAC_GD_DI23_Msk (_U_(0x1) << XDMAC_GD_DI23_Pos) /**< (XDMAC_GD) XDMAC Channel 23 Disable Bit Mask */ +#define XDMAC_GD_DI23(value) (XDMAC_GD_DI23_Msk & ((value) << XDMAC_GD_DI23_Pos)) +#define XDMAC_GD_Msk _U_(0x00FFFFFF) /**< (XDMAC_GD) Register Mask */ + +#define XDMAC_GD_DI_Pos _U_(0) /**< (XDMAC_GD Position) XDMAC Channel 23 Disable Bit */ +#define XDMAC_GD_DI_Msk (_U_(0xFFFFFF) << XDMAC_GD_DI_Pos) /**< (XDMAC_GD Mask) DI */ +#define XDMAC_GD_DI(value) (XDMAC_GD_DI_Msk & ((value) << XDMAC_GD_DI_Pos)) + +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) ( R/ 32) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0_Pos _U_(0) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Position */ +#define XDMAC_GS_ST0_Msk (_U_(0x1) << XDMAC_GS_ST0_Pos) /**< (XDMAC_GS) XDMAC Channel 0 Status Bit Mask */ +#define XDMAC_GS_ST0(value) (XDMAC_GS_ST0_Msk & ((value) << XDMAC_GS_ST0_Pos)) +#define XDMAC_GS_ST1_Pos _U_(1) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Position */ +#define XDMAC_GS_ST1_Msk (_U_(0x1) << XDMAC_GS_ST1_Pos) /**< (XDMAC_GS) XDMAC Channel 1 Status Bit Mask */ +#define XDMAC_GS_ST1(value) (XDMAC_GS_ST1_Msk & ((value) << XDMAC_GS_ST1_Pos)) +#define XDMAC_GS_ST2_Pos _U_(2) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Position */ +#define XDMAC_GS_ST2_Msk (_U_(0x1) << XDMAC_GS_ST2_Pos) /**< (XDMAC_GS) XDMAC Channel 2 Status Bit Mask */ +#define XDMAC_GS_ST2(value) (XDMAC_GS_ST2_Msk & ((value) << XDMAC_GS_ST2_Pos)) +#define XDMAC_GS_ST3_Pos _U_(3) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Position */ +#define XDMAC_GS_ST3_Msk (_U_(0x1) << XDMAC_GS_ST3_Pos) /**< (XDMAC_GS) XDMAC Channel 3 Status Bit Mask */ +#define XDMAC_GS_ST3(value) (XDMAC_GS_ST3_Msk & ((value) << XDMAC_GS_ST3_Pos)) +#define XDMAC_GS_ST4_Pos _U_(4) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Position */ +#define XDMAC_GS_ST4_Msk (_U_(0x1) << XDMAC_GS_ST4_Pos) /**< (XDMAC_GS) XDMAC Channel 4 Status Bit Mask */ +#define XDMAC_GS_ST4(value) (XDMAC_GS_ST4_Msk & ((value) << XDMAC_GS_ST4_Pos)) +#define XDMAC_GS_ST5_Pos _U_(5) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Position */ +#define XDMAC_GS_ST5_Msk (_U_(0x1) << XDMAC_GS_ST5_Pos) /**< (XDMAC_GS) XDMAC Channel 5 Status Bit Mask */ +#define XDMAC_GS_ST5(value) (XDMAC_GS_ST5_Msk & ((value) << XDMAC_GS_ST5_Pos)) +#define XDMAC_GS_ST6_Pos _U_(6) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Position */ +#define XDMAC_GS_ST6_Msk (_U_(0x1) << XDMAC_GS_ST6_Pos) /**< (XDMAC_GS) XDMAC Channel 6 Status Bit Mask */ +#define XDMAC_GS_ST6(value) (XDMAC_GS_ST6_Msk & ((value) << XDMAC_GS_ST6_Pos)) +#define XDMAC_GS_ST7_Pos _U_(7) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Position */ +#define XDMAC_GS_ST7_Msk (_U_(0x1) << XDMAC_GS_ST7_Pos) /**< (XDMAC_GS) XDMAC Channel 7 Status Bit Mask */ +#define XDMAC_GS_ST7(value) (XDMAC_GS_ST7_Msk & ((value) << XDMAC_GS_ST7_Pos)) +#define XDMAC_GS_ST8_Pos _U_(8) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Position */ +#define XDMAC_GS_ST8_Msk (_U_(0x1) << XDMAC_GS_ST8_Pos) /**< (XDMAC_GS) XDMAC Channel 8 Status Bit Mask */ +#define XDMAC_GS_ST8(value) (XDMAC_GS_ST8_Msk & ((value) << XDMAC_GS_ST8_Pos)) +#define XDMAC_GS_ST9_Pos _U_(9) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Position */ +#define XDMAC_GS_ST9_Msk (_U_(0x1) << XDMAC_GS_ST9_Pos) /**< (XDMAC_GS) XDMAC Channel 9 Status Bit Mask */ +#define XDMAC_GS_ST9(value) (XDMAC_GS_ST9_Msk & ((value) << XDMAC_GS_ST9_Pos)) +#define XDMAC_GS_ST10_Pos _U_(10) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Position */ +#define XDMAC_GS_ST10_Msk (_U_(0x1) << XDMAC_GS_ST10_Pos) /**< (XDMAC_GS) XDMAC Channel 10 Status Bit Mask */ +#define XDMAC_GS_ST10(value) (XDMAC_GS_ST10_Msk & ((value) << XDMAC_GS_ST10_Pos)) +#define XDMAC_GS_ST11_Pos _U_(11) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Position */ +#define XDMAC_GS_ST11_Msk (_U_(0x1) << XDMAC_GS_ST11_Pos) /**< (XDMAC_GS) XDMAC Channel 11 Status Bit Mask */ +#define XDMAC_GS_ST11(value) (XDMAC_GS_ST11_Msk & ((value) << XDMAC_GS_ST11_Pos)) +#define XDMAC_GS_ST12_Pos _U_(12) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Position */ +#define XDMAC_GS_ST12_Msk (_U_(0x1) << XDMAC_GS_ST12_Pos) /**< (XDMAC_GS) XDMAC Channel 12 Status Bit Mask */ +#define XDMAC_GS_ST12(value) (XDMAC_GS_ST12_Msk & ((value) << XDMAC_GS_ST12_Pos)) +#define XDMAC_GS_ST13_Pos _U_(13) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Position */ +#define XDMAC_GS_ST13_Msk (_U_(0x1) << XDMAC_GS_ST13_Pos) /**< (XDMAC_GS) XDMAC Channel 13 Status Bit Mask */ +#define XDMAC_GS_ST13(value) (XDMAC_GS_ST13_Msk & ((value) << XDMAC_GS_ST13_Pos)) +#define XDMAC_GS_ST14_Pos _U_(14) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Position */ +#define XDMAC_GS_ST14_Msk (_U_(0x1) << XDMAC_GS_ST14_Pos) /**< (XDMAC_GS) XDMAC Channel 14 Status Bit Mask */ +#define XDMAC_GS_ST14(value) (XDMAC_GS_ST14_Msk & ((value) << XDMAC_GS_ST14_Pos)) +#define XDMAC_GS_ST15_Pos _U_(15) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Position */ +#define XDMAC_GS_ST15_Msk (_U_(0x1) << XDMAC_GS_ST15_Pos) /**< (XDMAC_GS) XDMAC Channel 15 Status Bit Mask */ +#define XDMAC_GS_ST15(value) (XDMAC_GS_ST15_Msk & ((value) << XDMAC_GS_ST15_Pos)) +#define XDMAC_GS_ST16_Pos _U_(16) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Position */ +#define XDMAC_GS_ST16_Msk (_U_(0x1) << XDMAC_GS_ST16_Pos) /**< (XDMAC_GS) XDMAC Channel 16 Status Bit Mask */ +#define XDMAC_GS_ST16(value) (XDMAC_GS_ST16_Msk & ((value) << XDMAC_GS_ST16_Pos)) +#define XDMAC_GS_ST17_Pos _U_(17) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Position */ +#define XDMAC_GS_ST17_Msk (_U_(0x1) << XDMAC_GS_ST17_Pos) /**< (XDMAC_GS) XDMAC Channel 17 Status Bit Mask */ +#define XDMAC_GS_ST17(value) (XDMAC_GS_ST17_Msk & ((value) << XDMAC_GS_ST17_Pos)) +#define XDMAC_GS_ST18_Pos _U_(18) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Position */ +#define XDMAC_GS_ST18_Msk (_U_(0x1) << XDMAC_GS_ST18_Pos) /**< (XDMAC_GS) XDMAC Channel 18 Status Bit Mask */ +#define XDMAC_GS_ST18(value) (XDMAC_GS_ST18_Msk & ((value) << XDMAC_GS_ST18_Pos)) +#define XDMAC_GS_ST19_Pos _U_(19) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Position */ +#define XDMAC_GS_ST19_Msk (_U_(0x1) << XDMAC_GS_ST19_Pos) /**< (XDMAC_GS) XDMAC Channel 19 Status Bit Mask */ +#define XDMAC_GS_ST19(value) (XDMAC_GS_ST19_Msk & ((value) << XDMAC_GS_ST19_Pos)) +#define XDMAC_GS_ST20_Pos _U_(20) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Position */ +#define XDMAC_GS_ST20_Msk (_U_(0x1) << XDMAC_GS_ST20_Pos) /**< (XDMAC_GS) XDMAC Channel 20 Status Bit Mask */ +#define XDMAC_GS_ST20(value) (XDMAC_GS_ST20_Msk & ((value) << XDMAC_GS_ST20_Pos)) +#define XDMAC_GS_ST21_Pos _U_(21) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Position */ +#define XDMAC_GS_ST21_Msk (_U_(0x1) << XDMAC_GS_ST21_Pos) /**< (XDMAC_GS) XDMAC Channel 21 Status Bit Mask */ +#define XDMAC_GS_ST21(value) (XDMAC_GS_ST21_Msk & ((value) << XDMAC_GS_ST21_Pos)) +#define XDMAC_GS_ST22_Pos _U_(22) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Position */ +#define XDMAC_GS_ST22_Msk (_U_(0x1) << XDMAC_GS_ST22_Pos) /**< (XDMAC_GS) XDMAC Channel 22 Status Bit Mask */ +#define XDMAC_GS_ST22(value) (XDMAC_GS_ST22_Msk & ((value) << XDMAC_GS_ST22_Pos)) +#define XDMAC_GS_ST23_Pos _U_(23) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Position */ +#define XDMAC_GS_ST23_Msk (_U_(0x1) << XDMAC_GS_ST23_Pos) /**< (XDMAC_GS) XDMAC Channel 23 Status Bit Mask */ +#define XDMAC_GS_ST23(value) (XDMAC_GS_ST23_Msk & ((value) << XDMAC_GS_ST23_Pos)) +#define XDMAC_GS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GS) Register Mask */ + +#define XDMAC_GS_ST_Pos _U_(0) /**< (XDMAC_GS Position) XDMAC Channel 23 Status Bit */ +#define XDMAC_GS_ST_Msk (_U_(0xFFFFFF) << XDMAC_GS_ST_Pos) /**< (XDMAC_GS Mask) ST */ +#define XDMAC_GS_ST(value) (XDMAC_GS_ST_Msk & ((value) << XDMAC_GS_ST_Pos)) + +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) (R/W 32) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0_Pos _U_(0) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Position */ +#define XDMAC_GRS_RS0_Msk (_U_(0x1) << XDMAC_GRS_RS0_Pos) /**< (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS0(value) (XDMAC_GRS_RS0_Msk & ((value) << XDMAC_GRS_RS0_Pos)) +#define XDMAC_GRS_RS1_Pos _U_(1) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Position */ +#define XDMAC_GRS_RS1_Msk (_U_(0x1) << XDMAC_GRS_RS1_Pos) /**< (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS1(value) (XDMAC_GRS_RS1_Msk & ((value) << XDMAC_GRS_RS1_Pos)) +#define XDMAC_GRS_RS2_Pos _U_(2) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Position */ +#define XDMAC_GRS_RS2_Msk (_U_(0x1) << XDMAC_GRS_RS2_Pos) /**< (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS2(value) (XDMAC_GRS_RS2_Msk & ((value) << XDMAC_GRS_RS2_Pos)) +#define XDMAC_GRS_RS3_Pos _U_(3) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Position */ +#define XDMAC_GRS_RS3_Msk (_U_(0x1) << XDMAC_GRS_RS3_Pos) /**< (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS3(value) (XDMAC_GRS_RS3_Msk & ((value) << XDMAC_GRS_RS3_Pos)) +#define XDMAC_GRS_RS4_Pos _U_(4) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Position */ +#define XDMAC_GRS_RS4_Msk (_U_(0x1) << XDMAC_GRS_RS4_Pos) /**< (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS4(value) (XDMAC_GRS_RS4_Msk & ((value) << XDMAC_GRS_RS4_Pos)) +#define XDMAC_GRS_RS5_Pos _U_(5) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Position */ +#define XDMAC_GRS_RS5_Msk (_U_(0x1) << XDMAC_GRS_RS5_Pos) /**< (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS5(value) (XDMAC_GRS_RS5_Msk & ((value) << XDMAC_GRS_RS5_Pos)) +#define XDMAC_GRS_RS6_Pos _U_(6) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Position */ +#define XDMAC_GRS_RS6_Msk (_U_(0x1) << XDMAC_GRS_RS6_Pos) /**< (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS6(value) (XDMAC_GRS_RS6_Msk & ((value) << XDMAC_GRS_RS6_Pos)) +#define XDMAC_GRS_RS7_Pos _U_(7) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Position */ +#define XDMAC_GRS_RS7_Msk (_U_(0x1) << XDMAC_GRS_RS7_Pos) /**< (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS7(value) (XDMAC_GRS_RS7_Msk & ((value) << XDMAC_GRS_RS7_Pos)) +#define XDMAC_GRS_RS8_Pos _U_(8) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Position */ +#define XDMAC_GRS_RS8_Msk (_U_(0x1) << XDMAC_GRS_RS8_Pos) /**< (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS8(value) (XDMAC_GRS_RS8_Msk & ((value) << XDMAC_GRS_RS8_Pos)) +#define XDMAC_GRS_RS9_Pos _U_(9) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Position */ +#define XDMAC_GRS_RS9_Msk (_U_(0x1) << XDMAC_GRS_RS9_Pos) /**< (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS9(value) (XDMAC_GRS_RS9_Msk & ((value) << XDMAC_GRS_RS9_Pos)) +#define XDMAC_GRS_RS10_Pos _U_(10) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Position */ +#define XDMAC_GRS_RS10_Msk (_U_(0x1) << XDMAC_GRS_RS10_Pos) /**< (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS10(value) (XDMAC_GRS_RS10_Msk & ((value) << XDMAC_GRS_RS10_Pos)) +#define XDMAC_GRS_RS11_Pos _U_(11) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Position */ +#define XDMAC_GRS_RS11_Msk (_U_(0x1) << XDMAC_GRS_RS11_Pos) /**< (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS11(value) (XDMAC_GRS_RS11_Msk & ((value) << XDMAC_GRS_RS11_Pos)) +#define XDMAC_GRS_RS12_Pos _U_(12) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Position */ +#define XDMAC_GRS_RS12_Msk (_U_(0x1) << XDMAC_GRS_RS12_Pos) /**< (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS12(value) (XDMAC_GRS_RS12_Msk & ((value) << XDMAC_GRS_RS12_Pos)) +#define XDMAC_GRS_RS13_Pos _U_(13) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Position */ +#define XDMAC_GRS_RS13_Msk (_U_(0x1) << XDMAC_GRS_RS13_Pos) /**< (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS13(value) (XDMAC_GRS_RS13_Msk & ((value) << XDMAC_GRS_RS13_Pos)) +#define XDMAC_GRS_RS14_Pos _U_(14) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Position */ +#define XDMAC_GRS_RS14_Msk (_U_(0x1) << XDMAC_GRS_RS14_Pos) /**< (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS14(value) (XDMAC_GRS_RS14_Msk & ((value) << XDMAC_GRS_RS14_Pos)) +#define XDMAC_GRS_RS15_Pos _U_(15) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Position */ +#define XDMAC_GRS_RS15_Msk (_U_(0x1) << XDMAC_GRS_RS15_Pos) /**< (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS15(value) (XDMAC_GRS_RS15_Msk & ((value) << XDMAC_GRS_RS15_Pos)) +#define XDMAC_GRS_RS16_Pos _U_(16) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Position */ +#define XDMAC_GRS_RS16_Msk (_U_(0x1) << XDMAC_GRS_RS16_Pos) /**< (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS16(value) (XDMAC_GRS_RS16_Msk & ((value) << XDMAC_GRS_RS16_Pos)) +#define XDMAC_GRS_RS17_Pos _U_(17) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Position */ +#define XDMAC_GRS_RS17_Msk (_U_(0x1) << XDMAC_GRS_RS17_Pos) /**< (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS17(value) (XDMAC_GRS_RS17_Msk & ((value) << XDMAC_GRS_RS17_Pos)) +#define XDMAC_GRS_RS18_Pos _U_(18) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Position */ +#define XDMAC_GRS_RS18_Msk (_U_(0x1) << XDMAC_GRS_RS18_Pos) /**< (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS18(value) (XDMAC_GRS_RS18_Msk & ((value) << XDMAC_GRS_RS18_Pos)) +#define XDMAC_GRS_RS19_Pos _U_(19) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Position */ +#define XDMAC_GRS_RS19_Msk (_U_(0x1) << XDMAC_GRS_RS19_Pos) /**< (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS19(value) (XDMAC_GRS_RS19_Msk & ((value) << XDMAC_GRS_RS19_Pos)) +#define XDMAC_GRS_RS20_Pos _U_(20) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Position */ +#define XDMAC_GRS_RS20_Msk (_U_(0x1) << XDMAC_GRS_RS20_Pos) /**< (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS20(value) (XDMAC_GRS_RS20_Msk & ((value) << XDMAC_GRS_RS20_Pos)) +#define XDMAC_GRS_RS21_Pos _U_(21) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Position */ +#define XDMAC_GRS_RS21_Msk (_U_(0x1) << XDMAC_GRS_RS21_Pos) /**< (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS21(value) (XDMAC_GRS_RS21_Msk & ((value) << XDMAC_GRS_RS21_Pos)) +#define XDMAC_GRS_RS22_Pos _U_(22) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Position */ +#define XDMAC_GRS_RS22_Msk (_U_(0x1) << XDMAC_GRS_RS22_Pos) /**< (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS22(value) (XDMAC_GRS_RS22_Msk & ((value) << XDMAC_GRS_RS22_Pos)) +#define XDMAC_GRS_RS23_Pos _U_(23) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Position */ +#define XDMAC_GRS_RS23_Msk (_U_(0x1) << XDMAC_GRS_RS23_Pos) /**< (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit Mask */ +#define XDMAC_GRS_RS23(value) (XDMAC_GRS_RS23_Msk & ((value) << XDMAC_GRS_RS23_Pos)) +#define XDMAC_GRS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRS) Register Mask */ + +#define XDMAC_GRS_RS_Pos _U_(0) /**< (XDMAC_GRS Position) XDMAC Channel 23 Read Suspend Bit */ +#define XDMAC_GRS_RS_Msk (_U_(0xFFFFFF) << XDMAC_GRS_RS_Pos) /**< (XDMAC_GRS Mask) RS */ +#define XDMAC_GRS_RS(value) (XDMAC_GRS_RS_Msk & ((value) << XDMAC_GRS_RS_Pos)) + +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) (R/W 32) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0_Pos _U_(0) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Position */ +#define XDMAC_GWS_WS0_Msk (_U_(0x1) << XDMAC_GWS_WS0_Pos) /**< (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS0(value) (XDMAC_GWS_WS0_Msk & ((value) << XDMAC_GWS_WS0_Pos)) +#define XDMAC_GWS_WS1_Pos _U_(1) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Position */ +#define XDMAC_GWS_WS1_Msk (_U_(0x1) << XDMAC_GWS_WS1_Pos) /**< (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS1(value) (XDMAC_GWS_WS1_Msk & ((value) << XDMAC_GWS_WS1_Pos)) +#define XDMAC_GWS_WS2_Pos _U_(2) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Position */ +#define XDMAC_GWS_WS2_Msk (_U_(0x1) << XDMAC_GWS_WS2_Pos) /**< (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS2(value) (XDMAC_GWS_WS2_Msk & ((value) << XDMAC_GWS_WS2_Pos)) +#define XDMAC_GWS_WS3_Pos _U_(3) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Position */ +#define XDMAC_GWS_WS3_Msk (_U_(0x1) << XDMAC_GWS_WS3_Pos) /**< (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS3(value) (XDMAC_GWS_WS3_Msk & ((value) << XDMAC_GWS_WS3_Pos)) +#define XDMAC_GWS_WS4_Pos _U_(4) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Position */ +#define XDMAC_GWS_WS4_Msk (_U_(0x1) << XDMAC_GWS_WS4_Pos) /**< (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS4(value) (XDMAC_GWS_WS4_Msk & ((value) << XDMAC_GWS_WS4_Pos)) +#define XDMAC_GWS_WS5_Pos _U_(5) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Position */ +#define XDMAC_GWS_WS5_Msk (_U_(0x1) << XDMAC_GWS_WS5_Pos) /**< (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS5(value) (XDMAC_GWS_WS5_Msk & ((value) << XDMAC_GWS_WS5_Pos)) +#define XDMAC_GWS_WS6_Pos _U_(6) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Position */ +#define XDMAC_GWS_WS6_Msk (_U_(0x1) << XDMAC_GWS_WS6_Pos) /**< (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS6(value) (XDMAC_GWS_WS6_Msk & ((value) << XDMAC_GWS_WS6_Pos)) +#define XDMAC_GWS_WS7_Pos _U_(7) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Position */ +#define XDMAC_GWS_WS7_Msk (_U_(0x1) << XDMAC_GWS_WS7_Pos) /**< (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS7(value) (XDMAC_GWS_WS7_Msk & ((value) << XDMAC_GWS_WS7_Pos)) +#define XDMAC_GWS_WS8_Pos _U_(8) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Position */ +#define XDMAC_GWS_WS8_Msk (_U_(0x1) << XDMAC_GWS_WS8_Pos) /**< (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS8(value) (XDMAC_GWS_WS8_Msk & ((value) << XDMAC_GWS_WS8_Pos)) +#define XDMAC_GWS_WS9_Pos _U_(9) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Position */ +#define XDMAC_GWS_WS9_Msk (_U_(0x1) << XDMAC_GWS_WS9_Pos) /**< (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS9(value) (XDMAC_GWS_WS9_Msk & ((value) << XDMAC_GWS_WS9_Pos)) +#define XDMAC_GWS_WS10_Pos _U_(10) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Position */ +#define XDMAC_GWS_WS10_Msk (_U_(0x1) << XDMAC_GWS_WS10_Pos) /**< (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS10(value) (XDMAC_GWS_WS10_Msk & ((value) << XDMAC_GWS_WS10_Pos)) +#define XDMAC_GWS_WS11_Pos _U_(11) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Position */ +#define XDMAC_GWS_WS11_Msk (_U_(0x1) << XDMAC_GWS_WS11_Pos) /**< (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS11(value) (XDMAC_GWS_WS11_Msk & ((value) << XDMAC_GWS_WS11_Pos)) +#define XDMAC_GWS_WS12_Pos _U_(12) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Position */ +#define XDMAC_GWS_WS12_Msk (_U_(0x1) << XDMAC_GWS_WS12_Pos) /**< (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS12(value) (XDMAC_GWS_WS12_Msk & ((value) << XDMAC_GWS_WS12_Pos)) +#define XDMAC_GWS_WS13_Pos _U_(13) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Position */ +#define XDMAC_GWS_WS13_Msk (_U_(0x1) << XDMAC_GWS_WS13_Pos) /**< (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS13(value) (XDMAC_GWS_WS13_Msk & ((value) << XDMAC_GWS_WS13_Pos)) +#define XDMAC_GWS_WS14_Pos _U_(14) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Position */ +#define XDMAC_GWS_WS14_Msk (_U_(0x1) << XDMAC_GWS_WS14_Pos) /**< (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS14(value) (XDMAC_GWS_WS14_Msk & ((value) << XDMAC_GWS_WS14_Pos)) +#define XDMAC_GWS_WS15_Pos _U_(15) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Position */ +#define XDMAC_GWS_WS15_Msk (_U_(0x1) << XDMAC_GWS_WS15_Pos) /**< (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS15(value) (XDMAC_GWS_WS15_Msk & ((value) << XDMAC_GWS_WS15_Pos)) +#define XDMAC_GWS_WS16_Pos _U_(16) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Position */ +#define XDMAC_GWS_WS16_Msk (_U_(0x1) << XDMAC_GWS_WS16_Pos) /**< (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS16(value) (XDMAC_GWS_WS16_Msk & ((value) << XDMAC_GWS_WS16_Pos)) +#define XDMAC_GWS_WS17_Pos _U_(17) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Position */ +#define XDMAC_GWS_WS17_Msk (_U_(0x1) << XDMAC_GWS_WS17_Pos) /**< (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS17(value) (XDMAC_GWS_WS17_Msk & ((value) << XDMAC_GWS_WS17_Pos)) +#define XDMAC_GWS_WS18_Pos _U_(18) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Position */ +#define XDMAC_GWS_WS18_Msk (_U_(0x1) << XDMAC_GWS_WS18_Pos) /**< (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS18(value) (XDMAC_GWS_WS18_Msk & ((value) << XDMAC_GWS_WS18_Pos)) +#define XDMAC_GWS_WS19_Pos _U_(19) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Position */ +#define XDMAC_GWS_WS19_Msk (_U_(0x1) << XDMAC_GWS_WS19_Pos) /**< (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS19(value) (XDMAC_GWS_WS19_Msk & ((value) << XDMAC_GWS_WS19_Pos)) +#define XDMAC_GWS_WS20_Pos _U_(20) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Position */ +#define XDMAC_GWS_WS20_Msk (_U_(0x1) << XDMAC_GWS_WS20_Pos) /**< (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS20(value) (XDMAC_GWS_WS20_Msk & ((value) << XDMAC_GWS_WS20_Pos)) +#define XDMAC_GWS_WS21_Pos _U_(21) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Position */ +#define XDMAC_GWS_WS21_Msk (_U_(0x1) << XDMAC_GWS_WS21_Pos) /**< (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS21(value) (XDMAC_GWS_WS21_Msk & ((value) << XDMAC_GWS_WS21_Pos)) +#define XDMAC_GWS_WS22_Pos _U_(22) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Position */ +#define XDMAC_GWS_WS22_Msk (_U_(0x1) << XDMAC_GWS_WS22_Pos) /**< (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS22(value) (XDMAC_GWS_WS22_Msk & ((value) << XDMAC_GWS_WS22_Pos)) +#define XDMAC_GWS_WS23_Pos _U_(23) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Position */ +#define XDMAC_GWS_WS23_Msk (_U_(0x1) << XDMAC_GWS_WS23_Pos) /**< (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit Mask */ +#define XDMAC_GWS_WS23(value) (XDMAC_GWS_WS23_Msk & ((value) << XDMAC_GWS_WS23_Pos)) +#define XDMAC_GWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GWS) Register Mask */ + +#define XDMAC_GWS_WS_Pos _U_(0) /**< (XDMAC_GWS Position) XDMAC Channel 23 Write Suspend Bit */ +#define XDMAC_GWS_WS_Msk (_U_(0xFFFFFF) << XDMAC_GWS_WS_Pos) /**< (XDMAC_GWS Mask) WS */ +#define XDMAC_GWS_WS(value) (XDMAC_GWS_WS_Msk & ((value) << XDMAC_GWS_WS_Pos)) + +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) ( /W 32) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0_Pos _U_(0) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS0_Msk (_U_(0x1) << XDMAC_GRWS_RWS0_Pos) /**< (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS0(value) (XDMAC_GRWS_RWS0_Msk & ((value) << XDMAC_GRWS_RWS0_Pos)) +#define XDMAC_GRWS_RWS1_Pos _U_(1) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS1_Msk (_U_(0x1) << XDMAC_GRWS_RWS1_Pos) /**< (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS1(value) (XDMAC_GRWS_RWS1_Msk & ((value) << XDMAC_GRWS_RWS1_Pos)) +#define XDMAC_GRWS_RWS2_Pos _U_(2) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS2_Msk (_U_(0x1) << XDMAC_GRWS_RWS2_Pos) /**< (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS2(value) (XDMAC_GRWS_RWS2_Msk & ((value) << XDMAC_GRWS_RWS2_Pos)) +#define XDMAC_GRWS_RWS3_Pos _U_(3) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS3_Msk (_U_(0x1) << XDMAC_GRWS_RWS3_Pos) /**< (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS3(value) (XDMAC_GRWS_RWS3_Msk & ((value) << XDMAC_GRWS_RWS3_Pos)) +#define XDMAC_GRWS_RWS4_Pos _U_(4) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS4_Msk (_U_(0x1) << XDMAC_GRWS_RWS4_Pos) /**< (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS4(value) (XDMAC_GRWS_RWS4_Msk & ((value) << XDMAC_GRWS_RWS4_Pos)) +#define XDMAC_GRWS_RWS5_Pos _U_(5) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS5_Msk (_U_(0x1) << XDMAC_GRWS_RWS5_Pos) /**< (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS5(value) (XDMAC_GRWS_RWS5_Msk & ((value) << XDMAC_GRWS_RWS5_Pos)) +#define XDMAC_GRWS_RWS6_Pos _U_(6) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS6_Msk (_U_(0x1) << XDMAC_GRWS_RWS6_Pos) /**< (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS6(value) (XDMAC_GRWS_RWS6_Msk & ((value) << XDMAC_GRWS_RWS6_Pos)) +#define XDMAC_GRWS_RWS7_Pos _U_(7) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS7_Msk (_U_(0x1) << XDMAC_GRWS_RWS7_Pos) /**< (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS7(value) (XDMAC_GRWS_RWS7_Msk & ((value) << XDMAC_GRWS_RWS7_Pos)) +#define XDMAC_GRWS_RWS8_Pos _U_(8) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS8_Msk (_U_(0x1) << XDMAC_GRWS_RWS8_Pos) /**< (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS8(value) (XDMAC_GRWS_RWS8_Msk & ((value) << XDMAC_GRWS_RWS8_Pos)) +#define XDMAC_GRWS_RWS9_Pos _U_(9) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS9_Msk (_U_(0x1) << XDMAC_GRWS_RWS9_Pos) /**< (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS9(value) (XDMAC_GRWS_RWS9_Msk & ((value) << XDMAC_GRWS_RWS9_Pos)) +#define XDMAC_GRWS_RWS10_Pos _U_(10) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS10_Msk (_U_(0x1) << XDMAC_GRWS_RWS10_Pos) /**< (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS10(value) (XDMAC_GRWS_RWS10_Msk & ((value) << XDMAC_GRWS_RWS10_Pos)) +#define XDMAC_GRWS_RWS11_Pos _U_(11) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS11_Msk (_U_(0x1) << XDMAC_GRWS_RWS11_Pos) /**< (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS11(value) (XDMAC_GRWS_RWS11_Msk & ((value) << XDMAC_GRWS_RWS11_Pos)) +#define XDMAC_GRWS_RWS12_Pos _U_(12) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS12_Msk (_U_(0x1) << XDMAC_GRWS_RWS12_Pos) /**< (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS12(value) (XDMAC_GRWS_RWS12_Msk & ((value) << XDMAC_GRWS_RWS12_Pos)) +#define XDMAC_GRWS_RWS13_Pos _U_(13) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS13_Msk (_U_(0x1) << XDMAC_GRWS_RWS13_Pos) /**< (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS13(value) (XDMAC_GRWS_RWS13_Msk & ((value) << XDMAC_GRWS_RWS13_Pos)) +#define XDMAC_GRWS_RWS14_Pos _U_(14) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS14_Msk (_U_(0x1) << XDMAC_GRWS_RWS14_Pos) /**< (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS14(value) (XDMAC_GRWS_RWS14_Msk & ((value) << XDMAC_GRWS_RWS14_Pos)) +#define XDMAC_GRWS_RWS15_Pos _U_(15) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS15_Msk (_U_(0x1) << XDMAC_GRWS_RWS15_Pos) /**< (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS15(value) (XDMAC_GRWS_RWS15_Msk & ((value) << XDMAC_GRWS_RWS15_Pos)) +#define XDMAC_GRWS_RWS16_Pos _U_(16) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS16_Msk (_U_(0x1) << XDMAC_GRWS_RWS16_Pos) /**< (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS16(value) (XDMAC_GRWS_RWS16_Msk & ((value) << XDMAC_GRWS_RWS16_Pos)) +#define XDMAC_GRWS_RWS17_Pos _U_(17) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS17_Msk (_U_(0x1) << XDMAC_GRWS_RWS17_Pos) /**< (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS17(value) (XDMAC_GRWS_RWS17_Msk & ((value) << XDMAC_GRWS_RWS17_Pos)) +#define XDMAC_GRWS_RWS18_Pos _U_(18) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS18_Msk (_U_(0x1) << XDMAC_GRWS_RWS18_Pos) /**< (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS18(value) (XDMAC_GRWS_RWS18_Msk & ((value) << XDMAC_GRWS_RWS18_Pos)) +#define XDMAC_GRWS_RWS19_Pos _U_(19) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS19_Msk (_U_(0x1) << XDMAC_GRWS_RWS19_Pos) /**< (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS19(value) (XDMAC_GRWS_RWS19_Msk & ((value) << XDMAC_GRWS_RWS19_Pos)) +#define XDMAC_GRWS_RWS20_Pos _U_(20) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS20_Msk (_U_(0x1) << XDMAC_GRWS_RWS20_Pos) /**< (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS20(value) (XDMAC_GRWS_RWS20_Msk & ((value) << XDMAC_GRWS_RWS20_Pos)) +#define XDMAC_GRWS_RWS21_Pos _U_(21) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS21_Msk (_U_(0x1) << XDMAC_GRWS_RWS21_Pos) /**< (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS21(value) (XDMAC_GRWS_RWS21_Msk & ((value) << XDMAC_GRWS_RWS21_Pos)) +#define XDMAC_GRWS_RWS22_Pos _U_(22) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS22_Msk (_U_(0x1) << XDMAC_GRWS_RWS22_Pos) /**< (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS22(value) (XDMAC_GRWS_RWS22_Msk & ((value) << XDMAC_GRWS_RWS22_Pos)) +#define XDMAC_GRWS_RWS23_Pos _U_(23) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Position */ +#define XDMAC_GRWS_RWS23_Msk (_U_(0x1) << XDMAC_GRWS_RWS23_Pos) /**< (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit Mask */ +#define XDMAC_GRWS_RWS23(value) (XDMAC_GRWS_RWS23_Msk & ((value) << XDMAC_GRWS_RWS23_Pos)) +#define XDMAC_GRWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRWS) Register Mask */ + +#define XDMAC_GRWS_RWS_Pos _U_(0) /**< (XDMAC_GRWS Position) XDMAC Channel 23 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS_Msk (_U_(0xFFFFFF) << XDMAC_GRWS_RWS_Pos) /**< (XDMAC_GRWS Mask) RWS */ +#define XDMAC_GRWS_RWS(value) (XDMAC_GRWS_RWS_Msk & ((value) << XDMAC_GRWS_RWS_Pos)) + +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) ( /W 32) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0_Pos _U_(0) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR0_Msk (_U_(0x1) << XDMAC_GRWR_RWR0_Pos) /**< (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR0(value) (XDMAC_GRWR_RWR0_Msk & ((value) << XDMAC_GRWR_RWR0_Pos)) +#define XDMAC_GRWR_RWR1_Pos _U_(1) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR1_Msk (_U_(0x1) << XDMAC_GRWR_RWR1_Pos) /**< (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR1(value) (XDMAC_GRWR_RWR1_Msk & ((value) << XDMAC_GRWR_RWR1_Pos)) +#define XDMAC_GRWR_RWR2_Pos _U_(2) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR2_Msk (_U_(0x1) << XDMAC_GRWR_RWR2_Pos) /**< (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR2(value) (XDMAC_GRWR_RWR2_Msk & ((value) << XDMAC_GRWR_RWR2_Pos)) +#define XDMAC_GRWR_RWR3_Pos _U_(3) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR3_Msk (_U_(0x1) << XDMAC_GRWR_RWR3_Pos) /**< (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR3(value) (XDMAC_GRWR_RWR3_Msk & ((value) << XDMAC_GRWR_RWR3_Pos)) +#define XDMAC_GRWR_RWR4_Pos _U_(4) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR4_Msk (_U_(0x1) << XDMAC_GRWR_RWR4_Pos) /**< (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR4(value) (XDMAC_GRWR_RWR4_Msk & ((value) << XDMAC_GRWR_RWR4_Pos)) +#define XDMAC_GRWR_RWR5_Pos _U_(5) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR5_Msk (_U_(0x1) << XDMAC_GRWR_RWR5_Pos) /**< (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR5(value) (XDMAC_GRWR_RWR5_Msk & ((value) << XDMAC_GRWR_RWR5_Pos)) +#define XDMAC_GRWR_RWR6_Pos _U_(6) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR6_Msk (_U_(0x1) << XDMAC_GRWR_RWR6_Pos) /**< (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR6(value) (XDMAC_GRWR_RWR6_Msk & ((value) << XDMAC_GRWR_RWR6_Pos)) +#define XDMAC_GRWR_RWR7_Pos _U_(7) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR7_Msk (_U_(0x1) << XDMAC_GRWR_RWR7_Pos) /**< (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR7(value) (XDMAC_GRWR_RWR7_Msk & ((value) << XDMAC_GRWR_RWR7_Pos)) +#define XDMAC_GRWR_RWR8_Pos _U_(8) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR8_Msk (_U_(0x1) << XDMAC_GRWR_RWR8_Pos) /**< (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR8(value) (XDMAC_GRWR_RWR8_Msk & ((value) << XDMAC_GRWR_RWR8_Pos)) +#define XDMAC_GRWR_RWR9_Pos _U_(9) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR9_Msk (_U_(0x1) << XDMAC_GRWR_RWR9_Pos) /**< (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR9(value) (XDMAC_GRWR_RWR9_Msk & ((value) << XDMAC_GRWR_RWR9_Pos)) +#define XDMAC_GRWR_RWR10_Pos _U_(10) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR10_Msk (_U_(0x1) << XDMAC_GRWR_RWR10_Pos) /**< (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR10(value) (XDMAC_GRWR_RWR10_Msk & ((value) << XDMAC_GRWR_RWR10_Pos)) +#define XDMAC_GRWR_RWR11_Pos _U_(11) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR11_Msk (_U_(0x1) << XDMAC_GRWR_RWR11_Pos) /**< (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR11(value) (XDMAC_GRWR_RWR11_Msk & ((value) << XDMAC_GRWR_RWR11_Pos)) +#define XDMAC_GRWR_RWR12_Pos _U_(12) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR12_Msk (_U_(0x1) << XDMAC_GRWR_RWR12_Pos) /**< (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR12(value) (XDMAC_GRWR_RWR12_Msk & ((value) << XDMAC_GRWR_RWR12_Pos)) +#define XDMAC_GRWR_RWR13_Pos _U_(13) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR13_Msk (_U_(0x1) << XDMAC_GRWR_RWR13_Pos) /**< (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR13(value) (XDMAC_GRWR_RWR13_Msk & ((value) << XDMAC_GRWR_RWR13_Pos)) +#define XDMAC_GRWR_RWR14_Pos _U_(14) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR14_Msk (_U_(0x1) << XDMAC_GRWR_RWR14_Pos) /**< (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR14(value) (XDMAC_GRWR_RWR14_Msk & ((value) << XDMAC_GRWR_RWR14_Pos)) +#define XDMAC_GRWR_RWR15_Pos _U_(15) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR15_Msk (_U_(0x1) << XDMAC_GRWR_RWR15_Pos) /**< (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR15(value) (XDMAC_GRWR_RWR15_Msk & ((value) << XDMAC_GRWR_RWR15_Pos)) +#define XDMAC_GRWR_RWR16_Pos _U_(16) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR16_Msk (_U_(0x1) << XDMAC_GRWR_RWR16_Pos) /**< (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR16(value) (XDMAC_GRWR_RWR16_Msk & ((value) << XDMAC_GRWR_RWR16_Pos)) +#define XDMAC_GRWR_RWR17_Pos _U_(17) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR17_Msk (_U_(0x1) << XDMAC_GRWR_RWR17_Pos) /**< (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR17(value) (XDMAC_GRWR_RWR17_Msk & ((value) << XDMAC_GRWR_RWR17_Pos)) +#define XDMAC_GRWR_RWR18_Pos _U_(18) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR18_Msk (_U_(0x1) << XDMAC_GRWR_RWR18_Pos) /**< (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR18(value) (XDMAC_GRWR_RWR18_Msk & ((value) << XDMAC_GRWR_RWR18_Pos)) +#define XDMAC_GRWR_RWR19_Pos _U_(19) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR19_Msk (_U_(0x1) << XDMAC_GRWR_RWR19_Pos) /**< (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR19(value) (XDMAC_GRWR_RWR19_Msk & ((value) << XDMAC_GRWR_RWR19_Pos)) +#define XDMAC_GRWR_RWR20_Pos _U_(20) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR20_Msk (_U_(0x1) << XDMAC_GRWR_RWR20_Pos) /**< (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR20(value) (XDMAC_GRWR_RWR20_Msk & ((value) << XDMAC_GRWR_RWR20_Pos)) +#define XDMAC_GRWR_RWR21_Pos _U_(21) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR21_Msk (_U_(0x1) << XDMAC_GRWR_RWR21_Pos) /**< (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR21(value) (XDMAC_GRWR_RWR21_Msk & ((value) << XDMAC_GRWR_RWR21_Pos)) +#define XDMAC_GRWR_RWR22_Pos _U_(22) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR22_Msk (_U_(0x1) << XDMAC_GRWR_RWR22_Pos) /**< (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR22(value) (XDMAC_GRWR_RWR22_Msk & ((value) << XDMAC_GRWR_RWR22_Pos)) +#define XDMAC_GRWR_RWR23_Pos _U_(23) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Position */ +#define XDMAC_GRWR_RWR23_Msk (_U_(0x1) << XDMAC_GRWR_RWR23_Pos) /**< (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit Mask */ +#define XDMAC_GRWR_RWR23(value) (XDMAC_GRWR_RWR23_Msk & ((value) << XDMAC_GRWR_RWR23_Pos)) +#define XDMAC_GRWR_Msk _U_(0x00FFFFFF) /**< (XDMAC_GRWR) Register Mask */ + +#define XDMAC_GRWR_RWR_Pos _U_(0) /**< (XDMAC_GRWR Position) XDMAC Channel 23 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR_Msk (_U_(0xFFFFFF) << XDMAC_GRWR_RWR_Pos) /**< (XDMAC_GRWR Mask) RWR */ +#define XDMAC_GRWR_RWR(value) (XDMAC_GRWR_RWR_Msk & ((value) << XDMAC_GRWR_RWR_Pos)) + +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) ( /W 32) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0_Pos _U_(0) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ0_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ0_Pos) /**< (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ0(value) (XDMAC_GSWR_SWREQ0_Msk & ((value) << XDMAC_GSWR_SWREQ0_Pos)) +#define XDMAC_GSWR_SWREQ1_Pos _U_(1) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ1_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ1_Pos) /**< (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ1(value) (XDMAC_GSWR_SWREQ1_Msk & ((value) << XDMAC_GSWR_SWREQ1_Pos)) +#define XDMAC_GSWR_SWREQ2_Pos _U_(2) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ2_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ2_Pos) /**< (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ2(value) (XDMAC_GSWR_SWREQ2_Msk & ((value) << XDMAC_GSWR_SWREQ2_Pos)) +#define XDMAC_GSWR_SWREQ3_Pos _U_(3) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ3_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ3_Pos) /**< (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ3(value) (XDMAC_GSWR_SWREQ3_Msk & ((value) << XDMAC_GSWR_SWREQ3_Pos)) +#define XDMAC_GSWR_SWREQ4_Pos _U_(4) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ4_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ4_Pos) /**< (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ4(value) (XDMAC_GSWR_SWREQ4_Msk & ((value) << XDMAC_GSWR_SWREQ4_Pos)) +#define XDMAC_GSWR_SWREQ5_Pos _U_(5) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ5_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ5_Pos) /**< (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ5(value) (XDMAC_GSWR_SWREQ5_Msk & ((value) << XDMAC_GSWR_SWREQ5_Pos)) +#define XDMAC_GSWR_SWREQ6_Pos _U_(6) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ6_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ6_Pos) /**< (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ6(value) (XDMAC_GSWR_SWREQ6_Msk & ((value) << XDMAC_GSWR_SWREQ6_Pos)) +#define XDMAC_GSWR_SWREQ7_Pos _U_(7) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ7_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ7_Pos) /**< (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ7(value) (XDMAC_GSWR_SWREQ7_Msk & ((value) << XDMAC_GSWR_SWREQ7_Pos)) +#define XDMAC_GSWR_SWREQ8_Pos _U_(8) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ8_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ8_Pos) /**< (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ8(value) (XDMAC_GSWR_SWREQ8_Msk & ((value) << XDMAC_GSWR_SWREQ8_Pos)) +#define XDMAC_GSWR_SWREQ9_Pos _U_(9) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ9_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ9_Pos) /**< (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ9(value) (XDMAC_GSWR_SWREQ9_Msk & ((value) << XDMAC_GSWR_SWREQ9_Pos)) +#define XDMAC_GSWR_SWREQ10_Pos _U_(10) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ10_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ10_Pos) /**< (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ10(value) (XDMAC_GSWR_SWREQ10_Msk & ((value) << XDMAC_GSWR_SWREQ10_Pos)) +#define XDMAC_GSWR_SWREQ11_Pos _U_(11) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ11_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ11_Pos) /**< (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ11(value) (XDMAC_GSWR_SWREQ11_Msk & ((value) << XDMAC_GSWR_SWREQ11_Pos)) +#define XDMAC_GSWR_SWREQ12_Pos _U_(12) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ12_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ12_Pos) /**< (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ12(value) (XDMAC_GSWR_SWREQ12_Msk & ((value) << XDMAC_GSWR_SWREQ12_Pos)) +#define XDMAC_GSWR_SWREQ13_Pos _U_(13) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ13_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ13_Pos) /**< (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ13(value) (XDMAC_GSWR_SWREQ13_Msk & ((value) << XDMAC_GSWR_SWREQ13_Pos)) +#define XDMAC_GSWR_SWREQ14_Pos _U_(14) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ14_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ14_Pos) /**< (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ14(value) (XDMAC_GSWR_SWREQ14_Msk & ((value) << XDMAC_GSWR_SWREQ14_Pos)) +#define XDMAC_GSWR_SWREQ15_Pos _U_(15) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ15_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ15_Pos) /**< (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ15(value) (XDMAC_GSWR_SWREQ15_Msk & ((value) << XDMAC_GSWR_SWREQ15_Pos)) +#define XDMAC_GSWR_SWREQ16_Pos _U_(16) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ16_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ16_Pos) /**< (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ16(value) (XDMAC_GSWR_SWREQ16_Msk & ((value) << XDMAC_GSWR_SWREQ16_Pos)) +#define XDMAC_GSWR_SWREQ17_Pos _U_(17) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ17_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ17_Pos) /**< (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ17(value) (XDMAC_GSWR_SWREQ17_Msk & ((value) << XDMAC_GSWR_SWREQ17_Pos)) +#define XDMAC_GSWR_SWREQ18_Pos _U_(18) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ18_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ18_Pos) /**< (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ18(value) (XDMAC_GSWR_SWREQ18_Msk & ((value) << XDMAC_GSWR_SWREQ18_Pos)) +#define XDMAC_GSWR_SWREQ19_Pos _U_(19) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ19_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ19_Pos) /**< (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ19(value) (XDMAC_GSWR_SWREQ19_Msk & ((value) << XDMAC_GSWR_SWREQ19_Pos)) +#define XDMAC_GSWR_SWREQ20_Pos _U_(20) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ20_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ20_Pos) /**< (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ20(value) (XDMAC_GSWR_SWREQ20_Msk & ((value) << XDMAC_GSWR_SWREQ20_Pos)) +#define XDMAC_GSWR_SWREQ21_Pos _U_(21) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ21_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ21_Pos) /**< (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ21(value) (XDMAC_GSWR_SWREQ21_Msk & ((value) << XDMAC_GSWR_SWREQ21_Pos)) +#define XDMAC_GSWR_SWREQ22_Pos _U_(22) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ22_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ22_Pos) /**< (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ22(value) (XDMAC_GSWR_SWREQ22_Msk & ((value) << XDMAC_GSWR_SWREQ22_Pos)) +#define XDMAC_GSWR_SWREQ23_Pos _U_(23) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Position */ +#define XDMAC_GSWR_SWREQ23_Msk (_U_(0x1) << XDMAC_GSWR_SWREQ23_Pos) /**< (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit Mask */ +#define XDMAC_GSWR_SWREQ23(value) (XDMAC_GSWR_SWREQ23_Msk & ((value) << XDMAC_GSWR_SWREQ23_Pos)) +#define XDMAC_GSWR_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWR) Register Mask */ + +#define XDMAC_GSWR_SWREQ_Pos _U_(0) /**< (XDMAC_GSWR Position) XDMAC Channel 23 Software Request Bit */ +#define XDMAC_GSWR_SWREQ_Msk (_U_(0xFFFFFF) << XDMAC_GSWR_SWREQ_Pos) /**< (XDMAC_GSWR Mask) SWREQ */ +#define XDMAC_GSWR_SWREQ(value) (XDMAC_GSWR_SWREQ_Msk & ((value) << XDMAC_GSWR_SWREQ_Pos)) + +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) ( R/ 32) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0_Pos _U_(0) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS0_Msk (_U_(0x1) << XDMAC_GSWS_SWRS0_Pos) /**< (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS0(value) (XDMAC_GSWS_SWRS0_Msk & ((value) << XDMAC_GSWS_SWRS0_Pos)) +#define XDMAC_GSWS_SWRS1_Pos _U_(1) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS1_Msk (_U_(0x1) << XDMAC_GSWS_SWRS1_Pos) /**< (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS1(value) (XDMAC_GSWS_SWRS1_Msk & ((value) << XDMAC_GSWS_SWRS1_Pos)) +#define XDMAC_GSWS_SWRS2_Pos _U_(2) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS2_Msk (_U_(0x1) << XDMAC_GSWS_SWRS2_Pos) /**< (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS2(value) (XDMAC_GSWS_SWRS2_Msk & ((value) << XDMAC_GSWS_SWRS2_Pos)) +#define XDMAC_GSWS_SWRS3_Pos _U_(3) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS3_Msk (_U_(0x1) << XDMAC_GSWS_SWRS3_Pos) /**< (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS3(value) (XDMAC_GSWS_SWRS3_Msk & ((value) << XDMAC_GSWS_SWRS3_Pos)) +#define XDMAC_GSWS_SWRS4_Pos _U_(4) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS4_Msk (_U_(0x1) << XDMAC_GSWS_SWRS4_Pos) /**< (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS4(value) (XDMAC_GSWS_SWRS4_Msk & ((value) << XDMAC_GSWS_SWRS4_Pos)) +#define XDMAC_GSWS_SWRS5_Pos _U_(5) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS5_Msk (_U_(0x1) << XDMAC_GSWS_SWRS5_Pos) /**< (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS5(value) (XDMAC_GSWS_SWRS5_Msk & ((value) << XDMAC_GSWS_SWRS5_Pos)) +#define XDMAC_GSWS_SWRS6_Pos _U_(6) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS6_Msk (_U_(0x1) << XDMAC_GSWS_SWRS6_Pos) /**< (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS6(value) (XDMAC_GSWS_SWRS6_Msk & ((value) << XDMAC_GSWS_SWRS6_Pos)) +#define XDMAC_GSWS_SWRS7_Pos _U_(7) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS7_Msk (_U_(0x1) << XDMAC_GSWS_SWRS7_Pos) /**< (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS7(value) (XDMAC_GSWS_SWRS7_Msk & ((value) << XDMAC_GSWS_SWRS7_Pos)) +#define XDMAC_GSWS_SWRS8_Pos _U_(8) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS8_Msk (_U_(0x1) << XDMAC_GSWS_SWRS8_Pos) /**< (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS8(value) (XDMAC_GSWS_SWRS8_Msk & ((value) << XDMAC_GSWS_SWRS8_Pos)) +#define XDMAC_GSWS_SWRS9_Pos _U_(9) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS9_Msk (_U_(0x1) << XDMAC_GSWS_SWRS9_Pos) /**< (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS9(value) (XDMAC_GSWS_SWRS9_Msk & ((value) << XDMAC_GSWS_SWRS9_Pos)) +#define XDMAC_GSWS_SWRS10_Pos _U_(10) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS10_Msk (_U_(0x1) << XDMAC_GSWS_SWRS10_Pos) /**< (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS10(value) (XDMAC_GSWS_SWRS10_Msk & ((value) << XDMAC_GSWS_SWRS10_Pos)) +#define XDMAC_GSWS_SWRS11_Pos _U_(11) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS11_Msk (_U_(0x1) << XDMAC_GSWS_SWRS11_Pos) /**< (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS11(value) (XDMAC_GSWS_SWRS11_Msk & ((value) << XDMAC_GSWS_SWRS11_Pos)) +#define XDMAC_GSWS_SWRS12_Pos _U_(12) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS12_Msk (_U_(0x1) << XDMAC_GSWS_SWRS12_Pos) /**< (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS12(value) (XDMAC_GSWS_SWRS12_Msk & ((value) << XDMAC_GSWS_SWRS12_Pos)) +#define XDMAC_GSWS_SWRS13_Pos _U_(13) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS13_Msk (_U_(0x1) << XDMAC_GSWS_SWRS13_Pos) /**< (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS13(value) (XDMAC_GSWS_SWRS13_Msk & ((value) << XDMAC_GSWS_SWRS13_Pos)) +#define XDMAC_GSWS_SWRS14_Pos _U_(14) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS14_Msk (_U_(0x1) << XDMAC_GSWS_SWRS14_Pos) /**< (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS14(value) (XDMAC_GSWS_SWRS14_Msk & ((value) << XDMAC_GSWS_SWRS14_Pos)) +#define XDMAC_GSWS_SWRS15_Pos _U_(15) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS15_Msk (_U_(0x1) << XDMAC_GSWS_SWRS15_Pos) /**< (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS15(value) (XDMAC_GSWS_SWRS15_Msk & ((value) << XDMAC_GSWS_SWRS15_Pos)) +#define XDMAC_GSWS_SWRS16_Pos _U_(16) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS16_Msk (_U_(0x1) << XDMAC_GSWS_SWRS16_Pos) /**< (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS16(value) (XDMAC_GSWS_SWRS16_Msk & ((value) << XDMAC_GSWS_SWRS16_Pos)) +#define XDMAC_GSWS_SWRS17_Pos _U_(17) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS17_Msk (_U_(0x1) << XDMAC_GSWS_SWRS17_Pos) /**< (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS17(value) (XDMAC_GSWS_SWRS17_Msk & ((value) << XDMAC_GSWS_SWRS17_Pos)) +#define XDMAC_GSWS_SWRS18_Pos _U_(18) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS18_Msk (_U_(0x1) << XDMAC_GSWS_SWRS18_Pos) /**< (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS18(value) (XDMAC_GSWS_SWRS18_Msk & ((value) << XDMAC_GSWS_SWRS18_Pos)) +#define XDMAC_GSWS_SWRS19_Pos _U_(19) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS19_Msk (_U_(0x1) << XDMAC_GSWS_SWRS19_Pos) /**< (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS19(value) (XDMAC_GSWS_SWRS19_Msk & ((value) << XDMAC_GSWS_SWRS19_Pos)) +#define XDMAC_GSWS_SWRS20_Pos _U_(20) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS20_Msk (_U_(0x1) << XDMAC_GSWS_SWRS20_Pos) /**< (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS20(value) (XDMAC_GSWS_SWRS20_Msk & ((value) << XDMAC_GSWS_SWRS20_Pos)) +#define XDMAC_GSWS_SWRS21_Pos _U_(21) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS21_Msk (_U_(0x1) << XDMAC_GSWS_SWRS21_Pos) /**< (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS21(value) (XDMAC_GSWS_SWRS21_Msk & ((value) << XDMAC_GSWS_SWRS21_Pos)) +#define XDMAC_GSWS_SWRS22_Pos _U_(22) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS22_Msk (_U_(0x1) << XDMAC_GSWS_SWRS22_Pos) /**< (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS22(value) (XDMAC_GSWS_SWRS22_Msk & ((value) << XDMAC_GSWS_SWRS22_Pos)) +#define XDMAC_GSWS_SWRS23_Pos _U_(23) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Position */ +#define XDMAC_GSWS_SWRS23_Msk (_U_(0x1) << XDMAC_GSWS_SWRS23_Pos) /**< (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit Mask */ +#define XDMAC_GSWS_SWRS23(value) (XDMAC_GSWS_SWRS23_Msk & ((value) << XDMAC_GSWS_SWRS23_Pos)) +#define XDMAC_GSWS_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWS) Register Mask */ + +#define XDMAC_GSWS_SWRS_Pos _U_(0) /**< (XDMAC_GSWS Position) XDMAC Channel 23 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS_Msk (_U_(0xFFFFFF) << XDMAC_GSWS_SWRS_Pos) /**< (XDMAC_GSWS Mask) SWRS */ +#define XDMAC_GSWS_SWRS(value) (XDMAC_GSWS_SWRS_Msk & ((value) << XDMAC_GSWS_SWRS_Pos)) + +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) ( /W 32) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0_Pos _U_(0) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF0_Msk (_U_(0x1) << XDMAC_GSWF_SWF0_Pos) /**< (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF0(value) (XDMAC_GSWF_SWF0_Msk & ((value) << XDMAC_GSWF_SWF0_Pos)) +#define XDMAC_GSWF_SWF1_Pos _U_(1) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF1_Msk (_U_(0x1) << XDMAC_GSWF_SWF1_Pos) /**< (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF1(value) (XDMAC_GSWF_SWF1_Msk & ((value) << XDMAC_GSWF_SWF1_Pos)) +#define XDMAC_GSWF_SWF2_Pos _U_(2) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF2_Msk (_U_(0x1) << XDMAC_GSWF_SWF2_Pos) /**< (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF2(value) (XDMAC_GSWF_SWF2_Msk & ((value) << XDMAC_GSWF_SWF2_Pos)) +#define XDMAC_GSWF_SWF3_Pos _U_(3) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF3_Msk (_U_(0x1) << XDMAC_GSWF_SWF3_Pos) /**< (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF3(value) (XDMAC_GSWF_SWF3_Msk & ((value) << XDMAC_GSWF_SWF3_Pos)) +#define XDMAC_GSWF_SWF4_Pos _U_(4) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF4_Msk (_U_(0x1) << XDMAC_GSWF_SWF4_Pos) /**< (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF4(value) (XDMAC_GSWF_SWF4_Msk & ((value) << XDMAC_GSWF_SWF4_Pos)) +#define XDMAC_GSWF_SWF5_Pos _U_(5) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF5_Msk (_U_(0x1) << XDMAC_GSWF_SWF5_Pos) /**< (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF5(value) (XDMAC_GSWF_SWF5_Msk & ((value) << XDMAC_GSWF_SWF5_Pos)) +#define XDMAC_GSWF_SWF6_Pos _U_(6) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF6_Msk (_U_(0x1) << XDMAC_GSWF_SWF6_Pos) /**< (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF6(value) (XDMAC_GSWF_SWF6_Msk & ((value) << XDMAC_GSWF_SWF6_Pos)) +#define XDMAC_GSWF_SWF7_Pos _U_(7) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF7_Msk (_U_(0x1) << XDMAC_GSWF_SWF7_Pos) /**< (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF7(value) (XDMAC_GSWF_SWF7_Msk & ((value) << XDMAC_GSWF_SWF7_Pos)) +#define XDMAC_GSWF_SWF8_Pos _U_(8) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF8_Msk (_U_(0x1) << XDMAC_GSWF_SWF8_Pos) /**< (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF8(value) (XDMAC_GSWF_SWF8_Msk & ((value) << XDMAC_GSWF_SWF8_Pos)) +#define XDMAC_GSWF_SWF9_Pos _U_(9) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF9_Msk (_U_(0x1) << XDMAC_GSWF_SWF9_Pos) /**< (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF9(value) (XDMAC_GSWF_SWF9_Msk & ((value) << XDMAC_GSWF_SWF9_Pos)) +#define XDMAC_GSWF_SWF10_Pos _U_(10) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF10_Msk (_U_(0x1) << XDMAC_GSWF_SWF10_Pos) /**< (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF10(value) (XDMAC_GSWF_SWF10_Msk & ((value) << XDMAC_GSWF_SWF10_Pos)) +#define XDMAC_GSWF_SWF11_Pos _U_(11) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF11_Msk (_U_(0x1) << XDMAC_GSWF_SWF11_Pos) /**< (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF11(value) (XDMAC_GSWF_SWF11_Msk & ((value) << XDMAC_GSWF_SWF11_Pos)) +#define XDMAC_GSWF_SWF12_Pos _U_(12) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF12_Msk (_U_(0x1) << XDMAC_GSWF_SWF12_Pos) /**< (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF12(value) (XDMAC_GSWF_SWF12_Msk & ((value) << XDMAC_GSWF_SWF12_Pos)) +#define XDMAC_GSWF_SWF13_Pos _U_(13) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF13_Msk (_U_(0x1) << XDMAC_GSWF_SWF13_Pos) /**< (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF13(value) (XDMAC_GSWF_SWF13_Msk & ((value) << XDMAC_GSWF_SWF13_Pos)) +#define XDMAC_GSWF_SWF14_Pos _U_(14) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF14_Msk (_U_(0x1) << XDMAC_GSWF_SWF14_Pos) /**< (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF14(value) (XDMAC_GSWF_SWF14_Msk & ((value) << XDMAC_GSWF_SWF14_Pos)) +#define XDMAC_GSWF_SWF15_Pos _U_(15) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF15_Msk (_U_(0x1) << XDMAC_GSWF_SWF15_Pos) /**< (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF15(value) (XDMAC_GSWF_SWF15_Msk & ((value) << XDMAC_GSWF_SWF15_Pos)) +#define XDMAC_GSWF_SWF16_Pos _U_(16) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF16_Msk (_U_(0x1) << XDMAC_GSWF_SWF16_Pos) /**< (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF16(value) (XDMAC_GSWF_SWF16_Msk & ((value) << XDMAC_GSWF_SWF16_Pos)) +#define XDMAC_GSWF_SWF17_Pos _U_(17) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF17_Msk (_U_(0x1) << XDMAC_GSWF_SWF17_Pos) /**< (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF17(value) (XDMAC_GSWF_SWF17_Msk & ((value) << XDMAC_GSWF_SWF17_Pos)) +#define XDMAC_GSWF_SWF18_Pos _U_(18) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF18_Msk (_U_(0x1) << XDMAC_GSWF_SWF18_Pos) /**< (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF18(value) (XDMAC_GSWF_SWF18_Msk & ((value) << XDMAC_GSWF_SWF18_Pos)) +#define XDMAC_GSWF_SWF19_Pos _U_(19) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF19_Msk (_U_(0x1) << XDMAC_GSWF_SWF19_Pos) /**< (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF19(value) (XDMAC_GSWF_SWF19_Msk & ((value) << XDMAC_GSWF_SWF19_Pos)) +#define XDMAC_GSWF_SWF20_Pos _U_(20) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF20_Msk (_U_(0x1) << XDMAC_GSWF_SWF20_Pos) /**< (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF20(value) (XDMAC_GSWF_SWF20_Msk & ((value) << XDMAC_GSWF_SWF20_Pos)) +#define XDMAC_GSWF_SWF21_Pos _U_(21) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF21_Msk (_U_(0x1) << XDMAC_GSWF_SWF21_Pos) /**< (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF21(value) (XDMAC_GSWF_SWF21_Msk & ((value) << XDMAC_GSWF_SWF21_Pos)) +#define XDMAC_GSWF_SWF22_Pos _U_(22) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF22_Msk (_U_(0x1) << XDMAC_GSWF_SWF22_Pos) /**< (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF22(value) (XDMAC_GSWF_SWF22_Msk & ((value) << XDMAC_GSWF_SWF22_Pos)) +#define XDMAC_GSWF_SWF23_Pos _U_(23) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Position */ +#define XDMAC_GSWF_SWF23_Msk (_U_(0x1) << XDMAC_GSWF_SWF23_Pos) /**< (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit Mask */ +#define XDMAC_GSWF_SWF23(value) (XDMAC_GSWF_SWF23_Msk & ((value) << XDMAC_GSWF_SWF23_Pos)) +#define XDMAC_GSWF_Msk _U_(0x00FFFFFF) /**< (XDMAC_GSWF) Register Mask */ + +#define XDMAC_GSWF_SWF_Pos _U_(0) /**< (XDMAC_GSWF Position) XDMAC Channel 23 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF_Msk (_U_(0xFFFFFF) << XDMAC_GSWF_SWF_Pos) /**< (XDMAC_GSWF Mask) SWF */ +#define XDMAC_GSWF_SWF(value) (XDMAC_GSWF_SWF_Msk & ((value) << XDMAC_GSWF_SWF_Pos)) + +/** \brief XDMAC register offsets definitions */ +#define XDMAC_CIE_REG_OFST (0x00) /**< (XDMAC_CIE) Channel Interrupt Enable Register Offset */ +#define XDMAC_CID_REG_OFST (0x04) /**< (XDMAC_CID) Channel Interrupt Disable Register Offset */ +#define XDMAC_CIM_REG_OFST (0x08) /**< (XDMAC_CIM) Channel Interrupt Mask Register Offset */ +#define XDMAC_CIS_REG_OFST (0x0C) /**< (XDMAC_CIS) Channel Interrupt Status Register Offset */ +#define XDMAC_CSA_REG_OFST (0x10) /**< (XDMAC_CSA) Channel Source Address Register Offset */ +#define XDMAC_CDA_REG_OFST (0x14) /**< (XDMAC_CDA) Channel Destination Address Register Offset */ +#define XDMAC_CNDA_REG_OFST (0x18) /**< (XDMAC_CNDA) Channel Next Descriptor Address Register Offset */ +#define XDMAC_CNDC_REG_OFST (0x1C) /**< (XDMAC_CNDC) Channel Next Descriptor Control Register Offset */ +#define XDMAC_CUBC_REG_OFST (0x20) /**< (XDMAC_CUBC) Channel Microblock Control Register Offset */ +#define XDMAC_CBC_REG_OFST (0x24) /**< (XDMAC_CBC) Channel Block Control Register Offset */ +#define XDMAC_CC_REG_OFST (0x28) /**< (XDMAC_CC) Channel Configuration Register Offset */ +#define XDMAC_CDS_MSP_REG_OFST (0x2C) /**< (XDMAC_CDS_MSP) Channel Data Stride Memory Set Pattern Offset */ +#define XDMAC_CSUS_REG_OFST (0x30) /**< (XDMAC_CSUS) Channel Source Microblock Stride Offset */ +#define XDMAC_CDUS_REG_OFST (0x34) /**< (XDMAC_CDUS) Channel Destination Microblock Stride Offset */ +#define XDMAC_GTYPE_REG_OFST (0x00) /**< (XDMAC_GTYPE) Global Type Register Offset */ +#define XDMAC_GCFG_REG_OFST (0x04) /**< (XDMAC_GCFG) Global Configuration Register Offset */ +#define XDMAC_GWAC_REG_OFST (0x08) /**< (XDMAC_GWAC) Global Weighted Arbiter Configuration Register Offset */ +#define XDMAC_GIE_REG_OFST (0x0C) /**< (XDMAC_GIE) Global Interrupt Enable Register Offset */ +#define XDMAC_GID_REG_OFST (0x10) /**< (XDMAC_GID) Global Interrupt Disable Register Offset */ +#define XDMAC_GIM_REG_OFST (0x14) /**< (XDMAC_GIM) Global Interrupt Mask Register Offset */ +#define XDMAC_GIS_REG_OFST (0x18) /**< (XDMAC_GIS) Global Interrupt Status Register Offset */ +#define XDMAC_GE_REG_OFST (0x1C) /**< (XDMAC_GE) Global Channel Enable Register Offset */ +#define XDMAC_GD_REG_OFST (0x20) /**< (XDMAC_GD) Global Channel Disable Register Offset */ +#define XDMAC_GS_REG_OFST (0x24) /**< (XDMAC_GS) Global Channel Status Register Offset */ +#define XDMAC_GRS_REG_OFST (0x28) /**< (XDMAC_GRS) Global Channel Read Suspend Register Offset */ +#define XDMAC_GWS_REG_OFST (0x2C) /**< (XDMAC_GWS) Global Channel Write Suspend Register Offset */ +#define XDMAC_GRWS_REG_OFST (0x30) /**< (XDMAC_GRWS) Global Channel Read Write Suspend Register Offset */ +#define XDMAC_GRWR_REG_OFST (0x34) /**< (XDMAC_GRWR) Global Channel Read Write Resume Register Offset */ +#define XDMAC_GSWR_REG_OFST (0x38) /**< (XDMAC_GSWR) Global Channel Software Request Register Offset */ +#define XDMAC_GSWS_REG_OFST (0x3C) /**< (XDMAC_GSWS) Global Channel Software Request Status Register Offset */ +#define XDMAC_GSWF_REG_OFST (0x40) /**< (XDMAC_GSWF) Global Channel Software Flush Request Register Offset */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XDMAC_CHID register API structure */ +typedef struct +{ + __O uint32_t XDMAC_CIE; /**< Offset: 0x00 ( /W 32) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< Offset: 0x04 ( /W 32) Channel Interrupt Disable Register */ + __I uint32_t XDMAC_CIM; /**< Offset: 0x08 (R/ 32) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< Offset: 0x0C (R/ 32) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< Offset: 0x10 (R/W 32) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< Offset: 0x14 (R/W 32) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< Offset: 0x18 (R/W 32) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< Offset: 0x1C (R/W 32) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< Offset: 0x20 (R/W 32) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< Offset: 0x24 (R/W 32) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< Offset: 0x28 (R/W 32) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< Offset: 0x2C (R/W 32) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< Offset: 0x30 (R/W 32) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< Offset: 0x34 (R/W 32) Channel Destination Microblock Stride */ + __I uint8_t Reserved1[0x08]; +} xdmac_chid_registers_t; + +#define XDMAC_CHID_NUMBER _U_(24) + +/** \brief XDMAC register API structure */ +typedef struct +{ + __I uint32_t XDMAC_GTYPE; /**< Offset: 0x00 (R/ 32) Global Type Register */ + __IO uint32_t XDMAC_GCFG; /**< Offset: 0x04 (R/W 32) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< Offset: 0x08 (R/W 32) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< Offset: 0x0C ( /W 32) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< Offset: 0x10 ( /W 32) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< Offset: 0x14 (R/ 32) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< Offset: 0x18 (R/ 32) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< Offset: 0x1C ( /W 32) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< Offset: 0x20 ( /W 32) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< Offset: 0x24 (R/ 32) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< Offset: 0x28 (R/W 32) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< Offset: 0x2C (R/W 32) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< Offset: 0x30 ( /W 32) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< Offset: 0x34 ( /W 32) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< Offset: 0x38 ( /W 32) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< Offset: 0x3C (R/ 32) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< Offset: 0x40 ( /W 32) Global Channel Software Flush Request Register */ + __I uint8_t Reserved1[0x0C]; + xdmac_chid_registers_t XDMAC_CHID[XDMAC_CHID_NUMBER]; /**< Offset: 0x50 Channel Interrupt Enable Register */ +} xdmac_registers_t; + + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* _SAME70_XDMAC_COMPONENT_H_ */ diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j19b.h new file mode 100644 index 00000000..22b66952 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j19b.h @@ -0,0 +1,809 @@ +/** + * \brief Peripheral I/O description for SAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:02:47Z */ +#ifndef _SAME70J19B_GPIO_H_ +#define _SAME70J19B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70J19B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j20b.h new file mode 100644 index 00000000..8253b362 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j20b.h @@ -0,0 +1,809 @@ +/** + * \brief Peripheral I/O description for SAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:01Z */ +#ifndef _SAME70J20B_GPIO_H_ +#define _SAME70J20B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70J20B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j21b.h new file mode 100644 index 00000000..42c72bed --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70j21b.h @@ -0,0 +1,809 @@ +/** + * \brief Peripheral I/O description for SAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:14Z */ +#ifndef _SAME70J21B_GPIO_H_ +#define _SAME70J21B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70J21B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n19b.h new file mode 100644 index 00000000..4376ca89 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n19b.h @@ -0,0 +1,931 @@ +/** + * \brief Peripheral I/O description for SAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:20Z */ +#ifndef _SAME70N19B_GPIO_H_ +#define _SAME70N19B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70N19B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n20b.h new file mode 100644 index 00000000..3e7ab3ee --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n20b.h @@ -0,0 +1,931 @@ +/** + * \brief Peripheral I/O description for SAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:26Z */ +#ifndef _SAME70N20B_GPIO_H_ +#define _SAME70N20B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70N20B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n21b.h new file mode 100644 index 00000000..8d3ee07c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70n21b.h @@ -0,0 +1,931 @@ +/** + * \brief Peripheral I/O description for SAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:32Z */ +#ifndef _SAME70N21B_GPIO_H_ +#define _SAME70N21B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PD28B_MCAN1_CANRX1 _L_(124) /**< MCAN1 signal: MCAN1_CANRX1 on PD28 mux B */ +#define MUX_PD28B_MCAN1_CANRX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PD28B_MCAN1_CANRX1 (_U_(1) << 28) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70N21B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q19b.h new file mode 100644 index 00000000..2a5bb63f --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q19b.h @@ -0,0 +1,1437 @@ +/** + * \brief Peripheral I/O description for SAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:35Z */ +#ifndef _SAME70Q19B_GPIO_H_ +#define _SAME70Q19B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: EBI_DQM0 on PC18 mux A */ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: EBI_DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_U_(1) << 18) /**< EBI signal: EBI_DQM0 */ +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: EBI_DQM1 on PD15 mux C */ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: EBI_DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_U_(1) << 15) /**< EBI signal: EBI_DQM1 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: EBI_SDA0 on PC20 mux A */ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: EBI_SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_U_(1) << 20) /**< EBI signal: EBI_SDA0 */ +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: EBI_SDA1 on PC21 mux A */ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: EBI_SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_U_(1) << 21) /**< EBI signal: EBI_SDA1 */ +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: EBI_SDA11 on PC31 mux A */ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: EBI_SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_U_(1) << 31) /**< EBI signal: EBI_SDA11 */ +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: EBI_SDA12 on PA18 mux C */ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: EBI_SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_U_(1) << 18) /**< EBI signal: EBI_SDA12 */ +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: EBI_SDA2 on PC22 mux A */ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: EBI_SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_U_(1) << 22) /**< EBI signal: EBI_SDA2 */ +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: EBI_SDA3 on PC23 mux A */ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: EBI_SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_U_(1) << 23) /**< EBI signal: EBI_SDA3 */ +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: EBI_SDA4 on PC24 mux A */ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: EBI_SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_U_(1) << 24) /**< EBI signal: EBI_SDA4 */ +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: EBI_SDA5 on PC25 mux A */ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: EBI_SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_U_(1) << 25) /**< EBI signal: EBI_SDA5 */ +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: EBI_SDA6 on PC26 mux A */ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: EBI_SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_U_(1) << 26) /**< EBI signal: EBI_SDA6 */ +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: EBI_SDA7 on PC27 mux A */ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: EBI_SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_U_(1) << 27) /**< EBI signal: EBI_SDA7 */ +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: EBI_SDA8 on PC28 mux A */ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: EBI_SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_U_(1) << 28) /**< EBI signal: EBI_SDA8 */ +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: EBI_SDA9 on PC29 mux A */ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: EBI_SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_U_(1) << 29) /**< EBI signal: EBI_SDA9 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: I2SC1_CK on PA20 mux D */ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: I2SC1_CK */ +#define PIO_PA20D_I2SC1_CK (_U_(1) << 20) /**< I2SC1 signal: I2SC1_CK */ +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: I2SC1_DI0 on PE2 mux C */ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_U_(1) << 2) /**< I2SC1 signal: I2SC1_DI0 */ +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: I2SC1_DO0 on PE1 mux C */ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_U_(1) << 1) /**< I2SC1 signal: I2SC1_DO0 */ +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: I2SC1_MCK on PA19 mux D */ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: I2SC1_MCK */ +#define PIO_PA19D_I2SC1_MCK (_U_(1) << 19) /**< I2SC1 signal: I2SC1_MCK */ +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: I2SC1_WS on PE0 mux C */ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: I2SC1_WS */ +#define PIO_PE0C_I2SC1_WS (_U_(1) << 0) /**< I2SC1 signal: I2SC1_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70Q19B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q20b.h new file mode 100644 index 00000000..2072c46b --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q20b.h @@ -0,0 +1,1437 @@ +/** + * \brief Peripheral I/O description for SAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:39Z */ +#ifndef _SAME70Q20B_GPIO_H_ +#define _SAME70Q20B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: EBI_DQM0 on PC18 mux A */ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: EBI_DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_U_(1) << 18) /**< EBI signal: EBI_DQM0 */ +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: EBI_DQM1 on PD15 mux C */ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: EBI_DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_U_(1) << 15) /**< EBI signal: EBI_DQM1 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: EBI_SDA0 on PC20 mux A */ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: EBI_SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_U_(1) << 20) /**< EBI signal: EBI_SDA0 */ +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: EBI_SDA1 on PC21 mux A */ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: EBI_SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_U_(1) << 21) /**< EBI signal: EBI_SDA1 */ +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: EBI_SDA11 on PC31 mux A */ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: EBI_SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_U_(1) << 31) /**< EBI signal: EBI_SDA11 */ +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: EBI_SDA12 on PA18 mux C */ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: EBI_SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_U_(1) << 18) /**< EBI signal: EBI_SDA12 */ +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: EBI_SDA2 on PC22 mux A */ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: EBI_SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_U_(1) << 22) /**< EBI signal: EBI_SDA2 */ +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: EBI_SDA3 on PC23 mux A */ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: EBI_SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_U_(1) << 23) /**< EBI signal: EBI_SDA3 */ +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: EBI_SDA4 on PC24 mux A */ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: EBI_SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_U_(1) << 24) /**< EBI signal: EBI_SDA4 */ +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: EBI_SDA5 on PC25 mux A */ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: EBI_SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_U_(1) << 25) /**< EBI signal: EBI_SDA5 */ +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: EBI_SDA6 on PC26 mux A */ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: EBI_SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_U_(1) << 26) /**< EBI signal: EBI_SDA6 */ +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: EBI_SDA7 on PC27 mux A */ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: EBI_SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_U_(1) << 27) /**< EBI signal: EBI_SDA7 */ +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: EBI_SDA8 on PC28 mux A */ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: EBI_SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_U_(1) << 28) /**< EBI signal: EBI_SDA8 */ +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: EBI_SDA9 on PC29 mux A */ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: EBI_SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_U_(1) << 29) /**< EBI signal: EBI_SDA9 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: I2SC1_CK on PA20 mux D */ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: I2SC1_CK */ +#define PIO_PA20D_I2SC1_CK (_U_(1) << 20) /**< I2SC1 signal: I2SC1_CK */ +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: I2SC1_DI0 on PE2 mux C */ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_U_(1) << 2) /**< I2SC1 signal: I2SC1_DI0 */ +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: I2SC1_DO0 on PE1 mux C */ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_U_(1) << 1) /**< I2SC1 signal: I2SC1_DO0 */ +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: I2SC1_MCK on PA19 mux D */ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: I2SC1_MCK */ +#define PIO_PA19D_I2SC1_MCK (_U_(1) << 19) /**< I2SC1 signal: I2SC1_MCK */ +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: I2SC1_WS on PE0 mux C */ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: I2SC1_WS */ +#define PIO_PE0C_I2SC1_WS (_U_(1) << 0) /**< I2SC1 signal: I2SC1_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70Q20B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q21b.h new file mode 100644 index 00000000..73a74e71 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/pio/same70q21b.h @@ -0,0 +1,1437 @@ +/** + * \brief Peripheral I/O description for SAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70Q21B_GPIO_H_ +#define _SAME70Q21B_GPIO_H_ + +/* ========== Peripheral I/O pin numbers ========== */ +#define PIN_PA0 ( 0 ) /**< Pin Number for PA0 */ +#define PIN_PA1 ( 1 ) /**< Pin Number for PA1 */ +#define PIN_PA2 ( 2 ) /**< Pin Number for PA2 */ +#define PIN_PA3 ( 3 ) /**< Pin Number for PA3 */ +#define PIN_PA4 ( 4 ) /**< Pin Number for PA4 */ +#define PIN_PA5 ( 5 ) /**< Pin Number for PA5 */ +#define PIN_PA6 ( 6 ) /**< Pin Number for PA6 */ +#define PIN_PA7 ( 7 ) /**< Pin Number for PA7 */ +#define PIN_PA8 ( 8 ) /**< Pin Number for PA8 */ +#define PIN_PA9 ( 9 ) /**< Pin Number for PA9 */ +#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ +#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ +#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ +#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ +#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ +#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ +#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ +#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ +#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ +#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ +#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ +#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ +#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ +#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ +#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ +#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ +#define PIN_PA26 ( 26 ) /**< Pin Number for PA26 */ +#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ +#define PIN_PA28 ( 28 ) /**< Pin Number for PA28 */ +#define PIN_PA29 ( 29 ) /**< Pin Number for PA29 */ +#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ +#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ +#define PIN_PB0 ( 32 ) /**< Pin Number for PB0 */ +#define PIN_PB1 ( 33 ) /**< Pin Number for PB1 */ +#define PIN_PB2 ( 34 ) /**< Pin Number for PB2 */ +#define PIN_PB3 ( 35 ) /**< Pin Number for PB3 */ +#define PIN_PB4 ( 36 ) /**< Pin Number for PB4 */ +#define PIN_PB5 ( 37 ) /**< Pin Number for PB5 */ +#define PIN_PB6 ( 38 ) /**< Pin Number for PB6 */ +#define PIN_PB7 ( 39 ) /**< Pin Number for PB7 */ +#define PIN_PB8 ( 40 ) /**< Pin Number for PB8 */ +#define PIN_PB9 ( 41 ) /**< Pin Number for PB9 */ +#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ +#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ +#define PIN_PC0 ( 64 ) /**< Pin Number for PC0 */ +#define PIN_PC1 ( 65 ) /**< Pin Number for PC1 */ +#define PIN_PC2 ( 66 ) /**< Pin Number for PC2 */ +#define PIN_PC3 ( 67 ) /**< Pin Number for PC3 */ +#define PIN_PC4 ( 68 ) /**< Pin Number for PC4 */ +#define PIN_PC5 ( 69 ) /**< Pin Number for PC5 */ +#define PIN_PC6 ( 70 ) /**< Pin Number for PC6 */ +#define PIN_PC7 ( 71 ) /**< Pin Number for PC7 */ +#define PIN_PC8 ( 72 ) /**< Pin Number for PC8 */ +#define PIN_PC9 ( 73 ) /**< Pin Number for PC9 */ +#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ +#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ +#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ +#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ +#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ +#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ +#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ +#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ +#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ +#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ +#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ +#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ +#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ +#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ +#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ +#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ +#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ +#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ +#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ +#define PIN_PC29 ( 93 ) /**< Pin Number for PC29 */ +#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ +#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ +#define PIN_PD0 ( 96 ) /**< Pin Number for PD0 */ +#define PIN_PD1 ( 97 ) /**< Pin Number for PD1 */ +#define PIN_PD2 ( 98 ) /**< Pin Number for PD2 */ +#define PIN_PD3 ( 99 ) /**< Pin Number for PD3 */ +#define PIN_PD4 (100 ) /**< Pin Number for PD4 */ +#define PIN_PD5 (101 ) /**< Pin Number for PD5 */ +#define PIN_PD6 (102 ) /**< Pin Number for PD6 */ +#define PIN_PD7 (103 ) /**< Pin Number for PD7 */ +#define PIN_PD8 (104 ) /**< Pin Number for PD8 */ +#define PIN_PD9 (105 ) /**< Pin Number for PD9 */ +#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ +#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ +#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ +#define PIN_PD13 (109 ) /**< Pin Number for PD13 */ +#define PIN_PD14 (110 ) /**< Pin Number for PD14 */ +#define PIN_PD15 (111 ) /**< Pin Number for PD15 */ +#define PIN_PD16 (112 ) /**< Pin Number for PD16 */ +#define PIN_PD17 (113 ) /**< Pin Number for PD17 */ +#define PIN_PD18 (114 ) /**< Pin Number for PD18 */ +#define PIN_PD19 (115 ) /**< Pin Number for PD19 */ +#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ +#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ +#define PIN_PD22 (118 ) /**< Pin Number for PD22 */ +#define PIN_PD23 (119 ) /**< Pin Number for PD23 */ +#define PIN_PD24 (120 ) /**< Pin Number for PD24 */ +#define PIN_PD25 (121 ) /**< Pin Number for PD25 */ +#define PIN_PD26 (122 ) /**< Pin Number for PD26 */ +#define PIN_PD27 (123 ) /**< Pin Number for PD27 */ +#define PIN_PD28 (124 ) /**< Pin Number for PD28 */ +#define PIN_PD29 (125 ) /**< Pin Number for PD29 */ +#define PIN_PD30 (126 ) /**< Pin Number for PD30 */ +#define PIN_PD31 (127 ) /**< Pin Number for PD31 */ +#define PIN_PE0 (128 ) /**< Pin Number for PE0 */ +#define PIN_PE1 (129 ) /**< Pin Number for PE1 */ +#define PIN_PE2 (130 ) /**< Pin Number for PE2 */ +#define PIN_PE3 (131 ) /**< Pin Number for PE3 */ +#define PIN_PE4 (132 ) /**< Pin Number for PE4 */ +#define PIN_PE5 (133 ) /**< Pin Number for PE5 */ + +/* ========== Peripheral I/O masks ========== */ +#define PIO_PA0 (_U_(1) << 0) /**< PIO mask for PA0 */ +#define PIO_PA1 (_U_(1) << 1) /**< PIO mask for PA1 */ +#define PIO_PA2 (_U_(1) << 2) /**< PIO mask for PA2 */ +#define PIO_PA3 (_U_(1) << 3) /**< PIO mask for PA3 */ +#define PIO_PA4 (_U_(1) << 4) /**< PIO mask for PA4 */ +#define PIO_PA5 (_U_(1) << 5) /**< PIO mask for PA5 */ +#define PIO_PA6 (_U_(1) << 6) /**< PIO mask for PA6 */ +#define PIO_PA7 (_U_(1) << 7) /**< PIO mask for PA7 */ +#define PIO_PA8 (_U_(1) << 8) /**< PIO mask for PA8 */ +#define PIO_PA9 (_U_(1) << 9) /**< PIO mask for PA9 */ +#define PIO_PA10 (_U_(1) << 10) /**< PIO mask for PA10 */ +#define PIO_PA11 (_U_(1) << 11) /**< PIO mask for PA11 */ +#define PIO_PA12 (_U_(1) << 12) /**< PIO mask for PA12 */ +#define PIO_PA13 (_U_(1) << 13) /**< PIO mask for PA13 */ +#define PIO_PA14 (_U_(1) << 14) /**< PIO mask for PA14 */ +#define PIO_PA15 (_U_(1) << 15) /**< PIO mask for PA15 */ +#define PIO_PA16 (_U_(1) << 16) /**< PIO mask for PA16 */ +#define PIO_PA17 (_U_(1) << 17) /**< PIO mask for PA17 */ +#define PIO_PA18 (_U_(1) << 18) /**< PIO mask for PA18 */ +#define PIO_PA19 (_U_(1) << 19) /**< PIO mask for PA19 */ +#define PIO_PA20 (_U_(1) << 20) /**< PIO mask for PA20 */ +#define PIO_PA21 (_U_(1) << 21) /**< PIO mask for PA21 */ +#define PIO_PA22 (_U_(1) << 22) /**< PIO mask for PA22 */ +#define PIO_PA23 (_U_(1) << 23) /**< PIO mask for PA23 */ +#define PIO_PA24 (_U_(1) << 24) /**< PIO mask for PA24 */ +#define PIO_PA25 (_U_(1) << 25) /**< PIO mask for PA25 */ +#define PIO_PA26 (_U_(1) << 26) /**< PIO mask for PA26 */ +#define PIO_PA27 (_U_(1) << 27) /**< PIO mask for PA27 */ +#define PIO_PA28 (_U_(1) << 28) /**< PIO mask for PA28 */ +#define PIO_PA29 (_U_(1) << 29) /**< PIO mask for PA29 */ +#define PIO_PA30 (_U_(1) << 30) /**< PIO mask for PA30 */ +#define PIO_PA31 (_U_(1) << 31) /**< PIO mask for PA31 */ +#define PIO_PB0 (_U_(1) << 0) /**< PIO mask for PB0 */ +#define PIO_PB1 (_U_(1) << 1) /**< PIO mask for PB1 */ +#define PIO_PB2 (_U_(1) << 2) /**< PIO mask for PB2 */ +#define PIO_PB3 (_U_(1) << 3) /**< PIO mask for PB3 */ +#define PIO_PB4 (_U_(1) << 4) /**< PIO mask for PB4 */ +#define PIO_PB5 (_U_(1) << 5) /**< PIO mask for PB5 */ +#define PIO_PB6 (_U_(1) << 6) /**< PIO mask for PB6 */ +#define PIO_PB7 (_U_(1) << 7) /**< PIO mask for PB7 */ +#define PIO_PB8 (_U_(1) << 8) /**< PIO mask for PB8 */ +#define PIO_PB9 (_U_(1) << 9) /**< PIO mask for PB9 */ +#define PIO_PB12 (_U_(1) << 12) /**< PIO mask for PB12 */ +#define PIO_PB13 (_U_(1) << 13) /**< PIO mask for PB13 */ +#define PIO_PC0 (_U_(1) << 0) /**< PIO mask for PC0 */ +#define PIO_PC1 (_U_(1) << 1) /**< PIO mask for PC1 */ +#define PIO_PC2 (_U_(1) << 2) /**< PIO mask for PC2 */ +#define PIO_PC3 (_U_(1) << 3) /**< PIO mask for PC3 */ +#define PIO_PC4 (_U_(1) << 4) /**< PIO mask for PC4 */ +#define PIO_PC5 (_U_(1) << 5) /**< PIO mask for PC5 */ +#define PIO_PC6 (_U_(1) << 6) /**< PIO mask for PC6 */ +#define PIO_PC7 (_U_(1) << 7) /**< PIO mask for PC7 */ +#define PIO_PC8 (_U_(1) << 8) /**< PIO mask for PC8 */ +#define PIO_PC9 (_U_(1) << 9) /**< PIO mask for PC9 */ +#define PIO_PC10 (_U_(1) << 10) /**< PIO mask for PC10 */ +#define PIO_PC11 (_U_(1) << 11) /**< PIO mask for PC11 */ +#define PIO_PC12 (_U_(1) << 12) /**< PIO mask for PC12 */ +#define PIO_PC13 (_U_(1) << 13) /**< PIO mask for PC13 */ +#define PIO_PC14 (_U_(1) << 14) /**< PIO mask for PC14 */ +#define PIO_PC15 (_U_(1) << 15) /**< PIO mask for PC15 */ +#define PIO_PC16 (_U_(1) << 16) /**< PIO mask for PC16 */ +#define PIO_PC17 (_U_(1) << 17) /**< PIO mask for PC17 */ +#define PIO_PC18 (_U_(1) << 18) /**< PIO mask for PC18 */ +#define PIO_PC19 (_U_(1) << 19) /**< PIO mask for PC19 */ +#define PIO_PC20 (_U_(1) << 20) /**< PIO mask for PC20 */ +#define PIO_PC21 (_U_(1) << 21) /**< PIO mask for PC21 */ +#define PIO_PC22 (_U_(1) << 22) /**< PIO mask for PC22 */ +#define PIO_PC23 (_U_(1) << 23) /**< PIO mask for PC23 */ +#define PIO_PC24 (_U_(1) << 24) /**< PIO mask for PC24 */ +#define PIO_PC25 (_U_(1) << 25) /**< PIO mask for PC25 */ +#define PIO_PC26 (_U_(1) << 26) /**< PIO mask for PC26 */ +#define PIO_PC27 (_U_(1) << 27) /**< PIO mask for PC27 */ +#define PIO_PC28 (_U_(1) << 28) /**< PIO mask for PC28 */ +#define PIO_PC29 (_U_(1) << 29) /**< PIO mask for PC29 */ +#define PIO_PC30 (_U_(1) << 30) /**< PIO mask for PC30 */ +#define PIO_PC31 (_U_(1) << 31) /**< PIO mask for PC31 */ +#define PIO_PD0 (_U_(1) << 0) /**< PIO mask for PD0 */ +#define PIO_PD1 (_U_(1) << 1) /**< PIO mask for PD1 */ +#define PIO_PD2 (_U_(1) << 2) /**< PIO mask for PD2 */ +#define PIO_PD3 (_U_(1) << 3) /**< PIO mask for PD3 */ +#define PIO_PD4 (_U_(1) << 4) /**< PIO mask for PD4 */ +#define PIO_PD5 (_U_(1) << 5) /**< PIO mask for PD5 */ +#define PIO_PD6 (_U_(1) << 6) /**< PIO mask for PD6 */ +#define PIO_PD7 (_U_(1) << 7) /**< PIO mask for PD7 */ +#define PIO_PD8 (_U_(1) << 8) /**< PIO mask for PD8 */ +#define PIO_PD9 (_U_(1) << 9) /**< PIO mask for PD9 */ +#define PIO_PD10 (_U_(1) << 10) /**< PIO mask for PD10 */ +#define PIO_PD11 (_U_(1) << 11) /**< PIO mask for PD11 */ +#define PIO_PD12 (_U_(1) << 12) /**< PIO mask for PD12 */ +#define PIO_PD13 (_U_(1) << 13) /**< PIO mask for PD13 */ +#define PIO_PD14 (_U_(1) << 14) /**< PIO mask for PD14 */ +#define PIO_PD15 (_U_(1) << 15) /**< PIO mask for PD15 */ +#define PIO_PD16 (_U_(1) << 16) /**< PIO mask for PD16 */ +#define PIO_PD17 (_U_(1) << 17) /**< PIO mask for PD17 */ +#define PIO_PD18 (_U_(1) << 18) /**< PIO mask for PD18 */ +#define PIO_PD19 (_U_(1) << 19) /**< PIO mask for PD19 */ +#define PIO_PD20 (_U_(1) << 20) /**< PIO mask for PD20 */ +#define PIO_PD21 (_U_(1) << 21) /**< PIO mask for PD21 */ +#define PIO_PD22 (_U_(1) << 22) /**< PIO mask for PD22 */ +#define PIO_PD23 (_U_(1) << 23) /**< PIO mask for PD23 */ +#define PIO_PD24 (_U_(1) << 24) /**< PIO mask for PD24 */ +#define PIO_PD25 (_U_(1) << 25) /**< PIO mask for PD25 */ +#define PIO_PD26 (_U_(1) << 26) /**< PIO mask for PD26 */ +#define PIO_PD27 (_U_(1) << 27) /**< PIO mask for PD27 */ +#define PIO_PD28 (_U_(1) << 28) /**< PIO mask for PD28 */ +#define PIO_PD29 (_U_(1) << 29) /**< PIO mask for PD29 */ +#define PIO_PD30 (_U_(1) << 30) /**< PIO mask for PD30 */ +#define PIO_PD31 (_U_(1) << 31) /**< PIO mask for PD31 */ +#define PIO_PE0 (_U_(1) << 0) /**< PIO mask for PE0 */ +#define PIO_PE1 (_U_(1) << 1) /**< PIO mask for PE1 */ +#define PIO_PE2 (_U_(1) << 2) /**< PIO mask for PE2 */ +#define PIO_PE3 (_U_(1) << 3) /**< PIO mask for PE3 */ +#define PIO_PE4 (_U_(1) << 4) /**< PIO mask for PE4 */ +#define PIO_PE5 (_U_(1) << 5) /**< PIO mask for PE5 */ + +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIN_PD30X1_AFEC0_AD0 _L_(126) /**< AFEC0 signal: AFEC0_AD0 on PD30 mux X1 */ +#define PIO_PD30X1_AFEC0_AD0 (_U_(1) << 30) /**< AFEC0 signal: AFEC0_AD0 */ +#define PIN_PA21X1_AFEC0_AD1 _L_(21) /**< AFEC0 signal: AFEC0_AD1 on PA21 mux X1 */ +#define PIO_PA21X1_AFEC0_AD1 (_U_(1) << 21) /**< AFEC0 signal: AFEC0_AD1 */ +#define PIN_PB3X1_AFEC0_AD2 _L_(35) /**< AFEC0 signal: AFEC0_AD2 on PB3 mux X1 */ +#define PIO_PB3X1_AFEC0_AD2 (_U_(1) << 3) /**< AFEC0 signal: AFEC0_AD2 */ +#define PIN_PE5X1_AFEC0_AD3 _L_(133) /**< AFEC0 signal: AFEC0_AD3 on PE5 mux X1 */ +#define PIO_PE5X1_AFEC0_AD3 (_U_(1) << 5) /**< AFEC0 signal: AFEC0_AD3 */ +#define PIN_PE4X1_AFEC0_AD4 _L_(132) /**< AFEC0 signal: AFEC0_AD4 on PE4 mux X1 */ +#define PIO_PE4X1_AFEC0_AD4 (_U_(1) << 4) /**< AFEC0 signal: AFEC0_AD4 */ +#define PIN_PB2X1_AFEC0_AD5 _L_(34) /**< AFEC0 signal: AFEC0_AD5 on PB2 mux X1 */ +#define PIO_PB2X1_AFEC0_AD5 (_U_(1) << 2) /**< AFEC0 signal: AFEC0_AD5 */ +#define PIN_PA17X1_AFEC0_AD6 _L_(17) /**< AFEC0 signal: AFEC0_AD6 on PA17 mux X1 */ +#define PIO_PA17X1_AFEC0_AD6 (_U_(1) << 17) /**< AFEC0 signal: AFEC0_AD6 */ +#define PIN_PA18X1_AFEC0_AD7 _L_(18) /**< AFEC0 signal: AFEC0_AD7 on PA18 mux X1 */ +#define PIO_PA18X1_AFEC0_AD7 (_U_(1) << 18) /**< AFEC0 signal: AFEC0_AD7 */ +#define PIN_PA19X1_AFEC0_AD8 _L_(19) /**< AFEC0 signal: AFEC0_AD8 on PA19 mux X1 */ +#define PIO_PA19X1_AFEC0_AD8 (_U_(1) << 19) /**< AFEC0 signal: AFEC0_AD8 */ +#define PIN_PA20X1_AFEC0_AD9 _L_(20) /**< AFEC0 signal: AFEC0_AD9 on PA20 mux X1 */ +#define PIO_PA20X1_AFEC0_AD9 (_U_(1) << 20) /**< AFEC0 signal: AFEC0_AD9 */ +#define PIN_PB0X1_AFEC0_AD10 _L_(32) /**< AFEC0 signal: AFEC0_AD10 on PB0 mux X1 */ +#define PIO_PB0X1_AFEC0_AD10 (_U_(1) << 0) /**< AFEC0 signal: AFEC0_AD10 */ +#define PIN_PA8B_AFEC0_ADTRG _L_(8) /**< AFEC0 signal: AFEC0_ADTRG on PA8 mux B */ +#define MUX_PA8B_AFEC0_ADTRG _L_(1) /**< AFEC0 signal line function value: AFEC0_ADTRG */ +#define PIO_PA8B_AFEC0_ADTRG (_U_(1) << 8) /**< AFEC0 signal: AFEC0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIN_PB1X1_AFEC1_AD0 _L_(33) /**< AFEC1 signal: AFEC1_AD0 on PB1 mux X1 */ +#define PIO_PB1X1_AFEC1_AD0 (_U_(1) << 1) /**< AFEC1 signal: AFEC1_AD0 */ +#define PIN_PC13X1_AFEC1_AD1 _L_(77) /**< AFEC1 signal: AFEC1_AD1 on PC13 mux X1 */ +#define PIO_PC13X1_AFEC1_AD1 (_U_(1) << 13) /**< AFEC1 signal: AFEC1_AD1 */ +#define PIN_PC15X1_AFEC1_AD2 _L_(79) /**< AFEC1 signal: AFEC1_AD2 on PC15 mux X1 */ +#define PIO_PC15X1_AFEC1_AD2 (_U_(1) << 15) /**< AFEC1 signal: AFEC1_AD2 */ +#define PIN_PC12X1_AFEC1_AD3 _L_(76) /**< AFEC1 signal: AFEC1_AD3 on PC12 mux X1 */ +#define PIO_PC12X1_AFEC1_AD3 (_U_(1) << 12) /**< AFEC1 signal: AFEC1_AD3 */ +#define PIN_PC29X1_AFEC1_AD4 _L_(93) /**< AFEC1 signal: AFEC1_AD4 on PC29 mux X1 */ +#define PIO_PC29X1_AFEC1_AD4 (_U_(1) << 29) /**< AFEC1 signal: AFEC1_AD4 */ +#define PIN_PC30X1_AFEC1_AD5 _L_(94) /**< AFEC1 signal: AFEC1_AD5 on PC30 mux X1 */ +#define PIO_PC30X1_AFEC1_AD5 (_U_(1) << 30) /**< AFEC1 signal: AFEC1_AD5 */ +#define PIN_PC31X1_AFEC1_AD6 _L_(95) /**< AFEC1 signal: AFEC1_AD6 on PC31 mux X1 */ +#define PIO_PC31X1_AFEC1_AD6 (_U_(1) << 31) /**< AFEC1 signal: AFEC1_AD6 */ +#define PIN_PC26X1_AFEC1_AD7 _L_(90) /**< AFEC1 signal: AFEC1_AD7 on PC26 mux X1 */ +#define PIO_PC26X1_AFEC1_AD7 (_U_(1) << 26) /**< AFEC1 signal: AFEC1_AD7 */ +#define PIN_PC27X1_AFEC1_AD8 _L_(91) /**< AFEC1 signal: AFEC1_AD8 on PC27 mux X1 */ +#define PIO_PC27X1_AFEC1_AD8 (_U_(1) << 27) /**< AFEC1 signal: AFEC1_AD8 */ +#define PIN_PC0X1_AFEC1_AD9 _L_(64) /**< AFEC1 signal: AFEC1_AD9 on PC0 mux X1 */ +#define PIO_PC0X1_AFEC1_AD9 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD9 */ +#define PIN_PE3X1_AFEC1_AD10 _L_(131) /**< AFEC1 signal: AFEC1_AD10 on PE3 mux X1 */ +#define PIO_PE3X1_AFEC1_AD10 (_U_(1) << 3) /**< AFEC1 signal: AFEC1_AD10 */ +#define PIN_PE0X1_AFEC1_AD11 _L_(128) /**< AFEC1 signal: AFEC1_AD11 on PE0 mux X1 */ +#define PIO_PE0X1_AFEC1_AD11 (_U_(1) << 0) /**< AFEC1 signal: AFEC1_AD11 */ +#define PIN_PD9C_AFEC1_ADTRG _L_(105) /**< AFEC1 signal: AFEC1_ADTRG on PD9 mux C */ +#define MUX_PD9C_AFEC1_ADTRG _L_(2) /**< AFEC1 signal line function value: AFEC1_ADTRG */ +#define PIO_PD9C_AFEC1_ADTRG (_U_(1) << 9) /**< AFEC1 signal: AFEC1_ADTRG */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIN_PB13X1_DACC_DAC0 _L_(45) /**< DACC signal: DACC_DAC0 on PB13 mux X1 */ +#define PIO_PB13X1_DACC_DAC0 (_U_(1) << 13) /**< DACC signal: DACC_DAC0 */ +#define PIN_PD0X1_DACC_DAC1 _L_(96) /**< DACC signal: DACC_DAC1 on PD0 mux X1 */ +#define PIO_PD0X1_DACC_DAC1 (_U_(1) << 0) /**< DACC signal: DACC_DAC1 */ +#define PIN_PA2C_DACC_DATRG _L_(2) /**< DACC signal: DACC_DATRG on PA2 mux C */ +#define MUX_PA2C_DACC_DATRG _L_(2) /**< DACC signal line function value: DACC_DATRG */ +#define PIO_PA2C_DACC_DATRG (_U_(1) << 2) /**< DACC signal: DACC_DATRG */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIN_PC18A_EBI_A0 _L_(82) /**< EBI signal: EBI_A0 on PC18 mux A */ +#define MUX_PC18A_EBI_A0 _L_(0) /**< EBI signal line function value: EBI_A0 */ +#define PIO_PC18A_EBI_A0 (_U_(1) << 18) /**< EBI signal: EBI_A0 */ +#define PIN_PC19A_EBI_A1 _L_(83) /**< EBI signal: EBI_A1 on PC19 mux A */ +#define MUX_PC19A_EBI_A1 _L_(0) /**< EBI signal line function value: EBI_A1 */ +#define PIO_PC19A_EBI_A1 (_U_(1) << 19) /**< EBI signal: EBI_A1 */ +#define PIN_PC20A_EBI_A2 _L_(84) /**< EBI signal: EBI_A2 on PC20 mux A */ +#define MUX_PC20A_EBI_A2 _L_(0) /**< EBI signal line function value: EBI_A2 */ +#define PIO_PC20A_EBI_A2 (_U_(1) << 20) /**< EBI signal: EBI_A2 */ +#define PIN_PC21A_EBI_A3 _L_(85) /**< EBI signal: EBI_A3 on PC21 mux A */ +#define MUX_PC21A_EBI_A3 _L_(0) /**< EBI signal line function value: EBI_A3 */ +#define PIO_PC21A_EBI_A3 (_U_(1) << 21) /**< EBI signal: EBI_A3 */ +#define PIN_PC22A_EBI_A4 _L_(86) /**< EBI signal: EBI_A4 on PC22 mux A */ +#define MUX_PC22A_EBI_A4 _L_(0) /**< EBI signal line function value: EBI_A4 */ +#define PIO_PC22A_EBI_A4 (_U_(1) << 22) /**< EBI signal: EBI_A4 */ +#define PIN_PC23A_EBI_A5 _L_(87) /**< EBI signal: EBI_A5 on PC23 mux A */ +#define MUX_PC23A_EBI_A5 _L_(0) /**< EBI signal line function value: EBI_A5 */ +#define PIO_PC23A_EBI_A5 (_U_(1) << 23) /**< EBI signal: EBI_A5 */ +#define PIN_PC24A_EBI_A6 _L_(88) /**< EBI signal: EBI_A6 on PC24 mux A */ +#define MUX_PC24A_EBI_A6 _L_(0) /**< EBI signal line function value: EBI_A6 */ +#define PIO_PC24A_EBI_A6 (_U_(1) << 24) /**< EBI signal: EBI_A6 */ +#define PIN_PC25A_EBI_A7 _L_(89) /**< EBI signal: EBI_A7 on PC25 mux A */ +#define MUX_PC25A_EBI_A7 _L_(0) /**< EBI signal line function value: EBI_A7 */ +#define PIO_PC25A_EBI_A7 (_U_(1) << 25) /**< EBI signal: EBI_A7 */ +#define PIN_PC26A_EBI_A8 _L_(90) /**< EBI signal: EBI_A8 on PC26 mux A */ +#define MUX_PC26A_EBI_A8 _L_(0) /**< EBI signal line function value: EBI_A8 */ +#define PIO_PC26A_EBI_A8 (_U_(1) << 26) /**< EBI signal: EBI_A8 */ +#define PIN_PC27A_EBI_A9 _L_(91) /**< EBI signal: EBI_A9 on PC27 mux A */ +#define MUX_PC27A_EBI_A9 _L_(0) /**< EBI signal line function value: EBI_A9 */ +#define PIO_PC27A_EBI_A9 (_U_(1) << 27) /**< EBI signal: EBI_A9 */ +#define PIN_PC28A_EBI_A10 _L_(92) /**< EBI signal: EBI_A10 on PC28 mux A */ +#define MUX_PC28A_EBI_A10 _L_(0) /**< EBI signal line function value: EBI_A10 */ +#define PIO_PC28A_EBI_A10 (_U_(1) << 28) /**< EBI signal: EBI_A10 */ +#define PIN_PC29A_EBI_A11 _L_(93) /**< EBI signal: EBI_A11 on PC29 mux A */ +#define MUX_PC29A_EBI_A11 _L_(0) /**< EBI signal line function value: EBI_A11 */ +#define PIO_PC29A_EBI_A11 (_U_(1) << 29) /**< EBI signal: EBI_A11 */ +#define PIN_PC30A_EBI_A12 _L_(94) /**< EBI signal: EBI_A12 on PC30 mux A */ +#define MUX_PC30A_EBI_A12 _L_(0) /**< EBI signal line function value: EBI_A12 */ +#define PIO_PC30A_EBI_A12 (_U_(1) << 30) /**< EBI signal: EBI_A12 */ +#define PIN_PC31A_EBI_A13 _L_(95) /**< EBI signal: EBI_A13 on PC31 mux A */ +#define MUX_PC31A_EBI_A13 _L_(0) /**< EBI signal line function value: EBI_A13 */ +#define PIO_PC31A_EBI_A13 (_U_(1) << 31) /**< EBI signal: EBI_A13 */ +#define PIN_PA18C_EBI_A14 _L_(18) /**< EBI signal: EBI_A14 on PA18 mux C */ +#define MUX_PA18C_EBI_A14 _L_(2) /**< EBI signal line function value: EBI_A14 */ +#define PIO_PA18C_EBI_A14 (_U_(1) << 18) /**< EBI signal: EBI_A14 */ +#define PIN_PA19C_EBI_A15 _L_(19) /**< EBI signal: EBI_A15 on PA19 mux C */ +#define MUX_PA19C_EBI_A15 _L_(2) /**< EBI signal line function value: EBI_A15 */ +#define PIO_PA19C_EBI_A15 (_U_(1) << 19) /**< EBI signal: EBI_A15 */ +#define PIN_PA20C_EBI_A16 _L_(20) /**< EBI signal: EBI_A16 on PA20 mux C */ +#define MUX_PA20C_EBI_A16 _L_(2) /**< EBI signal line function value: EBI_A16 */ +#define PIO_PA20C_EBI_A16 (_U_(1) << 20) /**< EBI signal: EBI_A16 */ +#define PIN_PA0C_EBI_A17 _L_(0) /**< EBI signal: EBI_A17 on PA0 mux C */ +#define MUX_PA0C_EBI_A17 _L_(2) /**< EBI signal line function value: EBI_A17 */ +#define PIO_PA0C_EBI_A17 (_U_(1) << 0) /**< EBI signal: EBI_A17 */ +#define PIN_PA1C_EBI_A18 _L_(1) /**< EBI signal: EBI_A18 on PA1 mux C */ +#define MUX_PA1C_EBI_A18 _L_(2) /**< EBI signal line function value: EBI_A18 */ +#define PIO_PA1C_EBI_A18 (_U_(1) << 1) /**< EBI signal: EBI_A18 */ +#define PIN_PA23C_EBI_A19 _L_(23) /**< EBI signal: EBI_A19 on PA23 mux C */ +#define MUX_PA23C_EBI_A19 _L_(2) /**< EBI signal line function value: EBI_A19 */ +#define PIO_PA23C_EBI_A19 (_U_(1) << 23) /**< EBI signal: EBI_A19 */ +#define PIN_PA24C_EBI_A20 _L_(24) /**< EBI signal: EBI_A20 on PA24 mux C */ +#define MUX_PA24C_EBI_A20 _L_(2) /**< EBI signal line function value: EBI_A20 */ +#define PIO_PA24C_EBI_A20 (_U_(1) << 24) /**< EBI signal: EBI_A20 */ +#define PIN_PC16A_EBI_A21 _L_(80) /**< EBI signal: EBI_A21 on PC16 mux A */ +#define MUX_PC16A_EBI_A21 _L_(0) /**< EBI signal line function value: EBI_A21 */ +#define PIO_PC16A_EBI_A21 (_U_(1) << 16) /**< EBI signal: EBI_A21 */ +#define PIN_PC17A_EBI_A22 _L_(81) /**< EBI signal: EBI_A22 on PC17 mux A */ +#define MUX_PC17A_EBI_A22 _L_(0) /**< EBI signal line function value: EBI_A22 */ +#define PIO_PC17A_EBI_A22 (_U_(1) << 17) /**< EBI signal: EBI_A22 */ +#define PIN_PA25C_EBI_A23 _L_(25) /**< EBI signal: EBI_A23 on PA25 mux C */ +#define MUX_PA25C_EBI_A23 _L_(2) /**< EBI signal line function value: EBI_A23 */ +#define PIO_PA25C_EBI_A23 (_U_(1) << 25) /**< EBI signal: EBI_A23 */ +#define PIN_PA20C_EBI_BA0 _L_(20) /**< EBI signal: EBI_BA0 on PA20 mux C */ +#define MUX_PA20C_EBI_BA0 _L_(2) /**< EBI signal line function value: EBI_BA0 */ +#define PIO_PA20C_EBI_BA0 (_U_(1) << 20) /**< EBI signal: EBI_BA0 */ +#define PIN_PA0C_EBI_BA1 _L_(0) /**< EBI signal: EBI_BA1 on PA0 mux C */ +#define MUX_PA0C_EBI_BA1 _L_(2) /**< EBI signal line function value: EBI_BA1 */ +#define PIO_PA0C_EBI_BA1 (_U_(1) << 0) /**< EBI signal: EBI_BA1 */ +#define PIN_PD17C_EBI_CAS _L_(113) /**< EBI signal: EBI_CAS on PD17 mux C */ +#define MUX_PD17C_EBI_CAS _L_(2) /**< EBI signal line function value: EBI_CAS */ +#define PIO_PD17C_EBI_CAS (_U_(1) << 17) /**< EBI signal: EBI_CAS */ +#define PIN_PC0A_EBI_D0 _L_(64) /**< EBI signal: EBI_D0 on PC0 mux A */ +#define MUX_PC0A_EBI_D0 _L_(0) /**< EBI signal line function value: EBI_D0 */ +#define PIO_PC0A_EBI_D0 (_U_(1) << 0) /**< EBI signal: EBI_D0 */ +#define PIN_PC1A_EBI_D1 _L_(65) /**< EBI signal: EBI_D1 on PC1 mux A */ +#define MUX_PC1A_EBI_D1 _L_(0) /**< EBI signal line function value: EBI_D1 */ +#define PIO_PC1A_EBI_D1 (_U_(1) << 1) /**< EBI signal: EBI_D1 */ +#define PIN_PC2A_EBI_D2 _L_(66) /**< EBI signal: EBI_D2 on PC2 mux A */ +#define MUX_PC2A_EBI_D2 _L_(0) /**< EBI signal line function value: EBI_D2 */ +#define PIO_PC2A_EBI_D2 (_U_(1) << 2) /**< EBI signal: EBI_D2 */ +#define PIN_PC3A_EBI_D3 _L_(67) /**< EBI signal: EBI_D3 on PC3 mux A */ +#define MUX_PC3A_EBI_D3 _L_(0) /**< EBI signal line function value: EBI_D3 */ +#define PIO_PC3A_EBI_D3 (_U_(1) << 3) /**< EBI signal: EBI_D3 */ +#define PIN_PC4A_EBI_D4 _L_(68) /**< EBI signal: EBI_D4 on PC4 mux A */ +#define MUX_PC4A_EBI_D4 _L_(0) /**< EBI signal line function value: EBI_D4 */ +#define PIO_PC4A_EBI_D4 (_U_(1) << 4) /**< EBI signal: EBI_D4 */ +#define PIN_PC5A_EBI_D5 _L_(69) /**< EBI signal: EBI_D5 on PC5 mux A */ +#define MUX_PC5A_EBI_D5 _L_(0) /**< EBI signal line function value: EBI_D5 */ +#define PIO_PC5A_EBI_D5 (_U_(1) << 5) /**< EBI signal: EBI_D5 */ +#define PIN_PC6A_EBI_D6 _L_(70) /**< EBI signal: EBI_D6 on PC6 mux A */ +#define MUX_PC6A_EBI_D6 _L_(0) /**< EBI signal line function value: EBI_D6 */ +#define PIO_PC6A_EBI_D6 (_U_(1) << 6) /**< EBI signal: EBI_D6 */ +#define PIN_PC7A_EBI_D7 _L_(71) /**< EBI signal: EBI_D7 on PC7 mux A */ +#define MUX_PC7A_EBI_D7 _L_(0) /**< EBI signal line function value: EBI_D7 */ +#define PIO_PC7A_EBI_D7 (_U_(1) << 7) /**< EBI signal: EBI_D7 */ +#define PIN_PE0A_EBI_D8 _L_(128) /**< EBI signal: EBI_D8 on PE0 mux A */ +#define MUX_PE0A_EBI_D8 _L_(0) /**< EBI signal line function value: EBI_D8 */ +#define PIO_PE0A_EBI_D8 (_U_(1) << 0) /**< EBI signal: EBI_D8 */ +#define PIN_PE1A_EBI_D9 _L_(129) /**< EBI signal: EBI_D9 on PE1 mux A */ +#define MUX_PE1A_EBI_D9 _L_(0) /**< EBI signal line function value: EBI_D9 */ +#define PIO_PE1A_EBI_D9 (_U_(1) << 1) /**< EBI signal: EBI_D9 */ +#define PIN_PE2A_EBI_D10 _L_(130) /**< EBI signal: EBI_D10 on PE2 mux A */ +#define MUX_PE2A_EBI_D10 _L_(0) /**< EBI signal line function value: EBI_D10 */ +#define PIO_PE2A_EBI_D10 (_U_(1) << 2) /**< EBI signal: EBI_D10 */ +#define PIN_PE3A_EBI_D11 _L_(131) /**< EBI signal: EBI_D11 on PE3 mux A */ +#define MUX_PE3A_EBI_D11 _L_(0) /**< EBI signal line function value: EBI_D11 */ +#define PIO_PE3A_EBI_D11 (_U_(1) << 3) /**< EBI signal: EBI_D11 */ +#define PIN_PE4A_EBI_D12 _L_(132) /**< EBI signal: EBI_D12 on PE4 mux A */ +#define MUX_PE4A_EBI_D12 _L_(0) /**< EBI signal line function value: EBI_D12 */ +#define PIO_PE4A_EBI_D12 (_U_(1) << 4) /**< EBI signal: EBI_D12 */ +#define PIN_PE5A_EBI_D13 _L_(133) /**< EBI signal: EBI_D13 on PE5 mux A */ +#define MUX_PE5A_EBI_D13 _L_(0) /**< EBI signal line function value: EBI_D13 */ +#define PIO_PE5A_EBI_D13 (_U_(1) << 5) /**< EBI signal: EBI_D13 */ +#define PIN_PA15A_EBI_D14 _L_(15) /**< EBI signal: EBI_D14 on PA15 mux A */ +#define MUX_PA15A_EBI_D14 _L_(0) /**< EBI signal line function value: EBI_D14 */ +#define PIO_PA15A_EBI_D14 (_U_(1) << 15) /**< EBI signal: EBI_D14 */ +#define PIN_PA16A_EBI_D15 _L_(16) /**< EBI signal: EBI_D15 on PA16 mux A */ +#define MUX_PA16A_EBI_D15 _L_(0) /**< EBI signal line function value: EBI_D15 */ +#define PIO_PA16A_EBI_D15 (_U_(1) << 16) /**< EBI signal: EBI_D15 */ +#define PIN_PC18A_EBI_DQM0 _L_(82) /**< EBI signal: EBI_DQM0 on PC18 mux A */ +#define MUX_PC18A_EBI_DQM0 _L_(0) /**< EBI signal line function value: EBI_DQM0 */ +#define PIO_PC18A_EBI_DQM0 (_U_(1) << 18) /**< EBI signal: EBI_DQM0 */ +#define PIN_PD15C_EBI_DQM1 _L_(111) /**< EBI signal: EBI_DQM1 on PD15 mux C */ +#define MUX_PD15C_EBI_DQM1 _L_(2) /**< EBI signal line function value: EBI_DQM1 */ +#define PIO_PD15C_EBI_DQM1 (_U_(1) << 15) /**< EBI signal: EBI_DQM1 */ +#define PIN_PC16A_EBI_NANDALE _L_(80) /**< EBI signal: EBI_NANDALE on PC16 mux A */ +#define MUX_PC16A_EBI_NANDALE _L_(0) /**< EBI signal line function value: EBI_NANDALE */ +#define PIO_PC16A_EBI_NANDALE (_U_(1) << 16) /**< EBI signal: EBI_NANDALE */ +#define PIN_PC17A_EBI_NANDCLE _L_(81) /**< EBI signal: EBI_NANDCLE on PC17 mux A */ +#define MUX_PC17A_EBI_NANDCLE _L_(0) /**< EBI signal line function value: EBI_NANDCLE */ +#define PIO_PC17A_EBI_NANDCLE (_U_(1) << 17) /**< EBI signal: EBI_NANDCLE */ +#define PIN_PC9A_EBI_NANDOE _L_(73) /**< EBI signal: EBI_NANDOE on PC9 mux A */ +#define MUX_PC9A_EBI_NANDOE _L_(0) /**< EBI signal line function value: EBI_NANDOE */ +#define PIO_PC9A_EBI_NANDOE (_U_(1) << 9) /**< EBI signal: EBI_NANDOE */ +#define PIN_PC10A_EBI_NANDWE _L_(74) /**< EBI signal: EBI_NANDWE on PC10 mux A */ +#define MUX_PC10A_EBI_NANDWE _L_(0) /**< EBI signal line function value: EBI_NANDWE */ +#define PIO_PC10A_EBI_NANDWE (_U_(1) << 10) /**< EBI signal: EBI_NANDWE */ +#define PIN_PC18A_EBI_NBS0 _L_(82) /**< EBI signal: EBI_NBS0 on PC18 mux A */ +#define MUX_PC18A_EBI_NBS0 _L_(0) /**< EBI signal line function value: EBI_NBS0 */ +#define PIO_PC18A_EBI_NBS0 (_U_(1) << 18) /**< EBI signal: EBI_NBS0 */ +#define PIN_PD15C_EBI_NBS1 _L_(111) /**< EBI signal: EBI_NBS1 on PD15 mux C */ +#define MUX_PD15C_EBI_NBS1 _L_(2) /**< EBI signal line function value: EBI_NBS1 */ +#define PIO_PD15C_EBI_NBS1 (_U_(1) << 15) /**< EBI signal: EBI_NBS1 */ +#define PIN_PC14A_EBI_NCS0 _L_(78) /**< EBI signal: EBI_NCS0 on PC14 mux A */ +#define MUX_PC14A_EBI_NCS0 _L_(0) /**< EBI signal line function value: EBI_NCS0 */ +#define PIO_PC14A_EBI_NCS0 (_U_(1) << 14) /**< EBI signal: EBI_NCS0 */ +#define PIN_PC15A_EBI_NCS1 _L_(79) /**< EBI signal: EBI_NCS1 on PC15 mux A */ +#define MUX_PC15A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PC15A_EBI_NCS1 (_U_(1) << 15) /**< EBI signal: EBI_NCS1 */ +#define PIN_PD18A_EBI_NCS1 _L_(114) /**< EBI signal: EBI_NCS1 on PD18 mux A */ +#define MUX_PD18A_EBI_NCS1 _L_(0) /**< EBI signal line function value: EBI_NCS1 */ +#define PIO_PD18A_EBI_NCS1 (_U_(1) << 18) /**< EBI signal: EBI_NCS1 */ +#define PIN_PA22C_EBI_NCS2 _L_(22) /**< EBI signal: EBI_NCS2 on PA22 mux C */ +#define MUX_PA22C_EBI_NCS2 _L_(2) /**< EBI signal line function value: EBI_NCS2 */ +#define PIO_PA22C_EBI_NCS2 (_U_(1) << 22) /**< EBI signal: EBI_NCS2 */ +#define PIN_PC12A_EBI_NCS3 _L_(76) /**< EBI signal: EBI_NCS3 on PC12 mux A */ +#define MUX_PC12A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PC12A_EBI_NCS3 (_U_(1) << 12) /**< EBI signal: EBI_NCS3 */ +#define PIN_PD19A_EBI_NCS3 _L_(115) /**< EBI signal: EBI_NCS3 on PD19 mux A */ +#define MUX_PD19A_EBI_NCS3 _L_(0) /**< EBI signal line function value: EBI_NCS3 */ +#define PIO_PD19A_EBI_NCS3 (_U_(1) << 19) /**< EBI signal: EBI_NCS3 */ +#define PIN_PC11A_EBI_NRD _L_(75) /**< EBI signal: EBI_NRD on PC11 mux A */ +#define MUX_PC11A_EBI_NRD _L_(0) /**< EBI signal line function value: EBI_NRD */ +#define PIO_PC11A_EBI_NRD (_U_(1) << 11) /**< EBI signal: EBI_NRD */ +#define PIN_PC13A_EBI_NWAIT _L_(77) /**< EBI signal: EBI_NWAIT on PC13 mux A */ +#define MUX_PC13A_EBI_NWAIT _L_(0) /**< EBI signal line function value: EBI_NWAIT */ +#define PIO_PC13A_EBI_NWAIT (_U_(1) << 13) /**< EBI signal: EBI_NWAIT */ +#define PIN_PC8A_EBI_NWE _L_(72) /**< EBI signal: EBI_NWE on PC8 mux A */ +#define MUX_PC8A_EBI_NWE _L_(0) /**< EBI signal line function value: EBI_NWE */ +#define PIO_PC8A_EBI_NWE (_U_(1) << 8) /**< EBI signal: EBI_NWE */ +#define PIN_PC8A_EBI_NWR0 _L_(72) /**< EBI signal: EBI_NWR0 on PC8 mux A */ +#define MUX_PC8A_EBI_NWR0 _L_(0) /**< EBI signal line function value: EBI_NWR0 */ +#define PIO_PC8A_EBI_NWR0 (_U_(1) << 8) /**< EBI signal: EBI_NWR0 */ +#define PIN_PD15C_EBI_NWR1 _L_(111) /**< EBI signal: EBI_NWR1 on PD15 mux C */ +#define MUX_PD15C_EBI_NWR1 _L_(2) /**< EBI signal line function value: EBI_NWR1 */ +#define PIO_PD15C_EBI_NWR1 (_U_(1) << 15) /**< EBI signal: EBI_NWR1 */ +#define PIN_PD16C_EBI_RAS _L_(112) /**< EBI signal: EBI_RAS on PD16 mux C */ +#define MUX_PD16C_EBI_RAS _L_(2) /**< EBI signal line function value: EBI_RAS */ +#define PIO_PD16C_EBI_RAS (_U_(1) << 16) /**< EBI signal: EBI_RAS */ +#define PIN_PC13C_EBI_SDA10 _L_(77) /**< EBI signal: EBI_SDA10 on PC13 mux C */ +#define MUX_PC13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PC13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PD13C_EBI_SDA10 _L_(109) /**< EBI signal: EBI_SDA10 on PD13 mux C */ +#define MUX_PD13C_EBI_SDA10 _L_(2) /**< EBI signal line function value: EBI_SDA10 */ +#define PIO_PD13C_EBI_SDA10 (_U_(1) << 13) /**< EBI signal: EBI_SDA10 */ +#define PIN_PC20A_EBI_SDA0 _L_(84) /**< EBI signal: EBI_SDA0 on PC20 mux A */ +#define MUX_PC20A_EBI_SDA0 _L_(0) /**< EBI signal line function value: EBI_SDA0 */ +#define PIO_PC20A_EBI_SDA0 (_U_(1) << 20) /**< EBI signal: EBI_SDA0 */ +#define PIN_PC21A_EBI_SDA1 _L_(85) /**< EBI signal: EBI_SDA1 on PC21 mux A */ +#define MUX_PC21A_EBI_SDA1 _L_(0) /**< EBI signal line function value: EBI_SDA1 */ +#define PIO_PC21A_EBI_SDA1 (_U_(1) << 21) /**< EBI signal: EBI_SDA1 */ +#define PIN_PC31A_EBI_SDA11 _L_(95) /**< EBI signal: EBI_SDA11 on PC31 mux A */ +#define MUX_PC31A_EBI_SDA11 _L_(0) /**< EBI signal line function value: EBI_SDA11 */ +#define PIO_PC31A_EBI_SDA11 (_U_(1) << 31) /**< EBI signal: EBI_SDA11 */ +#define PIN_PA18C_EBI_SDA12 _L_(18) /**< EBI signal: EBI_SDA12 on PA18 mux C */ +#define MUX_PA18C_EBI_SDA12 _L_(2) /**< EBI signal line function value: EBI_SDA12 */ +#define PIO_PA18C_EBI_SDA12 (_U_(1) << 18) /**< EBI signal: EBI_SDA12 */ +#define PIN_PC22A_EBI_SDA2 _L_(86) /**< EBI signal: EBI_SDA2 on PC22 mux A */ +#define MUX_PC22A_EBI_SDA2 _L_(0) /**< EBI signal line function value: EBI_SDA2 */ +#define PIO_PC22A_EBI_SDA2 (_U_(1) << 22) /**< EBI signal: EBI_SDA2 */ +#define PIN_PC23A_EBI_SDA3 _L_(87) /**< EBI signal: EBI_SDA3 on PC23 mux A */ +#define MUX_PC23A_EBI_SDA3 _L_(0) /**< EBI signal line function value: EBI_SDA3 */ +#define PIO_PC23A_EBI_SDA3 (_U_(1) << 23) /**< EBI signal: EBI_SDA3 */ +#define PIN_PC24A_EBI_SDA4 _L_(88) /**< EBI signal: EBI_SDA4 on PC24 mux A */ +#define MUX_PC24A_EBI_SDA4 _L_(0) /**< EBI signal line function value: EBI_SDA4 */ +#define PIO_PC24A_EBI_SDA4 (_U_(1) << 24) /**< EBI signal: EBI_SDA4 */ +#define PIN_PC25A_EBI_SDA5 _L_(89) /**< EBI signal: EBI_SDA5 on PC25 mux A */ +#define MUX_PC25A_EBI_SDA5 _L_(0) /**< EBI signal line function value: EBI_SDA5 */ +#define PIO_PC25A_EBI_SDA5 (_U_(1) << 25) /**< EBI signal: EBI_SDA5 */ +#define PIN_PC26A_EBI_SDA6 _L_(90) /**< EBI signal: EBI_SDA6 on PC26 mux A */ +#define MUX_PC26A_EBI_SDA6 _L_(0) /**< EBI signal line function value: EBI_SDA6 */ +#define PIO_PC26A_EBI_SDA6 (_U_(1) << 26) /**< EBI signal: EBI_SDA6 */ +#define PIN_PC27A_EBI_SDA7 _L_(91) /**< EBI signal: EBI_SDA7 on PC27 mux A */ +#define MUX_PC27A_EBI_SDA7 _L_(0) /**< EBI signal line function value: EBI_SDA7 */ +#define PIO_PC27A_EBI_SDA7 (_U_(1) << 27) /**< EBI signal: EBI_SDA7 */ +#define PIN_PC28A_EBI_SDA8 _L_(92) /**< EBI signal: EBI_SDA8 on PC28 mux A */ +#define MUX_PC28A_EBI_SDA8 _L_(0) /**< EBI signal line function value: EBI_SDA8 */ +#define PIO_PC28A_EBI_SDA8 (_U_(1) << 28) /**< EBI signal: EBI_SDA8 */ +#define PIN_PC29A_EBI_SDA9 _L_(93) /**< EBI signal: EBI_SDA9 on PC29 mux A */ +#define MUX_PC29A_EBI_SDA9 _L_(0) /**< EBI signal line function value: EBI_SDA9 */ +#define PIO_PC29A_EBI_SDA9 (_U_(1) << 29) /**< EBI signal: EBI_SDA9 */ +#define PIN_PD23C_EBI_SDCK _L_(119) /**< EBI signal: EBI_SDCK on PD23 mux C */ +#define MUX_PD23C_EBI_SDCK _L_(2) /**< EBI signal line function value: EBI_SDCK */ +#define PIO_PD23C_EBI_SDCK (_U_(1) << 23) /**< EBI signal: EBI_SDCK */ +#define PIN_PD14C_EBI_SDCKE _L_(110) /**< EBI signal: EBI_SDCKE on PD14 mux C */ +#define MUX_PD14C_EBI_SDCKE _L_(2) /**< EBI signal line function value: EBI_SDCKE */ +#define PIO_PD14C_EBI_SDCKE (_U_(1) << 14) /**< EBI signal: EBI_SDCKE */ +#define PIN_PC15A_EBI_SDCS _L_(79) /**< EBI signal: EBI_SDCS on PC15 mux A */ +#define MUX_PC15A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PC15A_EBI_SDCS (_U_(1) << 15) /**< EBI signal: EBI_SDCS */ +#define PIN_PD18A_EBI_SDCS _L_(114) /**< EBI signal: EBI_SDCS on PD18 mux A */ +#define MUX_PD18A_EBI_SDCS _L_(0) /**< EBI signal line function value: EBI_SDCS */ +#define PIO_PD18A_EBI_SDCS (_U_(1) << 18) /**< EBI signal: EBI_SDCS */ +#define PIN_PD29C_EBI_SDWE _L_(125) /**< EBI signal: EBI_SDWE on PD29 mux C */ +#define MUX_PD29C_EBI_SDWE _L_(2) /**< EBI signal line function value: EBI_SDWE */ +#define PIO_PD29C_EBI_SDWE (_U_(1) << 29) /**< EBI signal: EBI_SDWE */ +/* ========== PIO definition for EFC peripheral ========== */ +#define PIN_PB12X1_EFC_ERASE _L_(44) /**< EFC signal: EFC_ERASE on PB12 mux X1 */ +#define PIO_PB12X1_EFC_ERASE (_U_(1) << 12) /**< EFC signal: EFC_ERASE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIN_PD13A_GMAC_GCOL _L_(109) /**< GMAC signal: GMAC_GCOL on PD13 mux A */ +#define MUX_PD13A_GMAC_GCOL _L_(0) /**< GMAC signal line function value: GMAC_GCOL */ +#define PIO_PD13A_GMAC_GCOL (_U_(1) << 13) /**< GMAC signal: GMAC_GCOL */ +#define PIN_PD10A_GMAC_GCRS _L_(106) /**< GMAC signal: GMAC_GCRS on PD10 mux A */ +#define MUX_PD10A_GMAC_GCRS _L_(0) /**< GMAC signal line function value: GMAC_GCRS */ +#define PIO_PD10A_GMAC_GCRS (_U_(1) << 10) /**< GMAC signal: GMAC_GCRS */ +#define PIN_PD8A_GMAC_GMDC _L_(104) /**< GMAC signal: GMAC_GMDC on PD8 mux A */ +#define MUX_PD8A_GMAC_GMDC _L_(0) /**< GMAC signal line function value: GMAC_GMDC */ +#define PIO_PD8A_GMAC_GMDC (_U_(1) << 8) /**< GMAC signal: GMAC_GMDC */ +#define PIN_PD9A_GMAC_GMDIO _L_(105) /**< GMAC signal: GMAC_GMDIO on PD9 mux A */ +#define MUX_PD9A_GMAC_GMDIO _L_(0) /**< GMAC signal line function value: GMAC_GMDIO */ +#define PIO_PD9A_GMAC_GMDIO (_U_(1) << 9) /**< GMAC signal: GMAC_GMDIO */ +#define PIN_PD5A_GMAC_GRX0 _L_(101) /**< GMAC signal: GMAC_GRX0 on PD5 mux A */ +#define MUX_PD5A_GMAC_GRX0 _L_(0) /**< GMAC signal line function value: GMAC_GRX0 */ +#define PIO_PD5A_GMAC_GRX0 (_U_(1) << 5) /**< GMAC signal: GMAC_GRX0 */ +#define PIN_PD6A_GMAC_GRX1 _L_(102) /**< GMAC signal: GMAC_GRX1 on PD6 mux A */ +#define MUX_PD6A_GMAC_GRX1 _L_(0) /**< GMAC signal line function value: GMAC_GRX1 */ +#define PIO_PD6A_GMAC_GRX1 (_U_(1) << 6) /**< GMAC signal: GMAC_GRX1 */ +#define PIN_PD11A_GMAC_GRX2 _L_(107) /**< GMAC signal: GMAC_GRX2 on PD11 mux A */ +#define MUX_PD11A_GMAC_GRX2 _L_(0) /**< GMAC signal line function value: GMAC_GRX2 */ +#define PIO_PD11A_GMAC_GRX2 (_U_(1) << 11) /**< GMAC signal: GMAC_GRX2 */ +#define PIN_PD12A_GMAC_GRX3 _L_(108) /**< GMAC signal: GMAC_GRX3 on PD12 mux A */ +#define MUX_PD12A_GMAC_GRX3 _L_(0) /**< GMAC signal line function value: GMAC_GRX3 */ +#define PIO_PD12A_GMAC_GRX3 (_U_(1) << 12) /**< GMAC signal: GMAC_GRX3 */ +#define PIN_PD14A_GMAC_GRXCK _L_(110) /**< GMAC signal: GMAC_GRXCK on PD14 mux A */ +#define MUX_PD14A_GMAC_GRXCK _L_(0) /**< GMAC signal line function value: GMAC_GRXCK */ +#define PIO_PD14A_GMAC_GRXCK (_U_(1) << 14) /**< GMAC signal: GMAC_GRXCK */ +#define PIN_PD4A_GMAC_GRXDV _L_(100) /**< GMAC signal: GMAC_GRXDV on PD4 mux A */ +#define MUX_PD4A_GMAC_GRXDV _L_(0) /**< GMAC signal line function value: GMAC_GRXDV */ +#define PIO_PD4A_GMAC_GRXDV (_U_(1) << 4) /**< GMAC signal: GMAC_GRXDV */ +#define PIN_PD7A_GMAC_GRXER _L_(103) /**< GMAC signal: GMAC_GRXER on PD7 mux A */ +#define MUX_PD7A_GMAC_GRXER _L_(0) /**< GMAC signal line function value: GMAC_GRXER */ +#define PIO_PD7A_GMAC_GRXER (_U_(1) << 7) /**< GMAC signal: GMAC_GRXER */ +#define PIN_PB1B_GMAC_GTSUCOMP _L_(33) /**< GMAC signal: GMAC_GTSUCOMP on PB1 mux B */ +#define MUX_PB1B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB1B_GMAC_GTSUCOMP (_U_(1) << 1) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PB12B_GMAC_GTSUCOMP _L_(44) /**< GMAC signal: GMAC_GTSUCOMP on PB12 mux B */ +#define MUX_PB12B_GMAC_GTSUCOMP _L_(1) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PB12B_GMAC_GTSUCOMP (_U_(1) << 12) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD11C_GMAC_GTSUCOMP _L_(107) /**< GMAC signal: GMAC_GTSUCOMP on PD11 mux C */ +#define MUX_PD11C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD11C_GMAC_GTSUCOMP (_U_(1) << 11) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD20C_GMAC_GTSUCOMP _L_(116) /**< GMAC signal: GMAC_GTSUCOMP on PD20 mux C */ +#define MUX_PD20C_GMAC_GTSUCOMP _L_(2) /**< GMAC signal line function value: GMAC_GTSUCOMP */ +#define PIO_PD20C_GMAC_GTSUCOMP (_U_(1) << 20) /**< GMAC signal: GMAC_GTSUCOMP */ +#define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GMAC_GTX0 on PD2 mux A */ +#define MUX_PD2A_GMAC_GTX0 _L_(0) /**< GMAC signal line function value: GMAC_GTX0 */ +#define PIO_PD2A_GMAC_GTX0 (_U_(1) << 2) /**< GMAC signal: GMAC_GTX0 */ +#define PIN_PD3A_GMAC_GTX1 _L_(99) /**< GMAC signal: GMAC_GTX1 on PD3 mux A */ +#define MUX_PD3A_GMAC_GTX1 _L_(0) /**< GMAC signal line function value: GMAC_GTX1 */ +#define PIO_PD3A_GMAC_GTX1 (_U_(1) << 3) /**< GMAC signal: GMAC_GTX1 */ +#define PIN_PD15A_GMAC_GTX2 _L_(111) /**< GMAC signal: GMAC_GTX2 on PD15 mux A */ +#define MUX_PD15A_GMAC_GTX2 _L_(0) /**< GMAC signal line function value: GMAC_GTX2 */ +#define PIO_PD15A_GMAC_GTX2 (_U_(1) << 15) /**< GMAC signal: GMAC_GTX2 */ +#define PIN_PD16A_GMAC_GTX3 _L_(112) /**< GMAC signal: GMAC_GTX3 on PD16 mux A */ +#define MUX_PD16A_GMAC_GTX3 _L_(0) /**< GMAC signal line function value: GMAC_GTX3 */ +#define PIO_PD16A_GMAC_GTX3 (_U_(1) << 16) /**< GMAC signal: GMAC_GTX3 */ +#define PIN_PD0A_GMAC_GTXCK _L_(96) /**< GMAC signal: GMAC_GTXCK on PD0 mux A */ +#define MUX_PD0A_GMAC_GTXCK _L_(0) /**< GMAC signal line function value: GMAC_GTXCK */ +#define PIO_PD0A_GMAC_GTXCK (_U_(1) << 0) /**< GMAC signal: GMAC_GTXCK */ +#define PIN_PD1A_GMAC_GTXEN _L_(97) /**< GMAC signal: GMAC_GTXEN on PD1 mux A */ +#define MUX_PD1A_GMAC_GTXEN _L_(0) /**< GMAC signal line function value: GMAC_GTXEN */ +#define PIO_PD1A_GMAC_GTXEN (_U_(1) << 1) /**< GMAC signal: GMAC_GTXEN */ +#define PIN_PD17A_GMAC_GTXER _L_(113) /**< GMAC signal: GMAC_GTXER on PD17 mux A */ +#define MUX_PD17A_GMAC_GTXER _L_(0) /**< GMAC signal line function value: GMAC_GTXER */ +#define PIO_PD17A_GMAC_GTXER (_U_(1) << 17) /**< GMAC signal: GMAC_GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIN_PA28C_HSMCI_MCCDA _L_(28) /**< HSMCI signal: HSMCI_MCCDA on PA28 mux C */ +#define MUX_PA28C_HSMCI_MCCDA _L_(2) /**< HSMCI signal line function value: HSMCI_MCCDA */ +#define PIO_PA28C_HSMCI_MCCDA (_U_(1) << 28) /**< HSMCI signal: HSMCI_MCCDA */ +#define PIN_PA25D_HSMCI_MCCK _L_(25) /**< HSMCI signal: HSMCI_MCCK on PA25 mux D */ +#define MUX_PA25D_HSMCI_MCCK _L_(3) /**< HSMCI signal line function value: HSMCI_MCCK */ +#define PIO_PA25D_HSMCI_MCCK (_U_(1) << 25) /**< HSMCI signal: HSMCI_MCCK */ +#define PIN_PA30C_HSMCI_MCDA0 _L_(30) /**< HSMCI signal: HSMCI_MCDA0 on PA30 mux C */ +#define MUX_PA30C_HSMCI_MCDA0 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA0 */ +#define PIO_PA30C_HSMCI_MCDA0 (_U_(1) << 30) /**< HSMCI signal: HSMCI_MCDA0 */ +#define PIN_PA31C_HSMCI_MCDA1 _L_(31) /**< HSMCI signal: HSMCI_MCDA1 on PA31 mux C */ +#define MUX_PA31C_HSMCI_MCDA1 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA1 */ +#define PIO_PA31C_HSMCI_MCDA1 (_U_(1) << 31) /**< HSMCI signal: HSMCI_MCDA1 */ +#define PIN_PA26C_HSMCI_MCDA2 _L_(26) /**< HSMCI signal: HSMCI_MCDA2 on PA26 mux C */ +#define MUX_PA26C_HSMCI_MCDA2 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA2 */ +#define PIO_PA26C_HSMCI_MCDA2 (_U_(1) << 26) /**< HSMCI signal: HSMCI_MCDA2 */ +#define PIN_PA27C_HSMCI_MCDA3 _L_(27) /**< HSMCI signal: HSMCI_MCDA3 on PA27 mux C */ +#define MUX_PA27C_HSMCI_MCDA3 _L_(2) /**< HSMCI signal line function value: HSMCI_MCDA3 */ +#define PIO_PA27C_HSMCI_MCDA3 (_U_(1) << 27) /**< HSMCI signal: HSMCI_MCDA3 */ +/* ========== PIO definition for I2SC0 peripheral ========== */ +#define PIN_PA1D_I2SC0_CK _L_(1) /**< I2SC0 signal: I2SC0_CK on PA1 mux D */ +#define MUX_PA1D_I2SC0_CK _L_(3) /**< I2SC0 signal line function value: I2SC0_CK */ +#define PIO_PA1D_I2SC0_CK (_U_(1) << 1) /**< I2SC0 signal: I2SC0_CK */ +#define PIN_PA16D_I2SC0_DI0 _L_(16) /**< I2SC0 signal: I2SC0_DI0 on PA16 mux D */ +#define MUX_PA16D_I2SC0_DI0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DI0 */ +#define PIO_PA16D_I2SC0_DI0 (_U_(1) << 16) /**< I2SC0 signal: I2SC0_DI0 */ +#define PIN_PA30D_I2SC0_DO0 _L_(30) /**< I2SC0 signal: I2SC0_DO0 on PA30 mux D */ +#define MUX_PA30D_I2SC0_DO0 _L_(3) /**< I2SC0 signal line function value: I2SC0_DO0 */ +#define PIO_PA30D_I2SC0_DO0 (_U_(1) << 30) /**< I2SC0 signal: I2SC0_DO0 */ +#define PIN_PA0D_I2SC0_MCK _L_(0) /**< I2SC0 signal: I2SC0_MCK on PA0 mux D */ +#define MUX_PA0D_I2SC0_MCK _L_(3) /**< I2SC0 signal line function value: I2SC0_MCK */ +#define PIO_PA0D_I2SC0_MCK (_U_(1) << 0) /**< I2SC0 signal: I2SC0_MCK */ +#define PIN_PA15D_I2SC0_WS _L_(15) /**< I2SC0 signal: I2SC0_WS on PA15 mux D */ +#define MUX_PA15D_I2SC0_WS _L_(3) /**< I2SC0 signal line function value: I2SC0_WS */ +#define PIO_PA15D_I2SC0_WS (_U_(1) << 15) /**< I2SC0 signal: I2SC0_WS */ +/* ========== PIO definition for I2SC1 peripheral ========== */ +#define PIN_PA20D_I2SC1_CK _L_(20) /**< I2SC1 signal: I2SC1_CK on PA20 mux D */ +#define MUX_PA20D_I2SC1_CK _L_(3) /**< I2SC1 signal line function value: I2SC1_CK */ +#define PIO_PA20D_I2SC1_CK (_U_(1) << 20) /**< I2SC1 signal: I2SC1_CK */ +#define PIN_PE2C_I2SC1_DI0 _L_(130) /**< I2SC1 signal: I2SC1_DI0 on PE2 mux C */ +#define MUX_PE2C_I2SC1_DI0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DI0 */ +#define PIO_PE2C_I2SC1_DI0 (_U_(1) << 2) /**< I2SC1 signal: I2SC1_DI0 */ +#define PIN_PE1C_I2SC1_DO0 _L_(129) /**< I2SC1 signal: I2SC1_DO0 on PE1 mux C */ +#define MUX_PE1C_I2SC1_DO0 _L_(2) /**< I2SC1 signal line function value: I2SC1_DO0 */ +#define PIO_PE1C_I2SC1_DO0 (_U_(1) << 1) /**< I2SC1 signal: I2SC1_DO0 */ +#define PIN_PA19D_I2SC1_MCK _L_(19) /**< I2SC1 signal: I2SC1_MCK on PA19 mux D */ +#define MUX_PA19D_I2SC1_MCK _L_(3) /**< I2SC1 signal line function value: I2SC1_MCK */ +#define PIO_PA19D_I2SC1_MCK (_U_(1) << 19) /**< I2SC1 signal: I2SC1_MCK */ +#define PIN_PE0C_I2SC1_WS _L_(128) /**< I2SC1 signal: I2SC1_WS on PE0 mux C */ +#define MUX_PE0C_I2SC1_WS _L_(2) /**< I2SC1 signal line function value: I2SC1_WS */ +#define PIO_PE0C_I2SC1_WS (_U_(1) << 0) /**< I2SC1 signal: I2SC1_WS */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIN_PD22D_ISI_D0 _L_(118) /**< ISI signal: ISI_D0 on PD22 mux D */ +#define MUX_PD22D_ISI_D0 _L_(3) /**< ISI signal line function value: ISI_D0 */ +#define PIO_PD22D_ISI_D0 (_U_(1) << 22) /**< ISI signal: ISI_D0 */ +#define PIN_PD21D_ISI_D1 _L_(117) /**< ISI signal: ISI_D1 on PD21 mux D */ +#define MUX_PD21D_ISI_D1 _L_(3) /**< ISI signal line function value: ISI_D1 */ +#define PIO_PD21D_ISI_D1 (_U_(1) << 21) /**< ISI signal: ISI_D1 */ +#define PIN_PB3D_ISI_D2 _L_(35) /**< ISI signal: ISI_D2 on PB3 mux D */ +#define MUX_PB3D_ISI_D2 _L_(3) /**< ISI signal line function value: ISI_D2 */ +#define PIO_PB3D_ISI_D2 (_U_(1) << 3) /**< ISI signal: ISI_D2 */ +#define PIN_PA9B_ISI_D3 _L_(9) /**< ISI signal: ISI_D3 on PA9 mux B */ +#define MUX_PA9B_ISI_D3 _L_(1) /**< ISI signal line function value: ISI_D3 */ +#define PIO_PA9B_ISI_D3 (_U_(1) << 9) /**< ISI signal: ISI_D3 */ +#define PIN_PA5B_ISI_D4 _L_(5) /**< ISI signal: ISI_D4 on PA5 mux B */ +#define MUX_PA5B_ISI_D4 _L_(1) /**< ISI signal line function value: ISI_D4 */ +#define PIO_PA5B_ISI_D4 (_U_(1) << 5) /**< ISI signal: ISI_D4 */ +#define PIN_PD11D_ISI_D5 _L_(107) /**< ISI signal: ISI_D5 on PD11 mux D */ +#define MUX_PD11D_ISI_D5 _L_(3) /**< ISI signal line function value: ISI_D5 */ +#define PIO_PD11D_ISI_D5 (_U_(1) << 11) /**< ISI signal: ISI_D5 */ +#define PIN_PD12D_ISI_D6 _L_(108) /**< ISI signal: ISI_D6 on PD12 mux D */ +#define MUX_PD12D_ISI_D6 _L_(3) /**< ISI signal line function value: ISI_D6 */ +#define PIO_PD12D_ISI_D6 (_U_(1) << 12) /**< ISI signal: ISI_D6 */ +#define PIN_PA27D_ISI_D7 _L_(27) /**< ISI signal: ISI_D7 on PA27 mux D */ +#define MUX_PA27D_ISI_D7 _L_(3) /**< ISI signal line function value: ISI_D7 */ +#define PIO_PA27D_ISI_D7 (_U_(1) << 27) /**< ISI signal: ISI_D7 */ +#define PIN_PD27D_ISI_D8 _L_(123) /**< ISI signal: ISI_D8 on PD27 mux D */ +#define MUX_PD27D_ISI_D8 _L_(3) /**< ISI signal line function value: ISI_D8 */ +#define PIO_PD27D_ISI_D8 (_U_(1) << 27) /**< ISI signal: ISI_D8 */ +#define PIN_PD28D_ISI_D9 _L_(124) /**< ISI signal: ISI_D9 on PD28 mux D */ +#define MUX_PD28D_ISI_D9 _L_(3) /**< ISI signal line function value: ISI_D9 */ +#define PIO_PD28D_ISI_D9 (_U_(1) << 28) /**< ISI signal: ISI_D9 */ +#define PIN_PD30D_ISI_D10 _L_(126) /**< ISI signal: ISI_D10 on PD30 mux D */ +#define MUX_PD30D_ISI_D10 _L_(3) /**< ISI signal line function value: ISI_D10 */ +#define PIO_PD30D_ISI_D10 (_U_(1) << 30) /**< ISI signal: ISI_D10 */ +#define PIN_PD31D_ISI_D11 _L_(127) /**< ISI signal: ISI_D11 on PD31 mux D */ +#define MUX_PD31D_ISI_D11 _L_(3) /**< ISI signal line function value: ISI_D11 */ +#define PIO_PD31D_ISI_D11 (_U_(1) << 31) /**< ISI signal: ISI_D11 */ +#define PIN_PD24D_ISI_HSYNC _L_(120) /**< ISI signal: ISI_HSYNC on PD24 mux D */ +#define MUX_PD24D_ISI_HSYNC _L_(3) /**< ISI signal line function value: ISI_HSYNC */ +#define PIO_PD24D_ISI_HSYNC (_U_(1) << 24) /**< ISI signal: ISI_HSYNC */ +#define PIN_PA24D_ISI_PCK _L_(24) /**< ISI signal: ISI_PCK on PA24 mux D */ +#define MUX_PA24D_ISI_PCK _L_(3) /**< ISI signal line function value: ISI_PCK */ +#define PIO_PA24D_ISI_PCK (_U_(1) << 24) /**< ISI signal: ISI_PCK */ +#define PIN_PD25D_ISI_VSYNC _L_(121) /**< ISI signal: ISI_VSYNC on PD25 mux D */ +#define MUX_PD25D_ISI_VSYNC _L_(3) /**< ISI signal line function value: ISI_VSYNC */ +#define PIO_PD25D_ISI_VSYNC (_U_(1) << 25) /**< ISI signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIN_PB3A_MCAN0_CANRX0 _L_(35) /**< MCAN0 signal: MCAN0_CANRX0 on PB3 mux A */ +#define MUX_PB3A_MCAN0_CANRX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANRX0 */ +#define PIO_PB3A_MCAN0_CANRX0 (_U_(1) << 3) /**< MCAN0 signal: MCAN0_CANRX0 */ +#define PIN_PB2A_MCAN0_CANTX0 _L_(34) /**< MCAN0 signal: MCAN0_CANTX0 on PB2 mux A */ +#define MUX_PB2A_MCAN0_CANTX0 _L_(0) /**< MCAN0 signal line function value: MCAN0_CANTX0 */ +#define PIO_PB2A_MCAN0_CANTX0 (_U_(1) << 2) /**< MCAN0 signal: MCAN0_CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIN_PC12C_MCAN1_CANRX1 _L_(76) /**< MCAN1 signal: MCAN1_CANRX1 on PC12 mux C */ +#define MUX_PC12C_MCAN1_CANRX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANRX1 */ +#define PIO_PC12C_MCAN1_CANRX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANRX1 */ +#define PIN_PC14C_MCAN1_CANTX1 _L_(78) /**< MCAN1 signal: MCAN1_CANTX1 on PC14 mux C */ +#define MUX_PC14C_MCAN1_CANTX1 _L_(2) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PC14C_MCAN1_CANTX1 (_U_(1) << 14) /**< MCAN1 signal: MCAN1_CANTX1 */ +#define PIN_PD12B_MCAN1_CANTX1 _L_(108) /**< MCAN1 signal: MCAN1_CANTX1 on PD12 mux B */ +#define MUX_PD12B_MCAN1_CANTX1 _L_(1) /**< MCAN1 signal line function value: MCAN1_CANTX1 */ +#define PIO_PD12B_MCAN1_CANTX1 (_U_(1) << 12) /**< MCAN1 signal: MCAN1_CANTX1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIN_PA6B_PMC_PCK0 _L_(6) /**< PMC signal: PMC_PCK0 on PA6 mux B */ +#define MUX_PA6B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PA6B_PMC_PCK0 (_U_(1) << 6) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB12D_PMC_PCK0 _L_(44) /**< PMC signal: PMC_PCK0 on PB12 mux D */ +#define MUX_PB12D_PMC_PCK0 _L_(3) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB12D_PMC_PCK0 (_U_(1) << 12) /**< PMC signal: PMC_PCK0 */ +#define PIN_PB13B_PMC_PCK0 _L_(45) /**< PMC signal: PMC_PCK0 on PB13 mux B */ +#define MUX_PB13B_PMC_PCK0 _L_(1) /**< PMC signal line function value: PMC_PCK0 */ +#define PIO_PB13B_PMC_PCK0 (_U_(1) << 13) /**< PMC signal: PMC_PCK0 */ +#define PIN_PA17B_PMC_PCK1 _L_(17) /**< PMC signal: PMC_PCK1 on PA17 mux B */ +#define MUX_PA17B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA17B_PMC_PCK1 (_U_(1) << 17) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA21B_PMC_PCK1 _L_(21) /**< PMC signal: PMC_PCK1 on PA21 mux B */ +#define MUX_PA21B_PMC_PCK1 _L_(1) /**< PMC signal line function value: PMC_PCK1 */ +#define PIO_PA21B_PMC_PCK1 (_U_(1) << 21) /**< PMC signal: PMC_PCK1 */ +#define PIN_PA3C_PMC_PCK2 _L_(3) /**< PMC signal: PMC_PCK2 on PA3 mux C */ +#define MUX_PA3C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA3C_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA18B_PMC_PCK2 _L_(18) /**< PMC signal: PMC_PCK2 on PA18 mux B */ +#define MUX_PA18B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA18B_PMC_PCK2 (_U_(1) << 18) /**< PMC signal: PMC_PCK2 */ +#define PIN_PA31B_PMC_PCK2 _L_(31) /**< PMC signal: PMC_PCK2 on PA31 mux B */ +#define MUX_PA31B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PA31B_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB3B_PMC_PCK2 _L_(35) /**< PMC signal: PMC_PCK2 on PB3 mux B */ +#define MUX_PB3B_PMC_PCK2 _L_(1) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PB3B_PMC_PCK2 (_U_(1) << 3) /**< PMC signal: PMC_PCK2 */ +#define PIN_PD31C_PMC_PCK2 _L_(127) /**< PMC signal: PMC_PCK2 on PD31 mux C */ +#define MUX_PD31C_PMC_PCK2 _L_(2) /**< PMC signal line function value: PMC_PCK2 */ +#define PIO_PD31C_PMC_PCK2 (_U_(1) << 31) /**< PMC signal: PMC_PCK2 */ +#define PIN_PB9X1_PMC_XIN _L_(41) /**< PMC signal: PMC_XIN on PB9 mux X1 */ +#define PIO_PB9X1_PMC_XIN (_U_(1) << 9) /**< PMC signal: PMC_XIN */ +#define PIN_PA7X1_PMC_XIN32 _L_(7) /**< PMC signal: PMC_XIN32 on PA7 mux X1 */ +#define PIO_PA7X1_PMC_XIN32 (_U_(1) << 7) /**< PMC signal: PMC_XIN32 */ +#define PIN_PB8X1_PMC_XOUT _L_(40) /**< PMC signal: PMC_XOUT on PB8 mux X1 */ +#define PIO_PB8X1_PMC_XOUT (_U_(1) << 8) /**< PMC signal: PMC_XOUT */ +#define PIN_PA8X1_PMC_XOUT32 _L_(8) /**< PMC signal: PMC_XOUT32 on PA8 mux X1 */ +#define PIO_PA8X1_PMC_XOUT32 (_U_(1) << 8) /**< PMC signal: PMC_XOUT32 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIN_PA10B_PWM0_PWMEXTRG0 _L_(10) /**< PWM0 signal: PWM0_PWMEXTRG0 on PA10 mux B */ +#define MUX_PA10B_PWM0_PWMEXTRG0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG0 */ +#define PIO_PA10B_PWM0_PWMEXTRG0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWMEXTRG0 */ +#define PIN_PA22B_PWM0_PWMEXTRG1 _L_(22) /**< PWM0 signal: PWM0_PWMEXTRG1 on PA22 mux B */ +#define MUX_PA22B_PWM0_PWMEXTRG1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMEXTRG1 */ +#define PIO_PA22B_PWM0_PWMEXTRG1 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMEXTRG1 */ +#define PIN_PA9C_PWM0_PWMFI0 _L_(9) /**< PWM0 signal: PWM0_PWMFI0 on PA9 mux C */ +#define MUX_PA9C_PWM0_PWMFI0 _L_(2) /**< PWM0 signal line function value: PWM0_PWMFI0 */ +#define PIO_PA9C_PWM0_PWMFI0 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI0 */ +#define PIN_PD8B_PWM0_PWMFI1 _L_(104) /**< PWM0 signal: PWM0_PWMFI1 on PD8 mux B */ +#define MUX_PD8B_PWM0_PWMFI1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI1 */ +#define PIO_PD8B_PWM0_PWMFI1 (_U_(1) << 8) /**< PWM0 signal: PWM0_PWMFI1 */ +#define PIN_PD9B_PWM0_PWMFI2 _L_(105) /**< PWM0 signal: PWM0_PWMFI2 on PD9 mux B */ +#define MUX_PD9B_PWM0_PWMFI2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMFI2 */ +#define PIO_PD9B_PWM0_PWMFI2 (_U_(1) << 9) /**< PWM0 signal: PWM0_PWMFI2 */ +#define PIN_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal: PWM0_PWMH0 on PA0 mux A */ +#define MUX_PA0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA11B_PWM0_PWMH0 _L_(11) /**< PWM0 signal: PWM0_PWMH0 on PA11 mux B */ +#define MUX_PA11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA23B_PWM0_PWMH0 _L_(23) /**< PWM0 signal: PWM0_PWMH0 on PA23 mux B */ +#define MUX_PA23B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PA23B_PWM0_PWMH0 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PB0A_PWM0_PWMH0 _L_(32) /**< PWM0 signal: PWM0_PWMH0 on PB0 mux A */ +#define MUX_PB0A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PB0A_PWM0_PWMH0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD11B_PWM0_PWMH0 _L_(107) /**< PWM0 signal: PWM0_PWMH0 on PD11 mux B */ +#define MUX_PD11B_PWM0_PWMH0 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD11B_PWM0_PWMH0 (_U_(1) << 11) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PD20A_PWM0_PWMH0 _L_(116) /**< PWM0 signal: PWM0_PWMH0 on PD20 mux A */ +#define MUX_PD20A_PWM0_PWMH0 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH0 */ +#define PIO_PD20A_PWM0_PWMH0 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWMH0 */ +#define PIN_PA2A_PWM0_PWMH1 _L_(2) /**< PWM0 signal: PWM0_PWMH1 on PA2 mux A */ +#define MUX_PA2A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA2A_PWM0_PWMH1 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA12B_PWM0_PWMH1 _L_(12) /**< PWM0 signal: PWM0_PWMH1 on PA12 mux B */ +#define MUX_PA12B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA12B_PWM0_PWMH1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA24B_PWM0_PWMH1 _L_(24) /**< PWM0 signal: PWM0_PWMH1 on PA24 mux B */ +#define MUX_PA24B_PWM0_PWMH1 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PA24B_PWM0_PWMH1 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PB1A_PWM0_PWMH1 _L_(33) /**< PWM0 signal: PWM0_PWMH1 on PB1 mux A */ +#define MUX_PB1A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PB1A_PWM0_PWMH1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PD21A_PWM0_PWMH1 _L_(117) /**< PWM0 signal: PWM0_PWMH1 on PD21 mux A */ +#define MUX_PD21A_PWM0_PWMH1 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH1 */ +#define PIO_PD21A_PWM0_PWMH1 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH1 */ +#define PIN_PA13B_PWM0_PWMH2 _L_(13) /**< PWM0 signal: PWM0_PWMH2 on PA13 mux B */ +#define MUX_PA13B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA13B_PWM0_PWMH2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA25B_PWM0_PWMH2 _L_(25) /**< PWM0 signal: PWM0_PWMH2 on PA25 mux B */ +#define MUX_PA25B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PA25B_PWM0_PWMH2 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PB4B_PWM0_PWMH2 _L_(36) /**< PWM0 signal: PWM0_PWMH2 on PB4 mux B */ +#define MUX_PB4B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PB4B_PWM0_PWMH2 (_U_(1) << 4) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PC19B_PWM0_PWMH2 _L_(83) /**< PWM0 signal: PWM0_PWMH2 on PC19 mux B */ +#define MUX_PC19B_PWM0_PWMH2 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PC19B_PWM0_PWMH2 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PD22A_PWM0_PWMH2 _L_(118) /**< PWM0 signal: PWM0_PWMH2 on PD22 mux A */ +#define MUX_PD22A_PWM0_PWMH2 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH2 */ +#define PIO_PD22A_PWM0_PWMH2 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWMH2 */ +#define PIN_PA7B_PWM0_PWMH3 _L_(7) /**< PWM0 signal: PWM0_PWMH3 on PA7 mux B */ +#define MUX_PA7B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA7B_PWM0_PWMH3 (_U_(1) << 7) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA14B_PWM0_PWMH3 _L_(14) /**< PWM0 signal: PWM0_PWMH3 on PA14 mux B */ +#define MUX_PA14B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA14B_PWM0_PWMH3 (_U_(1) << 14) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA17C_PWM0_PWMH3 _L_(17) /**< PWM0 signal: PWM0_PWMH3 on PA17 mux C */ +#define MUX_PA17C_PWM0_PWMH3 _L_(2) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PA17C_PWM0_PWMH3 (_U_(1) << 17) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC13B_PWM0_PWMH3 _L_(77) /**< PWM0 signal: PWM0_PWMH3 on PC13 mux B */ +#define MUX_PC13B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC13B_PWM0_PWMH3 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PC21B_PWM0_PWMH3 _L_(85) /**< PWM0 signal: PWM0_PWMH3 on PC21 mux B */ +#define MUX_PC21B_PWM0_PWMH3 _L_(1) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PC21B_PWM0_PWMH3 (_U_(1) << 21) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PD23A_PWM0_PWMH3 _L_(119) /**< PWM0 signal: PWM0_PWMH3 on PD23 mux A */ +#define MUX_PD23A_PWM0_PWMH3 _L_(0) /**< PWM0 signal line function value: PWM0_PWMH3 */ +#define PIO_PD23A_PWM0_PWMH3 (_U_(1) << 23) /**< PWM0 signal: PWM0_PWMH3 */ +#define PIN_PA1A_PWM0_PWML0 _L_(1) /**< PWM0 signal: PWM0_PWML0 on PA1 mux A */ +#define MUX_PA1A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA1A_PWM0_PWML0 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA19B_PWM0_PWML0 _L_(19) /**< PWM0 signal: PWM0_PWML0 on PA19 mux B */ +#define MUX_PA19B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PA19B_PWM0_PWML0 (_U_(1) << 19) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PB5B_PWM0_PWML0 _L_(37) /**< PWM0 signal: PWM0_PWML0 on PB5 mux B */ +#define MUX_PB5B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PB5B_PWM0_PWML0 (_U_(1) << 5) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PC0B_PWM0_PWML0 _L_(64) /**< PWM0 signal: PWM0_PWML0 on PC0 mux B */ +#define MUX_PC0B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PC0B_PWM0_PWML0 (_U_(1) << 0) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD10B_PWM0_PWML0 _L_(106) /**< PWM0 signal: PWM0_PWML0 on PD10 mux B */ +#define MUX_PD10B_PWM0_PWML0 _L_(1) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD10B_PWM0_PWML0 (_U_(1) << 10) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PD24A_PWM0_PWML0 _L_(120) /**< PWM0 signal: PWM0_PWML0 on PD24 mux A */ +#define MUX_PD24A_PWM0_PWML0 _L_(0) /**< PWM0 signal line function value: PWM0_PWML0 */ +#define PIO_PD24A_PWM0_PWML0 (_U_(1) << 24) /**< PWM0 signal: PWM0_PWML0 */ +#define PIN_PA20B_PWM0_PWML1 _L_(20) /**< PWM0 signal: PWM0_PWML1 on PA20 mux B */ +#define MUX_PA20B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PA20B_PWM0_PWML1 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PB12A_PWM0_PWML1 _L_(44) /**< PWM0 signal: PWM0_PWML1 on PB12 mux A */ +#define MUX_PB12A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PB12A_PWM0_PWML1 (_U_(1) << 12) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC1B_PWM0_PWML1 _L_(65) /**< PWM0 signal: PWM0_PWML1 on PC1 mux B */ +#define MUX_PC1B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC1B_PWM0_PWML1 (_U_(1) << 1) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PC18B_PWM0_PWML1 _L_(82) /**< PWM0 signal: PWM0_PWML1 on PC18 mux B */ +#define MUX_PC18B_PWM0_PWML1 _L_(1) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PC18B_PWM0_PWML1 (_U_(1) << 18) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PD25A_PWM0_PWML1 _L_(121) /**< PWM0 signal: PWM0_PWML1 on PD25 mux A */ +#define MUX_PD25A_PWM0_PWML1 _L_(0) /**< PWM0 signal line function value: PWM0_PWML1 */ +#define PIO_PD25A_PWM0_PWML1 (_U_(1) << 25) /**< PWM0 signal: PWM0_PWML1 */ +#define PIN_PA16C_PWM0_PWML2 _L_(16) /**< PWM0 signal: PWM0_PWML2 on PA16 mux C */ +#define MUX_PA16C_PWM0_PWML2 _L_(2) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA16C_PWM0_PWML2 (_U_(1) << 16) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA30A_PWM0_PWML2 _L_(30) /**< PWM0 signal: PWM0_PWML2 on PA30 mux A */ +#define MUX_PA30A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PA30A_PWM0_PWML2 (_U_(1) << 30) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PB13A_PWM0_PWML2 _L_(45) /**< PWM0 signal: PWM0_PWML2 on PB13 mux A */ +#define MUX_PB13A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PB13A_PWM0_PWML2 (_U_(1) << 13) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC2B_PWM0_PWML2 _L_(66) /**< PWM0 signal: PWM0_PWML2 on PC2 mux B */ +#define MUX_PC2B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC2B_PWM0_PWML2 (_U_(1) << 2) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PC20B_PWM0_PWML2 _L_(84) /**< PWM0 signal: PWM0_PWML2 on PC20 mux B */ +#define MUX_PC20B_PWM0_PWML2 _L_(1) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PC20B_PWM0_PWML2 (_U_(1) << 20) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PD26A_PWM0_PWML2 _L_(122) /**< PWM0 signal: PWM0_PWML2 on PD26 mux A */ +#define MUX_PD26A_PWM0_PWML2 _L_(0) /**< PWM0 signal line function value: PWM0_PWML2 */ +#define PIO_PD26A_PWM0_PWML2 (_U_(1) << 26) /**< PWM0 signal: PWM0_PWML2 */ +#define PIN_PA15C_PWM0_PWML3 _L_(15) /**< PWM0 signal: PWM0_PWML3 on PA15 mux C */ +#define MUX_PA15C_PWM0_PWML3 _L_(2) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PA15C_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC3B_PWM0_PWML3 _L_(67) /**< PWM0 signal: PWM0_PWML3 on PC3 mux B */ +#define MUX_PC3B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC3B_PWM0_PWML3 (_U_(1) << 3) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC15B_PWM0_PWML3 _L_(79) /**< PWM0 signal: PWM0_PWML3 on PC15 mux B */ +#define MUX_PC15B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC15B_PWM0_PWML3 (_U_(1) << 15) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PC22B_PWM0_PWML3 _L_(86) /**< PWM0 signal: PWM0_PWML3 on PC22 mux B */ +#define MUX_PC22B_PWM0_PWML3 _L_(1) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PC22B_PWM0_PWML3 (_U_(1) << 22) /**< PWM0 signal: PWM0_PWML3 */ +#define PIN_PD27A_PWM0_PWML3 _L_(123) /**< PWM0 signal: PWM0_PWML3 on PD27 mux A */ +#define MUX_PD27A_PWM0_PWML3 _L_(0) /**< PWM0 signal line function value: PWM0_PWML3 */ +#define PIO_PD27A_PWM0_PWML3 (_U_(1) << 27) /**< PWM0 signal: PWM0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIN_PA30B_PWM1_PWMEXTRG0 _L_(30) /**< PWM1 signal: PWM1_PWMEXTRG0 on PA30 mux B */ +#define MUX_PA30B_PWM1_PWMEXTRG0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMEXTRG0 */ +#define PIO_PA30B_PWM1_PWMEXTRG0 (_U_(1) << 30) /**< PWM1 signal: PWM1_PWMEXTRG0 */ +#define PIN_PA18A_PWM1_PWMEXTRG1 _L_(18) /**< PWM1 signal: PWM1_PWMEXTRG1 on PA18 mux A */ +#define MUX_PA18A_PWM1_PWMEXTRG1 _L_(0) /**< PWM1 signal line function value: PWM1_PWMEXTRG1 */ +#define PIO_PA18A_PWM1_PWMEXTRG1 (_U_(1) << 18) /**< PWM1 signal: PWM1_PWMEXTRG1 */ +#define PIN_PA21C_PWM1_PWMFI0 _L_(21) /**< PWM1 signal: PWM1_PWMFI0 on PA21 mux C */ +#define MUX_PA21C_PWM1_PWMFI0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMFI0 */ +#define PIO_PA21C_PWM1_PWMFI0 (_U_(1) << 21) /**< PWM1 signal: PWM1_PWMFI0 */ +#define PIN_PA26D_PWM1_PWMFI1 _L_(26) /**< PWM1 signal: PWM1_PWMFI1 on PA26 mux D */ +#define MUX_PA26D_PWM1_PWMFI1 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI1 */ +#define PIO_PA26D_PWM1_PWMFI1 (_U_(1) << 26) /**< PWM1 signal: PWM1_PWMFI1 */ +#define PIN_PA28D_PWM1_PWMFI2 _L_(28) /**< PWM1 signal: PWM1_PWMFI2 on PA28 mux D */ +#define MUX_PA28D_PWM1_PWMFI2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMFI2 */ +#define PIO_PA28D_PWM1_PWMFI2 (_U_(1) << 28) /**< PWM1 signal: PWM1_PWMFI2 */ +#define PIN_PA12C_PWM1_PWMH0 _L_(12) /**< PWM1 signal: PWM1_PWMH0 on PA12 mux C */ +#define MUX_PA12C_PWM1_PWMH0 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PA12C_PWM1_PWMH0 (_U_(1) << 12) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PD1B_PWM1_PWMH0 _L_(97) /**< PWM1 signal: PWM1_PWMH0 on PD1 mux B */ +#define MUX_PD1B_PWM1_PWMH0 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH0 */ +#define PIO_PD1B_PWM1_PWMH0 (_U_(1) << 1) /**< PWM1 signal: PWM1_PWMH0 */ +#define PIN_PA14C_PWM1_PWMH1 _L_(14) /**< PWM1 signal: PWM1_PWMH1 on PA14 mux C */ +#define MUX_PA14C_PWM1_PWMH1 _L_(2) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PA14C_PWM1_PWMH1 (_U_(1) << 14) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PD3B_PWM1_PWMH1 _L_(99) /**< PWM1 signal: PWM1_PWMH1 on PD3 mux B */ +#define MUX_PD3B_PWM1_PWMH1 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH1 */ +#define PIO_PD3B_PWM1_PWMH1 (_U_(1) << 3) /**< PWM1 signal: PWM1_PWMH1 */ +#define PIN_PA31D_PWM1_PWMH2 _L_(31) /**< PWM1 signal: PWM1_PWMH2 on PA31 mux D */ +#define MUX_PA31D_PWM1_PWMH2 _L_(3) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PA31D_PWM1_PWMH2 (_U_(1) << 31) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PD5B_PWM1_PWMH2 _L_(101) /**< PWM1 signal: PWM1_PWMH2 on PD5 mux B */ +#define MUX_PD5B_PWM1_PWMH2 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH2 */ +#define PIO_PD5B_PWM1_PWMH2 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWMH2 */ +#define PIN_PA8A_PWM1_PWMH3 _L_(8) /**< PWM1 signal: PWM1_PWMH3 on PA8 mux A */ +#define MUX_PA8A_PWM1_PWMH3 _L_(0) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PA8A_PWM1_PWMH3 (_U_(1) << 8) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PD7B_PWM1_PWMH3 _L_(103) /**< PWM1 signal: PWM1_PWMH3 on PD7 mux B */ +#define MUX_PD7B_PWM1_PWMH3 _L_(1) /**< PWM1 signal line function value: PWM1_PWMH3 */ +#define PIO_PD7B_PWM1_PWMH3 (_U_(1) << 7) /**< PWM1 signal: PWM1_PWMH3 */ +#define PIN_PA11C_PWM1_PWML0 _L_(11) /**< PWM1 signal: PWM1_PWML0 on PA11 mux C */ +#define MUX_PA11C_PWM1_PWML0 _L_(2) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PA11C_PWM1_PWML0 (_U_(1) << 11) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PD0B_PWM1_PWML0 _L_(96) /**< PWM1 signal: PWM1_PWML0 on PD0 mux B */ +#define MUX_PD0B_PWM1_PWML0 _L_(1) /**< PWM1 signal line function value: PWM1_PWML0 */ +#define PIO_PD0B_PWM1_PWML0 (_U_(1) << 0) /**< PWM1 signal: PWM1_PWML0 */ +#define PIN_PA13C_PWM1_PWML1 _L_(13) /**< PWM1 signal: PWM1_PWML1 on PA13 mux C */ +#define MUX_PA13C_PWM1_PWML1 _L_(2) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PA13C_PWM1_PWML1 (_U_(1) << 13) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWM1_PWML1 on PD2 mux B */ +#define MUX_PD2B_PWM1_PWML1 _L_(1) /**< PWM1 signal line function value: PWM1_PWML1 */ +#define PIO_PD2B_PWM1_PWML1 (_U_(1) << 2) /**< PWM1 signal: PWM1_PWML1 */ +#define PIN_PA23D_PWM1_PWML2 _L_(23) /**< PWM1 signal: PWM1_PWML2 on PA23 mux D */ +#define MUX_PA23D_PWM1_PWML2 _L_(3) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PA23D_PWM1_PWML2 (_U_(1) << 23) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PD4B_PWM1_PWML2 _L_(100) /**< PWM1 signal: PWM1_PWML2 on PD4 mux B */ +#define MUX_PD4B_PWM1_PWML2 _L_(1) /**< PWM1 signal line function value: PWM1_PWML2 */ +#define PIO_PD4B_PWM1_PWML2 (_U_(1) << 4) /**< PWM1 signal: PWM1_PWML2 */ +#define PIN_PA5A_PWM1_PWML3 _L_(5) /**< PWM1 signal: PWM1_PWML3 on PA5 mux A */ +#define MUX_PA5A_PWM1_PWML3 _L_(0) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PA5A_PWM1_PWML3 (_U_(1) << 5) /**< PWM1 signal: PWM1_PWML3 */ +#define PIN_PD6B_PWM1_PWML3 _L_(102) /**< PWM1 signal: PWM1_PWML3 on PD6 mux B */ +#define MUX_PD6B_PWM1_PWML3 _L_(1) /**< PWM1 signal line function value: PWM1_PWML3 */ +#define PIO_PD6B_PWM1_PWML3 (_U_(1) << 6) /**< PWM1 signal: PWM1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIN_PA11A_QSPI_QCS _L_(11) /**< QSPI signal: QSPI_QCS on PA11 mux A */ +#define MUX_PA11A_QSPI_QCS _L_(0) /**< QSPI signal line function value: QSPI_QCS */ +#define PIO_PA11A_QSPI_QCS (_U_(1) << 11) /**< QSPI signal: QSPI_QCS */ +#define PIN_PA13A_QSPI_QIO0 _L_(13) /**< QSPI signal: QSPI_QIO0 on PA13 mux A */ +#define MUX_PA13A_QSPI_QIO0 _L_(0) /**< QSPI signal line function value: QSPI_QIO0 */ +#define PIO_PA13A_QSPI_QIO0 (_U_(1) << 13) /**< QSPI signal: QSPI_QIO0 */ +#define PIN_PA12A_QSPI_QIO1 _L_(12) /**< QSPI signal: QSPI_QIO1 on PA12 mux A */ +#define MUX_PA12A_QSPI_QIO1 _L_(0) /**< QSPI signal line function value: QSPI_QIO1 */ +#define PIO_PA12A_QSPI_QIO1 (_U_(1) << 12) /**< QSPI signal: QSPI_QIO1 */ +#define PIN_PA17A_QSPI_QIO2 _L_(17) /**< QSPI signal: QSPI_QIO2 on PA17 mux A */ +#define MUX_PA17A_QSPI_QIO2 _L_(0) /**< QSPI signal line function value: QSPI_QIO2 */ +#define PIO_PA17A_QSPI_QIO2 (_U_(1) << 17) /**< QSPI signal: QSPI_QIO2 */ +#define PIN_PD31A_QSPI_QIO3 _L_(127) /**< QSPI signal: QSPI_QIO3 on PD31 mux A */ +#define MUX_PD31A_QSPI_QIO3 _L_(0) /**< QSPI signal line function value: QSPI_QIO3 */ +#define PIO_PD31A_QSPI_QIO3 (_U_(1) << 31) /**< QSPI signal: QSPI_QIO3 */ +#define PIN_PA14A_QSPI_QSCK _L_(14) /**< QSPI signal: QSPI_QSCK on PA14 mux A */ +#define MUX_PA14A_QSPI_QSCK _L_(0) /**< QSPI signal line function value: QSPI_QSCK */ +#define PIO_PA14A_QSPI_QSCK (_U_(1) << 14) /**< QSPI signal: QSPI_QSCK */ +/* ========== PIO definition for RTC peripheral ========== */ +#define PIN_PB0X1_RTC_RTCOUT0 _L_(32) /**< RTC signal: RTC_RTCOUT0 on PB0 mux X1 */ +#define PIO_PB0X1_RTC_RTCOUT0 (_U_(1) << 0) /**< RTC signal: RTC_RTCOUT0 */ +#define PIN_PB1X1_RTC_RTCOUT1 _L_(33) /**< RTC signal: RTC_RTCOUT1 on PB1 mux X1 */ +#define PIO_PB1X1_RTC_RTCOUT1 (_U_(1) << 1) /**< RTC signal: RTC_RTCOUT1 */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIN_PD20B_SPI0_MISO _L_(116) /**< SPI0 signal: SPI0_MISO on PD20 mux B */ +#define MUX_PD20B_SPI0_MISO _L_(1) /**< SPI0 signal line function value: SPI0_MISO */ +#define PIO_PD20B_SPI0_MISO (_U_(1) << 20) /**< SPI0 signal: SPI0_MISO */ +#define PIN_PD21B_SPI0_MOSI _L_(117) /**< SPI0 signal: SPI0_MOSI on PD21 mux B */ +#define MUX_PD21B_SPI0_MOSI _L_(1) /**< SPI0 signal line function value: SPI0_MOSI */ +#define PIO_PD21B_SPI0_MOSI (_U_(1) << 21) /**< SPI0 signal: SPI0_MOSI */ +#define PIN_PB2D_SPI0_NPCS0 _L_(34) /**< SPI0 signal: SPI0_NPCS0 on PB2 mux D */ +#define MUX_PB2D_SPI0_NPCS0 _L_(3) /**< SPI0 signal line function value: SPI0_NPCS0 */ +#define PIO_PB2D_SPI0_NPCS0 (_U_(1) << 2) /**< SPI0 signal: SPI0_NPCS0 */ +#define PIN_PA31A_SPI0_NPCS1 _L_(31) /**< SPI0 signal: SPI0_NPCS1 on PA31 mux A */ +#define MUX_PA31A_SPI0_NPCS1 _L_(0) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PA31A_SPI0_NPCS1 (_U_(1) << 31) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD25B_SPI0_NPCS1 _L_(121) /**< SPI0 signal: SPI0_NPCS1 on PD25 mux B */ +#define MUX_PD25B_SPI0_NPCS1 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (_U_(1) << 25) /**< SPI0 signal: SPI0_NPCS1 */ +#define PIN_PD12C_SPI0_NPCS2 _L_(108) /**< SPI0 signal: SPI0_NPCS2 on PD12 mux C */ +#define MUX_PD12C_SPI0_NPCS2 _L_(2) /**< SPI0 signal line function value: SPI0_NPCS2 */ +#define PIO_PD12C_SPI0_NPCS2 (_U_(1) << 12) /**< SPI0 signal: SPI0_NPCS2 */ +#define PIN_PD27B_SPI0_NPCS3 _L_(123) /**< SPI0 signal: SPI0_NPCS3 on PD27 mux B */ +#define MUX_PD27B_SPI0_NPCS3 _L_(1) /**< SPI0 signal line function value: SPI0_NPCS3 */ +#define PIO_PD27B_SPI0_NPCS3 (_U_(1) << 27) /**< SPI0 signal: SPI0_NPCS3 */ +#define PIN_PD22B_SPI0_SPCK _L_(118) /**< SPI0 signal: SPI0_SPCK on PD22 mux B */ +#define MUX_PD22B_SPI0_SPCK _L_(1) /**< SPI0 signal line function value: SPI0_SPCK */ +#define PIO_PD22B_SPI0_SPCK (_U_(1) << 22) /**< SPI0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIN_PC26C_SPI1_MISO _L_(90) /**< SPI1 signal: SPI1_MISO on PC26 mux C */ +#define MUX_PC26C_SPI1_MISO _L_(2) /**< SPI1 signal line function value: SPI1_MISO */ +#define PIO_PC26C_SPI1_MISO (_U_(1) << 26) /**< SPI1 signal: SPI1_MISO */ +#define PIN_PC27C_SPI1_MOSI _L_(91) /**< SPI1 signal: SPI1_MOSI on PC27 mux C */ +#define MUX_PC27C_SPI1_MOSI _L_(2) /**< SPI1 signal line function value: SPI1_MOSI */ +#define PIO_PC27C_SPI1_MOSI (_U_(1) << 27) /**< SPI1 signal: SPI1_MOSI */ +#define PIN_PC25C_SPI1_NPCS0 _L_(89) /**< SPI1 signal: SPI1_NPCS0 on PC25 mux C */ +#define MUX_PC25C_SPI1_NPCS0 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS0 */ +#define PIO_PC25C_SPI1_NPCS0 (_U_(1) << 25) /**< SPI1 signal: SPI1_NPCS0 */ +#define PIN_PC28C_SPI1_NPCS1 _L_(92) /**< SPI1 signal: SPI1_NPCS1 on PC28 mux C */ +#define MUX_PC28C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PC28C_SPI1_NPCS1 (_U_(1) << 28) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PD0C_SPI1_NPCS1 _L_(96) /**< SPI1 signal: SPI1_NPCS1 on PD0 mux C */ +#define MUX_PD0C_SPI1_NPCS1 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (_U_(1) << 0) /**< SPI1 signal: SPI1_NPCS1 */ +#define PIN_PC29C_SPI1_NPCS2 _L_(93) /**< SPI1 signal: SPI1_NPCS2 on PC29 mux C */ +#define MUX_PC29C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PC29C_SPI1_NPCS2 (_U_(1) << 29) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PD1C_SPI1_NPCS2 _L_(97) /**< SPI1 signal: SPI1_NPCS2 on PD1 mux C */ +#define MUX_PD1C_SPI1_NPCS2 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (_U_(1) << 1) /**< SPI1 signal: SPI1_NPCS2 */ +#define PIN_PC30C_SPI1_NPCS3 _L_(94) /**< SPI1 signal: SPI1_NPCS3 on PC30 mux C */ +#define MUX_PC30C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PC30C_SPI1_NPCS3 (_U_(1) << 30) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PD2C_SPI1_NPCS3 _L_(98) /**< SPI1 signal: SPI1_NPCS3 on PD2 mux C */ +#define MUX_PD2C_SPI1_NPCS3 _L_(2) /**< SPI1 signal line function value: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (_U_(1) << 2) /**< SPI1 signal: SPI1_NPCS3 */ +#define PIN_PC24C_SPI1_SPCK _L_(88) /**< SPI1 signal: SPI1_SPCK on PC24 mux C */ +#define MUX_PC24C_SPI1_SPCK _L_(2) /**< SPI1 signal line function value: SPI1_SPCK */ +#define PIO_PC24C_SPI1_SPCK (_U_(1) << 24) /**< SPI1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIN_PA10C_SSC_RD _L_(10) /**< SSC signal: SSC_RD on PA10 mux C */ +#define MUX_PA10C_SSC_RD _L_(2) /**< SSC signal line function value: SSC_RD */ +#define PIO_PA10C_SSC_RD (_U_(1) << 10) /**< SSC signal: SSC_RD */ +#define PIN_PD24B_SSC_RF _L_(120) /**< SSC signal: SSC_RF on PD24 mux B */ +#define MUX_PD24B_SSC_RF _L_(1) /**< SSC signal line function value: SSC_RF */ +#define PIO_PD24B_SSC_RF (_U_(1) << 24) /**< SSC signal: SSC_RF */ +#define PIN_PA22A_SSC_RK _L_(22) /**< SSC signal: SSC_RK on PA22 mux A */ +#define MUX_PA22A_SSC_RK _L_(0) /**< SSC signal line function value: SSC_RK */ +#define PIO_PA22A_SSC_RK (_U_(1) << 22) /**< SSC signal: SSC_RK */ +#define PIN_PB5D_SSC_TD _L_(37) /**< SSC signal: SSC_TD on PB5 mux D */ +#define MUX_PB5D_SSC_TD _L_(3) /**< SSC signal line function value: SSC_TD */ +#define PIO_PB5D_SSC_TD (_U_(1) << 5) /**< SSC signal: SSC_TD */ +#define PIN_PD10C_SSC_TD _L_(106) /**< SSC signal: SSC_TD on PD10 mux C */ +#define MUX_PD10C_SSC_TD _L_(2) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD10C_SSC_TD (_U_(1) << 10) /**< SSC signal: SSC_TD */ +#define PIN_PD26B_SSC_TD _L_(122) /**< SSC signal: SSC_TD on PD26 mux B */ +#define MUX_PD26B_SSC_TD _L_(1) /**< SSC signal line function value: SSC_TD */ +#define PIO_PD26B_SSC_TD (_U_(1) << 26) /**< SSC signal: SSC_TD */ +#define PIN_PB0D_SSC_TF _L_(32) /**< SSC signal: SSC_TF on PB0 mux D */ +#define MUX_PB0D_SSC_TF _L_(3) /**< SSC signal line function value: SSC_TF */ +#define PIO_PB0D_SSC_TF (_U_(1) << 0) /**< SSC signal: SSC_TF */ +#define PIN_PB1D_SSC_TK _L_(33) /**< SSC signal: SSC_TK on PB1 mux D */ +#define MUX_PB1D_SSC_TK _L_(3) /**< SSC signal line function value: SSC_TK */ +#define PIO_PB1D_SSC_TK (_U_(1) << 1) /**< SSC signal: SSC_TK */ +/* ========== PIO definition for SUPC peripheral ========== */ +#define PIN_PA0X1_SUPC_WKUP0 _L_(0) /**< SUPC signal: SUPC_WKUP0 on PA0 mux X1 */ +#define PIO_PA0X1_SUPC_WKUP0 (_U_(1) << 0) /**< SUPC signal: SUPC_WKUP0 */ +#define PIN_PA1X1_SUPC_WKUP1 _L_(1) /**< SUPC signal: SUPC_WKUP1 on PA1 mux X1 */ +#define PIO_PA1X1_SUPC_WKUP1 (_U_(1) << 1) /**< SUPC signal: SUPC_WKUP1 */ +#define PIN_PA2X1_SUPC_WKUP2 _L_(2) /**< SUPC signal: SUPC_WKUP2 on PA2 mux X1 */ +#define PIO_PA2X1_SUPC_WKUP2 (_U_(1) << 2) /**< SUPC signal: SUPC_WKUP2 */ +#define PIN_PA4X1_SUPC_WKUP3 _L_(4) /**< SUPC signal: SUPC_WKUP3 on PA4 mux X1 */ +#define PIO_PA4X1_SUPC_WKUP3 (_U_(1) << 4) /**< SUPC signal: SUPC_WKUP3 */ +#define PIN_PA5X1_SUPC_WKUP4 _L_(5) /**< SUPC signal: SUPC_WKUP4 on PA5 mux X1 */ +#define PIO_PA5X1_SUPC_WKUP4 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP4 */ +#define PIN_PD28X1_SUPC_WKUP5 _L_(124) /**< SUPC signal: SUPC_WKUP5 on PD28 mux X1 */ +#define PIO_PD28X1_SUPC_WKUP5 (_U_(1) << 28) /**< SUPC signal: SUPC_WKUP5 */ +#define PIN_PA9X1_SUPC_WKUP6 _L_(9) /**< SUPC signal: SUPC_WKUP6 on PA9 mux X1 */ +#define PIO_PA9X1_SUPC_WKUP6 (_U_(1) << 9) /**< SUPC signal: SUPC_WKUP6 */ +#define PIN_PA11X1_SUPC_WKUP7 _L_(11) /**< SUPC signal: SUPC_WKUP7 on PA11 mux X1 */ +#define PIO_PA11X1_SUPC_WKUP7 (_U_(1) << 11) /**< SUPC signal: SUPC_WKUP7 */ +#define PIN_PA14X1_SUPC_WKUP8 _L_(14) /**< SUPC signal: SUPC_WKUP8 on PA14 mux X1 */ +#define PIO_PA14X1_SUPC_WKUP8 (_U_(1) << 14) /**< SUPC signal: SUPC_WKUP8 */ +#define PIN_PA19X1_SUPC_WKUP9 _L_(19) /**< SUPC signal: SUPC_WKUP9 on PA19 mux X1 */ +#define PIO_PA19X1_SUPC_WKUP9 (_U_(1) << 19) /**< SUPC signal: SUPC_WKUP9 */ +#define PIN_PA20X1_SUPC_WKUP10 _L_(20) /**< SUPC signal: SUPC_WKUP10 on PA20 mux X1 */ +#define PIO_PA20X1_SUPC_WKUP10 (_U_(1) << 20) /**< SUPC signal: SUPC_WKUP10 */ +#define PIN_PA30X1_SUPC_WKUP11 _L_(30) /**< SUPC signal: SUPC_WKUP11 on PA30 mux X1 */ +#define PIO_PA30X1_SUPC_WKUP11 (_U_(1) << 30) /**< SUPC signal: SUPC_WKUP11 */ +#define PIN_PB3X1_SUPC_WKUP12 _L_(35) /**< SUPC signal: SUPC_WKUP12 on PB3 mux X1 */ +#define PIO_PB3X1_SUPC_WKUP12 (_U_(1) << 3) /**< SUPC signal: SUPC_WKUP12 */ +#define PIN_PB5X1_SUPC_WKUP13 _L_(37) /**< SUPC signal: SUPC_WKUP13 on PB5 mux X1 */ +#define PIO_PB5X1_SUPC_WKUP13 (_U_(1) << 5) /**< SUPC signal: SUPC_WKUP13 */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIN_PA4B_TC0_TCLK0 _L_(4) /**< TC0 signal: TC0_TCLK0 on PA4 mux B */ +#define MUX_PA4B_TC0_TCLK0 _L_(1) /**< TC0 signal line function value: TC0_TCLK0 */ +#define PIO_PA4B_TC0_TCLK0 (_U_(1) << 4) /**< TC0 signal: TC0_TCLK0 */ +#define PIN_PA28B_TC0_TCLK1 _L_(28) /**< TC0 signal: TC0_TCLK1 on PA28 mux B */ +#define MUX_PA28B_TC0_TCLK1 _L_(1) /**< TC0 signal line function value: TC0_TCLK1 */ +#define PIO_PA28B_TC0_TCLK1 (_U_(1) << 28) /**< TC0 signal: TC0_TCLK1 */ +#define PIN_PA29B_TC0_TCLK2 _L_(29) /**< TC0 signal: TC0_TCLK2 on PA29 mux B */ +#define MUX_PA29B_TC0_TCLK2 _L_(1) /**< TC0 signal line function value: TC0_TCLK2 */ +#define PIO_PA29B_TC0_TCLK2 (_U_(1) << 29) /**< TC0 signal: TC0_TCLK2 */ +#define PIN_PA0B_TC0_TIOA0 _L_(0) /**< TC0 signal: TC0_TIOA0 on PA0 mux B */ +#define MUX_PA0B_TC0_TIOA0 _L_(1) /**< TC0 signal line function value: TC0_TIOA0 */ +#define PIO_PA0B_TC0_TIOA0 (_U_(1) << 0) /**< TC0 signal: TC0_TIOA0 */ +#define PIN_PA15B_TC0_TIOA1 _L_(15) /**< TC0 signal: TC0_TIOA1 on PA15 mux B */ +#define MUX_PA15B_TC0_TIOA1 _L_(1) /**< TC0 signal line function value: TC0_TIOA1 */ +#define PIO_PA15B_TC0_TIOA1 (_U_(1) << 15) /**< TC0 signal: TC0_TIOA1 */ +#define PIN_PA26B_TC0_TIOA2 _L_(26) /**< TC0 signal: TC0_TIOA2 on PA26 mux B */ +#define MUX_PA26B_TC0_TIOA2 _L_(1) /**< TC0 signal line function value: TC0_TIOA2 */ +#define PIO_PA26B_TC0_TIOA2 (_U_(1) << 26) /**< TC0 signal: TC0_TIOA2 */ +#define PIN_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal: TC0_TIOB0 on PA1 mux B */ +#define MUX_PA1B_TC0_TIOB0 _L_(1) /**< TC0 signal line function value: TC0_TIOB0 */ +#define PIO_PA1B_TC0_TIOB0 (_U_(1) << 1) /**< TC0 signal: TC0_TIOB0 */ +#define PIN_PA16B_TC0_TIOB1 _L_(16) /**< TC0 signal: TC0_TIOB1 on PA16 mux B */ +#define MUX_PA16B_TC0_TIOB1 _L_(1) /**< TC0 signal line function value: TC0_TIOB1 */ +#define PIO_PA16B_TC0_TIOB1 (_U_(1) << 16) /**< TC0 signal: TC0_TIOB1 */ +#define PIN_PA27B_TC0_TIOB2 _L_(27) /**< TC0 signal: TC0_TIOB2 on PA27 mux B */ +#define MUX_PA27B_TC0_TIOB2 _L_(1) /**< TC0 signal line function value: TC0_TIOB2 */ +#define PIO_PA27B_TC0_TIOB2 (_U_(1) << 27) /**< TC0 signal: TC0_TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIN_PC25B_TC1_TCLK3 _L_(89) /**< TC1 signal: TC1_TCLK3 on PC25 mux B */ +#define MUX_PC25B_TC1_TCLK3 _L_(1) /**< TC1 signal line function value: TC1_TCLK3 */ +#define PIO_PC25B_TC1_TCLK3 (_U_(1) << 25) /**< TC1 signal: TC1_TCLK3 */ +#define PIN_PC28B_TC1_TCLK4 _L_(92) /**< TC1 signal: TC1_TCLK4 on PC28 mux B */ +#define MUX_PC28B_TC1_TCLK4 _L_(1) /**< TC1 signal line function value: TC1_TCLK4 */ +#define PIO_PC28B_TC1_TCLK4 (_U_(1) << 28) /**< TC1 signal: TC1_TCLK4 */ +#define PIN_PC31B_TC1_TCLK5 _L_(95) /**< TC1 signal: TC1_TCLK5 on PC31 mux B */ +#define MUX_PC31B_TC1_TCLK5 _L_(1) /**< TC1 signal line function value: TC1_TCLK5 */ +#define PIO_PC31B_TC1_TCLK5 (_U_(1) << 31) /**< TC1 signal: TC1_TCLK5 */ +#define PIN_PC23B_TC1_TIOA3 _L_(87) /**< TC1 signal: TC1_TIOA3 on PC23 mux B */ +#define MUX_PC23B_TC1_TIOA3 _L_(1) /**< TC1 signal line function value: TC1_TIOA3 */ +#define PIO_PC23B_TC1_TIOA3 (_U_(1) << 23) /**< TC1 signal: TC1_TIOA3 */ +#define PIN_PC26B_TC1_TIOA4 _L_(90) /**< TC1 signal: TC1_TIOA4 on PC26 mux B */ +#define MUX_PC26B_TC1_TIOA4 _L_(1) /**< TC1 signal line function value: TC1_TIOA4 */ +#define PIO_PC26B_TC1_TIOA4 (_U_(1) << 26) /**< TC1 signal: TC1_TIOA4 */ +#define PIN_PC29B_TC1_TIOA5 _L_(93) /**< TC1 signal: TC1_TIOA5 on PC29 mux B */ +#define MUX_PC29B_TC1_TIOA5 _L_(1) /**< TC1 signal line function value: TC1_TIOA5 */ +#define PIO_PC29B_TC1_TIOA5 (_U_(1) << 29) /**< TC1 signal: TC1_TIOA5 */ +#define PIN_PC24B_TC1_TIOB3 _L_(88) /**< TC1 signal: TC1_TIOB3 on PC24 mux B */ +#define MUX_PC24B_TC1_TIOB3 _L_(1) /**< TC1 signal line function value: TC1_TIOB3 */ +#define PIO_PC24B_TC1_TIOB3 (_U_(1) << 24) /**< TC1 signal: TC1_TIOB3 */ +#define PIN_PC27B_TC1_TIOB4 _L_(91) /**< TC1 signal: TC1_TIOB4 on PC27 mux B */ +#define MUX_PC27B_TC1_TIOB4 _L_(1) /**< TC1 signal line function value: TC1_TIOB4 */ +#define PIO_PC27B_TC1_TIOB4 (_U_(1) << 27) /**< TC1 signal: TC1_TIOB4 */ +#define PIN_PC30B_TC1_TIOB5 _L_(94) /**< TC1 signal: TC1_TIOB5 on PC30 mux B */ +#define MUX_PC30B_TC1_TIOB5 _L_(1) /**< TC1 signal line function value: TC1_TIOB5 */ +#define PIO_PC30B_TC1_TIOB5 (_U_(1) << 30) /**< TC1 signal: TC1_TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIN_PC7B_TC2_TCLK6 _L_(71) /**< TC2 signal: TC2_TCLK6 on PC7 mux B */ +#define MUX_PC7B_TC2_TCLK6 _L_(1) /**< TC2 signal line function value: TC2_TCLK6 */ +#define PIO_PC7B_TC2_TCLK6 (_U_(1) << 7) /**< TC2 signal: TC2_TCLK6 */ +#define PIN_PC10B_TC2_TCLK7 _L_(74) /**< TC2 signal: TC2_TCLK7 on PC10 mux B */ +#define MUX_PC10B_TC2_TCLK7 _L_(1) /**< TC2 signal line function value: TC2_TCLK7 */ +#define PIO_PC10B_TC2_TCLK7 (_U_(1) << 10) /**< TC2 signal: TC2_TCLK7 */ +#define PIN_PC14B_TC2_TCLK8 _L_(78) /**< TC2 signal: TC2_TCLK8 on PC14 mux B */ +#define MUX_PC14B_TC2_TCLK8 _L_(1) /**< TC2 signal line function value: TC2_TCLK8 */ +#define PIO_PC14B_TC2_TCLK8 (_U_(1) << 14) /**< TC2 signal: TC2_TCLK8 */ +#define PIN_PC5B_TC2_TIOA6 _L_(69) /**< TC2 signal: TC2_TIOA6 on PC5 mux B */ +#define MUX_PC5B_TC2_TIOA6 _L_(1) /**< TC2 signal line function value: TC2_TIOA6 */ +#define PIO_PC5B_TC2_TIOA6 (_U_(1) << 5) /**< TC2 signal: TC2_TIOA6 */ +#define PIN_PC8B_TC2_TIOA7 _L_(72) /**< TC2 signal: TC2_TIOA7 on PC8 mux B */ +#define MUX_PC8B_TC2_TIOA7 _L_(1) /**< TC2 signal line function value: TC2_TIOA7 */ +#define PIO_PC8B_TC2_TIOA7 (_U_(1) << 8) /**< TC2 signal: TC2_TIOA7 */ +#define PIN_PC11B_TC2_TIOA8 _L_(75) /**< TC2 signal: TC2_TIOA8 on PC11 mux B */ +#define MUX_PC11B_TC2_TIOA8 _L_(1) /**< TC2 signal line function value: TC2_TIOA8 */ +#define PIO_PC11B_TC2_TIOA8 (_U_(1) << 11) /**< TC2 signal: TC2_TIOA8 */ +#define PIN_PC6B_TC2_TIOB6 _L_(70) /**< TC2 signal: TC2_TIOB6 on PC6 mux B */ +#define MUX_PC6B_TC2_TIOB6 _L_(1) /**< TC2 signal line function value: TC2_TIOB6 */ +#define PIO_PC6B_TC2_TIOB6 (_U_(1) << 6) /**< TC2 signal: TC2_TIOB6 */ +#define PIN_PC9B_TC2_TIOB7 _L_(73) /**< TC2 signal: TC2_TIOB7 on PC9 mux B */ +#define MUX_PC9B_TC2_TIOB7 _L_(1) /**< TC2 signal line function value: TC2_TIOB7 */ +#define PIO_PC9B_TC2_TIOB7 (_U_(1) << 9) /**< TC2 signal: TC2_TIOB7 */ +#define PIN_PC12B_TC2_TIOB8 _L_(76) /**< TC2 signal: TC2_TIOB8 on PC12 mux B */ +#define MUX_PC12B_TC2_TIOB8 _L_(1) /**< TC2 signal line function value: TC2_TIOB8 */ +#define PIO_PC12B_TC2_TIOB8 (_U_(1) << 12) /**< TC2 signal: TC2_TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIN_PE2B_TC3_TCLK9 _L_(130) /**< TC3 signal: TC3_TCLK9 on PE2 mux B */ +#define MUX_PE2B_TC3_TCLK9 _L_(1) /**< TC3 signal line function value: TC3_TCLK9 */ +#define PIO_PE2B_TC3_TCLK9 (_U_(1) << 2) /**< TC3 signal: TC3_TCLK9 */ +#define PIN_PE5B_TC3_TCLK10 _L_(133) /**< TC3 signal: TC3_TCLK10 on PE5 mux B */ +#define MUX_PE5B_TC3_TCLK10 _L_(1) /**< TC3 signal line function value: TC3_TCLK10 */ +#define PIO_PE5B_TC3_TCLK10 (_U_(1) << 5) /**< TC3 signal: TC3_TCLK10 */ +#define PIN_PD24C_TC3_TCLK11 _L_(120) /**< TC3 signal: TC3_TCLK11 on PD24 mux C */ +#define MUX_PD24C_TC3_TCLK11 _L_(2) /**< TC3 signal line function value: TC3_TCLK11 */ +#define PIO_PD24C_TC3_TCLK11 (_U_(1) << 24) /**< TC3 signal: TC3_TCLK11 */ +#define PIN_PE0B_TC3_TIOA9 _L_(128) /**< TC3 signal: TC3_TIOA9 on PE0 mux B */ +#define MUX_PE0B_TC3_TIOA9 _L_(1) /**< TC3 signal line function value: TC3_TIOA9 */ +#define PIO_PE0B_TC3_TIOA9 (_U_(1) << 0) /**< TC3 signal: TC3_TIOA9 */ +#define PIN_PE3B_TC3_TIOA10 _L_(131) /**< TC3 signal: TC3_TIOA10 on PE3 mux B */ +#define MUX_PE3B_TC3_TIOA10 _L_(1) /**< TC3 signal line function value: TC3_TIOA10 */ +#define PIO_PE3B_TC3_TIOA10 (_U_(1) << 3) /**< TC3 signal: TC3_TIOA10 */ +#define PIN_PD21C_TC3_TIOA11 _L_(117) /**< TC3 signal: TC3_TIOA11 on PD21 mux C */ +#define MUX_PD21C_TC3_TIOA11 _L_(2) /**< TC3 signal line function value: TC3_TIOA11 */ +#define PIO_PD21C_TC3_TIOA11 (_U_(1) << 21) /**< TC3 signal: TC3_TIOA11 */ +#define PIN_PE1B_TC3_TIOB9 _L_(129) /**< TC3 signal: TC3_TIOB9 on PE1 mux B */ +#define MUX_PE1B_TC3_TIOB9 _L_(1) /**< TC3 signal line function value: TC3_TIOB9 */ +#define PIO_PE1B_TC3_TIOB9 (_U_(1) << 1) /**< TC3 signal: TC3_TIOB9 */ +#define PIN_PE4B_TC3_TIOB10 _L_(132) /**< TC3 signal: TC3_TIOB10 on PE4 mux B */ +#define MUX_PE4B_TC3_TIOB10 _L_(1) /**< TC3 signal line function value: TC3_TIOB10 */ +#define PIO_PE4B_TC3_TIOB10 (_U_(1) << 4) /**< TC3 signal: TC3_TIOB10 */ +#define PIN_PD22C_TC3_TIOB11 _L_(118) /**< TC3 signal: TC3_TIOB11 on PD22 mux C */ +#define MUX_PD22C_TC3_TIOB11 _L_(2) /**< TC3 signal line function value: TC3_TIOB11 */ +#define PIO_PD22C_TC3_TIOB11 (_U_(1) << 22) /**< TC3 signal: TC3_TIOB11 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIN_PA4A_TWIHS0_TWCK0 _L_(4) /**< TWIHS0 signal: TWIHS0_TWCK0 on PA4 mux A */ +#define MUX_PA4A_TWIHS0_TWCK0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWCK0 */ +#define PIO_PA4A_TWIHS0_TWCK0 (_U_(1) << 4) /**< TWIHS0 signal: TWIHS0_TWCK0 */ +#define PIN_PA3A_TWIHS0_TWD0 _L_(3) /**< TWIHS0 signal: TWIHS0_TWD0 on PA3 mux A */ +#define MUX_PA3A_TWIHS0_TWD0 _L_(0) /**< TWIHS0 signal line function value: TWIHS0_TWD0 */ +#define PIO_PA3A_TWIHS0_TWD0 (_U_(1) << 3) /**< TWIHS0 signal: TWIHS0_TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIN_PB5A_TWIHS1_TWCK1 _L_(37) /**< TWIHS1 signal: TWIHS1_TWCK1 on PB5 mux A */ +#define MUX_PB5A_TWIHS1_TWCK1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWCK1 */ +#define PIO_PB5A_TWIHS1_TWCK1 (_U_(1) << 5) /**< TWIHS1 signal: TWIHS1_TWCK1 */ +#define PIN_PB4A_TWIHS1_TWD1 _L_(36) /**< TWIHS1 signal: TWIHS1_TWD1 on PB4 mux A */ +#define MUX_PB4A_TWIHS1_TWD1 _L_(0) /**< TWIHS1 signal line function value: TWIHS1_TWD1 */ +#define PIO_PB4A_TWIHS1_TWD1 (_U_(1) << 4) /**< TWIHS1 signal: TWIHS1_TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIN_PD28C_TWIHS2_TWCK2 _L_(124) /**< TWIHS2 signal: TWIHS2_TWCK2 on PD28 mux C */ +#define MUX_PD28C_TWIHS2_TWCK2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWCK2 */ +#define PIO_PD28C_TWIHS2_TWCK2 (_U_(1) << 28) /**< TWIHS2 signal: TWIHS2_TWCK2 */ +#define PIN_PD27C_TWIHS2_TWD2 _L_(123) /**< TWIHS2 signal: TWIHS2_TWD2 on PD27 mux C */ +#define MUX_PD27C_TWIHS2_TWD2 _L_(2) /**< TWIHS2 signal line function value: TWIHS2_TWD2 */ +#define PIO_PD27C_TWIHS2_TWD2 (_U_(1) << 27) /**< TWIHS2 signal: TWIHS2_TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIN_PA9A_UART0_URXD0 _L_(9) /**< UART0 signal: UART0_URXD0 on PA9 mux A */ +#define MUX_PA9A_UART0_URXD0 _L_(0) /**< UART0 signal line function value: UART0_URXD0 */ +#define PIO_PA9A_UART0_URXD0 (_U_(1) << 9) /**< UART0 signal: UART0_URXD0 */ +#define PIN_PA10A_UART0_UTXD0 _L_(10) /**< UART0 signal: UART0_UTXD0 on PA10 mux A */ +#define MUX_PA10A_UART0_UTXD0 _L_(0) /**< UART0 signal line function value: UART0_UTXD0 */ +#define PIO_PA10A_UART0_UTXD0 (_U_(1) << 10) /**< UART0 signal: UART0_UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIN_PA5C_UART1_URXD1 _L_(5) /**< UART1 signal: UART1_URXD1 on PA5 mux C */ +#define MUX_PA5C_UART1_URXD1 _L_(2) /**< UART1 signal line function value: UART1_URXD1 */ +#define PIO_PA5C_UART1_URXD1 (_U_(1) << 5) /**< UART1 signal: UART1_URXD1 */ +#define PIN_PA4C_UART1_UTXD1 _L_(4) /**< UART1 signal: UART1_UTXD1 on PA4 mux C */ +#define MUX_PA4C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA4C_UART1_UTXD1 (_U_(1) << 4) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PA6C_UART1_UTXD1 _L_(6) /**< UART1 signal: UART1_UTXD1 on PA6 mux C */ +#define MUX_PA6C_UART1_UTXD1 _L_(2) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PA6C_UART1_UTXD1 (_U_(1) << 6) /**< UART1 signal: UART1_UTXD1 */ +#define PIN_PD26D_UART1_UTXD1 _L_(122) /**< UART1 signal: UART1_UTXD1 on PD26 mux D */ +#define MUX_PD26D_UART1_UTXD1 _L_(3) /**< UART1 signal line function value: UART1_UTXD1 */ +#define PIO_PD26D_UART1_UTXD1 (_U_(1) << 26) /**< UART1 signal: UART1_UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIN_PD25C_UART2_URXD2 _L_(121) /**< UART2 signal: UART2_URXD2 on PD25 mux C */ +#define MUX_PD25C_UART2_URXD2 _L_(2) /**< UART2 signal line function value: UART2_URXD2 */ +#define PIO_PD25C_UART2_URXD2 (_U_(1) << 25) /**< UART2 signal: UART2_URXD2 */ +#define PIN_PD26C_UART2_UTXD2 _L_(122) /**< UART2 signal: UART2_UTXD2 on PD26 mux C */ +#define MUX_PD26C_UART2_UTXD2 _L_(2) /**< UART2 signal line function value: UART2_UTXD2 */ +#define PIO_PD26C_UART2_UTXD2 (_U_(1) << 26) /**< UART2 signal: UART2_UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIN_PD28A_UART3_URXD3 _L_(124) /**< UART3 signal: UART3_URXD3 on PD28 mux A */ +#define MUX_PD28A_UART3_URXD3 _L_(0) /**< UART3 signal line function value: UART3_URXD3 */ +#define PIO_PD28A_UART3_URXD3 (_U_(1) << 28) /**< UART3 signal: UART3_URXD3 */ +#define PIN_PD30A_UART3_UTXD3 _L_(126) /**< UART3 signal: UART3_UTXD3 on PD30 mux A */ +#define MUX_PD30A_UART3_UTXD3 _L_(0) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD30A_UART3_UTXD3 (_U_(1) << 30) /**< UART3 signal: UART3_UTXD3 */ +#define PIN_PD31B_UART3_UTXD3 _L_(127) /**< UART3 signal: UART3_UTXD3 on PD31 mux B */ +#define MUX_PD31B_UART3_UTXD3 _L_(1) /**< UART3 signal line function value: UART3_UTXD3 */ +#define PIO_PD31B_UART3_UTXD3 (_U_(1) << 31) /**< UART3 signal: UART3_UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIN_PD18C_UART4_URXD4 _L_(114) /**< UART4 signal: UART4_URXD4 on PD18 mux C */ +#define MUX_PD18C_UART4_URXD4 _L_(2) /**< UART4 signal line function value: UART4_URXD4 */ +#define PIO_PD18C_UART4_URXD4 (_U_(1) << 18) /**< UART4 signal: UART4_URXD4 */ +#define PIN_PD3C_UART4_UTXD4 _L_(99) /**< UART4 signal: UART4_UTXD4 on PD3 mux C */ +#define MUX_PD3C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD3C_UART4_UTXD4 (_U_(1) << 3) /**< UART4 signal: UART4_UTXD4 */ +#define PIN_PD19C_UART4_UTXD4 _L_(115) /**< UART4 signal: UART4_UTXD4 on PD19 mux C */ +#define MUX_PD19C_UART4_UTXD4 _L_(2) /**< UART4 signal line function value: UART4_UTXD4 */ +#define PIO_PD19C_UART4_UTXD4 (_U_(1) << 19) /**< UART4 signal: UART4_UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIN_PB2C_USART0_CTS0 _L_(34) /**< USART0 signal: USART0_CTS0 on PB2 mux C */ +#define MUX_PB2C_USART0_CTS0 _L_(2) /**< USART0 signal line function value: USART0_CTS0 */ +#define PIO_PB2C_USART0_CTS0 (_U_(1) << 2) /**< USART0 signal: USART0_CTS0 */ +#define PIN_PD0D_USART0_DCD0 _L_(96) /**< USART0 signal: USART0_DCD0 on PD0 mux D */ +#define MUX_PD0D_USART0_DCD0 _L_(3) /**< USART0 signal line function value: USART0_DCD0 */ +#define PIO_PD0D_USART0_DCD0 (_U_(1) << 0) /**< USART0 signal: USART0_DCD0 */ +#define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: USART0_DSR0 on PD2 mux D */ +#define MUX_PD2D_USART0_DSR0 _L_(3) /**< USART0 signal line function value: USART0_DSR0 */ +#define PIO_PD2D_USART0_DSR0 (_U_(1) << 2) /**< USART0 signal: USART0_DSR0 */ +#define PIN_PD1D_USART0_DTR0 _L_(97) /**< USART0 signal: USART0_DTR0 on PD1 mux D */ +#define MUX_PD1D_USART0_DTR0 _L_(3) /**< USART0 signal line function value: USART0_DTR0 */ +#define PIO_PD1D_USART0_DTR0 (_U_(1) << 1) /**< USART0 signal: USART0_DTR0 */ +#define PIN_PD3D_USART0_RI0 _L_(99) /**< USART0 signal: USART0_RI0 on PD3 mux D */ +#define MUX_PD3D_USART0_RI0 _L_(3) /**< USART0 signal line function value: USART0_RI0 */ +#define PIO_PD3D_USART0_RI0 (_U_(1) << 3) /**< USART0 signal: USART0_RI0 */ +#define PIN_PB3C_USART0_RTS0 _L_(35) /**< USART0 signal: USART0_RTS0 on PB3 mux C */ +#define MUX_PB3C_USART0_RTS0 _L_(2) /**< USART0 signal line function value: USART0_RTS0 */ +#define PIO_PB3C_USART0_RTS0 (_U_(1) << 3) /**< USART0 signal: USART0_RTS0 */ +#define PIN_PB0C_USART0_RXD0 _L_(32) /**< USART0 signal: USART0_RXD0 on PB0 mux C */ +#define MUX_PB0C_USART0_RXD0 _L_(2) /**< USART0 signal line function value: USART0_RXD0 */ +#define PIO_PB0C_USART0_RXD0 (_U_(1) << 0) /**< USART0 signal: USART0_RXD0 */ +#define PIN_PB13C_USART0_SCK0 _L_(45) /**< USART0 signal: USART0_SCK0 on PB13 mux C */ +#define MUX_PB13C_USART0_SCK0 _L_(2) /**< USART0 signal line function value: USART0_SCK0 */ +#define PIO_PB13C_USART0_SCK0 (_U_(1) << 13) /**< USART0 signal: USART0_SCK0 */ +#define PIN_PB1C_USART0_TXD0 _L_(33) /**< USART0 signal: USART0_TXD0 on PB1 mux C */ +#define MUX_PB1C_USART0_TXD0 _L_(2) /**< USART0 signal line function value: USART0_TXD0 */ +#define PIO_PB1C_USART0_TXD0 (_U_(1) << 1) /**< USART0 signal: USART0_TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIN_PA25A_USART1_CTS1 _L_(25) /**< USART1 signal: USART1_CTS1 on PA25 mux A */ +#define MUX_PA25A_USART1_CTS1 _L_(0) /**< USART1 signal line function value: USART1_CTS1 */ +#define PIO_PA25A_USART1_CTS1 (_U_(1) << 25) /**< USART1 signal: USART1_CTS1 */ +#define PIN_PA26A_USART1_DCD1 _L_(26) /**< USART1 signal: USART1_DCD1 on PA26 mux A */ +#define MUX_PA26A_USART1_DCD1 _L_(0) /**< USART1 signal line function value: USART1_DCD1 */ +#define PIO_PA26A_USART1_DCD1 (_U_(1) << 26) /**< USART1 signal: USART1_DCD1 */ +#define PIN_PA28A_USART1_DSR1 _L_(28) /**< USART1 signal: USART1_DSR1 on PA28 mux A */ +#define MUX_PA28A_USART1_DSR1 _L_(0) /**< USART1 signal line function value: USART1_DSR1 */ +#define PIO_PA28A_USART1_DSR1 (_U_(1) << 28) /**< USART1 signal: USART1_DSR1 */ +#define PIN_PA27A_USART1_DTR1 _L_(27) /**< USART1 signal: USART1_DTR1 on PA27 mux A */ +#define MUX_PA27A_USART1_DTR1 _L_(0) /**< USART1 signal line function value: USART1_DTR1 */ +#define PIO_PA27A_USART1_DTR1 (_U_(1) << 27) /**< USART1 signal: USART1_DTR1 */ +#define PIN_PA3B_USART1_LONCOL1 _L_(3) /**< USART1 signal: USART1_LONCOL1 on PA3 mux B */ +#define MUX_PA3B_USART1_LONCOL1 _L_(1) /**< USART1 signal line function value: USART1_LONCOL1 */ +#define PIO_PA3B_USART1_LONCOL1 (_U_(1) << 3) /**< USART1 signal: USART1_LONCOL1 */ +#define PIN_PA29A_USART1_RI1 _L_(29) /**< USART1 signal: USART1_RI1 on PA29 mux A */ +#define MUX_PA29A_USART1_RI1 _L_(0) /**< USART1 signal line function value: USART1_RI1 */ +#define PIO_PA29A_USART1_RI1 (_U_(1) << 29) /**< USART1 signal: USART1_RI1 */ +#define PIN_PA24A_USART1_RTS1 _L_(24) /**< USART1 signal: USART1_RTS1 on PA24 mux A */ +#define MUX_PA24A_USART1_RTS1 _L_(0) /**< USART1 signal line function value: USART1_RTS1 */ +#define PIO_PA24A_USART1_RTS1 (_U_(1) << 24) /**< USART1 signal: USART1_RTS1 */ +#define PIN_PA21A_USART1_RXD1 _L_(21) /**< USART1 signal: USART1_RXD1 on PA21 mux A */ +#define MUX_PA21A_USART1_RXD1 _L_(0) /**< USART1 signal line function value: USART1_RXD1 */ +#define PIO_PA21A_USART1_RXD1 (_U_(1) << 21) /**< USART1 signal: USART1_RXD1 */ +#define PIN_PA23A_USART1_SCK1 _L_(23) /**< USART1 signal: USART1_SCK1 on PA23 mux A */ +#define MUX_PA23A_USART1_SCK1 _L_(0) /**< USART1 signal line function value: USART1_SCK1 */ +#define PIO_PA23A_USART1_SCK1 (_U_(1) << 23) /**< USART1 signal: USART1_SCK1 */ +#define PIN_PB4D_USART1_TXD1 _L_(36) /**< USART1 signal: USART1_TXD1 on PB4 mux D */ +#define MUX_PB4D_USART1_TXD1 _L_(3) /**< USART1 signal line function value: USART1_TXD1 */ +#define PIO_PB4D_USART1_TXD1 (_U_(1) << 4) /**< USART1 signal: USART1_TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIN_PD19B_USART2_CTS2 _L_(115) /**< USART2 signal: USART2_CTS2 on PD19 mux B */ +#define MUX_PD19B_USART2_CTS2 _L_(1) /**< USART2 signal line function value: USART2_CTS2 */ +#define PIO_PD19B_USART2_CTS2 (_U_(1) << 19) /**< USART2 signal: USART2_CTS2 */ +#define PIN_PD4D_USART2_DCD2 _L_(100) /**< USART2 signal: USART2_DCD2 on PD4 mux D */ +#define MUX_PD4D_USART2_DCD2 _L_(3) /**< USART2 signal line function value: USART2_DCD2 */ +#define PIO_PD4D_USART2_DCD2 (_U_(1) << 4) /**< USART2 signal: USART2_DCD2 */ +#define PIN_PD6D_USART2_DSR2 _L_(102) /**< USART2 signal: USART2_DSR2 on PD6 mux D */ +#define MUX_PD6D_USART2_DSR2 _L_(3) /**< USART2 signal line function value: USART2_DSR2 */ +#define PIO_PD6D_USART2_DSR2 (_U_(1) << 6) /**< USART2 signal: USART2_DSR2 */ +#define PIN_PD5D_USART2_DTR2 _L_(101) /**< USART2 signal: USART2_DTR2 on PD5 mux D */ +#define MUX_PD5D_USART2_DTR2 _L_(3) /**< USART2 signal line function value: USART2_DTR2 */ +#define PIO_PD5D_USART2_DTR2 (_U_(1) << 5) /**< USART2 signal: USART2_DTR2 */ +#define PIN_PD7D_USART2_RI2 _L_(103) /**< USART2 signal: USART2_RI2 on PD7 mux D */ +#define MUX_PD7D_USART2_RI2 _L_(3) /**< USART2 signal line function value: USART2_RI2 */ +#define PIO_PD7D_USART2_RI2 (_U_(1) << 7) /**< USART2 signal: USART2_RI2 */ +#define PIN_PD18B_USART2_RTS2 _L_(114) /**< USART2 signal: USART2_RTS2 on PD18 mux B */ +#define MUX_PD18B_USART2_RTS2 _L_(1) /**< USART2 signal line function value: USART2_RTS2 */ +#define PIO_PD18B_USART2_RTS2 (_U_(1) << 18) /**< USART2 signal: USART2_RTS2 */ +#define PIN_PD15B_USART2_RXD2 _L_(111) /**< USART2 signal: USART2_RXD2 on PD15 mux B */ +#define MUX_PD15B_USART2_RXD2 _L_(1) /**< USART2 signal line function value: USART2_RXD2 */ +#define PIO_PD15B_USART2_RXD2 (_U_(1) << 15) /**< USART2 signal: USART2_RXD2 */ +#define PIN_PD17B_USART2_SCK2 _L_(113) /**< USART2 signal: USART2_SCK2 on PD17 mux B */ +#define MUX_PD17B_USART2_SCK2 _L_(1) /**< USART2 signal line function value: USART2_SCK2 */ +#define PIO_PD17B_USART2_SCK2 (_U_(1) << 17) /**< USART2 signal: USART2_SCK2 */ +#define PIN_PD16B_USART2_TXD2 _L_(112) /**< USART2 signal: USART2_TXD2 on PD16 mux B */ +#define MUX_PD16B_USART2_TXD2 _L_(1) /**< USART2 signal line function value: USART2_TXD2 */ +#define PIO_PD16B_USART2_TXD2 (_U_(1) << 16) /**< USART2 signal: USART2_TXD2 */ +/* ========== PIO definition for ICE peripheral ========== */ +#define PIN_PB7X1_ICE_SWDCLK _L_(39) /**< ICE signal: ICE_SWDCLK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_SWDCLK (_U_(1) << 7) /**< ICE signal: ICE_SWDCLK */ +#define PIN_PB6X1_ICE_SWDIO _L_(38) /**< ICE signal: ICE_SWDIO on PB6 mux X1 */ +#define PIO_PB6X1_ICE_SWDIO (_U_(1) << 6) /**< ICE signal: ICE_SWDIO */ +#define PIN_PB7X1_ICE_TCK _L_(39) /**< ICE signal: ICE_TCK on PB7 mux X1 */ +#define PIO_PB7X1_ICE_TCK (_U_(1) << 7) /**< ICE signal: ICE_TCK */ +#define PIN_PB4X1_ICE_TDI _L_(36) /**< ICE signal: ICE_TDI on PB4 mux X1 */ +#define PIO_PB4X1_ICE_TDI (_U_(1) << 4) /**< ICE signal: ICE_TDI */ +#define PIN_PB5X1_ICE_TDO _L_(37) /**< ICE signal: ICE_TDO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TDO (_U_(1) << 5) /**< ICE signal: ICE_TDO */ +#define PIN_PB6X1_ICE_TMS _L_(38) /**< ICE signal: ICE_TMS on PB6 mux X1 */ +#define PIO_PB6X1_ICE_TMS (_U_(1) << 6) /**< ICE signal: ICE_TMS */ +#define PIN_PB5X1_ICE_TRACESWO _L_(37) /**< ICE signal: ICE_TRACESWO on PB5 mux X1 */ +#define PIO_PB5X1_ICE_TRACESWO (_U_(1) << 5) /**< ICE signal: ICE_TRACESWO */ +/* ========== PIO definition for TPIU peripheral ========== */ +#define PIN_PD8D_TPIU_TRACECLK _L_(104) /**< TPIU signal: TPIU_TRACECLK on PD8 mux D */ +#define MUX_PD8D_TPIU_TRACECLK _L_(3) /**< TPIU signal line function value: TPIU_TRACECLK */ +#define PIO_PD8D_TPIU_TRACECLK (_U_(1) << 8) /**< TPIU signal: TPIU_TRACECLK */ +#define PIN_PD4C_TPIU_TRACED0 _L_(100) /**< TPIU signal: TPIU_TRACED0 on PD4 mux C */ +#define MUX_PD4C_TPIU_TRACED0 _L_(2) /**< TPIU signal line function value: TPIU_TRACED0 */ +#define PIO_PD4C_TPIU_TRACED0 (_U_(1) << 4) /**< TPIU signal: TPIU_TRACED0 */ +#define PIN_PD5C_TPIU_TRACED1 _L_(101) /**< TPIU signal: TPIU_TRACED1 on PD5 mux C */ +#define MUX_PD5C_TPIU_TRACED1 _L_(2) /**< TPIU signal line function value: TPIU_TRACED1 */ +#define PIO_PD5C_TPIU_TRACED1 (_U_(1) << 5) /**< TPIU signal: TPIU_TRACED1 */ +#define PIN_PD6C_TPIU_TRACED2 _L_(102) /**< TPIU signal: TPIU_TRACED2 on PD6 mux C */ +#define MUX_PD6C_TPIU_TRACED2 _L_(2) /**< TPIU signal line function value: TPIU_TRACED2 */ +#define PIO_PD6C_TPIU_TRACED2 (_U_(1) << 6) /**< TPIU signal: TPIU_TRACED2 */ +#define PIN_PD7C_TPIU_TRACED3 _L_(103) /**< TPIU signal: TPIU_TRACED3 on PD7 mux C */ +#define MUX_PD7C_TPIU_TRACED3 _L_(2) /**< TPIU signal line function value: TPIU_TRACED3 */ +#define PIO_PD7C_TPIU_TRACED3 (_U_(1) << 7) /**< TPIU signal: TPIU_TRACED3 */ + +#endif /* _SAME70Q21B_GPIO_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/sam.h b/arch/arm/SAME70/SAME70B/mcu/inc/sam.h new file mode 100644 index 00000000..623fbe13 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/sam.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME70N20B__) || defined(__ATSAME70N20B__) + #include "same70n20b.h" +#elif defined(__SAME70J21B__) || defined(__ATSAME70J21B__) + #include "same70j21b.h" +#elif defined(__SAME70J19B__) || defined(__ATSAME70J19B__) + #include "same70j19b.h" +#elif defined(__SAME70N19B__) || defined(__ATSAME70N19B__) + #include "same70n19b.h" +#elif defined(__SAME70Q19B__) || defined(__ATSAME70Q19B__) + #include "same70q19b.h" +#elif defined(__SAME70Q20B__) || defined(__ATSAME70Q20B__) + #include "same70q20b.h" +#elif defined(__SAME70Q21B__) || defined(__ATSAME70Q21B__) + #include "same70q21b.h" +#elif defined(__SAME70J20B__) || defined(__ATSAME70J20B__) + #include "same70j20b.h" +#elif defined(__SAME70N21B__) || defined(__ATSAME70N21B__) + #include "same70n21b.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70j19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70j19b.h new file mode 100644 index 00000000..bcdffcb5 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70j19b.h @@ -0,0 +1,628 @@ +/** + * \brief Header file for ATSAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:02:47Z */ +#ifndef _SAME70J19B_H_ +#define _SAME70J19B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J19B_definitions SAME70J19B definitions + This file defines all structures and symbols for SAME70J19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#include "pio/same70j19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J19B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J19B definitions */ + + +#endif /* _SAME70J19B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70j20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70j20b.h new file mode 100644 index 00000000..447a72b0 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70j20b.h @@ -0,0 +1,628 @@ +/** + * \brief Header file for ATSAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:01Z */ +#ifndef _SAME70J20B_H_ +#define _SAME70J20B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J20B_definitions SAME70J20B definitions + This file defines all structures and symbols for SAME70J20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#include "pio/same70j20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J20B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J20B definitions */ + + +#endif /* _SAME70J20B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70j21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70j21b.h new file mode 100644 index 00000000..5488c1cc --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70j21b.h @@ -0,0 +1,628 @@ +/** + * \brief Header file for ATSAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:14Z */ +#ifndef _SAME70J21B_H_ +#define _SAME70J21B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70J21B_definitions SAME70J21B definitions + This file defines all structures and symbols for SAME70J21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70J21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pvReserved15; + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pvReserved18; + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pvReserved21; + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pvReserved37; + void* pvReserved38; + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pvReserved41; + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pvReserved45; + void* pvReserved46; + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pvReserved69; + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void PIOD_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70J21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70J21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70J21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70J21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#include "pio/same70j21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70J21B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000000) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70J21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70J21B definitions */ + + +#endif /* _SAME70J21B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70n19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70n19b.h new file mode 100644 index 00000000..e6a85286 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70n19b.h @@ -0,0 +1,673 @@ +/** + * \brief Header file for ATSAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:20Z */ +#ifndef _SAME70N19B_H_ +#define _SAME70N19B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N19B_definitions SAME70N19B definitions + This file defines all structures and symbols for SAME70N19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_MAX ( 69) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#include "pio/same70n19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N19B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N19B definitions */ + + +#endif /* _SAME70N19B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70n20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70n20b.h new file mode 100644 index 00000000..c767813a --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70n20b.h @@ -0,0 +1,673 @@ +/** + * \brief Header file for ATSAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:26Z */ +#ifndef _SAME70N20B_H_ +#define _SAME70N20B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N20B_definitions SAME70N20B definitions + This file defines all structures and symbols for SAME70N20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_MAX ( 69) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#include "pio/same70n20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N20B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N20B definitions */ + + +#endif /* _SAME70N20B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70n21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70n21b.h new file mode 100644 index 00000000..eb9d8786 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70n21b.h @@ -0,0 +1,673 @@ +/** + * \brief Header file for ATSAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:32Z */ +#ifndef _SAME70N21B_H_ +#define _SAME70N21B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70N21B_definitions SAME70N21B definitions + This file defines all structures and symbols for SAME70N21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70N21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pvReserved42; + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pvReserved70; + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70N21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70N21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70N21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ + +#define ID_PERIPH_MAX ( 69) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70N21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70N21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#include "pio/same70n21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70N21B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000001) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70N21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70N21B definitions */ + + +#endif /* _SAME70N21B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70q19b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70q19b.h new file mode 100644 index 00000000..f1be3bfd --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70q19b.h @@ -0,0 +1,713 @@ +/** + * \brief Header file for ATSAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:35Z */ +#ifndef _SAME70Q19B_H_ +#define _SAME70Q19B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q19B_definitions SAME70Q19B definitions + This file defines all structures and symbols for SAME70Q19B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q19B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q19B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q19B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q19B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_MAX ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define I2SC1_REGS ((i2sc_registers_t*)0x40090000) /**< \brief I2SC1 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q19B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define I2SC1_BASE_ADDRESS _UL_(0x40090000) /**< \brief I2SC1 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q19B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#include "pio/same70q19b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 1024) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q19B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA10D0A01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q19B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q19B definitions */ + + +#endif /* _SAME70Q19B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70q20b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70q20b.h new file mode 100644 index 00000000..8882ea04 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70q20b.h @@ -0,0 +1,713 @@ +/** + * \brief Header file for ATSAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:39Z */ +#ifndef _SAME70Q20B_H_ +#define _SAME70Q20B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q20B_definitions SAME70Q20B definitions + This file defines all structures and symbols for SAME70Q20B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q20B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q20B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q20B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q20B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_MAX ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define I2SC1_REGS ((i2sc_registers_t*)0x40090000) /**< \brief I2SC1 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q20B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define I2SC1_BASE_ADDRESS _UL_(0x40090000) /**< \brief I2SC1 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q20B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#include "pio/same70q20b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 2048) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q20B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020C01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q20B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q20B definitions */ + + +#endif /* _SAME70Q20B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/same70q21b.h b/arch/arm/SAME70/SAME70B/mcu/inc/same70q21b.h new file mode 100644 index 00000000..00405ebb --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/same70q21b.h @@ -0,0 +1,713 @@ +/** + * \brief Header file for ATSAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + * + * Subject to your compliance with these terms, you may use Microchip software and any derivatives + * exclusively with Microchip products. It is your responsibility to comply with third party license + * terms applicable to your use of third party software (including open source software) that may + * accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, + * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND + * FITNESS FOR A PARTICULAR PURPOSE. + * + * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF + * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT + * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + */ + +/* file generated from device description version 2020-03-04T11:03:42Z */ +#ifndef _SAME70Q21B_H_ +#define _SAME70Q21B_H_ + +// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) +#define HEADER_FORMAT_VERSION "2.0.0" + +#define HEADER_FORMAT_VERSION_MAJOR (2) +#define HEADER_FORMAT_VERSION_MINOR (0) + +/** \addtogroup SAME70Q21B_definitions SAME70Q21B definitions + This file defines all structures and symbols for SAME70Q21B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# include +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !defined(SKIP_INTEGER_LITERALS) +# if defined(_U_) || defined(_L_) || defined(_UL_) +# error "Integer Literals macros already defined elsewhere" +# endif + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ +# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ +# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ + +#else /* Assembler */ + +# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +# define _L_(x) x /**< Assembler: Long integer literal constant value */ +# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ +/** @} end of Atmel Global Defines */ + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** CORTEX-M7 Processor Exceptions Numbers ******************************/ + Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ + PendSV_IRQn = -2, /**< -2 Pendable request for system service */ + SysTick_IRQn = -1, /**< -1 System Tick Timer */ +/****** SAME70Q21B specific Interrupt Numbers ***********************************/ + SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */ + UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */ + PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */ + PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */ + PIOC_IRQn = 12, /**< 12 Parallel Input/Output Controller (PIOC) */ + USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + USART2_IRQn = 15, /**< 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */ + PIOE_IRQn = 17, /**< 17 Parallel Input/Output Controller (PIOE) */ + HSMCI_IRQn = 18, /**< 18 High Speed MultiMedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 Serial Peripheral Interface (SPI0) */ + SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */ + TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */ + TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */ + TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */ + TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */ + TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */ + TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */ + AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */ + DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */ + PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */ + ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */ + USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */ + MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */ + MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */ + MCAN1_INT0_IRQn = 37, /**< 37 Controller Area Network (MCAN1) */ + MCAN1_INT1_IRQn = 38, /**< 38 Controller Area Network (MCAN1) */ + GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 Two-wire Interface High Speed (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 Serial Peripheral Interface (SPI1) */ + QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */ + UART3_IRQn = 45, /**< 45 Universal Asynchronous Receiver Transmitter (UART3) */ + UART4_IRQn = 46, /**< 46 Universal Asynchronous Receiver Transmitter (UART4) */ + TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */ + TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */ + TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */ + TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */ + TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */ + TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */ + AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */ + TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */ + ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */ + FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */ + SDRAMC_IRQn = 62, /**< 62 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */ + CCW_IRQn = 64, /**< 64 System Control Block (SCB) */ + CCF_IRQn = 65, /**< 65 System Control Block (SCB) */ + GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */ + IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */ + I2SC0_IRQn = 69, /**< 69 Inter-IC Sound Controller (I2SC0) */ + I2SC1_IRQn = 70, /**< 70 Inter-IC Sound Controller (I2SC1) */ + GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */ + GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */ + + PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */ +} IRQn_Type; +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + /* CORTEX-M7 handlers */ + void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ + void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ + void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ + void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + void* pvReservedC9; + void* pvReservedC8; + void* pvReservedC7; + void* pvReservedC6; + void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ + void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ + void* pvReservedC3; + void* pfnPendSV_Handler; /* -2 Pendable request for system service */ + void* pfnSysTick_Handler; /* -1 System Tick Timer */ + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */ + void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */ + void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */ + void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */ + void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */ + void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */ + void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */ + void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */ + void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */ + void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */ + void* pfnPIOC_Handler; /* 12 Parallel Input/Output Controller (PIOC) */ + void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ + void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ + void* pfnUSART2_Handler; /* 15 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ + void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */ + void* pfnPIOE_Handler; /* 17 Parallel Input/Output Controller (PIOE) */ + void* pfnHSMCI_Handler; /* 18 High Speed MultiMedia Card Interface (HSMCI) */ + void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */ + void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface (SPI0) */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */ + void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */ + void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */ + void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */ + void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */ + void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */ + void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */ + void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */ + void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */ + void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */ + void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */ + void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */ + void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */ + void* pfnMCAN1_INT0_Handler; /* 37 Controller Area Network (MCAN1) */ + void* pfnMCAN1_INT1_Handler; /* 38 Controller Area Network (MCAN1) */ + void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */ + void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */ + void* pfnTWIHS2_Handler; /* 41 Two-wire Interface High Speed (TWIHS2) */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface (SPI1) */ + void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */ + void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */ + void* pfnUART3_Handler; /* 45 Universal Asynchronous Receiver Transmitter (UART3) */ + void* pfnUART4_Handler; /* 46 Universal Asynchronous Receiver Transmitter (UART4) */ + void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */ + void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */ + void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */ + void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */ + void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */ + void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */ + void* pvReserved53; + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */ + void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */ + void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */ + void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */ + void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */ + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller (SDRAMC) */ + void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */ + void* pfnCCW_Handler; /* 64 System Control Block (SCB) */ + void* pfnCCF_Handler; /* 65 System Control Block (SCB) */ + void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */ + void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */ + void* pfnI2SC0_Handler; /* 69 Inter-IC Sound Controller (I2SC0) */ + void* pfnI2SC1_Handler; /* 70 Inter-IC Sound Controller (I2SC1) */ + void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */ + void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */ +} DeviceVectors; + +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS +/* CORTEX-M7 exception handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemoryManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ + +#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS +/* Peripherals interrupt handlers */ +void SUPC_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void WDT_Handler ( void ); +void PMC_Handler ( void ); +void EFC_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void HSMCI_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void SPI0_Handler ( void ); +void SSC_Handler ( void ); +void TC0_CH0_Handler ( void ); +void TC0_CH1_Handler ( void ); +void TC0_CH2_Handler ( void ); +void TC1_CH0_Handler ( void ); +void TC1_CH1_Handler ( void ); +void TC1_CH2_Handler ( void ); +void AFEC0_Handler ( void ); +void DACC_Handler ( void ); +void PWM0_Handler ( void ); +void ICM_Handler ( void ); +void ACC_Handler ( void ); +void USBHS_Handler ( void ); +void MCAN0_INT0_Handler ( void ); +void MCAN0_INT1_Handler ( void ); +void MCAN1_INT0_Handler ( void ); +void MCAN1_INT1_Handler ( void ); +void GMAC_Handler ( void ); +void AFEC1_Handler ( void ); +void TWIHS2_Handler ( void ); +void SPI1_Handler ( void ); +void QSPI_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void TC2_CH0_Handler ( void ); +void TC2_CH1_Handler ( void ); +void TC2_CH2_Handler ( void ); +void TC3_CH0_Handler ( void ); +void TC3_CH1_Handler ( void ); +void TC3_CH2_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void XDMAC_Handler ( void ); +void ISI_Handler ( void ); +void PWM1_Handler ( void ); +void FPU_Handler ( void ); +void SDRAMC_Handler ( void ); +void RSWDT_Handler ( void ); +void CCW_Handler ( void ); +void CCF_Handler ( void ); +void GMAC_Q1_Handler ( void ); +void GMAC_Q2_Handler ( void ); +void IXC_Handler ( void ); +void I2SC0_Handler ( void ); +void I2SC1_Handler ( void ); +void GMAC_Q3_Handler ( void ); +void GMAC_Q4_Handler ( void ); +void GMAC_Q5_Handler ( void ); +#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ +#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */ +#define __CM7_REV 0x0101 /**< CM7 Core Revision */ +#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /**< MPU present or not */ +#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ +#define __FPU_PRESENT 1 /**< FPU present or not */ +#define __FPU_DP 1 /**< Double Precision FPU */ +#define __ICACHE_PRESENT 1 /**< Instruction Cache present */ +#define __DCACHE_PRESENT 1 /**< Data Cache present */ +#define __ITCM_PRESENT 1 /**< Instruction TCM present */ +#define __DTCM_PRESENT 1 /**< Data TCM present */ +#define __DEBUG_LVL 1 +#define __TRACE_LVL 1 +#define __ARCH_ARM 1 +#define __ARCH_ARM_CORTEX_M 1 + +/* + * \brief CMSIS includes + */ +#include "core_cm7.h" +#if defined USE_CMSIS_INIT +#include "system_same70.h" +#endif /* USE_CMSIS_INIT */ + +/** \defgroup SAME70Q21B_api Peripheral Software API + * @{ + */ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70Q21B */ +/* ************************************************************************** */ +#include "component/acc.h" +#include "component/aes.h" +#include "component/afec.h" +#include "component/chipid.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gmac.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/i2sc.h" +#include "component/icm.h" +#include "component/isi.h" +#include "component/matrix.h" +#include "component/mcan.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/qspi.h" +#include "component/rstc.h" +#include "component/rswdt.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/sdramc.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/trng.h" +#include "component/twihs.h" +#include "component/uart.h" +#include "component/usart.h" +#include "component/usbhs.h" +#include "component/utmi.h" +#include "component/wdt.h" +#include "component/xdmac.h" +/** @} end of Peripheral Software API */ + +/** \addtogroup SAME70Q21B_id Peripheral Ids Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ +#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ +#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ +#define ID_PIOC ( 12) /**< \brief Parallel Input/Output Controller (PIOC) */ +#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ +#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ +#define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ +#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ +#define ID_PIOE ( 17) /**< \brief Parallel Input/Output Controller (PIOE) */ +#define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ +#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ +#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ +#define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ +#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ +#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ +#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ +#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ +#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ +#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ +#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ +#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ +#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ +#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ +#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ +#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ +#define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ +#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ +#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ +#define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ +#define ID_SPI1 ( 42) /**< \brief Serial Peripheral Interface (SPI1) */ +#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ +#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ +#define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ +#define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ +#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ +#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ +#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ +#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ +#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ +#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ +#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ +#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ +#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ +#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ +#define ID_SDRAMC ( 62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ +#define ID_I2SC0 ( 69) /**< \brief Inter-IC Sound Controller (I2SC0) */ +#define ID_I2SC1 ( 70) /**< \brief Inter-IC Sound Controller (I2SC1) */ + +#define ID_PERIPH_MAX ( 70) /**< \brief Number of peripheral IDs */ +/** @} end of Peripheral Ids Definitions */ + +/** \addtogroup SAME70Q21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */ +#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */ +#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */ +#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */ +#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */ +#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */ +#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */ +#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */ +#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */ +#define HSMCI_REGS ((hsmci_registers_t*)0x40000000) /**< \brief HSMCI Registers Address */ +#define I2SC0_REGS ((i2sc_registers_t*)0x4008c000) /**< \brief I2SC0 Registers Address */ +#define I2SC1_REGS ((i2sc_registers_t*)0x40090000) /**< \brief I2SC1 Registers Address */ +#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */ +#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */ +#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */ +#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */ +#define MCAN1_REGS ((mcan_registers_t*)0x40034000) /**< \brief MCAN1 Registers Address */ +#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */ +#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */ +#define PIOC_REGS ((pio_registers_t*)0x400e1200) /**< \brief PIOC Registers Address */ +#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */ +#define PIOE_REGS ((pio_registers_t*)0x400e1600) /**< \brief PIOE Registers Address */ +#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */ +#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */ +#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */ +#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */ +#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */ +#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */ +#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */ +#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */ +#define SDRAMC_REGS ((sdramc_registers_t*)0x40084000) /**< \brief SDRAMC Registers Address */ +#define SMC_REGS ((smc_registers_t*)0x40080000) /**< \brief SMC Registers Address */ +#define SPI0_REGS ((spi_registers_t*)0x40008000) /**< \brief SPI0 Registers Address */ +#define SPI1_REGS ((spi_registers_t*)0x40058000) /**< \brief SPI1 Registers Address */ +#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */ +#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */ +#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */ +#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */ +#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */ +#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */ +#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */ +#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */ +#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */ +#define TWIHS2_REGS ((twihs_registers_t*)0x40060000) /**< \brief TWIHS2 Registers Address */ +#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */ +#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */ +#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */ +#define UART3_REGS ((uart_registers_t*)0x400e1c00) /**< \brief UART3 Registers Address */ +#define UART4_REGS ((uart_registers_t*)0x400e1e00) /**< \brief UART4 Registers Address */ +#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */ +#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */ +#define USART2_REGS ((usart_registers_t*)0x4002c000) /**< \brief USART2 Registers Address */ +#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */ +#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */ +#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */ +#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */ +#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q21B_base Peripheral Base Address Definitions + * @{ + */ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */ +#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */ +#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */ +#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */ +#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */ +#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */ +#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */ +#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */ +#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */ +#define HSMCI_BASE_ADDRESS _UL_(0x40000000) /**< \brief HSMCI Base Address */ +#define I2SC0_BASE_ADDRESS _UL_(0x4008c000) /**< \brief I2SC0 Base Address */ +#define I2SC1_BASE_ADDRESS _UL_(0x40090000) /**< \brief I2SC1 Base Address */ +#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */ +#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */ +#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */ +#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */ +#define MCAN1_BASE_ADDRESS _UL_(0x40034000) /**< \brief MCAN1 Base Address */ +#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */ +#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */ +#define PIOC_BASE_ADDRESS _UL_(0x400e1200) /**< \brief PIOC Base Address */ +#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */ +#define PIOE_BASE_ADDRESS _UL_(0x400e1600) /**< \brief PIOE Base Address */ +#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */ +#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */ +#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */ +#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */ +#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */ +#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */ +#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */ +#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */ +#define SDRAMC_BASE_ADDRESS _UL_(0x40084000) /**< \brief SDRAMC Base Address */ +#define SMC_BASE_ADDRESS _UL_(0x40080000) /**< \brief SMC Base Address */ +#define SPI0_BASE_ADDRESS _UL_(0x40008000) /**< \brief SPI0 Base Address */ +#define SPI1_BASE_ADDRESS _UL_(0x40058000) /**< \brief SPI1 Base Address */ +#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */ +#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */ +#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */ +#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */ +#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */ +#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */ +#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */ +#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */ +#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */ +#define TWIHS2_BASE_ADDRESS _UL_(0x40060000) /**< \brief TWIHS2 Base Address */ +#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */ +#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */ +#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */ +#define UART3_BASE_ADDRESS _UL_(0x400e1c00) /**< \brief UART3 Base Address */ +#define UART4_BASE_ADDRESS _UL_(0x400e1e00) /**< \brief UART4 Base Address */ +#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */ +#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */ +#define USART2_BASE_ADDRESS _UL_(0x4002c000) /**< \brief USART2 Base Address */ +#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */ +#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */ +#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */ +#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */ +/** @} end of Peripheral Base Address Definitions */ + +/** \addtogroup SAME70Q21B_pio Peripheral Pio Definitions + * @{ + */ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#include "pio/same70q21b.h" +/** @} end of Peripheral Pio Definitions */ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ + +#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */ +#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */ +#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */ +#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */ +#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */ +#define IFLASH_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: flash */ +#define IFLASH_PAGE_SIZE _UL_( 512) +#define IFLASH_NB_OF_PAGES _UL_( 4096) + +#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */ +#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */ +#define IRAM_SIZE _UL_(0x00060000) /* 384kB Memory segment type: ram */ +#define EBI_CS0_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS1_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS2_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define EBI_CS3_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ +#define SDRAM_CS_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: other */ + +#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/ +#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/ +#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/ +#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/ +#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/ +#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/ +#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/ +#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/ +#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/ +#define EBI_CS0_ADDR _UL_(0x60000000) /**< EBI_CS0 base address (type: other)*/ +#define EBI_CS1_ADDR _UL_(0x61000000) /**< EBI_CS1 base address (type: other)*/ +#define EBI_CS2_ADDR _UL_(0x62000000) /**< EBI_CS2 base address (type: other)*/ +#define EBI_CS3_ADDR _UL_(0x63000000) /**< EBI_CS3 base address (type: other)*/ +#define SDRAM_CS_ADDR _UL_(0x70000000) /**< SDRAM_CS base address (type: other)*/ + +/* ************************************************************************** */ +/** DEVICE SIGNATURES FOR SAME70Q21B */ +/* ************************************************************************** */ +#define CHIP_JTAGID _UL_(0X05B3D03F) +#define CHIP_CIDR _UL_(0XA1020E01) +#define CHIP_EXID _UL_(0X00000002) + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME70Q21B */ +/* ************************************************************************** */ +#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) +#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */ +#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) +#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) +#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) +#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) +#define CHIP_FREQ_CPU_MAX _UL_(300000000) +#define CHIP_FREQ_XTAL_32K _UL_(32768) +#define CHIP_FREQ_XTAL_12M _UL_(12000000) +#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */ +#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */ +#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */ + + + +#ifdef __cplusplus +} +#endif + +/** @} end of SAME70Q21B definitions */ + + +#endif /* _SAME70Q21B_H_ */ + diff --git a/arch/arm/SAME70/SAME70B/mcu/inc/system_same70.h b/arch/arm/SAME70/SAME70B/mcu/inc/system_same70.h new file mode 100644 index 00000000..d673cb6d --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/inc/system_same70.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon device startup + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SYSTEM_SAME70_H_INCLUDED_ +#define _SYSTEM_SAME70_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_SAME70_H_INCLUDED */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j19b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j19b.c new file mode 100644 index 00000000..2b9a5b3e --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j19b.c @@ -0,0 +1,268 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j19b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j20b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j20b.c new file mode 100644 index 00000000..674262bf --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j20b.c @@ -0,0 +1,268 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j20b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j21b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j21b.c new file mode 100644 index 00000000..96f647cd --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70j21b.c @@ -0,0 +1,268 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j21b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pvReserved37 = (void*) (0UL), /* 37 Reserved */ + .pvReserved38 = (void*) (0UL), /* 38 Reserved */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pvReserved45 = (void*) (0UL), /* 45 Reserved */ + .pvReserved46 = (void*) (0UL), /* 46 Reserved */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n19b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n19b.c new file mode 100644 index 00000000..804f573a --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n19b.c @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n19b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n20b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n20b.c new file mode 100644 index 00000000..7cfdbc09 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n20b.c @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n20b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n21b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n21b.c new file mode 100644 index 00000000..9b7d0418 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70n21b.c @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n21b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q19b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q19b.c new file mode 100644 index 00000000..4dfdb1b8 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q19b.c @@ -0,0 +1,282 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q19b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 70 Inter-IC Sound Controller */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q20b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q20b.c new file mode 100644 index 00000000..8375d076 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q20b.c @@ -0,0 +1,282 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q20b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 70 Inter-IC Sound Controller */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q21b.c b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q21b.c new file mode 100644 index 00000000..70dccd41 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/startup_same70q21b.c @@ -0,0 +1,282 @@ +/** + * \file + * + * \brief GCC startup file for ATSAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M7 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN0_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCAN1_INT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_CH2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void FPU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCW_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CCF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void IXC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void I2SC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void GMAC_Q5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedC9 = (void*) (0UL), /* Reserved */ + .pvReservedC8 = (void*) (0UL), /* Reserved */ + .pvReservedC7 = (void*) (0UL), /* Reserved */ + .pvReservedC6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedC3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real-time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 Universal Asynchronous Receiver Transmitter */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 Universal Asynchronous Receiver Transmitter */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel Input/Output Controller */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel Input/Output Controller */ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel Input/Output Controller */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 Universal Synchronous Asynchronous Receiver Transmitter */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel Input/Output Controller */ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel Input/Output Controller */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 High Speed MultiMedia Card Interface */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two-wire Interface High Speed */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two-wire Interface High Speed */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_CH0_Handler = (void*) TC0_CH0_Handler, /* 23 Timer/Counter 0 Channel 0 */ + .pfnTC0_CH1_Handler = (void*) TC0_CH1_Handler, /* 24 Timer/Counter 0 Channel 1 */ + .pfnTC0_CH2_Handler = (void*) TC0_CH2_Handler, /* 25 Timer/Counter 0 Channel 2 */ + .pfnTC1_CH0_Handler = (void*) TC1_CH0_Handler, /* 26 Timer/Counter 1 Channel 0 */ + .pfnTC1_CH1_Handler = (void*) TC1_CH1_Handler, /* 27 Timer/Counter 1 Channel 1 */ + .pfnTC1_CH2_Handler = (void*) TC1_CH2_Handler, /* 28 Timer/Counter 1 Channel 2 */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front-End Controller */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital-to-Analog Converter Controller */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation Controller */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator Controller */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB High-Speed Interface */ + .pfnMCAN0_INT0_Handler = (void*) MCAN0_INT0_Handler, /* 35 Controller Area Network */ + .pfnMCAN0_INT1_Handler = (void*) MCAN0_INT1_Handler, /* 36 Controller Area Network */ + .pfnMCAN1_INT0_Handler = (void*) MCAN1_INT0_Handler, /* 37 Controller Area Network */ + .pfnMCAN1_INT1_Handler = (void*) MCAN1_INT1_Handler, /* 38 Controller Area Network */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Gigabit Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front-End Controller */ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two-wire Interface High Speed */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 Universal Asynchronous Receiver Transmitter */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 Universal Asynchronous Receiver Transmitter */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 Universal Asynchronous Receiver Transmitter */ + .pfnTC2_CH0_Handler = (void*) TC2_CH0_Handler, /* 47 Timer/Counter 2 Channel 0 */ + .pfnTC2_CH1_Handler = (void*) TC2_CH1_Handler, /* 48 Timer/Counter 2 Channel 1 */ + .pfnTC2_CH2_Handler = (void*) TC2_CH2_Handler, /* 49 Timer/Counter 2 Channel 2 */ + .pfnTC3_CH0_Handler = (void*) TC3_CH0_Handler, /* 50 Timer/Counter 3 Channel 0 */ + .pfnTC3_CH1_Handler = (void*) TC3_CH1_Handler, /* 51 Timer/Counter 3 Channel 1 */ + .pfnTC3_CH2_Handler = (void*) TC3_CH2_Handler, /* 52 Timer/Counter 3 Channel 2 */ + .pvReserved53 = (void*) (0UL), /* 53 Reserved */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Number Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 Extensible DMA Controller */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Image Sensor Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation Controller */ + .pfnFPU_Handler = (void*) FPU_Handler, /* 61 Floating Point Unit */ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler, /* 63 Reinforced Safety Watchdog Timer */ + .pfnCCW_Handler = (void*) CCW_Handler, /* 64 System Control Block */ + .pfnCCF_Handler = (void*) CCF_Handler, /* 65 System Control Block */ + .pfnGMAC_Q1_Handler = (void*) GMAC_Q1_Handler, /* 66 Gigabit Ethernet MAC */ + .pfnGMAC_Q2_Handler = (void*) GMAC_Q2_Handler, /* 67 Gigabit Ethernet MAC */ + .pfnIXC_Handler = (void*) IXC_Handler, /* 68 Floating Point Unit */ + .pfnI2SC0_Handler = (void*) I2SC0_Handler, /* 69 Inter-IC Sound Controller */ + .pfnI2SC1_Handler = (void*) I2SC1_Handler, /* 70 Inter-IC Sound Controller */ + .pfnGMAC_Q3_Handler = (void*) GMAC_Q3_Handler, /* 71 Gigabit Ethernet MAC */ + .pfnGMAC_Q4_Handler = (void*) GMAC_Q4_Handler, /* 72 Gigabit Ethernet MAC */ + .pfnGMAC_Q5_Handler = (void*) GMAC_Q5_Handler /* 73 Gigabit Ethernet MAC */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70j19b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j19b.c new file mode 100644 index 00000000..b544e90c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j19b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j19b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70j20b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j20b.c new file mode 100644 index 00000000..bb304dfa --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j20b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j20b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70j21b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j21b.c new file mode 100644 index 00000000..a695117b --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70j21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70J21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70j21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70n19b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n19b.c new file mode 100644 index 00000000..d9c37b22 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n19b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n19b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70n20b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n20b.c new file mode 100644 index 00000000..0ab47f14 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n20b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n20b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70n21b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n21b.c new file mode 100644 index 00000000..225d767a --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70n21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70N21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70n21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70q19b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q19b.c new file mode 100644 index 00000000..f2414f84 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q19b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q19B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q19b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70q20b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q20b.c new file mode 100644 index 00000000..ecb1c965 --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q20b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q20B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q20b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/arm/SAME70/SAME70B/mcu/src/system_same70q21b.c b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q21b.c new file mode 100644 index 00000000..a4bf566c --- /dev/null +++ b/arch/arm/SAME70/SAME70B/mcu/src/system_same70q21b.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief System configuration file for ATSAME70Q21B + * + * Copyright (c) 2020 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#include "same70q21b.h" + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +extern "C" { +#endif +/* *INDENT-ON* */ +/** \endcond */ + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (12000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * \brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** \cond 0 */ +/* *INDENT-OFF* */ +#ifdef __cplusplus +} +#endif +/* *INDENT-ON* */ +/** \endcond */ diff --git a/arch/mcu-lookup.toml b/arch/mcu-lookup.toml deleted file mode 100644 index 34800af9..00000000 --- a/arch/mcu-lookup.toml +++ /dev/null @@ -1,21 +0,0 @@ -[cfg.mcu] -samd21j18a = "${ESF_DIR}/arch/arm/SAMD21/SAMD21A/cfg/samd21j18a.toml" - -[make.mcu] -samd21e15a = "arch.arm.samd21a.samd21e15a" -samd21e16a = "arch.arm.samd21a.samd21e16a" -samd21e17a = "arch.arm.samd21a.samd21e17a" -samd21e18a = "arch.arm.samd21a.samd21e18a" -samd21g15a = "arch.arm.samd21a.samd21g15a" -samd21g16a = "arch.arm.samd21a.samd21g16a" -samd21g17a = "arch.arm.samd21a.samd21g17a" -samd21g17au = "arch.arm.samd2a1.samd21g17au" -samd21g18a = "arch.arm.samd21a.samd21g18a" -samd21g18au = "arch.arm.samd21a.samd21g18au" -samd21j15a = "arch.arm.samd21a.samd21j15a" -samd21j16a = "arch.arm.samd21a.samd21j16a" -samd21j17a = "arch.arm.samd21a.samd21j17a" -samd21j18a = "arch.arm.samd21a.samd21j18a" - -[sym.mcu] -# To be implemented \ No newline at end of file diff --git a/arch/make-manifest.toml b/manifest/make-manifest.toml similarity index 100% rename from arch/make-manifest.toml rename to manifest/make-manifest.toml diff --git a/manifest/target-manifest.toml b/manifest/target-manifest.toml new file mode 100644 index 00000000..eddee0f1 --- /dev/null +++ b/manifest/target-manifest.toml @@ -0,0 +1,71 @@ +[target.make] +# samd21 family +# samd21a series +samd21e15a = "arch.arm.samd21a.samd21e15a" +samd21e16a = "arch.arm.samd21a.samd21e16a" +samd21e17a = "arch.arm.samd21a.samd21e17a" +samd21e18a = "arch.arm.samd21a.samd21e18a" +samd21g15a = "arch.arm.samd21a.samd21g15a" +samd21g16a = "arch.arm.samd21a.samd21g16a" +samd21g17a = "arch.arm.samd21a.samd21g17a" +samd21g17au = "arch.arm.samd2a1.samd21g17au" +samd21g18a = "arch.arm.samd21a.samd21g18a" +samd21g18au = "arch.arm.samd21a.samd21g18au" +samd21j15a = "arch.arm.samd21a.samd21j15a" +samd21j16a = "arch.arm.samd21a.samd21j16a" +samd21j17a = "arch.arm.samd21a.samd21j17a" +samd21j18a = "arch.arm.samd21a.samd21j18a" +# same54 family +# same54n/p series +same54n19a = "arch.arm.same54.same54n19a" +same54n20a = "arch.arm.same54.same54n20a" +same54p19a = "arch.arm.same54.same54p19a" +same54p20a = "arch.arm.same54.same54p20a" +# same70 family +# same70a series +same70j19a = "arch.arm.same70.same70a.same70j19a" +same70j20a = "arch.arm.same70.same70a.same70j20a" +same70j21a = "arch.arm.same70.same70a.same70j21a" +same70n19a = "arch.arm.same70.same70a.same70n19a" +same70n20a = "arch.arm.same70.same70a.same70n20a" +same70n21a = "arch.arm.same70.same70a.same70n21a" +same70q19a = "arch.arm.same70.same70a.same70q19a" +same70q20a = "arch.arm.same70.same70a.same70q20a" +same70q21a = "arch.arm.same70.same70a.same70q21a" + +# target.cfg contains the file locations for all config manifests for all mcus +# target.cfg contains things like symlinks +[target.cfg] +# samd21 family +# samd21a series +samd21e15a = "arch/arm/SAMD21/SAMD21A/cfg/samd21e15a.toml" +samd21e16a = "arch/arm/SAMD21/SAMD21A/cfg/samd21e16a.toml" +samd21e17a = "arch/arm/SAMD21/SAMD21A/cfg/samd21e17a.toml" +samd21e18a = "arch/arm/SAMD21/SAMD21A/cfg/samd21e18a.toml" +samd21g15a = "arch/arm/SAMD21/SAMD21A/cfg/samd21g15a.toml" +samd21g16a = "arch/arm/SAMD21/SAMD21A/cfg/samd21g16a.toml" +samd21g17a = "arch/arm/SAMD21/SAMD21A/cfg/samd21g17a.toml" +samd21g17au = "arch/arm/SAMD21/SAMD21A/cfg/samd21g17au.toml" +samd21g18a = "arch/arm/SAMD21/SAMD21A/cfg/samd21g18a.toml" +samd21g18au = "arch/arm/SAMD21/SAMD21A/cfg/samd21g18au.toml" +samd21j15a = "arch/arm/SAMD21/SAMD21A/cfg/samd21j15a.toml" +samd21j16a = "arch/arm/SAMD21/SAMD21A/cfg/samd21j16a.toml" +samd21j17a = "arch/arm/SAMD21/SAMD21A/cfg/samd21j17a.toml" +samd21j18a = "arch/arm/SAMD21/SAMD21A/cfg/samd21j18a.toml" +# same54 family +# same54a series +same54n19a = "arch/arm/SAME54/SAMD54A/cfg/same54n19a.toml" +same54n20a = "arch/arm/SAME54/SAMD54A/cfg/same54n20a.toml" +same54p19a = "arch/arm/SAME54/SAMD54A/cfg/same54p19a.toml" +same54p20a = "arch/arm/SAME54/SAMD54A/cfg/same54p20a.toml" +# same70 family +# same70a series +same70j19 = "arch/arm/SAME70/SAMD70A/cfg/same70j19a.toml" +same70j20 = "arch/arm/SAME70/SAMD70A/cfg/same70j20a.toml" +same70j21 = "arch/arm/SAME70/SAMD70A/cfg/same70j21a.toml" +same70n19 = "arch/arm/SAME70/SAMD70A/cfg/same70n19a.toml" +same70n20 = "arch/arm/SAME70/SAMD70A/cfg/same70n19a.toml" +same70n21 = "arch/arm/SAME70/SAMD70A/cfg/same70n20a.toml" +same70q19 = "arch/arm/SAME70/SAMD70A/cfg/same70q21a.toml" +same70q20 = "arch/arm/SAME70/SAMD70A/cfg/same70q20a.toml" +same70q21 = "arch/arm/SAME70/SAMD70A/cfg/same70q21a.toml"