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fuck windows line endings honestly

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stable
Penguin 3 years ago
parent 6758c57836
commit bdabdde746
140 changed files with 118215 additions and 118044 deletions
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LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;
[PreviousUsedMakefileFiles] [PreviousUsedMakefileFiles]
SourceFiles=Core/Src/main.c;Core/Src/stm32l4xx_it.c;Core/Src/stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;;; SourceFiles=Core/Src/main.c;Core/Src/stm32l4xx_it.c;Core/Src/stm32l4xx_hal_msp.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Core/Src/system_stm32l4xx.c;;;
HeaderPath=Drivers/STM32L4xx_HAL_Driver/Inc;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L4xx/Include;Drivers/CMSIS/Include;Core/Inc; HeaderPath=Drivers/STM32L4xx_HAL_Driver/Inc;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L4xx/Include;Drivers/CMSIS/Include;Core/Inc;
CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER; CDefines=USE_HAL_DRIVER;STM32L432xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
[PreviousGenFiles] [PreviousGenFiles]
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Core/Inc/main.h
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/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file : main.h * @file : main.h
* @brief : Header for main.c file. * @brief : Header for main.c file.
* This file contains the common defines of the application. * This file contains the common defines of the application.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2022 STMicroelectronics. * Copyright (c) 2022 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H #ifndef __MAIN_H
#define __MAIN_H #define __MAIN_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h" #include "stm32l4xx_hal.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */ /* USER CODE BEGIN ET */
/* USER CODE END ET */ /* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */ /* USER CODE BEGIN EC */
/* USER CODE END EC */ /* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
/* USER CODE END EM */ /* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/ /* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void); void Error_Handler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/
#define MCO_Pin GPIO_PIN_0 #define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOA #define MCO_GPIO_Port GPIOA
#define VCP_TX_Pin GPIO_PIN_2 #define VCP_TX_Pin GPIO_PIN_2
#define VCP_TX_GPIO_Port GPIOA #define VCP_TX_GPIO_Port GPIOA
#define SWDIO_Pin GPIO_PIN_13 #define SWDIO_Pin GPIO_PIN_13
#define SWDIO_GPIO_Port GPIOA #define SWDIO_GPIO_Port GPIOA
#define SWCLK_Pin GPIO_PIN_14 #define SWCLK_Pin GPIO_PIN_14
#define SWCLK_GPIO_Port GPIOA #define SWCLK_GPIO_Port GPIOA
#define VCP_RX_Pin GPIO_PIN_15 #define VCP_RX_Pin GPIO_PIN_15
#define VCP_RX_GPIO_Port GPIOA #define VCP_RX_GPIO_Port GPIOA
#define LD3_Pin GPIO_PIN_3 #define LD3_Pin GPIO_PIN_3
#define LD3_GPIO_Port GPIOB #define LD3_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */ /* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */ /* USER CODE END Private defines */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __MAIN_H */ #endif /* __MAIN_H */

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Core/Inc/stm32l4xx_hal_conf.h
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@ -1,482 +1,482 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_conf.h * @file stm32l4xx_hal_conf.h
* @author MCD Application Team * @author MCD Application Team
* @brief HAL configuration template file. * @brief HAL configuration template file.
* This file should be copied to the application folder and renamed * This file should be copied to the application folder and renamed
* to stm32l4xx_hal_conf.h. * to stm32l4xx_hal_conf.h.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CONF_H #ifndef STM32L4xx_HAL_CONF_H
#define STM32L4xx_HAL_CONF_H #define STM32L4xx_HAL_CONF_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */ /* ########################## Module Selection ############################## */
/** /**
* @brief This is the list of modules to be used in the HAL driver * @brief This is the list of modules to be used in the HAL driver
*/ */
#define HAL_MODULE_ENABLED #define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */ /*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */ /*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */ /*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */ /*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DMA2D_MODULE_ENABLED */ /*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */ /*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */ /*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */ /*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */ /*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */ /*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */ /*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LTDC_MODULE_ENABLED */ /*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */ /*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */ /*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */ /*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_PKA_MODULE_ENABLED */ /*#define HAL_PKA_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */ /*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */ /*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */ /*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */ /*#define HAL_SWPMI_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED
/*#define HAL_TSC_MODULE_ENABLED */ /*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_EXTI_MODULE_ENABLED */ /*#define HAL_EXTI_MODULE_ENABLED */
/*#define HAL_PSSI_MODULE_ENABLED */ /*#define HAL_PSSI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/ /* ########################## Oscillator Values adaptation ####################*/
/** /**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency * This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
* @brief Internal Multiple Speed oscillator (MSI) default value. * @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset. * This value is the default MSI range value after Reset.
*/ */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
/** /**
* @brief Internal High Speed oscillator (HSI) value. * @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency * This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL). * (when HSI is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to * This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations. * which is subject to manufacturing process variations.
*/ */
#if !defined (HSI48_VALUE) #if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. #define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/ The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */ #endif /* HSI48_VALUE */
/** /**
* @brief Internal Low Speed oscillator (LSI) value. * @brief Internal Low Speed oscillator (LSI) value.
*/ */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature.*/ in voltage and temperature.*/
/** /**
* @brief External Low Speed oscillator (LSE) value. * @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency * This value is used by the UART, RTC HAL module to compute the system frequency
*/ */
#if !defined (LSE_VALUE) #if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT) #if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
* @brief External clock source for SAI1 peripheral * @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency. * frequency.
*/ */
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) #if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/ #define EXTERNAL_SAI1_CLOCK_VALUE 2097000U /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/** /**
* @brief External clock source for SAI2 peripheral * @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency. * frequency.
*/ */
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) #if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/ #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/
#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */ === you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */ /* ########################### System Configuration ######################### */
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ #define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 0U #define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U #define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**
* @brief Uncomment the line below to expanse the "assert_param" macro in the * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code * HAL drivers code
*/ */
/* #define USE_FULL_ASSERT 1U */ /* #define USE_FULL_ASSERT 1U */
/* ################## Register callback feature configuration ############### */ /* ################## Register callback feature configuration ############### */
/** /**
* @brief Set below the peripheral configuration to "1U" to add the support * @brief Set below the peripheral configuration to "1U" to add the support
* of HAL callback registration/deregistration feature for the HAL * of HAL callback registration/deregistration feature for the HAL
* driver(s). This allows user application to provide specific callback * driver(s). This allows user application to provide specific callback
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
* the default weak callback functions (see each stm32l4xx_hal_ppp.h file * the default weak callback functions (see each stm32l4xx_hal_ppp.h file
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
* for each PPP peripheral). * for each PPP peripheral).
*/ */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U #define USE_HAL_ADC_REGISTER_CALLBACKS 0U
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U #define USE_HAL_CAN_REGISTER_CALLBACKS 0U
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U #define USE_HAL_COMP_REGISTER_CALLBACKS 0U
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U #define USE_HAL_DAC_REGISTER_CALLBACKS 0U
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U #define USE_HAL_DSI_REGISTER_CALLBACKS 0U
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U #define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U #define USE_HAL_HASH_REGISTER_CALLBACKS 0U
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U #define USE_HAL_HCD_REGISTER_CALLBACKS 0U
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U #define USE_HAL_I2C_REGISTER_CALLBACKS 0U
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U #define USE_HAL_MMC_REGISTER_CALLBACKS 0U
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U #define USE_HAL_OSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U #define USE_HAL_PCD_REGISTER_CALLBACKS 0U
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U #define USE_HAL_RNG_REGISTER_CALLBACKS 0U
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U #define USE_HAL_RTC_REGISTER_CALLBACKS 0U
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U #define USE_HAL_SAI_REGISTER_CALLBACKS 0U
#define USE_HAL_SD_REGISTER_CALLBACKS 0U #define USE_HAL_SD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U #define USE_HAL_SPI_REGISTER_CALLBACKS 0U
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U #define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U #define USE_HAL_TIM_REGISTER_CALLBACKS 0U
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U #define USE_HAL_TSC_REGISTER_CALLBACKS 0U
#define USE_HAL_UART_REGISTER_CALLBACKS 0U #define USE_HAL_UART_REGISTER_CALLBACKS 0U
#define USE_HAL_USART_REGISTER_CALLBACKS 0U #define USE_HAL_USART_REGISTER_CALLBACKS 0U
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver * Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver * Deactivated: CRC code cleaned from driver
*/ */
#define USE_SPI_CRC 0U #define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/** /**
* @brief Include module's header file * @brief Include module's header file
*/ */
#ifdef HAL_RCC_MODULE_ENABLED #ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h" #include "stm32l4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */ #endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h" #include "stm32l4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED #ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h" #include "stm32l4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */ #endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED #ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h" #include "stm32l4xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */ #endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED #ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h" #include "stm32l4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */ #endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED #ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h" #include "stm32l4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */ #endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED #ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h" #include "stm32l4xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */ #endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED #ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "Legacy/stm32l4xx_hal_can_legacy.h" #include "Legacy/stm32l4xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED #ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h" #include "stm32l4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */ #endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED #ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h" #include "stm32l4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */ #endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED #ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h" #include "stm32l4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */ #endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED #ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h" #include "stm32l4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */ #endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED #ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h" #include "stm32l4xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */ #endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED #ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h" #include "stm32l4xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */ #endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED #ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h" #include "stm32l4xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */ #endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED #ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32l4xx_hal_exti.h" #include "stm32l4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */ #endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED #ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h" #include "stm32l4xx_hal_gfxmmu.h"
#endif /* HAL_GFXMMU_MODULE_ENABLED */ #endif /* HAL_GFXMMU_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED #ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h" #include "stm32l4xx_hal_firewall.h"
#endif /* HAL_FIREWALL_MODULE_ENABLED */ #endif /* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED #ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h" #include "stm32l4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */ #endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED #ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h" #include "stm32l4xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */ #endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED #ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h" #include "stm32l4xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */ #endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED #ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h" #include "stm32l4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */ #endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED #ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h" #include "stm32l4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */ #endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED #ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h" #include "stm32l4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */ #endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED #ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h" #include "stm32l4xx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */ #endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED #ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h" #include "stm32l4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */ #endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED #ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h" #include "stm32l4xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */ #endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED #ifdef HAL_MMC_MODULE_ENABLED
#include "stm32l4xx_hal_mmc.h" #include "stm32l4xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */ #endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED #ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h" #include "stm32l4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */ #endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED #ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h" #include "stm32l4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */ #endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED #ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h" #include "stm32l4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */ #endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED #ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h" #include "stm32l4xx_hal_ospi.h"
#endif /* HAL_OSPI_MODULE_ENABLED */ #endif /* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED #ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h" #include "stm32l4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */ #endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED #ifdef HAL_PKA_MODULE_ENABLED
#include "stm32l4xx_hal_pka.h" #include "stm32l4xx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */ #endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_PSSI_MODULE_ENABLED #ifdef HAL_PSSI_MODULE_ENABLED
#include "stm32l4xx_hal_pssi.h" #include "stm32l4xx_hal_pssi.h"
#endif /* HAL_PSSI_MODULE_ENABLED */ #endif /* HAL_PSSI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED #ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h" #include "stm32l4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */ #endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED #ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h" #include "stm32l4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */ #endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED #ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h" #include "stm32l4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */ #endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED #ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h" #include "stm32l4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */ #endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED #ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h" #include "stm32l4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */ #endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED #ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h" #include "stm32l4xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */ #endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED #ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h" #include "stm32l4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ #endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED #ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h" #include "stm32l4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */ #endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED #ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h" #include "stm32l4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */ #endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED #ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h" #include "stm32l4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */ #endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED #ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h" #include "stm32l4xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */ #endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED #ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h" #include "stm32l4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */ #endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED #ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h" #include "stm32l4xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */ #endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED #ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h" #include "stm32l4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */ #endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED #ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h" #include "stm32l4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */ #endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED #ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h" #include "stm32l4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */ #endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT #ifdef USE_FULL_ASSERT
/** /**
* @brief The assert_param macro is used for function's parameters check. * @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function * @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source * which reports the name of the source file and the source
* line number of the call that failed. * line number of the call that failed.
* If expr is true, it returns no value. * If expr is true, it returns no value.
* @retval None * @retval None
*/ */
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */ /* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line); void assert_failed(uint8_t *file, uint32_t line);
#else #else
#define assert_param(expr) ((void)0U) #define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */ #endif /* USE_FULL_ASSERT */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32L4xx_HAL_CONF_H */ #endif /* STM32L4xx_HAL_CONF_H */

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Core/Inc/stm32l4xx_it.h
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/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_it.h * @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers. * @brief This file contains the headers of the interrupt handlers.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2022 STMicroelectronics. * Copyright (c) 2022 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H #ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H #define __STM32L4xx_IT_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */ /* USER CODE BEGIN ET */
/* USER CODE END ET */ /* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */ /* USER CODE BEGIN EC */
/* USER CODE END EC */ /* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
/* USER CODE END EM */ /* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/ /* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void); void NMI_Handler(void);
void HardFault_Handler(void); void HardFault_Handler(void);
void MemManage_Handler(void); void MemManage_Handler(void);
void BusFault_Handler(void); void BusFault_Handler(void);
void UsageFault_Handler(void); void UsageFault_Handler(void);
void SVC_Handler(void); void SVC_Handler(void);
void DebugMon_Handler(void); void DebugMon_Handler(void);
void PendSV_Handler(void); void PendSV_Handler(void);
void SysTick_Handler(void); void SysTick_Handler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32L4xx_IT_H */ #endif /* __STM32L4xx_IT_H */

695
Core/Src/main.c
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/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file : main.c * @file : main.c
* @brief : Main program body * @brief : Main program body
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2022 STMicroelectronics. * Copyright (c) 2022 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */ /* USER CODE BEGIN PTD */
/* USER CODE END PTD */ /* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */ /* USER CODE BEGIN PD */
/* USER CODE END PD */ /* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */ /* USER CODE BEGIN PM */
/* USER CODE END PM */ /* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef htim2; TIM_HandleTypeDef htim2;
UART_HandleTypeDef huart2; UART_HandleTypeDef huart2;
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
/* USER CODE END PV */ /* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void); void SystemClock_Config(void);
static void MX_GPIO_Init(void); static void MX_GPIO_Init(void);
static void MX_TIM2_Init(void); static void MX_TIM2_Init(void);
static void MX_USART2_UART_Init(void); static void MX_USART2_UART_Init(void);
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
void setPWM(TIM_HandleTypeDef timer, uint32_t channel, uint8_t duty_cycle_as_percent); void setPWM(TIM_HandleTypeDef *timer, uint32_t channel, uint8_t duty_cycle_as_percent);
/* USER CODE END PFP */ /* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
/** /**
* @brief The application entry point. * @brief The application entry point.
* @retval int * @retval int
*/ */
int main(void) int main(void)
{ {
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/ /* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init(); HAL_Init();
/* USER CODE BEGIN Init */ /* USER CODE BEGIN Init */
/* USER CODE END Init */ /* USER CODE END Init */
/* Configure the system clock */ /* Configure the system clock */
SystemClock_Config(); SystemClock_Config();
/* USER CODE BEGIN SysInit */ /* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */ /* USER CODE END SysInit */
/* Initialize all configured peripherals */ /* Initialize all configured peripherals */
MX_GPIO_Init(); MX_GPIO_Init();
MX_TIM2_Init(); MX_TIM2_Init();
MX_USART2_UART_Init(); MX_USART2_UART_Init();
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
uint8_t buff[256] = {'\0'}; uint8_t buff[256] = {'\0'};
sprintf(buff, "Hello Worldblahblahfjdslkfjlasdfj\r\n"); sprintf(buff, "Hello Worldblahblahfjdslkfjlasdfj\r\n");
HAL_UART_Transmit(&huart2, "...\r\n", sizeof("...\r\n"), 100); HAL_UART_Transmit(&huart2, "...\r\n", sizeof("...\r\n"), 100);
HAL_UART_Transmit(&huart2, buff, sizeof(buff), 100); HAL_UART_Transmit(&huart2, buff, sizeof(buff), 100);
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2); HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4); HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
// setPWM(htim2, TIM_CHANNEL_2, 50); // setPWM(htim2, TIM_CHANNEL_2, 50);
// setPWM(htim2, TIM_CHANNEL_4, 25); // setPWM(htim2, TIM_CHANNEL_4, 25);
/* USER CODE END 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* Infinite loop */ /* USER CODE BEGIN WHILE */
/* USER CODE BEGIN WHILE */ while (1)
while (1) {
{ /* USER CODE END WHILE */
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
/* USER CODE BEGIN 3 */ }
} /* USER CODE END 3 */
/* USER CODE END 3 */ }
}
/**
/** * @brief System Clock Configuration
* @brief System Clock Configuration * @retval None
* @retval None */
*/ void SystemClock_Config(void)
void SystemClock_Config(void) {
{ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Configure the main internal regulator output voltage
/** Configure the main internal regulator output voltage */
*/ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
{ Error_Handler();
Error_Handler(); }
}
/** Configure LSE Drive Capability
/** Configure LSE Drive Capability */
*/ HAL_PWR_EnableBkUpAccess();
HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
/** Initializes the RCC Oscillators according to the specified parameters
/** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure.
* in the RCC_OscInitTypeDef structure. */
*/ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSIState = RCC_MSI_ON; RCC_OscInitStruct.MSICalibrationValue = 0;
RCC_OscInitStruct.MSICalibrationValue = 0; RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLM = 1; RCC_OscInitStruct.PLL.PLLN = 16;
RCC_OscInitStruct.PLL.PLLN = 16; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
{ Error_Handler();
Error_Handler(); }
}
/** Initializes the CPU, AHB and APB buses clocks
/** Initializes the CPU, AHB and APB buses clocks */
*/ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) Error_Handler();
{ }
Error_Handler();
} /** Enable MSI Auto calibration
*/
/** Enable MSI Auto calibration HAL_RCCEx_EnableMSIPLLMode();
*/ }
HAL_RCCEx_EnableMSIPLLMode();
} /**
* @brief TIM2 Initialization Function
/** * @param None
* @brief TIM2 Initialization Function * @retval None
* @param None */
* @retval None static void MX_TIM2_Init(void)
*/ {
static void MX_TIM2_Init(void)
{ /* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0}; /* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
/* USER CODE END TIM2_Init 1 */ htim2.Init.Prescaler = 127;
htim2.Instance = TIM2; htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
htim2.Init.Prescaler = 127; htim2.Init.Period = 499;
htim2.Init.CounterMode = TIM_COUNTERMODE_UP; htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim2.Init.Period = 499; htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; {
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) Error_Handler();
{ }
Error_Handler(); sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
} sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; {
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) Error_Handler();
{ }
Error_Handler(); sConfigOC.OCMode = TIM_OCMODE_PWM1;
} sConfigOC.Pulse = 250;
sConfigOC.OCMode = TIM_OCMODE_PWM1; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.Pulse = 250; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; {
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) Error_Handler();
{ }
Error_Handler(); sConfigOC.Pulse = 125;
} if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
sConfigOC.Pulse = 125; {
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) Error_Handler();
{ }
Error_Handler(); /* USER CODE BEGIN TIM2_Init 2 */
}
/* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
/* USER CODE END TIM2_Init 2 */ }
HAL_TIM_MspPostInit(&htim2);
/**
} * @brief USART2 Initialization Function
* @param None
/** * @retval None
* @brief USART2 Initialization Function */
* @param None static void MX_USART2_UART_Init(void)
* @retval None {
*/
static void MX_USART2_UART_Init(void) /* USER CODE BEGIN USART2_Init 0 */
{
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 0 */
/* USER CODE END USART2_Init 1 */
/* USER CODE BEGIN USART2_Init 1 */ huart2.Instance = USART2;
huart2.Init.BaudRate = 115200;
/* USER CODE END USART2_Init 1 */ huart2.Init.WordLength = UART_WORDLENGTH_8B;
huart2.Instance = USART2; huart2.Init.StopBits = UART_STOPBITS_1;
huart2.Init.BaudRate = 115200; huart2.Init.Parity = UART_PARITY_NONE;
huart2.Init.WordLength = UART_WORDLENGTH_8B; huart2.Init.Mode = UART_MODE_TX_RX;
huart2.Init.StopBits = UART_STOPBITS_1; huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart2.Init.Parity = UART_PARITY_NONE; huart2.Init.OverSampling = UART_OVERSAMPLING_16;
huart2.Init.Mode = UART_MODE_TX_RX; huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
huart2.Init.OverSampling = UART_OVERSAMPLING_16; if (HAL_UART_Init(&huart2) != HAL_OK)
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; {
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; Error_Handler();
if (HAL_UART_Init(&huart2) != HAL_OK) }
{ /* USER CODE BEGIN USART2_Init 2 */
Error_Handler();
} /* USER CODE END USART2_Init 2 */
/* USER CODE BEGIN USART2_Init 2 */ }
/* USER CODE END USART2_Init 2 */ /**
* @brief GPIO Initialization Function
} * @param None
* @retval None
/** */
* @brief GPIO Initialization Function static void MX_GPIO_Init(void)
* @param None {
* @retval None GPIO_InitTypeDef GPIO_InitStruct = {0};
*/
static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */
{ __HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct = {0}; __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE(); /*Configure GPIO pin Output Level */
__HAL_RCC_GPIOA_CLK_ENABLE(); HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8 | GPIO_PIN_9, GPIO_PIN_RESET);
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
/*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD3_GPIO_Port, LD3_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8|GPIO_PIN_9, GPIO_PIN_RESET);
/*Configure GPIO pins : PA8 PA9 */
/*Configure GPIO pin Output Level */ GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9;
HAL_GPIO_WritePin(LD3_GPIO_Port, LD3_Pin, GPIO_PIN_RESET); GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
/*Configure GPIO pins : PA8 PA9 */ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; /*Configure GPIO pin : LD3_Pin */
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Pin = LD3_Pin;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
/*Configure GPIO pin : LD3_Pin */ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Pin = LD3_Pin; HAL_GPIO_Init(LD3_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; }
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; /* USER CODE BEGIN 4 */
HAL_GPIO_Init(LD3_GPIO_Port, &GPIO_InitStruct); void setPWM(TIM_HandleTypeDef *timer, uint32_t channel, uint8_t dc_percent)
{
} HAL_TIM_PWM_Stop(timer, channel);
TIM_OC_InitTypeDef sConfigOC;
/* USER CODE BEGIN 4 */ timer->HAL_TIM_PWM_Init(timer);
void setPWM(TIM_HandleTypeDef timer, uint32_t channel, uint8_t duty_cycle_as_percent)
{ sConfigOC.OCMode = TIM_OCMODE_PWM1;
HAL_TIM_PWM_Stop(&timer, channel); sConfigOC.Pulse = (uint32_t)((duty_cycle_as_percent * timer.Init.Period) / 100.0f);
TIM_OC_InitTypeDef sConfigOC; HAL_TIM_PWM_ConfigChannel(timer, &sConfigOC, channel);
HAL_TIM_PWM_Init(&timer); HAL_TIM_PWM_Start(timer, channel);
}
/* USER CODE END 4 */
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = (uint32_t)((duty_cycle_as_percent * timer.Init.Period) / 100.0f); /**
HAL_TIM_PWM_ConfigChannel(&timer, &sConfigOC, channel); * @brief This function is executed in case of error occurrence.
HAL_TIM_PWM_Start(&timer, channel); * @retval None
*/
} void Error_Handler(void)
/* USER CODE END 4 */ {
/* USER CODE BEGIN Error_Handler_Debug */
/** /* User can add his own implementation to report the HAL error return state */
* @brief This function is executed in case of error occurrence. __disable_irq();
* @retval None while (1)
*/ {
void Error_Handler(void) }
{ /* USER CODE END Error_Handler_Debug */
/* USER CODE BEGIN Error_Handler_Debug */ }
/* User can add his own implementation to report the HAL error return state */
__disable_irq(); #ifdef USE_FULL_ASSERT
while (1) /**
{ * @brief Reports the name of the source file and the source line number
} * where the assert_param error has occurred.
/* USER CODE END Error_Handler_Debug */ * @param file: pointer to the source file name
} * @param line: assert_param error line source number
* @retval None
#ifdef USE_FULL_ASSERT */
/** void assert_failed(uint8_t *file, uint32_t line)
* @brief Reports the name of the source file and the source line number {
* where the assert_param error has occurred. /* USER CODE BEGIN 6 */
* @param file: pointer to the source file name /* User can add his own implementation to report the file name and line number,
* @param line: assert_param error line source number ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
* @retval None /* USER CODE END 6 */
*/ }
void assert_failed(uint8_t *file, uint32_t line) #endif /* USE_FULL_ASSERT */
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */

474
Core/Src/stm32l4xx_hal_msp.c
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@ -1,237 +1,237 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_msp.c * @file stm32l4xx_hal_msp.c
* @brief This file provides code for the MSP Initialization * @brief This file provides code for the MSP Initialization
* and de-Initialization codes. * and de-Initialization codes.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2022 STMicroelectronics. * Copyright (c) 2022 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* USER CODE BEGIN TD */
/* USER CODE END TD */ /* USER CODE END TD */
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */ /* USER CODE BEGIN Define */
/* USER CODE END Define */ /* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */ /* USER CODE BEGIN Macro */
/* USER CODE END Macro */ /* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
/* USER CODE END PV */ /* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
/* External functions --------------------------------------------------------*/ /* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */ /* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */ /* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/** /**
* Initializes the Global MSP. * Initializes the Global MSP.
*/ */
void HAL_MspInit(void) void HAL_MspInit(void)
{ {
/* USER CODE BEGIN MspInit 0 */ /* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */ /* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/ /* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */ /* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */ /* USER CODE END MspInit 1 */
} }
/** /**
* @brief TIM_PWM MSP Initialization * @brief TIM_PWM MSP Initialization
* This function configures the hardware resources used in this example * This function configures the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer * @param htim_pwm: TIM_PWM handle pointer
* @retval None * @retval None
*/ */
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
{ {
if(htim_pwm->Instance==TIM2) if(htim_pwm->Instance==TIM2)
{ {
/* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE(); __HAL_RCC_TIM2_CLK_ENABLE();
/* USER CODE BEGIN TIM2_MspInit 1 */ /* USER CODE BEGIN TIM2_MspInit 1 */
/* USER CODE END TIM2_MspInit 1 */ /* USER CODE END TIM2_MspInit 1 */
} }
} }
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{ {
GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim->Instance==TIM2) if(htim->Instance==TIM2)
{ {
/* USER CODE BEGIN TIM2_MspPostInit 0 */ /* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */ /* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
/**TIM2 GPIO Configuration /**TIM2 GPIO Configuration
PA1 ------> TIM2_CH2 PA1 ------> TIM2_CH2
PA3 ------> TIM2_CH4 PA3 ------> TIM2_CH4
*/ */
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_3; GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN TIM2_MspPostInit 1 */ /* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */ /* USER CODE END TIM2_MspPostInit 1 */
} }
} }
/** /**
* @brief TIM_PWM MSP De-Initialization * @brief TIM_PWM MSP De-Initialization
* This function freeze the hardware resources used in this example * This function freeze the hardware resources used in this example
* @param htim_pwm: TIM_PWM handle pointer * @param htim_pwm: TIM_PWM handle pointer
* @retval None * @retval None
*/ */
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
{ {
if(htim_pwm->Instance==TIM2) if(htim_pwm->Instance==TIM2)
{ {
/* USER CODE BEGIN TIM2_MspDeInit 0 */ /* USER CODE BEGIN TIM2_MspDeInit 0 */
/* USER CODE END TIM2_MspDeInit 0 */ /* USER CODE END TIM2_MspDeInit 0 */
/* Peripheral clock disable */ /* Peripheral clock disable */
__HAL_RCC_TIM2_CLK_DISABLE(); __HAL_RCC_TIM2_CLK_DISABLE();
/* USER CODE BEGIN TIM2_MspDeInit 1 */ /* USER CODE BEGIN TIM2_MspDeInit 1 */
/* USER CODE END TIM2_MspDeInit 1 */ /* USER CODE END TIM2_MspDeInit 1 */
} }
} }
/** /**
* @brief UART MSP Initialization * @brief UART MSP Initialization
* This function configures the hardware resources used in this example * This function configures the hardware resources used in this example
* @param huart: UART handle pointer * @param huart: UART handle pointer
* @retval None * @retval None
*/ */
void HAL_UART_MspInit(UART_HandleTypeDef* huart) void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{ {
GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(huart->Instance==USART2) if(huart->Instance==USART2)
{ {
/* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */
/** Initializes the peripherals clock /** Initializes the peripherals clock
*/ */
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
} }
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE(); __HAL_RCC_USART2_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
/**USART2 GPIO Configuration /**USART2 GPIO Configuration
PA2 ------> USART2_TX PA2 ------> USART2_TX
PA15 (JTDI) ------> USART2_RX PA15 (JTDI) ------> USART2_RX
*/ */
GPIO_InitStruct.Pin = VCP_TX_Pin; GPIO_InitStruct.Pin = VCP_TX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF7_USART2; GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = VCP_RX_Pin; GPIO_InitStruct.Pin = VCP_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF3_USART2; GPIO_InitStruct.Alternate = GPIO_AF3_USART2;
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */
} }
} }
/** /**
* @brief UART MSP De-Initialization * @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example * This function freeze the hardware resources used in this example
* @param huart: UART handle pointer * @param huart: UART handle pointer
* @retval None * @retval None
*/ */
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{ {
if(huart->Instance==USART2) if(huart->Instance==USART2)
{ {
/* USER CODE BEGIN USART2_MspDeInit 0 */ /* USER CODE BEGIN USART2_MspDeInit 0 */
/* USER CODE END USART2_MspDeInit 0 */ /* USER CODE END USART2_MspDeInit 0 */
/* Peripheral clock disable */ /* Peripheral clock disable */
__HAL_RCC_USART2_CLK_DISABLE(); __HAL_RCC_USART2_CLK_DISABLE();
/**USART2 GPIO Configuration /**USART2 GPIO Configuration
PA2 ------> USART2_TX PA2 ------> USART2_TX
PA15 (JTDI) ------> USART2_RX PA15 (JTDI) ------> USART2_RX
*/ */
HAL_GPIO_DeInit(GPIOA, VCP_TX_Pin|VCP_RX_Pin); HAL_GPIO_DeInit(GPIOA, VCP_TX_Pin|VCP_RX_Pin);
/* USER CODE BEGIN USART2_MspDeInit 1 */ /* USER CODE BEGIN USART2_MspDeInit 1 */
/* USER CODE END USART2_MspDeInit 1 */ /* USER CODE END USART2_MspDeInit 1 */
} }
} }
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */

406
Core/Src/stm32l4xx_it.c
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@ -1,203 +1,203 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_it.c * @file stm32l4xx_it.c
* @brief Interrupt Service Routines. * @brief Interrupt Service Routines.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2022 STMicroelectronics. * Copyright (c) 2022 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
#include "stm32l4xx_it.h" #include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* USER CODE BEGIN TD */
/* USER CODE END TD */ /* USER CODE END TD */
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */ /* USER CODE BEGIN PD */
/* USER CODE END PD */ /* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */ /* USER CODE BEGIN PM */
/* USER CODE END PM */ /* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
/* USER CODE END PV */ /* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
/* External variables --------------------------------------------------------*/ /* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */ /* USER CODE BEGIN EV */
/* USER CODE END EV */ /* USER CODE END EV */
/******************************************************************************/ /******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */ /* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/ /******************************************************************************/
/** /**
* @brief This function handles Non maskable interrupt. * @brief This function handles Non maskable interrupt.
*/ */
void NMI_Handler(void) void NMI_Handler(void)
{ {
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1) while (1)
{ {
} }
/* USER CODE END NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */
} }
/** /**
* @brief This function handles Hard fault interrupt. * @brief This function handles Hard fault interrupt.
*/ */
void HardFault_Handler(void) void HardFault_Handler(void)
{ {
/* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */
while (1) while (1)
{ {
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */
} }
} }
/** /**
* @brief This function handles Memory management fault. * @brief This function handles Memory management fault.
*/ */
void MemManage_Handler(void) void MemManage_Handler(void)
{ {
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */
while (1) while (1)
{ {
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */ /* USER CODE END W1_MemoryManagement_IRQn 0 */
} }
} }
/** /**
* @brief This function handles Prefetch fault, memory access fault. * @brief This function handles Prefetch fault, memory access fault.
*/ */
void BusFault_Handler(void) void BusFault_Handler(void)
{ {
/* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */
while (1) while (1)
{ {
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ /* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */ /* USER CODE END W1_BusFault_IRQn 0 */
} }
} }
/** /**
* @brief This function handles Undefined instruction or illegal state. * @brief This function handles Undefined instruction or illegal state.
*/ */
void UsageFault_Handler(void) void UsageFault_Handler(void)
{ {
/* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */
while (1) while (1)
{ {
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */ /* USER CODE END W1_UsageFault_IRQn 0 */
} }
} }
/** /**
* @brief This function handles System service call via SWI instruction. * @brief This function handles System service call via SWI instruction.
*/ */
void SVC_Handler(void) void SVC_Handler(void)
{ {
/* USER CODE BEGIN SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */ /* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */
} }
/** /**
* @brief This function handles Debug monitor. * @brief This function handles Debug monitor.
*/ */
void DebugMon_Handler(void) void DebugMon_Handler(void)
{ {
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */
} }
/** /**
* @brief This function handles Pendable request for system service. * @brief This function handles Pendable request for system service.
*/ */
void PendSV_Handler(void) void PendSV_Handler(void)
{ {
/* USER CODE BEGIN PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */ /* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */
} }
/** /**
* @brief This function handles System tick timer. * @brief This function handles System tick timer.
*/ */
void SysTick_Handler(void) void SysTick_Handler(void)
{ {
/* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */
HAL_IncTick(); HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */
} }
/******************************************************************************/ /******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */ /* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */ /* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */ /* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */ /* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/ /******************************************************************************/
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */

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/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32l4xx.c * @file system_stm32l4xx.c
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
* *
* This file provides two functions and one global variable to be called from * This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): This function is called at startup just after reset and * - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file. * the "startup_stm32l4xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
* *
* After each device reset the MSI (4 MHz) is used as system clock source. * After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program. * configure the system clock before to branch to main program.
* *
* This file configures the system clock as follows: * This file configures the system clock as follows:
*============================================================================= *=============================================================================
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* System Clock source | MSI * System Clock source | MSI
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000 * SYSCLK(Hz) | 4000000
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000 * HCLK(Hz) | 4000000
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* AHB Prescaler | 1 * AHB Prescaler | 1
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB1 Prescaler | 1 * APB1 Prescaler | 1
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* APB2 Prescaler | 1 * APB2 Prescaler | 1
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_M | 1 * PLL_M | 1
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_N | 8 * PLL_N | 8
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_P | 7 * PLL_P | 7
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_Q | 2 * PLL_Q | 2
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLL_R | 2 * PLL_R | 2
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI1_P | NA * PLLSAI1_P | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI1_Q | NA * PLLSAI1_Q | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI1_R | NA * PLLSAI1_R | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI2_P | NA * PLLSAI2_P | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI2_Q | NA * PLLSAI2_Q | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* PLLSAI2_R | NA * PLLSAI2_R | NA
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled * Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock | * SDIO and RNG clock |
*----------------------------------------------------------------------------- *-----------------------------------------------------------------------------
*============================================================================= *=============================================================================
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32l4xx_system /** @addtogroup stm32l4xx_system
* @{ * @{
*/ */
/** @addtogroup STM32L4xx_System_Private_Includes /** @addtogroup STM32L4xx_System_Private_Includes
* @{ * @{
*/ */
#include "stm32l4xx.h" #include "stm32l4xx.h"
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_Defines /** @addtogroup STM32L4xx_System_Private_Defines
* @{ * @{
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (MSI_VALUE) #if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */ #endif /* MSI_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/* Note: Following vector table addresses must be defined in line with linker /* Note: Following vector table addresses must be defined in line with linker
configuration. */ configuration. */
/*!< Uncomment the following line if you need to relocate the vector table /*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */ remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */ /* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table /*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM) #if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#else #else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */ #endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/ /******************************************************************************/
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_Macros /** @addtogroup STM32L4xx_System_Private_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_Variables /** @addtogroup STM32L4xx_System_Private_Variables
* @{ * @{
*/ */
/* The SystemCoreClock variable is updated in three ways: /* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 4000000U; uint32_t SystemCoreClock = 4000000U;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Private_Functions /** @addtogroup STM32L4xx_System_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief Setup the microcontroller system. * @brief Setup the microcontroller system.
* @retval None * @retval None
*/ */
void SystemInit(void) void SystemInit(void)
{ {
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
/* Configure the Vector Table location -------------------------------------*/ /* Configure the Vector Table location -------------------------------------*/
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
#endif #endif
/* FPU settings ------------------------------------------------------------*/ /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif #endif
} }
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
* *
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations * 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations * 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real * 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may * frequency of the crystal used. Otherwise, this function may
* have wrong result. * have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* *
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr; uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
/* Get MSI Range frequency--------------------------------------------------*/ /* Get MSI Range frequency--------------------------------------------------*/
if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U) if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
{ /* MSISRANGE from RCC_CSR applies */ { /* MSISRANGE from RCC_CSR applies */
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
} }
else else
{ /* MSIRANGE from RCC_CR applies */ { /* MSIRANGE from RCC_CR applies */
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
} }
/*MSI frequency range in HZ*/ /*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange]; msirange = MSIRangeTable[msirange];
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS) switch (RCC->CFGR & RCC_CFGR_SWS)
{ {
case 0x00: /* MSI used as system clock source */ case 0x00: /* MSI used as system clock source */
SystemCoreClock = msirange; SystemCoreClock = msirange;
break; break;
case 0x04: /* HSI used as system clock source */ case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x08: /* HSE used as system clock source */ case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x0C: /* PLL used as system clock source */ case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR SYSCLK = PLL_VCO / PLLR
*/ */
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
switch (pllsource) switch (pllsource)
{ {
case 0x02: /* HSI used as PLL clock source */ case 0x02: /* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm); pllvco = (HSI_VALUE / pllm);
break; break;
case 0x03: /* HSE used as PLL clock source */ case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm); pllvco = (HSE_VALUE / pllm);
break; break;
default: /* MSI used as PLL clock source */ default: /* MSI used as PLL clock source */
pllvco = (msirange / pllm); pllvco = (msirange / pllm);
break; break;
} }
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
SystemCoreClock = pllvco/pllr; SystemCoreClock = pllvco/pllr;
break; break;
default: default:
SystemCoreClock = msirange; SystemCoreClock = msirange;
break; break;
} }
/* Compute HCLK clock frequency --------------------------------------------*/ /* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */ /* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */ /* HCLK clock frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx.h * @file stm32l4xx.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32L4xx device used in the target application * - The STM32L4xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e. * - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32l4xx /** @addtogroup stm32l4xx
* @{ * @{
*/ */
#ifndef __STM32L4xx_H #ifndef __STM32L4xx_H
#define __STM32L4xx_H #define __STM32L4xx_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/** /**
* @brief STM32 Family * @brief STM32 Family
*/ */
#if !defined (STM32L4) #if !defined (STM32L4)
#define STM32L4 #define STM32L4
#endif /* STM32L4 */ #endif /* STM32L4 */
/* Uncomment the line below according to the target STM32L4 device used in your /* Uncomment the line below according to the target STM32L4 device used in your
application application
*/ */
#if !defined (STM32L412xx) && !defined (STM32L422xx) && \ #if !defined (STM32L412xx) && !defined (STM32L422xx) && \
!defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \
!defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \
!defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \
!defined (STM32L496xx) && !defined (STM32L4A6xx) && \ !defined (STM32L496xx) && !defined (STM32L4A6xx) && \
!defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \ !defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \
!defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)
/* #define STM32L412xx */ /*!< STM32L412xx Devices */ /* #define STM32L412xx */ /*!< STM32L412xx Devices */
/* #define STM32L422xx */ /*!< STM32L422xx Devices */ /* #define STM32L422xx */ /*!< STM32L422xx Devices */
/* #define STM32L431xx */ /*!< STM32L431xx Devices */ /* #define STM32L431xx */ /*!< STM32L431xx Devices */
/* #define STM32L432xx */ /*!< STM32L432xx Devices */ /* #define STM32L432xx */ /*!< STM32L432xx Devices */
/* #define STM32L433xx */ /*!< STM32L433xx Devices */ /* #define STM32L433xx */ /*!< STM32L433xx Devices */
/* #define STM32L442xx */ /*!< STM32L442xx Devices */ /* #define STM32L442xx */ /*!< STM32L442xx Devices */
/* #define STM32L443xx */ /*!< STM32L443xx Devices */ /* #define STM32L443xx */ /*!< STM32L443xx Devices */
/* #define STM32L451xx */ /*!< STM32L451xx Devices */ /* #define STM32L451xx */ /*!< STM32L451xx Devices */
/* #define STM32L452xx */ /*!< STM32L452xx Devices */ /* #define STM32L452xx */ /*!< STM32L452xx Devices */
/* #define STM32L462xx */ /*!< STM32L462xx Devices */ /* #define STM32L462xx */ /*!< STM32L462xx Devices */
/* #define STM32L471xx */ /*!< STM32L471xx Devices */ /* #define STM32L471xx */ /*!< STM32L471xx Devices */
/* #define STM32L475xx */ /*!< STM32L475xx Devices */ /* #define STM32L475xx */ /*!< STM32L475xx Devices */
/* #define STM32L476xx */ /*!< STM32L476xx Devices */ /* #define STM32L476xx */ /*!< STM32L476xx Devices */
/* #define STM32L485xx */ /*!< STM32L485xx Devices */ /* #define STM32L485xx */ /*!< STM32L485xx Devices */
/* #define STM32L486xx */ /*!< STM32L486xx Devices */ /* #define STM32L486xx */ /*!< STM32L486xx Devices */
/* #define STM32L496xx */ /*!< STM32L496xx Devices */ /* #define STM32L496xx */ /*!< STM32L496xx Devices */
/* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */
/* #define STM32L4P5xx */ /*!< STM32L4Q5xx Devices */ /* #define STM32L4P5xx */ /*!< STM32L4Q5xx Devices */
/* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */
/* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */
/* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */
/* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */
/* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */
/* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
*/ */
#if !defined (USE_HAL_DRIVER) #if !defined (USE_HAL_DRIVER)
/** /**
* @brief Comment the line below if you will not use the peripherals drivers. * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
/*#define USE_HAL_DRIVER */ /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number * @brief CMSIS Device version number
*/ */
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ #define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L4_CMSIS_VERSION_RC)) |(__STM32L4_CMSIS_VERSION_RC))
/** /**
* @} * @}
*/ */
/** @addtogroup Device_Included /** @addtogroup Device_Included
* @{ * @{
*/ */
#if defined(STM32L412xx) #if defined(STM32L412xx)
#include "stm32l412xx.h" #include "stm32l412xx.h"
#elif defined(STM32L422xx) #elif defined(STM32L422xx)
#include "stm32l422xx.h" #include "stm32l422xx.h"
#elif defined(STM32L431xx) #elif defined(STM32L431xx)
#include "stm32l431xx.h" #include "stm32l431xx.h"
#elif defined(STM32L432xx) #elif defined(STM32L432xx)
#include "stm32l432xx.h" #include "stm32l432xx.h"
#elif defined(STM32L433xx) #elif defined(STM32L433xx)
#include "stm32l433xx.h" #include "stm32l433xx.h"
#elif defined(STM32L442xx) #elif defined(STM32L442xx)
#include "stm32l442xx.h" #include "stm32l442xx.h"
#elif defined(STM32L443xx) #elif defined(STM32L443xx)
#include "stm32l443xx.h" #include "stm32l443xx.h"
#elif defined(STM32L451xx) #elif defined(STM32L451xx)
#include "stm32l451xx.h" #include "stm32l451xx.h"
#elif defined(STM32L452xx) #elif defined(STM32L452xx)
#include "stm32l452xx.h" #include "stm32l452xx.h"
#elif defined(STM32L462xx) #elif defined(STM32L462xx)
#include "stm32l462xx.h" #include "stm32l462xx.h"
#elif defined(STM32L471xx) #elif defined(STM32L471xx)
#include "stm32l471xx.h" #include "stm32l471xx.h"
#elif defined(STM32L475xx) #elif defined(STM32L475xx)
#include "stm32l475xx.h" #include "stm32l475xx.h"
#elif defined(STM32L476xx) #elif defined(STM32L476xx)
#include "stm32l476xx.h" #include "stm32l476xx.h"
#elif defined(STM32L485xx) #elif defined(STM32L485xx)
#include "stm32l485xx.h" #include "stm32l485xx.h"
#elif defined(STM32L486xx) #elif defined(STM32L486xx)
#include "stm32l486xx.h" #include "stm32l486xx.h"
#elif defined(STM32L496xx) #elif defined(STM32L496xx)
#include "stm32l496xx.h" #include "stm32l496xx.h"
#elif defined(STM32L4A6xx) #elif defined(STM32L4A6xx)
#include "stm32l4a6xx.h" #include "stm32l4a6xx.h"
#elif defined(STM32L4P5xx) #elif defined(STM32L4P5xx)
#include "stm32l4p5xx.h" #include "stm32l4p5xx.h"
#elif defined(STM32L4Q5xx) #elif defined(STM32L4Q5xx)
#include "stm32l4q5xx.h" #include "stm32l4q5xx.h"
#elif defined(STM32L4R5xx) #elif defined(STM32L4R5xx)
#include "stm32l4r5xx.h" #include "stm32l4r5xx.h"
#elif defined(STM32L4R7xx) #elif defined(STM32L4R7xx)
#include "stm32l4r7xx.h" #include "stm32l4r7xx.h"
#elif defined(STM32L4R9xx) #elif defined(STM32L4R9xx)
#include "stm32l4r9xx.h" #include "stm32l4r9xx.h"
#elif defined(STM32L4S5xx) #elif defined(STM32L4S5xx)
#include "stm32l4s5xx.h" #include "stm32l4s5xx.h"
#elif defined(STM32L4S7xx) #elif defined(STM32L4S7xx)
#include "stm32l4s7xx.h" #include "stm32l4s7xx.h"
#elif defined(STM32L4S9xx) #elif defined(STM32L4S9xx)
#include "stm32l4s9xx.h" #include "stm32l4s9xx.h"
#else #else
#error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum
{ {
RESET = 0, RESET = 0,
SET = !RESET SET = !RESET
} FlagStatus, ITStatus; } FlagStatus, ITStatus;
typedef enum typedef enum
{ {
DISABLE = 0, DISABLE = 0,
ENABLE = !DISABLE ENABLE = !DISABLE
} FunctionalState; } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum
{ {
SUCCESS = 0, SUCCESS = 0,
ERROR = !SUCCESS ERROR = !SUCCESS
} ErrorStatus; } ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0)) #define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG)) #define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of CMSIS compiler intrinsics for register exclusive access */ /* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */ /* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \ #define ATOMIC_SET_BIT(REG, BIT) \
do { \ do { \
uint32_t val; \ uint32_t val; \
do { \ do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0) } while(0)
/* Atomic 32-bit register access macro to clear one or several bits */ /* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \ #define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \ do { \
uint32_t val; \ uint32_t val; \
do { \ do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0) } while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */ /* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \ do { \
uint32_t val; \ uint32_t val; \
do { \ do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0) } while(0)
/* Atomic 16-bit register access macro to set one or several bits */ /* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \ #define ATOMIC_SETH_BIT(REG, BIT) \
do { \ do { \
uint16_t val; \ uint16_t val; \
do { \ do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0) } while(0)
/* Atomic 16-bit register access macro to clear one or several bits */ /* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \ #define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \ do { \
uint16_t val; \ uint16_t val; \
do { \ do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0) } while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */ /* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \ do { \
uint16_t val; \ uint16_t val; \
do { \ do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0) } while(0)
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER) #if defined (USE_HAL_DRIVER)
#include "stm32l4xx_hal.h" #include "stm32l4xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32L4xx_H */ #endif /* __STM32L4xx_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */

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Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h
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/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32l4xx.h * @file system_stm32l4xx.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32l4xx_system /** @addtogroup stm32l4xx_system
* @{ * @{
*/ */
/** /**
* @brief Define to prevent recursive inclusion * @brief Define to prevent recursive inclusion
*/ */
#ifndef __SYSTEM_STM32L4XX_H #ifndef __SYSTEM_STM32L4XX_H
#define __SYSTEM_STM32L4XX_H #define __SYSTEM_STM32L4XX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** @addtogroup STM32L4xx_System_Includes /** @addtogroup STM32L4xx_System_Includes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Exported_Variables /** @addtogroup STM32L4xx_System_Exported_Variables
* @{ * @{
*/ */
/* The SystemCoreClock variable is updated in three ways: /* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq() 2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Exported_Constants /** @addtogroup STM32L4xx_System_Exported_Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Exported_Macros /** @addtogroup STM32L4xx_System_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32L4xx_System_Exported_Functions /** @addtogroup STM32L4xx_System_Exported_Functions
* @{ * @{
*/ */
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /*__SYSTEM_STM32L4XX_H */ #endif /*__SYSTEM_STM32L4XX_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */

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Drivers/CMSIS/Device/ST/STM32L4xx/LICENSE.txt
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This software component is provided to you as part of a software package and This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms, software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply. the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at: You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0 https://opensource.org/licenses/Apache-2.0

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Drivers/CMSIS/Include/cmsis_compiler.h
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/**************************************************************************//** /**************************************************************************//**
* @file cmsis_compiler.h * @file cmsis_compiler.h
* @brief CMSIS compiler generic header file * @brief CMSIS compiler generic header file
* @version V5.1.0 * @version V5.1.0
* @date 09. October 2018 * @date 09. October 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#ifndef __CMSIS_COMPILER_H #ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H
#include <stdint.h> #include <stdint.h>
/* /*
* Arm Compiler 4/5 * Arm Compiler 4/5
*/ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/* /*
* Arm Compiler 6.6 LTM (armclang) * Arm Compiler 6.6 LTM (armclang)
*/ */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h" #include "cmsis_armclang_ltm.h"
/* /*
* Arm Compiler above 6.10.1 (armclang) * Arm Compiler above 6.10.1 (armclang)
*/ */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h" #include "cmsis_armclang.h"
/* /*
* GNU Compiler * GNU Compiler
*/ */
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/* /*
* IAR Compiler * IAR Compiler
*/ */
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h> #include <cmsis_iccarm.h>
/* /*
* TI Arm Compiler * TI Arm Compiler
*/ */
#elif defined ( __TI_ARM__ ) #elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __attribute__((packed)) #define __PACKED __attribute__((packed))
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed)) #define __PACKED_STRUCT struct __attribute__((packed))
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed)) #define __PACKED_UNION union __attribute__((packed))
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x))) #define __ALIGNED(x) __attribute__((aligned(x)))
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#define __RESTRICT __restrict #define __RESTRICT __restrict
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
/* /*
* TASKING Compiler * TASKING Compiler
*/ */
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __packed__ #define __PACKED __packed__
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__ #define __PACKED_STRUCT struct __packed__
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__ #define __PACKED_UNION union __packed__
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; }; struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __align(x) #define __ALIGNED(x) __align(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
/* /*
* COSMIC Compiler * COSMIC Compiler
*/ */
#elif defined ( __CSMC__ ) #elif defined ( __CSMC__ )
#include <cmsis_csm.h> #include <cmsis_csm.h>
#ifndef __ASM #ifndef __ASM
#define __ASM _asm #define __ASM _asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here // NO RETURN is automatically detected hence no warning here
#define __NO_RETURN #define __NO_RETURN
#endif #endif
#ifndef __USED #ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored. #warning No compiler specific solution for __USED. __USED is ignored.
#define __USED #define __USED
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __weak #define __WEAK __weak
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED @packed #define __PACKED @packed
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct #define __PACKED_STRUCT @packed struct
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION @packed union #define __PACKED_UNION @packed union
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; }; @packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x) #define __ALIGNED(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
#ifndef __COMPILER_BARRIER #ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0 #define __COMPILER_BARRIER() (void)0
#endif #endif
#else #else
#error Unknown compiler. #error Unknown compiler.
#endif #endif
#endif /* __CMSIS_COMPILER_H */ #endif /* __CMSIS_COMPILER_H */

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Drivers/CMSIS/Include/cmsis_version.h
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/**************************************************************************//** /**************************************************************************//**
* @file cmsis_version.h * @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions * @brief CMSIS Core(M) Version definitions
* @version V5.0.3 * @version V5.0.3
* @date 24. June 2019 * @date 24. June 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved. * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CMSIS_VERSION_H #ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H #define __CMSIS_VERSION_H
/* CMSIS Version definitions */ /* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif #endif

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Drivers/CMSIS/Include/mpu_armv7.h
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/****************************************************************************** /******************************************************************************
* @file mpu_armv7.h * @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU * @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.0 * @version V5.1.0
* @date 08. March 2019 * @date 08. March 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved. * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV7_H #ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value /** MPU Region Base Address Register Value
* *
* \param Region The region to be configured, number 0 to 15. * \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region. * \param BaseAddress The base address for the region.
*/ */
#define ARM_MPU_RBAR(Region, BaseAddress) \ #define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk)) (MPU_RBAR_VALID_Msk))
/** /**
* MPU Memory Access Attributes * MPU Memory Access Attributes
* *
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/ */
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk)))) (((MPU_RASR_ENABLE_Msk))))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/** /**
* MPU Memory Access Attribute for strongly ordered memory. * MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b * - TEX: 000b
* - Shareable * - Shareable
* - Non-cacheable * - Non-cacheable
* - Non-bufferable * - Non-bufferable
*/ */
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/** /**
* MPU Memory Access Attribute for device memory. * MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable) * - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Non-cacheable * - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable) * - Bufferable (if shareable) or non-bufferable (if non-shareable)
* *
* \param IsShareable Configures the device memory as shareable or non-shareable. * \param IsShareable Configures the device memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/** /**
* MPU Memory Access Attribute for normal memory. * MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules) * - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules)
* *
* \param OuterCp Configures the outer cache policy. * \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy. * \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable. * \param IsShareable Configures the memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/** /**
* MPU Memory Access Attribute non-cacheable policy. * MPU Memory Access Attribute non-cacheable policy.
*/ */
#define ARM_MPU_CACHEP_NOCACHE 0U #define ARM_MPU_CACHEP_NOCACHE 0U
/** /**
* MPU Memory Access Attribute write-back, write and read allocate policy. * MPU Memory Access Attribute write-back, write and read allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_WRA 1U #define ARM_MPU_CACHEP_WB_WRA 1U
/** /**
* MPU Memory Access Attribute write-through, no write allocate policy. * MPU Memory Access Attribute write-through, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WT_NWA 2U #define ARM_MPU_CACHEP_WT_NWA 2U
/** /**
* MPU Memory Access Attribute write-back, no write allocate policy. * MPU Memory Access Attribute write-back, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_NWA 3U #define ARM_MPU_CACHEP_WB_NWA 3U
/** /**
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{ {
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
__DSB(); __DSB();
__ISB(); __ISB();
} }
/** Disable the MPU. /** Disable the MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable(void) __STATIC_INLINE void ARM_MPU_Disable(void)
{ {
__DMB(); __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
/** Clear and disable the given MPU region. /** Clear and disable the given MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RASR = 0U; MPU->RASR = 0U;
} }
/** Configure an MPU region. /** Configure an MPU region.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{ {
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Configure the given MPU region. /** Configure the given MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Memcopy with strictly ordered memory access, e.g. for register targets. /** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to. * \param dst Destination data is copied to.
* \param src Source data is copied from. * \param src Source data is copied from.
* \param len Amount of data words to be copied. * \param len Amount of data words to be copied.
*/ */
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
} }
/** Load the given number of MPU regions from a table. /** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) { while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES; table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES;
} }
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
} }
#endif #endif

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Drivers/CMSIS/Include/mpu_armv8.h
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@ -1,346 +1,346 @@
/****************************************************************************** /******************************************************************************
* @file mpu_armv8.h * @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.0 * @version V5.1.0
* @date 08. March 2019 * @date 08. March 2019
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2019 Arm Limited. All rights reserved. * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV8_H #ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */ /** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U ) #define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */ /** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner) /** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data. * \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy. * \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/ */
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U) #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U) #define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute /** \brief Memory Attribute
* \param O Outer memory attributes * \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/ */
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */ /** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U) #define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */ /** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U) #define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */ /** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U) #define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions /** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory. * \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/ */
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value /** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region. * \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region. * \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/ */
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \ ((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value /** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region. * \param IDX The attribute index to be associated with this memory region.
*/ */
#define ARM_MPU_RLAR(LIMIT, IDX) \ #define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk)) (MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos) #if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value /** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region. * \param IDX The attribute index to be associated with this memory region.
*/ */
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk)) (MPU_RLAR_EN_Msk))
#endif #endif
/** /**
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{ {
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
__DSB(); __DSB();
__ISB(); __ISB();
} }
/** Disable the MPU. /** Disable the MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable(void) __STATIC_INLINE void ARM_MPU_Disable(void)
{ {
__DMB(); __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Enable the Non-secure MPU. /** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{ {
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
__DSB(); __DSB();
__ISB(); __ISB();
} }
/** Disable the Non-secure MPU. /** Disable the Non-secure MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable_NS(void) __STATIC_INLINE void ARM_MPU_Disable_NS(void)
{ {
__DMB(); __DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
#endif #endif
/** Set the memory attribute encoding to the given MPU. /** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured. * \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{ {
const uint8_t reg = idx / 4U; const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U); const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos; const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index return; // invalid index
} }
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
} }
/** Set the memory attribute encoding. /** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{ {
ARM_MPU_SetMemAttrEx(MPU, idx, attr); ARM_MPU_SetMemAttrEx(MPU, idx, attr);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU. /** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{ {
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
} }
#endif #endif
/** Clear and disable the given MPU region of the given MPU. /** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used. * \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{ {
mpu->RNR = rnr; mpu->RNR = rnr;
mpu->RLAR = 0U; mpu->RLAR = 0U;
} }
/** Clear and disable the given MPU region. /** Clear and disable the given MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{ {
ARM_MPU_ClrRegionEx(MPU, rnr); ARM_MPU_ClrRegionEx(MPU, rnr);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region. /** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{ {
ARM_MPU_ClrRegionEx(MPU_NS, rnr); ARM_MPU_ClrRegionEx(MPU_NS, rnr);
} }
#endif #endif
/** Configure the given MPU region of the given MPU. /** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used. * \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
mpu->RNR = rnr; mpu->RNR = rnr;
mpu->RBAR = rbar; mpu->RBAR = rbar;
mpu->RLAR = rlar; mpu->RLAR = rlar;
} }
/** Configure the given MPU region. /** Configure the given MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Configure the given Non-secure MPU region. /** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
} }
#endif #endif
/** Memcopy with strictly ordered memory access, e.g. for register targets. /** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to. * \param dst Destination data is copied to.
* \param src Source data is copied from. * \param src Source data is copied from.
* \param len Amount of data words to be copied. * \param len Amount of data words to be copied.
*/ */
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
} }
/** Load the given number of MPU regions from a table to the given MPU. /** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used. * \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) { if (cnt == 1U) {
mpu->RNR = rnr; mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else { } else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase; mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset; uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c; table += c;
cnt -= c; cnt -= c;
rnrOffset = 0U; rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES; rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase; mpu->RNR = rnrBase;
} }
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
} }
} }
/** Load the given number of MPU regions from a table. /** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
ARM_MPU_LoadEx(MPU, rnr, table, cnt); ARM_MPU_LoadEx(MPU, rnr, table, cnt);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU. /** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
} }
#endif #endif
#endif #endif

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/****************************************************************************** /******************************************************************************
* @file tz_context.h * @file tz_context.h
* @brief Context Management for Armv8-M TrustZone * @brief Context Management for Armv8-M TrustZone
* @version V1.0.1 * @version V1.0.1
* @date 10. January 2018 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef TZ_CONTEXT_H #ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H #define TZ_CONTEXT_H
#include <stdint.h> #include <stdint.h>
#ifndef TZ_MODULEID_T #ifndef TZ_MODULEID_T
#define TZ_MODULEID_T #define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process. /// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t; typedef uint32_t TZ_ModuleId_t;
#endif #endif
/// \details TZ Memory ID identifies an allocated memory slot. /// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t; typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system /// Initialize secure context memory system
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void); uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone /// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode /// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier /// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error /// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch) /// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch) /// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H #endif // TZ_CONTEXT_H

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Apache License Apache License
Version 2.0, January 2004 Version 2.0, January 2004
http://www.apache.org/licenses/ http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions. 1. Definitions.
"License" shall mean the terms and conditions for use, reproduction, "License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document. and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by "Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License. the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all "Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition, control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the "control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the otherwise, or (ii) ownership of fifty percent (50%) or more of the
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/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_cortex.h * @file stm32l4xx_hal_cortex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of CORTEX HAL module. * @brief Header file of CORTEX HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file in * This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component. * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_CORTEX_H #ifndef STM32L4xx_HAL_CORTEX_H
#define STM32L4xx_HAL_CORTEX_H #define STM32L4xx_HAL_CORTEX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup CORTEX CORTEX /** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver * @brief CORTEX HAL module driver
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types /** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{ * @{
*/ */
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure * @brief MPU Region initialization structure
* @{ * @{
*/ */
typedef struct typedef struct
{ {
uint8_t Enable; /*!< Specifies the status of the region. uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect. uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect. uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level. uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type. uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status. uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef; }MPU_Region_InitTypeDef;
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{ * @{
*/ */
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{ * @{
*/ */
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
4 bits for subpriority */ 4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
3 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
2 bits for subpriority */ 2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
1 bit for subpriority */ 1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
0 bit for subpriority */ 0 bit for subpriority */
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{ * @{
*/ */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/** /**
* @} * @}
*/ */
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{ * @{
*/ */
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{ * @{
*/ */
#define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00) #define MPU_REGION_DISABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{ * @{
*/ */
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{ * @{
*/ */
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{ * @{
*/ */
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{ * @{
*/ */
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{ * @{
*/ */
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL4 ((uint8_t)0x04) #define MPU_TEX_LEVEL4 ((uint8_t)0x04)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{ * @{
*/ */
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{ * @{
*/ */
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{ * @{
*/ */
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{ * @{
*/ */
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions * @brief Initialization and Configuration functions
* @{ * @{
*/ */
/* Initialization and Configuration functions *****************************/ /* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void); void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions * @brief Cortex control functions
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void); uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void); void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void); void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{ * @{
*/ */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4)) ((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE)) ((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2) || \ ((TYPE) == MPU_TEX_LEVEL2) || \
((TYPE) == MPU_TEX_LEVEL4)) ((TYPE) == MPU_TEX_LEVEL4))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO)) ((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7)) ((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB)) ((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32L4xx_HAL_CORTEX_H */ #endif /* STM32L4xx_HAL_CORTEX_H */

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Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
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@ -1,209 +1,209 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_def.h * @file stm32l4xx_hal_def.h
* @author MCD Application Team * @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and * @brief This file contains HAL common defines, enumeration, macros and
* structures definitions. * structures definitions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DEF_H #ifndef STM32L4xx_HAL_DEF_H
#define STM32L4xx_HAL_DEF_H #define STM32L4xx_HAL_DEF_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx.h" #include "stm32l4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h> #include <stddef.h>
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** /**
* @brief HAL Status structures definition * @brief HAL Status structures definition
*/ */
typedef enum typedef enum
{ {
HAL_OK = 0x00, HAL_OK = 0x00,
HAL_ERROR = 0x01, HAL_ERROR = 0x01,
HAL_BUSY = 0x02, HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03 HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef; } HAL_StatusTypeDef;
/** /**
* @brief HAL Lock structures definition * @brief HAL Lock structures definition
*/ */
typedef enum typedef enum
{ {
HAL_UNLOCKED = 0x00, HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01 HAL_LOCKED = 0x01
} HAL_LockTypeDef; } HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \ do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0) } while(0)
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle. * @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter * - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field. * to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function * Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed * HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed). * (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling * - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function * In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware. * HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None * @retval None
*/ */
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1) #if (USE_RTOS == 1)
/* Reserved for future use */ /* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release " #error " USE_RTOS should be 0 in the current HAL release "
#else #else
#define __HAL_LOCK(__HANDLE__) \ #define __HAL_LOCK(__HANDLE__) \
do{ \ do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \ if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \ { \
return HAL_BUSY; \ return HAL_BUSY; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Lock = HAL_LOCKED; \ (__HANDLE__)->Lock = HAL_LOCKED; \
} \ } \
}while (0) }while (0)
#define __HAL_UNLOCK(__HANDLE__) \ #define __HAL_UNLOCK(__HANDLE__) \
do{ \ do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \ (__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0) }while (0)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif #endif
#ifndef __packed #ifndef __packed
#define __packed __attribute__((packed)) #define __packed __attribute__((packed))
#endif #endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
#ifndef __packed #ifndef __packed
#define __packed __attribute__((__packed__)) #define __packed __attribute__((__packed__))
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif #endif
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif #endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#else #else
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END #define __ALIGN_END
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5 */ #if defined (__CC_ARM) /* ARM Compiler V5 */
#define __ALIGN_BEGIN __align(4) #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */ #elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __CC_ARM */ #endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6 /* ARM Compiler V4/V5 and V6
-------------------------- --------------------------
RAM functions are defined using the toolchain options. RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module. Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const' Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target' Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog. dialog.
*/ */
#define __RAM_FUNC #define __RAM_FUNC
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc". RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/ */
#define __RAM_FUNC __ramfunc #define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
/* GNU Compiler /* GNU Compiler
------------ ------------
RAM functions are defined using a specific toolchain attribute RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))". "__attribute__((section(".RamFunc")))".
*/ */
#define __RAM_FUNC __attribute__((section(".RamFunc"))) #define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif #endif
/** /**
* @brief __NOINLINE definition * @brief __NOINLINE definition
*/ */
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler /* ARM V4/V5 and V6 & GNU Compiler
------------------------------- -------------------------------
*/ */
#define __NOINLINE __attribute__ ( (noinline) ) #define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
*/ */
#define __NOINLINE _Pragma("optimize = no_inline") #define __NOINLINE _Pragma("optimize = no_inline")
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32L4xx_HAL_DEF_H */ #endif /* STM32L4xx_HAL_DEF_H */

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/** /**
****************************************************************************** ******************************************************************************
* @file stm32l4xx_hal_dma_ex.h * @file stm32l4xx_hal_dma_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of DMA HAL extension module. * @brief Header file of DMA HAL extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* Copyright (c) 2017 STMicroelectronics. * Copyright (c) 2017 STMicroelectronics.
* All rights reserved. * All rights reserved.
* *
* This software is licensed under terms that can be found in the LICENSE file * This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component. * in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS. * If no LICENSE file comes with this software, it is provided AS-IS.
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L4xx_HAL_DMA_EX_H #ifndef STM32L4xx_HAL_DMA_EX_H
#define STM32L4xx_HAL_DMA_EX_H #define STM32L4xx_HAL_DMA_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#if defined(DMAMUX1) #if defined(DMAMUX1)
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_def.h" #include "stm32l4xx_hal_def.h"
/** @addtogroup STM32L4xx_HAL_Driver /** @addtogroup STM32L4xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup DMAEx /** @addtogroup DMAEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @{ * @{
*/ */
/** /**
* @brief HAL DMA Synchro definition * @brief HAL DMA Synchro definition
*/ */
/** /**
* @brief HAL DMAMUX Synchronization configuration structure definition * @brief HAL DMAMUX Synchronization configuration structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/ This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */ This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxSyncConfigTypeDef; }HAL_DMA_MuxSyncConfigTypeDef;
/** /**
* @brief HAL DMAMUX request generator parameters structure definition * @brief HAL DMAMUX request generator parameters structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}HAL_DMA_MuxRequestGeneratorConfigTypeDef; }HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{ * @{
*/ */
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
* @{ * @{
*/ */
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ #define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ #define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ #define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ #define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ #define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ #define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ #define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ #define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ #define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ #define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ #define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ #define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ #define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ #define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ #define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ #define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ #define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ #define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ #define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ #define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ #define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ #define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */
/** /**
* @} * @}
*/ */
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
* @{ * @{
*/ */
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ #define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ #define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ #define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ #define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
/** /**
* @} * @}
*/ */
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
* @{ * @{
*/ */
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ #define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */
#if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
#define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ #define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */
#define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ #define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */
#endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
#define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ #define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */
#define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ #define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */
/** /**
* @} * @}
*/ */
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{ * @{
*/ */
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */ #define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ #define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ #define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ #define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions /** @addtogroup DMAEx_Exported_Functions
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
/** @addtogroup DMAEx_Exported_Functions_Group1 /** @addtogroup DMAEx_Exported_Functions_Group1
* @{ * @{
*/ */
/* ------------------------- REQUEST -----------------------------------------*/ /* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/ /* ------------------------- SYNCHRO -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private defines -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros /** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx private macros * @brief DMAEx private macros
* @{ * @{
*/ */
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE)) ((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT) #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* DMAMUX1 */ #endif /* DMAMUX1 */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32L4xx_HAL_DMA_H */ #endif /* STM32L4xx_HAL_DMA_H */

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