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penguin 4 years ago
parent 56dc781395
commit 32114c85ab
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46
test/same54p20a_test/cfg/conf_core.h
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@ -11,6 +11,11 @@
#define _CONF_CLOCKS_H_ #define _CONF_CLOCKS_H_
#include "clocks.h" #include "clocks.h"
/** @name Core-Master-Clock-Configuration
* Configuration options for the master clock.
* @{
*/
/** /**
* Define the number of wait states for the master clock. * Define the number of wait states for the master clock.
* Can be [0-15]. * Can be [0-15].
@ -35,6 +40,8 @@
* - 0 => Disabled * - 0 => Disabled
* - 1 => Enabled * - 1 => Enabled
*/ */
/** @} */
#define CONF_CORE_DMA_ENABLE (0) #define CONF_CORE_DMA_ENABLE (0)
/** /**
@ -47,7 +54,11 @@
#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0) #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0) #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0) #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
// XOSC0 Config /** @name Core-XOSC0-Configuration
* Configuration options for XOSC0.
* @{
*/
#define CONF_CORE_CLK_XOSC0_ENABLE (1) #define CONF_CORE_CLK_XOSC0_ENABLE (1)
#define CONF_CORE_CLK_XOSC0_XTALEN (1) #define CONF_CORE_CLK_XOSC0_XTALEN (1)
#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0) #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
@ -59,7 +70,13 @@
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
// XOSC1 Config /** @} */
/** @name Core-XOSC1-Configuration
* Configuration options for XOSC1.
* @{
*/
#define CONF_CORE_CLK_XOSC1_ENABLE (0) #define CONF_CORE_CLK_XOSC1_ENABLE (0)
#define CONF_CORE_CLK_XOSC1_XTALEN (0) #define CONF_CORE_CLK_XOSC1_XTALEN (0)
#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0) #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
@ -71,7 +88,13 @@
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
// XOSC32K Config /** @} */
/** @name Core-XOSC32K-Configuration
* Configuration options for the external 32khz oscillator.
* @{
*/
#define CONF_CORE_CLK_XOSC32K_ENABLE (1) #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
@ -85,6 +108,8 @@
#define CONF_CORE_CLK_XOSC32K_SWBACK (0) #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0) #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
/** @} */
/** @name Core-DFLL48M-Configuration /** @name Core-DFLL48M-Configuration
* Configuration options for DFLL48M * Configuration options for DFLL48M
*/ */
@ -154,7 +179,11 @@
#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
/** @} */ /** @} */
// DPLL0 Config /** @name Core-DPLL0-Configuration
* Configuration Options for DPLL0.
* @{
*/
#define CONF_CORE_CLK_DPLL0_ENABLE (1) #define CONF_CORE_CLK_DPLL0_ENABLE (1)
#define CONF_CORE_CLK_DPLL0_ONDEMAND (0) #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0) #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
@ -192,7 +221,12 @@
*/ */
#define CONF_CORE_CLK_DPLL0_FILTER 0x0 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
// DPLL1 Config /** @} */
/** @name Core-DPLL1-Configuration
* Configuration Options for DPLL1.
* @{
*/
#define CONF_CORE_CLK_DPLL1_ENABLE (0) #define CONF_CORE_CLK_DPLL1_ENABLE (0)
#define CONF_CORE_CLK_DPLL1_ONDEMAND (0) #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0) #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
@ -232,6 +266,8 @@
*/ */
#define CONF_CORE_CLK_DPLL1_FILTER 0x0 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
/** @} */
// GCLK Generators Config // GCLK Generators Config
#define CONF_CORE_GCLK_0_ENABLE 1 #define CONF_CORE_GCLK_0_ENABLE 1
#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1

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test/same54p20a_test/doc/html/clocks_8c_source.html
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@ -526,19 +526,19 @@ $(function() {
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<div class="ttc" id="aconf__core_8h_html_a1f088d6654bb907ff388ced455b2dbb2"><div class="ttname"><a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_WAITLOCK</div><div class="ttdoc">This bit controls the DFLL output clock, depending on the lock status:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00124">conf_core.h:124</a></div></div> <div class="ttc" id="aconf__core_8h_html_a1f088d6654bb907ff388ced455b2dbb2"><div class="ttname"><a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_WAITLOCK</div><div class="ttdoc">This bit controls the DFLL output clock, depending on the lock status:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00148">conf_core.h:148</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a9de3ab7eb7e3c001d6aa7040f6311f10"><div class="ttname"><a href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL1_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00234">conf_core.h:234</a></div></div> <div class="ttc" id="aconf__core_8h_html_a9de3ab7eb7e3c001d6aa7040f6311f10"><div class="ttname"><a href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL1_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00267">conf_core.h:267</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a5cd9abca6f486eaebb6ddd236960b01a"><div class="ttname"><a href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL0_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00194">conf_core.h:194</a></div></div> <div class="ttc" id="aconf__core_8h_html_a5cd9abca6f486eaebb6ddd236960b01a"><div class="ttname"><a href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL0_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00222">conf_core.h:222</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aa9643e96439d0d47e0684a4b11c1f529"><div class="ttname"><a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a></div><div class="ttdeci">#define CONF_CORE_MCLK_CPUDIV</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00031">conf_core.h:31</a></div></div> <div class="ttc" id="aconf__core_8h_html_aa9643e96439d0d47e0684a4b11c1f529"><div class="ttname"><a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a></div><div class="ttdeci">#define CONF_CORE_MCLK_CPUDIV</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00036">conf_core.h:36</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a625e6fdb4c2120fc163e1b04178af3dd"><div class="ttname"><a href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a></div><div class="ttdeci">#define MCLK</div><div class="ttdoc">(MCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00914">same54n19a.h:914</a></div></div> <div class="ttc" id="asame54n19a_8h_html_a625e6fdb4c2120fc163e1b04178af3dd"><div class="ttname"><a href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a></div><div class="ttdeci">#define MCLK</div><div class="ttdoc">(MCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00914">same54n19a.h:914</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_af1a4b8f1d1a2265b93f22621f7903f88"><div class="ttname"><a href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a></div><div class="ttdeci">#define OSC32KCTRL</div><div class="ttdoc">(OSC32KCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00929">same54n19a.h:929</a></div></div> <div class="ttc" id="asame54n19a_8h_html_af1a4b8f1d1a2265b93f22621f7903f88"><div class="ttname"><a href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a></div><div class="ttdeci">#define OSC32KCTRL</div><div class="ttdoc">(OSC32KCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00929">same54n19a.h:929</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a55515b150245a993779a0d5f417cc828"><div class="ttname"><a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ONDEMAND</div><div class="ttdoc">Enables or Disables on-demand operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00107">conf_core.h:107</a></div></div> <div class="ttc" id="aconf__core_8h_html_a55515b150245a993779a0d5f417cc828"><div class="ttname"><a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ONDEMAND</div><div class="ttdoc">Enables or Disables on-demand operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00132">conf_core.h:132</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a49136ad5bf1adc9e9a0232349bcdce57"><div class="ttname"><a href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a></div><div class="ttdeci">#define OSCCTRL</div><div class="ttdoc">(OSCCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00925">same54n19a.h:925</a></div></div> <div class="ttc" id="asame54n19a_8h_html_a49136ad5bf1adc9e9a0232349bcdce57"><div class="ttname"><a href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a></div><div class="ttdeci">#define OSCCTRL</div><div class="ttdoc">(OSCCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00925">same54n19a.h:925</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ab6b320dcf67ec88f534adcbf77e2ce7b"><div class="ttname"><a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_RUNSTDBY</div><div class="ttdoc">Enables or Disables run-in-standby operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00115">conf_core.h:115</a></div></div> <div class="ttc" id="aconf__core_8h_html_ab6b320dcf67ec88f534adcbf77e2ce7b"><div class="ttname"><a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_RUNSTDBY</div><div class="ttdoc">Enables or Disables run-in-standby operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00140">conf_core.h:140</a></div></div>
<div class="ttc" id="aconf__core_8h_html"><div class="ttname"><a href="conf__core_8h.html">conf_core.h</a></div></div> <div class="ttc" id="aconf__core_8h_html"><div class="ttname"><a href="conf__core_8h.html">conf_core.h</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a03160c4c7871685bbde0e96f02825842"><div class="ttname"><a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ENABLE</div><div class="ttdoc">Enables or Disables the DFLL48M Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00099">conf_core.h:99</a></div></div> <div class="ttc" id="aconf__core_8h_html_a03160c4c7871685bbde0e96f02825842"><div class="ttname"><a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ENABLE</div><div class="ttdoc">Enables or Disables the DFLL48M Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00124">conf_core.h:124</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a23f9186cfd6ee5e60c8485315183271f"><div class="ttname"><a href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a></div><div class="ttdeci">#define GCLK</div><div class="ttdoc">(GCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00894">same54n19a.h:894</a></div></div> <div class="ttc" id="asame54n19a_8h_html_a23f9186cfd6ee5e60c8485315183271f"><div class="ttname"><a href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a></div><div class="ttdeci">#define GCLK</div><div class="ttdoc">(GCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00894">same54n19a.h:894</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a0d8e56832f3d1f24b98173e3a3aa0046"><div class="ttname"><a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_GCLK_SRC</div><div class="ttdoc">GCLK Source used to generate DFLL48M.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00154">conf_core.h:154</a></div></div> <div class="ttc" id="aconf__core_8h_html_a0d8e56832f3d1f24b98173e3a3aa0046"><div class="ttname"><a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_GCLK_SRC</div><div class="ttdoc">GCLK Source used to generate DFLL48M.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00178">conf_core.h:178</a></div></div>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_XTALEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_LOWBUFGAIN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ENALC</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_CFDEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_SWBEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_FREQUENCY</b>&#160;&#160;&#160;12000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ENABLE</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_XTALEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_LOWBUFGAIN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ENALC</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_CFDEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_SWBEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_FREQUENCY</b>&#160;&#160;&#160;12000000</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CGM</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_ONDEMAND</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_EN1K</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_EN32K</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_XTALEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CFDPRESC</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CFDEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_SWBACK</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_WRTLOCK</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDRFRAC_VAL</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDR_VAL</b>&#160;&#160;&#160;(119)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DIV_VAL</b>&#160;&#160;&#160;(5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOEN</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOFILTER</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LBYPASS</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LTIME</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_WUF</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_GCLK_SRC</b>&#160;&#160;&#160;GCLK_GENCTRL_SRC_XOSC0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_REFCLK</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
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<tr class="memitem:a5cd9abca6f486eaebb6ddd236960b01a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ENABLE</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDRFRAC_VAL</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDR_VAL</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DIV_VAL</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOEN</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOFILTER</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LBYPASS</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LTIME</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_WUF</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_GCLK_SRC</b>&#160;&#160;&#160;GCLK_GENCTRL_SRC_XOSC0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_REFCLK</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
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<tr class="memitem:a9de3ab7eb7e3c001d6aa7040f6311f10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a>&#160;&#160;&#160;0x0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_ENABLE</b>&#160;&#160;&#160;1</td></tr> #define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_ENABLE</b>&#160;&#160;&#160;1</td></tr>
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@ -560,6 +378,118 @@ Macros</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_IDC</b>&#160;&#160;&#160;0</td></tr> #define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_IDC</b>&#160;&#160;&#160;0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-Master-Clock-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration options for the master clock. </p>
</div></td></tr>
<tr class="memitem:ab46aa120e454ecf957efa4bd97be5bdf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a>&#160;&#160;&#160;0x5</td></tr>
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<tr class="memitem:aa9643e96439d0d47e0684a4b11c1f529"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:aa9643e96439d0d47e0684a4b11c1f529"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core-XOSC0-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration options for XOSC0. </p>
</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_XTALEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_LOWBUFGAIN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_ENALC</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_CFDEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_SWBEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC0_FREQUENCY</b>&#160;&#160;&#160;12000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-XOSC1-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration options for XOSC1. </p>
</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ENABLE</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_XTALEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_LOWBUFGAIN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_ENALC</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_CFDEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_SWBEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC1_FREQUENCY</b>&#160;&#160;&#160;12000000</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-XOSC32K-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration options for the external 32khz oscillator. </p>
</div></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CGM</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_STARTUP_TIME</b>&#160;&#160;&#160;CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_ONDEMAND</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_EN1K</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_EN32K</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_XTALEN</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CFDPRESC</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_CFDEN</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_SWBACK</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_XOSC32K_WRTLOCK</b>&#160;&#160;&#160;(0)</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DFLL48M-Configuration</div></td></tr> <tr><td colspan="2"><div class="groupHeader">Core-DFLL48M-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration options for DFLL48M </p> <tr><td colspan="2"><div class="groupText"><p>Configuration options for DFLL48M </p>
</div></td></tr> </div></td></tr>
@ -620,6 +550,94 @@ Macros</h2></td></tr>
<tr class="memitem:abfec7438288095803eebaefe1338e54c"><td class="memItemLeft" align="right" valign="top"><a id="abfec7438288095803eebaefe1338e54c"></a> <tr class="memitem:abfec7438288095803eebaefe1338e54c"><td class="memItemLeft" align="right" valign="top"><a id="abfec7438288095803eebaefe1338e54c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_OVERWRITE_CAL</b>&#160;&#160;&#160;0</td></tr> #define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_OVERWRITE_CAL</b>&#160;&#160;&#160;0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DPLL0-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration Options for DPLL0. </p>
</div></td></tr>
<tr class="memitem:a32837c3455721c1e932c7adcccfdf0cd"><td class="memItemLeft" align="right" valign="top"><a id="a32837c3455721c1e932c7adcccfdf0cd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ENABLE</b>&#160;&#160;&#160;(1)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDRFRAC_VAL</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDR_VAL</b>&#160;&#160;&#160;(119)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DIV_VAL</b>&#160;&#160;&#160;(5)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOEN</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOFILTER</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LBYPASS</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LTIME</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_WUF</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_GCLK_SRC</b>&#160;&#160;&#160;GCLK_GENCTRL_SRC_XOSC0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_REFCLK</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
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<tr class="memitem:a5cd9abca6f486eaebb6ddd236960b01a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a>&#160;&#160;&#160;0x0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DPLL1-Configuration</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Configuration Options for DPLL1. </p>
</div></td></tr>
<tr class="memitem:a98d3a5ebaa868e372e467d61e8f0915e"><td class="memItemLeft" align="right" valign="top"><a id="a98d3a5ebaa868e372e467d61e8f0915e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ENABLE</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ONDEMAND</b>&#160;&#160;&#160;(0)</td></tr>
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<tr class="memitem:ac2a6f39d072c0aa33b8c9c90c626f742"><td class="memItemLeft" align="right" valign="top"><a id="ac2a6f39d072c0aa33b8c9c90c626f742"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_RUNSTDBY</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDRFRAC_VAL</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDR_VAL</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DIV_VAL</b>&#160;&#160;&#160;(0)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOEN</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOFILTER</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LBYPASS</b>&#160;&#160;&#160;0</td></tr>
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<tr class="memitem:a51e32a541cfcdef0a10077488b1bda87"><td class="memItemLeft" align="right" valign="top"><a id="a51e32a541cfcdef0a10077488b1bda87"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LTIME</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a51e32a541cfcdef0a10077488b1bda87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a537f2fb05f6ee6cca0692bd32f2e23bb"><td class="memItemLeft" align="right" valign="top"><a id="a537f2fb05f6ee6cca0692bd32f2e23bb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_WUF</b>&#160;&#160;&#160;0</td></tr>
<tr class="separator:a537f2fb05f6ee6cca0692bd32f2e23bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_GCLK_SRC</b>&#160;&#160;&#160;GCLK_GENCTRL_SRC_XOSC0</td></tr>
<tr class="separator:a0780d9ac15356ac35efcc516ef288017"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_REFCLK</b>&#160;&#160;&#160;CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
<tr class="separator:a4ee0e9569732ce043f243a86c068b51a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9de3ab7eb7e3c001d6aa7040f6311f10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a>&#160;&#160;&#160;0x0</td></tr>
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</table> </table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><dl class="section author"><dt>Author</dt><dd>Penguin</dd></dl> <div class="textblock"><dl class="section author"><dt>Author</dt><dd>Penguin</dd></dl>
@ -648,7 +666,7 @@ Description</h1>
pg. 724 of datasheet </li> pg. 724 of datasheet </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00099">99</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00124">124</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
</div> </div>
</div> </div>
@ -680,7 +698,7 @@ pg. 724 of datasheet </li>
<li>11 =&gt; Generic clock generator 11 </li> <li>11 =&gt; Generic clock generator 11 </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00154">154</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00178">178</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
</div> </div>
</div> </div>
@ -703,7 +721,7 @@ pg. 724 of datasheet </li>
pg. 724 of datasheet </li> pg. 724 of datasheet </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00107">107</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00132">132</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
</div> </div>
</div> </div>
@ -726,7 +744,7 @@ pg. 724 of datasheet </li>
pg. 724 of datasheet </li> pg. 724 of datasheet </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00115">115</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00140">140</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
</div> </div>
</div> </div>
@ -745,12 +763,11 @@ pg. 724 of datasheet </li>
<p>This bit controls the DFLL output clock, depending on the lock status: </p> <p>This bit controls the DFLL output clock, depending on the lock status: </p>
<p>DFLL48M Wait Lock Control</p><ul> <p>DFLL48M Wait Lock Control</p><ul>
<li>0 =&gt; Output clock before the DFLL is locked.</li> <li>0 =&gt; Output clock before the DFLL is locked.</li>
<li>1 =&gt; Output clock when DFLL is locked (Fine lock).</li> <li>1 =&gt; Output clock when DFLL is locked (Fine lock). <br />
<li>6: Hello <br />
pg. 725 of datasheet </li> pg. 725 of datasheet </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00124">124</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00148">148</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -768,7 +785,7 @@ pg. 725 of datasheet </li>
<p>pg. 732 of the datasheet FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor 0x0 | 92.7 kHz | 0.76 0x1 | 131 kHz | 1.08 0x2 | 46.4 kHz | 0.38 0x3 | 65.6 kHz | 0.54 0x4 | 131 kHz | 0.56 0x5 | 185 kHz | 0.79 0x6 | 65.6 kHz | 0.28 0x7 | 92.7 kHz | 0.39 0x8 | 46.4 kHz | 1.49 0x9 | 65.6 kHz | 2.11 0xA | 23.2 kHz | 0.75 0xB | 32.8 kHz | 1.06 0xC | 65.6 kHz | 1.07 0xD | 92.7 kHz | 1.51 0xE | 32.8 kHz | 0.53 0xF | 46.4 kHz | 0.75</p> <p>pg. 732 of the datasheet FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor 0x0 | 92.7 kHz | 0.76 0x1 | 131 kHz | 1.08 0x2 | 46.4 kHz | 0.38 0x3 | 65.6 kHz | 0.54 0x4 | 131 kHz | 0.56 0x5 | 185 kHz | 0.79 0x6 | 65.6 kHz | 0.28 0x7 | 92.7 kHz | 0.39 0x8 | 46.4 kHz | 1.49 0x9 | 65.6 kHz | 2.11 0xA | 23.2 kHz | 0.75 0xB | 32.8 kHz | 1.06 0xC | 65.6 kHz | 1.07 0xD | 92.7 kHz | 1.51 0xE | 32.8 kHz | 0.53 0xF | 46.4 kHz | 0.75</p>
<p>When in doubt, leave this at its default. </p> <p>When in doubt, leave this at its default. </p>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00194">194</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00222">222</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -802,7 +819,7 @@ pg. 725 of datasheet </li>
<div class="line">0xF | 46.4 kHz | 0.75</div> <div class="line">0xF | 46.4 kHz | 0.75</div>
</div><!-- fragment --><p>When in doubt, leave this at its default. </p> </div><!-- fragment --><p>When in doubt, leave this at its default. </p>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00234">234</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00267">267</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -822,7 +839,7 @@ pg. 725 of datasheet </li>
<li>1 =&gt; Enabled </li> <li>1 =&gt; Enabled </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00045">45</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00052">52</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -842,7 +859,7 @@ pg. 725 of datasheet </li>
<li>1 =&gt; Enabled </li> <li>1 =&gt; Enabled </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00038">38</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00045">45</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -868,7 +885,7 @@ pg. 725 of datasheet </li>
<li>0x80 =&gt; Clock Divide by 128 </li> <li>0x80 =&gt; Clock Divide by 128 </li>
</ul> </ul>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00031">31</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00036">36</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -885,7 +902,7 @@ pg. 725 of datasheet </li>
</div><div class="memdoc"> </div><div class="memdoc">
<p>Define the number of wait states for the master clock. <a class="el" href="structCan.html" title="CAN APB hardware registers.">Can</a> be [0-15]. </p> <p>Define the number of wait states for the master clock. <a class="el" href="structCan.html" title="CAN APB hardware registers.">Can</a> be [0-15]. </p>
<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00018">18</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p> <p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00023">23</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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@ -74,225 +74,221 @@ $(function() {
<div class="line"><a name="l00011"></a><span class="lineno"> 11</span>&#160;<span class="preprocessor">#define _CONF_CLOCKS_H_</span></div> <div class="line"><a name="l00011"></a><span class="lineno"> 11</span>&#160;<span class="preprocessor">#define _CONF_CLOCKS_H_</span></div>
<div class="line"><a name="l00012"></a><span class="lineno"> 12</span>&#160;<span class="preprocessor">#include &quot;clocks.h&quot;</span></div> <div class="line"><a name="l00012"></a><span class="lineno"> 12</span>&#160;<span class="preprocessor">#include &quot;clocks.h&quot;</span></div>
<div class="line"><a name="l00013"></a><span class="lineno"> 13</span>&#160; </div> <div class="line"><a name="l00013"></a><span class="lineno"> 13</span>&#160; </div>
<div class="line"><a name="l00018"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf"> 18</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5</span></div> <div class="line"><a name="l00023"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf"> 23</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5</span></div>
<div class="line"><a name="l00019"></a><span class="lineno"> 19</span>&#160; </div> <div class="line"><a name="l00024"></a><span class="lineno"> 24</span>&#160; </div>
<div class="line"><a name="l00031"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529"> 31</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_CPUDIV 0x1</span></div> <div class="line"><a name="l00036"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529"> 36</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_CPUDIV 0x1</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>&#160; </div> <div class="line"><a name="l00037"></a><span class="lineno"> 37</span>&#160; </div>
<div class="line"><a name="l00038"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a16a34b830edda5b571c41a0f865f7051"> 38</a></span>&#160;<span class="preprocessor">#define CONF_CORE_DMA_ENABLE (0)</span></div> <div class="line"><a name="l00045"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a16a34b830edda5b571c41a0f865f7051"> 45</a></span>&#160;<span class="preprocessor">#define CONF_CORE_DMA_ENABLE (0)</span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span>&#160; </div>
<div class="line"><a name="l00045"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405"> 45</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CMCC_ENABLE (0)</span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160; </div> <div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160; </div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)</span></div> <div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405"> 52</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CMCC_ENABLE (0)</span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)</span></div> <div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160; </div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)</span></div> <div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)</span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>&#160;<span class="comment">// XOSC0 Config</span></div> <div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)</span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENABLE (1)</span></div> <div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)</span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_XTALEN (1)</span></div> <div class="line"><a name="l00057"></a><span class="lineno"> 57</span>&#160; </div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)</span></div> <div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENABLE (1)</span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)</span></div> <div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_XTALEN (1)</span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)</span></div> <div class="line"><a name="l00064"></a><span class="lineno"> 64</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENALC (1)</span></div> <div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_CFDEN (1)</span></div> <div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_SWBEN (0)</span></div> <div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENALC (1)</span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div> <div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_CFDEN (1)</span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000</span></div> <div class="line"><a name="l00069"></a><span class="lineno"> 69</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_SWBEN (0)</span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span>&#160; </div> <div class="line"><a name="l00070"></a><span class="lineno"> 70</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;<span class="comment">// XOSC1 Config</span></div> <div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENABLE (0)</span></div> <div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160; </div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_XTALEN (0)</span></div> <div class="line"><a name="l00080"></a><span class="lineno"> 80</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENABLE (0)</span></div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)</span></div> <div class="line"><a name="l00081"></a><span class="lineno"> 81</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_XTALEN (0)</span></div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)</span></div> <div class="line"><a name="l00082"></a><span class="lineno"> 82</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)</span></div> <div class="line"><a name="l00083"></a><span class="lineno"> 83</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENALC (0)</span></div> <div class="line"><a name="l00084"></a><span class="lineno"> 84</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00069"></a><span class="lineno"> 69</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_CFDEN (0)</span></div> <div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENALC (0)</span></div>
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_SWBEN (0)</span></div> <div class="line"><a name="l00086"></a><span class="lineno"> 86</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_CFDEN (0)</span></div>
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div> <div class="line"><a name="l00087"></a><span class="lineno"> 87</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_SWBEN (0)</span></div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000</span></div> <div class="line"><a name="l00088"></a><span class="lineno"> 88</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div>
<div class="line"><a name="l00073"></a><span class="lineno"> 73</span>&#160; </div> <div class="line"><a name="l00089"></a><span class="lineno"> 89</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>&#160;<span class="comment">// XOSC32K Config</span></div> <div class="line"><a name="l00090"></a><span class="lineno"> 90</span>&#160; </div>
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ENABLE (1)</span></div> <div class="line"><a name="l00098"></a><span class="lineno"> 98</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ENABLE (1)</span></div>
<div class="line"><a name="l00076"></a><span class="lineno"> 76</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE</span></div> <div class="line"><a name="l00099"></a><span class="lineno"> 99</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE</span></div>
<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</span></div> <div class="line"><a name="l00100"></a><span class="lineno"> 100</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</span></div>
<div class="line"><a name="l00078"></a><span class="lineno"> 78</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)</span></div> <div class="line"><a name="l00101"></a><span class="lineno"> 101</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)</span></div>
<div class="line"><a name="l00079"></a><span class="lineno"> 79</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)</span></div> <div class="line"><a name="l00102"></a><span class="lineno"> 102</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00080"></a><span class="lineno"> 80</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN1K (0)</span></div> <div class="line"><a name="l00103"></a><span class="lineno"> 103</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN1K (0)</span></div>
<div class="line"><a name="l00081"></a><span class="lineno"> 81</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN32K (1)</span></div> <div class="line"><a name="l00104"></a><span class="lineno"> 104</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN32K (1)</span></div>
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_XTALEN (1)</span></div> <div class="line"><a name="l00105"></a><span class="lineno"> 105</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_XTALEN (1)</span></div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)</span></div> <div class="line"><a name="l00106"></a><span class="lineno"> 106</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)</span></div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDEN (0)</span></div> <div class="line"><a name="l00107"></a><span class="lineno"> 107</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDEN (0)</span></div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_SWBACK (0)</span></div> <div class="line"><a name="l00108"></a><span class="lineno"> 108</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_SWBACK (0)</span></div>
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)</span></div> <div class="line"><a name="l00109"></a><span class="lineno"> 109</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)</span></div>
<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>&#160; </div> <div class="line"><a name="l00110"></a><span class="lineno"> 110</span>&#160; </div>
<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842"> 99</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ENABLE (1)</span></div> <div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842"> 124</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ENABLE (1)</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span>&#160; </div> <div class="line"><a name="l00125"></a><span class="lineno"> 125</span>&#160; </div>
<div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828"> 107</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ONDEMAND (0)</span></div> <div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828"> 132</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ONDEMAND (0)</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>&#160; </div> <div class="line"><a name="l00133"></a><span class="lineno"> 133</span>&#160; </div>
<div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b"> 115</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_RUNSTDBY (0)</span></div> <div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b"> 140</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00116"></a><span class="lineno"> 116</span>&#160; </div> <div class="line"><a name="l00141"></a><span class="lineno"> 141</span>&#160; </div>
<div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2"> 124</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_WAITLOCK (0)</span></div> <div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2"> 148</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_WAITLOCK (0)</span></div>
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_BPLKC (0)</span></div> <div class="line"><a name="l00149"></a><span class="lineno"> 149</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_BPLKC (0)</span></div>
<div class="line"><a name="l00126"></a><span class="lineno"> 126</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_QLDIS (0)</span></div> <div class="line"><a name="l00150"></a><span class="lineno"> 150</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_QLDIS (0)</span></div>
<div class="line"><a name="l00127"></a><span class="lineno"> 127</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CCDIS (1)</span></div> <div class="line"><a name="l00151"></a><span class="lineno"> 151</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CCDIS (1)</span></div>
<div class="line"><a name="l00128"></a><span class="lineno"> 128</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_USBCRM (1)</span></div> <div class="line"><a name="l00152"></a><span class="lineno"> 152</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_USBCRM (1)</span></div>
<div class="line"><a name="l00129"></a><span class="lineno"> 129</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_LLAW (0)</span></div> <div class="line"><a name="l00153"></a><span class="lineno"> 153</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_LLAW (0)</span></div>
<div class="line"><a name="l00130"></a><span class="lineno"> 130</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED</span></div> <div class="line"><a name="l00154"></a><span class="lineno"> 154</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED</span></div>
<div class="line"><a name="l00131"></a><span class="lineno"> 131</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MODE 0x01</span></div> <div class="line"><a name="l00155"></a><span class="lineno"> 155</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MODE 0x01</span></div>
<div class="line"><a name="l00132"></a><span class="lineno"> 132</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_DIFF_VAL 0</span></div> <div class="line"><a name="l00156"></a><span class="lineno"> 156</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_DIFF_VAL 0</span></div>
<div class="line"><a name="l00133"></a><span class="lineno"> 133</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)</span></div> <div class="line"><a name="l00157"></a><span class="lineno"> 157</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)</span></div>
<div class="line"><a name="l00134"></a><span class="lineno"> 134</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FINE_VAL 128</span></div> <div class="line"><a name="l00158"></a><span class="lineno"> 158</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FINE_VAL 128</span></div>
<div class="line"><a name="l00135"></a><span class="lineno"> 135</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CSTEP_VAL 1</span></div> <div class="line"><a name="l00159"></a><span class="lineno"> 159</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CSTEP_VAL 1</span></div>
<div class="line"><a name="l00136"></a><span class="lineno"> 136</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FSTEP_VAL 1</span></div> <div class="line"><a name="l00160"></a><span class="lineno"> 160</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FSTEP_VAL 1</span></div>
<div class="line"><a name="l00137"></a><span class="lineno"> 137</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)</span></div> <div class="line"><a name="l00161"></a><span class="lineno"> 161</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)</span></div>
<div class="line"><a name="l00138"></a><span class="lineno"> 138</span>&#160; </div> <div class="line"><a name="l00162"></a><span class="lineno"> 162</span>&#160; </div>
<div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046"> 154</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_GCLK_SRC 3</span></div> <div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046"> 178</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_GCLK_SRC 3</span></div>
<div class="line"><a name="l00155"></a><span class="lineno"> 155</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0</span></div> <div class="line"><a name="l00179"></a><span class="lineno"> 179</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0</span></div>
<div class="line"><a name="l00156"></a><span class="lineno"> 156</span>&#160; </div> <div class="line"><a name="l00180"></a><span class="lineno"> 180</span>&#160; </div>
<div class="line"><a name="l00158"></a><span class="lineno"> 158</span>&#160;<span class="comment">// DPLL0 Config</span></div> <div class="line"><a name="l00187"></a><span class="lineno"> 187</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ENABLE (1)</span></div>
<div class="line"><a name="l00159"></a><span class="lineno"> 159</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ENABLE (1)</span></div> <div class="line"><a name="l00188"></a><span class="lineno"> 188</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00160"></a><span class="lineno"> 160</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ONDEMAND (0)</span></div> <div class="line"><a name="l00189"></a><span class="lineno"> 189</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00161"></a><span class="lineno"> 161</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)</span></div> <div class="line"><a name="l00190"></a><span class="lineno"> 190</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00162"></a><span class="lineno"> 162</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0</span></div> <div class="line"><a name="l00191"></a><span class="lineno"> 191</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDR_VAL (119)</span></div>
<div class="line"><a name="l00163"></a><span class="lineno"> 163</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDR_VAL (119)</span></div> <div class="line"><a name="l00192"></a><span class="lineno"> 192</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DIV_VAL (5)</span></div>
<div class="line"><a name="l00164"></a><span class="lineno"> 164</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DIV_VAL (5)</span></div> <div class="line"><a name="l00193"></a><span class="lineno"> 193</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOEN 0</span></div>
<div class="line"><a name="l00165"></a><span class="lineno"> 165</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOEN 0</span></div> <div class="line"><a name="l00194"></a><span class="lineno"> 194</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00166"></a><span class="lineno"> 166</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div> <div class="line"><a name="l00195"></a><span class="lineno"> 195</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LBYPASS 1</span></div>
<div class="line"><a name="l00167"></a><span class="lineno"> 167</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LBYPASS 1</span></div> <div class="line"><a name="l00196"></a><span class="lineno"> 196</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LTIME 0</span></div>
<div class="line"><a name="l00168"></a><span class="lineno"> 168</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LTIME 0</span></div> <div class="line"><a name="l00197"></a><span class="lineno"> 197</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_WUF 0</span></div>
<div class="line"><a name="l00169"></a><span class="lineno"> 169</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_WUF 0</span></div> <div class="line"><a name="l00198"></a><span class="lineno"> 198</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00170"></a><span class="lineno"> 170</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00199"></a><span class="lineno"> 199</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00171"></a><span class="lineno"> 171</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div> <div class="line"><a name="l00200"></a><span class="lineno"> 200</span>&#160; </div>
<div class="line"><a name="l00172"></a><span class="lineno"> 172</span>&#160; </div> <div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a"> 222</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_FILTER 0x0</span></div>
<div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a"> 194</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_FILTER 0x0</span></div> <div class="line"><a name="l00223"></a><span class="lineno"> 223</span>&#160; </div>
<div class="line"><a name="l00195"></a><span class="lineno"> 195</span>&#160; </div> <div class="line"><a name="l00230"></a><span class="lineno"> 230</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ENABLE (0)</span></div>
<div class="line"><a name="l00196"></a><span class="lineno"> 196</span>&#160;<span class="comment">// DPLL1 Config</span></div> <div class="line"><a name="l00231"></a><span class="lineno"> 231</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00197"></a><span class="lineno"> 197</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ENABLE (0)</span></div> <div class="line"><a name="l00232"></a><span class="lineno"> 232</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00198"></a><span class="lineno"> 198</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ONDEMAND (0)</span></div> <div class="line"><a name="l00233"></a><span class="lineno"> 233</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)</span></div> <div class="line"><a name="l00234"></a><span class="lineno"> 234</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDR_VAL (0)</span></div>
<div class="line"><a name="l00200"></a><span class="lineno"> 200</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0</span></div> <div class="line"><a name="l00235"></a><span class="lineno"> 235</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DIV_VAL (0)</span></div>
<div class="line"><a name="l00201"></a><span class="lineno"> 201</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDR_VAL (0)</span></div> <div class="line"><a name="l00236"></a><span class="lineno"> 236</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOEN 0</span></div>
<div class="line"><a name="l00202"></a><span class="lineno"> 202</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DIV_VAL (0)</span></div> <div class="line"><a name="l00237"></a><span class="lineno"> 237</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00203"></a><span class="lineno"> 203</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOEN 0</span></div> <div class="line"><a name="l00238"></a><span class="lineno"> 238</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LBYPASS 0</span></div>
<div class="line"><a name="l00204"></a><span class="lineno"> 204</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div> <div class="line"><a name="l00239"></a><span class="lineno"> 239</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LTIME 0</span></div>
<div class="line"><a name="l00205"></a><span class="lineno"> 205</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LBYPASS 0</span></div> <div class="line"><a name="l00240"></a><span class="lineno"> 240</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_WUF 0</span></div>
<div class="line"><a name="l00206"></a><span class="lineno"> 206</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LTIME 0</span></div> <div class="line"><a name="l00241"></a><span class="lineno"> 241</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00207"></a><span class="lineno"> 207</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_WUF 0</span></div> <div class="line"><a name="l00242"></a><span class="lineno"> 242</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00208"></a><span class="lineno"> 208</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00243"></a><span class="lineno"> 243</span>&#160; </div>
<div class="line"><a name="l00209"></a><span class="lineno"> 209</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div> <div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10"> 267</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_FILTER 0x0</span></div>
<div class="line"><a name="l00210"></a><span class="lineno"> 210</span>&#160; </div> <div class="line"><a name="l00268"></a><span class="lineno"> 268</span>&#160; </div>
<div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10"> 234</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_FILTER 0x0</span></div> <div class="line"><a name="l00271"></a><span class="lineno"> 271</span>&#160;<span class="comment">// GCLK Generators Config</span></div>
<div class="line"><a name="l00235"></a><span class="lineno"> 235</span>&#160; </div> <div class="line"><a name="l00272"></a><span class="lineno"> 272</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_ENABLE 1</span></div>
<div class="line"><a name="l00236"></a><span class="lineno"> 236</span>&#160;<span class="comment">// GCLK Generators Config</span></div> <div class="line"><a name="l00273"></a><span class="lineno"> 273</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1</span></div>
<div class="line"><a name="l00237"></a><span class="lineno"> 237</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_ENABLE 1</span></div> <div class="line"><a name="l00274"></a><span class="lineno"> 274</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00238"></a><span class="lineno"> 238</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1</span></div> <div class="line"><a name="l00275"></a><span class="lineno"> 275</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIV_VAL 1</span></div>
<div class="line"><a name="l00239"></a><span class="lineno"> 239</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00276"></a><span class="lineno"> 276</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIVSEL 0</span></div>
<div class="line"><a name="l00240"></a><span class="lineno"> 240</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIV_VAL 1</span></div> <div class="line"><a name="l00277"></a><span class="lineno"> 277</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1</span></div>
<div class="line"><a name="l00241"></a><span class="lineno"> 241</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIVSEL 0</span></div> <div class="line"><a name="l00278"></a><span class="lineno"> 278</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1</span></div>
<div class="line"><a name="l00242"></a><span class="lineno"> 242</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1</span></div> <div class="line"><a name="l00279"></a><span class="lineno"> 279</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_IDC 1</span></div>
<div class="line"><a name="l00243"></a><span class="lineno"> 243</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1</span></div> <div class="line"><a name="l00280"></a><span class="lineno"> 280</span>&#160; </div>
<div class="line"><a name="l00244"></a><span class="lineno"> 244</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_IDC 1</span></div> <div class="line"><a name="l00281"></a><span class="lineno"> 281</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_ENABLE 0</span></div>
<div class="line"><a name="l00245"></a><span class="lineno"> 245</span>&#160; </div> <div class="line"><a name="l00282"></a><span class="lineno"> 282</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00246"></a><span class="lineno"> 246</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_ENABLE 0</span></div> <div class="line"><a name="l00283"></a><span class="lineno"> 283</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00247"></a><span class="lineno"> 247</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00284"></a><span class="lineno"> 284</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIV_VAL 1</span></div>
<div class="line"><a name="l00248"></a><span class="lineno"> 248</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00285"></a><span class="lineno"> 285</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIVSEL 0</span></div>
<div class="line"><a name="l00249"></a><span class="lineno"> 249</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIV_VAL 1</span></div> <div class="line"><a name="l00286"></a><span class="lineno"> 286</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00250"></a><span class="lineno"> 250</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIVSEL 0</span></div> <div class="line"><a name="l00287"></a><span class="lineno"> 287</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00251"></a><span class="lineno"> 251</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00288"></a><span class="lineno"> 288</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_IDC 0</span></div>
<div class="line"><a name="l00252"></a><span class="lineno"> 252</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00289"></a><span class="lineno"> 289</span>&#160; </div>
<div class="line"><a name="l00253"></a><span class="lineno"> 253</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_IDC 0</span></div> <div class="line"><a name="l00290"></a><span class="lineno"> 290</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_ENABLE 0</span></div>
<div class="line"><a name="l00254"></a><span class="lineno"> 254</span>&#160; </div> <div class="line"><a name="l00291"></a><span class="lineno"> 291</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00255"></a><span class="lineno"> 255</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_ENABLE 0</span></div> <div class="line"><a name="l00292"></a><span class="lineno"> 292</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00256"></a><span class="lineno"> 256</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00293"></a><span class="lineno"> 293</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIV_VAL 1</span></div>
<div class="line"><a name="l00257"></a><span class="lineno"> 257</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00294"></a><span class="lineno"> 294</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIVSEL 0</span></div>
<div class="line"><a name="l00258"></a><span class="lineno"> 258</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIV_VAL 1</span></div> <div class="line"><a name="l00295"></a><span class="lineno"> 295</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00259"></a><span class="lineno"> 259</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIVSEL 0</span></div> <div class="line"><a name="l00296"></a><span class="lineno"> 296</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00260"></a><span class="lineno"> 260</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00297"></a><span class="lineno"> 297</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_IDC 0</span></div>
<div class="line"><a name="l00261"></a><span class="lineno"> 261</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00298"></a><span class="lineno"> 298</span>&#160; </div>
<div class="line"><a name="l00262"></a><span class="lineno"> 262</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_IDC 0</span></div> <div class="line"><a name="l00299"></a><span class="lineno"> 299</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_ENABLE 1</span></div>
<div class="line"><a name="l00263"></a><span class="lineno"> 263</span>&#160; </div> <div class="line"><a name="l00300"></a><span class="lineno"> 300</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00264"></a><span class="lineno"> 264</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_ENABLE 1</span></div> <div class="line"><a name="l00301"></a><span class="lineno"> 301</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K</span></div>
<div class="line"><a name="l00265"></a><span class="lineno"> 265</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00302"></a><span class="lineno"> 302</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIV_VAL 1</span></div>
<div class="line"><a name="l00266"></a><span class="lineno"> 266</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K</span></div> <div class="line"><a name="l00303"></a><span class="lineno"> 303</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIVSEL 0</span></div>
<div class="line"><a name="l00267"></a><span class="lineno"> 267</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIV_VAL 1</span></div> <div class="line"><a name="l00304"></a><span class="lineno"> 304</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00268"></a><span class="lineno"> 268</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIVSEL 0</span></div> <div class="line"><a name="l00305"></a><span class="lineno"> 305</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00269"></a><span class="lineno"> 269</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00306"></a><span class="lineno"> 306</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_IDC 0</span></div>
<div class="line"><a name="l00270"></a><span class="lineno"> 270</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00307"></a><span class="lineno"> 307</span>&#160; </div>
<div class="line"><a name="l00271"></a><span class="lineno"> 271</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_IDC 0</span></div> <div class="line"><a name="l00308"></a><span class="lineno"> 308</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_ENABLE 0</span></div>
<div class="line"><a name="l00272"></a><span class="lineno"> 272</span>&#160; </div> <div class="line"><a name="l00309"></a><span class="lineno"> 309</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00273"></a><span class="lineno"> 273</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_ENABLE 0</span></div> <div class="line"><a name="l00310"></a><span class="lineno"> 310</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00274"></a><span class="lineno"> 274</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00311"></a><span class="lineno"> 311</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIV_VAL 1</span></div>
<div class="line"><a name="l00275"></a><span class="lineno"> 275</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00312"></a><span class="lineno"> 312</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIVSEL 1</span></div>
<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIV_VAL 1</span></div> <div class="line"><a name="l00313"></a><span class="lineno"> 313</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00277"></a><span class="lineno"> 277</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIVSEL 1</span></div> <div class="line"><a name="l00314"></a><span class="lineno"> 314</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00278"></a><span class="lineno"> 278</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00315"></a><span class="lineno"> 315</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_IDC 0</span></div>
<div class="line"><a name="l00279"></a><span class="lineno"> 279</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00316"></a><span class="lineno"> 316</span>&#160; </div>
<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_IDC 0</span></div> <div class="line"><a name="l00317"></a><span class="lineno"> 317</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_ENABLE 0</span></div>
<div class="line"><a name="l00281"></a><span class="lineno"> 281</span>&#160; </div> <div class="line"><a name="l00318"></a><span class="lineno"> 318</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00282"></a><span class="lineno"> 282</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_ENABLE 0</span></div> <div class="line"><a name="l00319"></a><span class="lineno"> 319</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00283"></a><span class="lineno"> 283</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00320"></a><span class="lineno"> 320</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIV_VAL 1</span></div>
<div class="line"><a name="l00284"></a><span class="lineno"> 284</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00321"></a><span class="lineno"> 321</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIVSEL 0</span></div>
<div class="line"><a name="l00285"></a><span class="lineno"> 285</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIV_VAL 1</span></div> <div class="line"><a name="l00322"></a><span class="lineno"> 322</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00286"></a><span class="lineno"> 286</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIVSEL 0</span></div> <div class="line"><a name="l00323"></a><span class="lineno"> 323</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00287"></a><span class="lineno"> 287</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00324"></a><span class="lineno"> 324</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_IDC 0</span></div>
<div class="line"><a name="l00288"></a><span class="lineno"> 288</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00325"></a><span class="lineno"> 325</span>&#160; </div>
<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_IDC 0</span></div> <div class="line"><a name="l00326"></a><span class="lineno"> 326</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_ENABLE 0</span></div>
<div class="line"><a name="l00290"></a><span class="lineno"> 290</span>&#160; </div> <div class="line"><a name="l00327"></a><span class="lineno"> 327</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00291"></a><span class="lineno"> 291</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_ENABLE 0</span></div> <div class="line"><a name="l00328"></a><span class="lineno"> 328</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00292"></a><span class="lineno"> 292</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00329"></a><span class="lineno"> 329</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIV_VAL 1</span></div>
<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00330"></a><span class="lineno"> 330</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIVSEL 0</span></div>
<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIV_VAL 1</span></div> <div class="line"><a name="l00331"></a><span class="lineno"> 331</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00295"></a><span class="lineno"> 295</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIVSEL 0</span></div> <div class="line"><a name="l00332"></a><span class="lineno"> 332</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00296"></a><span class="lineno"> 296</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00333"></a><span class="lineno"> 333</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_IDC 0</span></div>
<div class="line"><a name="l00297"></a><span class="lineno"> 297</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00334"></a><span class="lineno"> 334</span>&#160; </div>
<div class="line"><a name="l00298"></a><span class="lineno"> 298</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_IDC 0</span></div> <div class="line"><a name="l00335"></a><span class="lineno"> 335</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_ENABLE 0</span></div>
<div class="line"><a name="l00299"></a><span class="lineno"> 299</span>&#160; </div> <div class="line"><a name="l00336"></a><span class="lineno"> 336</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00300"></a><span class="lineno"> 300</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_ENABLE 0</span></div> <div class="line"><a name="l00337"></a><span class="lineno"> 337</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00301"></a><span class="lineno"> 301</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00338"></a><span class="lineno"> 338</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIV_VAL 1</span></div>
<div class="line"><a name="l00302"></a><span class="lineno"> 302</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00339"></a><span class="lineno"> 339</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIVSEL 0</span></div>
<div class="line"><a name="l00303"></a><span class="lineno"> 303</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIV_VAL 1</span></div> <div class="line"><a name="l00340"></a><span class="lineno"> 340</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00304"></a><span class="lineno"> 304</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIVSEL 0</span></div> <div class="line"><a name="l00341"></a><span class="lineno"> 341</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00305"></a><span class="lineno"> 305</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00342"></a><span class="lineno"> 342</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_IDC 0</span></div>
<div class="line"><a name="l00306"></a><span class="lineno"> 306</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00343"></a><span class="lineno"> 343</span>&#160; </div>
<div class="line"><a name="l00307"></a><span class="lineno"> 307</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_IDC 0</span></div> <div class="line"><a name="l00344"></a><span class="lineno"> 344</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_ENABLE 0</span></div>
<div class="line"><a name="l00308"></a><span class="lineno"> 308</span>&#160; </div> <div class="line"><a name="l00345"></a><span class="lineno"> 345</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00309"></a><span class="lineno"> 309</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_ENABLE 0</span></div> <div class="line"><a name="l00346"></a><span class="lineno"> 346</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00310"></a><span class="lineno"> 310</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00347"></a><span class="lineno"> 347</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIV_VAL 1</span></div>
<div class="line"><a name="l00311"></a><span class="lineno"> 311</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00348"></a><span class="lineno"> 348</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIVSEL 0</span></div>
<div class="line"><a name="l00312"></a><span class="lineno"> 312</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIV_VAL 1</span></div> <div class="line"><a name="l00349"></a><span class="lineno"> 349</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00313"></a><span class="lineno"> 313</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIVSEL 0</span></div> <div class="line"><a name="l00350"></a><span class="lineno"> 350</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00314"></a><span class="lineno"> 314</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00351"></a><span class="lineno"> 351</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_IDC 0</span></div>
<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00352"></a><span class="lineno"> 352</span>&#160; </div>
<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_IDC 0</span></div> <div class="line"><a name="l00353"></a><span class="lineno"> 353</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_ENABLE 0</span></div>
<div class="line"><a name="l00317"></a><span class="lineno"> 317</span>&#160; </div> <div class="line"><a name="l00354"></a><span class="lineno"> 354</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00318"></a><span class="lineno"> 318</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_ENABLE 0</span></div> <div class="line"><a name="l00355"></a><span class="lineno"> 355</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00319"></a><span class="lineno"> 319</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00356"></a><span class="lineno"> 356</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIV_VAL 1</span></div>
<div class="line"><a name="l00320"></a><span class="lineno"> 320</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00357"></a><span class="lineno"> 357</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIVSEL 0</span></div>
<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIV_VAL 1</span></div> <div class="line"><a name="l00358"></a><span class="lineno"> 358</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00322"></a><span class="lineno"> 322</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIVSEL 0</span></div> <div class="line"><a name="l00359"></a><span class="lineno"> 359</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00360"></a><span class="lineno"> 360</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_IDC 0</span></div>
<div class="line"><a name="l00324"></a><span class="lineno"> 324</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00361"></a><span class="lineno"> 361</span>&#160; </div>
<div class="line"><a name="l00325"></a><span class="lineno"> 325</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_IDC 0</span></div> <div class="line"><a name="l00362"></a><span class="lineno"> 362</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_ENABLE 0</span></div>
<div class="line"><a name="l00326"></a><span class="lineno"> 326</span>&#160; </div> <div class="line"><a name="l00363"></a><span class="lineno"> 363</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00327"></a><span class="lineno"> 327</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_ENABLE 0</span></div> <div class="line"><a name="l00364"></a><span class="lineno"> 364</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00328"></a><span class="lineno"> 328</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00365"></a><span class="lineno"> 365</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIV_VAL 1</span></div>
<div class="line"><a name="l00329"></a><span class="lineno"> 329</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00366"></a><span class="lineno"> 366</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIVSEL 0</span></div>
<div class="line"><a name="l00330"></a><span class="lineno"> 330</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIV_VAL 1</span></div> <div class="line"><a name="l00367"></a><span class="lineno"> 367</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00331"></a><span class="lineno"> 331</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIVSEL 0</span></div> <div class="line"><a name="l00368"></a><span class="lineno"> 368</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00332"></a><span class="lineno"> 332</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00369"></a><span class="lineno"> 369</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_IDC 0</span></div>
<div class="line"><a name="l00333"></a><span class="lineno"> 333</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00370"></a><span class="lineno"> 370</span>&#160; </div>
<div class="line"><a name="l00334"></a><span class="lineno"> 334</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_IDC 0</span></div> <div class="line"><a name="l00371"></a><span class="lineno"> 371</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_ENABLE 0</span></div>
<div class="line"><a name="l00335"></a><span class="lineno"> 335</span>&#160; </div> <div class="line"><a name="l00372"></a><span class="lineno"> 372</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00336"></a><span class="lineno"> 336</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_ENABLE 0</span></div> <div class="line"><a name="l00373"></a><span class="lineno"> 373</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00337"></a><span class="lineno"> 337</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0</span></div> <div class="line"><a name="l00374"></a><span class="lineno"> 374</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIV_VAL 1</span></div>
<div class="line"><a name="l00338"></a><span class="lineno"> 338</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div> <div class="line"><a name="l00375"></a><span class="lineno"> 375</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIVSEL 0</span></div>
<div class="line"><a name="l00339"></a><span class="lineno"> 339</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIV_VAL 1</span></div> <div class="line"><a name="l00376"></a><span class="lineno"> 376</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00340"></a><span class="lineno"> 340</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIVSEL 0</span></div> <div class="line"><a name="l00377"></a><span class="lineno"> 377</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00341"></a><span class="lineno"> 341</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0</span></div> <div class="line"><a name="l00378"></a><span class="lineno"> 378</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_IDC 0</span></div>
<div class="line"><a name="l00342"></a><span class="lineno"> 342</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0</span></div> <div class="line"><a name="l00379"></a><span class="lineno"> 379</span>&#160; </div>
<div class="line"><a name="l00343"></a><span class="lineno"> 343</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_IDC 0</span></div> <div class="line"><a name="l00380"></a><span class="lineno"> 380</span>&#160; </div>
<div class="line"><a name="l00344"></a><span class="lineno"> 344</span>&#160; </div> <div class="line"><a name="l00381"></a><span class="lineno"> 381</span>&#160; </div>
<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>&#160; </div> <div class="line"><a name="l00382"></a><span class="lineno"> 382</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00346"></a><span class="lineno"> 346</span>&#160; </div>
<div class="line"><a name="l00347"></a><span class="lineno"> 347</span>&#160;<span class="preprocessor">#endif</span></div>
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<div class="ttc" id="aconf__core_8h_html_ab46aa120e454ecf957efa4bd97be5bdf"><div class="ttname"><a href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a></div><div class="ttdeci">#define CONF_CORE_MCLK_NVM_WAIT_STATE</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00018">conf_core.h:18</a></div></div> <div class="ttc" id="aconf__core_8h_html_ab46aa120e454ecf957efa4bd97be5bdf"><div class="ttname"><a href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a></div><div class="ttdeci">#define CONF_CORE_MCLK_NVM_WAIT_STATE</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00023">conf_core.h:23</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_ad18608913d3d6e423f3a79d84348910a"><div class="ttname"><a href="same54n19a_8h.html#ad18608913d3d6e423f3a79d84348910a">NVMCTRL</a></div><div class="ttdeci">#define NVMCTRL</div><div class="ttdoc">(NVMCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00918">same54n19a.h:918</a></div></div> <div class="ttc" id="asame54n19a_8h_html_ad18608913d3d6e423f3a79d84348910a"><div class="ttname"><a href="same54n19a_8h.html#ad18608913d3d6e423f3a79d84348910a">NVMCTRL</a></div><div class="ttdeci">#define NVMCTRL</div><div class="ttdoc">(NVMCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00918">same54n19a.h:918</a></div></div>
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