diff --git a/test/same54p20a_test/cfg/conf_core.h b/test/same54p20a_test/cfg/conf_core.h index 92544327..d90a74b1 100644 --- a/test/same54p20a_test/cfg/conf_core.h +++ b/test/same54p20a_test/cfg/conf_core.h @@ -11,6 +11,11 @@ #define _CONF_CLOCKS_H_ #include "clocks.h" +/** @name Core-Master-Clock-Configuration + * Configuration options for the master clock. + * @{ + */ + /** * Define the number of wait states for the master clock. * Can be [0-15]. @@ -35,6 +40,8 @@ * - 0 => Disabled * - 1 => Enabled */ + +/** @} */ #define CONF_CORE_DMA_ENABLE (0) /** @@ -47,7 +54,11 @@ #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0) #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0) #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0) -// XOSC0 Config +/** @name Core-XOSC0-Configuration + * Configuration options for XOSC0. + * @{ + */ + #define CONF_CORE_CLK_XOSC0_ENABLE (1) #define CONF_CORE_CLK_XOSC0_XTALEN (1) #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0) @@ -59,7 +70,13 @@ #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000 -// XOSC1 Config +/** @} */ + +/** @name Core-XOSC1-Configuration + * Configuration options for XOSC1. + * @{ + */ + #define CONF_CORE_CLK_XOSC1_ENABLE (0) #define CONF_CORE_CLK_XOSC1_XTALEN (0) #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0) @@ -71,7 +88,13 @@ #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000 -// XOSC32K Config +/** @} */ + +/** @name Core-XOSC32K-Configuration + * Configuration options for the external 32khz oscillator. + * @{ + */ + #define CONF_CORE_CLK_XOSC32K_ENABLE (1) #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us @@ -85,6 +108,8 @@ #define CONF_CORE_CLK_XOSC32K_SWBACK (0) #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0) +/** @} */ + /** @name Core-DFLL48M-Configuration * Configuration options for DFLL48M */ @@ -154,7 +179,11 @@ #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0 /** @} */ -// DPLL0 Config +/** @name Core-DPLL0-Configuration + * Configuration Options for DPLL0. + * @{ + */ + #define CONF_CORE_CLK_DPLL0_ENABLE (1) #define CONF_CORE_CLK_DPLL0_ONDEMAND (0) #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0) @@ -192,7 +221,12 @@ */ #define CONF_CORE_CLK_DPLL0_FILTER 0x0 -// DPLL1 Config +/** @} */ + +/** @name Core-DPLL1-Configuration + * Configuration Options for DPLL1. + * @{ + */ #define CONF_CORE_CLK_DPLL1_ENABLE (0) #define CONF_CORE_CLK_DPLL1_ONDEMAND (0) #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0) @@ -232,6 +266,8 @@ */ #define CONF_CORE_CLK_DPLL1_FILTER 0x0 +/** @} */ + // GCLK Generators Config #define CONF_CORE_GCLK_0_ENABLE 1 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1 diff --git a/test/same54p20a_test/doc/html/clocks_8c_source.html b/test/same54p20a_test/doc/html/clocks_8c_source.html index cb270577..c0dfeafd 100644 --- a/test/same54p20a_test/doc/html/clocks_8c_source.html +++ b/test/same54p20a_test/doc/html/clocks_8c_source.html @@ -526,19 +526,19 @@ $(function() {
455 #endif
456 }
-
CONF_CORE_CLK_DFLL_WAITLOCK
#define CONF_CORE_CLK_DFLL_WAITLOCK
This bit controls the DFLL output clock, depending on the lock status:
Definition: conf_core.h:124
-
CONF_CORE_CLK_DPLL1_FILTER
#define CONF_CORE_CLK_DPLL1_FILTER
Definition: conf_core.h:234
-
CONF_CORE_CLK_DPLL0_FILTER
#define CONF_CORE_CLK_DPLL0_FILTER
Definition: conf_core.h:194
-
CONF_CORE_MCLK_CPUDIV
#define CONF_CORE_MCLK_CPUDIV
Definition: conf_core.h:31
+
CONF_CORE_CLK_DFLL_WAITLOCK
#define CONF_CORE_CLK_DFLL_WAITLOCK
This bit controls the DFLL output clock, depending on the lock status:
Definition: conf_core.h:148
+
CONF_CORE_CLK_DPLL1_FILTER
#define CONF_CORE_CLK_DPLL1_FILTER
Definition: conf_core.h:267
+
CONF_CORE_CLK_DPLL0_FILTER
#define CONF_CORE_CLK_DPLL0_FILTER
Definition: conf_core.h:222
+
CONF_CORE_MCLK_CPUDIV
#define CONF_CORE_MCLK_CPUDIV
Definition: conf_core.h:36
MCLK
#define MCLK
(MCLK) APB Base Address
Definition: same54n19a.h:914
OSC32KCTRL
#define OSC32KCTRL
(OSC32KCTRL) APB Base Address
Definition: same54n19a.h:929
-
CONF_CORE_CLK_DFLL_ONDEMAND
#define CONF_CORE_CLK_DFLL_ONDEMAND
Enables or Disables on-demand operation.
Definition: conf_core.h:107
+
CONF_CORE_CLK_DFLL_ONDEMAND
#define CONF_CORE_CLK_DFLL_ONDEMAND
Enables or Disables on-demand operation.
Definition: conf_core.h:132
OSCCTRL
#define OSCCTRL
(OSCCTRL) APB Base Address
Definition: same54n19a.h:925
-
CONF_CORE_CLK_DFLL_RUNSTDBY
#define CONF_CORE_CLK_DFLL_RUNSTDBY
Enables or Disables run-in-standby operation.
Definition: conf_core.h:115
+
CONF_CORE_CLK_DFLL_RUNSTDBY
#define CONF_CORE_CLK_DFLL_RUNSTDBY
Enables or Disables run-in-standby operation.
Definition: conf_core.h:140
conf_core.h
-
CONF_CORE_CLK_DFLL_ENABLE
#define CONF_CORE_CLK_DFLL_ENABLE
Enables or Disables the DFLL48M Clock.
Definition: conf_core.h:99
+
CONF_CORE_CLK_DFLL_ENABLE
#define CONF_CORE_CLK_DFLL_ENABLE
Enables or Disables the DFLL48M Clock.
Definition: conf_core.h:124
GCLK
#define GCLK
(GCLK) APB Base Address
Definition: same54n19a.h:894
-
CONF_CORE_CLK_DFLL_GCLK_SRC
#define CONF_CORE_CLK_DFLL_GCLK_SRC
GCLK Source used to generate DFLL48M.
Definition: conf_core.h:154
+
CONF_CORE_CLK_DFLL_GCLK_SRC
#define CONF_CORE_CLK_DFLL_GCLK_SRC
GCLK Source used to generate DFLL48M.
Definition: conf_core.h:178
Generated by doxygen 1.8.20 diff --git a/test/same54p20a_test/doc/html/conf__core_8h.html b/test/same54p20a_test/doc/html/conf__core_8h.html index 636fc605..f5dcba59 100644 --- a/test/same54p20a_test/doc/html/conf__core_8h.html +++ b/test/same54p20a_test/doc/html/conf__core_8h.html @@ -77,10 +77,6 @@ $(function() { - - - - @@ -94,184 +90,6 @@ Macros - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -560,6 +378,118 @@ Macros + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -620,6 +550,94 @@ Macros + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Macros

#define CONF_CORE_MCLK_NVM_WAIT_STATE   0x5
 
#define CONF_CORE_MCLK_CPUDIV   0x1
 
#define CONF_CORE_DMA_ENABLE   (0)
 
#define CONF_CORE_CMCC_ENABLE   (0)
#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)
 
-#define CONF_CORE_CLK_XOSC0_ENABLE   (1)
 
-#define CONF_CORE_CLK_XOSC0_XTALEN   (1)
 
-#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)
 
-#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0)
 
-#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)
 
-#define CONF_CORE_CLK_XOSC0_ENALC   (1)
 
-#define CONF_CORE_CLK_XOSC0_CFDEN   (1)
 
-#define CONF_CORE_CLK_XOSC0_SWBEN   (0)
 
-#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
 
-#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000
 
-#define CONF_CORE_CLK_XOSC1_ENABLE   (0)
 
-#define CONF_CORE_CLK_XOSC1_XTALEN   (0)
 
-#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)
 
-#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0)
 
-#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)
 
-#define CONF_CORE_CLK_XOSC1_ENALC   (0)
 
-#define CONF_CORE_CLK_XOSC1_CFDEN   (0)
 
-#define CONF_CORE_CLK_XOSC1_SWBEN   (0)
 
-#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
 
-#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000
 
-#define CONF_CORE_CLK_XOSC32K_ENABLE   (1)
 
-#define CONF_CORE_CLK_XOSC32K_CGM   CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
 
-#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
 
-#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)
 
-#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)
 
-#define CONF_CORE_CLK_XOSC32K_EN1K   (0)
 
-#define CONF_CORE_CLK_XOSC32K_EN32K   (1)
 
-#define CONF_CORE_CLK_XOSC32K_XTALEN   (1)
 
-#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)
 
-#define CONF_CORE_CLK_XOSC32K_CFDEN   (0)
 
-#define CONF_CORE_CLK_XOSC32K_SWBACK   (0)
 
-#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)
 
-#define CONF_CORE_CLK_DPLL0_ENABLE   (1)
 
-#define CONF_CORE_CLK_DPLL0_ONDEMAND   (0)
 
-#define CONF_CORE_CLK_DPLL0_RUNSTDBY   (0)
 
-#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL   0
 
-#define CONF_CORE_CLK_DPLL0_LDR_VAL   (119)
 
-#define CONF_CORE_CLK_DPLL0_DIV_VAL   (5)
 
-#define CONF_CORE_CLK_DPLL0_DCOEN   0
 
-#define CONF_CORE_CLK_DPLL0_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
 
-#define CONF_CORE_CLK_DPLL0_LBYPASS   1
 
-#define CONF_CORE_CLK_DPLL0_LTIME   0
 
-#define CONF_CORE_CLK_DPLL0_WUF   0
 
-#define CONF_CORE_CLK_DPLL0_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
 
-#define CONF_CORE_CLK_DPLL0_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
 
#define CONF_CORE_CLK_DPLL0_FILTER   0x0
 
-#define CONF_CORE_CLK_DPLL1_ENABLE   (0)
 
-#define CONF_CORE_CLK_DPLL1_ONDEMAND   (0)
 
-#define CONF_CORE_CLK_DPLL1_RUNSTDBY   (0)
 
-#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL   0
 
-#define CONF_CORE_CLK_DPLL1_LDR_VAL   (0)
 
-#define CONF_CORE_CLK_DPLL1_DIV_VAL   (0)
 
-#define CONF_CORE_CLK_DPLL1_DCOEN   0
 
-#define CONF_CORE_CLK_DPLL1_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
 
-#define CONF_CORE_CLK_DPLL1_LBYPASS   0
 
-#define CONF_CORE_CLK_DPLL1_LTIME   0
 
-#define CONF_CORE_CLK_DPLL1_WUF   0
 
-#define CONF_CORE_CLK_DPLL1_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
 
-#define CONF_CORE_CLK_DPLL1_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
 
#define CONF_CORE_CLK_DPLL1_FILTER   0x0
 
#define CONF_CORE_GCLK_0_ENABLE   1
 
#define CONF_CORE_GCLK_11_IDC   0
 
Core-Master-Clock-Configuration

Configuration options for the master clock.

+
#define CONF_CORE_MCLK_NVM_WAIT_STATE   0x5
 
#define CONF_CORE_MCLK_CPUDIV   0x1
 
Core-XOSC0-Configuration

Configuration options for XOSC0.

+
+#define CONF_CORE_CLK_XOSC0_ENABLE   (1)
 
+#define CONF_CORE_CLK_XOSC0_XTALEN   (1)
 
+#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)
 
+#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0)
 
+#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)
 
+#define CONF_CORE_CLK_XOSC0_ENALC   (1)
 
+#define CONF_CORE_CLK_XOSC0_CFDEN   (1)
 
+#define CONF_CORE_CLK_XOSC0_SWBEN   (0)
 
+#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
 
+#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000
 
Core-XOSC1-Configuration

Configuration options for XOSC1.

+
+#define CONF_CORE_CLK_XOSC1_ENABLE   (0)
 
+#define CONF_CORE_CLK_XOSC1_XTALEN   (0)
 
+#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)
 
+#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0)
 
+#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)
 
+#define CONF_CORE_CLK_XOSC1_ENALC   (0)
 
+#define CONF_CORE_CLK_XOSC1_CFDEN   (0)
 
+#define CONF_CORE_CLK_XOSC1_SWBEN   (0)
 
+#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
 
+#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000
 
Core-XOSC32K-Configuration

Configuration options for the external 32khz oscillator.

+
+#define CONF_CORE_CLK_XOSC32K_ENABLE   (1)
 
+#define CONF_CORE_CLK_XOSC32K_CGM   CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
 
+#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
 
+#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)
 
+#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)
 
+#define CONF_CORE_CLK_XOSC32K_EN1K   (0)
 
+#define CONF_CORE_CLK_XOSC32K_EN32K   (1)
 
+#define CONF_CORE_CLK_XOSC32K_XTALEN   (1)
 
+#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)
 
+#define CONF_CORE_CLK_XOSC32K_CFDEN   (0)
 
+#define CONF_CORE_CLK_XOSC32K_SWBACK   (0)
 
+#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)
 
Core-DFLL48M-Configuration

Configuration options for DFLL48M

#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL   0
 
Core-DPLL0-Configuration

Configuration Options for DPLL0.

+
+#define CONF_CORE_CLK_DPLL0_ENABLE   (1)
 
+#define CONF_CORE_CLK_DPLL0_ONDEMAND   (0)
 
+#define CONF_CORE_CLK_DPLL0_RUNSTDBY   (0)
 
+#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL   0
 
+#define CONF_CORE_CLK_DPLL0_LDR_VAL   (119)
 
+#define CONF_CORE_CLK_DPLL0_DIV_VAL   (5)
 
+#define CONF_CORE_CLK_DPLL0_DCOEN   0
 
+#define CONF_CORE_CLK_DPLL0_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
 
+#define CONF_CORE_CLK_DPLL0_LBYPASS   1
 
+#define CONF_CORE_CLK_DPLL0_LTIME   0
 
+#define CONF_CORE_CLK_DPLL0_WUF   0
 
+#define CONF_CORE_CLK_DPLL0_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
 
+#define CONF_CORE_CLK_DPLL0_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
 
#define CONF_CORE_CLK_DPLL0_FILTER   0x0
 
Core-DPLL1-Configuration

Configuration Options for DPLL1.

+
+#define CONF_CORE_CLK_DPLL1_ENABLE   (0)
 
+#define CONF_CORE_CLK_DPLL1_ONDEMAND   (0)
 
+#define CONF_CORE_CLK_DPLL1_RUNSTDBY   (0)
 
+#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL   0
 
+#define CONF_CORE_CLK_DPLL1_LDR_VAL   (0)
 
+#define CONF_CORE_CLK_DPLL1_DIV_VAL   (0)
 
+#define CONF_CORE_CLK_DPLL1_DCOEN   0
 
+#define CONF_CORE_CLK_DPLL1_DCOFILTER   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
 
+#define CONF_CORE_CLK_DPLL1_LBYPASS   0
 
+#define CONF_CORE_CLK_DPLL1_LTIME   0
 
+#define CONF_CORE_CLK_DPLL1_WUF   0
 
+#define CONF_CORE_CLK_DPLL1_GCLK_SRC   GCLK_GENCTRL_SRC_XOSC0
 
+#define CONF_CORE_CLK_DPLL1_REFCLK   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
 
#define CONF_CORE_CLK_DPLL1_FILTER   0x0
 

Detailed Description

Author
Penguin
@@ -648,7 +666,7 @@ Description pg. 724 of datasheet -

Definition at line 99 of file conf_core.h.

+

Definition at line 124 of file conf_core.h.

@@ -680,7 +698,7 @@ pg. 724 of datasheet
  • 11 => Generic clock generator 11
    • -

    Definition at line 154 of file conf_core.h.

    +

    Definition at line 178 of file conf_core.h.

    @@ -703,7 +721,7 @@ pg. 724 of datasheet pg. 724 of datasheet -

    Definition at line 107 of file conf_core.h.

    +

    Definition at line 132 of file conf_core.h.

    @@ -726,7 +744,7 @@ pg. 724 of datasheet pg. 724 of datasheet -

    Definition at line 115 of file conf_core.h.

    +

    Definition at line 140 of file conf_core.h.

    @@ -745,12 +763,11 @@ pg. 724 of datasheet

    This bit controls the DFLL output clock, depending on the lock status:

    DFLL48M Wait Lock Control

    -

    Definition at line 124 of file conf_core.h.

    +

    Definition at line 148 of file conf_core.h.

    @@ -768,7 +785,7 @@ pg. 725 of datasheet

    pg. 732 of the datasheet FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor 0x0 | 92.7 kHz | 0.76 0x1 | 131 kHz | 1.08 0x2 | 46.4 kHz | 0.38 0x3 | 65.6 kHz | 0.54 0x4 | 131 kHz | 0.56 0x5 | 185 kHz | 0.79 0x6 | 65.6 kHz | 0.28 0x7 | 92.7 kHz | 0.39 0x8 | 46.4 kHz | 1.49 0x9 | 65.6 kHz | 2.11 0xA | 23.2 kHz | 0.75 0xB | 32.8 kHz | 1.06 0xC | 65.6 kHz | 1.07 0xD | 92.7 kHz | 1.51 0xE | 32.8 kHz | 0.53 0xF | 46.4 kHz | 0.75

    When in doubt, leave this at its default.

    -

    Definition at line 194 of file conf_core.h.

    +

    Definition at line 222 of file conf_core.h.

    @@ -802,7 +819,7 @@ pg. 725 of datasheet
    0xF | 46.4 kHz | 0.75

    When in doubt, leave this at its default.

    -

    Definition at line 234 of file conf_core.h.

    +

    Definition at line 267 of file conf_core.h.

    @@ -822,7 +839,7 @@ pg. 725 of datasheet
  • 1 => Enabled
    • -

    Definition at line 45 of file conf_core.h.

    +

    Definition at line 52 of file conf_core.h.

    @@ -842,7 +859,7 @@ pg. 725 of datasheet
  • 1 => Enabled
    • -

    Definition at line 38 of file conf_core.h.

    +

    Definition at line 45 of file conf_core.h.

    @@ -868,7 +885,7 @@ pg. 725 of datasheet
  • 0x80 => Clock Divide by 128
    • -

    Definition at line 31 of file conf_core.h.

    +

    Definition at line 36 of file conf_core.h.

    @@ -885,7 +902,7 @@ pg. 725 of datasheet

    Define the number of wait states for the master clock. Can be [0-15].

    -

    Definition at line 18 of file conf_core.h.

    +

    Definition at line 23 of file conf_core.h.

    diff --git a/test/same54p20a_test/doc/html/conf__core_8h_source.html b/test/same54p20a_test/doc/html/conf__core_8h_source.html index 166fbbce..1681016a 100644 --- a/test/same54p20a_test/doc/html/conf__core_8h_source.html +++ b/test/same54p20a_test/doc/html/conf__core_8h_source.html @@ -74,225 +74,221 @@ $(function() {
    11 #define _CONF_CLOCKS_H_
    12 #include "clocks.h"
    13 
    -
    18 #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
    -
    19 
    -
    31 #define CONF_CORE_MCLK_CPUDIV 0x1
    -
    32 
    -
    38 #define CONF_CORE_DMA_ENABLE (0)
    -
    39 
    -
    45 #define CONF_CORE_CMCC_ENABLE (0)
    +
    23 #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
    +
    24 
    +
    36 #define CONF_CORE_MCLK_CPUDIV 0x1
    +
    37 
    +
    45 #define CONF_CORE_DMA_ENABLE (0)
    46 
    -
    47 #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
    -
    48 #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
    -
    49 #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
    -
    50 // XOSC0 Config
    -
    51 #define CONF_CORE_CLK_XOSC0_ENABLE (1)
    -
    52 #define CONF_CORE_CLK_XOSC0_XTALEN (1)
    -
    53 #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
    -
    54 #define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
    -
    55 #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
    -
    56 #define CONF_CORE_CLK_XOSC0_ENALC (1)
    -
    57 #define CONF_CORE_CLK_XOSC0_CFDEN (1)
    -
    58 #define CONF_CORE_CLK_XOSC0_SWBEN (0)
    -
    59 #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    -
    60 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
    -
    61 
    -
    62 // XOSC1 Config
    -
    63 #define CONF_CORE_CLK_XOSC1_ENABLE (0)
    -
    64 #define CONF_CORE_CLK_XOSC1_XTALEN (0)
    -
    65 #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
    -
    66 #define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
    -
    67 #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
    -
    68 #define CONF_CORE_CLK_XOSC1_ENALC (0)
    -
    69 #define CONF_CORE_CLK_XOSC1_CFDEN (0)
    -
    70 #define CONF_CORE_CLK_XOSC1_SWBEN (0)
    -
    71 #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    -
    72 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
    -
    73 
    -
    74 // XOSC32K Config
    -
    75 #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
    -
    76 #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
    -
    77 #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
    -
    78 #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
    -
    79 #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
    -
    80 #define CONF_CORE_CLK_XOSC32K_EN1K (0)
    -
    81 #define CONF_CORE_CLK_XOSC32K_EN32K (1)
    -
    82 #define CONF_CORE_CLK_XOSC32K_XTALEN (1)
    -
    83 #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
    -
    84 #define CONF_CORE_CLK_XOSC32K_CFDEN (0)
    -
    85 #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
    -
    86 #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
    -
    87 
    -
    99 #define CONF_CORE_CLK_DFLL_ENABLE (1)
    -
    100 
    -
    107 #define CONF_CORE_CLK_DFLL_ONDEMAND (0)
    -
    108 
    -
    115 #define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
    -
    116 
    -
    124 #define CONF_CORE_CLK_DFLL_WAITLOCK (0)
    -
    125 #define CONF_CORE_CLK_DFLL_BPLKC (0)
    -
    126 #define CONF_CORE_CLK_DFLL_QLDIS (0)
    -
    127 #define CONF_CORE_CLK_DFLL_CCDIS (1)
    -
    128 #define CONF_CORE_CLK_DFLL_USBCRM (1)
    -
    129 #define CONF_CORE_CLK_DFLL_LLAW (0)
    -
    130 #define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
    -
    131 #define CONF_CORE_CLK_DFLL_MODE 0x01
    -
    132 #define CONF_CORE_CLK_DFLL_DIFF_VAL 0
    -
    133 #define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
    -
    134 #define CONF_CORE_CLK_DFLL_FINE_VAL 128
    -
    135 #define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
    -
    136 #define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
    -
    137 #define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
    -
    138 
    -
    154 #define CONF_CORE_CLK_DFLL_GCLK_SRC 3
    -
    155 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
    -
    156 
    -
    158 // DPLL0 Config
    -
    159 #define CONF_CORE_CLK_DPLL0_ENABLE (1)
    -
    160 #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
    -
    161 #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
    -
    162 #define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
    -
    163 #define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
    -
    164 #define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
    -
    165 #define CONF_CORE_CLK_DPLL0_DCOEN 0
    -
    166 #define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    -
    167 #define CONF_CORE_CLK_DPLL0_LBYPASS 1
    -
    168 #define CONF_CORE_CLK_DPLL0_LTIME 0
    -
    169 #define CONF_CORE_CLK_DPLL0_WUF 0
    -
    170 #define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    -
    171 #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    -
    172 
    -
    194 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
    -
    195 
    -
    196 // DPLL1 Config
    -
    197 #define CONF_CORE_CLK_DPLL1_ENABLE (0)
    -
    198 #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
    -
    199 #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
    -
    200 #define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
    -
    201 #define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
    -
    202 #define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
    -
    203 #define CONF_CORE_CLK_DPLL1_DCOEN 0
    -
    204 #define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    -
    205 #define CONF_CORE_CLK_DPLL1_LBYPASS 0
    -
    206 #define CONF_CORE_CLK_DPLL1_LTIME 0
    -
    207 #define CONF_CORE_CLK_DPLL1_WUF 0
    -
    208 #define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    -
    209 #define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    -
    210 
    -
    234 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
    -
    235 
    -
    236 // GCLK Generators Config
    -
    237 #define CONF_CORE_GCLK_0_ENABLE 1
    -
    238 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
    -
    239 #define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    240 #define CONF_CORE_GCLK_0_DIV_VAL 1
    -
    241 #define CONF_CORE_GCLK_0_DIVSEL 0
    -
    242 #define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
    -
    243 #define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
    -
    244 #define CONF_CORE_GCLK_0_IDC 1
    -
    245 
    -
    246 #define CONF_CORE_GCLK_1_ENABLE 0
    -
    247 #define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
    -
    248 #define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    249 #define CONF_CORE_GCLK_1_DIV_VAL 1
    -
    250 #define CONF_CORE_GCLK_1_DIVSEL 0
    -
    251 #define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
    -
    252 #define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
    -
    253 #define CONF_CORE_GCLK_1_IDC 0
    -
    254 
    -
    255 #define CONF_CORE_GCLK_2_ENABLE 0
    -
    256 #define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
    -
    257 #define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    258 #define CONF_CORE_GCLK_2_DIV_VAL 1
    -
    259 #define CONF_CORE_GCLK_2_DIVSEL 0
    -
    260 #define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
    -
    261 #define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
    -
    262 #define CONF_CORE_GCLK_2_IDC 0
    -
    263 
    -
    264 #define CONF_CORE_GCLK_3_ENABLE 1
    -
    265 #define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
    -
    266 #define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
    -
    267 #define CONF_CORE_GCLK_3_DIV_VAL 1
    -
    268 #define CONF_CORE_GCLK_3_DIVSEL 0
    -
    269 #define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
    -
    270 #define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
    -
    271 #define CONF_CORE_GCLK_3_IDC 0
    -
    272 
    -
    273 #define CONF_CORE_GCLK_4_ENABLE 0
    -
    274 #define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
    -
    275 #define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    276 #define CONF_CORE_GCLK_4_DIV_VAL 1
    -
    277 #define CONF_CORE_GCLK_4_DIVSEL 1
    -
    278 #define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
    -
    279 #define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
    -
    280 #define CONF_CORE_GCLK_4_IDC 0
    -
    281 
    -
    282 #define CONF_CORE_GCLK_5_ENABLE 0
    -
    283 #define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
    -
    284 #define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    285 #define CONF_CORE_GCLK_5_DIV_VAL 1
    -
    286 #define CONF_CORE_GCLK_5_DIVSEL 0
    -
    287 #define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
    -
    288 #define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
    -
    289 #define CONF_CORE_GCLK_5_IDC 0
    -
    290 
    -
    291 #define CONF_CORE_GCLK_6_ENABLE 0
    -
    292 #define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
    -
    293 #define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    294 #define CONF_CORE_GCLK_6_DIV_VAL 1
    -
    295 #define CONF_CORE_GCLK_6_DIVSEL 0
    -
    296 #define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
    -
    297 #define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
    -
    298 #define CONF_CORE_GCLK_6_IDC 0
    -
    299 
    -
    300 #define CONF_CORE_GCLK_7_ENABLE 0
    -
    301 #define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
    -
    302 #define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    303 #define CONF_CORE_GCLK_7_DIV_VAL 1
    -
    304 #define CONF_CORE_GCLK_7_DIVSEL 0
    -
    305 #define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
    -
    306 #define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
    -
    307 #define CONF_CORE_GCLK_7_IDC 0
    -
    308 
    -
    309 #define CONF_CORE_GCLK_8_ENABLE 0
    -
    310 #define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
    -
    311 #define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    312 #define CONF_CORE_GCLK_8_DIV_VAL 1
    -
    313 #define CONF_CORE_GCLK_8_DIVSEL 0
    -
    314 #define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
    -
    315 #define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
    -
    316 #define CONF_CORE_GCLK_8_IDC 0
    -
    317 
    -
    318 #define CONF_CORE_GCLK_9_ENABLE 0
    -
    319 #define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
    -
    320 #define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    321 #define CONF_CORE_GCLK_9_DIV_VAL 1
    -
    322 #define CONF_CORE_GCLK_9_DIVSEL 0
    -
    323 #define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
    -
    324 #define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
    -
    325 #define CONF_CORE_GCLK_9_IDC 0
    -
    326 
    -
    327 #define CONF_CORE_GCLK_10_ENABLE 0
    -
    328 #define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
    -
    329 #define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    330 #define CONF_CORE_GCLK_10_DIV_VAL 1
    -
    331 #define CONF_CORE_GCLK_10_DIVSEL 0
    -
    332 #define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
    -
    333 #define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
    -
    334 #define CONF_CORE_GCLK_10_IDC 0
    -
    335 
    -
    336 #define CONF_CORE_GCLK_11_ENABLE 0
    -
    337 #define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
    -
    338 #define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    339 #define CONF_CORE_GCLK_11_DIV_VAL 1
    -
    340 #define CONF_CORE_GCLK_11_DIVSEL 0
    -
    341 #define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
    -
    342 #define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
    -
    343 #define CONF_CORE_GCLK_11_IDC 0
    -
    344 
    -
    345 
    -
    346 
    -
    347 #endif
    +
    52 #define CONF_CORE_CMCC_ENABLE (0)
    +
    53 
    +
    54 #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
    +
    55 #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
    +
    56 #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
    +
    57 
    +
    62 #define CONF_CORE_CLK_XOSC0_ENABLE (1)
    +
    63 #define CONF_CORE_CLK_XOSC0_XTALEN (1)
    +
    64 #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
    +
    65 #define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
    +
    66 #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
    +
    67 #define CONF_CORE_CLK_XOSC0_ENALC (1)
    +
    68 #define CONF_CORE_CLK_XOSC0_CFDEN (1)
    +
    69 #define CONF_CORE_CLK_XOSC0_SWBEN (0)
    +
    70 #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    +
    71 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
    +
    72 
    +
    80 #define CONF_CORE_CLK_XOSC1_ENABLE (0)
    +
    81 #define CONF_CORE_CLK_XOSC1_XTALEN (0)
    +
    82 #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
    +
    83 #define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
    +
    84 #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
    +
    85 #define CONF_CORE_CLK_XOSC1_ENALC (0)
    +
    86 #define CONF_CORE_CLK_XOSC1_CFDEN (0)
    +
    87 #define CONF_CORE_CLK_XOSC1_SWBEN (0)
    +
    88 #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    +
    89 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
    +
    90 
    +
    98 #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
    +
    99 #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
    +
    100 #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
    +
    101 #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
    +
    102 #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
    +
    103 #define CONF_CORE_CLK_XOSC32K_EN1K (0)
    +
    104 #define CONF_CORE_CLK_XOSC32K_EN32K (1)
    +
    105 #define CONF_CORE_CLK_XOSC32K_XTALEN (1)
    +
    106 #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
    +
    107 #define CONF_CORE_CLK_XOSC32K_CFDEN (0)
    +
    108 #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
    +
    109 #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
    +
    110 
    +
    124 #define CONF_CORE_CLK_DFLL_ENABLE (1)
    +
    125 
    +
    132 #define CONF_CORE_CLK_DFLL_ONDEMAND (0)
    +
    133 
    +
    140 #define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
    +
    141 
    +
    148 #define CONF_CORE_CLK_DFLL_WAITLOCK (0)
    +
    149 #define CONF_CORE_CLK_DFLL_BPLKC (0)
    +
    150 #define CONF_CORE_CLK_DFLL_QLDIS (0)
    +
    151 #define CONF_CORE_CLK_DFLL_CCDIS (1)
    +
    152 #define CONF_CORE_CLK_DFLL_USBCRM (1)
    +
    153 #define CONF_CORE_CLK_DFLL_LLAW (0)
    +
    154 #define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
    +
    155 #define CONF_CORE_CLK_DFLL_MODE 0x01
    +
    156 #define CONF_CORE_CLK_DFLL_DIFF_VAL 0
    +
    157 #define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
    +
    158 #define CONF_CORE_CLK_DFLL_FINE_VAL 128
    +
    159 #define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
    +
    160 #define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
    +
    161 #define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
    +
    162 
    +
    178 #define CONF_CORE_CLK_DFLL_GCLK_SRC 3
    +
    179 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
    +
    180 
    +
    187 #define CONF_CORE_CLK_DPLL0_ENABLE (1)
    +
    188 #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
    +
    189 #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
    +
    190 #define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
    +
    191 #define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
    +
    192 #define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
    +
    193 #define CONF_CORE_CLK_DPLL0_DCOEN 0
    +
    194 #define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    +
    195 #define CONF_CORE_CLK_DPLL0_LBYPASS 1
    +
    196 #define CONF_CORE_CLK_DPLL0_LTIME 0
    +
    197 #define CONF_CORE_CLK_DPLL0_WUF 0
    +
    198 #define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    +
    199 #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    +
    200 
    +
    222 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
    +
    223 
    +
    230 #define CONF_CORE_CLK_DPLL1_ENABLE (0)
    +
    231 #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
    +
    232 #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
    +
    233 #define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
    +
    234 #define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
    +
    235 #define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
    +
    236 #define CONF_CORE_CLK_DPLL1_DCOEN 0
    +
    237 #define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    +
    238 #define CONF_CORE_CLK_DPLL1_LBYPASS 0
    +
    239 #define CONF_CORE_CLK_DPLL1_LTIME 0
    +
    240 #define CONF_CORE_CLK_DPLL1_WUF 0
    +
    241 #define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    +
    242 #define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    +
    243 
    +
    267 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
    +
    268 
    +
    271 // GCLK Generators Config
    +
    272 #define CONF_CORE_GCLK_0_ENABLE 1
    +
    273 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
    +
    274 #define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    275 #define CONF_CORE_GCLK_0_DIV_VAL 1
    +
    276 #define CONF_CORE_GCLK_0_DIVSEL 0
    +
    277 #define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
    +
    278 #define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
    +
    279 #define CONF_CORE_GCLK_0_IDC 1
    +
    280 
    +
    281 #define CONF_CORE_GCLK_1_ENABLE 0
    +
    282 #define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
    +
    283 #define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    284 #define CONF_CORE_GCLK_1_DIV_VAL 1
    +
    285 #define CONF_CORE_GCLK_1_DIVSEL 0
    +
    286 #define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
    +
    287 #define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
    +
    288 #define CONF_CORE_GCLK_1_IDC 0
    +
    289 
    +
    290 #define CONF_CORE_GCLK_2_ENABLE 0
    +
    291 #define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
    +
    292 #define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    293 #define CONF_CORE_GCLK_2_DIV_VAL 1
    +
    294 #define CONF_CORE_GCLK_2_DIVSEL 0
    +
    295 #define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
    +
    296 #define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
    +
    297 #define CONF_CORE_GCLK_2_IDC 0
    +
    298 
    +
    299 #define CONF_CORE_GCLK_3_ENABLE 1
    +
    300 #define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
    +
    301 #define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
    +
    302 #define CONF_CORE_GCLK_3_DIV_VAL 1
    +
    303 #define CONF_CORE_GCLK_3_DIVSEL 0
    +
    304 #define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
    +
    305 #define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
    +
    306 #define CONF_CORE_GCLK_3_IDC 0
    +
    307 
    +
    308 #define CONF_CORE_GCLK_4_ENABLE 0
    +
    309 #define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
    +
    310 #define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    311 #define CONF_CORE_GCLK_4_DIV_VAL 1
    +
    312 #define CONF_CORE_GCLK_4_DIVSEL 1
    +
    313 #define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
    +
    314 #define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
    +
    315 #define CONF_CORE_GCLK_4_IDC 0
    +
    316 
    +
    317 #define CONF_CORE_GCLK_5_ENABLE 0
    +
    318 #define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
    +
    319 #define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    320 #define CONF_CORE_GCLK_5_DIV_VAL 1
    +
    321 #define CONF_CORE_GCLK_5_DIVSEL 0
    +
    322 #define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
    +
    323 #define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
    +
    324 #define CONF_CORE_GCLK_5_IDC 0
    +
    325 
    +
    326 #define CONF_CORE_GCLK_6_ENABLE 0
    +
    327 #define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
    +
    328 #define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    329 #define CONF_CORE_GCLK_6_DIV_VAL 1
    +
    330 #define CONF_CORE_GCLK_6_DIVSEL 0
    +
    331 #define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
    +
    332 #define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
    +
    333 #define CONF_CORE_GCLK_6_IDC 0
    +
    334 
    +
    335 #define CONF_CORE_GCLK_7_ENABLE 0
    +
    336 #define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
    +
    337 #define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    338 #define CONF_CORE_GCLK_7_DIV_VAL 1
    +
    339 #define CONF_CORE_GCLK_7_DIVSEL 0
    +
    340 #define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
    +
    341 #define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
    +
    342 #define CONF_CORE_GCLK_7_IDC 0
    +
    343 
    +
    344 #define CONF_CORE_GCLK_8_ENABLE 0
    +
    345 #define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
    +
    346 #define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    347 #define CONF_CORE_GCLK_8_DIV_VAL 1
    +
    348 #define CONF_CORE_GCLK_8_DIVSEL 0
    +
    349 #define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
    +
    350 #define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
    +
    351 #define CONF_CORE_GCLK_8_IDC 0
    +
    352 
    +
    353 #define CONF_CORE_GCLK_9_ENABLE 0
    +
    354 #define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
    +
    355 #define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    356 #define CONF_CORE_GCLK_9_DIV_VAL 1
    +
    357 #define CONF_CORE_GCLK_9_DIVSEL 0
    +
    358 #define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
    +
    359 #define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
    +
    360 #define CONF_CORE_GCLK_9_IDC 0
    +
    361 
    +
    362 #define CONF_CORE_GCLK_10_ENABLE 0
    +
    363 #define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
    +
    364 #define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    365 #define CONF_CORE_GCLK_10_DIV_VAL 1
    +
    366 #define CONF_CORE_GCLK_10_DIVSEL 0
    +
    367 #define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
    +
    368 #define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
    +
    369 #define CONF_CORE_GCLK_10_IDC 0
    +
    370 
    +
    371 #define CONF_CORE_GCLK_11_ENABLE 0
    +
    372 #define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
    +
    373 #define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    374 #define CONF_CORE_GCLK_11_DIV_VAL 1
    +
    375 #define CONF_CORE_GCLK_11_DIVSEL 0
    +
    376 #define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
    +
    377 #define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
    +
    378 #define CONF_CORE_GCLK_11_IDC 0
    +
    379 
    +
    380 
    +
    381 
    +
    382 #endif
    diff --git a/test/same54p20a_test/doc/html/memory_8c_source.html b/test/same54p20a_test/doc/html/memory_8c_source.html index f888290d..e664ac86 100644 --- a/test/same54p20a_test/doc/html/memory_8c_source.html +++ b/test/same54p20a_test/doc/html/memory_8c_source.html @@ -96,7 +96,7 @@ $(function() {
    25 }
    26 
    -
    CONF_CORE_MCLK_NVM_WAIT_STATE
    #define CONF_CORE_MCLK_NVM_WAIT_STATE
    Definition: conf_core.h:18
    +
    CONF_CORE_MCLK_NVM_WAIT_STATE
    #define CONF_CORE_MCLK_NVM_WAIT_STATE
    Definition: conf_core.h:23
    NVMCTRL
    #define NVMCTRL
    (NVMCTRL) APB Base Address
    Definition: same54n19a.h:918
    MCLK
    #define MCLK
    (MCLK) APB Base Address
    Definition: same54n19a.h:914
    conf_core.h