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adding mcu headers for atmel chips

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stable
penguin 4 years ago
parent 7113c7f56f
commit 07ade28ba2
552 changed files with 106689 additions and 13 deletions
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1
arch/.#make-manifest.toml
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penguin@penguin-arch-home.68690:1602942911

163
arch/arm/SAMD51/SAMD51A/ld/samd51g18a_flash.ld
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51G18A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51g18a_sram.ld
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/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51G18A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51g19a_flash.ld
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51G19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51g19a_sram.ld
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/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51G19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51j18a_flash.ld
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@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51J18A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51j18a_sram.ld
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@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51J18A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x8000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51j19a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51J19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
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. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51j19a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51J19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51j20a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51J20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51j20a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51J20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51n19a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51n19a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51n20a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51n20a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51p19a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51P19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51p19a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51P19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAMD51/SAMD51A/ld/samd51p20a_flash.ld
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAMD51P20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAMD51/SAMD51A/ld/samd51p20a_sram.ld
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/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAMD51P20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

64
arch/arm/SAMD51/SAMD51A/mcu/inc/component-version.h
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/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 3
#define COMPONENT_VERSION_MINOR 3
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version.
//
#define COMPONENT_VERSION 30003
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 76
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "3.3"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2020-10-09 15:30:02"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */

410
arch/arm/SAMD51/SAMD51A/mcu/inc/component/ac.h
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/**
* \brief Component description for AC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_AC_COMPONENT_H_
#define _SAMD51_AC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR AC */
/* ************************************************************************** */
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#define AC_CTRLA_RESETVALUE _U_(0x00) /**< (AC_CTRLA) Control A Reset Value */
#define AC_CTRLA_SWRST_Pos _U_(0) /**< (AC_CTRLA) Software Reset Position */
#define AC_CTRLA_SWRST_Msk (_U_(0x1) << AC_CTRLA_SWRST_Pos) /**< (AC_CTRLA) Software Reset Mask */
#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & ((value) << AC_CTRLA_SWRST_Pos))
#define AC_CTRLA_ENABLE_Pos _U_(1) /**< (AC_CTRLA) Enable Position */
#define AC_CTRLA_ENABLE_Msk (_U_(0x1) << AC_CTRLA_ENABLE_Pos) /**< (AC_CTRLA) Enable Mask */
#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & ((value) << AC_CTRLA_ENABLE_Pos))
#define AC_CTRLA_Msk _U_(0x03) /**< (AC_CTRLA) Register Mask */
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#define AC_CTRLB_RESETVALUE _U_(0x00) /**< (AC_CTRLB) Control B Reset Value */
#define AC_CTRLB_START0_Pos _U_(0) /**< (AC_CTRLB) Comparator 0 Start Comparison Position */
#define AC_CTRLB_START0_Msk (_U_(0x1) << AC_CTRLB_START0_Pos) /**< (AC_CTRLB) Comparator 0 Start Comparison Mask */
#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & ((value) << AC_CTRLB_START0_Pos))
#define AC_CTRLB_START1_Pos _U_(1) /**< (AC_CTRLB) Comparator 1 Start Comparison Position */
#define AC_CTRLB_START1_Msk (_U_(0x1) << AC_CTRLB_START1_Pos) /**< (AC_CTRLB) Comparator 1 Start Comparison Mask */
#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & ((value) << AC_CTRLB_START1_Pos))
#define AC_CTRLB_Msk _U_(0x03) /**< (AC_CTRLB) Register Mask */
#define AC_CTRLB_START_Pos _U_(0) /**< (AC_CTRLB Position) Comparator x Start Comparison */
#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) /**< (AC_CTRLB Mask) START */
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#define AC_EVCTRL_RESETVALUE _U_(0x00) /**< (AC_EVCTRL) Event Control Reset Value */
#define AC_EVCTRL_COMPEO0_Pos _U_(0) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Position */
#define AC_EVCTRL_COMPEO0_Msk (_U_(0x1) << AC_EVCTRL_COMPEO0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Mask */
#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & ((value) << AC_EVCTRL_COMPEO0_Pos))
#define AC_EVCTRL_COMPEO1_Pos _U_(1) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Position */
#define AC_EVCTRL_COMPEO1_Msk (_U_(0x1) << AC_EVCTRL_COMPEO1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Mask */
#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & ((value) << AC_EVCTRL_COMPEO1_Pos))
#define AC_EVCTRL_WINEO0_Pos _U_(4) /**< (AC_EVCTRL) Window 0 Event Output Enable Position */
#define AC_EVCTRL_WINEO0_Msk (_U_(0x1) << AC_EVCTRL_WINEO0_Pos) /**< (AC_EVCTRL) Window 0 Event Output Enable Mask */
#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & ((value) << AC_EVCTRL_WINEO0_Pos))
#define AC_EVCTRL_COMPEI0_Pos _U_(8) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Position */
#define AC_EVCTRL_COMPEI0_Msk (_U_(0x1) << AC_EVCTRL_COMPEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Mask */
#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & ((value) << AC_EVCTRL_COMPEI0_Pos))
#define AC_EVCTRL_COMPEI1_Pos _U_(9) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Position */
#define AC_EVCTRL_COMPEI1_Msk (_U_(0x1) << AC_EVCTRL_COMPEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Mask */
#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & ((value) << AC_EVCTRL_COMPEI1_Pos))
#define AC_EVCTRL_INVEI0_Pos _U_(12) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */
#define AC_EVCTRL_INVEI0_Msk (_U_(0x1) << AC_EVCTRL_INVEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */
#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & ((value) << AC_EVCTRL_INVEI0_Pos))
#define AC_EVCTRL_INVEI1_Pos _U_(13) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */
#define AC_EVCTRL_INVEI1_Msk (_U_(0x1) << AC_EVCTRL_INVEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */
#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & ((value) << AC_EVCTRL_INVEI1_Pos))
#define AC_EVCTRL_Msk _U_(0x3313) /**< (AC_EVCTRL) Register Mask */
#define AC_EVCTRL_COMPEO_Pos _U_(0) /**< (AC_EVCTRL Position) Comparator x Event Output Enable */
#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) /**< (AC_EVCTRL Mask) COMPEO */
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
#define AC_EVCTRL_WINEO_Pos _U_(4) /**< (AC_EVCTRL Position) Window x Event Output Enable */
#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) /**< (AC_EVCTRL Mask) WINEO */
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
#define AC_EVCTRL_COMPEI_Pos _U_(8) /**< (AC_EVCTRL Position) Comparator x Event Input Enable */
#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) /**< (AC_EVCTRL Mask) COMPEI */
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
#define AC_EVCTRL_INVEI_Pos _U_(12) /**< (AC_EVCTRL Position) Comparator x Input Event Invert Enable */
#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) /**< (AC_EVCTRL Mask) INVEI */
#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< (AC_INTENCLR) Interrupt Enable Clear Reset Value */
#define AC_INTENCLR_COMP0_Pos _U_(0) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Position */
#define AC_INTENCLR_COMP0_Msk (_U_(0x1) << AC_INTENCLR_COMP0_Pos) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */
#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & ((value) << AC_INTENCLR_COMP0_Pos))
#define AC_INTENCLR_COMP1_Pos _U_(1) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Position */
#define AC_INTENCLR_COMP1_Msk (_U_(0x1) << AC_INTENCLR_COMP1_Pos) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */
#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & ((value) << AC_INTENCLR_COMP1_Pos))
#define AC_INTENCLR_WIN0_Pos _U_(4) /**< (AC_INTENCLR) Window 0 Interrupt Enable Position */
#define AC_INTENCLR_WIN0_Msk (_U_(0x1) << AC_INTENCLR_WIN0_Pos) /**< (AC_INTENCLR) Window 0 Interrupt Enable Mask */
#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & ((value) << AC_INTENCLR_WIN0_Pos))
#define AC_INTENCLR_Msk _U_(0x13) /**< (AC_INTENCLR) Register Mask */
#define AC_INTENCLR_COMP_Pos _U_(0) /**< (AC_INTENCLR Position) Comparator x Interrupt Enable */
#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) /**< (AC_INTENCLR Mask) COMP */
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
#define AC_INTENCLR_WIN_Pos _U_(4) /**< (AC_INTENCLR Position) Window x Interrupt Enable */
#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) /**< (AC_INTENCLR Mask) WIN */
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#define AC_INTENSET_RESETVALUE _U_(0x00) /**< (AC_INTENSET) Interrupt Enable Set Reset Value */
#define AC_INTENSET_COMP0_Pos _U_(0) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Position */
#define AC_INTENSET_COMP0_Msk (_U_(0x1) << AC_INTENSET_COMP0_Pos) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Mask */
#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & ((value) << AC_INTENSET_COMP0_Pos))
#define AC_INTENSET_COMP1_Pos _U_(1) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Position */
#define AC_INTENSET_COMP1_Msk (_U_(0x1) << AC_INTENSET_COMP1_Pos) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Mask */
#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & ((value) << AC_INTENSET_COMP1_Pos))
#define AC_INTENSET_WIN0_Pos _U_(4) /**< (AC_INTENSET) Window 0 Interrupt Enable Position */
#define AC_INTENSET_WIN0_Msk (_U_(0x1) << AC_INTENSET_WIN0_Pos) /**< (AC_INTENSET) Window 0 Interrupt Enable Mask */
#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & ((value) << AC_INTENSET_WIN0_Pos))
#define AC_INTENSET_Msk _U_(0x13) /**< (AC_INTENSET) Register Mask */
#define AC_INTENSET_COMP_Pos _U_(0) /**< (AC_INTENSET Position) Comparator x Interrupt Enable */
#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) /**< (AC_INTENSET Mask) COMP */
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
#define AC_INTENSET_WIN_Pos _U_(4) /**< (AC_INTENSET Position) Window x Interrupt Enable */
#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) /**< (AC_INTENSET Mask) WIN */
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define AC_INTFLAG_COMP0_Pos _U_(0) /**< (AC_INTFLAG) Comparator 0 Position */
#define AC_INTFLAG_COMP0_Msk (_U_(0x1) << AC_INTFLAG_COMP0_Pos) /**< (AC_INTFLAG) Comparator 0 Mask */
#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & ((value) << AC_INTFLAG_COMP0_Pos))
#define AC_INTFLAG_COMP1_Pos _U_(1) /**< (AC_INTFLAG) Comparator 1 Position */
#define AC_INTFLAG_COMP1_Msk (_U_(0x1) << AC_INTFLAG_COMP1_Pos) /**< (AC_INTFLAG) Comparator 1 Mask */
#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & ((value) << AC_INTFLAG_COMP1_Pos))
#define AC_INTFLAG_WIN0_Pos _U_(4) /**< (AC_INTFLAG) Window 0 Position */
#define AC_INTFLAG_WIN0_Msk (_U_(0x1) << AC_INTFLAG_WIN0_Pos) /**< (AC_INTFLAG) Window 0 Mask */
#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & ((value) << AC_INTFLAG_WIN0_Pos))
#define AC_INTFLAG_Msk _U_(0x13) /**< (AC_INTFLAG) Register Mask */
#define AC_INTFLAG_COMP_Pos _U_(0) /**< (AC_INTFLAG Position) Comparator x */
#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) /**< (AC_INTFLAG Mask) COMP */
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
#define AC_INTFLAG_WIN_Pos _U_(4) /**< (AC_INTFLAG Position) Window x */
#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) /**< (AC_INTFLAG Mask) WIN */
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */
#define AC_STATUSA_RESETVALUE _U_(0x00) /**< (AC_STATUSA) Status A Reset Value */
#define AC_STATUSA_STATE0_Pos _U_(0) /**< (AC_STATUSA) Comparator 0 Current State Position */
#define AC_STATUSA_STATE0_Msk (_U_(0x1) << AC_STATUSA_STATE0_Pos) /**< (AC_STATUSA) Comparator 0 Current State Mask */
#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & ((value) << AC_STATUSA_STATE0_Pos))
#define AC_STATUSA_STATE1_Pos _U_(1) /**< (AC_STATUSA) Comparator 1 Current State Position */
#define AC_STATUSA_STATE1_Msk (_U_(0x1) << AC_STATUSA_STATE1_Pos) /**< (AC_STATUSA) Comparator 1 Current State Mask */
#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & ((value) << AC_STATUSA_STATE1_Pos))
#define AC_STATUSA_WSTATE0_Pos _U_(4) /**< (AC_STATUSA) Window 0 Current State Position */
#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Window 0 Current State Mask */
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< (AC_STATUSA) Signal is above window */
#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< (AC_STATUSA) Signal is inside window */
#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< (AC_STATUSA) Signal is below window */
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is above window Position */
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is inside window Position */
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is below window Position */
#define AC_STATUSA_Msk _U_(0x33) /**< (AC_STATUSA) Register Mask */
#define AC_STATUSA_STATE_Pos _U_(0) /**< (AC_STATUSA Position) Comparator x Current State */
#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) /**< (AC_STATUSA Mask) STATE */
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */
#define AC_STATUSB_RESETVALUE _U_(0x00) /**< (AC_STATUSB) Status B Reset Value */
#define AC_STATUSB_READY0_Pos _U_(0) /**< (AC_STATUSB) Comparator 0 Ready Position */
#define AC_STATUSB_READY0_Msk (_U_(0x1) << AC_STATUSB_READY0_Pos) /**< (AC_STATUSB) Comparator 0 Ready Mask */
#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & ((value) << AC_STATUSB_READY0_Pos))
#define AC_STATUSB_READY1_Pos _U_(1) /**< (AC_STATUSB) Comparator 1 Ready Position */
#define AC_STATUSB_READY1_Msk (_U_(0x1) << AC_STATUSB_READY1_Pos) /**< (AC_STATUSB) Comparator 1 Ready Mask */
#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & ((value) << AC_STATUSB_READY1_Pos))
#define AC_STATUSB_Msk _U_(0x03) /**< (AC_STATUSB) Register Mask */
#define AC_STATUSB_READY_Pos _U_(0) /**< (AC_STATUSB Position) Comparator x Ready */
#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) /**< (AC_STATUSB Mask) READY */
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< (AC_DBGCTRL) Debug Control Reset Value */
#define AC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AC_DBGCTRL) Debug Run Position */
#define AC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /**< (AC_DBGCTRL) Debug Run Mask */
#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & ((value) << AC_DBGCTRL_DBGRUN_Pos))
#define AC_DBGCTRL_Msk _U_(0x01) /**< (AC_DBGCTRL) Register Mask */
/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< (AC_WINCTRL) Window Control Reset Value */
#define AC_WINCTRL_WEN0_Pos _U_(0) /**< (AC_WINCTRL) Window 0 Mode Enable Position */
#define AC_WINCTRL_WEN0_Msk (_U_(0x1) << AC_WINCTRL_WEN0_Pos) /**< (AC_WINCTRL) Window 0 Mode Enable Mask */
#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & ((value) << AC_WINCTRL_WEN0_Pos))
#define AC_WINCTRL_WINTSEL0_Pos _U_(1) /**< (AC_WINCTRL) Window 0 Interrupt Selection Position */
#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Window 0 Interrupt Selection Mask */
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< (AC_WINCTRL) Interrupt on signal above window */
#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< (AC_WINCTRL) Interrupt on signal inside window */
#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< (AC_WINCTRL) Interrupt on signal below window */
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< (AC_WINCTRL) Interrupt on signal outside window */
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal above window Position */
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal inside window Position */
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal below window Position */
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal outside window Position */
#define AC_WINCTRL_Msk _U_(0x07) /**< (AC_WINCTRL) Register Mask */
#define AC_WINCTRL_WEN_Pos _U_(0) /**< (AC_WINCTRL Position) Window x Mode Enable */
#define AC_WINCTRL_WEN_Msk (_U_(0x1) << AC_WINCTRL_WEN_Pos) /**< (AC_WINCTRL Mask) WEN */
#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & ((value) << AC_WINCTRL_WEN_Pos))
/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
#define AC_SCALER_RESETVALUE _U_(0x00) /**< (AC_SCALER) Scaler n Reset Value */
#define AC_SCALER_VALUE_Pos _U_(0) /**< (AC_SCALER) Scaler Value Position */
#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) /**< (AC_SCALER) Scaler Value Mask */
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
#define AC_SCALER_Msk _U_(0x3F) /**< (AC_SCALER) Register Mask */
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#define AC_COMPCTRL_RESETVALUE _U_(0x00) /**< (AC_COMPCTRL) Comparator Control n Reset Value */
#define AC_COMPCTRL_ENABLE_Pos _U_(1) /**< (AC_COMPCTRL) Enable Position */
#define AC_COMPCTRL_ENABLE_Msk (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) /**< (AC_COMPCTRL) Enable Mask */
#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & ((value) << AC_COMPCTRL_ENABLE_Pos))
#define AC_COMPCTRL_SINGLE_Pos _U_(2) /**< (AC_COMPCTRL) Single-Shot Mode Position */
#define AC_COMPCTRL_SINGLE_Msk (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) /**< (AC_COMPCTRL) Single-Shot Mode Mask */
#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & ((value) << AC_COMPCTRL_SINGLE_Pos))
#define AC_COMPCTRL_INTSEL_Pos _U_(3) /**< (AC_COMPCTRL) Interrupt Selection Position */
#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt Selection Mask */
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< (AC_COMPCTRL) Interrupt on comparator output toggle */
#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< (AC_COMPCTRL) Interrupt on comparator output rising */
#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< (AC_COMPCTRL) Interrupt on comparator output falling */
#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output toggle Position */
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output rising Position */
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output falling Position */
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */
#define AC_COMPCTRL_RUNSTDBY_Pos _U_(6) /**< (AC_COMPCTRL) Run in Standby Position */
#define AC_COMPCTRL_RUNSTDBY_Msk (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /**< (AC_COMPCTRL) Run in Standby Mask */
#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & ((value) << AC_COMPCTRL_RUNSTDBY_Pos))
#define AC_COMPCTRL_MUXNEG_Pos _U_(8) /**< (AC_COMPCTRL) Negative Input Mux Selection Position */
#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Negative Input Mux Selection Mask */
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< (AC_COMPCTRL) Ground */
#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< (AC_COMPCTRL) VDD scaler */
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< (AC_COMPCTRL) Internal bandgap voltage */
#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< (AC_COMPCTRL) DAC output */
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Ground Position */
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) VDD scaler Position */
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Internal bandgap voltage Position */
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) DAC output Position */
#define AC_COMPCTRL_MUXPOS_Pos _U_(12) /**< (AC_COMPCTRL) Positive Input Mux Selection Position */
#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) Positive Input Mux Selection Mask */
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< (AC_COMPCTRL) VDD Scaler */
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */
#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) VDD Scaler Position */
#define AC_COMPCTRL_SWAP_Pos _U_(15) /**< (AC_COMPCTRL) Swap Inputs and Invert Position */
#define AC_COMPCTRL_SWAP_Msk (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) /**< (AC_COMPCTRL) Swap Inputs and Invert Mask */
#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & ((value) << AC_COMPCTRL_SWAP_Pos))
#define AC_COMPCTRL_SPEED_Pos _U_(16) /**< (AC_COMPCTRL) Speed Selection Position */
#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) Speed Selection Mask */
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< (AC_COMPCTRL) High speed */
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) High speed Position */
#define AC_COMPCTRL_HYSTEN_Pos _U_(19) /**< (AC_COMPCTRL) Hysteresis Enable Position */
#define AC_COMPCTRL_HYSTEN_Msk (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /**< (AC_COMPCTRL) Hysteresis Enable Mask */
#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & ((value) << AC_COMPCTRL_HYSTEN_Pos))
#define AC_COMPCTRL_HYST_Pos _U_(20) /**< (AC_COMPCTRL) Hysteresis Level Position */
#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) Hysteresis Level Mask */
#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos))
#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< (AC_COMPCTRL) 50mV */
#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< (AC_COMPCTRL) 100mV */
#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< (AC_COMPCTRL) 150mV */
#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 50mV Position */
#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 100mV Position */
#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 150mV Position */
#define AC_COMPCTRL_FLEN_Pos _U_(24) /**< (AC_COMPCTRL) Filter Length Position */
#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) Filter Length Mask */
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) No filtering */
#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) */
#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) */
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) No filtering Position */
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */
#define AC_COMPCTRL_OUT_Pos _U_(28) /**< (AC_COMPCTRL) Output Position */
#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) Output Mask */
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */
#define AC_COMPCTRL_Msk _U_(0x373BF75E) /**< (AC_COMPCTRL) Register Mask */
/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */
#define AC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (AC_SYNCBUSY) Synchronization Busy Reset Value */
#define AC_SYNCBUSY_SWRST_Pos _U_(0) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Position */
#define AC_SYNCBUSY_SWRST_Msk (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */
#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & ((value) << AC_SYNCBUSY_SWRST_Pos))
#define AC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (AC_SYNCBUSY) Enable Synchronization Busy Position */
#define AC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /**< (AC_SYNCBUSY) Enable Synchronization Busy Mask */
#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & ((value) << AC_SYNCBUSY_ENABLE_Pos))
#define AC_SYNCBUSY_WINCTRL_Pos _U_(2) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */
#define AC_SYNCBUSY_WINCTRL_Msk (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */
#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & ((value) << AC_SYNCBUSY_WINCTRL_Pos))
#define AC_SYNCBUSY_COMPCTRL0_Pos _U_(3) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */
#define AC_SYNCBUSY_COMPCTRL0_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */
#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & ((value) << AC_SYNCBUSY_COMPCTRL0_Pos))
#define AC_SYNCBUSY_COMPCTRL1_Pos _U_(4) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */
#define AC_SYNCBUSY_COMPCTRL1_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */
#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & ((value) << AC_SYNCBUSY_COMPCTRL1_Pos))
#define AC_SYNCBUSY_Msk _U_(0x0000001F) /**< (AC_SYNCBUSY) Register Mask */
#define AC_SYNCBUSY_COMPCTRL_Pos _U_(3) /**< (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /**< (AC_SYNCBUSY Mask) COMPCTRL */
#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */
#define AC_CALIB_RESETVALUE _U_(0x101) /**< (AC_CALIB) Calibration Reset Value */
#define AC_CALIB_BIAS0_Pos _U_(0) /**< (AC_CALIB) COMP0/1 Bias Scaling Position */
#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) /**< (AC_CALIB) COMP0/1 Bias Scaling Mask */
#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos))
#define AC_CALIB_Msk _U_(0x0003) /**< (AC_CALIB) Register Mask */
/** \brief AC register offsets definitions */
#define AC_CTRLA_REG_OFST (0x00) /**< (AC_CTRLA) Control A Offset */
#define AC_CTRLB_REG_OFST (0x01) /**< (AC_CTRLB) Control B Offset */
#define AC_EVCTRL_REG_OFST (0x02) /**< (AC_EVCTRL) Event Control Offset */
#define AC_INTENCLR_REG_OFST (0x04) /**< (AC_INTENCLR) Interrupt Enable Clear Offset */
#define AC_INTENSET_REG_OFST (0x05) /**< (AC_INTENSET) Interrupt Enable Set Offset */
#define AC_INTFLAG_REG_OFST (0x06) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define AC_STATUSA_REG_OFST (0x07) /**< (AC_STATUSA) Status A Offset */
#define AC_STATUSB_REG_OFST (0x08) /**< (AC_STATUSB) Status B Offset */
#define AC_DBGCTRL_REG_OFST (0x09) /**< (AC_DBGCTRL) Debug Control Offset */
#define AC_WINCTRL_REG_OFST (0x0A) /**< (AC_WINCTRL) Window Control Offset */
#define AC_SCALER_REG_OFST (0x0C) /**< (AC_SCALER) Scaler n Offset */
#define AC_COMPCTRL_REG_OFST (0x10) /**< (AC_COMPCTRL) Comparator Control n Offset */
#define AC_SYNCBUSY_REG_OFST (0x20) /**< (AC_SYNCBUSY) Synchronization Busy Offset */
#define AC_CALIB_REG_OFST (0x24) /**< (AC_CALIB) Calibration Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief AC register API structure */
typedef struct
{ /* Analog Comparators */
__IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */
__IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */
__IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */
__I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */
__IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */
__IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */
__I uint8_t Reserved1[0x01];
__IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */
__I uint8_t Reserved2[0x02];
__IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */
__I uint8_t Reserved3[0x08];
__I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */
__IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */
} ac_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_AC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/adc.h
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/**
* \brief Component description for ADC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_ADC_COMPONENT_H_
#define _SAMD51_ADC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR ADC */
/* ************************************************************************** */
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */
#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< (ADC_CTRLA) Control A Reset Value */
#define ADC_CTRLA_SWRST_Pos _U_(0) /**< (ADC_CTRLA) Software Reset Position */
#define ADC_CTRLA_SWRST_Msk (_U_(0x1) << ADC_CTRLA_SWRST_Pos) /**< (ADC_CTRLA) Software Reset Mask */
#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos))
#define ADC_CTRLA_ENABLE_Pos _U_(1) /**< (ADC_CTRLA) Enable Position */
#define ADC_CTRLA_ENABLE_Msk (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) /**< (ADC_CTRLA) Enable Mask */
#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos))
#define ADC_CTRLA_DUALSEL_Pos _U_(3) /**< (ADC_CTRLA) Dual Mode Trigger Selection Position */
#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Dual Mode Trigger Selection Mask */
#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos))
#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */
#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */
#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */
#define ADC_CTRLA_SLAVEEN_Pos _U_(5) /**< (ADC_CTRLA) Slave Enable Position */
#define ADC_CTRLA_SLAVEEN_Msk (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /**< (ADC_CTRLA) Slave Enable Mask */
#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & ((value) << ADC_CTRLA_SLAVEEN_Pos))
#define ADC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (ADC_CTRLA) Run in Standby Position */
#define ADC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /**< (ADC_CTRLA) Run in Standby Mask */
#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos))
#define ADC_CTRLA_ONDEMAND_Pos _U_(7) /**< (ADC_CTRLA) On Demand Control Position */
#define ADC_CTRLA_ONDEMAND_Msk (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /**< (ADC_CTRLA) On Demand Control Mask */
#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & ((value) << ADC_CTRLA_ONDEMAND_Pos))
#define ADC_CTRLA_PRESCALER_Pos _U_(8) /**< (ADC_CTRLA) Prescaler Configuration Position */
#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Prescaler Configuration Mask */
#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos))
#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< (ADC_CTRLA) Peripheral clock divided by 2 */
#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< (ADC_CTRLA) Peripheral clock divided by 4 */
#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< (ADC_CTRLA) Peripheral clock divided by 8 */
#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< (ADC_CTRLA) Peripheral clock divided by 16 */
#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< (ADC_CTRLA) Peripheral clock divided by 32 */
#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (ADC_CTRLA) Peripheral clock divided by 64 */
#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< (ADC_CTRLA) Peripheral clock divided by 128 */
#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< (ADC_CTRLA) Peripheral clock divided by 256 */
#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 2 Position */
#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 4 Position */
#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 8 Position */
#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 16 Position */
#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 32 Position */
#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 64 Position */
#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 128 Position */
#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 256 Position */
#define ADC_CTRLA_R2R_Pos _U_(15) /**< (ADC_CTRLA) Rail to Rail Operation Enable Position */
#define ADC_CTRLA_R2R_Msk (_U_(0x1) << ADC_CTRLA_R2R_Pos) /**< (ADC_CTRLA) Rail to Rail Operation Enable Mask */
#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & ((value) << ADC_CTRLA_R2R_Pos))
#define ADC_CTRLA_Msk _U_(0x87FB) /**< (ADC_CTRLA) Register Mask */
/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */
#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< (ADC_EVCTRL) Event Control Reset Value */
#define ADC_EVCTRL_FLUSHEI_Pos _U_(0) /**< (ADC_EVCTRL) Flush Event Input Enable Position */
#define ADC_EVCTRL_FLUSHEI_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /**< (ADC_EVCTRL) Flush Event Input Enable Mask */
#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & ((value) << ADC_EVCTRL_FLUSHEI_Pos))
#define ADC_EVCTRL_STARTEI_Pos _U_(1) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Position */
#define ADC_EVCTRL_STARTEI_Msk (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Mask */
#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos))
#define ADC_EVCTRL_FLUSHINV_Pos _U_(2) /**< (ADC_EVCTRL) Flush Event Invert Enable Position */
#define ADC_EVCTRL_FLUSHINV_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /**< (ADC_EVCTRL) Flush Event Invert Enable Mask */
#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & ((value) << ADC_EVCTRL_FLUSHINV_Pos))
#define ADC_EVCTRL_STARTINV_Pos _U_(3) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Position */
#define ADC_EVCTRL_STARTINV_Msk (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */
#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & ((value) << ADC_EVCTRL_STARTINV_Pos))
#define ADC_EVCTRL_RESRDYEO_Pos _U_(4) /**< (ADC_EVCTRL) Result Ready Event Out Position */
#define ADC_EVCTRL_RESRDYEO_Msk (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /**< (ADC_EVCTRL) Result Ready Event Out Mask */
#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos))
#define ADC_EVCTRL_WINMONEO_Pos _U_(5) /**< (ADC_EVCTRL) Window Monitor Event Out Position */
#define ADC_EVCTRL_WINMONEO_Msk (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /**< (ADC_EVCTRL) Window Monitor Event Out Mask */
#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos))
#define ADC_EVCTRL_Msk _U_(0x3F) /**< (ADC_EVCTRL) Register Mask */
/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */
#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< (ADC_DBGCTRL) Debug Control Reset Value */
#define ADC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (ADC_DBGCTRL) Debug Run Position */
#define ADC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /**< (ADC_DBGCTRL) Debug Run Mask */
#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos))
#define ADC_DBGCTRL_Msk _U_(0x01) /**< (ADC_DBGCTRL) Register Mask */
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */
#define ADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< (ADC_INPUTCTRL) Input Control Reset Value */
#define ADC_INPUTCTRL_MUXPOS_Pos _U_(0) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */
#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< (ADC_INPUTCTRL) ADC AIN8 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< (ADC_INPUTCTRL) ADC AIN9 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< (ADC_INPUTCTRL) ADC AIN10 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< (ADC_INPUTCTRL) ADC AIN11 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< (ADC_INPUTCTRL) ADC AIN12 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< (ADC_INPUTCTRL) ADC AIN13 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< (ADC_INPUTCTRL) ADC AIN14 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< (ADC_INPUTCTRL) ADC AIN15 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< (ADC_INPUTCTRL) ADC AIN16 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< (ADC_INPUTCTRL) ADC AIN17 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< (ADC_INPUTCTRL) ADC AIN18 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< (ADC_INPUTCTRL) ADC AIN19 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< (ADC_INPUTCTRL) ADC AIN20 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< (ADC_INPUTCTRL) ADC AIN21 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< (ADC_INPUTCTRL) ADC AIN22 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< (ADC_INPUTCTRL) ADC AIN23 Pin */
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< (ADC_INPUTCTRL) Bandgap Voltage */
#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP */
#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC */
#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< (ADC_INPUTCTRL) DAC Output */
#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) */
#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN20 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN21 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN22 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN23 Pin Position */
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */
#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position */
#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */
#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position */
#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) Position */
#define ADC_INPUTCTRL_DIFFMODE_Pos _U_(7) /**< (ADC_INPUTCTRL) Differential Mode Position */
#define ADC_INPUTCTRL_DIFFMODE_Msk (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /**< (ADC_INPUTCTRL) Differential Mode Mask */
#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & ((value) << ADC_INPUTCTRL_DIFFMODE_Pos))
#define ADC_INPUTCTRL_MUXNEG_Pos _U_(8) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */
#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< (ADC_INPUTCTRL) Internal Ground */
#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */
#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position */
#define ADC_INPUTCTRL_DSEQSTOP_Pos _U_(15) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Position */
#define ADC_INPUTCTRL_DSEQSTOP_Msk (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Mask */
#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & ((value) << ADC_INPUTCTRL_DSEQSTOP_Pos))
#define ADC_INPUTCTRL_Msk _U_(0x9F9F) /**< (ADC_INPUTCTRL) Register Mask */
/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */
#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< (ADC_CTRLB) Control B Reset Value */
#define ADC_CTRLB_LEFTADJ_Pos _U_(0) /**< (ADC_CTRLB) Left-Adjusted Result Position */
#define ADC_CTRLB_LEFTADJ_Msk (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /**< (ADC_CTRLB) Left-Adjusted Result Mask */
#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos))
#define ADC_CTRLB_FREERUN_Pos _U_(1) /**< (ADC_CTRLB) Free Running Mode Position */
#define ADC_CTRLB_FREERUN_Msk (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) /**< (ADC_CTRLB) Free Running Mode Mask */
#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos))
#define ADC_CTRLB_CORREN_Pos _U_(2) /**< (ADC_CTRLB) Digital Correction Logic Enable Position */
#define ADC_CTRLB_CORREN_Msk (_U_(0x1) << ADC_CTRLB_CORREN_Pos) /**< (ADC_CTRLB) Digital Correction Logic Enable Mask */
#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos))
#define ADC_CTRLB_RESSEL_Pos _U_(3) /**< (ADC_CTRLB) Conversion Result Resolution Position */
#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) Conversion Result Resolution Mask */
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< (ADC_CTRLB) 12-bit result */
#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< (ADC_CTRLB) For averaging mode output */
#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< (ADC_CTRLB) 10-bit result */
#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< (ADC_CTRLB) 8-bit result */
#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position */
#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) For averaging mode output Position */
#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position */
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 8-bit result Position */
#define ADC_CTRLB_WINMODE_Pos _U_(8) /**< (ADC_CTRLB) Window Monitor Mode Position */
#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) Window Monitor Mode Mask */
#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos))
#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< (ADC_CTRLB) No window mode (default) */
#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< (ADC_CTRLB) RESULT > WINLT */
#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< (ADC_CTRLB) RESULT < WINUT */
#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< (ADC_CTRLB) WINLT < RESULT < WINUT */
#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) */
#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) No window mode (default) Position */
#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT > WINLT Position */
#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT < WINUT Position */
#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) WINLT < RESULT < WINUT Position */
#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */
#define ADC_CTRLB_WINSS_Pos _U_(11) /**< (ADC_CTRLB) Window Single Sample Position */
#define ADC_CTRLB_WINSS_Msk (_U_(0x1) << ADC_CTRLB_WINSS_Pos) /**< (ADC_CTRLB) Window Single Sample Mask */
#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & ((value) << ADC_CTRLB_WINSS_Pos))
#define ADC_CTRLB_Msk _U_(0x0F1F) /**< (ADC_CTRLB) Register Mask */
/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */
#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< (ADC_REFCTRL) Reference Control Reset Value */
#define ADC_REFCTRL_REFSEL_Pos _U_(0) /**< (ADC_REFCTRL) Reference Selection Position */
#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Reference Selection Mask */
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< (ADC_REFCTRL) Internal Bandgap Reference */
#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< (ADC_REFCTRL) 1/2 VDDANA */
#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< (ADC_REFCTRL) VDDANA */
#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< (ADC_REFCTRL) External Reference A */
#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< (ADC_REFCTRL) External Reference B */
#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< (ADC_REFCTRL) External Reference C (only on ADC1) */
#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Internal Bandgap Reference Position */
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA Position */
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) VDDANA Position */
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference A Position */
#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference B Position */
#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference C (only on ADC1) Position */
#define ADC_REFCTRL_REFCOMP_Pos _U_(7) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */
#define ADC_REFCTRL_REFCOMP_Msk (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */
#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos))
#define ADC_REFCTRL_Msk _U_(0x8F) /**< (ADC_REFCTRL) Register Mask */
/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */
#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< (ADC_AVGCTRL) Average Control Reset Value */
#define ADC_AVGCTRL_SAMPLENUM_Pos _U_(0) /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */
#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< (ADC_AVGCTRL) 1 sample */
#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< (ADC_AVGCTRL) 2 samples */
#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< (ADC_AVGCTRL) 4 samples */
#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< (ADC_AVGCTRL) 8 samples */
#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< (ADC_AVGCTRL) 16 samples */
#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< (ADC_AVGCTRL) 32 samples */
#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< (ADC_AVGCTRL) 64 samples */
#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< (ADC_AVGCTRL) 128 samples */
#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< (ADC_AVGCTRL) 256 samples */
#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< (ADC_AVGCTRL) 512 samples */
#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< (ADC_AVGCTRL) 1024 samples */
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position */
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position */
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position */
#define ADC_AVGCTRL_ADJRES_Pos _U_(4) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */
#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
#define ADC_AVGCTRL_Msk _U_(0x7F) /**< (ADC_AVGCTRL) Register Mask */
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */
#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< (ADC_SAMPCTRL) Sample Time Control Reset Value */
#define ADC_SAMPCTRL_SAMPLEN_Pos _U_(0) /**< (ADC_SAMPCTRL) Sampling Time Length Position */
#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /**< (ADC_SAMPCTRL) Sampling Time Length Mask */
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
#define ADC_SAMPCTRL_OFFCOMP_Pos _U_(7) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */
#define ADC_SAMPCTRL_OFFCOMP_Msk (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */
#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & ((value) << ADC_SAMPCTRL_OFFCOMP_Pos))
#define ADC_SAMPCTRL_Msk _U_(0xBF) /**< (ADC_SAMPCTRL) Register Mask */
/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */
#define ADC_WINLT_RESETVALUE _U_(0x00) /**< (ADC_WINLT) Window Monitor Lower Threshold Reset Value */
#define ADC_WINLT_WINLT_Pos _U_(0) /**< (ADC_WINLT) Window Lower Threshold Position */
#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) /**< (ADC_WINLT) Window Lower Threshold Mask */
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
#define ADC_WINLT_Msk _U_(0xFFFF) /**< (ADC_WINLT) Register Mask */
/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */
#define ADC_WINUT_RESETVALUE _U_(0x00) /**< (ADC_WINUT) Window Monitor Upper Threshold Reset Value */
#define ADC_WINUT_WINUT_Pos _U_(0) /**< (ADC_WINUT) Window Upper Threshold Position */
#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) /**< (ADC_WINUT) Window Upper Threshold Mask */
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
#define ADC_WINUT_Msk _U_(0xFFFF) /**< (ADC_WINUT) Register Mask */
/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */
#define ADC_GAINCORR_RESETVALUE _U_(0x00) /**< (ADC_GAINCORR) Gain Correction Reset Value */
#define ADC_GAINCORR_GAINCORR_Pos _U_(0) /**< (ADC_GAINCORR) Gain Correction Value Position */
#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /**< (ADC_GAINCORR) Gain Correction Value Mask */
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
#define ADC_GAINCORR_Msk _U_(0x0FFF) /**< (ADC_GAINCORR) Register Mask */
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */
#define ADC_OFFSETCORR_RESETVALUE _U_(0x00) /**< (ADC_OFFSETCORR) Offset Correction Reset Value */
#define ADC_OFFSETCORR_OFFSETCORR_Pos _U_(0) /**< (ADC_OFFSETCORR) Offset Correction Value Position */
#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /**< (ADC_OFFSETCORR) Offset Correction Value Mask */
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
#define ADC_OFFSETCORR_Msk _U_(0x0FFF) /**< (ADC_OFFSETCORR) Register Mask */
/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */
#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< (ADC_SWTRIG) Software Trigger Reset Value */
#define ADC_SWTRIG_FLUSH_Pos _U_(0) /**< (ADC_SWTRIG) ADC Conversion Flush Position */
#define ADC_SWTRIG_FLUSH_Msk (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) /**< (ADC_SWTRIG) ADC Conversion Flush Mask */
#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos))
#define ADC_SWTRIG_START_Pos _U_(1) /**< (ADC_SWTRIG) Start ADC Conversion Position */
#define ADC_SWTRIG_START_Msk (_U_(0x1) << ADC_SWTRIG_START_Pos) /**< (ADC_SWTRIG) Start ADC Conversion Mask */
#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos))
#define ADC_SWTRIG_Msk _U_(0x03) /**< (ADC_SWTRIG) Register Mask */
/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */
#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< (ADC_INTENCLR) Interrupt Enable Clear Reset Value */
#define ADC_INTENCLR_RESRDY_Pos _U_(0) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Position */
#define ADC_INTENCLR_RESRDY_Msk (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Mask */
#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos))
#define ADC_INTENCLR_OVERRUN_Pos _U_(1) /**< (ADC_INTENCLR) Overrun Interrupt Disable Position */
#define ADC_INTENCLR_OVERRUN_Msk (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /**< (ADC_INTENCLR) Overrun Interrupt Disable Mask */
#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos))
#define ADC_INTENCLR_WINMON_Pos _U_(2) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Position */
#define ADC_INTENCLR_WINMON_Msk (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */
#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos))
#define ADC_INTENCLR_Msk _U_(0x07) /**< (ADC_INTENCLR) Register Mask */
/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */
#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< (ADC_INTENSET) Interrupt Enable Set Reset Value */
#define ADC_INTENSET_RESRDY_Pos _U_(0) /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */
#define ADC_INTENSET_RESRDY_Msk (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */
#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos))
#define ADC_INTENSET_OVERRUN_Pos _U_(1) /**< (ADC_INTENSET) Overrun Interrupt Enable Position */
#define ADC_INTENSET_OVERRUN_Msk (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */
#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos))
#define ADC_INTENSET_WINMON_Pos _U_(2) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */
#define ADC_INTENSET_WINMON_Msk (_U_(0x1) << ADC_INTENSET_WINMON_Pos) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */
#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos))
#define ADC_INTENSET_Msk _U_(0x07) /**< (ADC_INTENSET) Register Mask */
/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */
#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define ADC_INTFLAG_RESRDY_Pos _U_(0) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Position */
#define ADC_INTFLAG_RESRDY_Msk (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Mask */
#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos))
#define ADC_INTFLAG_OVERRUN_Pos _U_(1) /**< (ADC_INTFLAG) Overrun Interrupt Flag Position */
#define ADC_INTFLAG_OVERRUN_Msk (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /**< (ADC_INTFLAG) Overrun Interrupt Flag Mask */
#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos))
#define ADC_INTFLAG_WINMON_Pos _U_(2) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Position */
#define ADC_INTFLAG_WINMON_Msk (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */
#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos))
#define ADC_INTFLAG_Msk _U_(0x07) /**< (ADC_INTFLAG) Register Mask */
/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */
#define ADC_STATUS_RESETVALUE _U_(0x00) /**< (ADC_STATUS) Status Reset Value */
#define ADC_STATUS_ADCBUSY_Pos _U_(0) /**< (ADC_STATUS) ADC Busy Status Position */
#define ADC_STATUS_ADCBUSY_Msk (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) /**< (ADC_STATUS) ADC Busy Status Mask */
#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & ((value) << ADC_STATUS_ADCBUSY_Pos))
#define ADC_STATUS_WCC_Pos _U_(2) /**< (ADC_STATUS) Window Comparator Counter Position */
#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) /**< (ADC_STATUS) Window Comparator Counter Mask */
#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos))
#define ADC_STATUS_Msk _U_(0xFD) /**< (ADC_STATUS) Register Mask */
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */
#define ADC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (ADC_SYNCBUSY) Synchronization Busy Reset Value */
#define ADC_SYNCBUSY_SWRST_Pos _U_(0) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Position */
#define ADC_SYNCBUSY_SWRST_Msk (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */
#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & ((value) << ADC_SYNCBUSY_SWRST_Pos))
#define ADC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */
#define ADC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */
#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & ((value) << ADC_SYNCBUSY_ENABLE_Pos))
#define ADC_SYNCBUSY_INPUTCTRL_Pos _U_(2) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Position */
#define ADC_SYNCBUSY_INPUTCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */
#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & ((value) << ADC_SYNCBUSY_INPUTCTRL_Pos))
#define ADC_SYNCBUSY_CTRLB_Pos _U_(3) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Position */
#define ADC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Mask */
#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & ((value) << ADC_SYNCBUSY_CTRLB_Pos))
#define ADC_SYNCBUSY_REFCTRL_Pos _U_(4) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */
#define ADC_SYNCBUSY_REFCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */
#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & ((value) << ADC_SYNCBUSY_REFCTRL_Pos))
#define ADC_SYNCBUSY_AVGCTRL_Pos _U_(5) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Position */
#define ADC_SYNCBUSY_AVGCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */
#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & ((value) << ADC_SYNCBUSY_AVGCTRL_Pos))
#define ADC_SYNCBUSY_SAMPCTRL_Pos _U_(6) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */
#define ADC_SYNCBUSY_SAMPCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */
#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & ((value) << ADC_SYNCBUSY_SAMPCTRL_Pos))
#define ADC_SYNCBUSY_WINLT_Pos _U_(7) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */
#define ADC_SYNCBUSY_WINLT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */
#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & ((value) << ADC_SYNCBUSY_WINLT_Pos))
#define ADC_SYNCBUSY_WINUT_Pos _U_(8) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */
#define ADC_SYNCBUSY_WINUT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */
#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & ((value) << ADC_SYNCBUSY_WINUT_Pos))
#define ADC_SYNCBUSY_GAINCORR_Pos _U_(9) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */
#define ADC_SYNCBUSY_GAINCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */
#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & ((value) << ADC_SYNCBUSY_GAINCORR_Pos))
#define ADC_SYNCBUSY_OFFSETCORR_Pos _U_(10) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */
#define ADC_SYNCBUSY_OFFSETCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */
#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & ((value) << ADC_SYNCBUSY_OFFSETCORR_Pos))
#define ADC_SYNCBUSY_SWTRIG_Pos _U_(11) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */
#define ADC_SYNCBUSY_SWTRIG_Msk (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */
#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & ((value) << ADC_SYNCBUSY_SWTRIG_Pos))
#define ADC_SYNCBUSY_Msk _U_(0x00000FFF) /**< (ADC_SYNCBUSY) Register Mask */
/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */
#define ADC_DSEQDATA_RESETVALUE _U_(0x00) /**< (ADC_DSEQDATA) DMA Sequencial Data Reset Value */
#define ADC_DSEQDATA_DATA_Pos _U_(0) /**< (ADC_DSEQDATA) DMA Sequential Data Position */
#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /**< (ADC_DSEQDATA) DMA Sequential Data Mask */
#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos))
#define ADC_DSEQDATA_Msk _U_(0xFFFFFFFF) /**< (ADC_DSEQDATA) Register Mask */
/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */
#define ADC_DSEQCTRL_RESETVALUE _U_(0x00) /**< (ADC_DSEQCTRL) DMA Sequential Control Reset Value */
#define ADC_DSEQCTRL_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQCTRL) Input Control Position */
#define ADC_DSEQCTRL_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /**< (ADC_DSEQCTRL) Input Control Mask */
#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & ((value) << ADC_DSEQCTRL_INPUTCTRL_Pos))
#define ADC_DSEQCTRL_CTRLB_Pos _U_(1) /**< (ADC_DSEQCTRL) Control B Position */
#define ADC_DSEQCTRL_CTRLB_Msk (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /**< (ADC_DSEQCTRL) Control B Mask */
#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & ((value) << ADC_DSEQCTRL_CTRLB_Pos))
#define ADC_DSEQCTRL_REFCTRL_Pos _U_(2) /**< (ADC_DSEQCTRL) Reference Control Position */
#define ADC_DSEQCTRL_REFCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /**< (ADC_DSEQCTRL) Reference Control Mask */
#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & ((value) << ADC_DSEQCTRL_REFCTRL_Pos))
#define ADC_DSEQCTRL_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQCTRL) Average Control Position */
#define ADC_DSEQCTRL_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /**< (ADC_DSEQCTRL) Average Control Mask */
#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & ((value) << ADC_DSEQCTRL_AVGCTRL_Pos))
#define ADC_DSEQCTRL_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQCTRL) Sampling Time Control Position */
#define ADC_DSEQCTRL_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /**< (ADC_DSEQCTRL) Sampling Time Control Mask */
#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & ((value) << ADC_DSEQCTRL_SAMPCTRL_Pos))
#define ADC_DSEQCTRL_WINLT_Pos _U_(5) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */
#define ADC_DSEQCTRL_WINLT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */
#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & ((value) << ADC_DSEQCTRL_WINLT_Pos))
#define ADC_DSEQCTRL_WINUT_Pos _U_(6) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */
#define ADC_DSEQCTRL_WINUT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */
#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & ((value) << ADC_DSEQCTRL_WINUT_Pos))
#define ADC_DSEQCTRL_GAINCORR_Pos _U_(7) /**< (ADC_DSEQCTRL) Gain Correction Position */
#define ADC_DSEQCTRL_GAINCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /**< (ADC_DSEQCTRL) Gain Correction Mask */
#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & ((value) << ADC_DSEQCTRL_GAINCORR_Pos))
#define ADC_DSEQCTRL_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQCTRL) Offset Correction Position */
#define ADC_DSEQCTRL_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /**< (ADC_DSEQCTRL) Offset Correction Mask */
#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & ((value) << ADC_DSEQCTRL_OFFSETCORR_Pos))
#define ADC_DSEQCTRL_AUTOSTART_Pos _U_(31) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */
#define ADC_DSEQCTRL_AUTOSTART_Msk (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */
#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & ((value) << ADC_DSEQCTRL_AUTOSTART_Pos))
#define ADC_DSEQCTRL_Msk _U_(0x800001FF) /**< (ADC_DSEQCTRL) Register Mask */
/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */
#define ADC_DSEQSTAT_RESETVALUE _U_(0x00) /**< (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */
#define ADC_DSEQSTAT_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQSTAT) Input Control Position */
#define ADC_DSEQSTAT_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /**< (ADC_DSEQSTAT) Input Control Mask */
#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & ((value) << ADC_DSEQSTAT_INPUTCTRL_Pos))
#define ADC_DSEQSTAT_CTRLB_Pos _U_(1) /**< (ADC_DSEQSTAT) Control B Position */
#define ADC_DSEQSTAT_CTRLB_Msk (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /**< (ADC_DSEQSTAT) Control B Mask */
#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & ((value) << ADC_DSEQSTAT_CTRLB_Pos))
#define ADC_DSEQSTAT_REFCTRL_Pos _U_(2) /**< (ADC_DSEQSTAT) Reference Control Position */
#define ADC_DSEQSTAT_REFCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /**< (ADC_DSEQSTAT) Reference Control Mask */
#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & ((value) << ADC_DSEQSTAT_REFCTRL_Pos))
#define ADC_DSEQSTAT_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQSTAT) Average Control Position */
#define ADC_DSEQSTAT_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /**< (ADC_DSEQSTAT) Average Control Mask */
#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & ((value) << ADC_DSEQSTAT_AVGCTRL_Pos))
#define ADC_DSEQSTAT_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQSTAT) Sampling Time Control Position */
#define ADC_DSEQSTAT_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /**< (ADC_DSEQSTAT) Sampling Time Control Mask */
#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & ((value) << ADC_DSEQSTAT_SAMPCTRL_Pos))
#define ADC_DSEQSTAT_WINLT_Pos _U_(5) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */
#define ADC_DSEQSTAT_WINLT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */
#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & ((value) << ADC_DSEQSTAT_WINLT_Pos))
#define ADC_DSEQSTAT_WINUT_Pos _U_(6) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */
#define ADC_DSEQSTAT_WINUT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */
#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & ((value) << ADC_DSEQSTAT_WINUT_Pos))
#define ADC_DSEQSTAT_GAINCORR_Pos _U_(7) /**< (ADC_DSEQSTAT) Gain Correction Position */
#define ADC_DSEQSTAT_GAINCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /**< (ADC_DSEQSTAT) Gain Correction Mask */
#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & ((value) << ADC_DSEQSTAT_GAINCORR_Pos))
#define ADC_DSEQSTAT_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQSTAT) Offset Correction Position */
#define ADC_DSEQSTAT_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /**< (ADC_DSEQSTAT) Offset Correction Mask */
#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & ((value) << ADC_DSEQSTAT_OFFSETCORR_Pos))
#define ADC_DSEQSTAT_BUSY_Pos _U_(31) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Position */
#define ADC_DSEQSTAT_BUSY_Msk (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Mask */
#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & ((value) << ADC_DSEQSTAT_BUSY_Pos))
#define ADC_DSEQSTAT_Msk _U_(0x800001FF) /**< (ADC_DSEQSTAT) Register Mask */
/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */
#define ADC_RESULT_RESETVALUE _U_(0x00) /**< (ADC_RESULT) Result Conversion Value Reset Value */
#define ADC_RESULT_RESULT_Pos _U_(0) /**< (ADC_RESULT) Result Conversion Value Position */
#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) /**< (ADC_RESULT) Result Conversion Value Mask */
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
#define ADC_RESULT_Msk _U_(0xFFFF) /**< (ADC_RESULT) Register Mask */
/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */
#define ADC_RESS_RESETVALUE _U_(0x00) /**< (ADC_RESS) Last Sample Result Reset Value */
#define ADC_RESS_RESS_Pos _U_(0) /**< (ADC_RESS) Last ADC conversion result Position */
#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) /**< (ADC_RESS) Last ADC conversion result Mask */
#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos))
#define ADC_RESS_Msk _U_(0xFFFF) /**< (ADC_RESS) Register Mask */
/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */
#define ADC_CALIB_RESETVALUE _U_(0x00) /**< (ADC_CALIB) Calibration Reset Value */
#define ADC_CALIB_BIASCOMP_Pos _U_(0) /**< (ADC_CALIB) Bias Comparator Scaling Position */
#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) /**< (ADC_CALIB) Bias Comparator Scaling Mask */
#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
#define ADC_CALIB_BIASR2R_Pos _U_(4) /**< (ADC_CALIB) Bias R2R Ampli scaling Position */
#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) /**< (ADC_CALIB) Bias R2R Ampli scaling Mask */
#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos))
#define ADC_CALIB_BIASREFBUF_Pos _U_(8) /**< (ADC_CALIB) Bias Reference Buffer Scaling Position */
#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /**< (ADC_CALIB) Bias Reference Buffer Scaling Mask */
#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
#define ADC_CALIB_Msk _U_(0x0777) /**< (ADC_CALIB) Register Mask */
/** \brief ADC register offsets definitions */
#define ADC_CTRLA_REG_OFST (0x00) /**< (ADC_CTRLA) Control A Offset */
#define ADC_EVCTRL_REG_OFST (0x02) /**< (ADC_EVCTRL) Event Control Offset */
#define ADC_DBGCTRL_REG_OFST (0x03) /**< (ADC_DBGCTRL) Debug Control Offset */
#define ADC_INPUTCTRL_REG_OFST (0x04) /**< (ADC_INPUTCTRL) Input Control Offset */
#define ADC_CTRLB_REG_OFST (0x06) /**< (ADC_CTRLB) Control B Offset */
#define ADC_REFCTRL_REG_OFST (0x08) /**< (ADC_REFCTRL) Reference Control Offset */
#define ADC_AVGCTRL_REG_OFST (0x0A) /**< (ADC_AVGCTRL) Average Control Offset */
#define ADC_SAMPCTRL_REG_OFST (0x0B) /**< (ADC_SAMPCTRL) Sample Time Control Offset */
#define ADC_WINLT_REG_OFST (0x0C) /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */
#define ADC_WINUT_REG_OFST (0x0E) /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */
#define ADC_GAINCORR_REG_OFST (0x10) /**< (ADC_GAINCORR) Gain Correction Offset */
#define ADC_OFFSETCORR_REG_OFST (0x12) /**< (ADC_OFFSETCORR) Offset Correction Offset */
#define ADC_SWTRIG_REG_OFST (0x14) /**< (ADC_SWTRIG) Software Trigger Offset */
#define ADC_INTENCLR_REG_OFST (0x2C) /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */
#define ADC_INTENSET_REG_OFST (0x2D) /**< (ADC_INTENSET) Interrupt Enable Set Offset */
#define ADC_INTFLAG_REG_OFST (0x2E) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define ADC_STATUS_REG_OFST (0x2F) /**< (ADC_STATUS) Status Offset */
#define ADC_SYNCBUSY_REG_OFST (0x30) /**< (ADC_SYNCBUSY) Synchronization Busy Offset */
#define ADC_DSEQDATA_REG_OFST (0x34) /**< (ADC_DSEQDATA) DMA Sequencial Data Offset */
#define ADC_DSEQCTRL_REG_OFST (0x38) /**< (ADC_DSEQCTRL) DMA Sequential Control Offset */
#define ADC_DSEQSTAT_REG_OFST (0x3C) /**< (ADC_DSEQSTAT) DMA Sequencial Status Offset */
#define ADC_RESULT_REG_OFST (0x40) /**< (ADC_RESULT) Result Conversion Value Offset */
#define ADC_RESS_REG_OFST (0x44) /**< (ADC_RESS) Last Sample Result Offset */
#define ADC_CALIB_REG_OFST (0x48) /**< (ADC_CALIB) Calibration Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief ADC register API structure */
typedef struct
{ /* Analog Digital Converter */
__IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
__IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */
__IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */
__IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */
__IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */
__IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */
__I uint8_t Reserved1[0x01];
__IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */
__IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */
__IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */
__IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */
__IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */
__IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */
__IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */
__I uint8_t Reserved2[0x17];
__IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */
__IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */
__IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */
__I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */
__O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */
__IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */
__I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */
__I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */
__I uint8_t Reserved3[0x02];
__I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */
__I uint8_t Reserved4[0x02];
__IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */
} adc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_ADC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/aes.h
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/**
* \brief Component description for AES
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_AES_COMPONENT_H_
#define _SAMD51_AES_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR AES */
/* ************************************************************************** */
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */
#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */
#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */
#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos))
#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */
#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */
#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos))
#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */
#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */
#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */
#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos))
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */
#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */
#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */
#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos))
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */
#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */
#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */
#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos))
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */
#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */
#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */
#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos))
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */
#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */
#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */
#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos))
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */
#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */
#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */
#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */
#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos))
#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */
#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */
#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos))
#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */
#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */
#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos))
#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */
#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */
#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos))
#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */
#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */
#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */
#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos))
#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */
#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */
#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos))
#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */
#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */
#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */
#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos))
#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */
#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */
#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos))
#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */
#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */
#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */
#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos))
#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */
#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */
#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos))
#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */
#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */
#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */
#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */
#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos))
#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */
#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */
#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */
#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */
#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */
#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */
#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */
#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */
/** \brief AES register offsets definitions */
#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */
#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */
#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */
#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */
#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */
#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */
#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */
#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */
#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */
#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */
#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */
#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */
#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */
#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief AES register API structure */
typedef struct
{ /* Advanced Encryption Standard */
__IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */
__IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */
__IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */
__IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */
__I uint8_t Reserved1[0x02];
__O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */
__I uint8_t Reserved2[0x0C];
__IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */
__O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */
__I uint8_t Reserved3[0x10];
__IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */
__IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */
__I uint8_t Reserved4[0x04];
__IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */
__IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */
} aes_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_AES_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/ccl.h
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/**
* \brief Component description for CCL
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_CCL_COMPONENT_H_
#define _SAMD51_CCL_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR CCL */
/* ************************************************************************** */
/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< (CCL_CTRL) Control Reset Value */
#define CCL_CTRL_SWRST_Pos _U_(0) /**< (CCL_CTRL) Software Reset Position */
#define CCL_CTRL_SWRST_Msk (_U_(0x1) << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) Software Reset Mask */
#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & ((value) << CCL_CTRL_SWRST_Pos))
#define CCL_CTRL_SWRST_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is not reset */
#define CCL_CTRL_SWRST_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is reset */
#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is not reset Position */
#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is reset Position */
#define CCL_CTRL_ENABLE_Pos _U_(1) /**< (CCL_CTRL) Enable Position */
#define CCL_CTRL_ENABLE_Msk (_U_(0x1) << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) Enable Mask */
#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & ((value) << CCL_CTRL_ENABLE_Pos))
#define CCL_CTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is disabled */
#define CCL_CTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is enabled */
#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is disabled Position */
#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is enabled Position */
#define CCL_CTRL_RUNSTDBY_Pos _U_(6) /**< (CCL_CTRL) Run in Standby Position */
#define CCL_CTRL_RUNSTDBY_Msk (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Run in Standby Mask */
#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & ((value) << CCL_CTRL_RUNSTDBY_Pos))
#define CCL_CTRL_RUNSTDBY_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode */
#define CCL_CTRL_RUNSTDBY_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) Generic clock is required in standby sleep mode */
#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode Position */
#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is required in standby sleep mode Position */
#define CCL_CTRL_Msk _U_(0x43) /**< (CCL_CTRL) Register Mask */
/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< (CCL_SEQCTRL) SEQ Control x Reset Value */
#define CCL_SEQCTRL_SEQSEL_Pos _U_(0) /**< (CCL_SEQCTRL) Sequential Selection Position */
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential Selection Mask */
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< (CCL_SEQCTRL) Sequential logic is disabled */
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< (CCL_SEQCTRL) D flip flop */
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< (CCL_SEQCTRL) JK flip flop */
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< (CCL_SEQCTRL) D latch */
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< (CCL_SEQCTRL) RS latch */
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential logic is disabled Position */
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D flip flop Position */
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) JK flip flop Position */
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D latch Position */
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) RS latch Position */
#define CCL_SEQCTRL_Msk _U_(0x0F) /**< (CCL_SEQCTRL) Register Mask */
/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */
#define CCL_LUTCTRL_RESETVALUE _U_(0x00) /**< (CCL_LUTCTRL) LUT Control x Reset Value */
#define CCL_LUTCTRL_ENABLE_Pos _U_(1) /**< (CCL_LUTCTRL) LUT Enable Position */
#define CCL_LUTCTRL_ENABLE_Msk (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT Enable Mask */
#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & ((value) << CCL_LUTCTRL_ENABLE_Pos))
#define CCL_LUTCTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT block is disabled */
#define CCL_LUTCTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT block is enabled */
#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is disabled Position */
#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is enabled Position */
#define CCL_LUTCTRL_FILTSEL_Pos _U_(4) /**< (CCL_LUTCTRL) Filter Selection Position */
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter Selection Mask */
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Filter disabled */
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< (CCL_LUTCTRL) Synchronizer enabled */
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< (CCL_LUTCTRL) Filter enabled */
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter disabled Position */
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Synchronizer enabled Position */
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter enabled Position */
#define CCL_LUTCTRL_EDGESEL_Pos _U_(7) /**< (CCL_LUTCTRL) Edge Selection Position */
#define CCL_LUTCTRL_EDGESEL_Msk (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge Selection Mask */
#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & ((value) << CCL_LUTCTRL_EDGESEL_Pos))
#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Edge detector is disabled */
#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Edge detector is enabled */
#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is disabled Position */
#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is enabled Position */
#define CCL_LUTCTRL_INSEL0_Pos _U_(8) /**< (CCL_LUTCTRL) Input Selection 0 Position */
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Input Selection 0 Mask */
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Masked input Position */
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Event input source Position */
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) AC input source Position */
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TC input source Position */
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TCC input source Position */
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */
#define CCL_LUTCTRL_INSEL1_Pos _U_(12) /**< (CCL_LUTCTRL) Input Selection 1 Position */
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Input Selection 1 Mask */
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Masked input Position */
#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */
#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */
#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Event input source Position */
#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */
#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) AC input source Position */
#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TC input source Position */
#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */
#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TCC input source Position */
#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */
#define CCL_LUTCTRL_INSEL2_Pos _U_(16) /**< (CCL_LUTCTRL) Input Selection 2 Position */
#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Input Selection 2 Mask */
#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Masked input Position */
#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */
#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */
#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Event input source Position */
#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */
#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) AC input source Position */
#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TC input source Position */
#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */
#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TCC input source Position */
#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */
#define CCL_LUTCTRL_INVEI_Pos _U_(20) /**< (CCL_LUTCTRL) Inverted Event Input Enable Position */
#define CCL_LUTCTRL_INVEI_Msk (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Inverted Event Input Enable Mask */
#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & ((value) << CCL_LUTCTRL_INVEI_Pos))
#define CCL_LUTCTRL_INVEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Incoming event is not inverted */
#define CCL_LUTCTRL_INVEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Incoming event is inverted */
#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is not inverted Position */
#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is inverted Position */
#define CCL_LUTCTRL_LUTEI_Pos _U_(21) /**< (CCL_LUTCTRL) LUT Event Input Enable Position */
#define CCL_LUTCTRL_LUTEI_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT Event Input Enable Mask */
#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & ((value) << CCL_LUTCTRL_LUTEI_Pos))
#define CCL_LUTCTRL_LUTEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT incoming event is disabled */
#define CCL_LUTCTRL_LUTEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT incoming event is enabled */
#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is disabled Position */
#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is enabled Position */
#define CCL_LUTCTRL_LUTEO_Pos _U_(22) /**< (CCL_LUTCTRL) LUT Event Output Enable Position */
#define CCL_LUTCTRL_LUTEO_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT Event Output Enable Mask */
#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & ((value) << CCL_LUTCTRL_LUTEO_Pos))
#define CCL_LUTCTRL_LUTEO_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT event output is disabled */
#define CCL_LUTCTRL_LUTEO_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT event output is enabled */
#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is disabled Position */
#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is enabled Position */
#define CCL_LUTCTRL_TRUTH_Pos _U_(24) /**< (CCL_LUTCTRL) Truth Value Position */
#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /**< (CCL_LUTCTRL) Truth Value Mask */
#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
#define CCL_LUTCTRL_Msk _U_(0xFF7FFFB2) /**< (CCL_LUTCTRL) Register Mask */
/** \brief CCL register offsets definitions */
#define CCL_CTRL_REG_OFST (0x00) /**< (CCL_CTRL) Control Offset */
#define CCL_SEQCTRL_REG_OFST (0x04) /**< (CCL_SEQCTRL) SEQ Control x Offset */
#define CCL_LUTCTRL_REG_OFST (0x08) /**< (CCL_LUTCTRL) LUT Control x Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief CCL register API structure */
typedef struct
{ /* Configurable Custom Logic */
__IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */
__I uint8_t Reserved1[0x03];
__IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */
__I uint8_t Reserved2[0x02];
__IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */
} ccl_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_CCL_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/cmcc.h
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/**
* \brief Component description for CMCC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_CMCC_COMPONENT_H_
#define _SAMD51_CMCC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR CMCC */
/* ************************************************************************** */
/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */
#define CMCC_TYPE_RESETVALUE _U_(0x12D2) /**< (CMCC_TYPE) Cache Type Register Reset Value */
#define CMCC_TYPE_GCLK_Pos _U_(1) /**< (CMCC_TYPE) dynamic Clock Gating supported Position */
#define CMCC_TYPE_GCLK_Msk (_U_(0x1) << CMCC_TYPE_GCLK_Pos) /**< (CMCC_TYPE) dynamic Clock Gating supported Mask */
#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & ((value) << CMCC_TYPE_GCLK_Pos))
#define CMCC_TYPE_RRP_Pos _U_(4) /**< (CMCC_TYPE) Round Robin Policy supported Position */
#define CMCC_TYPE_RRP_Msk (_U_(0x1) << CMCC_TYPE_RRP_Pos) /**< (CMCC_TYPE) Round Robin Policy supported Mask */
#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & ((value) << CMCC_TYPE_RRP_Pos))
#define CMCC_TYPE_WAYNUM_Pos _U_(5) /**< (CMCC_TYPE) Number of Way Position */
#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Number of Way Mask */
#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< (CMCC_TYPE) Direct Mapped Cache */
#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< (CMCC_TYPE) 2-WAY set associative */
#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< (CMCC_TYPE) 4-WAY set associative */
#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Direct Mapped Cache Position */
#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 2-WAY set associative Position */
#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 4-WAY set associative Position */
#define CMCC_TYPE_LCKDOWN_Pos _U_(7) /**< (CMCC_TYPE) Lock Down supported Position */
#define CMCC_TYPE_LCKDOWN_Msk (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /**< (CMCC_TYPE) Lock Down supported Mask */
#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & ((value) << CMCC_TYPE_LCKDOWN_Pos))
#define CMCC_TYPE_CSIZE_Pos _U_(8) /**< (CMCC_TYPE) Cache Size Position */
#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size Mask */
#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_TYPE) Cache Size is 1 KB */
#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_TYPE) Cache Size is 2 KB */
#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_TYPE) Cache Size is 4 KB */
#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_TYPE) Cache Size is 8 KB */
#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_TYPE) Cache Size is 16 KB */
#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_TYPE) Cache Size is 32 KB */
#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_TYPE) Cache Size is 64 KB */
#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 1 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 2 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 4 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 8 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 16 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 32 KB Position */
#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 64 KB Position */
#define CMCC_TYPE_CLSIZE_Pos _U_(11) /**< (CMCC_TYPE) Cache Line Size Position */
#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size Mask */
#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< (CMCC_TYPE) Cache Line Size is 4 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< (CMCC_TYPE) Cache Line Size is 8 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< (CMCC_TYPE) Cache Line Size is 16 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< (CMCC_TYPE) Cache Line Size is 32 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< (CMCC_TYPE) Cache Line Size is 64 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< (CMCC_TYPE) Cache Line Size is 128 bytes */
#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 4 bytes Position */
#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 8 bytes Position */
#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 16 bytes Position */
#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 32 bytes Position */
#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 64 bytes Position */
#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 128 bytes Position */
#define CMCC_TYPE_Msk _U_(0x00003FF2) /**< (CMCC_TYPE) Register Mask */
/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
#define CMCC_CFG_RESETVALUE _U_(0x20) /**< (CMCC_CFG) Cache Configuration Register Reset Value */
#define CMCC_CFG_ICDIS_Pos _U_(1) /**< (CMCC_CFG) Instruction Cache Disable Position */
#define CMCC_CFG_ICDIS_Msk (_U_(0x1) << CMCC_CFG_ICDIS_Pos) /**< (CMCC_CFG) Instruction Cache Disable Mask */
#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & ((value) << CMCC_CFG_ICDIS_Pos))
#define CMCC_CFG_DCDIS_Pos _U_(2) /**< (CMCC_CFG) Data Cache Disable Position */
#define CMCC_CFG_DCDIS_Msk (_U_(0x1) << CMCC_CFG_DCDIS_Pos) /**< (CMCC_CFG) Data Cache Disable Mask */
#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & ((value) << CMCC_CFG_DCDIS_Pos))
#define CMCC_CFG_CSIZESW_Pos _U_(4) /**< (CMCC_CFG) Cache size configured by software Position */
#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) Cache size configured by software Mask */
#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_CFG) The Cache Size is configured to 1KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_CFG) The Cache Size is configured to 2KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_CFG) The Cache Size is configured to 4KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_CFG) The Cache Size is configured to 8KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_CFG) The Cache Size is configured to 16KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_CFG) The Cache Size is configured to 32KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_CFG) The Cache Size is configured to 64KB */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 1KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 2KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 4KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 8KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 16KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 32KB Position */
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 64KB Position */
#define CMCC_CFG_Msk _U_(0x00000076) /**< (CMCC_CFG) Register Mask */
/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
#define CMCC_CTRL_RESETVALUE _U_(0x00) /**< (CMCC_CTRL) Cache Control Register Reset Value */
#define CMCC_CTRL_CEN_Pos _U_(0) /**< (CMCC_CTRL) Cache Controller Enable Position */
#define CMCC_CTRL_CEN_Msk (_U_(0x1) << CMCC_CTRL_CEN_Pos) /**< (CMCC_CTRL) Cache Controller Enable Mask */
#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & ((value) << CMCC_CTRL_CEN_Pos))
#define CMCC_CTRL_Msk _U_(0x00000001) /**< (CMCC_CTRL) Register Mask */
/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */
#define CMCC_SR_RESETVALUE _U_(0x00) /**< (CMCC_SR) Cache Status Register Reset Value */
#define CMCC_SR_CSTS_Pos _U_(0) /**< (CMCC_SR) Cache Controller Status Position */
#define CMCC_SR_CSTS_Msk (_U_(0x1) << CMCC_SR_CSTS_Pos) /**< (CMCC_SR) Cache Controller Status Mask */
#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & ((value) << CMCC_SR_CSTS_Pos))
#define CMCC_SR_Msk _U_(0x00000001) /**< (CMCC_SR) Register Mask */
/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
#define CMCC_LCKWAY_RESETVALUE _U_(0x00) /**< (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */
#define CMCC_LCKWAY_LCKWAY_Pos _U_(0) /**< (CMCC_LCKWAY) Lockdown way Register Position */
#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /**< (CMCC_LCKWAY) Lockdown way Register Mask */
#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
#define CMCC_LCKWAY_Msk _U_(0x0000000F) /**< (CMCC_LCKWAY) Register Mask */
/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
#define CMCC_MAINT0_RESETVALUE _U_(0x00) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */
#define CMCC_MAINT0_INVALL_Pos _U_(0) /**< (CMCC_MAINT0) Cache Controller invalidate All Position */
#define CMCC_MAINT0_INVALL_Msk (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) /**< (CMCC_MAINT0) Cache Controller invalidate All Mask */
#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & ((value) << CMCC_MAINT0_INVALL_Pos))
#define CMCC_MAINT0_Msk _U_(0x00000001) /**< (CMCC_MAINT0) Register Mask */
/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
#define CMCC_MAINT1_RESETVALUE _U_(0x00) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */
#define CMCC_MAINT1_INDEX_Pos _U_(4) /**< (CMCC_MAINT1) Invalidate Index Position */
#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) /**< (CMCC_MAINT1) Invalidate Index Mask */
#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
#define CMCC_MAINT1_WAY_Pos _U_(28) /**< (CMCC_MAINT1) Invalidate Way Position */
#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Invalidate Way Mask */
#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation */
#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation Position */
#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation Position */
#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation Position */
#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation Position */
#define CMCC_MAINT1_Msk _U_(0xF0000FF0) /**< (CMCC_MAINT1) Register Mask */
/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
#define CMCC_MCFG_RESETVALUE _U_(0x00) /**< (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */
#define CMCC_MCFG_MODE_Pos _U_(0) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */
#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */
#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< (CMCC_MCFG) Cycle counter */
#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< (CMCC_MCFG) Instruction hit counter */
#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< (CMCC_MCFG) Data hit counter */
#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cycle counter Position */
#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Instruction hit counter Position */
#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Data hit counter Position */
#define CMCC_MCFG_Msk _U_(0x00000003) /**< (CMCC_MCFG) Register Mask */
/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
#define CMCC_MEN_RESETVALUE _U_(0x00) /**< (CMCC_MEN) Cache Monitor Enable Register Reset Value */
#define CMCC_MEN_MENABLE_Pos _U_(0) /**< (CMCC_MEN) Cache Controller Monitor Enable Position */
#define CMCC_MEN_MENABLE_Msk (_U_(0x1) << CMCC_MEN_MENABLE_Pos) /**< (CMCC_MEN) Cache Controller Monitor Enable Mask */
#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & ((value) << CMCC_MEN_MENABLE_Pos))
#define CMCC_MEN_Msk _U_(0x00000001) /**< (CMCC_MEN) Register Mask */
/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
#define CMCC_MCTRL_RESETVALUE _U_(0x00) /**< (CMCC_MCTRL) Cache Monitor Control Register Reset Value */
#define CMCC_MCTRL_SWRST_Pos _U_(0) /**< (CMCC_MCTRL) Cache Controller Software Reset Position */
#define CMCC_MCTRL_SWRST_Msk (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) /**< (CMCC_MCTRL) Cache Controller Software Reset Mask */
#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & ((value) << CMCC_MCTRL_SWRST_Pos))
#define CMCC_MCTRL_Msk _U_(0x00000001) /**< (CMCC_MCTRL) Register Mask */
/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */
#define CMCC_MSR_RESETVALUE _U_(0x00) /**< (CMCC_MSR) Cache Monitor Status Register Reset Value */
#define CMCC_MSR_EVENT_CNT_Pos _U_(0) /**< (CMCC_MSR) Monitor Event Counter Position */
#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /**< (CMCC_MSR) Monitor Event Counter Mask */
#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
#define CMCC_MSR_Msk _U_(0xFFFFFFFF) /**< (CMCC_MSR) Register Mask */
/** \brief CMCC register offsets definitions */
#define CMCC_TYPE_REG_OFST (0x00) /**< (CMCC_TYPE) Cache Type Register Offset */
#define CMCC_CFG_REG_OFST (0x04) /**< (CMCC_CFG) Cache Configuration Register Offset */
#define CMCC_CTRL_REG_OFST (0x08) /**< (CMCC_CTRL) Cache Control Register Offset */
#define CMCC_SR_REG_OFST (0x0C) /**< (CMCC_SR) Cache Status Register Offset */
#define CMCC_LCKWAY_REG_OFST (0x10) /**< (CMCC_LCKWAY) Cache Lock per Way Register Offset */
#define CMCC_MAINT0_REG_OFST (0x20) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Offset */
#define CMCC_MAINT1_REG_OFST (0x24) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Offset */
#define CMCC_MCFG_REG_OFST (0x28) /**< (CMCC_MCFG) Cache Monitor Configuration Register Offset */
#define CMCC_MEN_REG_OFST (0x2C) /**< (CMCC_MEN) Cache Monitor Enable Register Offset */
#define CMCC_MCTRL_REG_OFST (0x30) /**< (CMCC_MCTRL) Cache Monitor Control Register Offset */
#define CMCC_MSR_REG_OFST (0x34) /**< (CMCC_MSR) Cache Monitor Status Register Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief CMCC register API structure */
typedef struct
{ /* Cortex M Cache Controller */
__I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */
__IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */
__O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */
__I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */
__IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */
__I uint8_t Reserved1[0x0C];
__O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
__O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
__IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
__IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
__O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */
__I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */
} cmcc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_CMCC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/dac.h
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/**
* \brief Component description for DAC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_DAC_COMPONENT_H_
#define _SAMD51_DAC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR DAC */
/* ************************************************************************** */
/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< (DAC_CTRLA) Control A Reset Value */
#define DAC_CTRLA_SWRST_Pos _U_(0) /**< (DAC_CTRLA) Software Reset Position */
#define DAC_CTRLA_SWRST_Msk (_U_(0x1) << DAC_CTRLA_SWRST_Pos) /**< (DAC_CTRLA) Software Reset Mask */
#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & ((value) << DAC_CTRLA_SWRST_Pos))
#define DAC_CTRLA_ENABLE_Pos _U_(1) /**< (DAC_CTRLA) Enable DAC Controller Position */
#define DAC_CTRLA_ENABLE_Msk (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) /**< (DAC_CTRLA) Enable DAC Controller Mask */
#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & ((value) << DAC_CTRLA_ENABLE_Pos))
#define DAC_CTRLA_Msk _U_(0x03) /**< (DAC_CTRLA) Register Mask */
/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< (DAC_CTRLB) Control B Reset Value */
#define DAC_CTRLB_DIFF_Pos _U_(0) /**< (DAC_CTRLB) Differential mode enable Position */
#define DAC_CTRLB_DIFF_Msk (_U_(0x1) << DAC_CTRLB_DIFF_Pos) /**< (DAC_CTRLB) Differential mode enable Mask */
#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & ((value) << DAC_CTRLB_DIFF_Pos))
#define DAC_CTRLB_REFSEL_Pos _U_(1) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Position */
#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Mask */
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< (DAC_CTRLB) External reference unbuffered */
#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< (DAC_CTRLB) Analog supply */
#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< (DAC_CTRLB) External reference buffered */
#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< (DAC_CTRLB) Internal bandgap reference */
#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference unbuffered Position */
#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Analog supply Position */
#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference buffered Position */
#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Internal bandgap reference Position */
#define DAC_CTRLB_Msk _U_(0x07) /**< (DAC_CTRLB) Register Mask */
/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< (DAC_EVCTRL) Event Control Reset Value */
#define DAC_EVCTRL_STARTEI0_Pos _U_(0) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */
#define DAC_EVCTRL_STARTEI0_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */
#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & ((value) << DAC_EVCTRL_STARTEI0_Pos))
#define DAC_EVCTRL_STARTEI1_Pos _U_(1) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */
#define DAC_EVCTRL_STARTEI1_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */
#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & ((value) << DAC_EVCTRL_STARTEI1_Pos))
#define DAC_EVCTRL_EMPTYEO0_Pos _U_(2) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */
#define DAC_EVCTRL_EMPTYEO0_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */
#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & ((value) << DAC_EVCTRL_EMPTYEO0_Pos))
#define DAC_EVCTRL_EMPTYEO1_Pos _U_(3) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */
#define DAC_EVCTRL_EMPTYEO1_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */
#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & ((value) << DAC_EVCTRL_EMPTYEO1_Pos))
#define DAC_EVCTRL_INVEI0_Pos _U_(4) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */
#define DAC_EVCTRL_INVEI0_Msk (_U_(0x1) << DAC_EVCTRL_INVEI0_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */
#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & ((value) << DAC_EVCTRL_INVEI0_Pos))
#define DAC_EVCTRL_INVEI1_Pos _U_(5) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */
#define DAC_EVCTRL_INVEI1_Msk (_U_(0x1) << DAC_EVCTRL_INVEI1_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */
#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & ((value) << DAC_EVCTRL_INVEI1_Pos))
#define DAC_EVCTRL_RESRDYEO0_Pos _U_(6) /**< (DAC_EVCTRL) Result Ready Event Output 0 Position */
#define DAC_EVCTRL_RESRDYEO0_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 0 Mask */
#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & ((value) << DAC_EVCTRL_RESRDYEO0_Pos))
#define DAC_EVCTRL_RESRDYEO1_Pos _U_(7) /**< (DAC_EVCTRL) Result Ready Event Output 1 Position */
#define DAC_EVCTRL_RESRDYEO1_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 1 Mask */
#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & ((value) << DAC_EVCTRL_RESRDYEO1_Pos))
#define DAC_EVCTRL_Msk _U_(0xFF) /**< (DAC_EVCTRL) Register Mask */
#define DAC_EVCTRL_STARTEI_Pos _U_(0) /**< (DAC_EVCTRL Position) Start Conversion Event Input DAC x */
#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) /**< (DAC_EVCTRL Mask) STARTEI */
#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
#define DAC_EVCTRL_EMPTYEO_Pos _U_(2) /**< (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */
#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /**< (DAC_EVCTRL Mask) EMPTYEO */
#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
#define DAC_EVCTRL_INVEI_Pos _U_(4) /**< (DAC_EVCTRL Position) Enable Invertion of DAC x input event */
#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) /**< (DAC_EVCTRL Mask) INVEI */
#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
#define DAC_EVCTRL_RESRDYEO_Pos _U_(6) /**< (DAC_EVCTRL Position) Result Ready Event Output x */
#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /**< (DAC_EVCTRL Mask) RESRDYEO */
#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< (DAC_INTENCLR) Interrupt Enable Clear Reset Value */
#define DAC_INTENCLR_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */
#define DAC_INTENCLR_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */
#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & ((value) << DAC_INTENCLR_UNDERRUN0_Pos))
#define DAC_INTENCLR_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */
#define DAC_INTENCLR_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */
#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & ((value) << DAC_INTENCLR_UNDERRUN1_Pos))
#define DAC_INTENCLR_EMPTY0_Pos _U_(2) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */
#define DAC_INTENCLR_EMPTY0_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */
#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & ((value) << DAC_INTENCLR_EMPTY0_Pos))
#define DAC_INTENCLR_EMPTY1_Pos _U_(3) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */
#define DAC_INTENCLR_EMPTY1_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */
#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & ((value) << DAC_INTENCLR_EMPTY1_Pos))
#define DAC_INTENCLR_RESRDY0_Pos _U_(4) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */
#define DAC_INTENCLR_RESRDY0_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */
#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & ((value) << DAC_INTENCLR_RESRDY0_Pos))
#define DAC_INTENCLR_RESRDY1_Pos _U_(5) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */
#define DAC_INTENCLR_RESRDY1_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */
#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & ((value) << DAC_INTENCLR_RESRDY1_Pos))
#define DAC_INTENCLR_OVERRUN0_Pos _U_(6) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */
#define DAC_INTENCLR_OVERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */
#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & ((value) << DAC_INTENCLR_OVERRUN0_Pos))
#define DAC_INTENCLR_OVERRUN1_Pos _U_(7) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */
#define DAC_INTENCLR_OVERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */
#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & ((value) << DAC_INTENCLR_OVERRUN1_Pos))
#define DAC_INTENCLR_Msk _U_(0xFF) /**< (DAC_INTENCLR) Register Mask */
#define DAC_INTENCLR_UNDERRUN_Pos _U_(0) /**< (DAC_INTENCLR Position) Underrun x Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /**< (DAC_INTENCLR Mask) UNDERRUN */
#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
#define DAC_INTENCLR_EMPTY_Pos _U_(2) /**< (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) /**< (DAC_INTENCLR Mask) EMPTY */
#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
#define DAC_INTENCLR_RESRDY_Pos _U_(4) /**< (DAC_INTENCLR Position) Result x Ready Interrupt Enable */
#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) /**< (DAC_INTENCLR Mask) RESRDY */
#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
#define DAC_INTENCLR_OVERRUN_Pos _U_(6) /**< (DAC_INTENCLR Position) Overrun x Interrupt Enable */
#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /**< (DAC_INTENCLR Mask) OVERRUN */
#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< (DAC_INTENSET) Interrupt Enable Set Reset Value */
#define DAC_INTENSET_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Position */
#define DAC_INTENSET_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */
#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & ((value) << DAC_INTENSET_UNDERRUN0_Pos))
#define DAC_INTENSET_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Position */
#define DAC_INTENSET_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */
#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & ((value) << DAC_INTENSET_UNDERRUN1_Pos))
#define DAC_INTENSET_EMPTY0_Pos _U_(2) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */
#define DAC_INTENSET_EMPTY0_Msk (_U_(0x1) << DAC_INTENSET_EMPTY0_Pos) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */
#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & ((value) << DAC_INTENSET_EMPTY0_Pos))
#define DAC_INTENSET_EMPTY1_Pos _U_(3) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */
#define DAC_INTENSET_EMPTY1_Msk (_U_(0x1) << DAC_INTENSET_EMPTY1_Pos) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */
#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & ((value) << DAC_INTENSET_EMPTY1_Pos))
#define DAC_INTENSET_RESRDY0_Pos _U_(4) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */
#define DAC_INTENSET_RESRDY0_Msk (_U_(0x1) << DAC_INTENSET_RESRDY0_Pos) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */
#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & ((value) << DAC_INTENSET_RESRDY0_Pos))
#define DAC_INTENSET_RESRDY1_Pos _U_(5) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */
#define DAC_INTENSET_RESRDY1_Msk (_U_(0x1) << DAC_INTENSET_RESRDY1_Pos) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */
#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & ((value) << DAC_INTENSET_RESRDY1_Pos))
#define DAC_INTENSET_OVERRUN0_Pos _U_(6) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Position */
#define DAC_INTENSET_OVERRUN0_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */
#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & ((value) << DAC_INTENSET_OVERRUN0_Pos))
#define DAC_INTENSET_OVERRUN1_Pos _U_(7) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Position */
#define DAC_INTENSET_OVERRUN1_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */
#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & ((value) << DAC_INTENSET_OVERRUN1_Pos))
#define DAC_INTENSET_Msk _U_(0xFF) /**< (DAC_INTENSET) Register Mask */
#define DAC_INTENSET_UNDERRUN_Pos _U_(0) /**< (DAC_INTENSET Position) Underrun x Interrupt Enable */
#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /**< (DAC_INTENSET Mask) UNDERRUN */
#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
#define DAC_INTENSET_EMPTY_Pos _U_(2) /**< (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) /**< (DAC_INTENSET Mask) EMPTY */
#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
#define DAC_INTENSET_RESRDY_Pos _U_(4) /**< (DAC_INTENSET Position) Result x Ready Interrupt Enable */
#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) /**< (DAC_INTENSET Mask) RESRDY */
#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
#define DAC_INTENSET_OVERRUN_Pos _U_(6) /**< (DAC_INTENSET Position) Overrun x Interrupt Enable */
#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) /**< (DAC_INTENSET Mask) OVERRUN */
#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define DAC_INTFLAG_UNDERRUN0_Pos _U_(0) /**< (DAC_INTFLAG) Result 0 Underrun Position */
#define DAC_INTFLAG_UNDERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Underrun Mask */
#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & ((value) << DAC_INTFLAG_UNDERRUN0_Pos))
#define DAC_INTFLAG_UNDERRUN1_Pos _U_(1) /**< (DAC_INTFLAG) Result 1 Underrun Position */
#define DAC_INTFLAG_UNDERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Underrun Mask */
#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & ((value) << DAC_INTFLAG_UNDERRUN1_Pos))
#define DAC_INTFLAG_EMPTY0_Pos _U_(2) /**< (DAC_INTFLAG) Data Buffer 0 Empty Position */
#define DAC_INTFLAG_EMPTY0_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /**< (DAC_INTFLAG) Data Buffer 0 Empty Mask */
#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & ((value) << DAC_INTFLAG_EMPTY0_Pos))
#define DAC_INTFLAG_EMPTY1_Pos _U_(3) /**< (DAC_INTFLAG) Data Buffer 1 Empty Position */
#define DAC_INTFLAG_EMPTY1_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /**< (DAC_INTFLAG) Data Buffer 1 Empty Mask */
#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & ((value) << DAC_INTFLAG_EMPTY1_Pos))
#define DAC_INTFLAG_RESRDY0_Pos _U_(4) /**< (DAC_INTFLAG) Result 0 Ready Position */
#define DAC_INTFLAG_RESRDY0_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /**< (DAC_INTFLAG) Result 0 Ready Mask */
#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & ((value) << DAC_INTFLAG_RESRDY0_Pos))
#define DAC_INTFLAG_RESRDY1_Pos _U_(5) /**< (DAC_INTFLAG) Result 1 Ready Position */
#define DAC_INTFLAG_RESRDY1_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /**< (DAC_INTFLAG) Result 1 Ready Mask */
#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & ((value) << DAC_INTFLAG_RESRDY1_Pos))
#define DAC_INTFLAG_OVERRUN0_Pos _U_(6) /**< (DAC_INTFLAG) Result 0 Overrun Position */
#define DAC_INTFLAG_OVERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Overrun Mask */
#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & ((value) << DAC_INTFLAG_OVERRUN0_Pos))
#define DAC_INTFLAG_OVERRUN1_Pos _U_(7) /**< (DAC_INTFLAG) Result 1 Overrun Position */
#define DAC_INTFLAG_OVERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Overrun Mask */
#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & ((value) << DAC_INTFLAG_OVERRUN1_Pos))
#define DAC_INTFLAG_Msk _U_(0xFF) /**< (DAC_INTFLAG) Register Mask */
#define DAC_INTFLAG_UNDERRUN_Pos _U_(0) /**< (DAC_INTFLAG Position) Result x Underrun */
#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /**< (DAC_INTFLAG Mask) UNDERRUN */
#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
#define DAC_INTFLAG_EMPTY_Pos _U_(2) /**< (DAC_INTFLAG Position) Data Buffer x Empty */
#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) /**< (DAC_INTFLAG Mask) EMPTY */
#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
#define DAC_INTFLAG_RESRDY_Pos _U_(4) /**< (DAC_INTFLAG Position) Result x Ready */
#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) /**< (DAC_INTFLAG Mask) RESRDY */
#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
#define DAC_INTFLAG_OVERRUN_Pos _U_(6) /**< (DAC_INTFLAG Position) Result x Overrun */
#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /**< (DAC_INTFLAG Mask) OVERRUN */
#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */
#define DAC_STATUS_RESETVALUE _U_(0x00) /**< (DAC_STATUS) Status Reset Value */
#define DAC_STATUS_READY0_Pos _U_(0) /**< (DAC_STATUS) DAC 0 Startup Ready Position */
#define DAC_STATUS_READY0_Msk (_U_(0x1) << DAC_STATUS_READY0_Pos) /**< (DAC_STATUS) DAC 0 Startup Ready Mask */
#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & ((value) << DAC_STATUS_READY0_Pos))
#define DAC_STATUS_READY1_Pos _U_(1) /**< (DAC_STATUS) DAC 1 Startup Ready Position */
#define DAC_STATUS_READY1_Msk (_U_(0x1) << DAC_STATUS_READY1_Pos) /**< (DAC_STATUS) DAC 1 Startup Ready Mask */
#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & ((value) << DAC_STATUS_READY1_Pos))
#define DAC_STATUS_EOC0_Pos _U_(2) /**< (DAC_STATUS) DAC 0 End of Conversion Position */
#define DAC_STATUS_EOC0_Msk (_U_(0x1) << DAC_STATUS_EOC0_Pos) /**< (DAC_STATUS) DAC 0 End of Conversion Mask */
#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & ((value) << DAC_STATUS_EOC0_Pos))
#define DAC_STATUS_EOC1_Pos _U_(3) /**< (DAC_STATUS) DAC 1 End of Conversion Position */
#define DAC_STATUS_EOC1_Msk (_U_(0x1) << DAC_STATUS_EOC1_Pos) /**< (DAC_STATUS) DAC 1 End of Conversion Mask */
#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & ((value) << DAC_STATUS_EOC1_Pos))
#define DAC_STATUS_Msk _U_(0x0F) /**< (DAC_STATUS) Register Mask */
#define DAC_STATUS_READY_Pos _U_(0) /**< (DAC_STATUS Position) DAC x Startup Ready */
#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) /**< (DAC_STATUS Mask) READY */
#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
#define DAC_STATUS_EOC_Pos _U_(2) /**< (DAC_STATUS Position) DAC x End of Conversion */
#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) /**< (DAC_STATUS Mask) EOC */
#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */
#define DAC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (DAC_SYNCBUSY) Synchronization Busy Reset Value */
#define DAC_SYNCBUSY_SWRST_Pos _U_(0) /**< (DAC_SYNCBUSY) Software Reset Position */
#define DAC_SYNCBUSY_SWRST_Msk (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /**< (DAC_SYNCBUSY) Software Reset Mask */
#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & ((value) << DAC_SYNCBUSY_SWRST_Pos))
#define DAC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (DAC_SYNCBUSY) DAC Enable Status Position */
#define DAC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /**< (DAC_SYNCBUSY) DAC Enable Status Mask */
#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & ((value) << DAC_SYNCBUSY_ENABLE_Pos))
#define DAC_SYNCBUSY_DATA0_Pos _U_(2) /**< (DAC_SYNCBUSY) Data DAC 0 Position */
#define DAC_SYNCBUSY_DATA0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /**< (DAC_SYNCBUSY) Data DAC 0 Mask */
#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & ((value) << DAC_SYNCBUSY_DATA0_Pos))
#define DAC_SYNCBUSY_DATA1_Pos _U_(3) /**< (DAC_SYNCBUSY) Data DAC 1 Position */
#define DAC_SYNCBUSY_DATA1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /**< (DAC_SYNCBUSY) Data DAC 1 Mask */
#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & ((value) << DAC_SYNCBUSY_DATA1_Pos))
#define DAC_SYNCBUSY_DATABUF0_Pos _U_(4) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Position */
#define DAC_SYNCBUSY_DATABUF0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */
#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & ((value) << DAC_SYNCBUSY_DATABUF0_Pos))
#define DAC_SYNCBUSY_DATABUF1_Pos _U_(5) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Position */
#define DAC_SYNCBUSY_DATABUF1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */
#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & ((value) << DAC_SYNCBUSY_DATABUF1_Pos))
#define DAC_SYNCBUSY_Msk _U_(0x0000003F) /**< (DAC_SYNCBUSY) Register Mask */
#define DAC_SYNCBUSY_DATA_Pos _U_(2) /**< (DAC_SYNCBUSY Position) Data DAC x */
#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) /**< (DAC_SYNCBUSY Mask) DATA */
#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
#define DAC_SYNCBUSY_DATABUF_Pos _U_(4) /**< (DAC_SYNCBUSY Position) Data Buffer DAC x */
#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /**< (DAC_SYNCBUSY Mask) DATABUF */
#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
#define DAC_DACCTRL_RESETVALUE _U_(0x00) /**< (DAC_DACCTRL) DAC n Control Reset Value */
#define DAC_DACCTRL_LEFTADJ_Pos _U_(0) /**< (DAC_DACCTRL) Left Adjusted Data Position */
#define DAC_DACCTRL_LEFTADJ_Msk (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /**< (DAC_DACCTRL) Left Adjusted Data Mask */
#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & ((value) << DAC_DACCTRL_LEFTADJ_Pos))
#define DAC_DACCTRL_ENABLE_Pos _U_(1) /**< (DAC_DACCTRL) Enable DAC0 Position */
#define DAC_DACCTRL_ENABLE_Msk (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) /**< (DAC_DACCTRL) Enable DAC0 Mask */
#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & ((value) << DAC_DACCTRL_ENABLE_Pos))
#define DAC_DACCTRL_CCTRL_Pos _U_(2) /**< (DAC_DACCTRL) Current Control Position */
#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) Current Control Mask */
#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< (DAC_DACCTRL) 100kSPS */
#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< (DAC_DACCTRL) 500kSPS */
#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< (DAC_DACCTRL) 1MSPS */
#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 100kSPS Position */
#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 500kSPS Position */
#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 1MSPS Position */
#define DAC_DACCTRL_FEXT_Pos _U_(5) /**< (DAC_DACCTRL) Standalone Filter Position */
#define DAC_DACCTRL_FEXT_Msk (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) /**< (DAC_DACCTRL) Standalone Filter Mask */
#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & ((value) << DAC_DACCTRL_FEXT_Pos))
#define DAC_DACCTRL_RUNSTDBY_Pos _U_(6) /**< (DAC_DACCTRL) Run in Standby Position */
#define DAC_DACCTRL_RUNSTDBY_Msk (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /**< (DAC_DACCTRL) Run in Standby Mask */
#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & ((value) << DAC_DACCTRL_RUNSTDBY_Pos))
#define DAC_DACCTRL_DITHER_Pos _U_(7) /**< (DAC_DACCTRL) Dithering Mode Position */
#define DAC_DACCTRL_DITHER_Msk (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) /**< (DAC_DACCTRL) Dithering Mode Mask */
#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & ((value) << DAC_DACCTRL_DITHER_Pos))
#define DAC_DACCTRL_REFRESH_Pos _U_(8) /**< (DAC_DACCTRL) Refresh period Position */
#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh period Mask */
#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _U_(0x0) /**< (DAC_DACCTRL) Do not Refresh */
#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _U_(0x1) /**< (DAC_DACCTRL) Refresh every 30 us */
#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _U_(0x2) /**< (DAC_DACCTRL) Refresh every 60 us */
#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _U_(0x3) /**< (DAC_DACCTRL) Refresh every 90 us */
#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _U_(0x4) /**< (DAC_DACCTRL) Refresh every 120 us */
#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _U_(0x5) /**< (DAC_DACCTRL) Refresh every 150 us */
#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _U_(0x6) /**< (DAC_DACCTRL) Refresh every 180 us */
#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _U_(0x7) /**< (DAC_DACCTRL) Refresh every 210 us */
#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _U_(0x8) /**< (DAC_DACCTRL) Refresh every 240 us */
#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _U_(0x9) /**< (DAC_DACCTRL) Refresh every 270 us */
#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _U_(0xA) /**< (DAC_DACCTRL) Refresh every 300 us */
#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _U_(0xB) /**< (DAC_DACCTRL) Refresh every 330 us */
#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _U_(0xC) /**< (DAC_DACCTRL) Refresh every 360 us */
#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _U_(0xD) /**< (DAC_DACCTRL) Refresh every 390 us */
#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _U_(0xE) /**< (DAC_DACCTRL) Refresh every 420 us */
#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _U_(0xF) /**< (DAC_DACCTRL) Refresh every 450 us */
#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Do not Refresh Position */
#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 30 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 60 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 90 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 120 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 150 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 180 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 210 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 240 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 270 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 300 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 330 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 360 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 390 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 420 us Position */
#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 450 us Position */
#define DAC_DACCTRL_OSR_Pos _U_(13) /**< (DAC_DACCTRL) Sampling Rate Position */
#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) Sampling Rate Mask */
#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
#define DAC_DACCTRL_OSR_OSR_1_Val _U_(0x0) /**< (DAC_DACCTRL) No Over Sampling */
#define DAC_DACCTRL_OSR_OSR_2_Val _U_(0x1) /**< (DAC_DACCTRL) 2x Over Sampling Ratio */
#define DAC_DACCTRL_OSR_OSR_4_Val _U_(0x2) /**< (DAC_DACCTRL) 4x Over Sampling Ratio */
#define DAC_DACCTRL_OSR_OSR_8_Val _U_(0x3) /**< (DAC_DACCTRL) 8x Over Sampling Ratio */
#define DAC_DACCTRL_OSR_OSR_16_Val _U_(0x4) /**< (DAC_DACCTRL) 16x Over Sampling Ratio */
#define DAC_DACCTRL_OSR_OSR_32_Val _U_(0x5) /**< (DAC_DACCTRL) 32x Over Sampling Ratio */
#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) No Over Sampling Position */
#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 2x Over Sampling Ratio Position */
#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 4x Over Sampling Ratio Position */
#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 8x Over Sampling Ratio Position */
#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 16x Over Sampling Ratio Position */
#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 32x Over Sampling Ratio Position */
#define DAC_DACCTRL_Msk _U_(0xEFEF) /**< (DAC_DACCTRL) Register Mask */
/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
#define DAC_DATA_RESETVALUE _U_(0x00) /**< (DAC_DATA) DAC n Data Reset Value */
#define DAC_DATA_DATA_Pos _U_(0) /**< (DAC_DATA) DAC0 Data Position */
#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) /**< (DAC_DATA) DAC0 Data Mask */
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
#define DAC_DATA_Msk _U_(0xFFFF) /**< (DAC_DATA) Register Mask */
/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
#define DAC_DATABUF_RESETVALUE _U_(0x00) /**< (DAC_DATABUF) DAC n Data Buffer Reset Value */
#define DAC_DATABUF_DATABUF_Pos _U_(0) /**< (DAC_DATABUF) DAC0 Data Buffer Position */
#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /**< (DAC_DATABUF) DAC0 Data Buffer Mask */
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
#define DAC_DATABUF_Msk _U_(0xFFFF) /**< (DAC_DATABUF) Register Mask */
/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< (DAC_DBGCTRL) Debug Control Reset Value */
#define DAC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (DAC_DBGCTRL) Debug Run Position */
#define DAC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /**< (DAC_DBGCTRL) Debug Run Mask */
#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & ((value) << DAC_DBGCTRL_DBGRUN_Pos))
#define DAC_DBGCTRL_Msk _U_(0x01) /**< (DAC_DBGCTRL) Register Mask */
/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */
#define DAC_RESULT_RESETVALUE _U_(0x00) /**< (DAC_RESULT) Filter Result Reset Value */
#define DAC_RESULT_RESULT_Pos _U_(0) /**< (DAC_RESULT) Filter Result Position */
#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) /**< (DAC_RESULT) Filter Result Mask */
#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
#define DAC_RESULT_Msk _U_(0xFFFF) /**< (DAC_RESULT) Register Mask */
/** \brief DAC register offsets definitions */
#define DAC_CTRLA_REG_OFST (0x00) /**< (DAC_CTRLA) Control A Offset */
#define DAC_CTRLB_REG_OFST (0x01) /**< (DAC_CTRLB) Control B Offset */
#define DAC_EVCTRL_REG_OFST (0x02) /**< (DAC_EVCTRL) Event Control Offset */
#define DAC_INTENCLR_REG_OFST (0x04) /**< (DAC_INTENCLR) Interrupt Enable Clear Offset */
#define DAC_INTENSET_REG_OFST (0x05) /**< (DAC_INTENSET) Interrupt Enable Set Offset */
#define DAC_INTFLAG_REG_OFST (0x06) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define DAC_STATUS_REG_OFST (0x07) /**< (DAC_STATUS) Status Offset */
#define DAC_SYNCBUSY_REG_OFST (0x08) /**< (DAC_SYNCBUSY) Synchronization Busy Offset */
#define DAC_DACCTRL_REG_OFST (0x0C) /**< (DAC_DACCTRL) DAC n Control Offset */
#define DAC_DATA_REG_OFST (0x10) /**< (DAC_DATA) DAC n Data Offset */
#define DAC_DATABUF_REG_OFST (0x14) /**< (DAC_DATABUF) DAC n Data Buffer Offset */
#define DAC_DBGCTRL_REG_OFST (0x18) /**< (DAC_DBGCTRL) Debug Control Offset */
#define DAC_RESULT_REG_OFST (0x1C) /**< (DAC_RESULT) Filter Result Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief DAC register API structure */
typedef struct
{ /* Digital-to-Analog Converter */
__IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */
__IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */
__I uint8_t Reserved1[0x01];
__IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */
__I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */
__IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */
__O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */
__O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */
__IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */
__I uint8_t Reserved2[0x03];
__I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */
} dac_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_DAC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/dmac.h
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arch/arm/SAMD51/SAMD51A/mcu/inc/component/dsu.h
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/**
* \brief Component description for DSU
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_DSU_COMPONENT_H_
#define _SAMD51_DSU_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR DSU */
/* ************************************************************************** */
/* -------- DSU_CTRL : (DSU Offset: 0x00) ( /W 8) Control -------- */
#define DSU_CTRL_RESETVALUE _U_(0x00) /**< (DSU_CTRL) Control Reset Value */
#define DSU_CTRL_SWRST_Pos _U_(0) /**< (DSU_CTRL) Software Reset Position */
#define DSU_CTRL_SWRST_Msk (_U_(0x1) << DSU_CTRL_SWRST_Pos) /**< (DSU_CTRL) Software Reset Mask */
#define DSU_CTRL_SWRST(value) (DSU_CTRL_SWRST_Msk & ((value) << DSU_CTRL_SWRST_Pos))
#define DSU_CTRL_CRC_Pos _U_(2) /**< (DSU_CTRL) 32-bit Cyclic Redundancy Code Position */
#define DSU_CTRL_CRC_Msk (_U_(0x1) << DSU_CTRL_CRC_Pos) /**< (DSU_CTRL) 32-bit Cyclic Redundancy Code Mask */
#define DSU_CTRL_CRC(value) (DSU_CTRL_CRC_Msk & ((value) << DSU_CTRL_CRC_Pos))
#define DSU_CTRL_MBIST_Pos _U_(3) /**< (DSU_CTRL) Memory built-in self-test Position */
#define DSU_CTRL_MBIST_Msk (_U_(0x1) << DSU_CTRL_MBIST_Pos) /**< (DSU_CTRL) Memory built-in self-test Mask */
#define DSU_CTRL_MBIST(value) (DSU_CTRL_MBIST_Msk & ((value) << DSU_CTRL_MBIST_Pos))
#define DSU_CTRL_CE_Pos _U_(4) /**< (DSU_CTRL) Chip-Erase Position */
#define DSU_CTRL_CE_Msk (_U_(0x1) << DSU_CTRL_CE_Pos) /**< (DSU_CTRL) Chip-Erase Mask */
#define DSU_CTRL_CE(value) (DSU_CTRL_CE_Msk & ((value) << DSU_CTRL_CE_Pos))
#define DSU_CTRL_Msk _U_(0x1D) /**< (DSU_CTRL) Register Mask */
/* -------- DSU_STATUSA : (DSU Offset: 0x01) (R/W 8) Status A -------- */
#define DSU_STATUSA_RESETVALUE _U_(0x00) /**< (DSU_STATUSA) Status A Reset Value */
#define DSU_STATUSA_DONE_Pos _U_(0) /**< (DSU_STATUSA) Done Position */
#define DSU_STATUSA_DONE_Msk (_U_(0x1) << DSU_STATUSA_DONE_Pos) /**< (DSU_STATUSA) Done Mask */
#define DSU_STATUSA_DONE(value) (DSU_STATUSA_DONE_Msk & ((value) << DSU_STATUSA_DONE_Pos))
#define DSU_STATUSA_CRSTEXT_Pos _U_(1) /**< (DSU_STATUSA) CPU Reset Phase Extension Position */
#define DSU_STATUSA_CRSTEXT_Msk (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) /**< (DSU_STATUSA) CPU Reset Phase Extension Mask */
#define DSU_STATUSA_CRSTEXT(value) (DSU_STATUSA_CRSTEXT_Msk & ((value) << DSU_STATUSA_CRSTEXT_Pos))
#define DSU_STATUSA_BERR_Pos _U_(2) /**< (DSU_STATUSA) Bus Error Position */
#define DSU_STATUSA_BERR_Msk (_U_(0x1) << DSU_STATUSA_BERR_Pos) /**< (DSU_STATUSA) Bus Error Mask */
#define DSU_STATUSA_BERR(value) (DSU_STATUSA_BERR_Msk & ((value) << DSU_STATUSA_BERR_Pos))
#define DSU_STATUSA_FAIL_Pos _U_(3) /**< (DSU_STATUSA) Failure Position */
#define DSU_STATUSA_FAIL_Msk (_U_(0x1) << DSU_STATUSA_FAIL_Pos) /**< (DSU_STATUSA) Failure Mask */
#define DSU_STATUSA_FAIL(value) (DSU_STATUSA_FAIL_Msk & ((value) << DSU_STATUSA_FAIL_Pos))
#define DSU_STATUSA_PERR_Pos _U_(4) /**< (DSU_STATUSA) Protection Error Position */
#define DSU_STATUSA_PERR_Msk (_U_(0x1) << DSU_STATUSA_PERR_Pos) /**< (DSU_STATUSA) Protection Error Mask */
#define DSU_STATUSA_PERR(value) (DSU_STATUSA_PERR_Msk & ((value) << DSU_STATUSA_PERR_Pos))
#define DSU_STATUSA_Msk _U_(0x1F) /**< (DSU_STATUSA) Register Mask */
/* -------- DSU_STATUSB : (DSU Offset: 0x02) ( R/ 8) Status B -------- */
#define DSU_STATUSB_RESETVALUE _U_(0x00) /**< (DSU_STATUSB) Status B Reset Value */
#define DSU_STATUSB_PROT_Pos _U_(0) /**< (DSU_STATUSB) Protected Position */
#define DSU_STATUSB_PROT_Msk (_U_(0x1) << DSU_STATUSB_PROT_Pos) /**< (DSU_STATUSB) Protected Mask */
#define DSU_STATUSB_PROT(value) (DSU_STATUSB_PROT_Msk & ((value) << DSU_STATUSB_PROT_Pos))
#define DSU_STATUSB_DBGPRES_Pos _U_(1) /**< (DSU_STATUSB) Debugger Present Position */
#define DSU_STATUSB_DBGPRES_Msk (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) /**< (DSU_STATUSB) Debugger Present Mask */
#define DSU_STATUSB_DBGPRES(value) (DSU_STATUSB_DBGPRES_Msk & ((value) << DSU_STATUSB_DBGPRES_Pos))
#define DSU_STATUSB_DCCD0_Pos _U_(2) /**< (DSU_STATUSB) Debug Communication Channel 0 Dirty Position */
#define DSU_STATUSB_DCCD0_Msk (_U_(0x1) << DSU_STATUSB_DCCD0_Pos) /**< (DSU_STATUSB) Debug Communication Channel 0 Dirty Mask */
#define DSU_STATUSB_DCCD0(value) (DSU_STATUSB_DCCD0_Msk & ((value) << DSU_STATUSB_DCCD0_Pos))
#define DSU_STATUSB_DCCD1_Pos _U_(3) /**< (DSU_STATUSB) Debug Communication Channel 1 Dirty Position */
#define DSU_STATUSB_DCCD1_Msk (_U_(0x1) << DSU_STATUSB_DCCD1_Pos) /**< (DSU_STATUSB) Debug Communication Channel 1 Dirty Mask */
#define DSU_STATUSB_DCCD1(value) (DSU_STATUSB_DCCD1_Msk & ((value) << DSU_STATUSB_DCCD1_Pos))
#define DSU_STATUSB_HPE_Pos _U_(4) /**< (DSU_STATUSB) Hot-Plugging Enable Position */
#define DSU_STATUSB_HPE_Msk (_U_(0x1) << DSU_STATUSB_HPE_Pos) /**< (DSU_STATUSB) Hot-Plugging Enable Mask */
#define DSU_STATUSB_HPE(value) (DSU_STATUSB_HPE_Msk & ((value) << DSU_STATUSB_HPE_Pos))
#define DSU_STATUSB_CELCK_Pos _U_(5) /**< (DSU_STATUSB) Chip Erase Locked Position */
#define DSU_STATUSB_CELCK_Msk (_U_(0x1) << DSU_STATUSB_CELCK_Pos) /**< (DSU_STATUSB) Chip Erase Locked Mask */
#define DSU_STATUSB_CELCK(value) (DSU_STATUSB_CELCK_Msk & ((value) << DSU_STATUSB_CELCK_Pos))
#define DSU_STATUSB_Msk _U_(0x3F) /**< (DSU_STATUSB) Register Mask */
#define DSU_STATUSB_DCCD_Pos _U_(2) /**< (DSU_STATUSB Position) Debug Communication Channel x Dirty */
#define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) /**< (DSU_STATUSB Mask) DCCD */
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
/* -------- DSU_ADDR : (DSU Offset: 0x04) (R/W 32) Address -------- */
#define DSU_ADDR_RESETVALUE _U_(0x00) /**< (DSU_ADDR) Address Reset Value */
#define DSU_ADDR_AMOD_Pos _U_(0) /**< (DSU_ADDR) Access Mode Position */
#define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos) /**< (DSU_ADDR) Access Mode Mask */
#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
#define DSU_ADDR_ADDR_Pos _U_(2) /**< (DSU_ADDR) Address Position */
#define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) /**< (DSU_ADDR) Address Mask */
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
#define DSU_ADDR_Msk _U_(0xFFFFFFFF) /**< (DSU_ADDR) Register Mask */
/* -------- DSU_LENGTH : (DSU Offset: 0x08) (R/W 32) Length -------- */
#define DSU_LENGTH_RESETVALUE _U_(0x00) /**< (DSU_LENGTH) Length Reset Value */
#define DSU_LENGTH_LENGTH_Pos _U_(2) /**< (DSU_LENGTH) Length Position */
#define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) /**< (DSU_LENGTH) Length Mask */
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
#define DSU_LENGTH_Msk _U_(0xFFFFFFFC) /**< (DSU_LENGTH) Register Mask */
/* -------- DSU_DATA : (DSU Offset: 0x0C) (R/W 32) Data -------- */
#define DSU_DATA_RESETVALUE _U_(0x00) /**< (DSU_DATA) Data Reset Value */
#define DSU_DATA_DATA_Pos _U_(0) /**< (DSU_DATA) Data Position */
#define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) /**< (DSU_DATA) Data Mask */
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
#define DSU_DATA_Msk _U_(0xFFFFFFFF) /**< (DSU_DATA) Register Mask */
/* -------- DSU_DCC : (DSU Offset: 0x10) (R/W 32) Debug Communication Channel n -------- */
#define DSU_DCC_RESETVALUE _U_(0x00) /**< (DSU_DCC) Debug Communication Channel n Reset Value */
#define DSU_DCC_DATA_Pos _U_(0) /**< (DSU_DCC) Data Position */
#define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) /**< (DSU_DCC) Data Mask */
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
#define DSU_DCC_Msk _U_(0xFFFFFFFF) /**< (DSU_DCC) Register Mask */
/* -------- DSU_DID : (DSU Offset: 0x18) ( R/ 32) Device Identification -------- */
#define DSU_DID_RESETVALUE _U_(0x60060200) /**< (DSU_DID) Device Identification Reset Value */
#define DSU_DID_DEVSEL_Pos _U_(0) /**< (DSU_DID) Device Select Position */
#define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) /**< (DSU_DID) Device Select Mask */
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
#define DSU_DID_REVISION_Pos _U_(8) /**< (DSU_DID) Revision Number Position */
#define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) /**< (DSU_DID) Revision Number Mask */
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
#define DSU_DID_DIE_Pos _U_(12) /**< (DSU_DID) Die Number Position */
#define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) /**< (DSU_DID) Die Number Mask */
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
#define DSU_DID_SERIES_Pos _U_(16) /**< (DSU_DID) Series Position */
#define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) /**< (DSU_DID) Series Mask */
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
#define DSU_DID_SERIES_0_Val _U_(0x0) /**< (DSU_DID) Cortex-M0+ processor, basic feature set */
#define DSU_DID_SERIES_1_Val _U_(0x1) /**< (DSU_DID) Cortex-M0+ processor, USB */
#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) /**< (DSU_DID) Cortex-M0+ processor, basic feature set Position */
#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) /**< (DSU_DID) Cortex-M0+ processor, USB Position */
#define DSU_DID_FAMILY_Pos _U_(23) /**< (DSU_DID) Family Position */
#define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) /**< (DSU_DID) Family Mask */
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
#define DSU_DID_FAMILY_0_Val _U_(0x0) /**< (DSU_DID) General purpose microcontroller */
#define DSU_DID_FAMILY_1_Val _U_(0x1) /**< (DSU_DID) PicoPower */
#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) /**< (DSU_DID) General purpose microcontroller Position */
#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) /**< (DSU_DID) PicoPower Position */
#define DSU_DID_PROCESSOR_Pos _U_(28) /**< (DSU_DID) Processor Position */
#define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Processor Mask */
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
#define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1) /**< (DSU_DID) Cortex-M0+ */
#define DSU_DID_PROCESSOR_CM23_Val _U_(0x2) /**< (DSU_DID) Cortex-M23 */
#define DSU_DID_PROCESSOR_CM3_Val _U_(0x3) /**< (DSU_DID) Cortex-M3 */
#define DSU_DID_PROCESSOR_CM4_Val _U_(0x5) /**< (DSU_DID) Cortex-M4 */
#define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6) /**< (DSU_DID) Cortex-M4 with FPU */
#define DSU_DID_PROCESSOR_CM33_Val _U_(0x7) /**< (DSU_DID) Cortex-M33 */
#define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M0+ Position */
#define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M23 Position */
#define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M3 Position */
#define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M4 Position */
#define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M4 with FPU Position */
#define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos) /**< (DSU_DID) Cortex-M33 Position */
#define DSU_DID_Msk _U_(0xFFBFFFFF) /**< (DSU_DID) Register Mask */
/* -------- DSU_CFG : (DSU Offset: 0x1C) (R/W 32) Configuration -------- */
#define DSU_CFG_RESETVALUE _U_(0x02) /**< (DSU_CFG) Configuration Reset Value */
#define DSU_CFG_LQOS_Pos _U_(0) /**< (DSU_CFG) Latency Quality Of Service Position */
#define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos) /**< (DSU_CFG) Latency Quality Of Service Mask */
#define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
#define DSU_CFG_DCCDMALEVEL_Pos _U_(2) /**< (DSU_CFG) DMA Trigger Level Position */
#define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos) /**< (DSU_CFG) DMA Trigger Level Mask */
#define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
#define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0) /**< (DSU_CFG) Trigger rises when DCC is empty */
#define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1) /**< (DSU_CFG) Trigger rises when DCC is full */
#define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos) /**< (DSU_CFG) Trigger rises when DCC is empty Position */
#define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos) /**< (DSU_CFG) Trigger rises when DCC is full Position */
#define DSU_CFG_ETBRAMEN_Pos _U_(4) /**< (DSU_CFG) Trace Control Position */
#define DSU_CFG_ETBRAMEN_Msk (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos) /**< (DSU_CFG) Trace Control Mask */
#define DSU_CFG_ETBRAMEN(value) (DSU_CFG_ETBRAMEN_Msk & ((value) << DSU_CFG_ETBRAMEN_Pos))
#define DSU_CFG_Msk _U_(0x0000001F) /**< (DSU_CFG) Register Mask */
/* -------- DSU_DCFG : (DSU Offset: 0xF0) (R/W 32) Device Configuration -------- */
#define DSU_DCFG_RESETVALUE _U_(0x00) /**< (DSU_DCFG) Device Configuration Reset Value */
#define DSU_DCFG_DCFG_Pos _U_(0) /**< (DSU_DCFG) Device Configuration Position */
#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) /**< (DSU_DCFG) Device Configuration Mask */
#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
#define DSU_DCFG_Msk _U_(0xFFFFFFFF) /**< (DSU_DCFG) Register Mask */
/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) ( R/ 32) CoreSight ROM Table Entry 0 -------- */
#define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< (DSU_ENTRY0) CoreSight ROM Table Entry 0 Reset Value */
#define DSU_ENTRY0_EPRES_Pos _U_(0) /**< (DSU_ENTRY0) Entry Present Position */
#define DSU_ENTRY0_EPRES_Msk (_U_(0x1) << DSU_ENTRY0_EPRES_Pos) /**< (DSU_ENTRY0) Entry Present Mask */
#define DSU_ENTRY0_EPRES(value) (DSU_ENTRY0_EPRES_Msk & ((value) << DSU_ENTRY0_EPRES_Pos))
#define DSU_ENTRY0_FMT_Pos _U_(1) /**< (DSU_ENTRY0) Format Position */
#define DSU_ENTRY0_FMT_Msk (_U_(0x1) << DSU_ENTRY0_FMT_Pos) /**< (DSU_ENTRY0) Format Mask */
#define DSU_ENTRY0_FMT(value) (DSU_ENTRY0_FMT_Msk & ((value) << DSU_ENTRY0_FMT_Pos))
#define DSU_ENTRY0_ADDOFF_Pos _U_(12) /**< (DSU_ENTRY0) Address Offset Position */
#define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos) /**< (DSU_ENTRY0) Address Offset Mask */
#define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
#define DSU_ENTRY0_Msk _U_(0xFFFFF003) /**< (DSU_ENTRY0) Register Mask */
/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) ( R/ 32) CoreSight ROM Table Entry 1 -------- */
#define DSU_ENTRY1_RESETVALUE _U_(0x00) /**< (DSU_ENTRY1) CoreSight ROM Table Entry 1 Reset Value */
#define DSU_ENTRY1_Msk _U_(0x00000000) /**< (DSU_ENTRY1) Register Mask */
/* -------- DSU_END : (DSU Offset: 0x1008) ( R/ 32) CoreSight ROM Table End -------- */
#define DSU_END_RESETVALUE _U_(0x00) /**< (DSU_END) CoreSight ROM Table End Reset Value */
#define DSU_END_END_Pos _U_(0) /**< (DSU_END) End Marker Position */
#define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos) /**< (DSU_END) End Marker Mask */
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
#define DSU_END_Msk _U_(0xFFFFFFFF) /**< (DSU_END) Register Mask */
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) ( R/ 32) CoreSight ROM Table Memory Type -------- */
#define DSU_MEMTYPE_RESETVALUE _U_(0x00) /**< (DSU_MEMTYPE) CoreSight ROM Table Memory Type Reset Value */
#define DSU_MEMTYPE_SMEMP_Pos _U_(0) /**< (DSU_MEMTYPE) System Memory Present Position */
#define DSU_MEMTYPE_SMEMP_Msk (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos) /**< (DSU_MEMTYPE) System Memory Present Mask */
#define DSU_MEMTYPE_SMEMP(value) (DSU_MEMTYPE_SMEMP_Msk & ((value) << DSU_MEMTYPE_SMEMP_Pos))
#define DSU_MEMTYPE_Msk _U_(0x00000001) /**< (DSU_MEMTYPE) Register Mask */
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) ( R/ 32) Peripheral Identification 4 -------- */
#define DSU_PID4_RESETVALUE _U_(0x00) /**< (DSU_PID4) Peripheral Identification 4 Reset Value */
#define DSU_PID4_JEPCC_Pos _U_(0) /**< (DSU_PID4) JEP-106 Continuation Code Position */
#define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos) /**< (DSU_PID4) JEP-106 Continuation Code Mask */
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
#define DSU_PID4_FKBC_Pos _U_(4) /**< (DSU_PID4) 4KB count Position */
#define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos) /**< (DSU_PID4) 4KB count Mask */
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
#define DSU_PID4_Msk _U_(0x000000FF) /**< (DSU_PID4) Register Mask */
/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) ( R/ 32) Peripheral Identification 5 -------- */
#define DSU_PID5_RESETVALUE _U_(0x00) /**< (DSU_PID5) Peripheral Identification 5 Reset Value */
#define DSU_PID5_Msk _U_(0x00000000) /**< (DSU_PID5) Register Mask */
/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) ( R/ 32) Peripheral Identification 6 -------- */
#define DSU_PID6_RESETVALUE _U_(0x00) /**< (DSU_PID6) Peripheral Identification 6 Reset Value */
#define DSU_PID6_Msk _U_(0x00000000) /**< (DSU_PID6) Register Mask */
/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) ( R/ 32) Peripheral Identification 7 -------- */
#define DSU_PID7_RESETVALUE _U_(0x00) /**< (DSU_PID7) Peripheral Identification 7 Reset Value */
#define DSU_PID7_Msk _U_(0x00000000) /**< (DSU_PID7) Register Mask */
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) ( R/ 32) Peripheral Identification 0 -------- */
#define DSU_PID0_RESETVALUE _U_(0xD0) /**< (DSU_PID0) Peripheral Identification 0 Reset Value */
#define DSU_PID0_PARTNBL_Pos _U_(0) /**< (DSU_PID0) Part Number Low Position */
#define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos) /**< (DSU_PID0) Part Number Low Mask */
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
#define DSU_PID0_Msk _U_(0x000000FF) /**< (DSU_PID0) Register Mask */
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) ( R/ 32) Peripheral Identification 1 -------- */
#define DSU_PID1_RESETVALUE _U_(0xFC) /**< (DSU_PID1) Peripheral Identification 1 Reset Value */
#define DSU_PID1_PARTNBH_Pos _U_(0) /**< (DSU_PID1) Part Number High Position */
#define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos) /**< (DSU_PID1) Part Number High Mask */
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
#define DSU_PID1_JEPIDCL_Pos _U_(4) /**< (DSU_PID1) Low part of the JEP-106 Identity Code Position */
#define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos) /**< (DSU_PID1) Low part of the JEP-106 Identity Code Mask */
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
#define DSU_PID1_Msk _U_(0x000000FF) /**< (DSU_PID1) Register Mask */
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) ( R/ 32) Peripheral Identification 2 -------- */
#define DSU_PID2_RESETVALUE _U_(0x09) /**< (DSU_PID2) Peripheral Identification 2 Reset Value */
#define DSU_PID2_JEPIDCH_Pos _U_(0) /**< (DSU_PID2) JEP-106 Identity Code High Position */
#define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos) /**< (DSU_PID2) JEP-106 Identity Code High Mask */
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
#define DSU_PID2_JEPU_Pos _U_(3) /**< (DSU_PID2) JEP-106 Identity Code is used Position */
#define DSU_PID2_JEPU_Msk (_U_(0x1) << DSU_PID2_JEPU_Pos) /**< (DSU_PID2) JEP-106 Identity Code is used Mask */
#define DSU_PID2_JEPU(value) (DSU_PID2_JEPU_Msk & ((value) << DSU_PID2_JEPU_Pos))
#define DSU_PID2_REVISION_Pos _U_(4) /**< (DSU_PID2) Revision Number Position */
#define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos) /**< (DSU_PID2) Revision Number Mask */
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
#define DSU_PID2_Msk _U_(0x000000FF) /**< (DSU_PID2) Register Mask */
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) ( R/ 32) Peripheral Identification 3 -------- */
#define DSU_PID3_RESETVALUE _U_(0x00) /**< (DSU_PID3) Peripheral Identification 3 Reset Value */
#define DSU_PID3_CUSMOD_Pos _U_(0) /**< (DSU_PID3) ARM CUSMOD Position */
#define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos) /**< (DSU_PID3) ARM CUSMOD Mask */
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
#define DSU_PID3_REVAND_Pos _U_(4) /**< (DSU_PID3) Revision Number Position */
#define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos) /**< (DSU_PID3) Revision Number Mask */
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
#define DSU_PID3_Msk _U_(0x000000FF) /**< (DSU_PID3) Register Mask */
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) ( R/ 32) Component Identification 0 -------- */
#define DSU_CID0_RESETVALUE _U_(0x0D) /**< (DSU_CID0) Component Identification 0 Reset Value */
#define DSU_CID0_PREAMBLEB0_Pos _U_(0) /**< (DSU_CID0) Preamble Byte 0 Position */
#define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) /**< (DSU_CID0) Preamble Byte 0 Mask */
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
#define DSU_CID0_Msk _U_(0x000000FF) /**< (DSU_CID0) Register Mask */
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) ( R/ 32) Component Identification 1 -------- */
#define DSU_CID1_RESETVALUE _U_(0x10) /**< (DSU_CID1) Component Identification 1 Reset Value */
#define DSU_CID1_PREAMBLE_Pos _U_(0) /**< (DSU_CID1) Preamble Position */
#define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos) /**< (DSU_CID1) Preamble Mask */
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
#define DSU_CID1_CCLASS_Pos _U_(4) /**< (DSU_CID1) Component Class Position */
#define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos) /**< (DSU_CID1) Component Class Mask */
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
#define DSU_CID1_Msk _U_(0x000000FF) /**< (DSU_CID1) Register Mask */
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) ( R/ 32) Component Identification 2 -------- */
#define DSU_CID2_RESETVALUE _U_(0x05) /**< (DSU_CID2) Component Identification 2 Reset Value */
#define DSU_CID2_PREAMBLEB2_Pos _U_(0) /**< (DSU_CID2) Preamble Byte 2 Position */
#define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) /**< (DSU_CID2) Preamble Byte 2 Mask */
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
#define DSU_CID2_Msk _U_(0x000000FF) /**< (DSU_CID2) Register Mask */
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) ( R/ 32) Component Identification 3 -------- */
#define DSU_CID3_RESETVALUE _U_(0xB1) /**< (DSU_CID3) Component Identification 3 Reset Value */
#define DSU_CID3_PREAMBLEB3_Pos _U_(0) /**< (DSU_CID3) Preamble Byte 3 Position */
#define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) /**< (DSU_CID3) Preamble Byte 3 Mask */
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
#define DSU_CID3_Msk _U_(0x000000FF) /**< (DSU_CID3) Register Mask */
/** \brief DSU register offsets definitions */
#define DSU_CTRL_REG_OFST (0x00) /**< (DSU_CTRL) Control Offset */
#define DSU_STATUSA_REG_OFST (0x01) /**< (DSU_STATUSA) Status A Offset */
#define DSU_STATUSB_REG_OFST (0x02) /**< (DSU_STATUSB) Status B Offset */
#define DSU_ADDR_REG_OFST (0x04) /**< (DSU_ADDR) Address Offset */
#define DSU_LENGTH_REG_OFST (0x08) /**< (DSU_LENGTH) Length Offset */
#define DSU_DATA_REG_OFST (0x0C) /**< (DSU_DATA) Data Offset */
#define DSU_DCC_REG_OFST (0x10) /**< (DSU_DCC) Debug Communication Channel n Offset */
#define DSU_DID_REG_OFST (0x18) /**< (DSU_DID) Device Identification Offset */
#define DSU_CFG_REG_OFST (0x1C) /**< (DSU_CFG) Configuration Offset */
#define DSU_DCFG_REG_OFST (0xF0) /**< (DSU_DCFG) Device Configuration Offset */
#define DSU_ENTRY0_REG_OFST (0x1000) /**< (DSU_ENTRY0) CoreSight ROM Table Entry 0 Offset */
#define DSU_ENTRY1_REG_OFST (0x1004) /**< (DSU_ENTRY1) CoreSight ROM Table Entry 1 Offset */
#define DSU_END_REG_OFST (0x1008) /**< (DSU_END) CoreSight ROM Table End Offset */
#define DSU_MEMTYPE_REG_OFST (0x1FCC) /**< (DSU_MEMTYPE) CoreSight ROM Table Memory Type Offset */
#define DSU_PID4_REG_OFST (0x1FD0) /**< (DSU_PID4) Peripheral Identification 4 Offset */
#define DSU_PID5_REG_OFST (0x1FD4) /**< (DSU_PID5) Peripheral Identification 5 Offset */
#define DSU_PID6_REG_OFST (0x1FD8) /**< (DSU_PID6) Peripheral Identification 6 Offset */
#define DSU_PID7_REG_OFST (0x1FDC) /**< (DSU_PID7) Peripheral Identification 7 Offset */
#define DSU_PID0_REG_OFST (0x1FE0) /**< (DSU_PID0) Peripheral Identification 0 Offset */
#define DSU_PID1_REG_OFST (0x1FE4) /**< (DSU_PID1) Peripheral Identification 1 Offset */
#define DSU_PID2_REG_OFST (0x1FE8) /**< (DSU_PID2) Peripheral Identification 2 Offset */
#define DSU_PID3_REG_OFST (0x1FEC) /**< (DSU_PID3) Peripheral Identification 3 Offset */
#define DSU_CID0_REG_OFST (0x1FF0) /**< (DSU_CID0) Component Identification 0 Offset */
#define DSU_CID1_REG_OFST (0x1FF4) /**< (DSU_CID1) Component Identification 1 Offset */
#define DSU_CID2_REG_OFST (0x1FF8) /**< (DSU_CID2) Component Identification 2 Offset */
#define DSU_CID3_REG_OFST (0x1FFC) /**< (DSU_CID3) Component Identification 3 Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief DSU register API structure */
typedef struct
{ /* Device Service Unit */
__O uint8_t DSU_CTRL; /**< Offset: 0x00 ( /W 8) Control */
__IO uint8_t DSU_STATUSA; /**< Offset: 0x01 (R/W 8) Status A */
__I uint8_t DSU_STATUSB; /**< Offset: 0x02 (R/ 8) Status B */
__I uint8_t Reserved1[0x01];
__IO uint32_t DSU_ADDR; /**< Offset: 0x04 (R/W 32) Address */
__IO uint32_t DSU_LENGTH; /**< Offset: 0x08 (R/W 32) Length */
__IO uint32_t DSU_DATA; /**< Offset: 0x0C (R/W 32) Data */
__IO uint32_t DSU_DCC[2]; /**< Offset: 0x10 (R/W 32) Debug Communication Channel n */
__I uint32_t DSU_DID; /**< Offset: 0x18 (R/ 32) Device Identification */
__IO uint32_t DSU_CFG; /**< Offset: 0x1C (R/W 32) Configuration */
__I uint8_t Reserved2[0xD0];
__IO uint32_t DSU_DCFG[2]; /**< Offset: 0xF0 (R/W 32) Device Configuration */
__I uint8_t Reserved3[0xF08];
__I uint32_t DSU_ENTRY0; /**< Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */
__I uint32_t DSU_ENTRY1; /**< Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */
__I uint32_t DSU_END; /**< Offset: 0x1008 (R/ 32) CoreSight ROM Table End */
__I uint8_t Reserved4[0xFC0];
__I uint32_t DSU_MEMTYPE; /**< Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */
__I uint32_t DSU_PID4; /**< Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
__I uint32_t DSU_PID5; /**< Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
__I uint32_t DSU_PID6; /**< Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */
__I uint32_t DSU_PID7; /**< Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */
__I uint32_t DSU_PID0; /**< Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I uint32_t DSU_PID1; /**< Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I uint32_t DSU_PID2; /**< Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I uint32_t DSU_PID3; /**< Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I uint32_t DSU_CID0; /**< Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I uint32_t DSU_CID1; /**< Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I uint32_t DSU_CID2; /**< Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I uint32_t DSU_CID3; /**< Offset: 0x1FFC (R/ 32) Component Identification 3 */
} dsu_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_DSU_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/eic.h
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/**
* \brief Component description for EIC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_EIC_COMPONENT_H_
#define _SAMD51_EIC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR EIC */
/* ************************************************************************** */
/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */
#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< (EIC_CTRLA) Control A Reset Value */
#define EIC_CTRLA_SWRST_Pos _U_(0) /**< (EIC_CTRLA) Software Reset Position */
#define EIC_CTRLA_SWRST_Msk (_U_(0x1) << EIC_CTRLA_SWRST_Pos) /**< (EIC_CTRLA) Software Reset Mask */
#define EIC_CTRLA_SWRST(value) (EIC_CTRLA_SWRST_Msk & ((value) << EIC_CTRLA_SWRST_Pos))
#define EIC_CTRLA_ENABLE_Pos _U_(1) /**< (EIC_CTRLA) Enable Position */
#define EIC_CTRLA_ENABLE_Msk (_U_(0x1) << EIC_CTRLA_ENABLE_Pos) /**< (EIC_CTRLA) Enable Mask */
#define EIC_CTRLA_ENABLE(value) (EIC_CTRLA_ENABLE_Msk & ((value) << EIC_CTRLA_ENABLE_Pos))
#define EIC_CTRLA_CKSEL_Pos _U_(4) /**< (EIC_CTRLA) Clock Selection Position */
#define EIC_CTRLA_CKSEL_Msk (_U_(0x1) << EIC_CTRLA_CKSEL_Pos) /**< (EIC_CTRLA) Clock Selection Mask */
#define EIC_CTRLA_CKSEL(value) (EIC_CTRLA_CKSEL_Msk & ((value) << EIC_CTRLA_CKSEL_Pos))
#define EIC_CTRLA_CKSEL_CLK_GCLK_Val _U_(0x0) /**< (EIC_CTRLA) Clocked by GCLK */
#define EIC_CTRLA_CKSEL_CLK_ULP32K_Val _U_(0x1) /**< (EIC_CTRLA) Clocked by ULP32K */
#define EIC_CTRLA_CKSEL_CLK_GCLK (EIC_CTRLA_CKSEL_CLK_GCLK_Val << EIC_CTRLA_CKSEL_Pos) /**< (EIC_CTRLA) Clocked by GCLK Position */
#define EIC_CTRLA_CKSEL_CLK_ULP32K (EIC_CTRLA_CKSEL_CLK_ULP32K_Val << EIC_CTRLA_CKSEL_Pos) /**< (EIC_CTRLA) Clocked by ULP32K Position */
#define EIC_CTRLA_Msk _U_(0x13) /**< (EIC_CTRLA) Register Mask */
/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */
#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< (EIC_NMICTRL) Non-Maskable Interrupt Control Reset Value */
#define EIC_NMICTRL_NMISENSE_Pos _U_(0) /**< (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Position */
#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Non-Maskable Interrupt Sense Configuration Mask */
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< (EIC_NMICTRL) No detection */
#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< (EIC_NMICTRL) Rising-edge detection */
#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< (EIC_NMICTRL) Falling-edge detection */
#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< (EIC_NMICTRL) Both-edges detection */
#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< (EIC_NMICTRL) High-level detection */
#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< (EIC_NMICTRL) Low-level detection */
#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) No detection Position */
#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Rising-edge detection Position */
#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Falling-edge detection Position */
#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Both-edges detection Position */
#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) High-level detection Position */
#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Low-level detection Position */
#define EIC_NMICTRL_NMIFILTEN_Pos _U_(3) /**< (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Position */
#define EIC_NMICTRL_NMIFILTEN_Msk (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos) /**< (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Mask */
#define EIC_NMICTRL_NMIFILTEN(value) (EIC_NMICTRL_NMIFILTEN_Msk & ((value) << EIC_NMICTRL_NMIFILTEN_Pos))
#define EIC_NMICTRL_NMIASYNCH_Pos _U_(4) /**< (EIC_NMICTRL) Asynchronous Edge Detection Mode Position */
#define EIC_NMICTRL_NMIASYNCH_Msk (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos) /**< (EIC_NMICTRL) Asynchronous Edge Detection Mode Mask */
#define EIC_NMICTRL_NMIASYNCH(value) (EIC_NMICTRL_NMIASYNCH_Msk & ((value) << EIC_NMICTRL_NMIASYNCH_Pos))
#define EIC_NMICTRL_NMIASYNCH_SYNC_Val _U_(0x0) /**< (EIC_NMICTRL) Edge detection is clock synchronously operated */
#define EIC_NMICTRL_NMIASYNCH_ASYNC_Val _U_(0x1) /**< (EIC_NMICTRL) Edge detection is clock asynchronously operated */
#define EIC_NMICTRL_NMIASYNCH_SYNC (EIC_NMICTRL_NMIASYNCH_SYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /**< (EIC_NMICTRL) Edge detection is clock synchronously operated Position */
#define EIC_NMICTRL_NMIASYNCH_ASYNC (EIC_NMICTRL_NMIASYNCH_ASYNC_Val << EIC_NMICTRL_NMIASYNCH_Pos) /**< (EIC_NMICTRL) Edge detection is clock asynchronously operated Position */
#define EIC_NMICTRL_Msk _U_(0x1F) /**< (EIC_NMICTRL) Register Mask */
/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */
#define EIC_NMIFLAG_RESETVALUE _U_(0x00) /**< (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Reset Value */
#define EIC_NMIFLAG_NMI_Pos _U_(0) /**< (EIC_NMIFLAG) Non-Maskable Interrupt Position */
#define EIC_NMIFLAG_NMI_Msk (_U_(0x1) << EIC_NMIFLAG_NMI_Pos) /**< (EIC_NMIFLAG) Non-Maskable Interrupt Mask */
#define EIC_NMIFLAG_NMI(value) (EIC_NMIFLAG_NMI_Msk & ((value) << EIC_NMIFLAG_NMI_Pos))
#define EIC_NMIFLAG_Msk _U_(0x0001) /**< (EIC_NMIFLAG) Register Mask */
/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
#define EIC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (EIC_SYNCBUSY) Synchronization Busy Reset Value */
#define EIC_SYNCBUSY_SWRST_Pos _U_(0) /**< (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Position */
#define EIC_SYNCBUSY_SWRST_Msk (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos) /**< (EIC_SYNCBUSY) Software Reset Synchronization Busy Status Mask */
#define EIC_SYNCBUSY_SWRST(value) (EIC_SYNCBUSY_SWRST_Msk & ((value) << EIC_SYNCBUSY_SWRST_Pos))
#define EIC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (EIC_SYNCBUSY) Enable Synchronization Busy Status Position */
#define EIC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos) /**< (EIC_SYNCBUSY) Enable Synchronization Busy Status Mask */
#define EIC_SYNCBUSY_ENABLE(value) (EIC_SYNCBUSY_ENABLE_Msk & ((value) << EIC_SYNCBUSY_ENABLE_Pos))
#define EIC_SYNCBUSY_Msk _U_(0x00000003) /**< (EIC_SYNCBUSY) Register Mask */
/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
#define EIC_EVCTRL_RESETVALUE _U_(0x00) /**< (EIC_EVCTRL) Event Control Reset Value */
#define EIC_EVCTRL_EXTINTEO_Pos _U_(0) /**< (EIC_EVCTRL) External Interrupt Event Output Enable Position */
#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos) /**< (EIC_EVCTRL) External Interrupt Event Output Enable Mask */
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
#define EIC_EVCTRL_Msk _U_(0x0000FFFF) /**< (EIC_EVCTRL) Register Mask */
/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
#define EIC_INTENCLR_RESETVALUE _U_(0x00) /**< (EIC_INTENCLR) Interrupt Enable Clear Reset Value */
#define EIC_INTENCLR_EXTINT_Pos _U_(0) /**< (EIC_INTENCLR) External Interrupt Enable Position */
#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos) /**< (EIC_INTENCLR) External Interrupt Enable Mask */
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
#define EIC_INTENCLR_Msk _U_(0x0000FFFF) /**< (EIC_INTENCLR) Register Mask */
/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
#define EIC_INTENSET_RESETVALUE _U_(0x00) /**< (EIC_INTENSET) Interrupt Enable Set Reset Value */
#define EIC_INTENSET_EXTINT_Pos _U_(0) /**< (EIC_INTENSET) External Interrupt Enable Position */
#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos) /**< (EIC_INTENSET) External Interrupt Enable Mask */
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
#define EIC_INTENSET_Msk _U_(0x0000FFFF) /**< (EIC_INTENSET) Register Mask */
/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
#define EIC_INTFLAG_RESETVALUE _U_(0x00) /**< (EIC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define EIC_INTFLAG_EXTINT_Pos _U_(0) /**< (EIC_INTFLAG) External Interrupt Position */
#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos) /**< (EIC_INTFLAG) External Interrupt Mask */
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
#define EIC_INTFLAG_Msk _U_(0x0000FFFF) /**< (EIC_INTFLAG) Register Mask */
/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */
#define EIC_ASYNCH_RESETVALUE _U_(0x00) /**< (EIC_ASYNCH) External Interrupt Asynchronous Mode Reset Value */
#define EIC_ASYNCH_ASYNCH_Pos _U_(0) /**< (EIC_ASYNCH) Asynchronous Edge Detection Mode Position */
#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos) /**< (EIC_ASYNCH) Asynchronous Edge Detection Mode Mask */
#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
#define EIC_ASYNCH_ASYNCH_SYNC_Val _U_(0x0) /**< (EIC_ASYNCH) Edge detection is clock synchronously operated */
#define EIC_ASYNCH_ASYNCH_ASYNC_Val _U_(0x1) /**< (EIC_ASYNCH) Edge detection is clock asynchronously operated */
#define EIC_ASYNCH_ASYNCH_SYNC (EIC_ASYNCH_ASYNCH_SYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /**< (EIC_ASYNCH) Edge detection is clock synchronously operated Position */
#define EIC_ASYNCH_ASYNCH_ASYNC (EIC_ASYNCH_ASYNCH_ASYNC_Val << EIC_ASYNCH_ASYNCH_Pos) /**< (EIC_ASYNCH) Edge detection is clock asynchronously operated Position */
#define EIC_ASYNCH_Msk _U_(0x0000FFFF) /**< (EIC_ASYNCH) Register Mask */
/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */
#define EIC_CONFIG_RESETVALUE _U_(0x00) /**< (EIC_CONFIG) External Interrupt Sense Configuration Reset Value */
#define EIC_CONFIG_SENSE0_Pos _U_(0) /**< (EIC_CONFIG) Input Sense Configuration 0 Position */
#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Input Sense Configuration 0 Mask */
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN0_Pos _U_(3) /**< (EIC_CONFIG) Filter Enable 0 Position */
#define EIC_CONFIG_FILTEN0_Msk (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos) /**< (EIC_CONFIG) Filter Enable 0 Mask */
#define EIC_CONFIG_FILTEN0(value) (EIC_CONFIG_FILTEN0_Msk & ((value) << EIC_CONFIG_FILTEN0_Pos))
#define EIC_CONFIG_SENSE1_Pos _U_(4) /**< (EIC_CONFIG) Input Sense Configuration 1 Position */
#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Input Sense Configuration 1 Mask */
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN1_Pos _U_(7) /**< (EIC_CONFIG) Filter Enable 1 Position */
#define EIC_CONFIG_FILTEN1_Msk (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos) /**< (EIC_CONFIG) Filter Enable 1 Mask */
#define EIC_CONFIG_FILTEN1(value) (EIC_CONFIG_FILTEN1_Msk & ((value) << EIC_CONFIG_FILTEN1_Pos))
#define EIC_CONFIG_SENSE2_Pos _U_(8) /**< (EIC_CONFIG) Input Sense Configuration 2 Position */
#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Input Sense Configuration 2 Mask */
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN2_Pos _U_(11) /**< (EIC_CONFIG) Filter Enable 2 Position */
#define EIC_CONFIG_FILTEN2_Msk (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos) /**< (EIC_CONFIG) Filter Enable 2 Mask */
#define EIC_CONFIG_FILTEN2(value) (EIC_CONFIG_FILTEN2_Msk & ((value) << EIC_CONFIG_FILTEN2_Pos))
#define EIC_CONFIG_SENSE3_Pos _U_(12) /**< (EIC_CONFIG) Input Sense Configuration 3 Position */
#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Input Sense Configuration 3 Mask */
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN3_Pos _U_(15) /**< (EIC_CONFIG) Filter Enable 3 Position */
#define EIC_CONFIG_FILTEN3_Msk (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos) /**< (EIC_CONFIG) Filter Enable 3 Mask */
#define EIC_CONFIG_FILTEN3(value) (EIC_CONFIG_FILTEN3_Msk & ((value) << EIC_CONFIG_FILTEN3_Pos))
#define EIC_CONFIG_SENSE4_Pos _U_(16) /**< (EIC_CONFIG) Input Sense Configuration 4 Position */
#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Input Sense Configuration 4 Mask */
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN4_Pos _U_(19) /**< (EIC_CONFIG) Filter Enable 4 Position */
#define EIC_CONFIG_FILTEN4_Msk (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos) /**< (EIC_CONFIG) Filter Enable 4 Mask */
#define EIC_CONFIG_FILTEN4(value) (EIC_CONFIG_FILTEN4_Msk & ((value) << EIC_CONFIG_FILTEN4_Pos))
#define EIC_CONFIG_SENSE5_Pos _U_(20) /**< (EIC_CONFIG) Input Sense Configuration 5 Position */
#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Input Sense Configuration 5 Mask */
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN5_Pos _U_(23) /**< (EIC_CONFIG) Filter Enable 5 Position */
#define EIC_CONFIG_FILTEN5_Msk (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) /**< (EIC_CONFIG) Filter Enable 5 Mask */
#define EIC_CONFIG_FILTEN5(value) (EIC_CONFIG_FILTEN5_Msk & ((value) << EIC_CONFIG_FILTEN5_Pos))
#define EIC_CONFIG_SENSE6_Pos _U_(24) /**< (EIC_CONFIG) Input Sense Configuration 6 Position */
#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Input Sense Configuration 6 Mask */
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN6_Pos _U_(27) /**< (EIC_CONFIG) Filter Enable 6 Position */
#define EIC_CONFIG_FILTEN6_Msk (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos) /**< (EIC_CONFIG) Filter Enable 6 Mask */
#define EIC_CONFIG_FILTEN6(value) (EIC_CONFIG_FILTEN6_Msk & ((value) << EIC_CONFIG_FILTEN6_Pos))
#define EIC_CONFIG_SENSE7_Pos _U_(28) /**< (EIC_CONFIG) Input Sense Configuration 7 Position */
#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Input Sense Configuration 7 Mask */
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) No detection Position */
#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Rising edge detection Position */
#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Falling edge detection Position */
#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Both edges detection Position */
#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) High level detection Position */
#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Low level detection Position */
#define EIC_CONFIG_FILTEN7_Pos _U_(31) /**< (EIC_CONFIG) Filter Enable 7 Position */
#define EIC_CONFIG_FILTEN7_Msk (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos) /**< (EIC_CONFIG) Filter Enable 7 Mask */
#define EIC_CONFIG_FILTEN7(value) (EIC_CONFIG_FILTEN7_Msk & ((value) << EIC_CONFIG_FILTEN7_Pos))
#define EIC_CONFIG_Msk _U_(0xFFFFFFFF) /**< (EIC_CONFIG) Register Mask */
/* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */
#define EIC_DEBOUNCEN_RESETVALUE _U_(0x00) /**< (EIC_DEBOUNCEN) Debouncer Enable Reset Value */
#define EIC_DEBOUNCEN_DEBOUNCEN_Pos _U_(0) /**< (EIC_DEBOUNCEN) Debouncer Enable Position */
#define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos) /**< (EIC_DEBOUNCEN) Debouncer Enable Mask */
#define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
#define EIC_DEBOUNCEN_Msk _U_(0x0000FFFF) /**< (EIC_DEBOUNCEN) Register Mask */
/* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */
#define EIC_DPRESCALER_RESETVALUE _U_(0x00) /**< (EIC_DPRESCALER) Debouncer Prescaler Reset Value */
#define EIC_DPRESCALER_PRESCALER0_Pos _U_(0) /**< (EIC_DPRESCALER) Debouncer Prescaler Position */
#define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) Debouncer Prescaler Mask */
#define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
#define EIC_DPRESCALER_PRESCALER0_DIV2_Val _U_(0x0) /**< (EIC_DPRESCALER) EIC clock divided by 2 */
#define EIC_DPRESCALER_PRESCALER0_DIV4_Val _U_(0x1) /**< (EIC_DPRESCALER) EIC clock divided by 4 */
#define EIC_DPRESCALER_PRESCALER0_DIV8_Val _U_(0x2) /**< (EIC_DPRESCALER) EIC clock divided by 8 */
#define EIC_DPRESCALER_PRESCALER0_DIV16_Val _U_(0x3) /**< (EIC_DPRESCALER) EIC clock divided by 16 */
#define EIC_DPRESCALER_PRESCALER0_DIV32_Val _U_(0x4) /**< (EIC_DPRESCALER) EIC clock divided by 32 */
#define EIC_DPRESCALER_PRESCALER0_DIV64_Val _U_(0x5) /**< (EIC_DPRESCALER) EIC clock divided by 64 */
#define EIC_DPRESCALER_PRESCALER0_DIV128_Val _U_(0x6) /**< (EIC_DPRESCALER) EIC clock divided by 128 */
#define EIC_DPRESCALER_PRESCALER0_DIV256_Val _U_(0x7) /**< (EIC_DPRESCALER) EIC clock divided by 256 */
#define EIC_DPRESCALER_PRESCALER0_DIV2 (EIC_DPRESCALER_PRESCALER0_DIV2_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 2 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV4 (EIC_DPRESCALER_PRESCALER0_DIV4_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 4 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV8 (EIC_DPRESCALER_PRESCALER0_DIV8_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 8 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV16 (EIC_DPRESCALER_PRESCALER0_DIV16_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 16 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV32 (EIC_DPRESCALER_PRESCALER0_DIV32_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 32 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV64 (EIC_DPRESCALER_PRESCALER0_DIV64_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 64 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV128 (EIC_DPRESCALER_PRESCALER0_DIV128_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 128 Position */
#define EIC_DPRESCALER_PRESCALER0_DIV256 (EIC_DPRESCALER_PRESCALER0_DIV256_Val << EIC_DPRESCALER_PRESCALER0_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 256 Position */
#define EIC_DPRESCALER_STATES0_Pos _U_(3) /**< (EIC_DPRESCALER) Debouncer number of states Position */
#define EIC_DPRESCALER_STATES0_Msk (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos) /**< (EIC_DPRESCALER) Debouncer number of states Mask */
#define EIC_DPRESCALER_STATES0(value) (EIC_DPRESCALER_STATES0_Msk & ((value) << EIC_DPRESCALER_STATES0_Pos))
#define EIC_DPRESCALER_STATES0_LFREQ3_Val _U_(0x0) /**< (EIC_DPRESCALER) 3 low frequency samples */
#define EIC_DPRESCALER_STATES0_LFREQ7_Val _U_(0x1) /**< (EIC_DPRESCALER) 7 low frequency samples */
#define EIC_DPRESCALER_STATES0_LFREQ3 (EIC_DPRESCALER_STATES0_LFREQ3_Val << EIC_DPRESCALER_STATES0_Pos) /**< (EIC_DPRESCALER) 3 low frequency samples Position */
#define EIC_DPRESCALER_STATES0_LFREQ7 (EIC_DPRESCALER_STATES0_LFREQ7_Val << EIC_DPRESCALER_STATES0_Pos) /**< (EIC_DPRESCALER) 7 low frequency samples Position */
#define EIC_DPRESCALER_PRESCALER1_Pos _U_(4) /**< (EIC_DPRESCALER) Debouncer Prescaler Position */
#define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) Debouncer Prescaler Mask */
#define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
#define EIC_DPRESCALER_PRESCALER1_DIV2_Val _U_(0x0) /**< (EIC_DPRESCALER) EIC clock divided by 2 */
#define EIC_DPRESCALER_PRESCALER1_DIV4_Val _U_(0x1) /**< (EIC_DPRESCALER) EIC clock divided by 4 */
#define EIC_DPRESCALER_PRESCALER1_DIV8_Val _U_(0x2) /**< (EIC_DPRESCALER) EIC clock divided by 8 */
#define EIC_DPRESCALER_PRESCALER1_DIV16_Val _U_(0x3) /**< (EIC_DPRESCALER) EIC clock divided by 16 */
#define EIC_DPRESCALER_PRESCALER1_DIV32_Val _U_(0x4) /**< (EIC_DPRESCALER) EIC clock divided by 32 */
#define EIC_DPRESCALER_PRESCALER1_DIV64_Val _U_(0x5) /**< (EIC_DPRESCALER) EIC clock divided by 64 */
#define EIC_DPRESCALER_PRESCALER1_DIV128_Val _U_(0x6) /**< (EIC_DPRESCALER) EIC clock divided by 128 */
#define EIC_DPRESCALER_PRESCALER1_DIV256_Val _U_(0x7) /**< (EIC_DPRESCALER) EIC clock divided by 256 */
#define EIC_DPRESCALER_PRESCALER1_DIV2 (EIC_DPRESCALER_PRESCALER1_DIV2_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 2 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV4 (EIC_DPRESCALER_PRESCALER1_DIV4_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 4 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV8 (EIC_DPRESCALER_PRESCALER1_DIV8_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 8 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV16 (EIC_DPRESCALER_PRESCALER1_DIV16_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 16 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV32 (EIC_DPRESCALER_PRESCALER1_DIV32_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 32 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV64 (EIC_DPRESCALER_PRESCALER1_DIV64_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 64 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV128 (EIC_DPRESCALER_PRESCALER1_DIV128_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 128 Position */
#define EIC_DPRESCALER_PRESCALER1_DIV256 (EIC_DPRESCALER_PRESCALER1_DIV256_Val << EIC_DPRESCALER_PRESCALER1_Pos) /**< (EIC_DPRESCALER) EIC clock divided by 256 Position */
#define EIC_DPRESCALER_STATES1_Pos _U_(7) /**< (EIC_DPRESCALER) Debouncer number of states Position */
#define EIC_DPRESCALER_STATES1_Msk (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos) /**< (EIC_DPRESCALER) Debouncer number of states Mask */
#define EIC_DPRESCALER_STATES1(value) (EIC_DPRESCALER_STATES1_Msk & ((value) << EIC_DPRESCALER_STATES1_Pos))
#define EIC_DPRESCALER_STATES1_LFREQ3_Val _U_(0x0) /**< (EIC_DPRESCALER) 3 low frequency samples */
#define EIC_DPRESCALER_STATES1_LFREQ7_Val _U_(0x1) /**< (EIC_DPRESCALER) 7 low frequency samples */
#define EIC_DPRESCALER_STATES1_LFREQ3 (EIC_DPRESCALER_STATES1_LFREQ3_Val << EIC_DPRESCALER_STATES1_Pos) /**< (EIC_DPRESCALER) 3 low frequency samples Position */
#define EIC_DPRESCALER_STATES1_LFREQ7 (EIC_DPRESCALER_STATES1_LFREQ7_Val << EIC_DPRESCALER_STATES1_Pos) /**< (EIC_DPRESCALER) 7 low frequency samples Position */
#define EIC_DPRESCALER_TICKON_Pos _U_(16) /**< (EIC_DPRESCALER) Pin Sampler frequency selection Position */
#define EIC_DPRESCALER_TICKON_Msk (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos) /**< (EIC_DPRESCALER) Pin Sampler frequency selection Mask */
#define EIC_DPRESCALER_TICKON(value) (EIC_DPRESCALER_TICKON_Msk & ((value) << EIC_DPRESCALER_TICKON_Pos))
#define EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val _U_(0x0) /**< (EIC_DPRESCALER) Clocked by GCLK */
#define EIC_DPRESCALER_TICKON_CLK_LFREQ_Val _U_(0x1) /**< (EIC_DPRESCALER) Clocked by Low Frequency Clock */
#define EIC_DPRESCALER_TICKON_CLK_GCLK_EIC (EIC_DPRESCALER_TICKON_CLK_GCLK_EIC_Val << EIC_DPRESCALER_TICKON_Pos) /**< (EIC_DPRESCALER) Clocked by GCLK Position */
#define EIC_DPRESCALER_TICKON_CLK_LFREQ (EIC_DPRESCALER_TICKON_CLK_LFREQ_Val << EIC_DPRESCALER_TICKON_Pos) /**< (EIC_DPRESCALER) Clocked by Low Frequency Clock Position */
#define EIC_DPRESCALER_Msk _U_(0x000100FF) /**< (EIC_DPRESCALER) Register Mask */
/* -------- EIC_PINSTATE : (EIC Offset: 0x38) ( R/ 32) Pin State -------- */
#define EIC_PINSTATE_RESETVALUE _U_(0x00) /**< (EIC_PINSTATE) Pin State Reset Value */
#define EIC_PINSTATE_PINSTATE_Pos _U_(0) /**< (EIC_PINSTATE) Pin State Position */
#define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos) /**< (EIC_PINSTATE) Pin State Mask */
#define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
#define EIC_PINSTATE_Msk _U_(0x0000FFFF) /**< (EIC_PINSTATE) Register Mask */
/** \brief EIC register offsets definitions */
#define EIC_CTRLA_REG_OFST (0x00) /**< (EIC_CTRLA) Control A Offset */
#define EIC_NMICTRL_REG_OFST (0x01) /**< (EIC_NMICTRL) Non-Maskable Interrupt Control Offset */
#define EIC_NMIFLAG_REG_OFST (0x02) /**< (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Offset */
#define EIC_SYNCBUSY_REG_OFST (0x04) /**< (EIC_SYNCBUSY) Synchronization Busy Offset */
#define EIC_EVCTRL_REG_OFST (0x08) /**< (EIC_EVCTRL) Event Control Offset */
#define EIC_INTENCLR_REG_OFST (0x0C) /**< (EIC_INTENCLR) Interrupt Enable Clear Offset */
#define EIC_INTENSET_REG_OFST (0x10) /**< (EIC_INTENSET) Interrupt Enable Set Offset */
#define EIC_INTFLAG_REG_OFST (0x14) /**< (EIC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define EIC_ASYNCH_REG_OFST (0x18) /**< (EIC_ASYNCH) External Interrupt Asynchronous Mode Offset */
#define EIC_CONFIG_REG_OFST (0x1C) /**< (EIC_CONFIG) External Interrupt Sense Configuration Offset */
#define EIC_DEBOUNCEN_REG_OFST (0x30) /**< (EIC_DEBOUNCEN) Debouncer Enable Offset */
#define EIC_DPRESCALER_REG_OFST (0x34) /**< (EIC_DPRESCALER) Debouncer Prescaler Offset */
#define EIC_PINSTATE_REG_OFST (0x38) /**< (EIC_PINSTATE) Pin State Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief EIC register API structure */
typedef struct
{ /* External Interrupt Controller */
__IO uint8_t EIC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__IO uint8_t EIC_NMICTRL; /**< Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */
__IO uint16_t EIC_NMIFLAG; /**< Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */
__I uint32_t EIC_SYNCBUSY; /**< Offset: 0x04 (R/ 32) Synchronization Busy */
__IO uint32_t EIC_EVCTRL; /**< Offset: 0x08 (R/W 32) Event Control */
__IO uint32_t EIC_INTENCLR; /**< Offset: 0x0C (R/W 32) Interrupt Enable Clear */
__IO uint32_t EIC_INTENSET; /**< Offset: 0x10 (R/W 32) Interrupt Enable Set */
__IO uint32_t EIC_INTFLAG; /**< Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
__IO uint32_t EIC_ASYNCH; /**< Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */
__IO uint32_t EIC_CONFIG[2]; /**< Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */
__I uint8_t Reserved1[0x0C];
__IO uint32_t EIC_DEBOUNCEN; /**< Offset: 0x30 (R/W 32) Debouncer Enable */
__IO uint32_t EIC_DPRESCALER; /**< Offset: 0x34 (R/W 32) Debouncer Prescaler */
__I uint32_t EIC_PINSTATE; /**< Offset: 0x38 (R/ 32) Pin State */
} eic_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_EIC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/evsys.h
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/**
* \brief Component description for EVSYS
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_EVSYS_COMPONENT_H_
#define _SAMD51_EVSYS_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR EVSYS */
/* ************************************************************************** */
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x00) (R/W 32) Channel n Control -------- */
#define EVSYS_CHANNEL_RESETVALUE _U_(0x8000) /**< (EVSYS_CHANNEL) Channel n Control Reset Value */
#define EVSYS_CHANNEL_EVGEN_Pos _U_(0) /**< (EVSYS_CHANNEL) Event Generator Selection Position */
#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos) /**< (EVSYS_CHANNEL) Event Generator Selection Mask */
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
#define EVSYS_CHANNEL_PATH_Pos _U_(8) /**< (EVSYS_CHANNEL) Path Selection Position */
#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Path Selection Mask */
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< (EVSYS_CHANNEL) Synchronous path */
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< (EVSYS_CHANNEL) Resynchronized path */
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< (EVSYS_CHANNEL) Asynchronous path */
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Synchronous path Position */
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Resynchronized path Position */
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Asynchronous path Position */
#define EVSYS_CHANNEL_EDGSEL_Pos _U_(10) /**< (EVSYS_CHANNEL) Edge Detection Selection Position */
#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Edge Detection Selection Mask */
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path Position */
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path Position */
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path Position */
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Position */
#define EVSYS_CHANNEL_RUNSTDBY_Pos _U_(14) /**< (EVSYS_CHANNEL) Run in standby Position */
#define EVSYS_CHANNEL_RUNSTDBY_Msk (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos) /**< (EVSYS_CHANNEL) Run in standby Mask */
#define EVSYS_CHANNEL_RUNSTDBY(value) (EVSYS_CHANNEL_RUNSTDBY_Msk & ((value) << EVSYS_CHANNEL_RUNSTDBY_Pos))
#define EVSYS_CHANNEL_ONDEMAND_Pos _U_(15) /**< (EVSYS_CHANNEL) Generic Clock On Demand Position */
#define EVSYS_CHANNEL_ONDEMAND_Msk (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos) /**< (EVSYS_CHANNEL) Generic Clock On Demand Mask */
#define EVSYS_CHANNEL_ONDEMAND(value) (EVSYS_CHANNEL_ONDEMAND_Msk & ((value) << EVSYS_CHANNEL_ONDEMAND_Pos))
#define EVSYS_CHANNEL_Msk _U_(0x0000CF7F) /**< (EVSYS_CHANNEL) Register Mask */
/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x04) (R/W 8) Channel n Interrupt Enable Clear -------- */
#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00) /**< (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear Reset Value */
#define EVSYS_CHINTENCLR_OVR_Pos _U_(0) /**< (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Position */
#define EVSYS_CHINTENCLR_OVR_Msk (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos) /**< (EVSYS_CHINTENCLR) Channel Overrun Interrupt Disable Mask */
#define EVSYS_CHINTENCLR_OVR(value) (EVSYS_CHINTENCLR_OVR_Msk & ((value) << EVSYS_CHINTENCLR_OVR_Pos))
#define EVSYS_CHINTENCLR_EVD_Pos _U_(1) /**< (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Position */
#define EVSYS_CHINTENCLR_EVD_Msk (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos) /**< (EVSYS_CHINTENCLR) Channel Event Detected Interrupt Disable Mask */
#define EVSYS_CHINTENCLR_EVD(value) (EVSYS_CHINTENCLR_EVD_Msk & ((value) << EVSYS_CHINTENCLR_EVD_Pos))
#define EVSYS_CHINTENCLR_Msk _U_(0x03) /**< (EVSYS_CHINTENCLR) Register Mask */
/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x05) (R/W 8) Channel n Interrupt Enable Set -------- */
#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00) /**< (EVSYS_CHINTENSET) Channel n Interrupt Enable Set Reset Value */
#define EVSYS_CHINTENSET_OVR_Pos _U_(0) /**< (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Position */
#define EVSYS_CHINTENSET_OVR_Msk (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos) /**< (EVSYS_CHINTENSET) Channel Overrun Interrupt Enable Mask */
#define EVSYS_CHINTENSET_OVR(value) (EVSYS_CHINTENSET_OVR_Msk & ((value) << EVSYS_CHINTENSET_OVR_Pos))
#define EVSYS_CHINTENSET_EVD_Pos _U_(1) /**< (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Position */
#define EVSYS_CHINTENSET_EVD_Msk (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos) /**< (EVSYS_CHINTENSET) Channel Event Detected Interrupt Enable Mask */
#define EVSYS_CHINTENSET_EVD(value) (EVSYS_CHINTENSET_EVD_Msk & ((value) << EVSYS_CHINTENSET_EVD_Pos))
#define EVSYS_CHINTENSET_Msk _U_(0x03) /**< (EVSYS_CHINTENSET) Register Mask */
/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x06) (R/W 8) Channel n Interrupt Flag Status and Clear -------- */
#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00) /**< (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear Reset Value */
#define EVSYS_CHINTFLAG_OVR_Pos _U_(0) /**< (EVSYS_CHINTFLAG) Channel Overrun Position */
#define EVSYS_CHINTFLAG_OVR_Msk (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos) /**< (EVSYS_CHINTFLAG) Channel Overrun Mask */
#define EVSYS_CHINTFLAG_OVR(value) (EVSYS_CHINTFLAG_OVR_Msk & ((value) << EVSYS_CHINTFLAG_OVR_Pos))
#define EVSYS_CHINTFLAG_EVD_Pos _U_(1) /**< (EVSYS_CHINTFLAG) Channel Event Detected Position */
#define EVSYS_CHINTFLAG_EVD_Msk (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos) /**< (EVSYS_CHINTFLAG) Channel Event Detected Mask */
#define EVSYS_CHINTFLAG_EVD(value) (EVSYS_CHINTFLAG_EVD_Msk & ((value) << EVSYS_CHINTFLAG_EVD_Pos))
#define EVSYS_CHINTFLAG_Msk _U_(0x03) /**< (EVSYS_CHINTFLAG) Register Mask */
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x07) ( R/ 8) Channel n Status -------- */
#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01) /**< (EVSYS_CHSTATUS) Channel n Status Reset Value */
#define EVSYS_CHSTATUS_RDYUSR_Pos _U_(0) /**< (EVSYS_CHSTATUS) Ready User Position */
#define EVSYS_CHSTATUS_RDYUSR_Msk (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos) /**< (EVSYS_CHSTATUS) Ready User Mask */
#define EVSYS_CHSTATUS_RDYUSR(value) (EVSYS_CHSTATUS_RDYUSR_Msk & ((value) << EVSYS_CHSTATUS_RDYUSR_Pos))
#define EVSYS_CHSTATUS_BUSYCH_Pos _U_(1) /**< (EVSYS_CHSTATUS) Busy Channel Position */
#define EVSYS_CHSTATUS_BUSYCH_Msk (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos) /**< (EVSYS_CHSTATUS) Busy Channel Mask */
#define EVSYS_CHSTATUS_BUSYCH(value) (EVSYS_CHSTATUS_BUSYCH_Msk & ((value) << EVSYS_CHSTATUS_BUSYCH_Pos))
#define EVSYS_CHSTATUS_Msk _U_(0x03) /**< (EVSYS_CHSTATUS) Register Mask */
/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */
#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< (EVSYS_CTRLA) Control Reset Value */
#define EVSYS_CTRLA_SWRST_Pos _U_(0) /**< (EVSYS_CTRLA) Software Reset Position */
#define EVSYS_CTRLA_SWRST_Msk (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos) /**< (EVSYS_CTRLA) Software Reset Mask */
#define EVSYS_CTRLA_SWRST(value) (EVSYS_CTRLA_SWRST_Msk & ((value) << EVSYS_CTRLA_SWRST_Pos))
#define EVSYS_CTRLA_Msk _U_(0x01) /**< (EVSYS_CTRLA) Register Mask */
/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x04) ( /W 32) Software Event -------- */
#define EVSYS_SWEVT_RESETVALUE _U_(0x00) /**< (EVSYS_SWEVT) Software Event Reset Value */
#define EVSYS_SWEVT_CHANNEL0_Pos _U_(0) /**< (EVSYS_SWEVT) Channel 0 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL0_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL0_Pos) /**< (EVSYS_SWEVT) Channel 0 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL0(value) (EVSYS_SWEVT_CHANNEL0_Msk & ((value) << EVSYS_SWEVT_CHANNEL0_Pos))
#define EVSYS_SWEVT_CHANNEL1_Pos _U_(1) /**< (EVSYS_SWEVT) Channel 1 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL1_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL1_Pos) /**< (EVSYS_SWEVT) Channel 1 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL1(value) (EVSYS_SWEVT_CHANNEL1_Msk & ((value) << EVSYS_SWEVT_CHANNEL1_Pos))
#define EVSYS_SWEVT_CHANNEL2_Pos _U_(2) /**< (EVSYS_SWEVT) Channel 2 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL2_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL2_Pos) /**< (EVSYS_SWEVT) Channel 2 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL2(value) (EVSYS_SWEVT_CHANNEL2_Msk & ((value) << EVSYS_SWEVT_CHANNEL2_Pos))
#define EVSYS_SWEVT_CHANNEL3_Pos _U_(3) /**< (EVSYS_SWEVT) Channel 3 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL3_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL3_Pos) /**< (EVSYS_SWEVT) Channel 3 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL3(value) (EVSYS_SWEVT_CHANNEL3_Msk & ((value) << EVSYS_SWEVT_CHANNEL3_Pos))
#define EVSYS_SWEVT_CHANNEL4_Pos _U_(4) /**< (EVSYS_SWEVT) Channel 4 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL4_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL4_Pos) /**< (EVSYS_SWEVT) Channel 4 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL4(value) (EVSYS_SWEVT_CHANNEL4_Msk & ((value) << EVSYS_SWEVT_CHANNEL4_Pos))
#define EVSYS_SWEVT_CHANNEL5_Pos _U_(5) /**< (EVSYS_SWEVT) Channel 5 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL5_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL5_Pos) /**< (EVSYS_SWEVT) Channel 5 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL5(value) (EVSYS_SWEVT_CHANNEL5_Msk & ((value) << EVSYS_SWEVT_CHANNEL5_Pos))
#define EVSYS_SWEVT_CHANNEL6_Pos _U_(6) /**< (EVSYS_SWEVT) Channel 6 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL6_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL6_Pos) /**< (EVSYS_SWEVT) Channel 6 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL6(value) (EVSYS_SWEVT_CHANNEL6_Msk & ((value) << EVSYS_SWEVT_CHANNEL6_Pos))
#define EVSYS_SWEVT_CHANNEL7_Pos _U_(7) /**< (EVSYS_SWEVT) Channel 7 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL7_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL7_Pos) /**< (EVSYS_SWEVT) Channel 7 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL7(value) (EVSYS_SWEVT_CHANNEL7_Msk & ((value) << EVSYS_SWEVT_CHANNEL7_Pos))
#define EVSYS_SWEVT_CHANNEL8_Pos _U_(8) /**< (EVSYS_SWEVT) Channel 8 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL8_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL8_Pos) /**< (EVSYS_SWEVT) Channel 8 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL8(value) (EVSYS_SWEVT_CHANNEL8_Msk & ((value) << EVSYS_SWEVT_CHANNEL8_Pos))
#define EVSYS_SWEVT_CHANNEL9_Pos _U_(9) /**< (EVSYS_SWEVT) Channel 9 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL9_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL9_Pos) /**< (EVSYS_SWEVT) Channel 9 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL9(value) (EVSYS_SWEVT_CHANNEL9_Msk & ((value) << EVSYS_SWEVT_CHANNEL9_Pos))
#define EVSYS_SWEVT_CHANNEL10_Pos _U_(10) /**< (EVSYS_SWEVT) Channel 10 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL10_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL10_Pos) /**< (EVSYS_SWEVT) Channel 10 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL10(value) (EVSYS_SWEVT_CHANNEL10_Msk & ((value) << EVSYS_SWEVT_CHANNEL10_Pos))
#define EVSYS_SWEVT_CHANNEL11_Pos _U_(11) /**< (EVSYS_SWEVT) Channel 11 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL11_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL11_Pos) /**< (EVSYS_SWEVT) Channel 11 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL11(value) (EVSYS_SWEVT_CHANNEL11_Msk & ((value) << EVSYS_SWEVT_CHANNEL11_Pos))
#define EVSYS_SWEVT_CHANNEL12_Pos _U_(12) /**< (EVSYS_SWEVT) Channel 12 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL12_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL12_Pos) /**< (EVSYS_SWEVT) Channel 12 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL12(value) (EVSYS_SWEVT_CHANNEL12_Msk & ((value) << EVSYS_SWEVT_CHANNEL12_Pos))
#define EVSYS_SWEVT_CHANNEL13_Pos _U_(13) /**< (EVSYS_SWEVT) Channel 13 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL13_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL13_Pos) /**< (EVSYS_SWEVT) Channel 13 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL13(value) (EVSYS_SWEVT_CHANNEL13_Msk & ((value) << EVSYS_SWEVT_CHANNEL13_Pos))
#define EVSYS_SWEVT_CHANNEL14_Pos _U_(14) /**< (EVSYS_SWEVT) Channel 14 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL14_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL14_Pos) /**< (EVSYS_SWEVT) Channel 14 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL14(value) (EVSYS_SWEVT_CHANNEL14_Msk & ((value) << EVSYS_SWEVT_CHANNEL14_Pos))
#define EVSYS_SWEVT_CHANNEL15_Pos _U_(15) /**< (EVSYS_SWEVT) Channel 15 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL15_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL15_Pos) /**< (EVSYS_SWEVT) Channel 15 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL15(value) (EVSYS_SWEVT_CHANNEL15_Msk & ((value) << EVSYS_SWEVT_CHANNEL15_Pos))
#define EVSYS_SWEVT_CHANNEL16_Pos _U_(16) /**< (EVSYS_SWEVT) Channel 16 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL16_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL16_Pos) /**< (EVSYS_SWEVT) Channel 16 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL16(value) (EVSYS_SWEVT_CHANNEL16_Msk & ((value) << EVSYS_SWEVT_CHANNEL16_Pos))
#define EVSYS_SWEVT_CHANNEL17_Pos _U_(17) /**< (EVSYS_SWEVT) Channel 17 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL17_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL17_Pos) /**< (EVSYS_SWEVT) Channel 17 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL17(value) (EVSYS_SWEVT_CHANNEL17_Msk & ((value) << EVSYS_SWEVT_CHANNEL17_Pos))
#define EVSYS_SWEVT_CHANNEL18_Pos _U_(18) /**< (EVSYS_SWEVT) Channel 18 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL18_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL18_Pos) /**< (EVSYS_SWEVT) Channel 18 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL18(value) (EVSYS_SWEVT_CHANNEL18_Msk & ((value) << EVSYS_SWEVT_CHANNEL18_Pos))
#define EVSYS_SWEVT_CHANNEL19_Pos _U_(19) /**< (EVSYS_SWEVT) Channel 19 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL19_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL19_Pos) /**< (EVSYS_SWEVT) Channel 19 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL19(value) (EVSYS_SWEVT_CHANNEL19_Msk & ((value) << EVSYS_SWEVT_CHANNEL19_Pos))
#define EVSYS_SWEVT_CHANNEL20_Pos _U_(20) /**< (EVSYS_SWEVT) Channel 20 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL20_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL20_Pos) /**< (EVSYS_SWEVT) Channel 20 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL20(value) (EVSYS_SWEVT_CHANNEL20_Msk & ((value) << EVSYS_SWEVT_CHANNEL20_Pos))
#define EVSYS_SWEVT_CHANNEL21_Pos _U_(21) /**< (EVSYS_SWEVT) Channel 21 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL21_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL21_Pos) /**< (EVSYS_SWEVT) Channel 21 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL21(value) (EVSYS_SWEVT_CHANNEL21_Msk & ((value) << EVSYS_SWEVT_CHANNEL21_Pos))
#define EVSYS_SWEVT_CHANNEL22_Pos _U_(22) /**< (EVSYS_SWEVT) Channel 22 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL22_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL22_Pos) /**< (EVSYS_SWEVT) Channel 22 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL22(value) (EVSYS_SWEVT_CHANNEL22_Msk & ((value) << EVSYS_SWEVT_CHANNEL22_Pos))
#define EVSYS_SWEVT_CHANNEL23_Pos _U_(23) /**< (EVSYS_SWEVT) Channel 23 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL23_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL23_Pos) /**< (EVSYS_SWEVT) Channel 23 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL23(value) (EVSYS_SWEVT_CHANNEL23_Msk & ((value) << EVSYS_SWEVT_CHANNEL23_Pos))
#define EVSYS_SWEVT_CHANNEL24_Pos _U_(24) /**< (EVSYS_SWEVT) Channel 24 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL24_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL24_Pos) /**< (EVSYS_SWEVT) Channel 24 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL24(value) (EVSYS_SWEVT_CHANNEL24_Msk & ((value) << EVSYS_SWEVT_CHANNEL24_Pos))
#define EVSYS_SWEVT_CHANNEL25_Pos _U_(25) /**< (EVSYS_SWEVT) Channel 25 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL25_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL25_Pos) /**< (EVSYS_SWEVT) Channel 25 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL25(value) (EVSYS_SWEVT_CHANNEL25_Msk & ((value) << EVSYS_SWEVT_CHANNEL25_Pos))
#define EVSYS_SWEVT_CHANNEL26_Pos _U_(26) /**< (EVSYS_SWEVT) Channel 26 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL26_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL26_Pos) /**< (EVSYS_SWEVT) Channel 26 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL26(value) (EVSYS_SWEVT_CHANNEL26_Msk & ((value) << EVSYS_SWEVT_CHANNEL26_Pos))
#define EVSYS_SWEVT_CHANNEL27_Pos _U_(27) /**< (EVSYS_SWEVT) Channel 27 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL27_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL27_Pos) /**< (EVSYS_SWEVT) Channel 27 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL27(value) (EVSYS_SWEVT_CHANNEL27_Msk & ((value) << EVSYS_SWEVT_CHANNEL27_Pos))
#define EVSYS_SWEVT_CHANNEL28_Pos _U_(28) /**< (EVSYS_SWEVT) Channel 28 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL28_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL28_Pos) /**< (EVSYS_SWEVT) Channel 28 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL28(value) (EVSYS_SWEVT_CHANNEL28_Msk & ((value) << EVSYS_SWEVT_CHANNEL28_Pos))
#define EVSYS_SWEVT_CHANNEL29_Pos _U_(29) /**< (EVSYS_SWEVT) Channel 29 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL29_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL29_Pos) /**< (EVSYS_SWEVT) Channel 29 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL29(value) (EVSYS_SWEVT_CHANNEL29_Msk & ((value) << EVSYS_SWEVT_CHANNEL29_Pos))
#define EVSYS_SWEVT_CHANNEL30_Pos _U_(30) /**< (EVSYS_SWEVT) Channel 30 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL30_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL30_Pos) /**< (EVSYS_SWEVT) Channel 30 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL30(value) (EVSYS_SWEVT_CHANNEL30_Msk & ((value) << EVSYS_SWEVT_CHANNEL30_Pos))
#define EVSYS_SWEVT_CHANNEL31_Pos _U_(31) /**< (EVSYS_SWEVT) Channel 31 Software Selection Position */
#define EVSYS_SWEVT_CHANNEL31_Msk (_U_(0x1) << EVSYS_SWEVT_CHANNEL31_Pos) /**< (EVSYS_SWEVT) Channel 31 Software Selection Mask */
#define EVSYS_SWEVT_CHANNEL31(value) (EVSYS_SWEVT_CHANNEL31_Msk & ((value) << EVSYS_SWEVT_CHANNEL31_Pos))
#define EVSYS_SWEVT_Msk _U_(0xFFFFFFFF) /**< (EVSYS_SWEVT) Register Mask */
#define EVSYS_SWEVT_CHANNEL_Pos _U_(0) /**< (EVSYS_SWEVT Position) Channel 3x Software Selection */
#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos) /**< (EVSYS_SWEVT Mask) CHANNEL */
#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x08) (R/W 8) Priority Control -------- */
#define EVSYS_PRICTRL_RESETVALUE _U_(0x00) /**< (EVSYS_PRICTRL) Priority Control Reset Value */
#define EVSYS_PRICTRL_PRI_Pos _U_(0) /**< (EVSYS_PRICTRL) Channel Priority Number Position */
#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos) /**< (EVSYS_PRICTRL) Channel Priority Number Mask */
#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
#define EVSYS_PRICTRL_RREN_Pos _U_(7) /**< (EVSYS_PRICTRL) Round-Robin Scheduling Enable Position */
#define EVSYS_PRICTRL_RREN_Msk (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos) /**< (EVSYS_PRICTRL) Round-Robin Scheduling Enable Mask */
#define EVSYS_PRICTRL_RREN(value) (EVSYS_PRICTRL_RREN_Msk & ((value) << EVSYS_PRICTRL_RREN_Pos))
#define EVSYS_PRICTRL_Msk _U_(0x8F) /**< (EVSYS_PRICTRL) Register Mask */
/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x10) (R/W 16) Channel Pending Interrupt -------- */
#define EVSYS_INTPEND_RESETVALUE _U_(0x4000) /**< (EVSYS_INTPEND) Channel Pending Interrupt Reset Value */
#define EVSYS_INTPEND_ID_Pos _U_(0) /**< (EVSYS_INTPEND) Channel ID Position */
#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos) /**< (EVSYS_INTPEND) Channel ID Mask */
#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
#define EVSYS_INTPEND_OVR_Pos _U_(8) /**< (EVSYS_INTPEND) Channel Overrun Position */
#define EVSYS_INTPEND_OVR_Msk (_U_(0x1) << EVSYS_INTPEND_OVR_Pos) /**< (EVSYS_INTPEND) Channel Overrun Mask */
#define EVSYS_INTPEND_OVR(value) (EVSYS_INTPEND_OVR_Msk & ((value) << EVSYS_INTPEND_OVR_Pos))
#define EVSYS_INTPEND_EVD_Pos _U_(9) /**< (EVSYS_INTPEND) Channel Event Detected Position */
#define EVSYS_INTPEND_EVD_Msk (_U_(0x1) << EVSYS_INTPEND_EVD_Pos) /**< (EVSYS_INTPEND) Channel Event Detected Mask */
#define EVSYS_INTPEND_EVD(value) (EVSYS_INTPEND_EVD_Msk & ((value) << EVSYS_INTPEND_EVD_Pos))
#define EVSYS_INTPEND_READY_Pos _U_(14) /**< (EVSYS_INTPEND) Ready Position */
#define EVSYS_INTPEND_READY_Msk (_U_(0x1) << EVSYS_INTPEND_READY_Pos) /**< (EVSYS_INTPEND) Ready Mask */
#define EVSYS_INTPEND_READY(value) (EVSYS_INTPEND_READY_Msk & ((value) << EVSYS_INTPEND_READY_Pos))
#define EVSYS_INTPEND_BUSY_Pos _U_(15) /**< (EVSYS_INTPEND) Busy Position */
#define EVSYS_INTPEND_BUSY_Msk (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos) /**< (EVSYS_INTPEND) Busy Mask */
#define EVSYS_INTPEND_BUSY(value) (EVSYS_INTPEND_BUSY_Msk & ((value) << EVSYS_INTPEND_BUSY_Pos))
#define EVSYS_INTPEND_Msk _U_(0xC30F) /**< (EVSYS_INTPEND) Register Mask */
/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x14) ( R/ 32) Interrupt Status -------- */
#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00) /**< (EVSYS_INTSTATUS) Interrupt Status Reset Value */
#define EVSYS_INTSTATUS_CHINT0_Pos _U_(0) /**< (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT0_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT0_Pos) /**< (EVSYS_INTSTATUS) Channel 0 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT0(value) (EVSYS_INTSTATUS_CHINT0_Msk & ((value) << EVSYS_INTSTATUS_CHINT0_Pos))
#define EVSYS_INTSTATUS_CHINT1_Pos _U_(1) /**< (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT1_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT1_Pos) /**< (EVSYS_INTSTATUS) Channel 1 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT1(value) (EVSYS_INTSTATUS_CHINT1_Msk & ((value) << EVSYS_INTSTATUS_CHINT1_Pos))
#define EVSYS_INTSTATUS_CHINT2_Pos _U_(2) /**< (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT2_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT2_Pos) /**< (EVSYS_INTSTATUS) Channel 2 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT2(value) (EVSYS_INTSTATUS_CHINT2_Msk & ((value) << EVSYS_INTSTATUS_CHINT2_Pos))
#define EVSYS_INTSTATUS_CHINT3_Pos _U_(3) /**< (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT3_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT3_Pos) /**< (EVSYS_INTSTATUS) Channel 3 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT3(value) (EVSYS_INTSTATUS_CHINT3_Msk & ((value) << EVSYS_INTSTATUS_CHINT3_Pos))
#define EVSYS_INTSTATUS_CHINT4_Pos _U_(4) /**< (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT4_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT4_Pos) /**< (EVSYS_INTSTATUS) Channel 4 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT4(value) (EVSYS_INTSTATUS_CHINT4_Msk & ((value) << EVSYS_INTSTATUS_CHINT4_Pos))
#define EVSYS_INTSTATUS_CHINT5_Pos _U_(5) /**< (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT5_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT5_Pos) /**< (EVSYS_INTSTATUS) Channel 5 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT5(value) (EVSYS_INTSTATUS_CHINT5_Msk & ((value) << EVSYS_INTSTATUS_CHINT5_Pos))
#define EVSYS_INTSTATUS_CHINT6_Pos _U_(6) /**< (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT6_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT6_Pos) /**< (EVSYS_INTSTATUS) Channel 6 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT6(value) (EVSYS_INTSTATUS_CHINT6_Msk & ((value) << EVSYS_INTSTATUS_CHINT6_Pos))
#define EVSYS_INTSTATUS_CHINT7_Pos _U_(7) /**< (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT7_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT7_Pos) /**< (EVSYS_INTSTATUS) Channel 7 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT7(value) (EVSYS_INTSTATUS_CHINT7_Msk & ((value) << EVSYS_INTSTATUS_CHINT7_Pos))
#define EVSYS_INTSTATUS_CHINT8_Pos _U_(8) /**< (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT8_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT8_Pos) /**< (EVSYS_INTSTATUS) Channel 8 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT8(value) (EVSYS_INTSTATUS_CHINT8_Msk & ((value) << EVSYS_INTSTATUS_CHINT8_Pos))
#define EVSYS_INTSTATUS_CHINT9_Pos _U_(9) /**< (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT9_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT9_Pos) /**< (EVSYS_INTSTATUS) Channel 9 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT9(value) (EVSYS_INTSTATUS_CHINT9_Msk & ((value) << EVSYS_INTSTATUS_CHINT9_Pos))
#define EVSYS_INTSTATUS_CHINT10_Pos _U_(10) /**< (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT10_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT10_Pos) /**< (EVSYS_INTSTATUS) Channel 10 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT10(value) (EVSYS_INTSTATUS_CHINT10_Msk & ((value) << EVSYS_INTSTATUS_CHINT10_Pos))
#define EVSYS_INTSTATUS_CHINT11_Pos _U_(11) /**< (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Position */
#define EVSYS_INTSTATUS_CHINT11_Msk (_U_(0x1) << EVSYS_INTSTATUS_CHINT11_Pos) /**< (EVSYS_INTSTATUS) Channel 11 Pending Interrupt Mask */
#define EVSYS_INTSTATUS_CHINT11(value) (EVSYS_INTSTATUS_CHINT11_Msk & ((value) << EVSYS_INTSTATUS_CHINT11_Pos))
#define EVSYS_INTSTATUS_Msk _U_(0x00000FFF) /**< (EVSYS_INTSTATUS) Register Mask */
#define EVSYS_INTSTATUS_CHINT_Pos _U_(0) /**< (EVSYS_INTSTATUS Position) Channel xx Pending Interrupt */
#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos) /**< (EVSYS_INTSTATUS Mask) CHINT */
#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x18) ( R/ 32) Busy Channels -------- */
#define EVSYS_BUSYCH_RESETVALUE _U_(0x00) /**< (EVSYS_BUSYCH) Busy Channels Reset Value */
#define EVSYS_BUSYCH_BUSYCH0_Pos _U_(0) /**< (EVSYS_BUSYCH) Busy Channel 0 Position */
#define EVSYS_BUSYCH_BUSYCH0_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH0_Pos) /**< (EVSYS_BUSYCH) Busy Channel 0 Mask */
#define EVSYS_BUSYCH_BUSYCH0(value) (EVSYS_BUSYCH_BUSYCH0_Msk & ((value) << EVSYS_BUSYCH_BUSYCH0_Pos))
#define EVSYS_BUSYCH_BUSYCH1_Pos _U_(1) /**< (EVSYS_BUSYCH) Busy Channel 1 Position */
#define EVSYS_BUSYCH_BUSYCH1_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH1_Pos) /**< (EVSYS_BUSYCH) Busy Channel 1 Mask */
#define EVSYS_BUSYCH_BUSYCH1(value) (EVSYS_BUSYCH_BUSYCH1_Msk & ((value) << EVSYS_BUSYCH_BUSYCH1_Pos))
#define EVSYS_BUSYCH_BUSYCH2_Pos _U_(2) /**< (EVSYS_BUSYCH) Busy Channel 2 Position */
#define EVSYS_BUSYCH_BUSYCH2_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH2_Pos) /**< (EVSYS_BUSYCH) Busy Channel 2 Mask */
#define EVSYS_BUSYCH_BUSYCH2(value) (EVSYS_BUSYCH_BUSYCH2_Msk & ((value) << EVSYS_BUSYCH_BUSYCH2_Pos))
#define EVSYS_BUSYCH_BUSYCH3_Pos _U_(3) /**< (EVSYS_BUSYCH) Busy Channel 3 Position */
#define EVSYS_BUSYCH_BUSYCH3_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH3_Pos) /**< (EVSYS_BUSYCH) Busy Channel 3 Mask */
#define EVSYS_BUSYCH_BUSYCH3(value) (EVSYS_BUSYCH_BUSYCH3_Msk & ((value) << EVSYS_BUSYCH_BUSYCH3_Pos))
#define EVSYS_BUSYCH_BUSYCH4_Pos _U_(4) /**< (EVSYS_BUSYCH) Busy Channel 4 Position */
#define EVSYS_BUSYCH_BUSYCH4_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH4_Pos) /**< (EVSYS_BUSYCH) Busy Channel 4 Mask */
#define EVSYS_BUSYCH_BUSYCH4(value) (EVSYS_BUSYCH_BUSYCH4_Msk & ((value) << EVSYS_BUSYCH_BUSYCH4_Pos))
#define EVSYS_BUSYCH_BUSYCH5_Pos _U_(5) /**< (EVSYS_BUSYCH) Busy Channel 5 Position */
#define EVSYS_BUSYCH_BUSYCH5_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH5_Pos) /**< (EVSYS_BUSYCH) Busy Channel 5 Mask */
#define EVSYS_BUSYCH_BUSYCH5(value) (EVSYS_BUSYCH_BUSYCH5_Msk & ((value) << EVSYS_BUSYCH_BUSYCH5_Pos))
#define EVSYS_BUSYCH_BUSYCH6_Pos _U_(6) /**< (EVSYS_BUSYCH) Busy Channel 6 Position */
#define EVSYS_BUSYCH_BUSYCH6_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH6_Pos) /**< (EVSYS_BUSYCH) Busy Channel 6 Mask */
#define EVSYS_BUSYCH_BUSYCH6(value) (EVSYS_BUSYCH_BUSYCH6_Msk & ((value) << EVSYS_BUSYCH_BUSYCH6_Pos))
#define EVSYS_BUSYCH_BUSYCH7_Pos _U_(7) /**< (EVSYS_BUSYCH) Busy Channel 7 Position */
#define EVSYS_BUSYCH_BUSYCH7_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH7_Pos) /**< (EVSYS_BUSYCH) Busy Channel 7 Mask */
#define EVSYS_BUSYCH_BUSYCH7(value) (EVSYS_BUSYCH_BUSYCH7_Msk & ((value) << EVSYS_BUSYCH_BUSYCH7_Pos))
#define EVSYS_BUSYCH_BUSYCH8_Pos _U_(8) /**< (EVSYS_BUSYCH) Busy Channel 8 Position */
#define EVSYS_BUSYCH_BUSYCH8_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH8_Pos) /**< (EVSYS_BUSYCH) Busy Channel 8 Mask */
#define EVSYS_BUSYCH_BUSYCH8(value) (EVSYS_BUSYCH_BUSYCH8_Msk & ((value) << EVSYS_BUSYCH_BUSYCH8_Pos))
#define EVSYS_BUSYCH_BUSYCH9_Pos _U_(9) /**< (EVSYS_BUSYCH) Busy Channel 9 Position */
#define EVSYS_BUSYCH_BUSYCH9_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH9_Pos) /**< (EVSYS_BUSYCH) Busy Channel 9 Mask */
#define EVSYS_BUSYCH_BUSYCH9(value) (EVSYS_BUSYCH_BUSYCH9_Msk & ((value) << EVSYS_BUSYCH_BUSYCH9_Pos))
#define EVSYS_BUSYCH_BUSYCH10_Pos _U_(10) /**< (EVSYS_BUSYCH) Busy Channel 10 Position */
#define EVSYS_BUSYCH_BUSYCH10_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH10_Pos) /**< (EVSYS_BUSYCH) Busy Channel 10 Mask */
#define EVSYS_BUSYCH_BUSYCH10(value) (EVSYS_BUSYCH_BUSYCH10_Msk & ((value) << EVSYS_BUSYCH_BUSYCH10_Pos))
#define EVSYS_BUSYCH_BUSYCH11_Pos _U_(11) /**< (EVSYS_BUSYCH) Busy Channel 11 Position */
#define EVSYS_BUSYCH_BUSYCH11_Msk (_U_(0x1) << EVSYS_BUSYCH_BUSYCH11_Pos) /**< (EVSYS_BUSYCH) Busy Channel 11 Mask */
#define EVSYS_BUSYCH_BUSYCH11(value) (EVSYS_BUSYCH_BUSYCH11_Msk & ((value) << EVSYS_BUSYCH_BUSYCH11_Pos))
#define EVSYS_BUSYCH_Msk _U_(0x00000FFF) /**< (EVSYS_BUSYCH) Register Mask */
#define EVSYS_BUSYCH_BUSYCH_Pos _U_(0) /**< (EVSYS_BUSYCH Position) Busy Channel xx */
#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos) /**< (EVSYS_BUSYCH Mask) BUSYCH */
#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x1C) ( R/ 32) Ready Users -------- */
#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF) /**< (EVSYS_READYUSR) Ready Users Reset Value */
#define EVSYS_READYUSR_READYUSR0_Pos _U_(0) /**< (EVSYS_READYUSR) Ready User for Channel 0 Position */
#define EVSYS_READYUSR_READYUSR0_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR0_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 0 Mask */
#define EVSYS_READYUSR_READYUSR0(value) (EVSYS_READYUSR_READYUSR0_Msk & ((value) << EVSYS_READYUSR_READYUSR0_Pos))
#define EVSYS_READYUSR_READYUSR1_Pos _U_(1) /**< (EVSYS_READYUSR) Ready User for Channel 1 Position */
#define EVSYS_READYUSR_READYUSR1_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR1_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 1 Mask */
#define EVSYS_READYUSR_READYUSR1(value) (EVSYS_READYUSR_READYUSR1_Msk & ((value) << EVSYS_READYUSR_READYUSR1_Pos))
#define EVSYS_READYUSR_READYUSR2_Pos _U_(2) /**< (EVSYS_READYUSR) Ready User for Channel 2 Position */
#define EVSYS_READYUSR_READYUSR2_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR2_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 2 Mask */
#define EVSYS_READYUSR_READYUSR2(value) (EVSYS_READYUSR_READYUSR2_Msk & ((value) << EVSYS_READYUSR_READYUSR2_Pos))
#define EVSYS_READYUSR_READYUSR3_Pos _U_(3) /**< (EVSYS_READYUSR) Ready User for Channel 3 Position */
#define EVSYS_READYUSR_READYUSR3_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR3_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 3 Mask */
#define EVSYS_READYUSR_READYUSR3(value) (EVSYS_READYUSR_READYUSR3_Msk & ((value) << EVSYS_READYUSR_READYUSR3_Pos))
#define EVSYS_READYUSR_READYUSR4_Pos _U_(4) /**< (EVSYS_READYUSR) Ready User for Channel 4 Position */
#define EVSYS_READYUSR_READYUSR4_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR4_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 4 Mask */
#define EVSYS_READYUSR_READYUSR4(value) (EVSYS_READYUSR_READYUSR4_Msk & ((value) << EVSYS_READYUSR_READYUSR4_Pos))
#define EVSYS_READYUSR_READYUSR5_Pos _U_(5) /**< (EVSYS_READYUSR) Ready User for Channel 5 Position */
#define EVSYS_READYUSR_READYUSR5_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR5_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 5 Mask */
#define EVSYS_READYUSR_READYUSR5(value) (EVSYS_READYUSR_READYUSR5_Msk & ((value) << EVSYS_READYUSR_READYUSR5_Pos))
#define EVSYS_READYUSR_READYUSR6_Pos _U_(6) /**< (EVSYS_READYUSR) Ready User for Channel 6 Position */
#define EVSYS_READYUSR_READYUSR6_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR6_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 6 Mask */
#define EVSYS_READYUSR_READYUSR6(value) (EVSYS_READYUSR_READYUSR6_Msk & ((value) << EVSYS_READYUSR_READYUSR6_Pos))
#define EVSYS_READYUSR_READYUSR7_Pos _U_(7) /**< (EVSYS_READYUSR) Ready User for Channel 7 Position */
#define EVSYS_READYUSR_READYUSR7_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR7_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 7 Mask */
#define EVSYS_READYUSR_READYUSR7(value) (EVSYS_READYUSR_READYUSR7_Msk & ((value) << EVSYS_READYUSR_READYUSR7_Pos))
#define EVSYS_READYUSR_READYUSR8_Pos _U_(8) /**< (EVSYS_READYUSR) Ready User for Channel 8 Position */
#define EVSYS_READYUSR_READYUSR8_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR8_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 8 Mask */
#define EVSYS_READYUSR_READYUSR8(value) (EVSYS_READYUSR_READYUSR8_Msk & ((value) << EVSYS_READYUSR_READYUSR8_Pos))
#define EVSYS_READYUSR_READYUSR9_Pos _U_(9) /**< (EVSYS_READYUSR) Ready User for Channel 9 Position */
#define EVSYS_READYUSR_READYUSR9_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR9_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 9 Mask */
#define EVSYS_READYUSR_READYUSR9(value) (EVSYS_READYUSR_READYUSR9_Msk & ((value) << EVSYS_READYUSR_READYUSR9_Pos))
#define EVSYS_READYUSR_READYUSR10_Pos _U_(10) /**< (EVSYS_READYUSR) Ready User for Channel 10 Position */
#define EVSYS_READYUSR_READYUSR10_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR10_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 10 Mask */
#define EVSYS_READYUSR_READYUSR10(value) (EVSYS_READYUSR_READYUSR10_Msk & ((value) << EVSYS_READYUSR_READYUSR10_Pos))
#define EVSYS_READYUSR_READYUSR11_Pos _U_(11) /**< (EVSYS_READYUSR) Ready User for Channel 11 Position */
#define EVSYS_READYUSR_READYUSR11_Msk (_U_(0x1) << EVSYS_READYUSR_READYUSR11_Pos) /**< (EVSYS_READYUSR) Ready User for Channel 11 Mask */
#define EVSYS_READYUSR_READYUSR11(value) (EVSYS_READYUSR_READYUSR11_Msk & ((value) << EVSYS_READYUSR_READYUSR11_Pos))
#define EVSYS_READYUSR_Msk _U_(0x00000FFF) /**< (EVSYS_READYUSR) Register Mask */
#define EVSYS_READYUSR_READYUSR_Pos _U_(0) /**< (EVSYS_READYUSR Position) Ready User for Channel xx */
#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos) /**< (EVSYS_READYUSR Mask) READYUSR */
#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
#define EVSYS_USER_RESETVALUE _U_(0x00) /**< (EVSYS_USER) User Multiplexer n Reset Value */
#define EVSYS_USER_CHANNEL_Pos _U_(0) /**< (EVSYS_USER) Channel Event Selection Position */
#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos) /**< (EVSYS_USER) Channel Event Selection Mask */
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
#define EVSYS_USER_Msk _U_(0x0000003F) /**< (EVSYS_USER) Register Mask */
/** \brief EVSYS register offsets definitions */
#define EVSYS_CHANNEL_REG_OFST (0x00) /**< (EVSYS_CHANNEL) Channel n Control Offset */
#define EVSYS_CHINTENCLR_REG_OFST (0x04) /**< (EVSYS_CHINTENCLR) Channel n Interrupt Enable Clear Offset */
#define EVSYS_CHINTENSET_REG_OFST (0x05) /**< (EVSYS_CHINTENSET) Channel n Interrupt Enable Set Offset */
#define EVSYS_CHINTFLAG_REG_OFST (0x06) /**< (EVSYS_CHINTFLAG) Channel n Interrupt Flag Status and Clear Offset */
#define EVSYS_CHSTATUS_REG_OFST (0x07) /**< (EVSYS_CHSTATUS) Channel n Status Offset */
#define EVSYS_CTRLA_REG_OFST (0x00) /**< (EVSYS_CTRLA) Control Offset */
#define EVSYS_SWEVT_REG_OFST (0x04) /**< (EVSYS_SWEVT) Software Event Offset */
#define EVSYS_PRICTRL_REG_OFST (0x08) /**< (EVSYS_PRICTRL) Priority Control Offset */
#define EVSYS_INTPEND_REG_OFST (0x10) /**< (EVSYS_INTPEND) Channel Pending Interrupt Offset */
#define EVSYS_INTSTATUS_REG_OFST (0x14) /**< (EVSYS_INTSTATUS) Interrupt Status Offset */
#define EVSYS_BUSYCH_REG_OFST (0x18) /**< (EVSYS_BUSYCH) Busy Channels Offset */
#define EVSYS_READYUSR_REG_OFST (0x1C) /**< (EVSYS_READYUSR) Ready Users Offset */
#define EVSYS_USER_REG_OFST (0x120) /**< (EVSYS_USER) User Multiplexer n Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief CHANNEL register API structure */
typedef struct
{
__IO uint32_t EVSYS_CHANNEL; /**< Offset: 0x00 (R/W 32) Channel n Control */
__IO uint8_t EVSYS_CHINTENCLR; /**< Offset: 0x04 (R/W 8) Channel n Interrupt Enable Clear */
__IO uint8_t EVSYS_CHINTENSET; /**< Offset: 0x05 (R/W 8) Channel n Interrupt Enable Set */
__IO uint8_t EVSYS_CHINTFLAG; /**< Offset: 0x06 (R/W 8) Channel n Interrupt Flag Status and Clear */
__I uint8_t EVSYS_CHSTATUS; /**< Offset: 0x07 (R/ 8) Channel n Status */
} evsys_channel_registers_t;
#define EVSYS_CHANNEL_NUMBER _U_(32)
/** \brief EVSYS register API structure */
typedef struct
{ /* Event System Interface */
__IO uint8_t EVSYS_CTRLA; /**< Offset: 0x00 (R/W 8) Control */
__I uint8_t Reserved1[0x03];
__O uint32_t EVSYS_SWEVT; /**< Offset: 0x04 ( /W 32) Software Event */
__IO uint8_t EVSYS_PRICTRL; /**< Offset: 0x08 (R/W 8) Priority Control */
__I uint8_t Reserved2[0x07];
__IO uint16_t EVSYS_INTPEND; /**< Offset: 0x10 (R/W 16) Channel Pending Interrupt */
__I uint8_t Reserved3[0x02];
__I uint32_t EVSYS_INTSTATUS; /**< Offset: 0x14 (R/ 32) Interrupt Status */
__I uint32_t EVSYS_BUSYCH; /**< Offset: 0x18 (R/ 32) Busy Channels */
__I uint32_t EVSYS_READYUSR; /**< Offset: 0x1C (R/ 32) Ready Users */
evsys_channel_registers_t CHANNEL[EVSYS_CHANNEL_NUMBER]; /**< Offset: 0x20 */
__IO uint32_t EVSYS_USER[67]; /**< Offset: 0x120 (R/W 32) User Multiplexer n */
} evsys_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_EVSYS_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/freqm.h
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/**
* \brief Component description for FREQM
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_FREQM_COMPONENT_H_
#define _SAMD51_FREQM_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR FREQM */
/* ************************************************************************** */
/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< (FREQM_CTRLA) Control A Register Reset Value */
#define FREQM_CTRLA_SWRST_Pos _U_(0) /**< (FREQM_CTRLA) Software Reset Position */
#define FREQM_CTRLA_SWRST_Msk (_U_(0x1) << FREQM_CTRLA_SWRST_Pos) /**< (FREQM_CTRLA) Software Reset Mask */
#define FREQM_CTRLA_SWRST(value) (FREQM_CTRLA_SWRST_Msk & ((value) << FREQM_CTRLA_SWRST_Pos))
#define FREQM_CTRLA_ENABLE_Pos _U_(1) /**< (FREQM_CTRLA) Enable Position */
#define FREQM_CTRLA_ENABLE_Msk (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos) /**< (FREQM_CTRLA) Enable Mask */
#define FREQM_CTRLA_ENABLE(value) (FREQM_CTRLA_ENABLE_Msk & ((value) << FREQM_CTRLA_ENABLE_Pos))
#define FREQM_CTRLA_Msk _U_(0x03) /**< (FREQM_CTRLA) Register Mask */
/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< (FREQM_CTRLB) Control B Register Reset Value */
#define FREQM_CTRLB_START_Pos _U_(0) /**< (FREQM_CTRLB) Start Measurement Position */
#define FREQM_CTRLB_START_Msk (_U_(0x1) << FREQM_CTRLB_START_Pos) /**< (FREQM_CTRLB) Start Measurement Mask */
#define FREQM_CTRLB_START(value) (FREQM_CTRLB_START_Msk & ((value) << FREQM_CTRLB_START_Pos))
#define FREQM_CTRLB_Msk _U_(0x01) /**< (FREQM_CTRLB) Register Mask */
/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
#define FREQM_CFGA_RESETVALUE _U_(0x00) /**< (FREQM_CFGA) Config A register Reset Value */
#define FREQM_CFGA_REFNUM_Pos _U_(0) /**< (FREQM_CFGA) Number of Reference Clock Cycles Position */
#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos) /**< (FREQM_CFGA) Number of Reference Clock Cycles Mask */
#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
#define FREQM_CFGA_Msk _U_(0x00FF) /**< (FREQM_CFGA) Register Mask */
/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< (FREQM_INTENCLR) Interrupt Enable Clear Register Reset Value */
#define FREQM_INTENCLR_DONE_Pos _U_(0) /**< (FREQM_INTENCLR) Measurement Done Interrupt Enable Position */
#define FREQM_INTENCLR_DONE_Msk (_U_(0x1) << FREQM_INTENCLR_DONE_Pos) /**< (FREQM_INTENCLR) Measurement Done Interrupt Enable Mask */
#define FREQM_INTENCLR_DONE(value) (FREQM_INTENCLR_DONE_Msk & ((value) << FREQM_INTENCLR_DONE_Pos))
#define FREQM_INTENCLR_Msk _U_(0x01) /**< (FREQM_INTENCLR) Register Mask */
/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< (FREQM_INTENSET) Interrupt Enable Set Register Reset Value */
#define FREQM_INTENSET_DONE_Pos _U_(0) /**< (FREQM_INTENSET) Measurement Done Interrupt Enable Position */
#define FREQM_INTENSET_DONE_Msk (_U_(0x1) << FREQM_INTENSET_DONE_Pos) /**< (FREQM_INTENSET) Measurement Done Interrupt Enable Mask */
#define FREQM_INTENSET_DONE(value) (FREQM_INTENSET_DONE_Msk & ((value) << FREQM_INTENSET_DONE_Pos))
#define FREQM_INTENSET_Msk _U_(0x01) /**< (FREQM_INTENSET) Register Mask */
/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< (FREQM_INTFLAG) Interrupt Flag Register Reset Value */
#define FREQM_INTFLAG_DONE_Pos _U_(0) /**< (FREQM_INTFLAG) Measurement Done Position */
#define FREQM_INTFLAG_DONE_Msk (_U_(0x1) << FREQM_INTFLAG_DONE_Pos) /**< (FREQM_INTFLAG) Measurement Done Mask */
#define FREQM_INTFLAG_DONE(value) (FREQM_INTFLAG_DONE_Msk & ((value) << FREQM_INTFLAG_DONE_Pos))
#define FREQM_INTFLAG_Msk _U_(0x01) /**< (FREQM_INTFLAG) Register Mask */
/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< (FREQM_STATUS) Status Register Reset Value */
#define FREQM_STATUS_BUSY_Pos _U_(0) /**< (FREQM_STATUS) FREQM Status Position */
#define FREQM_STATUS_BUSY_Msk (_U_(0x1) << FREQM_STATUS_BUSY_Pos) /**< (FREQM_STATUS) FREQM Status Mask */
#define FREQM_STATUS_BUSY(value) (FREQM_STATUS_BUSY_Msk & ((value) << FREQM_STATUS_BUSY_Pos))
#define FREQM_STATUS_OVF_Pos _U_(1) /**< (FREQM_STATUS) Sticky Count Value Overflow Position */
#define FREQM_STATUS_OVF_Msk (_U_(0x1) << FREQM_STATUS_OVF_Pos) /**< (FREQM_STATUS) Sticky Count Value Overflow Mask */
#define FREQM_STATUS_OVF(value) (FREQM_STATUS_OVF_Msk & ((value) << FREQM_STATUS_OVF_Pos))
#define FREQM_STATUS_Msk _U_(0x03) /**< (FREQM_STATUS) Register Mask */
/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) ( R/ 32) Synchronization Busy Register -------- */
#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00) /**< (FREQM_SYNCBUSY) Synchronization Busy Register Reset Value */
#define FREQM_SYNCBUSY_SWRST_Pos _U_(0) /**< (FREQM_SYNCBUSY) Software Reset Position */
#define FREQM_SYNCBUSY_SWRST_Msk (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos) /**< (FREQM_SYNCBUSY) Software Reset Mask */
#define FREQM_SYNCBUSY_SWRST(value) (FREQM_SYNCBUSY_SWRST_Msk & ((value) << FREQM_SYNCBUSY_SWRST_Pos))
#define FREQM_SYNCBUSY_ENABLE_Pos _U_(1) /**< (FREQM_SYNCBUSY) Enable Position */
#define FREQM_SYNCBUSY_ENABLE_Msk (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos) /**< (FREQM_SYNCBUSY) Enable Mask */
#define FREQM_SYNCBUSY_ENABLE(value) (FREQM_SYNCBUSY_ENABLE_Msk & ((value) << FREQM_SYNCBUSY_ENABLE_Pos))
#define FREQM_SYNCBUSY_Msk _U_(0x00000003) /**< (FREQM_SYNCBUSY) Register Mask */
/* -------- FREQM_VALUE : (FREQM Offset: 0x10) ( R/ 32) Count Value Register -------- */
#define FREQM_VALUE_RESETVALUE _U_(0x00) /**< (FREQM_VALUE) Count Value Register Reset Value */
#define FREQM_VALUE_VALUE_Pos _U_(0) /**< (FREQM_VALUE) Measurement Value Position */
#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) /**< (FREQM_VALUE) Measurement Value Mask */
#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
#define FREQM_VALUE_Msk _U_(0x00FFFFFF) /**< (FREQM_VALUE) Register Mask */
/** \brief FREQM register offsets definitions */
#define FREQM_CTRLA_REG_OFST (0x00) /**< (FREQM_CTRLA) Control A Register Offset */
#define FREQM_CTRLB_REG_OFST (0x01) /**< (FREQM_CTRLB) Control B Register Offset */
#define FREQM_CFGA_REG_OFST (0x02) /**< (FREQM_CFGA) Config A register Offset */
#define FREQM_INTENCLR_REG_OFST (0x08) /**< (FREQM_INTENCLR) Interrupt Enable Clear Register Offset */
#define FREQM_INTENSET_REG_OFST (0x09) /**< (FREQM_INTENSET) Interrupt Enable Set Register Offset */
#define FREQM_INTFLAG_REG_OFST (0x0A) /**< (FREQM_INTFLAG) Interrupt Flag Register Offset */
#define FREQM_STATUS_REG_OFST (0x0B) /**< (FREQM_STATUS) Status Register Offset */
#define FREQM_SYNCBUSY_REG_OFST (0x0C) /**< (FREQM_SYNCBUSY) Synchronization Busy Register Offset */
#define FREQM_VALUE_REG_OFST (0x10) /**< (FREQM_VALUE) Count Value Register Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief FREQM register API structure */
typedef struct
{ /* Frequency Meter */
__IO uint8_t FREQM_CTRLA; /**< Offset: 0x00 (R/W 8) Control A Register */
__O uint8_t FREQM_CTRLB; /**< Offset: 0x01 ( /W 8) Control B Register */
__IO uint16_t FREQM_CFGA; /**< Offset: 0x02 (R/W 16) Config A register */
__I uint8_t Reserved1[0x04];
__IO uint8_t FREQM_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
__IO uint8_t FREQM_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
__IO uint8_t FREQM_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Register */
__IO uint8_t FREQM_STATUS; /**< Offset: 0x0B (R/W 8) Status Register */
__I uint32_t FREQM_SYNCBUSY; /**< Offset: 0x0C (R/ 32) Synchronization Busy Register */
__I uint32_t FREQM_VALUE; /**< Offset: 0x10 (R/ 32) Count Value Register */
} freqm_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_FREQM_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/gclk.h
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/**
* \brief Component description for GCLK
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_GCLK_COMPONENT_H_
#define _SAMD51_GCLK_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR GCLK */
/* ************************************************************************** */
/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< (GCLK_CTRLA) Control Reset Value */
#define GCLK_CTRLA_SWRST_Pos _U_(0) /**< (GCLK_CTRLA) Software Reset Position */
#define GCLK_CTRLA_SWRST_Msk (_U_(0x1) << GCLK_CTRLA_SWRST_Pos) /**< (GCLK_CTRLA) Software Reset Mask */
#define GCLK_CTRLA_SWRST(value) (GCLK_CTRLA_SWRST_Msk & ((value) << GCLK_CTRLA_SWRST_Pos))
#define GCLK_CTRLA_Msk _U_(0x01) /**< (GCLK_CTRLA) Register Mask */
/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) ( R/ 32) Synchronization Busy -------- */
#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00) /**< (GCLK_SYNCBUSY) Synchronization Busy Reset Value */
#define GCLK_SYNCBUSY_SWRST_Pos _U_(0) /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Position */
#define GCLK_SYNCBUSY_SWRST_Msk (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos) /**< (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit Mask */
#define GCLK_SYNCBUSY_SWRST(value) (GCLK_SYNCBUSY_SWRST_Msk & ((value) << GCLK_SYNCBUSY_SWRST_Pos))
#define GCLK_SYNCBUSY_GENCTRL_Pos _U_(2) /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Position */
#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic Clock Generator Control n Synchronization Busy bits Mask */
#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< (GCLK_SYNCBUSY) Generic clock generator 0 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< (GCLK_SYNCBUSY) Generic clock generator 1 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< (GCLK_SYNCBUSY) Generic clock generator 2 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< (GCLK_SYNCBUSY) Generic clock generator 3 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< (GCLK_SYNCBUSY) Generic clock generator 4 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< (GCLK_SYNCBUSY) Generic clock generator 5 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< (GCLK_SYNCBUSY) Generic clock generator 6 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< (GCLK_SYNCBUSY) Generic clock generator 7 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< (GCLK_SYNCBUSY) Generic clock generator 8 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200) /**< (GCLK_SYNCBUSY) Generic clock generator 9 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400) /**< (GCLK_SYNCBUSY) Generic clock generator 10 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800) /**< (GCLK_SYNCBUSY) Generic clock generator 11 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 0 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 1 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 2 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 3 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 4 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 5 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 6 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 7 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 8 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 9 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 10 Position */
#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos) /**< (GCLK_SYNCBUSY) Generic clock generator 11 Position */
#define GCLK_SYNCBUSY_Msk _U_(0x00003FFD) /**< (GCLK_SYNCBUSY) Register Mask */
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
#define GCLK_GENCTRL_RESETVALUE _U_(0x00) /**< (GCLK_GENCTRL) Generic Clock Generator Control Reset Value */
#define GCLK_GENCTRL_SRC_Pos _U_(0) /**< (GCLK_GENCTRL) Source Select Position */
#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Source Select Mask */
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0) /**< (GCLK_GENCTRL) XOSC0 oscillator output */
#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1) /**< (GCLK_GENCTRL) XOSC1 oscillator output */
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2) /**< (GCLK_GENCTRL) Generator input pad */
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3) /**< (GCLK_GENCTRL) Generic clock generator 1 output */
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4) /**< (GCLK_GENCTRL) OSCULP32K oscillator output */
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< (GCLK_GENCTRL) XOSC32K oscillator output */
#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6) /**< (GCLK_GENCTRL) DFLL output */
#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7) /**< (GCLK_GENCTRL) DPLL0 output */
#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8) /**< (GCLK_GENCTRL) DPLL1 output */
#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC0 oscillator output Position */
#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC1 oscillator output Position */
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generator input pad Position */
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generic clock generator 1 output Position */
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSCULP32K oscillator output Position */
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC32K oscillator output Position */
#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DFLL output Position */
#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL0 output Position */
#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL1 output Position */
#define GCLK_GENCTRL_GENEN_Pos _U_(8) /**< (GCLK_GENCTRL) Generic Clock Generator Enable Position */
#define GCLK_GENCTRL_GENEN_Msk (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos) /**< (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
#define GCLK_GENCTRL_GENEN(value) (GCLK_GENCTRL_GENEN_Msk & ((value) << GCLK_GENCTRL_GENEN_Pos))
#define GCLK_GENCTRL_IDC_Pos _U_(9) /**< (GCLK_GENCTRL) Improve Duty Cycle Position */
#define GCLK_GENCTRL_IDC_Msk (_U_(0x1) << GCLK_GENCTRL_IDC_Pos) /**< (GCLK_GENCTRL) Improve Duty Cycle Mask */
#define GCLK_GENCTRL_IDC(value) (GCLK_GENCTRL_IDC_Msk & ((value) << GCLK_GENCTRL_IDC_Pos))
#define GCLK_GENCTRL_OOV_Pos _U_(10) /**< (GCLK_GENCTRL) Output Off Value Position */
#define GCLK_GENCTRL_OOV_Msk (_U_(0x1) << GCLK_GENCTRL_OOV_Pos) /**< (GCLK_GENCTRL) Output Off Value Mask */
#define GCLK_GENCTRL_OOV(value) (GCLK_GENCTRL_OOV_Msk & ((value) << GCLK_GENCTRL_OOV_Pos))
#define GCLK_GENCTRL_OE_Pos _U_(11) /**< (GCLK_GENCTRL) Output Enable Position */
#define GCLK_GENCTRL_OE_Msk (_U_(0x1) << GCLK_GENCTRL_OE_Pos) /**< (GCLK_GENCTRL) Output Enable Mask */
#define GCLK_GENCTRL_OE(value) (GCLK_GENCTRL_OE_Msk & ((value) << GCLK_GENCTRL_OE_Pos))
#define GCLK_GENCTRL_DIVSEL_Pos _U_(12) /**< (GCLK_GENCTRL) Divide Selection Position */
#define GCLK_GENCTRL_DIVSEL_Msk (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide Selection Mask */
#define GCLK_GENCTRL_DIVSEL(value) (GCLK_GENCTRL_DIVSEL_Msk & ((value) << GCLK_GENCTRL_DIVSEL_Pos))
#define GCLK_GENCTRL_DIVSEL_DIV1_Val _U_(0x0) /**< (GCLK_GENCTRL) Divide input directly by divider factor */
#define GCLK_GENCTRL_DIVSEL_DIV2_Val _U_(0x1) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) */
#define GCLK_GENCTRL_DIVSEL_DIV1 (GCLK_GENCTRL_DIVSEL_DIV1_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input directly by divider factor Position */
#define GCLK_GENCTRL_DIVSEL_DIV2 (GCLK_GENCTRL_DIVSEL_DIV2_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) Position */
#define GCLK_GENCTRL_RUNSTDBY_Pos _U_(13) /**< (GCLK_GENCTRL) Run in Standby Position */
#define GCLK_GENCTRL_RUNSTDBY_Msk (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos) /**< (GCLK_GENCTRL) Run in Standby Mask */
#define GCLK_GENCTRL_RUNSTDBY(value) (GCLK_GENCTRL_RUNSTDBY_Msk & ((value) << GCLK_GENCTRL_RUNSTDBY_Pos))
#define GCLK_GENCTRL_DIV_Pos _U_(16) /**< (GCLK_GENCTRL) Division Factor Position */
#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos) /**< (GCLK_GENCTRL) Division Factor Mask */
#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
#define GCLK_GENCTRL_Msk _U_(0xFFFF3F0F) /**< (GCLK_GENCTRL) Register Mask */
/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
#define GCLK_PCHCTRL_RESETVALUE _U_(0x00) /**< (GCLK_PCHCTRL) Peripheral Clock Control Reset Value */
#define GCLK_PCHCTRL_GEN_Pos _U_(0) /**< (GCLK_PCHCTRL) Generic Clock Generator Position */
#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic Clock Generator Mask */
#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< (GCLK_PCHCTRL) Generic clock generator 0 */
#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< (GCLK_PCHCTRL) Generic clock generator 1 */
#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< (GCLK_PCHCTRL) Generic clock generator 2 */
#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< (GCLK_PCHCTRL) Generic clock generator 3 */
#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< (GCLK_PCHCTRL) Generic clock generator 4 */
#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< (GCLK_PCHCTRL) Generic clock generator 5 */
#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< (GCLK_PCHCTRL) Generic clock generator 6 */
#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< (GCLK_PCHCTRL) Generic clock generator 7 */
#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< (GCLK_PCHCTRL) Generic clock generator 8 */
#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9) /**< (GCLK_PCHCTRL) Generic clock generator 9 */
#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA) /**< (GCLK_PCHCTRL) Generic clock generator 10 */
#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB) /**< (GCLK_PCHCTRL) Generic clock generator 11 */
#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 0 Position */
#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 1 Position */
#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 2 Position */
#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 3 Position */
#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 4 Position */
#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 5 Position */
#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 6 Position */
#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 7 Position */
#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 8 Position */
#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 9 Position */
#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 10 Position */
#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos) /**< (GCLK_PCHCTRL) Generic clock generator 11 Position */
#define GCLK_PCHCTRL_CHEN_Pos _U_(6) /**< (GCLK_PCHCTRL) Channel Enable Position */
#define GCLK_PCHCTRL_CHEN_Msk (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos) /**< (GCLK_PCHCTRL) Channel Enable Mask */
#define GCLK_PCHCTRL_CHEN(value) (GCLK_PCHCTRL_CHEN_Msk & ((value) << GCLK_PCHCTRL_CHEN_Pos))
#define GCLK_PCHCTRL_WRTLOCK_Pos _U_(7) /**< (GCLK_PCHCTRL) Write Lock Position */
#define GCLK_PCHCTRL_WRTLOCK_Msk (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos) /**< (GCLK_PCHCTRL) Write Lock Mask */
#define GCLK_PCHCTRL_WRTLOCK(value) (GCLK_PCHCTRL_WRTLOCK_Msk & ((value) << GCLK_PCHCTRL_WRTLOCK_Pos))
#define GCLK_PCHCTRL_Msk _U_(0x000000CF) /**< (GCLK_PCHCTRL) Register Mask */
/** \brief GCLK register offsets definitions */
#define GCLK_CTRLA_REG_OFST (0x00) /**< (GCLK_CTRLA) Control Offset */
#define GCLK_SYNCBUSY_REG_OFST (0x04) /**< (GCLK_SYNCBUSY) Synchronization Busy Offset */
#define GCLK_GENCTRL_REG_OFST (0x20) /**< (GCLK_GENCTRL) Generic Clock Generator Control Offset */
#define GCLK_PCHCTRL_REG_OFST (0x80) /**< (GCLK_PCHCTRL) Peripheral Clock Control Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief GCLK register API structure */
typedef struct
{ /* Generic Clock Generator */
__IO uint8_t GCLK_CTRLA; /**< Offset: 0x00 (R/W 8) Control */
__I uint8_t Reserved1[0x03];
__I uint32_t GCLK_SYNCBUSY; /**< Offset: 0x04 (R/ 32) Synchronization Busy */
__I uint8_t Reserved2[0x18];
__IO uint32_t GCLK_GENCTRL[12]; /**< Offset: 0x20 (R/W 32) Generic Clock Generator Control */
__I uint8_t Reserved3[0x30];
__IO uint32_t GCLK_PCHCTRL[48]; /**< Offset: 0x80 (R/W 32) Peripheral Clock Control */
} gclk_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_GCLK_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/hmatrixb.h
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/**
* \brief Component description for HMATRIXB
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_HMATRIXB_COMPONENT_H_
#define _SAMD51_HMATRIXB_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR HMATRIXB */
/* ************************************************************************** */
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x00) (R/W 32) Priority A for Slave -------- */
#define HMATRIXB_PRAS_RESETVALUE _U_(0x00) /**< (HMATRIXB_PRAS) Priority A for Slave Reset Value */
#define HMATRIXB_PRAS_Msk _U_(0x00000000) /**< (HMATRIXB_PRAS) Register Mask */
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x04) (R/W 32) Priority B for Slave -------- */
#define HMATRIXB_PRBS_RESETVALUE _U_(0x00) /**< (HMATRIXB_PRBS) Priority B for Slave Reset Value */
#define HMATRIXB_PRBS_Msk _U_(0x00000000) /**< (HMATRIXB_PRBS) Register Mask */
/** \brief HMATRIXB register offsets definitions */
#define HMATRIXB_PRAS_REG_OFST (0x00) /**< (HMATRIXB_PRAS) Priority A for Slave Offset */
#define HMATRIXB_PRBS_REG_OFST (0x04) /**< (HMATRIXB_PRBS) Priority B for Slave Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief PRS register API structure */
typedef struct
{
__IO uint32_t HMATRIXB_PRAS; /**< Offset: 0x00 (R/W 32) Priority A for Slave */
__IO uint32_t HMATRIXB_PRBS; /**< Offset: 0x04 (R/W 32) Priority B for Slave */
} hmatrixb_prs_registers_t;
#define HMATRIXB_PRS_NUMBER _U_(16)
/** \brief HMATRIXB register API structure */
typedef struct
{ /* HSB Matrix */
__I uint8_t Reserved1[0x80];
hmatrixb_prs_registers_t PRS[HMATRIXB_PRS_NUMBER]; /**< Offset: 0x80 */
} hmatrixb_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_HMATRIXB_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/i2s.h
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/**
* \brief Component description for I2S
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_I2S_COMPONENT_H_
#define _SAMD51_I2S_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR I2S */
/* ************************************************************************** */
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#define I2S_CTRLA_RESETVALUE _U_(0x00) /**< (I2S_CTRLA) Control A Reset Value */
#define I2S_CTRLA_SWRST_Pos _U_(0) /**< (I2S_CTRLA) Software Reset Position */
#define I2S_CTRLA_SWRST_Msk (_U_(0x1) << I2S_CTRLA_SWRST_Pos) /**< (I2S_CTRLA) Software Reset Mask */
#define I2S_CTRLA_SWRST(value) (I2S_CTRLA_SWRST_Msk & ((value) << I2S_CTRLA_SWRST_Pos))
#define I2S_CTRLA_ENABLE_Pos _U_(1) /**< (I2S_CTRLA) Enable Position */
#define I2S_CTRLA_ENABLE_Msk (_U_(0x1) << I2S_CTRLA_ENABLE_Pos) /**< (I2S_CTRLA) Enable Mask */
#define I2S_CTRLA_ENABLE(value) (I2S_CTRLA_ENABLE_Msk & ((value) << I2S_CTRLA_ENABLE_Pos))
#define I2S_CTRLA_CKEN0_Pos _U_(2) /**< (I2S_CTRLA) Clock Unit 0 Enable Position */
#define I2S_CTRLA_CKEN0_Msk (_U_(0x1) << I2S_CTRLA_CKEN0_Pos) /**< (I2S_CTRLA) Clock Unit 0 Enable Mask */
#define I2S_CTRLA_CKEN0(value) (I2S_CTRLA_CKEN0_Msk & ((value) << I2S_CTRLA_CKEN0_Pos))
#define I2S_CTRLA_CKEN1_Pos _U_(3) /**< (I2S_CTRLA) Clock Unit 1 Enable Position */
#define I2S_CTRLA_CKEN1_Msk (_U_(0x1) << I2S_CTRLA_CKEN1_Pos) /**< (I2S_CTRLA) Clock Unit 1 Enable Mask */
#define I2S_CTRLA_CKEN1(value) (I2S_CTRLA_CKEN1_Msk & ((value) << I2S_CTRLA_CKEN1_Pos))
#define I2S_CTRLA_TXEN_Pos _U_(4) /**< (I2S_CTRLA) Tx Serializer Enable Position */
#define I2S_CTRLA_TXEN_Msk (_U_(0x1) << I2S_CTRLA_TXEN_Pos) /**< (I2S_CTRLA) Tx Serializer Enable Mask */
#define I2S_CTRLA_TXEN(value) (I2S_CTRLA_TXEN_Msk & ((value) << I2S_CTRLA_TXEN_Pos))
#define I2S_CTRLA_RXEN_Pos _U_(5) /**< (I2S_CTRLA) Rx Serializer Enable Position */
#define I2S_CTRLA_RXEN_Msk (_U_(0x1) << I2S_CTRLA_RXEN_Pos) /**< (I2S_CTRLA) Rx Serializer Enable Mask */
#define I2S_CTRLA_RXEN(value) (I2S_CTRLA_RXEN_Msk & ((value) << I2S_CTRLA_RXEN_Pos))
#define I2S_CTRLA_Msk _U_(0x3F) /**< (I2S_CTRLA) Register Mask */
#define I2S_CTRLA_CKEN_Pos _U_(2) /**< (I2S_CTRLA Position) Clock Unit x Enable */
#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos) /**< (I2S_CTRLA Mask) CKEN */
#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#define I2S_CLKCTRL_RESETVALUE _U_(0x00) /**< (I2S_CLKCTRL) Clock Unit n Control Reset Value */
#define I2S_CLKCTRL_SLOTSIZE_Pos _U_(0) /**< (I2S_CLKCTRL) Slot Size Position */
#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) Slot Size Mask */
#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 8-bit Slot for Clock Unit n Position */
#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 16-bit Slot for Clock Unit n Position */
#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 24-bit Slot for Clock Unit n Position */
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 32-bit Slot for Clock Unit n Position */
#define I2S_CLKCTRL_NBSLOTS_Pos _U_(2) /**< (I2S_CLKCTRL) Number of Slots in Frame Position */
#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos) /**< (I2S_CLKCTRL) Number of Slots in Frame Mask */
#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
#define I2S_CLKCTRL_FSWIDTH_Pos _U_(5) /**< (I2S_CLKCTRL) Frame Sync Width Position */
#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Width Mask */
#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) Position */
#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide Position */
#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide Position */
#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested Position */
#define I2S_CLKCTRL_BITDELAY_Pos _U_(7) /**< (I2S_CLKCTRL) Data Delay from Frame Sync Position */
#define I2S_CLKCTRL_BITDELAY_Msk (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos) /**< (I2S_CLKCTRL) Data Delay from Frame Sync Mask */
#define I2S_CLKCTRL_BITDELAY(value) (I2S_CLKCTRL_BITDELAY_Msk & ((value) << I2S_CLKCTRL_BITDELAY_Pos))
#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< (I2S_CLKCTRL) I2S (1 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) /**< (I2S_CLKCTRL) Left Justified (0 Bit Delay) Position */
#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) /**< (I2S_CLKCTRL) I2S (1 Bit Delay) Position */
#define I2S_CLKCTRL_FSSEL_Pos _U_(8) /**< (I2S_CLKCTRL) Frame Sync Select Position */
#define I2S_CLKCTRL_FSSEL_Msk (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos) /**< (I2S_CLKCTRL) Frame Sync Select Mask */
#define I2S_CLKCTRL_FSSEL(value) (I2S_CLKCTRL_FSSEL_Msk & ((value) << I2S_CLKCTRL_FSSEL_Pos))
#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) /**< (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source Position */
#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) /**< (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source Position */
#define I2S_CLKCTRL_FSINV_Pos _U_(9) /**< (I2S_CLKCTRL) Frame Sync Invert Position */
#define I2S_CLKCTRL_FSINV_Msk (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos) /**< (I2S_CLKCTRL) Frame Sync Invert Mask */
#define I2S_CLKCTRL_FSINV(value) (I2S_CLKCTRL_FSINV_Msk & ((value) << I2S_CLKCTRL_FSINV_Pos))
#define I2S_CLKCTRL_FSOUTINV_Pos _U_(10) /**< (I2S_CLKCTRL) Frame Sync Output Invert Position */
#define I2S_CLKCTRL_FSOUTINV_Msk (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos) /**< (I2S_CLKCTRL) Frame Sync Output Invert Mask */
#define I2S_CLKCTRL_FSOUTINV(value) (I2S_CLKCTRL_FSOUTINV_Msk & ((value) << I2S_CLKCTRL_FSOUTINV_Pos))
#define I2S_CLKCTRL_SCKSEL_Pos _U_(11) /**< (I2S_CLKCTRL) Serial Clock Select Position */
#define I2S_CLKCTRL_SCKSEL_Msk (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos) /**< (I2S_CLKCTRL) Serial Clock Select Mask */
#define I2S_CLKCTRL_SCKSEL(value) (I2S_CLKCTRL_SCKSEL_Msk & ((value) << I2S_CLKCTRL_SCKSEL_Pos))
#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) /**< (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source Position */
#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) /**< (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source Position */
#define I2S_CLKCTRL_SCKOUTINV_Pos _U_(12) /**< (I2S_CLKCTRL) Serial Clock Output Invert Position */
#define I2S_CLKCTRL_SCKOUTINV_Msk (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos) /**< (I2S_CLKCTRL) Serial Clock Output Invert Mask */
#define I2S_CLKCTRL_SCKOUTINV(value) (I2S_CLKCTRL_SCKOUTINV_Msk & ((value) << I2S_CLKCTRL_SCKOUTINV_Pos))
#define I2S_CLKCTRL_MCKSEL_Pos _U_(13) /**< (I2S_CLKCTRL) Master Clock Select Position */
#define I2S_CLKCTRL_MCKSEL_Msk (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos) /**< (I2S_CLKCTRL) Master Clock Select Mask */
#define I2S_CLKCTRL_MCKSEL(value) (I2S_CLKCTRL_MCKSEL_Msk & ((value) << I2S_CLKCTRL_MCKSEL_Pos))
#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) /**< (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source Position */
#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) /**< (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source Position */
#define I2S_CLKCTRL_MCKEN_Pos _U_(14) /**< (I2S_CLKCTRL) Master Clock Enable Position */
#define I2S_CLKCTRL_MCKEN_Msk (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos) /**< (I2S_CLKCTRL) Master Clock Enable Mask */
#define I2S_CLKCTRL_MCKEN(value) (I2S_CLKCTRL_MCKEN_Msk & ((value) << I2S_CLKCTRL_MCKEN_Pos))
#define I2S_CLKCTRL_MCKOUTINV_Pos _U_(15) /**< (I2S_CLKCTRL) Master Clock Output Invert Position */
#define I2S_CLKCTRL_MCKOUTINV_Msk (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos) /**< (I2S_CLKCTRL) Master Clock Output Invert Mask */
#define I2S_CLKCTRL_MCKOUTINV(value) (I2S_CLKCTRL_MCKOUTINV_Msk & ((value) << I2S_CLKCTRL_MCKOUTINV_Pos))
#define I2S_CLKCTRL_MCKDIV_Pos _U_(16) /**< (I2S_CLKCTRL) Master Clock Division Factor Position */
#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos) /**< (I2S_CLKCTRL) Master Clock Division Factor Mask */
#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
#define I2S_CLKCTRL_MCKOUTDIV_Pos _U_(24) /**< (I2S_CLKCTRL) Master Clock Output Division Factor Position */
#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos) /**< (I2S_CLKCTRL) Master Clock Output Division Factor Mask */
#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
#define I2S_CLKCTRL_Msk _U_(0x3F3FFFFF) /**< (I2S_CLKCTRL) Register Mask */
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#define I2S_INTENCLR_RESETVALUE _U_(0x00) /**< (I2S_INTENCLR) Interrupt Enable Clear Reset Value */
#define I2S_INTENCLR_RXRDY0_Pos _U_(0) /**< (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Position */
#define I2S_INTENCLR_RXRDY0_Msk (_U_(0x1) << I2S_INTENCLR_RXRDY0_Pos) /**< (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Mask */
#define I2S_INTENCLR_RXRDY0(value) (I2S_INTENCLR_RXRDY0_Msk & ((value) << I2S_INTENCLR_RXRDY0_Pos))
#define I2S_INTENCLR_RXRDY1_Pos _U_(1) /**< (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Position */
#define I2S_INTENCLR_RXRDY1_Msk (_U_(0x1) << I2S_INTENCLR_RXRDY1_Pos) /**< (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Mask */
#define I2S_INTENCLR_RXRDY1(value) (I2S_INTENCLR_RXRDY1_Msk & ((value) << I2S_INTENCLR_RXRDY1_Pos))
#define I2S_INTENCLR_RXOR0_Pos _U_(4) /**< (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Position */
#define I2S_INTENCLR_RXOR0_Msk (_U_(0x1) << I2S_INTENCLR_RXOR0_Pos) /**< (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Mask */
#define I2S_INTENCLR_RXOR0(value) (I2S_INTENCLR_RXOR0_Msk & ((value) << I2S_INTENCLR_RXOR0_Pos))
#define I2S_INTENCLR_RXOR1_Pos _U_(5) /**< (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Position */
#define I2S_INTENCLR_RXOR1_Msk (_U_(0x1) << I2S_INTENCLR_RXOR1_Pos) /**< (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Mask */
#define I2S_INTENCLR_RXOR1(value) (I2S_INTENCLR_RXOR1_Msk & ((value) << I2S_INTENCLR_RXOR1_Pos))
#define I2S_INTENCLR_TXRDY0_Pos _U_(8) /**< (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Position */
#define I2S_INTENCLR_TXRDY0_Msk (_U_(0x1) << I2S_INTENCLR_TXRDY0_Pos) /**< (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Mask */
#define I2S_INTENCLR_TXRDY0(value) (I2S_INTENCLR_TXRDY0_Msk & ((value) << I2S_INTENCLR_TXRDY0_Pos))
#define I2S_INTENCLR_TXRDY1_Pos _U_(9) /**< (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Position */
#define I2S_INTENCLR_TXRDY1_Msk (_U_(0x1) << I2S_INTENCLR_TXRDY1_Pos) /**< (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Mask */
#define I2S_INTENCLR_TXRDY1(value) (I2S_INTENCLR_TXRDY1_Msk & ((value) << I2S_INTENCLR_TXRDY1_Pos))
#define I2S_INTENCLR_TXUR0_Pos _U_(12) /**< (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Position */
#define I2S_INTENCLR_TXUR0_Msk (_U_(0x1) << I2S_INTENCLR_TXUR0_Pos) /**< (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Mask */
#define I2S_INTENCLR_TXUR0(value) (I2S_INTENCLR_TXUR0_Msk & ((value) << I2S_INTENCLR_TXUR0_Pos))
#define I2S_INTENCLR_TXUR1_Pos _U_(13) /**< (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Position */
#define I2S_INTENCLR_TXUR1_Msk (_U_(0x1) << I2S_INTENCLR_TXUR1_Pos) /**< (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Mask */
#define I2S_INTENCLR_TXUR1(value) (I2S_INTENCLR_TXUR1_Msk & ((value) << I2S_INTENCLR_TXUR1_Pos))
#define I2S_INTENCLR_Msk _U_(0x3333) /**< (I2S_INTENCLR) Register Mask */
#define I2S_INTENCLR_RXRDY_Pos _U_(0) /**< (I2S_INTENCLR Position) Receive Ready x Interrupt Enable */
#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos) /**< (I2S_INTENCLR Mask) RXRDY */
#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
#define I2S_INTENCLR_RXOR_Pos _U_(4) /**< (I2S_INTENCLR Position) Receive Overrun x Interrupt Enable */
#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos) /**< (I2S_INTENCLR Mask) RXOR */
#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
#define I2S_INTENCLR_TXRDY_Pos _U_(8) /**< (I2S_INTENCLR Position) Transmit Ready x Interrupt Enable */
#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos) /**< (I2S_INTENCLR Mask) TXRDY */
#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
#define I2S_INTENCLR_TXUR_Pos _U_(12) /**< (I2S_INTENCLR Position) Transmit Underrun x Interrupt Enable */
#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos) /**< (I2S_INTENCLR Mask) TXUR */
#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#define I2S_INTENSET_RESETVALUE _U_(0x00) /**< (I2S_INTENSET) Interrupt Enable Set Reset Value */
#define I2S_INTENSET_RXRDY0_Pos _U_(0) /**< (I2S_INTENSET) Receive Ready 0 Interrupt Enable Position */
#define I2S_INTENSET_RXRDY0_Msk (_U_(0x1) << I2S_INTENSET_RXRDY0_Pos) /**< (I2S_INTENSET) Receive Ready 0 Interrupt Enable Mask */
#define I2S_INTENSET_RXRDY0(value) (I2S_INTENSET_RXRDY0_Msk & ((value) << I2S_INTENSET_RXRDY0_Pos))
#define I2S_INTENSET_RXRDY1_Pos _U_(1) /**< (I2S_INTENSET) Receive Ready 1 Interrupt Enable Position */
#define I2S_INTENSET_RXRDY1_Msk (_U_(0x1) << I2S_INTENSET_RXRDY1_Pos) /**< (I2S_INTENSET) Receive Ready 1 Interrupt Enable Mask */
#define I2S_INTENSET_RXRDY1(value) (I2S_INTENSET_RXRDY1_Msk & ((value) << I2S_INTENSET_RXRDY1_Pos))
#define I2S_INTENSET_RXOR0_Pos _U_(4) /**< (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Position */
#define I2S_INTENSET_RXOR0_Msk (_U_(0x1) << I2S_INTENSET_RXOR0_Pos) /**< (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Mask */
#define I2S_INTENSET_RXOR0(value) (I2S_INTENSET_RXOR0_Msk & ((value) << I2S_INTENSET_RXOR0_Pos))
#define I2S_INTENSET_RXOR1_Pos _U_(5) /**< (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Position */
#define I2S_INTENSET_RXOR1_Msk (_U_(0x1) << I2S_INTENSET_RXOR1_Pos) /**< (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Mask */
#define I2S_INTENSET_RXOR1(value) (I2S_INTENSET_RXOR1_Msk & ((value) << I2S_INTENSET_RXOR1_Pos))
#define I2S_INTENSET_TXRDY0_Pos _U_(8) /**< (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Position */
#define I2S_INTENSET_TXRDY0_Msk (_U_(0x1) << I2S_INTENSET_TXRDY0_Pos) /**< (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Mask */
#define I2S_INTENSET_TXRDY0(value) (I2S_INTENSET_TXRDY0_Msk & ((value) << I2S_INTENSET_TXRDY0_Pos))
#define I2S_INTENSET_TXRDY1_Pos _U_(9) /**< (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Position */
#define I2S_INTENSET_TXRDY1_Msk (_U_(0x1) << I2S_INTENSET_TXRDY1_Pos) /**< (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Mask */
#define I2S_INTENSET_TXRDY1(value) (I2S_INTENSET_TXRDY1_Msk & ((value) << I2S_INTENSET_TXRDY1_Pos))
#define I2S_INTENSET_TXUR0_Pos _U_(12) /**< (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Position */
#define I2S_INTENSET_TXUR0_Msk (_U_(0x1) << I2S_INTENSET_TXUR0_Pos) /**< (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Mask */
#define I2S_INTENSET_TXUR0(value) (I2S_INTENSET_TXUR0_Msk & ((value) << I2S_INTENSET_TXUR0_Pos))
#define I2S_INTENSET_TXUR1_Pos _U_(13) /**< (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Position */
#define I2S_INTENSET_TXUR1_Msk (_U_(0x1) << I2S_INTENSET_TXUR1_Pos) /**< (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Mask */
#define I2S_INTENSET_TXUR1(value) (I2S_INTENSET_TXUR1_Msk & ((value) << I2S_INTENSET_TXUR1_Pos))
#define I2S_INTENSET_Msk _U_(0x3333) /**< (I2S_INTENSET) Register Mask */
#define I2S_INTENSET_RXRDY_Pos _U_(0) /**< (I2S_INTENSET Position) Receive Ready x Interrupt Enable */
#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos) /**< (I2S_INTENSET Mask) RXRDY */
#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
#define I2S_INTENSET_RXOR_Pos _U_(4) /**< (I2S_INTENSET Position) Receive Overrun x Interrupt Enable */
#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos) /**< (I2S_INTENSET Mask) RXOR */
#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
#define I2S_INTENSET_TXRDY_Pos _U_(8) /**< (I2S_INTENSET Position) Transmit Ready x Interrupt Enable */
#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos) /**< (I2S_INTENSET Mask) TXRDY */
#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
#define I2S_INTENSET_TXUR_Pos _U_(12) /**< (I2S_INTENSET Position) Transmit Underrun x Interrupt Enable */
#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos) /**< (I2S_INTENSET Mask) TXUR */
#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#define I2S_INTFLAG_RESETVALUE _U_(0x00) /**< (I2S_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define I2S_INTFLAG_RXRDY0_Pos _U_(0) /**< (I2S_INTFLAG) Receive Ready 0 Position */
#define I2S_INTFLAG_RXRDY0_Msk (_U_(0x1) << I2S_INTFLAG_RXRDY0_Pos) /**< (I2S_INTFLAG) Receive Ready 0 Mask */
#define I2S_INTFLAG_RXRDY0(value) (I2S_INTFLAG_RXRDY0_Msk & ((value) << I2S_INTFLAG_RXRDY0_Pos))
#define I2S_INTFLAG_RXRDY1_Pos _U_(1) /**< (I2S_INTFLAG) Receive Ready 1 Position */
#define I2S_INTFLAG_RXRDY1_Msk (_U_(0x1) << I2S_INTFLAG_RXRDY1_Pos) /**< (I2S_INTFLAG) Receive Ready 1 Mask */
#define I2S_INTFLAG_RXRDY1(value) (I2S_INTFLAG_RXRDY1_Msk & ((value) << I2S_INTFLAG_RXRDY1_Pos))
#define I2S_INTFLAG_RXOR0_Pos _U_(4) /**< (I2S_INTFLAG) Receive Overrun 0 Position */
#define I2S_INTFLAG_RXOR0_Msk (_U_(0x1) << I2S_INTFLAG_RXOR0_Pos) /**< (I2S_INTFLAG) Receive Overrun 0 Mask */
#define I2S_INTFLAG_RXOR0(value) (I2S_INTFLAG_RXOR0_Msk & ((value) << I2S_INTFLAG_RXOR0_Pos))
#define I2S_INTFLAG_RXOR1_Pos _U_(5) /**< (I2S_INTFLAG) Receive Overrun 1 Position */
#define I2S_INTFLAG_RXOR1_Msk (_U_(0x1) << I2S_INTFLAG_RXOR1_Pos) /**< (I2S_INTFLAG) Receive Overrun 1 Mask */
#define I2S_INTFLAG_RXOR1(value) (I2S_INTFLAG_RXOR1_Msk & ((value) << I2S_INTFLAG_RXOR1_Pos))
#define I2S_INTFLAG_TXRDY0_Pos _U_(8) /**< (I2S_INTFLAG) Transmit Ready 0 Position */
#define I2S_INTFLAG_TXRDY0_Msk (_U_(0x1) << I2S_INTFLAG_TXRDY0_Pos) /**< (I2S_INTFLAG) Transmit Ready 0 Mask */
#define I2S_INTFLAG_TXRDY0(value) (I2S_INTFLAG_TXRDY0_Msk & ((value) << I2S_INTFLAG_TXRDY0_Pos))
#define I2S_INTFLAG_TXRDY1_Pos _U_(9) /**< (I2S_INTFLAG) Transmit Ready 1 Position */
#define I2S_INTFLAG_TXRDY1_Msk (_U_(0x1) << I2S_INTFLAG_TXRDY1_Pos) /**< (I2S_INTFLAG) Transmit Ready 1 Mask */
#define I2S_INTFLAG_TXRDY1(value) (I2S_INTFLAG_TXRDY1_Msk & ((value) << I2S_INTFLAG_TXRDY1_Pos))
#define I2S_INTFLAG_TXUR0_Pos _U_(12) /**< (I2S_INTFLAG) Transmit Underrun 0 Position */
#define I2S_INTFLAG_TXUR0_Msk (_U_(0x1) << I2S_INTFLAG_TXUR0_Pos) /**< (I2S_INTFLAG) Transmit Underrun 0 Mask */
#define I2S_INTFLAG_TXUR0(value) (I2S_INTFLAG_TXUR0_Msk & ((value) << I2S_INTFLAG_TXUR0_Pos))
#define I2S_INTFLAG_TXUR1_Pos _U_(13) /**< (I2S_INTFLAG) Transmit Underrun 1 Position */
#define I2S_INTFLAG_TXUR1_Msk (_U_(0x1) << I2S_INTFLAG_TXUR1_Pos) /**< (I2S_INTFLAG) Transmit Underrun 1 Mask */
#define I2S_INTFLAG_TXUR1(value) (I2S_INTFLAG_TXUR1_Msk & ((value) << I2S_INTFLAG_TXUR1_Pos))
#define I2S_INTFLAG_Msk _U_(0x3333) /**< (I2S_INTFLAG) Register Mask */
#define I2S_INTFLAG_RXRDY_Pos _U_(0) /**< (I2S_INTFLAG Position) Receive Ready x */
#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos) /**< (I2S_INTFLAG Mask) RXRDY */
#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
#define I2S_INTFLAG_RXOR_Pos _U_(4) /**< (I2S_INTFLAG Position) Receive Overrun x */
#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos) /**< (I2S_INTFLAG Mask) RXOR */
#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
#define I2S_INTFLAG_TXRDY_Pos _U_(8) /**< (I2S_INTFLAG Position) Transmit Ready x */
#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos) /**< (I2S_INTFLAG Mask) TXRDY */
#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
#define I2S_INTFLAG_TXUR_Pos _U_(12) /**< (I2S_INTFLAG Position) Transmit Underrun x */
#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos) /**< (I2S_INTFLAG Mask) TXUR */
#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) ( R/ 16) Synchronization Status -------- */
#define I2S_SYNCBUSY_RESETVALUE _U_(0x00) /**< (I2S_SYNCBUSY) Synchronization Status Reset Value */
#define I2S_SYNCBUSY_SWRST_Pos _U_(0) /**< (I2S_SYNCBUSY) Software Reset Synchronization Status Position */
#define I2S_SYNCBUSY_SWRST_Msk (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos) /**< (I2S_SYNCBUSY) Software Reset Synchronization Status Mask */
#define I2S_SYNCBUSY_SWRST(value) (I2S_SYNCBUSY_SWRST_Msk & ((value) << I2S_SYNCBUSY_SWRST_Pos))
#define I2S_SYNCBUSY_ENABLE_Pos _U_(1) /**< (I2S_SYNCBUSY) Enable Synchronization Status Position */
#define I2S_SYNCBUSY_ENABLE_Msk (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos) /**< (I2S_SYNCBUSY) Enable Synchronization Status Mask */
#define I2S_SYNCBUSY_ENABLE(value) (I2S_SYNCBUSY_ENABLE_Msk & ((value) << I2S_SYNCBUSY_ENABLE_Pos))
#define I2S_SYNCBUSY_CKEN0_Pos _U_(2) /**< (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Position */
#define I2S_SYNCBUSY_CKEN0_Msk (_U_(0x1) << I2S_SYNCBUSY_CKEN0_Pos) /**< (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Mask */
#define I2S_SYNCBUSY_CKEN0(value) (I2S_SYNCBUSY_CKEN0_Msk & ((value) << I2S_SYNCBUSY_CKEN0_Pos))
#define I2S_SYNCBUSY_CKEN1_Pos _U_(3) /**< (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Position */
#define I2S_SYNCBUSY_CKEN1_Msk (_U_(0x1) << I2S_SYNCBUSY_CKEN1_Pos) /**< (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Mask */
#define I2S_SYNCBUSY_CKEN1(value) (I2S_SYNCBUSY_CKEN1_Msk & ((value) << I2S_SYNCBUSY_CKEN1_Pos))
#define I2S_SYNCBUSY_TXEN_Pos _U_(4) /**< (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status Position */
#define I2S_SYNCBUSY_TXEN_Msk (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos) /**< (I2S_SYNCBUSY) Tx Serializer Enable Synchronization Status Mask */
#define I2S_SYNCBUSY_TXEN(value) (I2S_SYNCBUSY_TXEN_Msk & ((value) << I2S_SYNCBUSY_TXEN_Pos))
#define I2S_SYNCBUSY_RXEN_Pos _U_(5) /**< (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status Position */
#define I2S_SYNCBUSY_RXEN_Msk (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos) /**< (I2S_SYNCBUSY) Rx Serializer Enable Synchronization Status Mask */
#define I2S_SYNCBUSY_RXEN(value) (I2S_SYNCBUSY_RXEN_Msk & ((value) << I2S_SYNCBUSY_RXEN_Pos))
#define I2S_SYNCBUSY_TXDATA_Pos _U_(8) /**< (I2S_SYNCBUSY) Tx Data Synchronization Status Position */
#define I2S_SYNCBUSY_TXDATA_Msk (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos) /**< (I2S_SYNCBUSY) Tx Data Synchronization Status Mask */
#define I2S_SYNCBUSY_TXDATA(value) (I2S_SYNCBUSY_TXDATA_Msk & ((value) << I2S_SYNCBUSY_TXDATA_Pos))
#define I2S_SYNCBUSY_RXDATA_Pos _U_(9) /**< (I2S_SYNCBUSY) Rx Data Synchronization Status Position */
#define I2S_SYNCBUSY_RXDATA_Msk (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos) /**< (I2S_SYNCBUSY) Rx Data Synchronization Status Mask */
#define I2S_SYNCBUSY_RXDATA(value) (I2S_SYNCBUSY_RXDATA_Msk & ((value) << I2S_SYNCBUSY_RXDATA_Pos))
#define I2S_SYNCBUSY_Msk _U_(0x033F) /**< (I2S_SYNCBUSY) Register Mask */
#define I2S_SYNCBUSY_CKEN_Pos _U_(2) /**< (I2S_SYNCBUSY Position) Clock Unit x Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos) /**< (I2S_SYNCBUSY Mask) CKEN */
#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
#define I2S_TXCTRL_RESETVALUE _U_(0x00) /**< (I2S_TXCTRL) Tx Serializer Control Reset Value */
#define I2S_TXCTRL_TXDEFAULT_Pos _U_(2) /**< (I2S_TXCTRL) Line Default Line when Slot Disabled Position */
#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos) /**< (I2S_TXCTRL) Line Default Line when Slot Disabled Mask */
#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< (I2S_TXCTRL) Output Default Value is 0 */
#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< (I2S_TXCTRL) Output Default Value is 1 */
#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< (I2S_TXCTRL) Output Default Value is high impedance */
#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos) /**< (I2S_TXCTRL) Output Default Value is 0 Position */
#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos) /**< (I2S_TXCTRL) Output Default Value is 1 Position */
#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos) /**< (I2S_TXCTRL) Output Default Value is high impedance Position */
#define I2S_TXCTRL_TXSAME_Pos _U_(4) /**< (I2S_TXCTRL) Transmit Data when Underrun Position */
#define I2S_TXCTRL_TXSAME_Msk (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos) /**< (I2S_TXCTRL) Transmit Data when Underrun Mask */
#define I2S_TXCTRL_TXSAME(value) (I2S_TXCTRL_TXSAME_Msk & ((value) << I2S_TXCTRL_TXSAME_Pos))
#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0) /**< (I2S_TXCTRL) Zero data transmitted in case of underrun */
#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1) /**< (I2S_TXCTRL) Last data transmitted in case of underrun */
#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos) /**< (I2S_TXCTRL) Zero data transmitted in case of underrun Position */
#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos) /**< (I2S_TXCTRL) Last data transmitted in case of underrun Position */
#define I2S_TXCTRL_SLOTADJ_Pos _U_(7) /**< (I2S_TXCTRL) Data Slot Formatting Adjust Position */
#define I2S_TXCTRL_SLOTADJ_Msk (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos) /**< (I2S_TXCTRL) Data Slot Formatting Adjust Mask */
#define I2S_TXCTRL_SLOTADJ(value) (I2S_TXCTRL_SLOTADJ_Msk & ((value) << I2S_TXCTRL_SLOTADJ_Pos))
#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< (I2S_TXCTRL) Data is right adjusted in slot */
#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< (I2S_TXCTRL) Data is left adjusted in slot */
#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos) /**< (I2S_TXCTRL) Data is right adjusted in slot Position */
#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos) /**< (I2S_TXCTRL) Data is left adjusted in slot Position */
#define I2S_TXCTRL_DATASIZE_Pos _U_(8) /**< (I2S_TXCTRL) Data Word Size Position */
#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) Data Word Size Mask */
#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0) /**< (I2S_TXCTRL) 32 bits */
#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1) /**< (I2S_TXCTRL) 24 bits */
#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2) /**< (I2S_TXCTRL) 20 bits */
#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3) /**< (I2S_TXCTRL) 18 bits */
#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4) /**< (I2S_TXCTRL) 16 bits */
#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5) /**< (I2S_TXCTRL) 16 bits compact stereo */
#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6) /**< (I2S_TXCTRL) 8 bits */
#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7) /**< (I2S_TXCTRL) 8 bits compact stereo */
#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 32 bits Position */
#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 24 bits Position */
#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 20 bits Position */
#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 18 bits Position */
#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 16 bits Position */
#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 16 bits compact stereo Position */
#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 8 bits Position */
#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos) /**< (I2S_TXCTRL) 8 bits compact stereo Position */
#define I2S_TXCTRL_WORDADJ_Pos _U_(12) /**< (I2S_TXCTRL) Data Word Formatting Adjust Position */
#define I2S_TXCTRL_WORDADJ_Msk (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos) /**< (I2S_TXCTRL) Data Word Formatting Adjust Mask */
#define I2S_TXCTRL_WORDADJ(value) (I2S_TXCTRL_WORDADJ_Msk & ((value) << I2S_TXCTRL_WORDADJ_Pos))
#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< (I2S_TXCTRL) Data is right adjusted in word */
#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< (I2S_TXCTRL) Data is left adjusted in word */
#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos) /**< (I2S_TXCTRL) Data is right adjusted in word Position */
#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos) /**< (I2S_TXCTRL) Data is left adjusted in word Position */
#define I2S_TXCTRL_EXTEND_Pos _U_(13) /**< (I2S_TXCTRL) Data Formatting Bit Extension Position */
#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos) /**< (I2S_TXCTRL) Data Formatting Bit Extension Mask */
#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< (I2S_TXCTRL) Extend with zeroes */
#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1) /**< (I2S_TXCTRL) Extend with ones */
#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< (I2S_TXCTRL) Extend with Most Significant Bit */
#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< (I2S_TXCTRL) Extend with Least Significant Bit */
#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos) /**< (I2S_TXCTRL) Extend with zeroes Position */
#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos) /**< (I2S_TXCTRL) Extend with ones Position */
#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos) /**< (I2S_TXCTRL) Extend with Most Significant Bit Position */
#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos) /**< (I2S_TXCTRL) Extend with Least Significant Bit Position */
#define I2S_TXCTRL_BITREV_Pos _U_(15) /**< (I2S_TXCTRL) Data Formatting Bit Reverse Position */
#define I2S_TXCTRL_BITREV_Msk (_U_(0x1) << I2S_TXCTRL_BITREV_Pos) /**< (I2S_TXCTRL) Data Formatting Bit Reverse Mask */
#define I2S_TXCTRL_BITREV(value) (I2S_TXCTRL_BITREV_Msk & ((value) << I2S_TXCTRL_BITREV_Pos))
#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first */
#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos) /**< (I2S_TXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) Position */
#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos) /**< (I2S_TXCTRL) Transfer Data Least Significant Bit (LSB) first Position */
#define I2S_TXCTRL_SLOTDIS0_Pos _U_(16) /**< (I2S_TXCTRL) Slot 0 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS0_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS0_Pos) /**< (I2S_TXCTRL) Slot 0 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS0(value) (I2S_TXCTRL_SLOTDIS0_Msk & ((value) << I2S_TXCTRL_SLOTDIS0_Pos))
#define I2S_TXCTRL_SLOTDIS1_Pos _U_(17) /**< (I2S_TXCTRL) Slot 1 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS1_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS1_Pos) /**< (I2S_TXCTRL) Slot 1 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS1(value) (I2S_TXCTRL_SLOTDIS1_Msk & ((value) << I2S_TXCTRL_SLOTDIS1_Pos))
#define I2S_TXCTRL_SLOTDIS2_Pos _U_(18) /**< (I2S_TXCTRL) Slot 2 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS2_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS2_Pos) /**< (I2S_TXCTRL) Slot 2 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS2(value) (I2S_TXCTRL_SLOTDIS2_Msk & ((value) << I2S_TXCTRL_SLOTDIS2_Pos))
#define I2S_TXCTRL_SLOTDIS3_Pos _U_(19) /**< (I2S_TXCTRL) Slot 3 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS3_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS3_Pos) /**< (I2S_TXCTRL) Slot 3 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS3(value) (I2S_TXCTRL_SLOTDIS3_Msk & ((value) << I2S_TXCTRL_SLOTDIS3_Pos))
#define I2S_TXCTRL_SLOTDIS4_Pos _U_(20) /**< (I2S_TXCTRL) Slot 4 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS4_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS4_Pos) /**< (I2S_TXCTRL) Slot 4 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS4(value) (I2S_TXCTRL_SLOTDIS4_Msk & ((value) << I2S_TXCTRL_SLOTDIS4_Pos))
#define I2S_TXCTRL_SLOTDIS5_Pos _U_(21) /**< (I2S_TXCTRL) Slot 5 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS5_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS5_Pos) /**< (I2S_TXCTRL) Slot 5 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS5(value) (I2S_TXCTRL_SLOTDIS5_Msk & ((value) << I2S_TXCTRL_SLOTDIS5_Pos))
#define I2S_TXCTRL_SLOTDIS6_Pos _U_(22) /**< (I2S_TXCTRL) Slot 6 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS6_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS6_Pos) /**< (I2S_TXCTRL) Slot 6 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS6(value) (I2S_TXCTRL_SLOTDIS6_Msk & ((value) << I2S_TXCTRL_SLOTDIS6_Pos))
#define I2S_TXCTRL_SLOTDIS7_Pos _U_(23) /**< (I2S_TXCTRL) Slot 7 Disabled for this Serializer Position */
#define I2S_TXCTRL_SLOTDIS7_Msk (_U_(0x1) << I2S_TXCTRL_SLOTDIS7_Pos) /**< (I2S_TXCTRL) Slot 7 Disabled for this Serializer Mask */
#define I2S_TXCTRL_SLOTDIS7(value) (I2S_TXCTRL_SLOTDIS7_Msk & ((value) << I2S_TXCTRL_SLOTDIS7_Pos))
#define I2S_TXCTRL_MONO_Pos _U_(24) /**< (I2S_TXCTRL) Mono Mode Position */
#define I2S_TXCTRL_MONO_Msk (_U_(0x1) << I2S_TXCTRL_MONO_Pos) /**< (I2S_TXCTRL) Mono Mode Mask */
#define I2S_TXCTRL_MONO(value) (I2S_TXCTRL_MONO_Msk & ((value) << I2S_TXCTRL_MONO_Pos))
#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0) /**< (I2S_TXCTRL) Normal mode */
#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1) /**< (I2S_TXCTRL) Left channel data is duplicated to right channel */
#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos) /**< (I2S_TXCTRL) Normal mode Position */
#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos) /**< (I2S_TXCTRL) Left channel data is duplicated to right channel Position */
#define I2S_TXCTRL_DMA_Pos _U_(25) /**< (I2S_TXCTRL) Single or Multiple DMA Channels Position */
#define I2S_TXCTRL_DMA_Msk (_U_(0x1) << I2S_TXCTRL_DMA_Pos) /**< (I2S_TXCTRL) Single or Multiple DMA Channels Mask */
#define I2S_TXCTRL_DMA(value) (I2S_TXCTRL_DMA_Msk & ((value) << I2S_TXCTRL_DMA_Pos))
#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0) /**< (I2S_TXCTRL) Single DMA channel */
#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< (I2S_TXCTRL) One DMA channel per data channel */
#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos) /**< (I2S_TXCTRL) Single DMA channel Position */
#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos) /**< (I2S_TXCTRL) One DMA channel per data channel Position */
#define I2S_TXCTRL_Msk _U_(0x03FFF79C) /**< (I2S_TXCTRL) Register Mask */
#define I2S_TXCTRL_SLOTDIS_Pos _U_(16) /**< (I2S_TXCTRL Position) Slot x Disabled for this Serializer */
#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos) /**< (I2S_TXCTRL Mask) SLOTDIS */
#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
#define I2S_RXCTRL_RESETVALUE _U_(0x00) /**< (I2S_RXCTRL) Rx Serializer Control Reset Value */
#define I2S_RXCTRL_SERMODE_Pos _U_(0) /**< (I2S_RXCTRL) Serializer Mode Position */
#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos) /**< (I2S_RXCTRL) Serializer Mode Mask */
#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0) /**< (I2S_RXCTRL) Receive */
#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2) /**< (I2S_RXCTRL) Receive one PDM data on each serial clock edge */
#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos) /**< (I2S_RXCTRL) Receive Position */
#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos) /**< (I2S_RXCTRL) Receive one PDM data on each serial clock edge Position */
#define I2S_RXCTRL_CLKSEL_Pos _U_(5) /**< (I2S_RXCTRL) Clock Unit Selection Position */
#define I2S_RXCTRL_CLKSEL_Msk (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos) /**< (I2S_RXCTRL) Clock Unit Selection Mask */
#define I2S_RXCTRL_CLKSEL(value) (I2S_RXCTRL_CLKSEL_Msk & ((value) << I2S_RXCTRL_CLKSEL_Pos))
#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< (I2S_RXCTRL) Use Clock Unit 0 */
#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< (I2S_RXCTRL) Use Clock Unit 1 */
#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos) /**< (I2S_RXCTRL) Use Clock Unit 0 Position */
#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos) /**< (I2S_RXCTRL) Use Clock Unit 1 Position */
#define I2S_RXCTRL_SLOTADJ_Pos _U_(7) /**< (I2S_RXCTRL) Data Slot Formatting Adjust Position */
#define I2S_RXCTRL_SLOTADJ_Msk (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos) /**< (I2S_RXCTRL) Data Slot Formatting Adjust Mask */
#define I2S_RXCTRL_SLOTADJ(value) (I2S_RXCTRL_SLOTADJ_Msk & ((value) << I2S_RXCTRL_SLOTADJ_Pos))
#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< (I2S_RXCTRL) Data is right adjusted in slot */
#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< (I2S_RXCTRL) Data is left adjusted in slot */
#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos) /**< (I2S_RXCTRL) Data is right adjusted in slot Position */
#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos) /**< (I2S_RXCTRL) Data is left adjusted in slot Position */
#define I2S_RXCTRL_DATASIZE_Pos _U_(8) /**< (I2S_RXCTRL) Data Word Size Position */
#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) Data Word Size Mask */
#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0) /**< (I2S_RXCTRL) 32 bits */
#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1) /**< (I2S_RXCTRL) 24 bits */
#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2) /**< (I2S_RXCTRL) 20 bits */
#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3) /**< (I2S_RXCTRL) 18 bits */
#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4) /**< (I2S_RXCTRL) 16 bits */
#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5) /**< (I2S_RXCTRL) 16 bits compact stereo */
#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6) /**< (I2S_RXCTRL) 8 bits */
#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7) /**< (I2S_RXCTRL) 8 bits compact stereo */
#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 32 bits Position */
#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 24 bits Position */
#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 20 bits Position */
#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 18 bits Position */
#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 16 bits Position */
#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 16 bits compact stereo Position */
#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 8 bits Position */
#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos) /**< (I2S_RXCTRL) 8 bits compact stereo Position */
#define I2S_RXCTRL_WORDADJ_Pos _U_(12) /**< (I2S_RXCTRL) Data Word Formatting Adjust Position */
#define I2S_RXCTRL_WORDADJ_Msk (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos) /**< (I2S_RXCTRL) Data Word Formatting Adjust Mask */
#define I2S_RXCTRL_WORDADJ(value) (I2S_RXCTRL_WORDADJ_Msk & ((value) << I2S_RXCTRL_WORDADJ_Pos))
#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< (I2S_RXCTRL) Data is right adjusted in word */
#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< (I2S_RXCTRL) Data is left adjusted in word */
#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos) /**< (I2S_RXCTRL) Data is right adjusted in word Position */
#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos) /**< (I2S_RXCTRL) Data is left adjusted in word Position */
#define I2S_RXCTRL_EXTEND_Pos _U_(13) /**< (I2S_RXCTRL) Data Formatting Bit Extension Position */
#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos) /**< (I2S_RXCTRL) Data Formatting Bit Extension Mask */
#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0) /**< (I2S_RXCTRL) Extend with zeroes */
#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1) /**< (I2S_RXCTRL) Extend with ones */
#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< (I2S_RXCTRL) Extend with Most Significant Bit */
#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< (I2S_RXCTRL) Extend with Least Significant Bit */
#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos) /**< (I2S_RXCTRL) Extend with zeroes Position */
#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos) /**< (I2S_RXCTRL) Extend with ones Position */
#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos) /**< (I2S_RXCTRL) Extend with Most Significant Bit Position */
#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos) /**< (I2S_RXCTRL) Extend with Least Significant Bit Position */
#define I2S_RXCTRL_BITREV_Pos _U_(15) /**< (I2S_RXCTRL) Data Formatting Bit Reverse Position */
#define I2S_RXCTRL_BITREV_Msk (_U_(0x1) << I2S_RXCTRL_BITREV_Pos) /**< (I2S_RXCTRL) Data Formatting Bit Reverse Mask */
#define I2S_RXCTRL_BITREV(value) (I2S_RXCTRL_BITREV_Msk & ((value) << I2S_RXCTRL_BITREV_Pos))
#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0) /**< (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1) /**< (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first */
#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos) /**< (I2S_RXCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) Position */
#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos) /**< (I2S_RXCTRL) Transfer Data Least Significant Bit (LSB) first Position */
#define I2S_RXCTRL_SLOTDIS0_Pos _U_(16) /**< (I2S_RXCTRL) Slot 0 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS0_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS0_Pos) /**< (I2S_RXCTRL) Slot 0 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS0(value) (I2S_RXCTRL_SLOTDIS0_Msk & ((value) << I2S_RXCTRL_SLOTDIS0_Pos))
#define I2S_RXCTRL_SLOTDIS1_Pos _U_(17) /**< (I2S_RXCTRL) Slot 1 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS1_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS1_Pos) /**< (I2S_RXCTRL) Slot 1 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS1(value) (I2S_RXCTRL_SLOTDIS1_Msk & ((value) << I2S_RXCTRL_SLOTDIS1_Pos))
#define I2S_RXCTRL_SLOTDIS2_Pos _U_(18) /**< (I2S_RXCTRL) Slot 2 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS2_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS2_Pos) /**< (I2S_RXCTRL) Slot 2 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS2(value) (I2S_RXCTRL_SLOTDIS2_Msk & ((value) << I2S_RXCTRL_SLOTDIS2_Pos))
#define I2S_RXCTRL_SLOTDIS3_Pos _U_(19) /**< (I2S_RXCTRL) Slot 3 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS3_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS3_Pos) /**< (I2S_RXCTRL) Slot 3 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS3(value) (I2S_RXCTRL_SLOTDIS3_Msk & ((value) << I2S_RXCTRL_SLOTDIS3_Pos))
#define I2S_RXCTRL_SLOTDIS4_Pos _U_(20) /**< (I2S_RXCTRL) Slot 4 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS4_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS4_Pos) /**< (I2S_RXCTRL) Slot 4 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS4(value) (I2S_RXCTRL_SLOTDIS4_Msk & ((value) << I2S_RXCTRL_SLOTDIS4_Pos))
#define I2S_RXCTRL_SLOTDIS5_Pos _U_(21) /**< (I2S_RXCTRL) Slot 5 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS5_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS5_Pos) /**< (I2S_RXCTRL) Slot 5 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS5(value) (I2S_RXCTRL_SLOTDIS5_Msk & ((value) << I2S_RXCTRL_SLOTDIS5_Pos))
#define I2S_RXCTRL_SLOTDIS6_Pos _U_(22) /**< (I2S_RXCTRL) Slot 6 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS6_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS6_Pos) /**< (I2S_RXCTRL) Slot 6 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS6(value) (I2S_RXCTRL_SLOTDIS6_Msk & ((value) << I2S_RXCTRL_SLOTDIS6_Pos))
#define I2S_RXCTRL_SLOTDIS7_Pos _U_(23) /**< (I2S_RXCTRL) Slot 7 Disabled for this Serializer Position */
#define I2S_RXCTRL_SLOTDIS7_Msk (_U_(0x1) << I2S_RXCTRL_SLOTDIS7_Pos) /**< (I2S_RXCTRL) Slot 7 Disabled for this Serializer Mask */
#define I2S_RXCTRL_SLOTDIS7(value) (I2S_RXCTRL_SLOTDIS7_Msk & ((value) << I2S_RXCTRL_SLOTDIS7_Pos))
#define I2S_RXCTRL_MONO_Pos _U_(24) /**< (I2S_RXCTRL) Mono Mode Position */
#define I2S_RXCTRL_MONO_Msk (_U_(0x1) << I2S_RXCTRL_MONO_Pos) /**< (I2S_RXCTRL) Mono Mode Mask */
#define I2S_RXCTRL_MONO(value) (I2S_RXCTRL_MONO_Msk & ((value) << I2S_RXCTRL_MONO_Pos))
#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0) /**< (I2S_RXCTRL) Normal mode */
#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1) /**< (I2S_RXCTRL) Left channel data is duplicated to right channel */
#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos) /**< (I2S_RXCTRL) Normal mode Position */
#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos) /**< (I2S_RXCTRL) Left channel data is duplicated to right channel Position */
#define I2S_RXCTRL_DMA_Pos _U_(25) /**< (I2S_RXCTRL) Single or Multiple DMA Channels Position */
#define I2S_RXCTRL_DMA_Msk (_U_(0x1) << I2S_RXCTRL_DMA_Pos) /**< (I2S_RXCTRL) Single or Multiple DMA Channels Mask */
#define I2S_RXCTRL_DMA(value) (I2S_RXCTRL_DMA_Msk & ((value) << I2S_RXCTRL_DMA_Pos))
#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0) /**< (I2S_RXCTRL) Single DMA channel */
#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< (I2S_RXCTRL) One DMA channel per data channel */
#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos) /**< (I2S_RXCTRL) Single DMA channel Position */
#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos) /**< (I2S_RXCTRL) One DMA channel per data channel Position */
#define I2S_RXCTRL_RXLOOP_Pos _U_(26) /**< (I2S_RXCTRL) Loop-back Test Mode Position */
#define I2S_RXCTRL_RXLOOP_Msk (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos) /**< (I2S_RXCTRL) Loop-back Test Mode Mask */
#define I2S_RXCTRL_RXLOOP(value) (I2S_RXCTRL_RXLOOP_Msk & ((value) << I2S_RXCTRL_RXLOOP_Pos))
#define I2S_RXCTRL_Msk _U_(0x07FFF7A3) /**< (I2S_RXCTRL) Register Mask */
#define I2S_RXCTRL_SLOTDIS_Pos _U_(16) /**< (I2S_RXCTRL Position) Slot x Disabled for this Serializer */
#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos) /**< (I2S_RXCTRL Mask) SLOTDIS */
#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
#define I2S_TXDATA_RESETVALUE _U_(0x00) /**< (I2S_TXDATA) Tx Data Reset Value */
#define I2S_TXDATA_DATA_Pos _U_(0) /**< (I2S_TXDATA) Sample Data Position */
#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos) /**< (I2S_TXDATA) Sample Data Mask */
#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
#define I2S_TXDATA_Msk _U_(0xFFFFFFFF) /**< (I2S_TXDATA) Register Mask */
/* -------- I2S_RXDATA : (I2S Offset: 0x34) ( R/ 32) Rx Data -------- */
#define I2S_RXDATA_RESETVALUE _U_(0x00) /**< (I2S_RXDATA) Rx Data Reset Value */
#define I2S_RXDATA_DATA_Pos _U_(0) /**< (I2S_RXDATA) Sample Data Position */
#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos) /**< (I2S_RXDATA) Sample Data Mask */
#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
#define I2S_RXDATA_Msk _U_(0xFFFFFFFF) /**< (I2S_RXDATA) Register Mask */
/** \brief I2S register offsets definitions */
#define I2S_CTRLA_REG_OFST (0x00) /**< (I2S_CTRLA) Control A Offset */
#define I2S_CLKCTRL_REG_OFST (0x04) /**< (I2S_CLKCTRL) Clock Unit n Control Offset */
#define I2S_INTENCLR_REG_OFST (0x0C) /**< (I2S_INTENCLR) Interrupt Enable Clear Offset */
#define I2S_INTENSET_REG_OFST (0x10) /**< (I2S_INTENSET) Interrupt Enable Set Offset */
#define I2S_INTFLAG_REG_OFST (0x14) /**< (I2S_INTFLAG) Interrupt Flag Status and Clear Offset */
#define I2S_SYNCBUSY_REG_OFST (0x18) /**< (I2S_SYNCBUSY) Synchronization Status Offset */
#define I2S_TXCTRL_REG_OFST (0x20) /**< (I2S_TXCTRL) Tx Serializer Control Offset */
#define I2S_RXCTRL_REG_OFST (0x24) /**< (I2S_RXCTRL) Rx Serializer Control Offset */
#define I2S_TXDATA_REG_OFST (0x30) /**< (I2S_TXDATA) Tx Data Offset */
#define I2S_RXDATA_REG_OFST (0x34) /**< (I2S_RXDATA) Rx Data Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief I2S register API structure */
typedef struct
{ /* Inter-IC Sound Interface */
__IO uint8_t I2S_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__I uint8_t Reserved1[0x03];
__IO uint32_t I2S_CLKCTRL[2]; /**< Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO uint16_t I2S_INTENCLR; /**< Offset: 0x0C (R/W 16) Interrupt Enable Clear */
__I uint8_t Reserved2[0x02];
__IO uint16_t I2S_INTENSET; /**< Offset: 0x10 (R/W 16) Interrupt Enable Set */
__I uint8_t Reserved3[0x02];
__IO uint16_t I2S_INTFLAG; /**< Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
__I uint8_t Reserved4[0x02];
__I uint16_t I2S_SYNCBUSY; /**< Offset: 0x18 (R/ 16) Synchronization Status */
__I uint8_t Reserved5[0x06];
__IO uint32_t I2S_TXCTRL; /**< Offset: 0x20 (R/W 32) Tx Serializer Control */
__IO uint32_t I2S_RXCTRL; /**< Offset: 0x24 (R/W 32) Rx Serializer Control */
__I uint8_t Reserved6[0x08];
__O uint32_t I2S_TXDATA; /**< Offset: 0x30 ( /W 32) Tx Data */
__I uint32_t I2S_RXDATA; /**< Offset: 0x34 (R/ 32) Rx Data */
} i2s_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_I2S_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/icm.h
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/**
* \brief Component description for ICM
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_ICM_COMPONENT_H_
#define _SAMD51_ICM_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR ICM */
/* ************************************************************************** */
/* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
#define ICM_RADDR_Msk _U_(0x00000000) /**< (ICM_RADDR) Register Mask */
/* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
#define ICM_RCFG_RESETVALUE _U_(0x00) /**< (ICM_RCFG) Region Configuration Reset Value */
#define ICM_RCFG_CDWBN_Pos _U_(0) /**< (ICM_RCFG) Compare Digest Write Back Position */
#define ICM_RCFG_CDWBN_Msk (_U_(0x1) << ICM_RCFG_CDWBN_Pos) /**< (ICM_RCFG) Compare Digest Write Back Mask */
#define ICM_RCFG_CDWBN(value) (ICM_RCFG_CDWBN_Msk & ((value) << ICM_RCFG_CDWBN_Pos))
#define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_WRAP_Pos _U_(1) /**< (ICM_RCFG) Region Wrap Position */
#define ICM_RCFG_WRAP_Msk (_U_(0x1) << ICM_RCFG_WRAP_Pos) /**< (ICM_RCFG) Region Wrap Mask */
#define ICM_RCFG_WRAP(value) (ICM_RCFG_WRAP_Msk & ((value) << ICM_RCFG_WRAP_Pos))
#define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_EOM_Pos _U_(2) /**< (ICM_RCFG) End of Monitoring Position */
#define ICM_RCFG_EOM_Msk (_U_(0x1) << ICM_RCFG_EOM_Pos) /**< (ICM_RCFG) End of Monitoring Mask */
#define ICM_RCFG_EOM(value) (ICM_RCFG_EOM_Msk & ((value) << ICM_RCFG_EOM_Pos))
#define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_RHIEN_Pos _U_(4) /**< (ICM_RCFG) Region Hash Interrupt Enable Position */
#define ICM_RCFG_RHIEN_Msk (_U_(0x1) << ICM_RCFG_RHIEN_Pos) /**< (ICM_RCFG) Region Hash Interrupt Enable Mask */
#define ICM_RCFG_RHIEN(value) (ICM_RCFG_RHIEN_Msk & ((value) << ICM_RCFG_RHIEN_Pos))
#define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_DMIEN_Pos _U_(5) /**< (ICM_RCFG) Region Digest Mismatch Interrupt Enable Position */
#define ICM_RCFG_DMIEN_Msk (_U_(0x1) << ICM_RCFG_DMIEN_Pos) /**< (ICM_RCFG) Region Digest Mismatch Interrupt Enable Mask */
#define ICM_RCFG_DMIEN(value) (ICM_RCFG_DMIEN_Msk & ((value) << ICM_RCFG_DMIEN_Pos))
#define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_BEIEN_Pos _U_(6) /**< (ICM_RCFG) Region Bus Error Interrupt Enable Position */
#define ICM_RCFG_BEIEN_Msk (_U_(0x1) << ICM_RCFG_BEIEN_Pos) /**< (ICM_RCFG) Region Bus Error Interrupt Enable Mask */
#define ICM_RCFG_BEIEN(value) (ICM_RCFG_BEIEN_Msk & ((value) << ICM_RCFG_BEIEN_Pos))
#define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_WCIEN_Pos _U_(7) /**< (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable Position */
#define ICM_RCFG_WCIEN_Msk (_U_(0x1) << ICM_RCFG_WCIEN_Pos) /**< (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable Mask */
#define ICM_RCFG_WCIEN(value) (ICM_RCFG_WCIEN_Msk & ((value) << ICM_RCFG_WCIEN_Pos))
#define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_ECIEN_Pos _U_(8) /**< (ICM_RCFG) Region End bit Condition detected Interrupt Enable Position */
#define ICM_RCFG_ECIEN_Msk (_U_(0x1) << ICM_RCFG_ECIEN_Pos) /**< (ICM_RCFG) Region End bit Condition detected Interrupt Enable Mask */
#define ICM_RCFG_ECIEN(value) (ICM_RCFG_ECIEN_Msk & ((value) << ICM_RCFG_ECIEN_Pos))
#define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_SUIEN_Pos _U_(9) /**< (ICM_RCFG) Region Status Updated Interrupt Enable Position */
#define ICM_RCFG_SUIEN_Msk (_U_(0x1) << ICM_RCFG_SUIEN_Pos) /**< (ICM_RCFG) Region Status Updated Interrupt Enable Mask */
#define ICM_RCFG_SUIEN(value) (ICM_RCFG_SUIEN_Msk & ((value) << ICM_RCFG_SUIEN_Pos))
#define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_PROCDLY_Pos _U_(10) /**< (ICM_RCFG) SHA Processing Delay Position */
#define ICM_RCFG_PROCDLY_Msk (_U_(0x1) << ICM_RCFG_PROCDLY_Pos) /**< (ICM_RCFG) SHA Processing Delay Mask */
#define ICM_RCFG_PROCDLY(value) (ICM_RCFG_PROCDLY_Msk & ((value) << ICM_RCFG_PROCDLY_Pos))
#define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< (ICM_RCFG) */
#define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< (ICM_RCFG) */
#define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos) /**< (ICM_RCFG) Position */
#define ICM_RCFG_ALGO_Pos _U_(12) /**< (ICM_RCFG) SHA Algorithm Position */
#define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos) /**< (ICM_RCFG) SHA Algorithm Mask */
#define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
#define ICM_RCFG_MRPROT_Pos _U_(24) /**< (ICM_RCFG) Memory Region AHB Protection Position */
#define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos) /**< (ICM_RCFG) Memory Region AHB Protection Mask */
#define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
#define ICM_RCFG_Msk _U_(0x3F0077F7) /**< (ICM_RCFG) Register Mask */
/* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
#define ICM_RCTRL_TRSIZE_Pos _U_(0) /**< (ICM_RCTRL) Transfer Size Position */
#define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos) /**< (ICM_RCTRL) Transfer Size Mask */
#define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
#define ICM_RCTRL_Msk _U_(0x0000FFFF) /**< (ICM_RCTRL) Register Mask */
/* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
#define ICM_RNEXT_Msk _U_(0x00000000) /**< (ICM_RNEXT) Register Mask */
/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
#define ICM_CFG_RESETVALUE _U_(0x00) /**< (ICM_CFG) Configuration Reset Value */
#define ICM_CFG_WBDIS_Pos _U_(0) /**< (ICM_CFG) Write Back Disable Position */
#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */
#define ICM_CFG_WBDIS(value) (ICM_CFG_WBDIS_Msk & ((value) << ICM_CFG_WBDIS_Pos))
#define ICM_CFG_EOMDIS_Pos _U_(1) /**< (ICM_CFG) End of Monitoring Disable Position */
#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */
#define ICM_CFG_EOMDIS(value) (ICM_CFG_EOMDIS_Msk & ((value) << ICM_CFG_EOMDIS_Pos))
#define ICM_CFG_SLBDIS_Pos _U_(2) /**< (ICM_CFG) Secondary List Branching Disable Position */
#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */
#define ICM_CFG_SLBDIS(value) (ICM_CFG_SLBDIS_Msk & ((value) << ICM_CFG_SLBDIS_Pos))
#define ICM_CFG_BBC_Pos _U_(4) /**< (ICM_CFG) Bus Burden Control Position */
#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */
#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
#define ICM_CFG_ASCD_Pos _U_(8) /**< (ICM_CFG) Automatic Switch To Compare Digest Position */
#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */
#define ICM_CFG_ASCD(value) (ICM_CFG_ASCD_Msk & ((value) << ICM_CFG_ASCD_Pos))
#define ICM_CFG_DUALBUFF_Pos _U_(9) /**< (ICM_CFG) Dual Input Buffer Position */
#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */
#define ICM_CFG_DUALBUFF(value) (ICM_CFG_DUALBUFF_Msk & ((value) << ICM_CFG_DUALBUFF_Pos))
#define ICM_CFG_UIHASH_Pos _U_(12) /**< (ICM_CFG) User Initial Hash Value Position */
#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */
#define ICM_CFG_UIHASH(value) (ICM_CFG_UIHASH_Msk & ((value) << ICM_CFG_UIHASH_Pos))
#define ICM_CFG_UALGO_Pos _U_(13) /**< (ICM_CFG) User SHA Algorithm Position */
#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */
#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 Algorithm */
#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 Algorithm */
#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 Algorithm */
#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 Algorithm Position */
#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 Algorithm Position */
#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 Algorithm Position */
#define ICM_CFG_Msk _U_(0x0000F3F7) /**< (ICM_CFG) Register Mask */
/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
#define ICM_CTRL_ENABLE_Pos _U_(0) /**< (ICM_CTRL) ICM Enable Position */
#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */
#define ICM_CTRL_ENABLE(value) (ICM_CTRL_ENABLE_Msk & ((value) << ICM_CTRL_ENABLE_Pos))
#define ICM_CTRL_DISABLE_Pos _U_(1) /**< (ICM_CTRL) ICM Disable Register Position */
#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */
#define ICM_CTRL_DISABLE(value) (ICM_CTRL_DISABLE_Msk & ((value) << ICM_CTRL_DISABLE_Pos))
#define ICM_CTRL_SWRST_Pos _U_(2) /**< (ICM_CTRL) Software Reset Position */
#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */
#define ICM_CTRL_SWRST(value) (ICM_CTRL_SWRST_Msk & ((value) << ICM_CTRL_SWRST_Pos))
#define ICM_CTRL_REHASH_Pos _U_(4) /**< (ICM_CTRL) Recompute Internal Hash Position */
#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */
#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
#define ICM_CTRL_RMDIS_Pos _U_(8) /**< (ICM_CTRL) Region Monitoring Disable Position */
#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */
#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
#define ICM_CTRL_RMEN_Pos _U_(12) /**< (ICM_CTRL) Region Monitoring Enable Position */
#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */
#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
#define ICM_CTRL_Msk _U_(0x0000FFF7) /**< (ICM_CTRL) Register Mask */
/* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status -------- */
#define ICM_SR_RESETVALUE _U_(0x00) /**< (ICM_SR) Status Reset Value */
#define ICM_SR_ENABLE_Pos _U_(0) /**< (ICM_SR) ICM Controller Enable Register Position */
#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */
#define ICM_SR_ENABLE(value) (ICM_SR_ENABLE_Msk & ((value) << ICM_SR_ENABLE_Pos))
#define ICM_SR_RAWRMDIS_Pos _U_(8) /**< (ICM_SR) RAW Region Monitoring Disabled Status Position */
#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) RAW Region Monitoring Disabled Status Mask */
#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
#define ICM_SR_RMDIS_Pos _U_(12) /**< (ICM_SR) Region Monitoring Disabled Status Position */
#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */
#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
#define ICM_SR_Msk _U_(0x0000FF01) /**< (ICM_SR) Register Mask */
/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
#define ICM_IER_RHC_Pos _U_(0) /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */
#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */
#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
#define ICM_IER_RDM_Pos _U_(4) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */
#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */
#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
#define ICM_IER_RBE_Pos _U_(8) /**< (ICM_IER) Region Bus Error Interrupt Enable Position */
#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */
#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
#define ICM_IER_RWC_Pos _U_(12) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */
#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */
#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
#define ICM_IER_REC_Pos _U_(16) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */
#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */
#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
#define ICM_IER_RSU_Pos _U_(20) /**< (ICM_IER) Region Status Updated Interrupt Disable Position */
#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */
#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
#define ICM_IER_URAD_Pos _U_(24) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */
#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */
#define ICM_IER_URAD(value) (ICM_IER_URAD_Msk & ((value) << ICM_IER_URAD_Pos))
#define ICM_IER_Msk _U_(0x01FFFFFF) /**< (ICM_IER) Register Mask */
/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
#define ICM_IDR_RESETVALUE _U_(0x00) /**< (ICM_IDR) Interrupt Disable Reset Value */
#define ICM_IDR_RHC_Pos _U_(0) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */
#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */
#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
#define ICM_IDR_RDM_Pos _U_(4) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */
#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */
#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
#define ICM_IDR_RBE_Pos _U_(8) /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */
#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */
#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
#define ICM_IDR_RWC_Pos _U_(12) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */
#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */
#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
#define ICM_IDR_REC_Pos _U_(16) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */
#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */
#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
#define ICM_IDR_RSU_Pos _U_(20) /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */
#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */
#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
#define ICM_IDR_URAD_Pos _U_(24) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */
#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */
#define ICM_IDR_URAD(value) (ICM_IDR_URAD_Msk & ((value) << ICM_IDR_URAD_Pos))
#define ICM_IDR_Msk _U_(0x01FFFFFF) /**< (ICM_IDR) Register Mask */
/* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask -------- */
#define ICM_IMR_RESETVALUE _U_(0x00) /**< (ICM_IMR) Interrupt Mask Reset Value */
#define ICM_IMR_RHC_Pos _U_(0) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */
#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */
#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
#define ICM_IMR_RDM_Pos _U_(4) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */
#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */
#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
#define ICM_IMR_RBE_Pos _U_(8) /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */
#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */
#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
#define ICM_IMR_RWC_Pos _U_(12) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */
#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */
#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
#define ICM_IMR_REC_Pos _U_(16) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */
#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */
#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
#define ICM_IMR_RSU_Pos _U_(20) /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */
#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */
#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
#define ICM_IMR_URAD_Pos _U_(24) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */
#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */
#define ICM_IMR_URAD(value) (ICM_IMR_URAD_Msk & ((value) << ICM_IMR_URAD_Pos))
#define ICM_IMR_Msk _U_(0x01FFFFFF) /**< (ICM_IMR) Register Mask */
/* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status -------- */
#define ICM_ISR_RESETVALUE _U_(0x00) /**< (ICM_ISR) Interrupt Status Reset Value */
#define ICM_ISR_RHC_Pos _U_(0) /**< (ICM_ISR) Region Hash Completed Position */
#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */
#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
#define ICM_ISR_RDM_Pos _U_(4) /**< (ICM_ISR) Region Digest Mismatch Position */
#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */
#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
#define ICM_ISR_RBE_Pos _U_(8) /**< (ICM_ISR) Region Bus Error Position */
#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */
#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
#define ICM_ISR_RWC_Pos _U_(12) /**< (ICM_ISR) Region Wrap Condition Detected Position */
#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */
#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
#define ICM_ISR_REC_Pos _U_(16) /**< (ICM_ISR) Region End bit Condition Detected Position */
#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */
#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
#define ICM_ISR_RSU_Pos _U_(20) /**< (ICM_ISR) Region Status Updated Detected Position */
#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */
#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
#define ICM_ISR_URAD_Pos _U_(24) /**< (ICM_ISR) Undefined Register Access Detection Status Position */
#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */
#define ICM_ISR_URAD(value) (ICM_ISR_URAD_Msk & ((value) << ICM_ISR_URAD_Pos))
#define ICM_ISR_Msk _U_(0x01FFFFFF) /**< (ICM_ISR) Register Mask */
/* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status -------- */
#define ICM_UASR_RESETVALUE _U_(0x00) /**< (ICM_UASR) Undefined Access Status Reset Value */
#define ICM_UASR_URAT_Pos _U_(0) /**< (ICM_UASR) Undefined Register Access Trace Position */
#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */
#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */
#define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) CFG modified during active monitoring */
#define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) DSCR modified during active monitoring */
#define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) HASH modified during active monitoring */
#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded Position */
#define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) CFG modified during active monitoring Position */
#define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) DSCR modified during active monitoring Position */
#define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) HASH modified during active monitoring Position */
#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */
#define ICM_UASR_Msk _U_(0x00000007) /**< (ICM_UASR) Register Mask */
/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
#define ICM_DSCR_RESETVALUE _U_(0x00) /**< (ICM_DSCR) Region Descriptor Area Start Address Reset Value */
#define ICM_DSCR_DASA_Pos _U_(6) /**< (ICM_DSCR) Descriptor Area Start Address Position */
#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */
#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */
/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
#define ICM_HASH_RESETVALUE _U_(0x00) /**< (ICM_HASH) Region Hash Area Start Address Reset Value */
#define ICM_HASH_HASA_Pos _U_(7) /**< (ICM_HASH) Hash Area Start Address Position */
#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */
#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */
/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
#define ICM_UIHVAL_RESETVALUE _U_(0x00) /**< (ICM_UIHVAL) User Initial Hash Value n Reset Value */
#define ICM_UIHVAL_VAL_Pos _U_(0) /**< (ICM_UIHVAL) Initial Hash Value Position */
#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */
#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */
/** \brief ICM register offsets definitions */
#define ICM_RADDR_REG_OFST (0x00) /**< (ICM_RADDR) Region Start Address Offset */
#define ICM_RCFG_REG_OFST (0x04) /**< (ICM_RCFG) Region Configuration Offset */
#define ICM_RCTRL_REG_OFST (0x08) /**< (ICM_RCTRL) Region Control Offset */
#define ICM_RNEXT_REG_OFST (0x0C) /**< (ICM_RNEXT) Region Next Address Offset */
#define ICM_CFG_REG_OFST (0x00) /**< (ICM_CFG) Configuration Offset */
#define ICM_CTRL_REG_OFST (0x04) /**< (ICM_CTRL) Control Offset */
#define ICM_SR_REG_OFST (0x08) /**< (ICM_SR) Status Offset */
#define ICM_IER_REG_OFST (0x10) /**< (ICM_IER) Interrupt Enable Offset */
#define ICM_IDR_REG_OFST (0x14) /**< (ICM_IDR) Interrupt Disable Offset */
#define ICM_IMR_REG_OFST (0x18) /**< (ICM_IMR) Interrupt Mask Offset */
#define ICM_ISR_REG_OFST (0x1C) /**< (ICM_ISR) Interrupt Status Offset */
#define ICM_UASR_REG_OFST (0x20) /**< (ICM_UASR) Undefined Access Status Offset */
#define ICM_DSCR_REG_OFST (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Offset */
#define ICM_HASH_REG_OFST (0x34) /**< (ICM_HASH) Region Hash Area Start Address Offset */
#define ICM_UIHVAL_REG_OFST (0x38) /**< (ICM_UIHVAL) User Initial Hash Value n Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief ICM_DESCRIPTOR register API structure */
typedef struct
{ /* Integrity Check Monitor */
__IO uint32_t ICM_RADDR; /**< Offset: 0x00 (R/W 32) Region Start Address */
__IO uint32_t ICM_RCFG; /**< Offset: 0x04 (R/W 32) Region Configuration */
__IO uint32_t ICM_RCTRL; /**< Offset: 0x08 (R/W 32) Region Control */
__IO uint32_t ICM_RNEXT; /**< Offset: 0x0C (R/W 32) Region Next Address */
} icm_descriptor_registers_t;
/** \brief ICM register API structure */
typedef struct
{ /* Integrity Check Monitor */
__IO uint32_t ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration */
__O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control */
__I uint32_t ICM_SR; /**< Offset: 0x08 (R/ 32) Status */
__I uint8_t Reserved1[0x04];
__O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable */
__O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable */
__I uint32_t ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask */
__I uint32_t ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status */
__I uint32_t ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status */
__I uint8_t Reserved2[0x0C];
__IO uint32_t ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */
__IO uint32_t ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address */
__O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value n */
} icm_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief ICM_DESCRIPTOR memory section attribute */
#define SECTION_ICM_DESCRIPTOR
#endif /* _SAMD51_ICM_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/mclk.h
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/**
* \brief Component description for MCLK
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_MCLK_COMPONENT_H_
#define _SAMD51_MCLK_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR MCLK */
/* ************************************************************************** */
/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< (MCLK_INTENCLR) Interrupt Enable Clear Reset Value */
#define MCLK_INTENCLR_CKRDY_Pos _U_(0) /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Position */
#define MCLK_INTENCLR_CKRDY_Msk (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos) /**< (MCLK_INTENCLR) Clock Ready Interrupt Enable Mask */
#define MCLK_INTENCLR_CKRDY(value) (MCLK_INTENCLR_CKRDY_Msk & ((value) << MCLK_INTENCLR_CKRDY_Pos))
#define MCLK_INTENCLR_Msk _U_(0x01) /**< (MCLK_INTENCLR) Register Mask */
/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< (MCLK_INTENSET) Interrupt Enable Set Reset Value */
#define MCLK_INTENSET_CKRDY_Pos _U_(0) /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Position */
#define MCLK_INTENSET_CKRDY_Msk (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos) /**< (MCLK_INTENSET) Clock Ready Interrupt Enable Mask */
#define MCLK_INTENSET_CKRDY(value) (MCLK_INTENSET_CKRDY_Msk & ((value) << MCLK_INTENSET_CKRDY_Pos))
#define MCLK_INTENSET_Msk _U_(0x01) /**< (MCLK_INTENSET) Register Mask */
/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< (MCLK_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define MCLK_INTFLAG_CKRDY_Pos _U_(0) /**< (MCLK_INTFLAG) Clock Ready Position */
#define MCLK_INTFLAG_CKRDY_Msk (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos) /**< (MCLK_INTFLAG) Clock Ready Mask */
#define MCLK_INTFLAG_CKRDY(value) (MCLK_INTFLAG_CKRDY_Msk & ((value) << MCLK_INTFLAG_CKRDY_Pos))
#define MCLK_INTFLAG_Msk _U_(0x01) /**< (MCLK_INTFLAG) Register Mask */
/* -------- MCLK_HSDIV : (MCLK Offset: 0x04) ( R/ 8) HS Clock Division -------- */
#define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< (MCLK_HSDIV) HS Clock Division Reset Value */
#define MCLK_HSDIV_DIV_Pos _U_(0) /**< (MCLK_HSDIV) CPU Clock Division Factor Position */
#define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos) /**< (MCLK_HSDIV) CPU Clock Division Factor Mask */
#define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
#define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< (MCLK_HSDIV) Divide by 1 */
#define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos) /**< (MCLK_HSDIV) Divide by 1 Position */
#define MCLK_HSDIV_Msk _U_(0xFF) /**< (MCLK_HSDIV) Register Mask */
/* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< (MCLK_CPUDIV) CPU Clock Division Reset Value */
#define MCLK_CPUDIV_DIV_Pos _U_(0) /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Position */
#define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Low-Power Clock Division Factor Mask */
#define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
#define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< (MCLK_CPUDIV) Divide by 1 */
#define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< (MCLK_CPUDIV) Divide by 2 */
#define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< (MCLK_CPUDIV) Divide by 4 */
#define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< (MCLK_CPUDIV) Divide by 8 */
#define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< (MCLK_CPUDIV) Divide by 16 */
#define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< (MCLK_CPUDIV) Divide by 32 */
#define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< (MCLK_CPUDIV) Divide by 64 */
#define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< (MCLK_CPUDIV) Divide by 128 */
#define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 1 Position */
#define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 2 Position */
#define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 4 Position */
#define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 8 Position */
#define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 16 Position */
#define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 32 Position */
#define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 64 Position */
#define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos) /**< (MCLK_CPUDIV) Divide by 128 Position */
#define MCLK_CPUDIV_Msk _U_(0xFF) /**< (MCLK_CPUDIV) Register Mask */
/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
#define MCLK_AHBMASK_RESETVALUE _U_(0xFFFFFF) /**< (MCLK_AHBMASK) AHB Mask Reset Value */
#define MCLK_AHBMASK_HPB0_Pos _U_(0) /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Position */
#define MCLK_AHBMASK_HPB0_Msk (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos) /**< (MCLK_AHBMASK) HPB0 AHB Clock Mask Mask */
#define MCLK_AHBMASK_HPB0(value) (MCLK_AHBMASK_HPB0_Msk & ((value) << MCLK_AHBMASK_HPB0_Pos))
#define MCLK_AHBMASK_HPB1_Pos _U_(1) /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Position */
#define MCLK_AHBMASK_HPB1_Msk (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos) /**< (MCLK_AHBMASK) HPB1 AHB Clock Mask Mask */
#define MCLK_AHBMASK_HPB1(value) (MCLK_AHBMASK_HPB1_Msk & ((value) << MCLK_AHBMASK_HPB1_Pos))
#define MCLK_AHBMASK_HPB2_Pos _U_(2) /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Position */
#define MCLK_AHBMASK_HPB2_Msk (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos) /**< (MCLK_AHBMASK) HPB2 AHB Clock Mask Mask */
#define MCLK_AHBMASK_HPB2(value) (MCLK_AHBMASK_HPB2_Msk & ((value) << MCLK_AHBMASK_HPB2_Pos))
#define MCLK_AHBMASK_HPB3_Pos _U_(3) /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Position */
#define MCLK_AHBMASK_HPB3_Msk (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos) /**< (MCLK_AHBMASK) HPB3 AHB Clock Mask Mask */
#define MCLK_AHBMASK_HPB3(value) (MCLK_AHBMASK_HPB3_Msk & ((value) << MCLK_AHBMASK_HPB3_Pos))
#define MCLK_AHBMASK_DSU_Pos _U_(4) /**< (MCLK_AHBMASK) DSU AHB Clock Mask Position */
#define MCLK_AHBMASK_DSU_Msk (_U_(0x1) << MCLK_AHBMASK_DSU_Pos) /**< (MCLK_AHBMASK) DSU AHB Clock Mask Mask */
#define MCLK_AHBMASK_DSU(value) (MCLK_AHBMASK_DSU_Msk & ((value) << MCLK_AHBMASK_DSU_Pos))
#define MCLK_AHBMASK_HMATRIX_Pos _U_(5) /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Position */
#define MCLK_AHBMASK_HMATRIX_Msk (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos) /**< (MCLK_AHBMASK) HMATRIX AHB Clock Mask Mask */
#define MCLK_AHBMASK_HMATRIX(value) (MCLK_AHBMASK_HMATRIX_Msk & ((value) << MCLK_AHBMASK_HMATRIX_Pos))
#define MCLK_AHBMASK_NVMCTRL_Pos _U_(6) /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Position */
#define MCLK_AHBMASK_NVMCTRL_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos) /**< (MCLK_AHBMASK) NVMCTRL AHB Clock Mask Mask */
#define MCLK_AHBMASK_NVMCTRL(value) (MCLK_AHBMASK_NVMCTRL_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_Pos))
#define MCLK_AHBMASK_HSRAM_Pos _U_(7) /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Position */
#define MCLK_AHBMASK_HSRAM_Msk (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos) /**< (MCLK_AHBMASK) HSRAM AHB Clock Mask Mask */
#define MCLK_AHBMASK_HSRAM(value) (MCLK_AHBMASK_HSRAM_Msk & ((value) << MCLK_AHBMASK_HSRAM_Pos))
#define MCLK_AHBMASK_CMCC_Pos _U_(8) /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Position */
#define MCLK_AHBMASK_CMCC_Msk (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos) /**< (MCLK_AHBMASK) CMCC AHB Clock Mask Mask */
#define MCLK_AHBMASK_CMCC(value) (MCLK_AHBMASK_CMCC_Msk & ((value) << MCLK_AHBMASK_CMCC_Pos))
#define MCLK_AHBMASK_DMAC_Pos _U_(9) /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Position */
#define MCLK_AHBMASK_DMAC_Msk (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos) /**< (MCLK_AHBMASK) DMAC AHB Clock Mask Mask */
#define MCLK_AHBMASK_DMAC(value) (MCLK_AHBMASK_DMAC_Msk & ((value) << MCLK_AHBMASK_DMAC_Pos))
#define MCLK_AHBMASK_USB_Pos _U_(10) /**< (MCLK_AHBMASK) USB AHB Clock Mask Position */
#define MCLK_AHBMASK_USB_Msk (_U_(0x1) << MCLK_AHBMASK_USB_Pos) /**< (MCLK_AHBMASK) USB AHB Clock Mask Mask */
#define MCLK_AHBMASK_USB(value) (MCLK_AHBMASK_USB_Msk & ((value) << MCLK_AHBMASK_USB_Pos))
#define MCLK_AHBMASK_BKUPRAM_Pos _U_(11) /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Position */
#define MCLK_AHBMASK_BKUPRAM_Msk (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos) /**< (MCLK_AHBMASK) BKUPRAM AHB Clock Mask Mask */
#define MCLK_AHBMASK_BKUPRAM(value) (MCLK_AHBMASK_BKUPRAM_Msk & ((value) << MCLK_AHBMASK_BKUPRAM_Pos))
#define MCLK_AHBMASK_PAC_Pos _U_(12) /**< (MCLK_AHBMASK) PAC AHB Clock Mask Position */
#define MCLK_AHBMASK_PAC_Msk (_U_(0x1) << MCLK_AHBMASK_PAC_Pos) /**< (MCLK_AHBMASK) PAC AHB Clock Mask Mask */
#define MCLK_AHBMASK_PAC(value) (MCLK_AHBMASK_PAC_Msk & ((value) << MCLK_AHBMASK_PAC_Pos))
#define MCLK_AHBMASK_QSPI_Pos _U_(13) /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Position */
#define MCLK_AHBMASK_QSPI_Msk (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos) /**< (MCLK_AHBMASK) QSPI AHB Clock Mask Mask */
#define MCLK_AHBMASK_QSPI(value) (MCLK_AHBMASK_QSPI_Msk & ((value) << MCLK_AHBMASK_QSPI_Pos))
#define MCLK_AHBMASK_SDHC0_Pos _U_(15) /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Position */
#define MCLK_AHBMASK_SDHC0_Msk (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos) /**< (MCLK_AHBMASK) SDHC0 AHB Clock Mask Mask */
#define MCLK_AHBMASK_SDHC0(value) (MCLK_AHBMASK_SDHC0_Msk & ((value) << MCLK_AHBMASK_SDHC0_Pos))
#define MCLK_AHBMASK_SDHC1_Pos _U_(16) /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Position */
#define MCLK_AHBMASK_SDHC1_Msk (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos) /**< (MCLK_AHBMASK) SDHC1 AHB Clock Mask Mask */
#define MCLK_AHBMASK_SDHC1(value) (MCLK_AHBMASK_SDHC1_Msk & ((value) << MCLK_AHBMASK_SDHC1_Pos))
#define MCLK_AHBMASK_ICM_Pos _U_(19) /**< (MCLK_AHBMASK) ICM AHB Clock Mask Position */
#define MCLK_AHBMASK_ICM_Msk (_U_(0x1) << MCLK_AHBMASK_ICM_Pos) /**< (MCLK_AHBMASK) ICM AHB Clock Mask Mask */
#define MCLK_AHBMASK_ICM(value) (MCLK_AHBMASK_ICM_Msk & ((value) << MCLK_AHBMASK_ICM_Pos))
#define MCLK_AHBMASK_PUKCC_Pos _U_(20) /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Position */
#define MCLK_AHBMASK_PUKCC_Msk (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos) /**< (MCLK_AHBMASK) PUKCC AHB Clock Mask Mask */
#define MCLK_AHBMASK_PUKCC(value) (MCLK_AHBMASK_PUKCC_Msk & ((value) << MCLK_AHBMASK_PUKCC_Pos))
#define MCLK_AHBMASK_QSPI_2X_Pos _U_(21) /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Position */
#define MCLK_AHBMASK_QSPI_2X_Msk (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos) /**< (MCLK_AHBMASK) QSPI_2X AHB Clock Mask Mask */
#define MCLK_AHBMASK_QSPI_2X(value) (MCLK_AHBMASK_QSPI_2X_Msk & ((value) << MCLK_AHBMASK_QSPI_2X_Pos))
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos _U_(22) /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Position */
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos) /**< (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask Mask */
#define MCLK_AHBMASK_NVMCTRL_SMEEPROM(value) (MCLK_AHBMASK_NVMCTRL_SMEEPROM_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos))
#define MCLK_AHBMASK_NVMCTRL_CACHE_Pos _U_(23) /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Position */
#define MCLK_AHBMASK_NVMCTRL_CACHE_Msk (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos) /**< (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask Mask */
#define MCLK_AHBMASK_NVMCTRL_CACHE(value) (MCLK_AHBMASK_NVMCTRL_CACHE_Msk & ((value) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos))
#define MCLK_AHBMASK_Msk _U_(0x00F9BFFF) /**< (MCLK_AHBMASK) Register Mask */
#define MCLK_AHBMASK_HPB_Pos _U_(0) /**< (MCLK_AHBMASK Position) HPBx AHB Clock Mask */
#define MCLK_AHBMASK_HPB_Msk (_U_(0xF) << MCLK_AHBMASK_HPB_Pos) /**< (MCLK_AHBMASK Mask) HPB */
#define MCLK_AHBMASK_HPB(value) (MCLK_AHBMASK_HPB_Msk & ((value) << MCLK_AHBMASK_HPB_Pos))
#define MCLK_AHBMASK_SDHC_Pos _U_(15) /**< (MCLK_AHBMASK Position) SDHCx AHB Clock Mask */
#define MCLK_AHBMASK_SDHC_Msk (_U_(0x3) << MCLK_AHBMASK_SDHC_Pos) /**< (MCLK_AHBMASK Mask) SDHC */
#define MCLK_AHBMASK_SDHC(value) (MCLK_AHBMASK_SDHC_Msk & ((value) << MCLK_AHBMASK_SDHC_Pos))
/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
#define MCLK_APBAMASK_RESETVALUE _U_(0x7FF) /**< (MCLK_APBAMASK) APBA Mask Reset Value */
#define MCLK_APBAMASK_PAC_Pos _U_(0) /**< (MCLK_APBAMASK) PAC APB Clock Enable Position */
#define MCLK_APBAMASK_PAC_Msk (_U_(0x1) << MCLK_APBAMASK_PAC_Pos) /**< (MCLK_APBAMASK) PAC APB Clock Enable Mask */
#define MCLK_APBAMASK_PAC(value) (MCLK_APBAMASK_PAC_Msk & ((value) << MCLK_APBAMASK_PAC_Pos))
#define MCLK_APBAMASK_PM_Pos _U_(1) /**< (MCLK_APBAMASK) PM APB Clock Enable Position */
#define MCLK_APBAMASK_PM_Msk (_U_(0x1) << MCLK_APBAMASK_PM_Pos) /**< (MCLK_APBAMASK) PM APB Clock Enable Mask */
#define MCLK_APBAMASK_PM(value) (MCLK_APBAMASK_PM_Msk & ((value) << MCLK_APBAMASK_PM_Pos))
#define MCLK_APBAMASK_MCLK_Pos _U_(2) /**< (MCLK_APBAMASK) MCLK APB Clock Enable Position */
#define MCLK_APBAMASK_MCLK_Msk (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos) /**< (MCLK_APBAMASK) MCLK APB Clock Enable Mask */
#define MCLK_APBAMASK_MCLK(value) (MCLK_APBAMASK_MCLK_Msk & ((value) << MCLK_APBAMASK_MCLK_Pos))
#define MCLK_APBAMASK_RSTC_Pos _U_(3) /**< (MCLK_APBAMASK) RSTC APB Clock Enable Position */
#define MCLK_APBAMASK_RSTC_Msk (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos) /**< (MCLK_APBAMASK) RSTC APB Clock Enable Mask */
#define MCLK_APBAMASK_RSTC(value) (MCLK_APBAMASK_RSTC_Msk & ((value) << MCLK_APBAMASK_RSTC_Pos))
#define MCLK_APBAMASK_OSCCTRL_Pos _U_(4) /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Position */
#define MCLK_APBAMASK_OSCCTRL_Msk (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos) /**< (MCLK_APBAMASK) OSCCTRL APB Clock Enable Mask */
#define MCLK_APBAMASK_OSCCTRL(value) (MCLK_APBAMASK_OSCCTRL_Msk & ((value) << MCLK_APBAMASK_OSCCTRL_Pos))
#define MCLK_APBAMASK_OSC32KCTRL_Pos _U_(5) /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Position */
#define MCLK_APBAMASK_OSC32KCTRL_Msk (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos) /**< (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable Mask */
#define MCLK_APBAMASK_OSC32KCTRL(value) (MCLK_APBAMASK_OSC32KCTRL_Msk & ((value) << MCLK_APBAMASK_OSC32KCTRL_Pos))
#define MCLK_APBAMASK_SUPC_Pos _U_(6) /**< (MCLK_APBAMASK) SUPC APB Clock Enable Position */
#define MCLK_APBAMASK_SUPC_Msk (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos) /**< (MCLK_APBAMASK) SUPC APB Clock Enable Mask */
#define MCLK_APBAMASK_SUPC(value) (MCLK_APBAMASK_SUPC_Msk & ((value) << MCLK_APBAMASK_SUPC_Pos))
#define MCLK_APBAMASK_GCLK_Pos _U_(7) /**< (MCLK_APBAMASK) GCLK APB Clock Enable Position */
#define MCLK_APBAMASK_GCLK_Msk (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos) /**< (MCLK_APBAMASK) GCLK APB Clock Enable Mask */
#define MCLK_APBAMASK_GCLK(value) (MCLK_APBAMASK_GCLK_Msk & ((value) << MCLK_APBAMASK_GCLK_Pos))
#define MCLK_APBAMASK_WDT_Pos _U_(8) /**< (MCLK_APBAMASK) WDT APB Clock Enable Position */
#define MCLK_APBAMASK_WDT_Msk (_U_(0x1) << MCLK_APBAMASK_WDT_Pos) /**< (MCLK_APBAMASK) WDT APB Clock Enable Mask */
#define MCLK_APBAMASK_WDT(value) (MCLK_APBAMASK_WDT_Msk & ((value) << MCLK_APBAMASK_WDT_Pos))
#define MCLK_APBAMASK_RTC_Pos _U_(9) /**< (MCLK_APBAMASK) RTC APB Clock Enable Position */
#define MCLK_APBAMASK_RTC_Msk (_U_(0x1) << MCLK_APBAMASK_RTC_Pos) /**< (MCLK_APBAMASK) RTC APB Clock Enable Mask */
#define MCLK_APBAMASK_RTC(value) (MCLK_APBAMASK_RTC_Msk & ((value) << MCLK_APBAMASK_RTC_Pos))
#define MCLK_APBAMASK_EIC_Pos _U_(10) /**< (MCLK_APBAMASK) EIC APB Clock Enable Position */
#define MCLK_APBAMASK_EIC_Msk (_U_(0x1) << MCLK_APBAMASK_EIC_Pos) /**< (MCLK_APBAMASK) EIC APB Clock Enable Mask */
#define MCLK_APBAMASK_EIC(value) (MCLK_APBAMASK_EIC_Msk & ((value) << MCLK_APBAMASK_EIC_Pos))
#define MCLK_APBAMASK_FREQM_Pos _U_(11) /**< (MCLK_APBAMASK) FREQM APB Clock Enable Position */
#define MCLK_APBAMASK_FREQM_Msk (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos) /**< (MCLK_APBAMASK) FREQM APB Clock Enable Mask */
#define MCLK_APBAMASK_FREQM(value) (MCLK_APBAMASK_FREQM_Msk & ((value) << MCLK_APBAMASK_FREQM_Pos))
#define MCLK_APBAMASK_SERCOM0_Pos _U_(12) /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Position */
#define MCLK_APBAMASK_SERCOM0_Msk (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos) /**< (MCLK_APBAMASK) SERCOM0 APB Clock Enable Mask */
#define MCLK_APBAMASK_SERCOM0(value) (MCLK_APBAMASK_SERCOM0_Msk & ((value) << MCLK_APBAMASK_SERCOM0_Pos))
#define MCLK_APBAMASK_SERCOM1_Pos _U_(13) /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Position */
#define MCLK_APBAMASK_SERCOM1_Msk (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos) /**< (MCLK_APBAMASK) SERCOM1 APB Clock Enable Mask */
#define MCLK_APBAMASK_SERCOM1(value) (MCLK_APBAMASK_SERCOM1_Msk & ((value) << MCLK_APBAMASK_SERCOM1_Pos))
#define MCLK_APBAMASK_TC0_Pos _U_(14) /**< (MCLK_APBAMASK) TC0 APB Clock Enable Position */
#define MCLK_APBAMASK_TC0_Msk (_U_(0x1) << MCLK_APBAMASK_TC0_Pos) /**< (MCLK_APBAMASK) TC0 APB Clock Enable Mask */
#define MCLK_APBAMASK_TC0(value) (MCLK_APBAMASK_TC0_Msk & ((value) << MCLK_APBAMASK_TC0_Pos))
#define MCLK_APBAMASK_TC1_Pos _U_(15) /**< (MCLK_APBAMASK) TC1 APB Clock Enable Position */
#define MCLK_APBAMASK_TC1_Msk (_U_(0x1) << MCLK_APBAMASK_TC1_Pos) /**< (MCLK_APBAMASK) TC1 APB Clock Enable Mask */
#define MCLK_APBAMASK_TC1(value) (MCLK_APBAMASK_TC1_Msk & ((value) << MCLK_APBAMASK_TC1_Pos))
#define MCLK_APBAMASK_Msk _U_(0x0000FFFF) /**< (MCLK_APBAMASK) Register Mask */
#define MCLK_APBAMASK_SERCOM_Pos _U_(12) /**< (MCLK_APBAMASK Position) SERCOMx APB Clock Enable */
#define MCLK_APBAMASK_SERCOM_Msk (_U_(0x3) << MCLK_APBAMASK_SERCOM_Pos) /**< (MCLK_APBAMASK Mask) SERCOM */
#define MCLK_APBAMASK_SERCOM(value) (MCLK_APBAMASK_SERCOM_Msk & ((value) << MCLK_APBAMASK_SERCOM_Pos))
#define MCLK_APBAMASK_TC_Pos _U_(14) /**< (MCLK_APBAMASK Position) TCx APB Clock Enable */
#define MCLK_APBAMASK_TC_Msk (_U_(0x3) << MCLK_APBAMASK_TC_Pos) /**< (MCLK_APBAMASK Mask) TC */
#define MCLK_APBAMASK_TC(value) (MCLK_APBAMASK_TC_Msk & ((value) << MCLK_APBAMASK_TC_Pos))
/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
#define MCLK_APBBMASK_RESETVALUE _U_(0x18056) /**< (MCLK_APBBMASK) APBB Mask Reset Value */
#define MCLK_APBBMASK_USB_Pos _U_(0) /**< (MCLK_APBBMASK) USB APB Clock Enable Position */
#define MCLK_APBBMASK_USB_Msk (_U_(0x1) << MCLK_APBBMASK_USB_Pos) /**< (MCLK_APBBMASK) USB APB Clock Enable Mask */
#define MCLK_APBBMASK_USB(value) (MCLK_APBBMASK_USB_Msk & ((value) << MCLK_APBBMASK_USB_Pos))
#define MCLK_APBBMASK_DSU_Pos _U_(1) /**< (MCLK_APBBMASK) DSU APB Clock Enable Position */
#define MCLK_APBBMASK_DSU_Msk (_U_(0x1) << MCLK_APBBMASK_DSU_Pos) /**< (MCLK_APBBMASK) DSU APB Clock Enable Mask */
#define MCLK_APBBMASK_DSU(value) (MCLK_APBBMASK_DSU_Msk & ((value) << MCLK_APBBMASK_DSU_Pos))
#define MCLK_APBBMASK_NVMCTRL_Pos _U_(2) /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Position */
#define MCLK_APBBMASK_NVMCTRL_Msk (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos) /**< (MCLK_APBBMASK) NVMCTRL APB Clock Enable Mask */
#define MCLK_APBBMASK_NVMCTRL(value) (MCLK_APBBMASK_NVMCTRL_Msk & ((value) << MCLK_APBBMASK_NVMCTRL_Pos))
#define MCLK_APBBMASK_PORT_Pos _U_(4) /**< (MCLK_APBBMASK) PORT APB Clock Enable Position */
#define MCLK_APBBMASK_PORT_Msk (_U_(0x1) << MCLK_APBBMASK_PORT_Pos) /**< (MCLK_APBBMASK) PORT APB Clock Enable Mask */
#define MCLK_APBBMASK_PORT(value) (MCLK_APBBMASK_PORT_Msk & ((value) << MCLK_APBBMASK_PORT_Pos))
#define MCLK_APBBMASK_HMATRIX_Pos _U_(6) /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Position */
#define MCLK_APBBMASK_HMATRIX_Msk (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos) /**< (MCLK_APBBMASK) HMATRIX APB Clock Enable Mask */
#define MCLK_APBBMASK_HMATRIX(value) (MCLK_APBBMASK_HMATRIX_Msk & ((value) << MCLK_APBBMASK_HMATRIX_Pos))
#define MCLK_APBBMASK_EVSYS_Pos _U_(7) /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Position */
#define MCLK_APBBMASK_EVSYS_Msk (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos) /**< (MCLK_APBBMASK) EVSYS APB Clock Enable Mask */
#define MCLK_APBBMASK_EVSYS(value) (MCLK_APBBMASK_EVSYS_Msk & ((value) << MCLK_APBBMASK_EVSYS_Pos))
#define MCLK_APBBMASK_SERCOM2_Pos _U_(9) /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Position */
#define MCLK_APBBMASK_SERCOM2_Msk (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos) /**< (MCLK_APBBMASK) SERCOM2 APB Clock Enable Mask */
#define MCLK_APBBMASK_SERCOM2(value) (MCLK_APBBMASK_SERCOM2_Msk & ((value) << MCLK_APBBMASK_SERCOM2_Pos))
#define MCLK_APBBMASK_SERCOM3_Pos _U_(10) /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Position */
#define MCLK_APBBMASK_SERCOM3_Msk (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos) /**< (MCLK_APBBMASK) SERCOM3 APB Clock Enable Mask */
#define MCLK_APBBMASK_SERCOM3(value) (MCLK_APBBMASK_SERCOM3_Msk & ((value) << MCLK_APBBMASK_SERCOM3_Pos))
#define MCLK_APBBMASK_TCC0_Pos _U_(11) /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Position */
#define MCLK_APBBMASK_TCC0_Msk (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos) /**< (MCLK_APBBMASK) TCC0 APB Clock Enable Mask */
#define MCLK_APBBMASK_TCC0(value) (MCLK_APBBMASK_TCC0_Msk & ((value) << MCLK_APBBMASK_TCC0_Pos))
#define MCLK_APBBMASK_TCC1_Pos _U_(12) /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Position */
#define MCLK_APBBMASK_TCC1_Msk (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos) /**< (MCLK_APBBMASK) TCC1 APB Clock Enable Mask */
#define MCLK_APBBMASK_TCC1(value) (MCLK_APBBMASK_TCC1_Msk & ((value) << MCLK_APBBMASK_TCC1_Pos))
#define MCLK_APBBMASK_TC2_Pos _U_(13) /**< (MCLK_APBBMASK) TC2 APB Clock Enable Position */
#define MCLK_APBBMASK_TC2_Msk (_U_(0x1) << MCLK_APBBMASK_TC2_Pos) /**< (MCLK_APBBMASK) TC2 APB Clock Enable Mask */
#define MCLK_APBBMASK_TC2(value) (MCLK_APBBMASK_TC2_Msk & ((value) << MCLK_APBBMASK_TC2_Pos))
#define MCLK_APBBMASK_TC3_Pos _U_(14) /**< (MCLK_APBBMASK) TC3 APB Clock Enable Position */
#define MCLK_APBBMASK_TC3_Msk (_U_(0x1) << MCLK_APBBMASK_TC3_Pos) /**< (MCLK_APBBMASK) TC3 APB Clock Enable Mask */
#define MCLK_APBBMASK_TC3(value) (MCLK_APBBMASK_TC3_Msk & ((value) << MCLK_APBBMASK_TC3_Pos))
#define MCLK_APBBMASK_RAMECC_Pos _U_(16) /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Position */
#define MCLK_APBBMASK_RAMECC_Msk (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos) /**< (MCLK_APBBMASK) RAMECC APB Clock Enable Mask */
#define MCLK_APBBMASK_RAMECC(value) (MCLK_APBBMASK_RAMECC_Msk & ((value) << MCLK_APBBMASK_RAMECC_Pos))
#define MCLK_APBBMASK_Msk _U_(0x00017ED7) /**< (MCLK_APBBMASK) Register Mask */
#define MCLK_APBBMASK_SERCOM_Pos _U_(9) /**< (MCLK_APBBMASK Position) SERCOM2 APB Clock Enable */
#define MCLK_APBBMASK_SERCOM_Msk (_U_(0x3) << MCLK_APBBMASK_SERCOM_Pos) /**< (MCLK_APBBMASK Mask) SERCOM */
#define MCLK_APBBMASK_SERCOM(value) (MCLK_APBBMASK_SERCOM_Msk & ((value) << MCLK_APBBMASK_SERCOM_Pos))
#define MCLK_APBBMASK_TCC_Pos _U_(11) /**< (MCLK_APBBMASK Position) TCCx APB Clock Enable */
#define MCLK_APBBMASK_TCC_Msk (_U_(0x3) << MCLK_APBBMASK_TCC_Pos) /**< (MCLK_APBBMASK Mask) TCC */
#define MCLK_APBBMASK_TCC(value) (MCLK_APBBMASK_TCC_Msk & ((value) << MCLK_APBBMASK_TCC_Pos))
#define MCLK_APBBMASK_TC_Pos _U_(13) /**< (MCLK_APBBMASK Position) TC2 APB Clock Enable */
#define MCLK_APBBMASK_TC_Msk (_U_(0x3) << MCLK_APBBMASK_TC_Pos) /**< (MCLK_APBBMASK Mask) TC */
#define MCLK_APBBMASK_TC(value) (MCLK_APBBMASK_TC_Msk & ((value) << MCLK_APBBMASK_TC_Pos))
/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
#define MCLK_APBCMASK_RESETVALUE _U_(0x2000) /**< (MCLK_APBCMASK) APBC Mask Reset Value */
#define MCLK_APBCMASK_TCC2_Pos _U_(3) /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Position */
#define MCLK_APBCMASK_TCC2_Msk (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos) /**< (MCLK_APBCMASK) TCC2 APB Clock Enable Mask */
#define MCLK_APBCMASK_TCC2(value) (MCLK_APBCMASK_TCC2_Msk & ((value) << MCLK_APBCMASK_TCC2_Pos))
#define MCLK_APBCMASK_TCC3_Pos _U_(4) /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Position */
#define MCLK_APBCMASK_TCC3_Msk (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos) /**< (MCLK_APBCMASK) TCC3 APB Clock Enable Mask */
#define MCLK_APBCMASK_TCC3(value) (MCLK_APBCMASK_TCC3_Msk & ((value) << MCLK_APBCMASK_TCC3_Pos))
#define MCLK_APBCMASK_TC4_Pos _U_(5) /**< (MCLK_APBCMASK) TC4 APB Clock Enable Position */
#define MCLK_APBCMASK_TC4_Msk (_U_(0x1) << MCLK_APBCMASK_TC4_Pos) /**< (MCLK_APBCMASK) TC4 APB Clock Enable Mask */
#define MCLK_APBCMASK_TC4(value) (MCLK_APBCMASK_TC4_Msk & ((value) << MCLK_APBCMASK_TC4_Pos))
#define MCLK_APBCMASK_TC5_Pos _U_(6) /**< (MCLK_APBCMASK) TC5 APB Clock Enable Position */
#define MCLK_APBCMASK_TC5_Msk (_U_(0x1) << MCLK_APBCMASK_TC5_Pos) /**< (MCLK_APBCMASK) TC5 APB Clock Enable Mask */
#define MCLK_APBCMASK_TC5(value) (MCLK_APBCMASK_TC5_Msk & ((value) << MCLK_APBCMASK_TC5_Pos))
#define MCLK_APBCMASK_PDEC_Pos _U_(7) /**< (MCLK_APBCMASK) PDEC APB Clock Enable Position */
#define MCLK_APBCMASK_PDEC_Msk (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos) /**< (MCLK_APBCMASK) PDEC APB Clock Enable Mask */
#define MCLK_APBCMASK_PDEC(value) (MCLK_APBCMASK_PDEC_Msk & ((value) << MCLK_APBCMASK_PDEC_Pos))
#define MCLK_APBCMASK_AC_Pos _U_(8) /**< (MCLK_APBCMASK) AC APB Clock Enable Position */
#define MCLK_APBCMASK_AC_Msk (_U_(0x1) << MCLK_APBCMASK_AC_Pos) /**< (MCLK_APBCMASK) AC APB Clock Enable Mask */
#define MCLK_APBCMASK_AC(value) (MCLK_APBCMASK_AC_Msk & ((value) << MCLK_APBCMASK_AC_Pos))
#define MCLK_APBCMASK_AES_Pos _U_(9) /**< (MCLK_APBCMASK) AES APB Clock Enable Position */
#define MCLK_APBCMASK_AES_Msk (_U_(0x1) << MCLK_APBCMASK_AES_Pos) /**< (MCLK_APBCMASK) AES APB Clock Enable Mask */
#define MCLK_APBCMASK_AES(value) (MCLK_APBCMASK_AES_Msk & ((value) << MCLK_APBCMASK_AES_Pos))
#define MCLK_APBCMASK_TRNG_Pos _U_(10) /**< (MCLK_APBCMASK) TRNG APB Clock Enable Position */
#define MCLK_APBCMASK_TRNG_Msk (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos) /**< (MCLK_APBCMASK) TRNG APB Clock Enable Mask */
#define MCLK_APBCMASK_TRNG(value) (MCLK_APBCMASK_TRNG_Msk & ((value) << MCLK_APBCMASK_TRNG_Pos))
#define MCLK_APBCMASK_ICM_Pos _U_(11) /**< (MCLK_APBCMASK) ICM APB Clock Enable Position */
#define MCLK_APBCMASK_ICM_Msk (_U_(0x1) << MCLK_APBCMASK_ICM_Pos) /**< (MCLK_APBCMASK) ICM APB Clock Enable Mask */
#define MCLK_APBCMASK_ICM(value) (MCLK_APBCMASK_ICM_Msk & ((value) << MCLK_APBCMASK_ICM_Pos))
#define MCLK_APBCMASK_QSPI_Pos _U_(13) /**< (MCLK_APBCMASK) QSPI APB Clock Enable Position */
#define MCLK_APBCMASK_QSPI_Msk (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos) /**< (MCLK_APBCMASK) QSPI APB Clock Enable Mask */
#define MCLK_APBCMASK_QSPI(value) (MCLK_APBCMASK_QSPI_Msk & ((value) << MCLK_APBCMASK_QSPI_Pos))
#define MCLK_APBCMASK_CCL_Pos _U_(14) /**< (MCLK_APBCMASK) CCL APB Clock Enable Position */
#define MCLK_APBCMASK_CCL_Msk (_U_(0x1) << MCLK_APBCMASK_CCL_Pos) /**< (MCLK_APBCMASK) CCL APB Clock Enable Mask */
#define MCLK_APBCMASK_CCL(value) (MCLK_APBCMASK_CCL_Msk & ((value) << MCLK_APBCMASK_CCL_Pos))
#define MCLK_APBCMASK_Msk _U_(0x00006FF8) /**< (MCLK_APBCMASK) Register Mask */
#define MCLK_APBCMASK_TCC_Pos _U_(3) /**< (MCLK_APBCMASK Position) TCC2 APB Clock Enable */
#define MCLK_APBCMASK_TCC_Msk (_U_(0x3) << MCLK_APBCMASK_TCC_Pos) /**< (MCLK_APBCMASK Mask) TCC */
#define MCLK_APBCMASK_TCC(value) (MCLK_APBCMASK_TCC_Msk & ((value) << MCLK_APBCMASK_TCC_Pos))
#define MCLK_APBCMASK_TC_Pos _U_(5) /**< (MCLK_APBCMASK Position) TC4 APB Clock Enable */
#define MCLK_APBCMASK_TC_Msk (_U_(0x3) << MCLK_APBCMASK_TC_Pos) /**< (MCLK_APBCMASK Mask) TC */
#define MCLK_APBCMASK_TC(value) (MCLK_APBCMASK_TC_Msk & ((value) << MCLK_APBCMASK_TC_Pos))
/* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
#define MCLK_APBDMASK_RESETVALUE _U_(0x00) /**< (MCLK_APBDMASK) APBD Mask Reset Value */
#define MCLK_APBDMASK_SERCOM4_Pos _U_(0) /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Position */
#define MCLK_APBDMASK_SERCOM4_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos) /**< (MCLK_APBDMASK) SERCOM4 APB Clock Enable Mask */
#define MCLK_APBDMASK_SERCOM4(value) (MCLK_APBDMASK_SERCOM4_Msk & ((value) << MCLK_APBDMASK_SERCOM4_Pos))
#define MCLK_APBDMASK_SERCOM5_Pos _U_(1) /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Position */
#define MCLK_APBDMASK_SERCOM5_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos) /**< (MCLK_APBDMASK) SERCOM5 APB Clock Enable Mask */
#define MCLK_APBDMASK_SERCOM5(value) (MCLK_APBDMASK_SERCOM5_Msk & ((value) << MCLK_APBDMASK_SERCOM5_Pos))
#define MCLK_APBDMASK_SERCOM6_Pos _U_(2) /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Position */
#define MCLK_APBDMASK_SERCOM6_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos) /**< (MCLK_APBDMASK) SERCOM6 APB Clock Enable Mask */
#define MCLK_APBDMASK_SERCOM6(value) (MCLK_APBDMASK_SERCOM6_Msk & ((value) << MCLK_APBDMASK_SERCOM6_Pos))
#define MCLK_APBDMASK_SERCOM7_Pos _U_(3) /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Position */
#define MCLK_APBDMASK_SERCOM7_Msk (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos) /**< (MCLK_APBDMASK) SERCOM7 APB Clock Enable Mask */
#define MCLK_APBDMASK_SERCOM7(value) (MCLK_APBDMASK_SERCOM7_Msk & ((value) << MCLK_APBDMASK_SERCOM7_Pos))
#define MCLK_APBDMASK_TCC4_Pos _U_(4) /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Position */
#define MCLK_APBDMASK_TCC4_Msk (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos) /**< (MCLK_APBDMASK) TCC4 APB Clock Enable Mask */
#define MCLK_APBDMASK_TCC4(value) (MCLK_APBDMASK_TCC4_Msk & ((value) << MCLK_APBDMASK_TCC4_Pos))
#define MCLK_APBDMASK_TC6_Pos _U_(5) /**< (MCLK_APBDMASK) TC6 APB Clock Enable Position */
#define MCLK_APBDMASK_TC6_Msk (_U_(0x1) << MCLK_APBDMASK_TC6_Pos) /**< (MCLK_APBDMASK) TC6 APB Clock Enable Mask */
#define MCLK_APBDMASK_TC6(value) (MCLK_APBDMASK_TC6_Msk & ((value) << MCLK_APBDMASK_TC6_Pos))
#define MCLK_APBDMASK_TC7_Pos _U_(6) /**< (MCLK_APBDMASK) TC7 APB Clock Enable Position */
#define MCLK_APBDMASK_TC7_Msk (_U_(0x1) << MCLK_APBDMASK_TC7_Pos) /**< (MCLK_APBDMASK) TC7 APB Clock Enable Mask */
#define MCLK_APBDMASK_TC7(value) (MCLK_APBDMASK_TC7_Msk & ((value) << MCLK_APBDMASK_TC7_Pos))
#define MCLK_APBDMASK_ADC0_Pos _U_(7) /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Position */
#define MCLK_APBDMASK_ADC0_Msk (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos) /**< (MCLK_APBDMASK) ADC0 APB Clock Enable Mask */
#define MCLK_APBDMASK_ADC0(value) (MCLK_APBDMASK_ADC0_Msk & ((value) << MCLK_APBDMASK_ADC0_Pos))
#define MCLK_APBDMASK_ADC1_Pos _U_(8) /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Position */
#define MCLK_APBDMASK_ADC1_Msk (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos) /**< (MCLK_APBDMASK) ADC1 APB Clock Enable Mask */
#define MCLK_APBDMASK_ADC1(value) (MCLK_APBDMASK_ADC1_Msk & ((value) << MCLK_APBDMASK_ADC1_Pos))
#define MCLK_APBDMASK_DAC_Pos _U_(9) /**< (MCLK_APBDMASK) DAC APB Clock Enable Position */
#define MCLK_APBDMASK_DAC_Msk (_U_(0x1) << MCLK_APBDMASK_DAC_Pos) /**< (MCLK_APBDMASK) DAC APB Clock Enable Mask */
#define MCLK_APBDMASK_DAC(value) (MCLK_APBDMASK_DAC_Msk & ((value) << MCLK_APBDMASK_DAC_Pos))
#define MCLK_APBDMASK_I2S_Pos _U_(10) /**< (MCLK_APBDMASK) I2S APB Clock Enable Position */
#define MCLK_APBDMASK_I2S_Msk (_U_(0x1) << MCLK_APBDMASK_I2S_Pos) /**< (MCLK_APBDMASK) I2S APB Clock Enable Mask */
#define MCLK_APBDMASK_I2S(value) (MCLK_APBDMASK_I2S_Msk & ((value) << MCLK_APBDMASK_I2S_Pos))
#define MCLK_APBDMASK_PCC_Pos _U_(11) /**< (MCLK_APBDMASK) PCC APB Clock Enable Position */
#define MCLK_APBDMASK_PCC_Msk (_U_(0x1) << MCLK_APBDMASK_PCC_Pos) /**< (MCLK_APBDMASK) PCC APB Clock Enable Mask */
#define MCLK_APBDMASK_PCC(value) (MCLK_APBDMASK_PCC_Msk & ((value) << MCLK_APBDMASK_PCC_Pos))
#define MCLK_APBDMASK_Msk _U_(0x00000FFF) /**< (MCLK_APBDMASK) Register Mask */
#define MCLK_APBDMASK_SERCOM_Pos _U_(0) /**< (MCLK_APBDMASK Position) SERCOM4 APB Clock Enable */
#define MCLK_APBDMASK_SERCOM_Msk (_U_(0xF) << MCLK_APBDMASK_SERCOM_Pos) /**< (MCLK_APBDMASK Mask) SERCOM */
#define MCLK_APBDMASK_SERCOM(value) (MCLK_APBDMASK_SERCOM_Msk & ((value) << MCLK_APBDMASK_SERCOM_Pos))
#define MCLK_APBDMASK_TCC_Pos _U_(4) /**< (MCLK_APBDMASK Position) TCC4 APB Clock Enable */
#define MCLK_APBDMASK_TCC_Msk (_U_(0x1) << MCLK_APBDMASK_TCC_Pos) /**< (MCLK_APBDMASK Mask) TCC */
#define MCLK_APBDMASK_TCC(value) (MCLK_APBDMASK_TCC_Msk & ((value) << MCLK_APBDMASK_TCC_Pos))
#define MCLK_APBDMASK_TC_Pos _U_(5) /**< (MCLK_APBDMASK Position) TC6 APB Clock Enable */
#define MCLK_APBDMASK_TC_Msk (_U_(0x3) << MCLK_APBDMASK_TC_Pos) /**< (MCLK_APBDMASK Mask) TC */
#define MCLK_APBDMASK_TC(value) (MCLK_APBDMASK_TC_Msk & ((value) << MCLK_APBDMASK_TC_Pos))
#define MCLK_APBDMASK_ADC_Pos _U_(7) /**< (MCLK_APBDMASK Position) ADCx APB Clock Enable */
#define MCLK_APBDMASK_ADC_Msk (_U_(0x3) << MCLK_APBDMASK_ADC_Pos) /**< (MCLK_APBDMASK Mask) ADC */
#define MCLK_APBDMASK_ADC(value) (MCLK_APBDMASK_ADC_Msk & ((value) << MCLK_APBDMASK_ADC_Pos))
/** \brief MCLK register offsets definitions */
#define MCLK_INTENCLR_REG_OFST (0x01) /**< (MCLK_INTENCLR) Interrupt Enable Clear Offset */
#define MCLK_INTENSET_REG_OFST (0x02) /**< (MCLK_INTENSET) Interrupt Enable Set Offset */
#define MCLK_INTFLAG_REG_OFST (0x03) /**< (MCLK_INTFLAG) Interrupt Flag Status and Clear Offset */
#define MCLK_HSDIV_REG_OFST (0x04) /**< (MCLK_HSDIV) HS Clock Division Offset */
#define MCLK_CPUDIV_REG_OFST (0x05) /**< (MCLK_CPUDIV) CPU Clock Division Offset */
#define MCLK_AHBMASK_REG_OFST (0x10) /**< (MCLK_AHBMASK) AHB Mask Offset */
#define MCLK_APBAMASK_REG_OFST (0x14) /**< (MCLK_APBAMASK) APBA Mask Offset */
#define MCLK_APBBMASK_REG_OFST (0x18) /**< (MCLK_APBBMASK) APBB Mask Offset */
#define MCLK_APBCMASK_REG_OFST (0x1C) /**< (MCLK_APBCMASK) APBC Mask Offset */
#define MCLK_APBDMASK_REG_OFST (0x20) /**< (MCLK_APBDMASK) APBD Mask Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief MCLK register API structure */
typedef struct
{ /* Main Clock */
__I uint8_t Reserved1[0x01];
__IO uint8_t MCLK_INTENCLR; /**< Offset: 0x01 (R/W 8) Interrupt Enable Clear */
__IO uint8_t MCLK_INTENSET; /**< Offset: 0x02 (R/W 8) Interrupt Enable Set */
__IO uint8_t MCLK_INTFLAG; /**< Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t MCLK_HSDIV; /**< Offset: 0x04 (R/ 8) HS Clock Division */
__IO uint8_t MCLK_CPUDIV; /**< Offset: 0x05 (R/W 8) CPU Clock Division */
__I uint8_t Reserved2[0x0A];
__IO uint32_t MCLK_AHBMASK; /**< Offset: 0x10 (R/W 32) AHB Mask */
__IO uint32_t MCLK_APBAMASK; /**< Offset: 0x14 (R/W 32) APBA Mask */
__IO uint32_t MCLK_APBBMASK; /**< Offset: 0x18 (R/W 32) APBB Mask */
__IO uint32_t MCLK_APBCMASK; /**< Offset: 0x1C (R/W 32) APBC Mask */
__IO uint32_t MCLK_APBDMASK; /**< Offset: 0x20 (R/W 32) APBD Mask */
} mclk_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_MCLK_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/nvmctrl.h
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/**
* \brief Component description for NVMCTRL
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_NVMCTRL_COMPONENT_H_
#define _SAMD51_NVMCTRL_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR NVMCTRL */
/* ************************************************************************** */
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#define NVMCTRL_CTRLA_RESETVALUE _U_(0x04) /**< (NVMCTRL_CTRLA) Control A Reset Value */
#define NVMCTRL_CTRLA_AUTOWS_Pos _U_(2) /**< (NVMCTRL_CTRLA) Auto Wait State Enable Position */
#define NVMCTRL_CTRLA_AUTOWS_Msk (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos) /**< (NVMCTRL_CTRLA) Auto Wait State Enable Mask */
#define NVMCTRL_CTRLA_AUTOWS(value) (NVMCTRL_CTRLA_AUTOWS_Msk & ((value) << NVMCTRL_CTRLA_AUTOWS_Pos))
#define NVMCTRL_CTRLA_SUSPEN_Pos _U_(3) /**< (NVMCTRL_CTRLA) Suspend Enable Position */
#define NVMCTRL_CTRLA_SUSPEN_Msk (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos) /**< (NVMCTRL_CTRLA) Suspend Enable Mask */
#define NVMCTRL_CTRLA_SUSPEN(value) (NVMCTRL_CTRLA_SUSPEN_Msk & ((value) << NVMCTRL_CTRLA_SUSPEN_Pos))
#define NVMCTRL_CTRLA_WMODE_Pos _U_(4) /**< (NVMCTRL_CTRLA) Write Mode Position */
#define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos) /**< (NVMCTRL_CTRLA) Write Mode Mask */
#define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
#define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0) /**< (NVMCTRL_CTRLA) Manual Write */
#define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1) /**< (NVMCTRL_CTRLA) Automatic Double Word Write */
#define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2) /**< (NVMCTRL_CTRLA) Automatic Quad Word */
#define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3) /**< (NVMCTRL_CTRLA) Automatic Page Write */
#define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos) /**< (NVMCTRL_CTRLA) Manual Write Position */
#define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos) /**< (NVMCTRL_CTRLA) Automatic Double Word Write Position */
#define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos) /**< (NVMCTRL_CTRLA) Automatic Quad Word Position */
#define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos) /**< (NVMCTRL_CTRLA) Automatic Page Write Position */
#define NVMCTRL_CTRLA_PRM_Pos _U_(6) /**< (NVMCTRL_CTRLA) Power Reduction Mode during Sleep Position */
#define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos) /**< (NVMCTRL_CTRLA) Power Reduction Mode during Sleep Mask */
#define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
#define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0) /**< (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1) /**< (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. */
#define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3) /**< (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) /**< (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. Position */
#define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos) /**< (NVMCTRL_CTRLA) NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. Position */
#define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos) /**< (NVMCTRL_CTRLA) NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. Position */
#define NVMCTRL_CTRLA_RWS_Pos _U_(8) /**< (NVMCTRL_CTRLA) NVM Read Wait States Position */
#define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos) /**< (NVMCTRL_CTRLA) NVM Read Wait States Mask */
#define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
#define NVMCTRL_CTRLA_AHBNS0_Pos _U_(12) /**< (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated Position */
#define NVMCTRL_CTRLA_AHBNS0_Msk (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos) /**< (NVMCTRL_CTRLA) Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated Mask */
#define NVMCTRL_CTRLA_AHBNS0(value) (NVMCTRL_CTRLA_AHBNS0_Msk & ((value) << NVMCTRL_CTRLA_AHBNS0_Pos))
#define NVMCTRL_CTRLA_AHBNS1_Pos _U_(13) /**< (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated Position */
#define NVMCTRL_CTRLA_AHBNS1_Msk (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos) /**< (NVMCTRL_CTRLA) Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated Mask */
#define NVMCTRL_CTRLA_AHBNS1(value) (NVMCTRL_CTRLA_AHBNS1_Msk & ((value) << NVMCTRL_CTRLA_AHBNS1_Pos))
#define NVMCTRL_CTRLA_CACHEDIS0_Pos _U_(14) /**< (NVMCTRL_CTRLA) AHB0 Cache Disable Position */
#define NVMCTRL_CTRLA_CACHEDIS0_Msk (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos) /**< (NVMCTRL_CTRLA) AHB0 Cache Disable Mask */
#define NVMCTRL_CTRLA_CACHEDIS0(value) (NVMCTRL_CTRLA_CACHEDIS0_Msk & ((value) << NVMCTRL_CTRLA_CACHEDIS0_Pos))
#define NVMCTRL_CTRLA_CACHEDIS1_Pos _U_(15) /**< (NVMCTRL_CTRLA) AHB1 Cache Disable Position */
#define NVMCTRL_CTRLA_CACHEDIS1_Msk (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos) /**< (NVMCTRL_CTRLA) AHB1 Cache Disable Mask */
#define NVMCTRL_CTRLA_CACHEDIS1(value) (NVMCTRL_CTRLA_CACHEDIS1_Msk & ((value) << NVMCTRL_CTRLA_CACHEDIS1_Pos))
#define NVMCTRL_CTRLA_Msk _U_(0xFFFC) /**< (NVMCTRL_CTRLA) Register Mask */
#define NVMCTRL_CTRLA_AHBNS_Pos _U_(12) /**< (NVMCTRL_CTRLA Position) Force AHBx access to NONSEQ, burst transfers are continuously rearbitrated */
#define NVMCTRL_CTRLA_AHBNS_Msk (_U_(0x3) << NVMCTRL_CTRLA_AHBNS_Pos) /**< (NVMCTRL_CTRLA Mask) AHBNS */
#define NVMCTRL_CTRLA_AHBNS(value) (NVMCTRL_CTRLA_AHBNS_Msk & ((value) << NVMCTRL_CTRLA_AHBNS_Pos))
#define NVMCTRL_CTRLA_CACHEDIS_Pos _U_(14) /**< (NVMCTRL_CTRLA Position) AHBx Cache Disable */
#define NVMCTRL_CTRLA_CACHEDIS_Msk (_U_(0x3) << NVMCTRL_CTRLA_CACHEDIS_Pos) /**< (NVMCTRL_CTRLA Mask) CACHEDIS */
#define NVMCTRL_CTRLA_CACHEDIS(value) (NVMCTRL_CTRLA_CACHEDIS_Msk & ((value) << NVMCTRL_CTRLA_CACHEDIS_Pos))
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
#define NVMCTRL_CTRLB_RESETVALUE _U_(0x00) /**< (NVMCTRL_CTRLB) Control B Reset Value */
#define NVMCTRL_CTRLB_CMD_Pos _U_(0) /**< (NVMCTRL_CTRLB) Command Position */
#define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Command Mask */
#define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
#define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0) /**< (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. */
#define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1) /**< (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page */
#define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3) /**< (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page */
#define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4) /**< (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. */
#define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10) /**< (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers */
#define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11) /**< (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12) /**< (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13) /**< (NVMCTRL_CTRLB) Sets the power reduction mode. */
#define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14) /**< (NVMCTRL_CTRLB) Clears the power reduction mode. */
#define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15) /**< (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. */
#define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16) /**< (NVMCTRL_CTRLB) Set Security Bit */
#define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17) /**< (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK */
#define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18) /**< (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available */
#define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19) /**< (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available */
#define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A) /**< (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence */
#define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B) /**< (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded */
#define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30) /**< (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 */
#define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31) /**< (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 */
#define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32) /**< (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm */
#define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33) /**< (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode */
#define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34) /**< (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean */
#define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35) /**< (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data */
#define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36) /**< (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) */
#define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37) /**< (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) */
#define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Erase Page - Only supported in the USER and AUX pages. Position */
#define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Erase Block - Erases the block addressed by the ADDR register, not supported in the user page Position */
#define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page Position */
#define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. Position */
#define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers Position */
#define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Lock Region - Locks the region containing the address location in the ADDR register. Position */
#define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Unlock Region - Unlocks the region containing the address location in the ADDR register. Position */
#define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Sets the power reduction mode. Position */
#define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Clears the power reduction mode. Position */
#define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Page Buffer Clear - Clears the page buffer. Position */
#define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Set Security Bit Position */
#define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK Position */
#define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Chip Erase Lock - DSU.CE command is not available Position */
#define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Chip Erase Unlock - DSU.CE command is available Position */
#define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence Position */
#define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Clears STATUS.BPDIS, Boot loader protection is not discarded Position */
#define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 0, deactivate Sector 1 Position */
#define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Activate SmartEEPROM Sector 1, deactivate Sector 0 Position */
#define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Starts SmartEEPROM sector reallocation algorithm Position */
#define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Flush SMEE data when in buffered mode Position */
#define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Lock access to SmartEEPROM data from any mean Position */
#define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Unlock access to SmartEEPROM data Position */
#define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Lock access to the SmartEEPROM Register Address Space (above 64KB) Position */
#define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos) /**< (NVMCTRL_CTRLB) Unlock access to the SmartEEPROM Register Address Space (above 64KB) Position */
#define NVMCTRL_CTRLB_CMDEX_Pos _U_(8) /**< (NVMCTRL_CTRLB) Command Execution Position */
#define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos) /**< (NVMCTRL_CTRLB) Command Execution Mask */
#define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
#define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5) /**< (NVMCTRL_CTRLB) Execution Key */
#define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos) /**< (NVMCTRL_CTRLB) Execution Key Position */
#define NVMCTRL_CTRLB_Msk _U_(0xFF7F) /**< (NVMCTRL_CTRLB) Register Mask */
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) ( R/ 32) NVM Parameter -------- */
#define NVMCTRL_PARAM_RESETVALUE _U_(0x60000) /**< (NVMCTRL_PARAM) NVM Parameter Reset Value */
#define NVMCTRL_PARAM_NVMP_Pos _U_(0) /**< (NVMCTRL_PARAM) NVM Pages Position */
#define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) /**< (NVMCTRL_PARAM) NVM Pages Mask */
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
#define NVMCTRL_PARAM_PSZ_Pos _U_(16) /**< (NVMCTRL_PARAM) Page Size Position */
#define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) Page Size Mask */
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
#define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< (NVMCTRL_PARAM) 8 bytes */
#define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< (NVMCTRL_PARAM) 16 bytes */
#define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< (NVMCTRL_PARAM) 32 bytes */
#define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< (NVMCTRL_PARAM) 64 bytes */
#define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< (NVMCTRL_PARAM) 128 bytes */
#define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< (NVMCTRL_PARAM) 256 bytes */
#define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< (NVMCTRL_PARAM) 512 bytes */
#define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< (NVMCTRL_PARAM) 1024 bytes */
#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 8 bytes Position */
#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 16 bytes Position */
#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 32 bytes Position */
#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 64 bytes Position */
#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 128 bytes Position */
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 256 bytes Position */
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 512 bytes Position */
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) /**< (NVMCTRL_PARAM) 1024 bytes Position */
#define NVMCTRL_PARAM_SEE_Pos _U_(31) /**< (NVMCTRL_PARAM) SmartEEPROM Supported Position */
#define NVMCTRL_PARAM_SEE_Msk (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) SmartEEPROM Supported Mask */
#define NVMCTRL_PARAM_SEE(value) (NVMCTRL_PARAM_SEE_Msk & ((value) << NVMCTRL_PARAM_SEE_Pos))
#define NVMCTRL_PARAM_SEE_A_Val _U_(0xA) /**< (NVMCTRL_PARAM) 163840 bytes */
#define NVMCTRL_PARAM_SEE_9_Val _U_(0x9) /**< (NVMCTRL_PARAM) 147456 bytes */
#define NVMCTRL_PARAM_SEE_8_Val _U_(0x8) /**< (NVMCTRL_PARAM) 131072 bytes */
#define NVMCTRL_PARAM_SEE_7_Val _U_(0x7) /**< (NVMCTRL_PARAM) 114688 bytes */
#define NVMCTRL_PARAM_SEE_6_Val _U_(0x6) /**< (NVMCTRL_PARAM) 98304 bytes */
#define NVMCTRL_PARAM_SEE_5_Val _U_(0x5) /**< (NVMCTRL_PARAM) 81920 bytes */
#define NVMCTRL_PARAM_SEE_4_Val _U_(0x4) /**< (NVMCTRL_PARAM) 65536 bytes */
#define NVMCTRL_PARAM_SEE_3_Val _U_(0x3) /**< (NVMCTRL_PARAM) 49152 bytes */
#define NVMCTRL_PARAM_SEE_2_Val _U_(0x2) /**< (NVMCTRL_PARAM) 32768 bytes */
#define NVMCTRL_PARAM_SEE_1_Val _U_(0x1) /**< (NVMCTRL_PARAM) 16384 bytes */
#define NVMCTRL_PARAM_SEE_0_Val _U_(0x0) /**< (NVMCTRL_PARAM) 0 bytes */
#define NVMCTRL_PARAM_SEE_A (NVMCTRL_PARAM_SEE_A_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 163840 bytes Position */
#define NVMCTRL_PARAM_SEE_9 (NVMCTRL_PARAM_SEE_9_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 147456 bytes Position */
#define NVMCTRL_PARAM_SEE_8 (NVMCTRL_PARAM_SEE_8_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 131072 bytes Position */
#define NVMCTRL_PARAM_SEE_7 (NVMCTRL_PARAM_SEE_7_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 114688 bytes Position */
#define NVMCTRL_PARAM_SEE_6 (NVMCTRL_PARAM_SEE_6_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 98304 bytes Position */
#define NVMCTRL_PARAM_SEE_5 (NVMCTRL_PARAM_SEE_5_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 81920 bytes Position */
#define NVMCTRL_PARAM_SEE_4 (NVMCTRL_PARAM_SEE_4_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 65536 bytes Position */
#define NVMCTRL_PARAM_SEE_3 (NVMCTRL_PARAM_SEE_3_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 49152 bytes Position */
#define NVMCTRL_PARAM_SEE_2 (NVMCTRL_PARAM_SEE_2_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 32768 bytes Position */
#define NVMCTRL_PARAM_SEE_1 (NVMCTRL_PARAM_SEE_1_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 16384 bytes Position */
#define NVMCTRL_PARAM_SEE_0 (NVMCTRL_PARAM_SEE_0_Val << NVMCTRL_PARAM_SEE_Pos) /**< (NVMCTRL_PARAM) 0 bytes Position */
#define NVMCTRL_PARAM_Msk _U_(0x8007FFFF) /**< (NVMCTRL_PARAM) Register Mask */
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< (NVMCTRL_INTENCLR) Interrupt Enable Clear Reset Value */
#define NVMCTRL_INTENCLR_DONE_Pos _U_(0) /**< (NVMCTRL_INTENCLR) Command Done Interrupt Clear Position */
#define NVMCTRL_INTENCLR_DONE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos) /**< (NVMCTRL_INTENCLR) Command Done Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_DONE(value) (NVMCTRL_INTENCLR_DONE_Msk & ((value) << NVMCTRL_INTENCLR_DONE_Pos))
#define NVMCTRL_INTENCLR_ADDRE_Pos _U_(1) /**< (NVMCTRL_INTENCLR) Address Error Position */
#define NVMCTRL_INTENCLR_ADDRE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos) /**< (NVMCTRL_INTENCLR) Address Error Mask */
#define NVMCTRL_INTENCLR_ADDRE(value) (NVMCTRL_INTENCLR_ADDRE_Msk & ((value) << NVMCTRL_INTENCLR_ADDRE_Pos))
#define NVMCTRL_INTENCLR_PROGE_Pos _U_(2) /**< (NVMCTRL_INTENCLR) Programming Error Interrupt Clear Position */
#define NVMCTRL_INTENCLR_PROGE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos) /**< (NVMCTRL_INTENCLR) Programming Error Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_PROGE(value) (NVMCTRL_INTENCLR_PROGE_Msk & ((value) << NVMCTRL_INTENCLR_PROGE_Pos))
#define NVMCTRL_INTENCLR_LOCKE_Pos _U_(3) /**< (NVMCTRL_INTENCLR) Lock Error Interrupt Clear Position */
#define NVMCTRL_INTENCLR_LOCKE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos) /**< (NVMCTRL_INTENCLR) Lock Error Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_LOCKE(value) (NVMCTRL_INTENCLR_LOCKE_Msk & ((value) << NVMCTRL_INTENCLR_LOCKE_Pos))
#define NVMCTRL_INTENCLR_ECCSE_Pos _U_(4) /**< (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear Position */
#define NVMCTRL_INTENCLR_ECCSE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos) /**< (NVMCTRL_INTENCLR) ECC Single Error Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_ECCSE(value) (NVMCTRL_INTENCLR_ECCSE_Msk & ((value) << NVMCTRL_INTENCLR_ECCSE_Pos))
#define NVMCTRL_INTENCLR_ECCDE_Pos _U_(5) /**< (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear Position */
#define NVMCTRL_INTENCLR_ECCDE_Msk (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos) /**< (NVMCTRL_INTENCLR) ECC Dual Error Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_ECCDE(value) (NVMCTRL_INTENCLR_ECCDE_Msk & ((value) << NVMCTRL_INTENCLR_ECCDE_Pos))
#define NVMCTRL_INTENCLR_NVME_Pos _U_(6) /**< (NVMCTRL_INTENCLR) NVM Error Interrupt Clear Position */
#define NVMCTRL_INTENCLR_NVME_Msk (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos) /**< (NVMCTRL_INTENCLR) NVM Error Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_NVME(value) (NVMCTRL_INTENCLR_NVME_Msk & ((value) << NVMCTRL_INTENCLR_NVME_Pos))
#define NVMCTRL_INTENCLR_SUSP_Pos _U_(7) /**< (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear Position */
#define NVMCTRL_INTENCLR_SUSP_Msk (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos) /**< (NVMCTRL_INTENCLR) Suspended Write Or Erase Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_SUSP(value) (NVMCTRL_INTENCLR_SUSP_Msk & ((value) << NVMCTRL_INTENCLR_SUSP_Pos))
#define NVMCTRL_INTENCLR_SEESFULL_Pos _U_(8) /**< (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear Position */
#define NVMCTRL_INTENCLR_SEESFULL_Msk (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos) /**< (NVMCTRL_INTENCLR) Active SEES Full Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_SEESFULL(value) (NVMCTRL_INTENCLR_SEESFULL_Msk & ((value) << NVMCTRL_INTENCLR_SEESFULL_Pos))
#define NVMCTRL_INTENCLR_SEESOVF_Pos _U_(9) /**< (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear Position */
#define NVMCTRL_INTENCLR_SEESOVF_Msk (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos) /**< (NVMCTRL_INTENCLR) Active SEES Overflow Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_SEESOVF(value) (NVMCTRL_INTENCLR_SEESOVF_Msk & ((value) << NVMCTRL_INTENCLR_SEESOVF_Pos))
#define NVMCTRL_INTENCLR_SEEWRC_Pos _U_(10) /**< (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear Position */
#define NVMCTRL_INTENCLR_SEEWRC_Msk (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos) /**< (NVMCTRL_INTENCLR) SEE Write Completed Interrupt Clear Mask */
#define NVMCTRL_INTENCLR_SEEWRC(value) (NVMCTRL_INTENCLR_SEEWRC_Msk & ((value) << NVMCTRL_INTENCLR_SEEWRC_Pos))
#define NVMCTRL_INTENCLR_Msk _U_(0x07FF) /**< (NVMCTRL_INTENCLR) Register Mask */
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
#define NVMCTRL_INTENSET_RESETVALUE _U_(0x00) /**< (NVMCTRL_INTENSET) Interrupt Enable Set Reset Value */
#define NVMCTRL_INTENSET_DONE_Pos _U_(0) /**< (NVMCTRL_INTENSET) Command Done Interrupt Enable Position */
#define NVMCTRL_INTENSET_DONE_Msk (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos) /**< (NVMCTRL_INTENSET) Command Done Interrupt Enable Mask */
#define NVMCTRL_INTENSET_DONE(value) (NVMCTRL_INTENSET_DONE_Msk & ((value) << NVMCTRL_INTENSET_DONE_Pos))
#define NVMCTRL_INTENSET_ADDRE_Pos _U_(1) /**< (NVMCTRL_INTENSET) Address Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_ADDRE_Msk (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos) /**< (NVMCTRL_INTENSET) Address Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_ADDRE(value) (NVMCTRL_INTENSET_ADDRE_Msk & ((value) << NVMCTRL_INTENSET_ADDRE_Pos))
#define NVMCTRL_INTENSET_PROGE_Pos _U_(2) /**< (NVMCTRL_INTENSET) Programming Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_PROGE_Msk (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos) /**< (NVMCTRL_INTENSET) Programming Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_PROGE(value) (NVMCTRL_INTENSET_PROGE_Msk & ((value) << NVMCTRL_INTENSET_PROGE_Pos))
#define NVMCTRL_INTENSET_LOCKE_Pos _U_(3) /**< (NVMCTRL_INTENSET) Lock Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_LOCKE_Msk (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos) /**< (NVMCTRL_INTENSET) Lock Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_LOCKE(value) (NVMCTRL_INTENSET_LOCKE_Msk & ((value) << NVMCTRL_INTENSET_LOCKE_Pos))
#define NVMCTRL_INTENSET_ECCSE_Pos _U_(4) /**< (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_ECCSE_Msk (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos) /**< (NVMCTRL_INTENSET) ECC Single Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_ECCSE(value) (NVMCTRL_INTENSET_ECCSE_Msk & ((value) << NVMCTRL_INTENSET_ECCSE_Pos))
#define NVMCTRL_INTENSET_ECCDE_Pos _U_(5) /**< (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_ECCDE_Msk (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos) /**< (NVMCTRL_INTENSET) ECC Dual Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_ECCDE(value) (NVMCTRL_INTENSET_ECCDE_Msk & ((value) << NVMCTRL_INTENSET_ECCDE_Pos))
#define NVMCTRL_INTENSET_NVME_Pos _U_(6) /**< (NVMCTRL_INTENSET) NVM Error Interrupt Enable Position */
#define NVMCTRL_INTENSET_NVME_Msk (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos) /**< (NVMCTRL_INTENSET) NVM Error Interrupt Enable Mask */
#define NVMCTRL_INTENSET_NVME(value) (NVMCTRL_INTENSET_NVME_Msk & ((value) << NVMCTRL_INTENSET_NVME_Pos))
#define NVMCTRL_INTENSET_SUSP_Pos _U_(7) /**< (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable Position */
#define NVMCTRL_INTENSET_SUSP_Msk (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos) /**< (NVMCTRL_INTENSET) Suspended Write Or Erase Interrupt Enable Mask */
#define NVMCTRL_INTENSET_SUSP(value) (NVMCTRL_INTENSET_SUSP_Msk & ((value) << NVMCTRL_INTENSET_SUSP_Pos))
#define NVMCTRL_INTENSET_SEESFULL_Pos _U_(8) /**< (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable Position */
#define NVMCTRL_INTENSET_SEESFULL_Msk (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos) /**< (NVMCTRL_INTENSET) Active SEES Full Interrupt Enable Mask */
#define NVMCTRL_INTENSET_SEESFULL(value) (NVMCTRL_INTENSET_SEESFULL_Msk & ((value) << NVMCTRL_INTENSET_SEESFULL_Pos))
#define NVMCTRL_INTENSET_SEESOVF_Pos _U_(9) /**< (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable Position */
#define NVMCTRL_INTENSET_SEESOVF_Msk (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos) /**< (NVMCTRL_INTENSET) Active SEES Overflow Interrupt Enable Mask */
#define NVMCTRL_INTENSET_SEESOVF(value) (NVMCTRL_INTENSET_SEESOVF_Msk & ((value) << NVMCTRL_INTENSET_SEESOVF_Pos))
#define NVMCTRL_INTENSET_SEEWRC_Pos _U_(10) /**< (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable Position */
#define NVMCTRL_INTENSET_SEEWRC_Msk (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos) /**< (NVMCTRL_INTENSET) SEE Write Completed Interrupt Enable Mask */
#define NVMCTRL_INTENSET_SEEWRC(value) (NVMCTRL_INTENSET_SEEWRC_Msk & ((value) << NVMCTRL_INTENSET_SEEWRC_Pos))
#define NVMCTRL_INTENSET_Msk _U_(0x07FF) /**< (NVMCTRL_INTENSET) Register Mask */
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
#define NVMCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< (NVMCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define NVMCTRL_INTFLAG_DONE_Pos _U_(0) /**< (NVMCTRL_INTFLAG) Command Done Position */
#define NVMCTRL_INTFLAG_DONE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos) /**< (NVMCTRL_INTFLAG) Command Done Mask */
#define NVMCTRL_INTFLAG_DONE(value) (NVMCTRL_INTFLAG_DONE_Msk & ((value) << NVMCTRL_INTFLAG_DONE_Pos))
#define NVMCTRL_INTFLAG_ADDRE_Pos _U_(1) /**< (NVMCTRL_INTFLAG) Address Error Position */
#define NVMCTRL_INTFLAG_ADDRE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos) /**< (NVMCTRL_INTFLAG) Address Error Mask */
#define NVMCTRL_INTFLAG_ADDRE(value) (NVMCTRL_INTFLAG_ADDRE_Msk & ((value) << NVMCTRL_INTFLAG_ADDRE_Pos))
#define NVMCTRL_INTFLAG_PROGE_Pos _U_(2) /**< (NVMCTRL_INTFLAG) Programming Error Position */
#define NVMCTRL_INTFLAG_PROGE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos) /**< (NVMCTRL_INTFLAG) Programming Error Mask */
#define NVMCTRL_INTFLAG_PROGE(value) (NVMCTRL_INTFLAG_PROGE_Msk & ((value) << NVMCTRL_INTFLAG_PROGE_Pos))
#define NVMCTRL_INTFLAG_LOCKE_Pos _U_(3) /**< (NVMCTRL_INTFLAG) Lock Error Position */
#define NVMCTRL_INTFLAG_LOCKE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos) /**< (NVMCTRL_INTFLAG) Lock Error Mask */
#define NVMCTRL_INTFLAG_LOCKE(value) (NVMCTRL_INTFLAG_LOCKE_Msk & ((value) << NVMCTRL_INTFLAG_LOCKE_Pos))
#define NVMCTRL_INTFLAG_ECCSE_Pos _U_(4) /**< (NVMCTRL_INTFLAG) ECC Single Error Position */
#define NVMCTRL_INTFLAG_ECCSE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos) /**< (NVMCTRL_INTFLAG) ECC Single Error Mask */
#define NVMCTRL_INTFLAG_ECCSE(value) (NVMCTRL_INTFLAG_ECCSE_Msk & ((value) << NVMCTRL_INTFLAG_ECCSE_Pos))
#define NVMCTRL_INTFLAG_ECCDE_Pos _U_(5) /**< (NVMCTRL_INTFLAG) ECC Dual Error Position */
#define NVMCTRL_INTFLAG_ECCDE_Msk (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos) /**< (NVMCTRL_INTFLAG) ECC Dual Error Mask */
#define NVMCTRL_INTFLAG_ECCDE(value) (NVMCTRL_INTFLAG_ECCDE_Msk & ((value) << NVMCTRL_INTFLAG_ECCDE_Pos))
#define NVMCTRL_INTFLAG_NVME_Pos _U_(6) /**< (NVMCTRL_INTFLAG) NVM Error Position */
#define NVMCTRL_INTFLAG_NVME_Msk (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos) /**< (NVMCTRL_INTFLAG) NVM Error Mask */
#define NVMCTRL_INTFLAG_NVME(value) (NVMCTRL_INTFLAG_NVME_Msk & ((value) << NVMCTRL_INTFLAG_NVME_Pos))
#define NVMCTRL_INTFLAG_SUSP_Pos _U_(7) /**< (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation Position */
#define NVMCTRL_INTFLAG_SUSP_Msk (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos) /**< (NVMCTRL_INTFLAG) Suspended Write Or Erase Operation Mask */
#define NVMCTRL_INTFLAG_SUSP(value) (NVMCTRL_INTFLAG_SUSP_Msk & ((value) << NVMCTRL_INTFLAG_SUSP_Pos))
#define NVMCTRL_INTFLAG_SEESFULL_Pos _U_(8) /**< (NVMCTRL_INTFLAG) Active SEES Full Position */
#define NVMCTRL_INTFLAG_SEESFULL_Msk (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos) /**< (NVMCTRL_INTFLAG) Active SEES Full Mask */
#define NVMCTRL_INTFLAG_SEESFULL(value) (NVMCTRL_INTFLAG_SEESFULL_Msk & ((value) << NVMCTRL_INTFLAG_SEESFULL_Pos))
#define NVMCTRL_INTFLAG_SEESOVF_Pos _U_(9) /**< (NVMCTRL_INTFLAG) Active SEES Overflow Position */
#define NVMCTRL_INTFLAG_SEESOVF_Msk (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos) /**< (NVMCTRL_INTFLAG) Active SEES Overflow Mask */
#define NVMCTRL_INTFLAG_SEESOVF(value) (NVMCTRL_INTFLAG_SEESOVF_Msk & ((value) << NVMCTRL_INTFLAG_SEESOVF_Pos))
#define NVMCTRL_INTFLAG_SEEWRC_Pos _U_(10) /**< (NVMCTRL_INTFLAG) SEE Write Completed Position */
#define NVMCTRL_INTFLAG_SEEWRC_Msk (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos) /**< (NVMCTRL_INTFLAG) SEE Write Completed Mask */
#define NVMCTRL_INTFLAG_SEEWRC(value) (NVMCTRL_INTFLAG_SEEWRC_Msk & ((value) << NVMCTRL_INTFLAG_SEEWRC_Pos))
#define NVMCTRL_INTFLAG_Msk _U_(0x07FF) /**< (NVMCTRL_INTFLAG) Register Mask */
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) ( R/ 16) Status -------- */
#define NVMCTRL_STATUS_RESETVALUE _U_(0x00) /**< (NVMCTRL_STATUS) Status Reset Value */
#define NVMCTRL_STATUS_READY_Pos _U_(0) /**< (NVMCTRL_STATUS) Ready to accept a command Position */
#define NVMCTRL_STATUS_READY_Msk (_U_(0x1) << NVMCTRL_STATUS_READY_Pos) /**< (NVMCTRL_STATUS) Ready to accept a command Mask */
#define NVMCTRL_STATUS_READY(value) (NVMCTRL_STATUS_READY_Msk & ((value) << NVMCTRL_STATUS_READY_Pos))
#define NVMCTRL_STATUS_PRM_Pos _U_(1) /**< (NVMCTRL_STATUS) Power Reduction Mode Position */
#define NVMCTRL_STATUS_PRM_Msk (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos) /**< (NVMCTRL_STATUS) Power Reduction Mode Mask */
#define NVMCTRL_STATUS_PRM(value) (NVMCTRL_STATUS_PRM_Msk & ((value) << NVMCTRL_STATUS_PRM_Pos))
#define NVMCTRL_STATUS_LOAD_Pos _U_(2) /**< (NVMCTRL_STATUS) NVM Page Buffer Active Loading Position */
#define NVMCTRL_STATUS_LOAD_Msk (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos) /**< (NVMCTRL_STATUS) NVM Page Buffer Active Loading Mask */
#define NVMCTRL_STATUS_LOAD(value) (NVMCTRL_STATUS_LOAD_Msk & ((value) << NVMCTRL_STATUS_LOAD_Pos))
#define NVMCTRL_STATUS_SUSP_Pos _U_(3) /**< (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended Position */
#define NVMCTRL_STATUS_SUSP_Msk (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos) /**< (NVMCTRL_STATUS) NVM Write Or Erase Operation Is Suspended Mask */
#define NVMCTRL_STATUS_SUSP(value) (NVMCTRL_STATUS_SUSP_Msk & ((value) << NVMCTRL_STATUS_SUSP_Pos))
#define NVMCTRL_STATUS_AFIRST_Pos _U_(4) /**< (NVMCTRL_STATUS) BANKA First Position */
#define NVMCTRL_STATUS_AFIRST_Msk (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos) /**< (NVMCTRL_STATUS) BANKA First Mask */
#define NVMCTRL_STATUS_AFIRST(value) (NVMCTRL_STATUS_AFIRST_Msk & ((value) << NVMCTRL_STATUS_AFIRST_Pos))
#define NVMCTRL_STATUS_BPDIS_Pos _U_(5) /**< (NVMCTRL_STATUS) Boot Loader Protection Disable Position */
#define NVMCTRL_STATUS_BPDIS_Msk (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos) /**< (NVMCTRL_STATUS) Boot Loader Protection Disable Mask */
#define NVMCTRL_STATUS_BPDIS(value) (NVMCTRL_STATUS_BPDIS_Msk & ((value) << NVMCTRL_STATUS_BPDIS_Pos))
#define NVMCTRL_STATUS_BOOTPROT_Pos _U_(8) /**< (NVMCTRL_STATUS) Boot Loader Protection Size Position */
#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) Boot Loader Protection Size Mask */
#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
#define NVMCTRL_STATUS_BOOTPROT_0_Val _U_(0xF) /**< (NVMCTRL_STATUS) 0 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_8_Val _U_(0xE) /**< (NVMCTRL_STATUS) 8 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_16_Val _U_(0xD) /**< (NVMCTRL_STATUS) 16 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_24_Val _U_(0xC) /**< (NVMCTRL_STATUS) 24 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_32_Val _U_(0xB) /**< (NVMCTRL_STATUS) 32 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_40_Val _U_(0xA) /**< (NVMCTRL_STATUS) 40 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_48_Val _U_(0x9) /**< (NVMCTRL_STATUS) 48 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_56_Val _U_(0x8) /**< (NVMCTRL_STATUS) 56 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_64_Val _U_(0x7) /**< (NVMCTRL_STATUS) 64 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_72_Val _U_(0x6) /**< (NVMCTRL_STATUS) 72 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_80_Val _U_(0x5) /**< (NVMCTRL_STATUS) 80 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_88_Val _U_(0x4) /**< (NVMCTRL_STATUS) 88 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_96_Val _U_(0x3) /**< (NVMCTRL_STATUS) 96 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_104_Val _U_(0x2) /**< (NVMCTRL_STATUS) 104 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_112_Val _U_(0x1) /**< (NVMCTRL_STATUS) 112 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_120_Val _U_(0x0) /**< (NVMCTRL_STATUS) 120 kbytes */
#define NVMCTRL_STATUS_BOOTPROT_0 (NVMCTRL_STATUS_BOOTPROT_0_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 0 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_8 (NVMCTRL_STATUS_BOOTPROT_8_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 8 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_16 (NVMCTRL_STATUS_BOOTPROT_16_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 16 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_24 (NVMCTRL_STATUS_BOOTPROT_24_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 24 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_32 (NVMCTRL_STATUS_BOOTPROT_32_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 32 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_40 (NVMCTRL_STATUS_BOOTPROT_40_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 40 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_48 (NVMCTRL_STATUS_BOOTPROT_48_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 48 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_56 (NVMCTRL_STATUS_BOOTPROT_56_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 56 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_64 (NVMCTRL_STATUS_BOOTPROT_64_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 64 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_72 (NVMCTRL_STATUS_BOOTPROT_72_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 72 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_80 (NVMCTRL_STATUS_BOOTPROT_80_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 80 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_88 (NVMCTRL_STATUS_BOOTPROT_88_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 88 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_96 (NVMCTRL_STATUS_BOOTPROT_96_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 96 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_104 (NVMCTRL_STATUS_BOOTPROT_104_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 104 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_112 (NVMCTRL_STATUS_BOOTPROT_112_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 112 kbytes Position */
#define NVMCTRL_STATUS_BOOTPROT_120 (NVMCTRL_STATUS_BOOTPROT_120_Val << NVMCTRL_STATUS_BOOTPROT_Pos) /**< (NVMCTRL_STATUS) 120 kbytes Position */
#define NVMCTRL_STATUS_Msk _U_(0x0F3F) /**< (NVMCTRL_STATUS) Register Mask */
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
#define NVMCTRL_ADDR_RESETVALUE _U_(0x00) /**< (NVMCTRL_ADDR) Address Reset Value */
#define NVMCTRL_ADDR_ADDR_Pos _U_(0) /**< (NVMCTRL_ADDR) NVM Address Position */
#define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos) /**< (NVMCTRL_ADDR) NVM Address Mask */
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
#define NVMCTRL_ADDR_Msk _U_(0x00FFFFFF) /**< (NVMCTRL_ADDR) Register Mask */
/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) ( R/ 32) Lock Section -------- */
#define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00) /**< (NVMCTRL_RUNLOCK) Lock Section Reset Value */
#define NVMCTRL_RUNLOCK_RUNLOCK_Pos _U_(0) /**< (NVMCTRL_RUNLOCK) Region Un-Lock Bits Position */
#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos) /**< (NVMCTRL_RUNLOCK) Region Un-Lock Bits Mask */
#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
#define NVMCTRL_RUNLOCK_Msk _U_(0xFFFFFFFF) /**< (NVMCTRL_RUNLOCK) Register Mask */
/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) ( R/ 32) Page Buffer Load Data x -------- */
#define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF) /**< (NVMCTRL_PBLDATA) Page Buffer Load Data x Reset Value */
#define NVMCTRL_PBLDATA_DATA_Pos _U_(0) /**< (NVMCTRL_PBLDATA) Page Buffer Data Position */
#define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos) /**< (NVMCTRL_PBLDATA) Page Buffer Data Mask */
#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
#define NVMCTRL_PBLDATA_Msk _U_(0xFFFFFFFF) /**< (NVMCTRL_PBLDATA) Register Mask */
/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) ( R/ 32) ECC Error Status Register -------- */
#define NVMCTRL_ECCERR_RESETVALUE _U_(0x00) /**< (NVMCTRL_ECCERR) ECC Error Status Register Reset Value */
#define NVMCTRL_ECCERR_ADDR_Pos _U_(0) /**< (NVMCTRL_ECCERR) Error Address Position */
#define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos) /**< (NVMCTRL_ECCERR) Error Address Mask */
#define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
#define NVMCTRL_ECCERR_TYPEL_Pos _U_(28) /**< (NVMCTRL_ECCERR) Low Double-Word Error Type Position */
#define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos) /**< (NVMCTRL_ECCERR) Low Double-Word Error Type Mask */
#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
#define NVMCTRL_ECCERR_TYPEL_None_Val _U_(0x0) /**< (NVMCTRL_ECCERR) No Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEL_Single_Val _U_(0x1) /**< (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
#define NVMCTRL_ECCERR_TYPEL_Dual_Val _U_(0x2) /**< (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEL_None (NVMCTRL_ECCERR_TYPEL_None_Val << NVMCTRL_ECCERR_TYPEL_Pos) /**< (NVMCTRL_ECCERR) No Error Detected Since Last Read Position */
#define NVMCTRL_ECCERR_TYPEL_Single (NVMCTRL_ECCERR_TYPEL_Single_Val << NVMCTRL_ECCERR_TYPEL_Pos) /**< (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read Position */
#define NVMCTRL_ECCERR_TYPEL_Dual (NVMCTRL_ECCERR_TYPEL_Dual_Val << NVMCTRL_ECCERR_TYPEL_Pos) /**< (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read Position */
#define NVMCTRL_ECCERR_TYPEH_Pos _U_(30) /**< (NVMCTRL_ECCERR) High Double-Word Error Type Position */
#define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos) /**< (NVMCTRL_ECCERR) High Double-Word Error Type Mask */
#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
#define NVMCTRL_ECCERR_TYPEH_None_Val _U_(0x0) /**< (NVMCTRL_ECCERR) No Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEH_Single_Val _U_(0x1) /**< (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read */
#define NVMCTRL_ECCERR_TYPEH_Dual_Val _U_(0x2) /**< (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read */
#define NVMCTRL_ECCERR_TYPEH_None (NVMCTRL_ECCERR_TYPEH_None_Val << NVMCTRL_ECCERR_TYPEH_Pos) /**< (NVMCTRL_ECCERR) No Error Detected Since Last Read Position */
#define NVMCTRL_ECCERR_TYPEH_Single (NVMCTRL_ECCERR_TYPEH_Single_Val << NVMCTRL_ECCERR_TYPEH_Pos) /**< (NVMCTRL_ECCERR) At Least One Single Error Detected Since last Read Position */
#define NVMCTRL_ECCERR_TYPEH_Dual (NVMCTRL_ECCERR_TYPEH_Dual_Val << NVMCTRL_ECCERR_TYPEH_Pos) /**< (NVMCTRL_ECCERR) At Least One Dual Error Detected Since Last Read Position */
#define NVMCTRL_ECCERR_Msk _U_(0xF0FFFFFF) /**< (NVMCTRL_ECCERR) Register Mask */
/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */
#define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00) /**< (NVMCTRL_DBGCTRL) Debug Control Reset Value */
#define NVMCTRL_DBGCTRL_ECCDIS_Pos _U_(0) /**< (NVMCTRL_DBGCTRL) Debugger ECC Read Disable Position */
#define NVMCTRL_DBGCTRL_ECCDIS_Msk (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos) /**< (NVMCTRL_DBGCTRL) Debugger ECC Read Disable Mask */
#define NVMCTRL_DBGCTRL_ECCDIS(value) (NVMCTRL_DBGCTRL_ECCDIS_Msk & ((value) << NVMCTRL_DBGCTRL_ECCDIS_Pos))
#define NVMCTRL_DBGCTRL_ECCELOG_Pos _U_(1) /**< (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode Position */
#define NVMCTRL_DBGCTRL_ECCELOG_Msk (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos) /**< (NVMCTRL_DBGCTRL) Debugger ECC Error Tracking Mode Mask */
#define NVMCTRL_DBGCTRL_ECCELOG(value) (NVMCTRL_DBGCTRL_ECCELOG_Msk & ((value) << NVMCTRL_DBGCTRL_ECCELOG_Pos))
#define NVMCTRL_DBGCTRL_Msk _U_(0x03) /**< (NVMCTRL_DBGCTRL) Register Mask */
/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */
#define NVMCTRL_SEECFG_RESETVALUE _U_(0x00) /**< (NVMCTRL_SEECFG) SmartEEPROM Configuration Register Reset Value */
#define NVMCTRL_SEECFG_WMODE_Pos _U_(0) /**< (NVMCTRL_SEECFG) Write Mode Position */
#define NVMCTRL_SEECFG_WMODE_Msk (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos) /**< (NVMCTRL_SEECFG) Write Mode Mask */
#define NVMCTRL_SEECFG_WMODE(value) (NVMCTRL_SEECFG_WMODE_Msk & ((value) << NVMCTRL_SEECFG_WMODE_Pos))
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0) /**< (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer */
#define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1) /**< (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested */
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos) /**< (NVMCTRL_SEECFG) A NVM write command is issued after each write in the pagebuffer Position */
#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos) /**< (NVMCTRL_SEECFG) A NVM write command is issued when a write to a new page is requested Position */
#define NVMCTRL_SEECFG_APRDIS_Pos _U_(1) /**< (NVMCTRL_SEECFG) Automatic Page Reallocation Disable Position */
#define NVMCTRL_SEECFG_APRDIS_Msk (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos) /**< (NVMCTRL_SEECFG) Automatic Page Reallocation Disable Mask */
#define NVMCTRL_SEECFG_APRDIS(value) (NVMCTRL_SEECFG_APRDIS_Msk & ((value) << NVMCTRL_SEECFG_APRDIS_Pos))
#define NVMCTRL_SEECFG_Msk _U_(0x03) /**< (NVMCTRL_SEECFG) Register Mask */
/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) ( R/ 32) SmartEEPROM Status Register -------- */
#define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00) /**< (NVMCTRL_SEESTAT) SmartEEPROM Status Register Reset Value */
#define NVMCTRL_SEESTAT_ASEES_Pos _U_(0) /**< (NVMCTRL_SEESTAT) Active SmartEEPROM Sector Position */
#define NVMCTRL_SEESTAT_ASEES_Msk (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos) /**< (NVMCTRL_SEESTAT) Active SmartEEPROM Sector Mask */
#define NVMCTRL_SEESTAT_ASEES(value) (NVMCTRL_SEESTAT_ASEES_Msk & ((value) << NVMCTRL_SEESTAT_ASEES_Pos))
#define NVMCTRL_SEESTAT_LOAD_Pos _U_(1) /**< (NVMCTRL_SEESTAT) Page Buffer Loaded Position */
#define NVMCTRL_SEESTAT_LOAD_Msk (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos) /**< (NVMCTRL_SEESTAT) Page Buffer Loaded Mask */
#define NVMCTRL_SEESTAT_LOAD(value) (NVMCTRL_SEESTAT_LOAD_Msk & ((value) << NVMCTRL_SEESTAT_LOAD_Pos))
#define NVMCTRL_SEESTAT_BUSY_Pos _U_(2) /**< (NVMCTRL_SEESTAT) Busy Position */
#define NVMCTRL_SEESTAT_BUSY_Msk (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos) /**< (NVMCTRL_SEESTAT) Busy Mask */
#define NVMCTRL_SEESTAT_BUSY(value) (NVMCTRL_SEESTAT_BUSY_Msk & ((value) << NVMCTRL_SEESTAT_BUSY_Pos))
#define NVMCTRL_SEESTAT_LOCK_Pos _U_(3) /**< (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked Position */
#define NVMCTRL_SEESTAT_LOCK_Msk (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos) /**< (NVMCTRL_SEESTAT) SmartEEPROM Write Access Is Locked Mask */
#define NVMCTRL_SEESTAT_LOCK(value) (NVMCTRL_SEESTAT_LOCK_Msk & ((value) << NVMCTRL_SEESTAT_LOCK_Pos))
#define NVMCTRL_SEESTAT_RLOCK_Pos _U_(4) /**< (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked Position */
#define NVMCTRL_SEESTAT_RLOCK_Msk (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos) /**< (NVMCTRL_SEESTAT) SmartEEPROM Write Access To Register Address Space Is Locked Mask */
#define NVMCTRL_SEESTAT_RLOCK(value) (NVMCTRL_SEESTAT_RLOCK_Msk & ((value) << NVMCTRL_SEESTAT_RLOCK_Pos))
#define NVMCTRL_SEESTAT_SBLK_Pos _U_(8) /**< (NVMCTRL_SEESTAT) Blocks Number In a Sector Position */
#define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos) /**< (NVMCTRL_SEESTAT) Blocks Number In a Sector Mask */
#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
#define NVMCTRL_SEESTAT_PSZ_Pos _U_(16) /**< (NVMCTRL_SEESTAT) SmartEEPROM Page Size Position */
#define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos) /**< (NVMCTRL_SEESTAT) SmartEEPROM Page Size Mask */
#define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
#define NVMCTRL_SEESTAT_Msk _U_(0x00070F1F) /**< (NVMCTRL_SEESTAT) Register Mask */
/** \brief NVMCTRL register offsets definitions */
#define NVMCTRL_CTRLA_REG_OFST (0x00) /**< (NVMCTRL_CTRLA) Control A Offset */
#define NVMCTRL_CTRLB_REG_OFST (0x04) /**< (NVMCTRL_CTRLB) Control B Offset */
#define NVMCTRL_PARAM_REG_OFST (0x08) /**< (NVMCTRL_PARAM) NVM Parameter Offset */
#define NVMCTRL_INTENCLR_REG_OFST (0x0C) /**< (NVMCTRL_INTENCLR) Interrupt Enable Clear Offset */
#define NVMCTRL_INTENSET_REG_OFST (0x0E) /**< (NVMCTRL_INTENSET) Interrupt Enable Set Offset */
#define NVMCTRL_INTFLAG_REG_OFST (0x10) /**< (NVMCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
#define NVMCTRL_STATUS_REG_OFST (0x12) /**< (NVMCTRL_STATUS) Status Offset */
#define NVMCTRL_ADDR_REG_OFST (0x14) /**< (NVMCTRL_ADDR) Address Offset */
#define NVMCTRL_RUNLOCK_REG_OFST (0x18) /**< (NVMCTRL_RUNLOCK) Lock Section Offset */
#define NVMCTRL_PBLDATA_REG_OFST (0x1C) /**< (NVMCTRL_PBLDATA) Page Buffer Load Data x Offset */
#define NVMCTRL_ECCERR_REG_OFST (0x24) /**< (NVMCTRL_ECCERR) ECC Error Status Register Offset */
#define NVMCTRL_DBGCTRL_REG_OFST (0x28) /**< (NVMCTRL_DBGCTRL) Debug Control Offset */
#define NVMCTRL_SEECFG_REG_OFST (0x2A) /**< (NVMCTRL_SEECFG) SmartEEPROM Configuration Register Offset */
#define NVMCTRL_SEESTAT_REG_OFST (0x2C) /**< (NVMCTRL_SEESTAT) SmartEEPROM Status Register Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief NVMCTRL register API structure */
typedef struct
{ /* Non-Volatile Memory Controller */
__IO uint16_t NVMCTRL_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */
__I uint8_t Reserved1[0x02];
__O uint16_t NVMCTRL_CTRLB; /**< Offset: 0x04 ( /W 16) Control B */
__I uint8_t Reserved2[0x02];
__I uint32_t NVMCTRL_PARAM; /**< Offset: 0x08 (R/ 32) NVM Parameter */
__IO uint16_t NVMCTRL_INTENCLR; /**< Offset: 0x0C (R/W 16) Interrupt Enable Clear */
__IO uint16_t NVMCTRL_INTENSET; /**< Offset: 0x0E (R/W 16) Interrupt Enable Set */
__IO uint16_t NVMCTRL_INTFLAG; /**< Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */
__I uint16_t NVMCTRL_STATUS; /**< Offset: 0x12 (R/ 16) Status */
__IO uint32_t NVMCTRL_ADDR; /**< Offset: 0x14 (R/W 32) Address */
__I uint32_t NVMCTRL_RUNLOCK; /**< Offset: 0x18 (R/ 32) Lock Section */
__I uint32_t NVMCTRL_PBLDATA[2]; /**< Offset: 0x1C (R/ 32) Page Buffer Load Data x */
__I uint32_t NVMCTRL_ECCERR; /**< Offset: 0x24 (R/ 32) ECC Error Status Register */
__IO uint8_t NVMCTRL_DBGCTRL; /**< Offset: 0x28 (R/W 8) Debug Control */
__I uint8_t Reserved3[0x01];
__IO uint8_t NVMCTRL_SEECFG; /**< Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */
__I uint8_t Reserved4[0x01];
__I uint32_t NVMCTRL_SEESTAT; /**< Offset: 0x2C (R/ 32) SmartEEPROM Status Register */
} nvmctrl_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_NVMCTRL_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/osc32kctrl.h
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/**
* \brief Component description for OSC32KCTRL
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_OSC32KCTRL_COMPONENT_H_
#define _SAMD51_OSC32KCTRL_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR OSC32KCTRL */
/* ************************************************************************** */
/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Reset Value */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY(value) (OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos))
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL(value) (OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos))
#define OSC32KCTRL_INTENCLR_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTENCLR) Register Mask */
/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTENSET) Interrupt Enable Set Reset Value */
#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */
#define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */
#define OSC32KCTRL_INTENSET_XOSC32KRDY(value) (OSC32KCTRL_INTENSET_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos))
#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */
#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */
#define OSC32KCTRL_INTENSET_XOSC32KFAIL(value) (OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos))
#define OSC32KCTRL_INTENSET_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTENSET) Register Mask */
/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY(value) (OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos))
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL(value) (OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos))
#define OSC32KCTRL_INTFLAG_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTFLAG) Register Mask */
/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */
#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_STATUS) Power and Clocks Status Reset Value */
#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_STATUS) XOSC32K Ready Position */
#define OSC32KCTRL_STATUS_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Ready Mask */
#define OSC32KCTRL_STATUS_XOSC32KRDY(value) (OSC32KCTRL_STATUS_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos))
#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */
#define OSC32KCTRL_STATUS_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */
#define OSC32KCTRL_STATUS_XOSC32KFAIL(value) (OSC32KCTRL_STATUS_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos))
#define OSC32KCTRL_STATUS_XOSC32KSW_Pos _U_(3) /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */
#define OSC32KCTRL_STATUS_XOSC32KSW_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */
#define OSC32KCTRL_STATUS_XOSC32KSW(value) (OSC32KCTRL_STATUS_XOSC32KSW_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KSW_Pos))
#define OSC32KCTRL_STATUS_Msk _U_(0x0000000D) /**< (OSC32KCTRL_STATUS) Register Mask */
/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Reset Value */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos _U_(0) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Position */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Mask */
#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator Position */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator Position */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position */
#define OSC32KCTRL_RTCCTRL_Msk _U_(0x07) /**< (OSC32KCTRL_RTCCTRL) Register Mask */
/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Reset Value */
#define OSC32KCTRL_XOSC32K_ENABLE_Pos _U_(1) /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Position */
#define OSC32KCTRL_XOSC32K_ENABLE_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */
#define OSC32KCTRL_XOSC32K_ENABLE(value) (OSC32KCTRL_XOSC32K_ENABLE_Msk & ((value) << OSC32KCTRL_XOSC32K_ENABLE_Pos))
#define OSC32KCTRL_XOSC32K_XTALEN_Pos _U_(2) /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */
#define OSC32KCTRL_XOSC32K_XTALEN_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */
#define OSC32KCTRL_XOSC32K_XTALEN(value) (OSC32KCTRL_XOSC32K_XTALEN_Msk & ((value) << OSC32KCTRL_XOSC32K_XTALEN_Pos))
#define OSC32KCTRL_XOSC32K_EN32K_Pos _U_(3) /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Position */
#define OSC32KCTRL_XOSC32K_EN32K_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Mask */
#define OSC32KCTRL_XOSC32K_EN32K(value) (OSC32KCTRL_XOSC32K_EN32K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN32K_Pos))
#define OSC32KCTRL_XOSC32K_EN1K_Pos _U_(4) /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Position */
#define OSC32KCTRL_XOSC32K_EN1K_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Mask */
#define OSC32KCTRL_XOSC32K_EN1K(value) (OSC32KCTRL_XOSC32K_EN1K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN1K_Pos))
#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos _U_(6) /**< (OSC32KCTRL_XOSC32K) Run in Standby Position */
#define OSC32KCTRL_XOSC32K_RUNSTDBY_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) /**< (OSC32KCTRL_XOSC32K) Run in Standby Mask */
#define OSC32KCTRL_XOSC32K_RUNSTDBY(value) (OSC32KCTRL_XOSC32K_RUNSTDBY_Msk & ((value) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos))
#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos _U_(7) /**< (OSC32KCTRL_XOSC32K) On Demand Control Position */
#define OSC32KCTRL_XOSC32K_ONDEMAND_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) /**< (OSC32KCTRL_XOSC32K) On Demand Control Mask */
#define OSC32KCTRL_XOSC32K_ONDEMAND(value) (OSC32KCTRL_XOSC32K_ONDEMAND_Msk & ((value) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos))
#define OSC32KCTRL_XOSC32K_STARTUP_Pos _U_(8) /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Position */
#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Mask */
#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val _U_(0x0) /**< (OSC32KCTRL_XOSC32K) 62.6 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val _U_(0x1) /**< (OSC32KCTRL_XOSC32K) 125 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val _U_(0x2) /**< (OSC32KCTRL_XOSC32K) 500 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val _U_(0x3) /**< (OSC32KCTRL_XOSC32K) 1000 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val _U_(0x4) /**< (OSC32KCTRL_XOSC32K) 2000 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val _U_(0x5) /**< (OSC32KCTRL_XOSC32K) 4000 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val _U_(0x6) /**< (OSC32KCTRL_XOSC32K) 8000 ms */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 62.6 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 125 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 500 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 1000 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 2000 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 4000 ms Position */
#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 8000 ms Position */
#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos _U_(12) /**< (OSC32KCTRL_XOSC32K) Write Lock Position */
#define OSC32KCTRL_XOSC32K_WRTLOCK_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) /**< (OSC32KCTRL_XOSC32K) Write Lock Mask */
#define OSC32KCTRL_XOSC32K_WRTLOCK(value) (OSC32KCTRL_XOSC32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos))
#define OSC32KCTRL_XOSC32K_CGM_Pos _U_(13) /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Position */
#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Mask */
#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< (OSC32KCTRL_XOSC32K) Standard mode */
#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< (OSC32KCTRL_XOSC32K) High Speed mode */
#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) Standard mode Position */
#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) High Speed mode Position */
#define OSC32KCTRL_XOSC32K_Msk _U_(0x77DE) /**< (OSC32KCTRL_XOSC32K) Register Mask */
/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Reset Value */
#define OSC32KCTRL_CFDCTRL_CFDEN_Pos _U_(0) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */
#define OSC32KCTRL_CFDCTRL_CFDEN_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */
#define OSC32KCTRL_CFDCTRL_CFDEN(value) (OSC32KCTRL_CFDCTRL_CFDEN_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDEN_Pos))
#define OSC32KCTRL_CFDCTRL_SWBACK_Pos _U_(1) /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */
#define OSC32KCTRL_CFDCTRL_SWBACK_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */
#define OSC32KCTRL_CFDCTRL_SWBACK(value) (OSC32KCTRL_CFDCTRL_SWBACK_Msk & ((value) << OSC32KCTRL_CFDCTRL_SWBACK_Pos))
#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos _U_(2) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */
#define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */
#define OSC32KCTRL_CFDCTRL_CFDPRESC(value) (OSC32KCTRL_CFDCTRL_CFDPRESC_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos))
#define OSC32KCTRL_CFDCTRL_Msk _U_(0x07) /**< (OSC32KCTRL_CFDCTRL) Register Mask */
/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_EVCTRL) Event Control Reset Value */
#define OSC32KCTRL_EVCTRL_CFDEO_Pos _U_(0) /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
#define OSC32KCTRL_EVCTRL_CFDEO_Msk (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos) /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
#define OSC32KCTRL_EVCTRL_CFDEO(value) (OSC32KCTRL_EVCTRL_CFDEO_Msk & ((value) << OSC32KCTRL_EVCTRL_CFDEO_Pos))
#define OSC32KCTRL_EVCTRL_Msk _U_(0x01) /**< (OSC32KCTRL_EVCTRL) Register Mask */
/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Reset Value */
#define OSC32KCTRL_OSCULP32K_EN32K_Pos _U_(1) /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Position */
#define OSC32KCTRL_OSCULP32K_EN32K_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos) /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Mask */
#define OSC32KCTRL_OSCULP32K_EN32K(value) (OSC32KCTRL_OSCULP32K_EN32K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN32K_Pos))
#define OSC32KCTRL_OSCULP32K_EN1K_Pos _U_(2) /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Position */
#define OSC32KCTRL_OSCULP32K_EN1K_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos) /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Mask */
#define OSC32KCTRL_OSCULP32K_EN1K(value) (OSC32KCTRL_OSCULP32K_EN1K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN1K_Pos))
#define OSC32KCTRL_OSCULP32K_CALIB_Pos _U_(8) /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Position */
#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Mask */
#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos _U_(15) /**< (OSC32KCTRL_OSCULP32K) Write Lock Position */
#define OSC32KCTRL_OSCULP32K_WRTLOCK_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) /**< (OSC32KCTRL_OSCULP32K) Write Lock Mask */
#define OSC32KCTRL_OSCULP32K_WRTLOCK(value) (OSC32KCTRL_OSCULP32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos))
#define OSC32KCTRL_OSCULP32K_Msk _U_(0x0000BF06) /**< (OSC32KCTRL_OSCULP32K) Register Mask */
/** \brief OSC32KCTRL register offsets definitions */
#define OSC32KCTRL_INTENCLR_REG_OFST (0x00) /**< (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Offset */
#define OSC32KCTRL_INTENSET_REG_OFST (0x04) /**< (OSC32KCTRL_INTENSET) Interrupt Enable Set Offset */
#define OSC32KCTRL_INTFLAG_REG_OFST (0x08) /**< (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
#define OSC32KCTRL_STATUS_REG_OFST (0x0C) /**< (OSC32KCTRL_STATUS) Power and Clocks Status Offset */
#define OSC32KCTRL_RTCCTRL_REG_OFST (0x10) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Offset */
#define OSC32KCTRL_XOSC32K_REG_OFST (0x14) /**< (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Offset */
#define OSC32KCTRL_CFDCTRL_REG_OFST (0x16) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Offset */
#define OSC32KCTRL_EVCTRL_REG_OFST (0x17) /**< (OSC32KCTRL_EVCTRL) Event Control Offset */
#define OSC32KCTRL_OSCULP32K_REG_OFST (0x1C) /**< (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief OSC32KCTRL register API structure */
typedef struct
{ /* 32kHz Oscillators Control */
__IO uint32_t OSC32KCTRL_INTENCLR; /**< Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO uint32_t OSC32KCTRL_INTENSET; /**< Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO uint32_t OSC32KCTRL_INTFLAG; /**< Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I uint32_t OSC32KCTRL_STATUS; /**< Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO uint8_t OSC32KCTRL_RTCCTRL; /**< Offset: 0x10 (R/W 8) RTC Clock Selection */
__I uint8_t Reserved1[0x03];
__IO uint16_t OSC32KCTRL_XOSC32K; /**< Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
__IO uint8_t OSC32KCTRL_CFDCTRL; /**< Offset: 0x16 (R/W 8) Clock Failure Detector Control */
__IO uint8_t OSC32KCTRL_EVCTRL; /**< Offset: 0x17 (R/W 8) Event Control */
__I uint8_t Reserved2[0x04];
__IO uint32_t OSC32KCTRL_OSCULP32K; /**< Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
} osc32kctrl_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_OSC32KCTRL_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/oscctrl.h
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/**
* \brief Component description for OSCCTRL
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_OSCCTRL_COMPONENT_H_
#define _SAMD51_OSCCTRL_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR OSCCTRL */
/* ************************************************************************** */
/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x00) (R/W 8) DPLL Control A -------- */
#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< (OSCCTRL_DPLLCTRLA) DPLL Control A Reset Value */
#define OSCCTRL_DPLLCTRLA_ENABLE_Pos _U_(1) /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Position */
#define OSCCTRL_DPLLCTRLA_ENABLE_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) /**< (OSCCTRL_DPLLCTRLA) DPLL Enable Mask */
#define OSCCTRL_DPLLCTRLA_ENABLE(value) (OSCCTRL_DPLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DPLLCTRLA_ENABLE_Pos))
#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_DPLLCTRLA) Run in Standby Position */
#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) /**< (OSCCTRL_DPLLCTRLA) Run in Standby Mask */
#define OSCCTRL_DPLLCTRLA_RUNSTDBY(value) (OSCCTRL_DPLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos))
#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_DPLLCTRLA) On Demand Control Position */
#define OSCCTRL_DPLLCTRLA_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) /**< (OSCCTRL_DPLLCTRLA) On Demand Control Mask */
#define OSCCTRL_DPLLCTRLA_ONDEMAND(value) (OSCCTRL_DPLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos))
#define OSCCTRL_DPLLCTRLA_Msk _U_(0xC2) /**< (OSCCTRL_DPLLCTRLA) Register Mask */
/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x04) (R/W 32) DPLL Ratio Control -------- */
#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLRATIO) DPLL Ratio Control Reset Value */
#define OSCCTRL_DPLLRATIO_LDR_Pos _U_(0) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Position */
#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Mask */
#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos _U_(16) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Position */
#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) /**< (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part Mask */
#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
#define OSCCTRL_DPLLRATIO_Msk _U_(0x001F1FFF) /**< (OSCCTRL_DPLLRATIO) Register Mask */
/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x08) (R/W 32) DPLL Control B -------- */
#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x20) /**< (OSCCTRL_DPLLCTRLB) DPLL Control B Reset Value */
#define OSCCTRL_DPLLCTRLB_FILTER_Pos _U_(0) /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Position */
#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection Mask */
#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val _U_(0x8) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val _U_(0x9) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val _U_(0xA) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val _U_(0xB) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val _U_(0xC) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val _U_(0xD) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val _U_(0xE) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val _U_(0xF) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER1 (OSCCTRL_DPLLCTRLB_FILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.76 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER2 (OSCCTRL_DPLLCTRLB_FILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 1.08 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER3 (OSCCTRL_DPLLCTRLB_FILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.38 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER4 (OSCCTRL_DPLLCTRLB_FILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.54 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER5 (OSCCTRL_DPLLCTRLB_FILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 131Khz and Damping Factor = 0.56 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER6 (OSCCTRL_DPLLCTRLB_FILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 185Khz and Damping Factor = 0.79 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER7 (OSCCTRL_DPLLCTRLB_FILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 0.28 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER8 (OSCCTRL_DPLLCTRLB_FILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 0.39 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER9 (OSCCTRL_DPLLCTRLB_FILTER_FILTER9_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 1.49 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER10 (OSCCTRL_DPLLCTRLB_FILTER_FILTER10_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 2.11 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER11 (OSCCTRL_DPLLCTRLB_FILTER_FILTER11_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 23.2Khz and Damping Factor = 0.75 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER12 (OSCCTRL_DPLLCTRLB_FILTER_FILTER12_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 1.06 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER13 (OSCCTRL_DPLLCTRLB_FILTER_FILTER13_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 65.6Khz and Damping Factor = 1.07 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER14 (OSCCTRL_DPLLCTRLB_FILTER_FILTER14_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 92.7Khz and Damping Factor = 1.51 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER15 (OSCCTRL_DPLLCTRLB_FILTER_FILTER15_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 32.8Khz and Damping Factor = 0.53 Position */
#define OSCCTRL_DPLLCTRLB_FILTER_FILTER16 (OSCCTRL_DPLLCTRLB_FILTER_FILTER16_Val << OSCCTRL_DPLLCTRLB_FILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Bandwidth = 46.4Khz and Damping Factor = 0.75 Position */
#define OSCCTRL_DPLLCTRLB_WUF_Pos _U_(4) /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Position */
#define OSCCTRL_DPLLCTRLB_WUF_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) /**< (OSCCTRL_DPLLCTRLB) Wake Up Fast Mask */
#define OSCCTRL_DPLLCTRLB_WUF(value) (OSCCTRL_DPLLCTRLB_WUF_Msk & ((value) << OSCCTRL_DPLLCTRLB_WUF_Pos))
#define OSCCTRL_DPLLCTRLB_REFCLK_Pos _U_(5) /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Position */
#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) Reference Clock Selection Mask */
#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */
#define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference Position */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC32K clock reference Position */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC0 clock reference Position */
#define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) /**< (OSCCTRL_DPLLCTRLB) XOSC1 clock reference Position */
#define OSCCTRL_DPLLCTRLB_LTIME_Pos _U_(8) /**< (OSCCTRL_DPLLCTRLB) Lock Time Position */
#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Lock Time Mask */
#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */
#define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */
#define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */
#define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */
#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */
#define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock Position */
#define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us Position */
#define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us Position */
#define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms Position */
#define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) /**< (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms Position */
#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos _U_(11) /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Position */
#define OSCCTRL_DPLLCTRLB_LBYPASS_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) /**< (OSCCTRL_DPLLCTRLB) Lock Bypass Mask */
#define OSCCTRL_DPLLCTRLB_LBYPASS(value) (OSCCTRL_DPLLCTRLB_LBYPASS_Msk & ((value) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos))
#define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos _U_(12) /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection Mask */
#define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val _U_(0x0) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val _U_(0x1) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val _U_(0x2) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val _U_(0x3) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val _U_(0x4) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val _U_(0x5) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val _U_(0x6) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val _U_(0x7) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER1_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER2_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER3_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER4_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER5_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER6_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER7_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 Position */
#define OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8 (OSCCTRL_DPLLCTRLB_DCOFILTER_FILTER8_Val << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) /**< (OSCCTRL_DPLLCTRLB) Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 Position */
#define OSCCTRL_DPLLCTRLB_DCOEN_Pos _U_(15) /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Position */
#define OSCCTRL_DPLLCTRLB_DCOEN_Msk (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos) /**< (OSCCTRL_DPLLCTRLB) DCO Filter Enable Mask */
#define OSCCTRL_DPLLCTRLB_DCOEN(value) (OSCCTRL_DPLLCTRLB_DCOEN_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOEN_Pos))
#define OSCCTRL_DPLLCTRLB_DIV_Pos _U_(16) /**< (OSCCTRL_DPLLCTRLB) Clock Divider Position */
#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) /**< (OSCCTRL_DPLLCTRLB) Clock Divider Mask */
#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
#define OSCCTRL_DPLLCTRLB_Msk _U_(0x07FFFFFF) /**< (OSCCTRL_DPLLCTRLB) Register Mask */
/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x0C) ( R/ 32) DPLL Synchronization Busy -------- */
#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Reset Value */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos _U_(1) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Position */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status Mask */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE(value) (OSCCTRL_DPLLSYNCBUSY_ENABLE_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos))
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos _U_(2) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Position */
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status Mask */
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO(value) (OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Msk & ((value) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos))
#define OSCCTRL_DPLLSYNCBUSY_Msk _U_(0x00000006) /**< (OSCCTRL_DPLLSYNCBUSY) Register Mask */
/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x10) ( R/ 32) DPLL Status -------- */
#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00) /**< (OSCCTRL_DPLLSTATUS) DPLL Status Reset Value */
#define OSCCTRL_DPLLSTATUS_LOCK_Pos _U_(0) /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Position */
#define OSCCTRL_DPLLSTATUS_LOCK_Msk (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) /**< (OSCCTRL_DPLLSTATUS) DPLL Lock Status Mask */
#define OSCCTRL_DPLLSTATUS_LOCK(value) (OSCCTRL_DPLLSTATUS_LOCK_Msk & ((value) << OSCCTRL_DPLLSTATUS_LOCK_Pos))
#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos _U_(1) /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Position */
#define OSCCTRL_DPLLSTATUS_CLKRDY_Msk (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) /**< (OSCCTRL_DPLLSTATUS) DPLL Clock Ready Mask */
#define OSCCTRL_DPLLSTATUS_CLKRDY(value) (OSCCTRL_DPLLSTATUS_CLKRDY_Msk & ((value) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos))
#define OSCCTRL_DPLLSTATUS_Msk _U_(0x00000003) /**< (OSCCTRL_DPLLSTATUS) Register Mask */
/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< (OSCCTRL_EVCTRL) Event Control Reset Value */
#define OSCCTRL_EVCTRL_CFDEO0_Pos _U_(0) /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Position */
#define OSCCTRL_EVCTRL_CFDEO0_Msk (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO0_Pos) /**< (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable Mask */
#define OSCCTRL_EVCTRL_CFDEO0(value) (OSCCTRL_EVCTRL_CFDEO0_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO0_Pos))
#define OSCCTRL_EVCTRL_CFDEO1_Pos _U_(1) /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Position */
#define OSCCTRL_EVCTRL_CFDEO1_Msk (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO1_Pos) /**< (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable Mask */
#define OSCCTRL_EVCTRL_CFDEO1(value) (OSCCTRL_EVCTRL_CFDEO1_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO1_Pos))
#define OSCCTRL_EVCTRL_Msk _U_(0x03) /**< (OSCCTRL_EVCTRL) Register Mask */
#define OSCCTRL_EVCTRL_CFDEO_Pos _U_(0) /**< (OSCCTRL_EVCTRL Position) Clock x Failure Detector Event Output Enable */
#define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos) /**< (OSCCTRL_EVCTRL Mask) CFDEO */
#define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTENCLR) Interrupt Enable Clear Reset Value */
#define OSCCTRL_INTENCLR_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Position */
#define OSCCTRL_INTENCLR_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos) /**< (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_XOSCRDY0(value) (OSCCTRL_INTENCLR_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY0_Pos))
#define OSCCTRL_INTENCLR_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Position */
#define OSCCTRL_INTENCLR_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos) /**< (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_XOSCRDY1(value) (OSCCTRL_INTENCLR_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY1_Pos))
#define OSCCTRL_INTENCLR_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Position */
#define OSCCTRL_INTENCLR_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos) /**< (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_XOSCFAIL0(value) (OSCCTRL_INTENCLR_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos))
#define OSCCTRL_INTENCLR_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Position */
#define OSCCTRL_INTENCLR_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos) /**< (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_XOSCFAIL1(value) (OSCCTRL_INTENCLR_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos))
#define OSCCTRL_INTENCLR_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) /**< (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DFLLRDY(value) (OSCCTRL_INTENCLR_DFLLRDY_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRDY_Pos))
#define OSCCTRL_INTENCLR_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) /**< (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DFLLOOB(value) (OSCCTRL_INTENCLR_DFLLOOB_Msk & ((value) << OSCCTRL_INTENCLR_DFLLOOB_Pos))
#define OSCCTRL_INTENCLR_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) /**< (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DFLLLCKF(value) (OSCCTRL_INTENCLR_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKF_Pos))
#define OSCCTRL_INTENCLR_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) /**< (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DFLLLCKC(value) (OSCCTRL_INTENCLR_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENCLR_DFLLLCKC_Pos))
#define OSCCTRL_INTENCLR_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) /**< (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DFLLRCS(value) (OSCCTRL_INTENCLR_DFLLRCS_Msk & ((value) << OSCCTRL_INTENCLR_DFLLRCS_Pos))
#define OSCCTRL_INTENCLR_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL0LCKR(value) (OSCCTRL_INTENCLR_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos))
#define OSCCTRL_INTENCLR_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL0LCKF(value) (OSCCTRL_INTENCLR_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos))
#define OSCCTRL_INTENCLR_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL0LTO(value) (OSCCTRL_INTENCLR_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LTO_Pos))
#define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL0LDRTO(value) (OSCCTRL_INTENCLR_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos))
#define OSCCTRL_INTENCLR_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL1LCKR(value) (OSCCTRL_INTENCLR_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos))
#define OSCCTRL_INTENCLR_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL1LCKF(value) (OSCCTRL_INTENCLR_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos))
#define OSCCTRL_INTENCLR_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL1LTO(value) (OSCCTRL_INTENCLR_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LTO_Pos))
#define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
#define OSCCTRL_INTENCLR_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
#define OSCCTRL_INTENCLR_DPLL1LDRTO(value) (OSCCTRL_INTENCLR_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos))
#define OSCCTRL_INTENCLR_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTENCLR) Register Mask */
#define OSCCTRL_INTENCLR_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTENCLR Position) XOSC x Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos) /**< (OSCCTRL_INTENCLR Mask) XOSCRDY */
#define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
#define OSCCTRL_INTENCLR_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTENCLR Position) XOSC x Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos) /**< (OSCCTRL_INTENCLR Mask) XOSCFAIL */
#define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTENSET) Interrupt Enable Set Reset Value */
#define OSCCTRL_INTENSET_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Position */
#define OSCCTRL_INTENSET_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY0_Pos) /**< (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable Mask */
#define OSCCTRL_INTENSET_XOSCRDY0(value) (OSCCTRL_INTENSET_XOSCRDY0_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY0_Pos))
#define OSCCTRL_INTENSET_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Position */
#define OSCCTRL_INTENSET_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY1_Pos) /**< (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable Mask */
#define OSCCTRL_INTENSET_XOSCRDY1(value) (OSCCTRL_INTENSET_XOSCRDY1_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY1_Pos))
#define OSCCTRL_INTENSET_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Position */
#define OSCCTRL_INTENSET_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos) /**< (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable Mask */
#define OSCCTRL_INTENSET_XOSCFAIL0(value) (OSCCTRL_INTENSET_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL0_Pos))
#define OSCCTRL_INTENSET_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Position */
#define OSCCTRL_INTENSET_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos) /**< (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable Mask */
#define OSCCTRL_INTENSET_XOSCFAIL1(value) (OSCCTRL_INTENSET_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL1_Pos))
#define OSCCTRL_INTENSET_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Position */
#define OSCCTRL_INTENSET_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) /**< (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DFLLRDY(value) (OSCCTRL_INTENSET_DFLLRDY_Msk & ((value) << OSCCTRL_INTENSET_DFLLRDY_Pos))
#define OSCCTRL_INTENSET_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Position */
#define OSCCTRL_INTENSET_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) /**< (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DFLLOOB(value) (OSCCTRL_INTENSET_DFLLOOB_Msk & ((value) << OSCCTRL_INTENSET_DFLLOOB_Pos))
#define OSCCTRL_INTENSET_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Position */
#define OSCCTRL_INTENSET_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) /**< (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DFLLLCKF(value) (OSCCTRL_INTENSET_DFLLLCKF_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKF_Pos))
#define OSCCTRL_INTENSET_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Position */
#define OSCCTRL_INTENSET_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) /**< (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DFLLLCKC(value) (OSCCTRL_INTENSET_DFLLLCKC_Msk & ((value) << OSCCTRL_INTENSET_DFLLLCKC_Pos))
#define OSCCTRL_INTENSET_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Position */
#define OSCCTRL_INTENSET_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) /**< (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DFLLRCS(value) (OSCCTRL_INTENSET_DFLLRCS_Msk & ((value) << OSCCTRL_INTENSET_DFLLRCS_Pos))
#define OSCCTRL_INTENSET_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL0LCKR(value) (OSCCTRL_INTENSET_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKR_Pos))
#define OSCCTRL_INTENSET_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL0LCKF(value) (OSCCTRL_INTENSET_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LCKF_Pos))
#define OSCCTRL_INTENSET_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL0LTO(value) (OSCCTRL_INTENSET_DPLL0LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LTO_Pos))
#define OSCCTRL_INTENSET_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL0LDRTO(value) (OSCCTRL_INTENSET_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos))
#define OSCCTRL_INTENSET_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL1LCKR(value) (OSCCTRL_INTENSET_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKR_Pos))
#define OSCCTRL_INTENSET_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL1LCKF(value) (OSCCTRL_INTENSET_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LCKF_Pos))
#define OSCCTRL_INTENSET_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL1LTO(value) (OSCCTRL_INTENSET_DPLL1LTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LTO_Pos))
#define OSCCTRL_INTENSET_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Position */
#define OSCCTRL_INTENSET_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable Mask */
#define OSCCTRL_INTENSET_DPLL1LDRTO(value) (OSCCTRL_INTENSET_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos))
#define OSCCTRL_INTENSET_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTENSET) Register Mask */
#define OSCCTRL_INTENSET_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTENSET Position) XOSC x Ready Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos) /**< (OSCCTRL_INTENSET Mask) XOSCRDY */
#define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
#define OSCCTRL_INTENSET_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTENSET Position) XOSC x Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos) /**< (OSCCTRL_INTENSET Mask) XOSCFAIL */
#define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define OSCCTRL_INTFLAG_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Position */
#define OSCCTRL_INTFLAG_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos) /**< (OSCCTRL_INTFLAG) XOSC 0 Ready Mask */
#define OSCCTRL_INTFLAG_XOSCRDY0(value) (OSCCTRL_INTFLAG_XOSCRDY0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY0_Pos))
#define OSCCTRL_INTFLAG_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Position */
#define OSCCTRL_INTFLAG_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos) /**< (OSCCTRL_INTFLAG) XOSC 1 Ready Mask */
#define OSCCTRL_INTFLAG_XOSCRDY1(value) (OSCCTRL_INTFLAG_XOSCRDY1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY1_Pos))
#define OSCCTRL_INTFLAG_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Position */
#define OSCCTRL_INTFLAG_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos) /**< (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector Mask */
#define OSCCTRL_INTFLAG_XOSCFAIL0(value) (OSCCTRL_INTFLAG_XOSCFAIL0_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos))
#define OSCCTRL_INTFLAG_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Position */
#define OSCCTRL_INTFLAG_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos) /**< (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector Mask */
#define OSCCTRL_INTFLAG_XOSCFAIL1(value) (OSCCTRL_INTFLAG_XOSCFAIL1_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos))
#define OSCCTRL_INTFLAG_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_INTFLAG) DFLL Ready Position */
#define OSCCTRL_INTFLAG_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) /**< (OSCCTRL_INTFLAG) DFLL Ready Mask */
#define OSCCTRL_INTFLAG_DFLLRDY(value) (OSCCTRL_INTFLAG_DFLLRDY_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRDY_Pos))
#define OSCCTRL_INTFLAG_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Position */
#define OSCCTRL_INTFLAG_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) /**< (OSCCTRL_INTFLAG) DFLL Out Of Bounds Mask */
#define OSCCTRL_INTFLAG_DFLLOOB(value) (OSCCTRL_INTFLAG_DFLLOOB_Msk & ((value) << OSCCTRL_INTFLAG_DFLLOOB_Pos))
#define OSCCTRL_INTFLAG_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Position */
#define OSCCTRL_INTFLAG_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) /**< (OSCCTRL_INTFLAG) DFLL Lock Fine Mask */
#define OSCCTRL_INTFLAG_DFLLLCKF(value) (OSCCTRL_INTFLAG_DFLLLCKF_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKF_Pos))
#define OSCCTRL_INTFLAG_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Position */
#define OSCCTRL_INTFLAG_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) /**< (OSCCTRL_INTFLAG) DFLL Lock Coarse Mask */
#define OSCCTRL_INTFLAG_DFLLLCKC(value) (OSCCTRL_INTFLAG_DFLLLCKC_Msk & ((value) << OSCCTRL_INTFLAG_DFLLLCKC_Pos))
#define OSCCTRL_INTFLAG_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Position */
#define OSCCTRL_INTFLAG_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) /**< (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped Mask */
#define OSCCTRL_INTFLAG_DFLLRCS(value) (OSCCTRL_INTFLAG_DFLLRCS_Msk & ((value) << OSCCTRL_INTFLAG_DFLLRCS_Pos))
#define OSCCTRL_INTFLAG_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Position */
#define OSCCTRL_INTFLAG_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Rise Mask */
#define OSCCTRL_INTFLAG_DPLL0LCKR(value) (OSCCTRL_INTFLAG_DPLL0LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos))
#define OSCCTRL_INTFLAG_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Position */
#define OSCCTRL_INTFLAG_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Fall Mask */
#define OSCCTRL_INTFLAG_DPLL0LCKF(value) (OSCCTRL_INTFLAG_DPLL0LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos))
#define OSCCTRL_INTFLAG_DPLL0LTO_Pos _U_(18) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Position */
#define OSCCTRL_INTFLAG_DPLL0LTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Lock Timeout Mask */
#define OSCCTRL_INTFLAG_DPLL0LTO(value) (OSCCTRL_INTFLAG_DPLL0LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LTO_Pos))
#define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Position */
#define OSCCTRL_INTFLAG_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete Mask */
#define OSCCTRL_INTFLAG_DPLL0LDRTO(value) (OSCCTRL_INTFLAG_DPLL0LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos))
#define OSCCTRL_INTFLAG_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Position */
#define OSCCTRL_INTFLAG_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Rise Mask */
#define OSCCTRL_INTFLAG_DPLL1LCKR(value) (OSCCTRL_INTFLAG_DPLL1LCKR_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos))
#define OSCCTRL_INTFLAG_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Position */
#define OSCCTRL_INTFLAG_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Fall Mask */
#define OSCCTRL_INTFLAG_DPLL1LCKF(value) (OSCCTRL_INTFLAG_DPLL1LCKF_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos))
#define OSCCTRL_INTFLAG_DPLL1LTO_Pos _U_(26) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Position */
#define OSCCTRL_INTFLAG_DPLL1LTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Lock Timeout Mask */
#define OSCCTRL_INTFLAG_DPLL1LTO(value) (OSCCTRL_INTFLAG_DPLL1LTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LTO_Pos))
#define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Position */
#define OSCCTRL_INTFLAG_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos) /**< (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete Mask */
#define OSCCTRL_INTFLAG_DPLL1LDRTO(value) (OSCCTRL_INTFLAG_DPLL1LDRTO_Msk & ((value) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos))
#define OSCCTRL_INTFLAG_Msk _U_(0x0F0F1F0F) /**< (OSCCTRL_INTFLAG) Register Mask */
#define OSCCTRL_INTFLAG_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_INTFLAG Position) XOSC x Ready */
#define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos) /**< (OSCCTRL_INTFLAG Mask) XOSCRDY */
#define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
#define OSCCTRL_INTFLAG_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_INTFLAG Position) XOSC x Clock Failure Detector */
#define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos) /**< (OSCCTRL_INTFLAG Mask) XOSCFAIL */
#define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */
#define OSCCTRL_STATUS_RESETVALUE _U_(0x00) /**< (OSCCTRL_STATUS) Status Reset Value */
#define OSCCTRL_STATUS_XOSCRDY0_Pos _U_(0) /**< (OSCCTRL_STATUS) XOSC 0 Ready Position */
#define OSCCTRL_STATUS_XOSCRDY0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Ready Mask */
#define OSCCTRL_STATUS_XOSCRDY0(value) (OSCCTRL_STATUS_XOSCRDY0_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY0_Pos))
#define OSCCTRL_STATUS_XOSCRDY1_Pos _U_(1) /**< (OSCCTRL_STATUS) XOSC 1 Ready Position */
#define OSCCTRL_STATUS_XOSCRDY1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Ready Mask */
#define OSCCTRL_STATUS_XOSCRDY1(value) (OSCCTRL_STATUS_XOSCRDY1_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY1_Pos))
#define OSCCTRL_STATUS_XOSCFAIL0_Pos _U_(2) /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Position */
#define OSCCTRL_STATUS_XOSCFAIL0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector Mask */
#define OSCCTRL_STATUS_XOSCFAIL0(value) (OSCCTRL_STATUS_XOSCFAIL0_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL0_Pos))
#define OSCCTRL_STATUS_XOSCFAIL1_Pos _U_(3) /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Position */
#define OSCCTRL_STATUS_XOSCFAIL1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector Mask */
#define OSCCTRL_STATUS_XOSCFAIL1(value) (OSCCTRL_STATUS_XOSCFAIL1_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL1_Pos))
#define OSCCTRL_STATUS_XOSCCKSW0_Pos _U_(4) /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Position */
#define OSCCTRL_STATUS_XOSCCKSW0_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW0_Pos) /**< (OSCCTRL_STATUS) XOSC 0 Clock Switch Mask */
#define OSCCTRL_STATUS_XOSCCKSW0(value) (OSCCTRL_STATUS_XOSCCKSW0_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW0_Pos))
#define OSCCTRL_STATUS_XOSCCKSW1_Pos _U_(5) /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Position */
#define OSCCTRL_STATUS_XOSCCKSW1_Msk (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW1_Pos) /**< (OSCCTRL_STATUS) XOSC 1 Clock Switch Mask */
#define OSCCTRL_STATUS_XOSCCKSW1(value) (OSCCTRL_STATUS_XOSCCKSW1_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW1_Pos))
#define OSCCTRL_STATUS_DFLLRDY_Pos _U_(8) /**< (OSCCTRL_STATUS) DFLL Ready Position */
#define OSCCTRL_STATUS_DFLLRDY_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) /**< (OSCCTRL_STATUS) DFLL Ready Mask */
#define OSCCTRL_STATUS_DFLLRDY(value) (OSCCTRL_STATUS_DFLLRDY_Msk & ((value) << OSCCTRL_STATUS_DFLLRDY_Pos))
#define OSCCTRL_STATUS_DFLLOOB_Pos _U_(9) /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Position */
#define OSCCTRL_STATUS_DFLLOOB_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) /**< (OSCCTRL_STATUS) DFLL Out Of Bounds Mask */
#define OSCCTRL_STATUS_DFLLOOB(value) (OSCCTRL_STATUS_DFLLOOB_Msk & ((value) << OSCCTRL_STATUS_DFLLOOB_Pos))
#define OSCCTRL_STATUS_DFLLLCKF_Pos _U_(10) /**< (OSCCTRL_STATUS) DFLL Lock Fine Position */
#define OSCCTRL_STATUS_DFLLLCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) /**< (OSCCTRL_STATUS) DFLL Lock Fine Mask */
#define OSCCTRL_STATUS_DFLLLCKF(value) (OSCCTRL_STATUS_DFLLLCKF_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKF_Pos))
#define OSCCTRL_STATUS_DFLLLCKC_Pos _U_(11) /**< (OSCCTRL_STATUS) DFLL Lock Coarse Position */
#define OSCCTRL_STATUS_DFLLLCKC_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) /**< (OSCCTRL_STATUS) DFLL Lock Coarse Mask */
#define OSCCTRL_STATUS_DFLLLCKC(value) (OSCCTRL_STATUS_DFLLLCKC_Msk & ((value) << OSCCTRL_STATUS_DFLLLCKC_Pos))
#define OSCCTRL_STATUS_DFLLRCS_Pos _U_(12) /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Position */
#define OSCCTRL_STATUS_DFLLRCS_Msk (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) /**< (OSCCTRL_STATUS) DFLL Reference Clock Stopped Mask */
#define OSCCTRL_STATUS_DFLLRCS(value) (OSCCTRL_STATUS_DFLLRCS_Msk & ((value) << OSCCTRL_STATUS_DFLLRCS_Pos))
#define OSCCTRL_STATUS_DPLL0LCKR_Pos _U_(16) /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Position */
#define OSCCTRL_STATUS_DPLL0LCKR_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos) /**< (OSCCTRL_STATUS) DPLL0 Lock Rise Mask */
#define OSCCTRL_STATUS_DPLL0LCKR(value) (OSCCTRL_STATUS_DPLL0LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKR_Pos))
#define OSCCTRL_STATUS_DPLL0LCKF_Pos _U_(17) /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Position */
#define OSCCTRL_STATUS_DPLL0LCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos) /**< (OSCCTRL_STATUS) DPLL0 Lock Fall Mask */
#define OSCCTRL_STATUS_DPLL0LCKF(value) (OSCCTRL_STATUS_DPLL0LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL0LCKF_Pos))
#define OSCCTRL_STATUS_DPLL0TO_Pos _U_(18) /**< (OSCCTRL_STATUS) DPLL0 Timeout Position */
#define OSCCTRL_STATUS_DPLL0TO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos) /**< (OSCCTRL_STATUS) DPLL0 Timeout Mask */
#define OSCCTRL_STATUS_DPLL0TO(value) (OSCCTRL_STATUS_DPLL0TO_Msk & ((value) << OSCCTRL_STATUS_DPLL0TO_Pos))
#define OSCCTRL_STATUS_DPLL0LDRTO_Pos _U_(19) /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Position */
#define OSCCTRL_STATUS_DPLL0LDRTO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos) /**< (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete Mask */
#define OSCCTRL_STATUS_DPLL0LDRTO(value) (OSCCTRL_STATUS_DPLL0LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL0LDRTO_Pos))
#define OSCCTRL_STATUS_DPLL1LCKR_Pos _U_(24) /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Position */
#define OSCCTRL_STATUS_DPLL1LCKR_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos) /**< (OSCCTRL_STATUS) DPLL1 Lock Rise Mask */
#define OSCCTRL_STATUS_DPLL1LCKR(value) (OSCCTRL_STATUS_DPLL1LCKR_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKR_Pos))
#define OSCCTRL_STATUS_DPLL1LCKF_Pos _U_(25) /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Position */
#define OSCCTRL_STATUS_DPLL1LCKF_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos) /**< (OSCCTRL_STATUS) DPLL1 Lock Fall Mask */
#define OSCCTRL_STATUS_DPLL1LCKF(value) (OSCCTRL_STATUS_DPLL1LCKF_Msk & ((value) << OSCCTRL_STATUS_DPLL1LCKF_Pos))
#define OSCCTRL_STATUS_DPLL1TO_Pos _U_(26) /**< (OSCCTRL_STATUS) DPLL1 Timeout Position */
#define OSCCTRL_STATUS_DPLL1TO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos) /**< (OSCCTRL_STATUS) DPLL1 Timeout Mask */
#define OSCCTRL_STATUS_DPLL1TO(value) (OSCCTRL_STATUS_DPLL1TO_Msk & ((value) << OSCCTRL_STATUS_DPLL1TO_Pos))
#define OSCCTRL_STATUS_DPLL1LDRTO_Pos _U_(27) /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Position */
#define OSCCTRL_STATUS_DPLL1LDRTO_Msk (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos) /**< (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete Mask */
#define OSCCTRL_STATUS_DPLL1LDRTO(value) (OSCCTRL_STATUS_DPLL1LDRTO_Msk & ((value) << OSCCTRL_STATUS_DPLL1LDRTO_Pos))
#define OSCCTRL_STATUS_Msk _U_(0x0F0F1F3F) /**< (OSCCTRL_STATUS) Register Mask */
#define OSCCTRL_STATUS_XOSCRDY_Pos _U_(0) /**< (OSCCTRL_STATUS Position) XOSC x Ready */
#define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos) /**< (OSCCTRL_STATUS Mask) XOSCRDY */
#define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
#define OSCCTRL_STATUS_XOSCFAIL_Pos _U_(2) /**< (OSCCTRL_STATUS Position) XOSC x Clock Failure Detector */
#define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos) /**< (OSCCTRL_STATUS Mask) XOSCFAIL */
#define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
#define OSCCTRL_STATUS_XOSCCKSW_Pos _U_(4) /**< (OSCCTRL_STATUS Position) XOSC x Clock Switch */
#define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos) /**< (OSCCTRL_STATUS Mask) XOSCCKSW */
#define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x80) /**< (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Reset Value */
#define OSCCTRL_XOSCCTRL_ENABLE_Pos _U_(1) /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Position */
#define OSCCTRL_XOSCCTRL_ENABLE_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Enable Mask */
#define OSCCTRL_XOSCCTRL_ENABLE(value) (OSCCTRL_XOSCCTRL_ENABLE_Msk & ((value) << OSCCTRL_XOSCCTRL_ENABLE_Pos))
#define OSCCTRL_XOSCCTRL_XTALEN_Pos _U_(2) /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Position */
#define OSCCTRL_XOSCCTRL_XTALEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) /**< (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable Mask */
#define OSCCTRL_XOSCCTRL_XTALEN(value) (OSCCTRL_XOSCCTRL_XTALEN_Msk & ((value) << OSCCTRL_XOSCCTRL_XTALEN_Pos))
#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_XOSCCTRL) Run in Standby Position */
#define OSCCTRL_XOSCCTRL_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) /**< (OSCCTRL_XOSCCTRL) Run in Standby Mask */
#define OSCCTRL_XOSCCTRL_RUNSTDBY(value) (OSCCTRL_XOSCCTRL_RUNSTDBY_Msk & ((value) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos))
#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_XOSCCTRL) On Demand Control Position */
#define OSCCTRL_XOSCCTRL_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) /**< (OSCCTRL_XOSCCTRL) On Demand Control Mask */
#define OSCCTRL_XOSCCTRL_ONDEMAND(value) (OSCCTRL_XOSCCTRL_ONDEMAND_Msk & ((value) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos))
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos _U_(8) /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Position */
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) /**< (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable Mask */
#define OSCCTRL_XOSCCTRL_LOWBUFGAIN(value) (OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos))
#define OSCCTRL_XOSCCTRL_IPTAT_Pos _U_(9) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Position */
#define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Reference Mask */
#define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
#define OSCCTRL_XOSCCTRL_IMULT_Pos _U_(11) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Position */
#define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos) /**< (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier Mask */
#define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
#define OSCCTRL_XOSCCTRL_ENALC_Pos _U_(15) /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Position */
#define OSCCTRL_XOSCCTRL_ENALC_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos) /**< (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable Mask */
#define OSCCTRL_XOSCCTRL_ENALC(value) (OSCCTRL_XOSCCTRL_ENALC_Msk & ((value) << OSCCTRL_XOSCCTRL_ENALC_Pos))
#define OSCCTRL_XOSCCTRL_CFDEN_Pos _U_(16) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Position */
#define OSCCTRL_XOSCCTRL_CFDEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable Mask */
#define OSCCTRL_XOSCCTRL_CFDEN(value) (OSCCTRL_XOSCCTRL_CFDEN_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDEN_Pos))
#define OSCCTRL_XOSCCTRL_SWBEN_Pos _U_(17) /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Position */
#define OSCCTRL_XOSCCTRL_SWBEN_Msk (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos) /**< (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable Mask */
#define OSCCTRL_XOSCCTRL_SWBEN(value) (OSCCTRL_XOSCCTRL_SWBEN_Msk & ((value) << OSCCTRL_XOSCCTRL_SWBEN_Pos))
#define OSCCTRL_XOSCCTRL_STARTUP_Pos _U_(20) /**< (OSCCTRL_XOSCCTRL) Start-Up Time Position */
#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) Start-Up Time Mask */
#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val _U_(0x0) /**< (OSCCTRL_XOSCCTRL) 31 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val _U_(0x1) /**< (OSCCTRL_XOSCCTRL) 61 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val _U_(0x2) /**< (OSCCTRL_XOSCCTRL) 122 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val _U_(0x3) /**< (OSCCTRL_XOSCCTRL) 244 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val _U_(0x4) /**< (OSCCTRL_XOSCCTRL) 488 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val _U_(0x5) /**< (OSCCTRL_XOSCCTRL) 977 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val _U_(0x6) /**< (OSCCTRL_XOSCCTRL) 1953 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val _U_(0x7) /**< (OSCCTRL_XOSCCTRL) 3906 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val _U_(0x8) /**< (OSCCTRL_XOSCCTRL) 7813 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val _U_(0x9) /**< (OSCCTRL_XOSCCTRL) 15625 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val _U_(0xA) /**< (OSCCTRL_XOSCCTRL) 31250 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val _U_(0xB) /**< (OSCCTRL_XOSCCTRL) 62500 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val _U_(0xC) /**< (OSCCTRL_XOSCCTRL) 125000 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val _U_(0xD) /**< (OSCCTRL_XOSCCTRL) 250000 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val _U_(0xE) /**< (OSCCTRL_XOSCCTRL) 500000 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val _U_(0xF) /**< (OSCCTRL_XOSCCTRL) 1000000 us */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 61 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 122 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 244 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 488 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 977 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE64 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE64_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1953 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE128 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE128_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 3906 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE256 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE256_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 7813 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE512 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE512_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 15625 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 31250 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 62500 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 125000 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 250000 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 500000 us Position */
#define OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768 (OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768_Val << OSCCTRL_XOSCCTRL_STARTUP_Pos) /**< (OSCCTRL_XOSCCTRL) 1000000 us Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_Pos _U_(24) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler Mask */
#define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val _U_(0x0) /**< (OSCCTRL_XOSCCTRL) 48 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val _U_(0x1) /**< (OSCCTRL_XOSCCTRL) 24 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val _U_(0x2) /**< (OSCCTRL_XOSCCTRL) 12 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val _U_(0x3) /**< (OSCCTRL_XOSCCTRL) 6 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val _U_(0x4) /**< (OSCCTRL_XOSCCTRL) 3 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val _U_(0x5) /**< (OSCCTRL_XOSCCTRL) 1.5 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val _U_(0x6) /**< (OSCCTRL_XOSCCTRL) 0.75 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val _U_(0x7) /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV1 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV1_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 48 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV2 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV2_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 24 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV4 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV4_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 12 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV8 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV8_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 6 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV16 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV16_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 3 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV32 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV32_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 1.5 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV64 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV64_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.75 MHz Position */
#define OSCCTRL_XOSCCTRL_CFDPRESC_DIV128 (OSCCTRL_XOSCCTRL_CFDPRESC_DIV128_Val << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) /**< (OSCCTRL_XOSCCTRL) 0.3125 MHz Position */
#define OSCCTRL_XOSCCTRL_Msk _U_(0x0FF3FFC6) /**< (OSCCTRL_XOSCCTRL) Register Mask */
/* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
#define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< (OSCCTRL_DFLLCTRLA) DFLL48M Control A Reset Value */
#define OSCCTRL_DFLLCTRLA_ENABLE_Pos _U_(1) /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Position */
#define OSCCTRL_DFLLCTRLA_ENABLE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos) /**< (OSCCTRL_DFLLCTRLA) DFLL Enable Mask */
#define OSCCTRL_DFLLCTRLA_ENABLE(value) (OSCCTRL_DFLLCTRLA_ENABLE_Msk & ((value) << OSCCTRL_DFLLCTRLA_ENABLE_Pos))
#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos _U_(6) /**< (OSCCTRL_DFLLCTRLA) Run in Standby Position */
#define OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) /**< (OSCCTRL_DFLLCTRLA) Run in Standby Mask */
#define OSCCTRL_DFLLCTRLA_RUNSTDBY(value) (OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk & ((value) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos))
#define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos _U_(7) /**< (OSCCTRL_DFLLCTRLA) On Demand Control Position */
#define OSCCTRL_DFLLCTRLA_ONDEMAND_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos) /**< (OSCCTRL_DFLLCTRLA) On Demand Control Mask */
#define OSCCTRL_DFLLCTRLA_ONDEMAND(value) (OSCCTRL_DFLLCTRLA_ONDEMAND_Msk & ((value) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos))
#define OSCCTRL_DFLLCTRLA_Msk _U_(0xC2) /**< (OSCCTRL_DFLLCTRLA) Register Mask */
/* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
#define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLCTRLB) DFLL48M Control B Reset Value */
#define OSCCTRL_DFLLCTRLB_MODE_Pos _U_(0) /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Position */
#define OSCCTRL_DFLLCTRLB_MODE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos) /**< (OSCCTRL_DFLLCTRLB) Operating Mode Selection Mask */
#define OSCCTRL_DFLLCTRLB_MODE(value) (OSCCTRL_DFLLCTRLB_MODE_Msk & ((value) << OSCCTRL_DFLLCTRLB_MODE_Pos))
#define OSCCTRL_DFLLCTRLB_STABLE_Pos _U_(1) /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Position */
#define OSCCTRL_DFLLCTRLB_STABLE_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos) /**< (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency Mask */
#define OSCCTRL_DFLLCTRLB_STABLE(value) (OSCCTRL_DFLLCTRLB_STABLE_Msk & ((value) << OSCCTRL_DFLLCTRLB_STABLE_Pos))
#define OSCCTRL_DFLLCTRLB_LLAW_Pos _U_(2) /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Position */
#define OSCCTRL_DFLLCTRLB_LLAW_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos) /**< (OSCCTRL_DFLLCTRLB) Lose Lock After Wake Mask */
#define OSCCTRL_DFLLCTRLB_LLAW(value) (OSCCTRL_DFLLCTRLB_LLAW_Msk & ((value) << OSCCTRL_DFLLCTRLB_LLAW_Pos))
#define OSCCTRL_DFLLCTRLB_USBCRM_Pos _U_(3) /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Position */
#define OSCCTRL_DFLLCTRLB_USBCRM_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos) /**< (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode Mask */
#define OSCCTRL_DFLLCTRLB_USBCRM(value) (OSCCTRL_DFLLCTRLB_USBCRM_Msk & ((value) << OSCCTRL_DFLLCTRLB_USBCRM_Pos))
#define OSCCTRL_DFLLCTRLB_CCDIS_Pos _U_(4) /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Position */
#define OSCCTRL_DFLLCTRLB_CCDIS_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos) /**< (OSCCTRL_DFLLCTRLB) Chill Cycle Disable Mask */
#define OSCCTRL_DFLLCTRLB_CCDIS(value) (OSCCTRL_DFLLCTRLB_CCDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_CCDIS_Pos))
#define OSCCTRL_DFLLCTRLB_QLDIS_Pos _U_(5) /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Position */
#define OSCCTRL_DFLLCTRLB_QLDIS_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos) /**< (OSCCTRL_DFLLCTRLB) Quick Lock Disable Mask */
#define OSCCTRL_DFLLCTRLB_QLDIS(value) (OSCCTRL_DFLLCTRLB_QLDIS_Msk & ((value) << OSCCTRL_DFLLCTRLB_QLDIS_Pos))
#define OSCCTRL_DFLLCTRLB_BPLCKC_Pos _U_(6) /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Position */
#define OSCCTRL_DFLLCTRLB_BPLCKC_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) /**< (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock Mask */
#define OSCCTRL_DFLLCTRLB_BPLCKC(value) (OSCCTRL_DFLLCTRLB_BPLCKC_Msk & ((value) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos))
#define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos _U_(7) /**< (OSCCTRL_DFLLCTRLB) Wait Lock Position */
#define OSCCTRL_DFLLCTRLB_WAITLOCK_Msk (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) /**< (OSCCTRL_DFLLCTRLB) Wait Lock Mask */
#define OSCCTRL_DFLLCTRLB_WAITLOCK(value) (OSCCTRL_DFLLCTRLB_WAITLOCK_Msk & ((value) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos))
#define OSCCTRL_DFLLCTRLB_Msk _U_(0xFF) /**< (OSCCTRL_DFLLCTRLB) Register Mask */
/* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
#define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLVAL) DFLL48M Value Reset Value */
#define OSCCTRL_DFLLVAL_FINE_Pos _U_(0) /**< (OSCCTRL_DFLLVAL) Fine Value Position */
#define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos) /**< (OSCCTRL_DFLLVAL) Fine Value Mask */
#define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
#define OSCCTRL_DFLLVAL_COARSE_Pos _U_(10) /**< (OSCCTRL_DFLLVAL) Coarse Value Position */
#define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) /**< (OSCCTRL_DFLLVAL) Coarse Value Mask */
#define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
#define OSCCTRL_DFLLVAL_DIFF_Pos _U_(16) /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Position */
#define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) /**< (OSCCTRL_DFLLVAL) Multiplication Ratio Difference Mask */
#define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
#define OSCCTRL_DFLLVAL_Msk _U_(0xFFFFFCFF) /**< (OSCCTRL_DFLLVAL) Register Mask */
/* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
#define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLMUL) DFLL48M Multiplier Reset Value */
#define OSCCTRL_DFLLMUL_MUL_Pos _U_(0) /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Position */
#define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) /**< (OSCCTRL_DFLLMUL) DFLL Multiply Factor Mask */
#define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
#define OSCCTRL_DFLLMUL_FSTEP_Pos _U_(16) /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Position */
#define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos) /**< (OSCCTRL_DFLLMUL) Fine Maximum Step Mask */
#define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
#define OSCCTRL_DFLLMUL_CSTEP_Pos _U_(26) /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Position */
#define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) /**< (OSCCTRL_DFLLMUL) Coarse Maximum Step Mask */
#define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
#define OSCCTRL_DFLLMUL_Msk _U_(0xFCFFFFFF) /**< (OSCCTRL_DFLLMUL) Register Mask */
/* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
#define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Reset Value */
#define OSCCTRL_DFLLSYNC_ENABLE_Pos _U_(1) /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Position */
#define OSCCTRL_DFLLSYNC_ENABLE_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos) /**< (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy Mask */
#define OSCCTRL_DFLLSYNC_ENABLE(value) (OSCCTRL_DFLLSYNC_ENABLE_Msk & ((value) << OSCCTRL_DFLLSYNC_ENABLE_Pos))
#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos _U_(2) /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Position */
#define OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy Mask */
#define OSCCTRL_DFLLSYNC_DFLLCTRLB(value) (OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos))
#define OSCCTRL_DFLLSYNC_DFLLVAL_Pos _U_(3) /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Position */
#define OSCCTRL_DFLLSYNC_DFLLVAL_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy Mask */
#define OSCCTRL_DFLLSYNC_DFLLVAL(value) (OSCCTRL_DFLLSYNC_DFLLVAL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos))
#define OSCCTRL_DFLLSYNC_DFLLMUL_Pos _U_(4) /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Position */
#define OSCCTRL_DFLLSYNC_DFLLMUL_Msk (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos) /**< (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy Mask */
#define OSCCTRL_DFLLSYNC_DFLLMUL(value) (OSCCTRL_DFLLSYNC_DFLLMUL_Msk & ((value) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos))
#define OSCCTRL_DFLLSYNC_Msk _U_(0x1E) /**< (OSCCTRL_DFLLSYNC) Register Mask */
/** \brief OSCCTRL register offsets definitions */
#define OSCCTRL_DPLLCTRLA_REG_OFST (0x00) /**< (OSCCTRL_DPLLCTRLA) DPLL Control A Offset */
#define OSCCTRL_DPLLRATIO_REG_OFST (0x04) /**< (OSCCTRL_DPLLRATIO) DPLL Ratio Control Offset */
#define OSCCTRL_DPLLCTRLB_REG_OFST (0x08) /**< (OSCCTRL_DPLLCTRLB) DPLL Control B Offset */
#define OSCCTRL_DPLLSYNCBUSY_REG_OFST (0x0C) /**< (OSCCTRL_DPLLSYNCBUSY) DPLL Synchronization Busy Offset */
#define OSCCTRL_DPLLSTATUS_REG_OFST (0x10) /**< (OSCCTRL_DPLLSTATUS) DPLL Status Offset */
#define OSCCTRL_EVCTRL_REG_OFST (0x00) /**< (OSCCTRL_EVCTRL) Event Control Offset */
#define OSCCTRL_INTENCLR_REG_OFST (0x04) /**< (OSCCTRL_INTENCLR) Interrupt Enable Clear Offset */
#define OSCCTRL_INTENSET_REG_OFST (0x08) /**< (OSCCTRL_INTENSET) Interrupt Enable Set Offset */
#define OSCCTRL_INTFLAG_REG_OFST (0x0C) /**< (OSCCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
#define OSCCTRL_STATUS_REG_OFST (0x10) /**< (OSCCTRL_STATUS) Status Offset */
#define OSCCTRL_XOSCCTRL_REG_OFST (0x14) /**< (OSCCTRL_XOSCCTRL) External Multipurpose Crystal Oscillator Control Offset */
#define OSCCTRL_DFLLCTRLA_REG_OFST (0x1C) /**< (OSCCTRL_DFLLCTRLA) DFLL48M Control A Offset */
#define OSCCTRL_DFLLCTRLB_REG_OFST (0x20) /**< (OSCCTRL_DFLLCTRLB) DFLL48M Control B Offset */
#define OSCCTRL_DFLLVAL_REG_OFST (0x24) /**< (OSCCTRL_DFLLVAL) DFLL48M Value Offset */
#define OSCCTRL_DFLLMUL_REG_OFST (0x28) /**< (OSCCTRL_DFLLMUL) DFLL48M Multiplier Offset */
#define OSCCTRL_DFLLSYNC_REG_OFST (0x2C) /**< (OSCCTRL_DFLLSYNC) DFLL48M Synchronization Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief DPLL register API structure */
typedef struct
{
__IO uint8_t OSCCTRL_DPLLCTRLA; /**< Offset: 0x00 (R/W 8) DPLL Control A */
__I uint8_t Reserved1[0x03];
__IO uint32_t OSCCTRL_DPLLRATIO; /**< Offset: 0x04 (R/W 32) DPLL Ratio Control */
__IO uint32_t OSCCTRL_DPLLCTRLB; /**< Offset: 0x08 (R/W 32) DPLL Control B */
__I uint32_t OSCCTRL_DPLLSYNCBUSY; /**< Offset: 0x0C (R/ 32) DPLL Synchronization Busy */
__I uint32_t OSCCTRL_DPLLSTATUS; /**< Offset: 0x10 (R/ 32) DPLL Status */
} oscctrl_dpll_registers_t;
#define OSCCTRL_DPLL_NUMBER _U_(2)
/** \brief OSCCTRL register API structure */
typedef struct
{ /* Oscillators Control */
__IO uint8_t OSCCTRL_EVCTRL; /**< Offset: 0x00 (R/W 8) Event Control */
__I uint8_t Reserved1[0x03];
__IO uint32_t OSCCTRL_INTENCLR; /**< Offset: 0x04 (R/W 32) Interrupt Enable Clear */
__IO uint32_t OSCCTRL_INTENSET; /**< Offset: 0x08 (R/W 32) Interrupt Enable Set */
__IO uint32_t OSCCTRL_INTFLAG; /**< Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */
__I uint32_t OSCCTRL_STATUS; /**< Offset: 0x10 (R/ 32) Status */
__IO uint32_t OSCCTRL_XOSCCTRL[2]; /**< Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */
__IO uint8_t OSCCTRL_DFLLCTRLA; /**< Offset: 0x1C (R/W 8) DFLL48M Control A */
__I uint8_t Reserved2[0x03];
__IO uint8_t OSCCTRL_DFLLCTRLB; /**< Offset: 0x20 (R/W 8) DFLL48M Control B */
__I uint8_t Reserved3[0x03];
__IO uint32_t OSCCTRL_DFLLVAL; /**< Offset: 0x24 (R/W 32) DFLL48M Value */
__IO uint32_t OSCCTRL_DFLLMUL; /**< Offset: 0x28 (R/W 32) DFLL48M Multiplier */
__IO uint8_t OSCCTRL_DFLLSYNC; /**< Offset: 0x2C (R/W 8) DFLL48M Synchronization */
__I uint8_t Reserved4[0x03];
oscctrl_dpll_registers_t DPLL[OSCCTRL_DPLL_NUMBER]; /**< Offset: 0x30 */
} oscctrl_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_OSCCTRL_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/pac.h
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/**
* \brief Component description for PAC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PAC_COMPONENT_H_
#define _SAMD51_PAC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PAC */
/* ************************************************************************** */
/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
#define PAC_WRCTRL_RESETVALUE _U_(0x00) /**< (PAC_WRCTRL) Write control Reset Value */
#define PAC_WRCTRL_PERID_Pos _U_(0) /**< (PAC_WRCTRL) Peripheral identifier Position */
#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos) /**< (PAC_WRCTRL) Peripheral identifier Mask */
#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
#define PAC_WRCTRL_KEY_Pos _U_(16) /**< (PAC_WRCTRL) Peripheral access control key Position */
#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos) /**< (PAC_WRCTRL) Peripheral access control key Mask */
#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< (PAC_WRCTRL) No action */
#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< (PAC_WRCTRL) Clear protection */
#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< (PAC_WRCTRL) Set protection */
#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< (PAC_WRCTRL) Set and lock protection */
#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) /**< (PAC_WRCTRL) No action Position */
#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) /**< (PAC_WRCTRL) Clear protection Position */
#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) /**< (PAC_WRCTRL) Set protection Position */
#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) /**< (PAC_WRCTRL) Set and lock protection Position */
#define PAC_WRCTRL_Msk _U_(0x00FFFFFF) /**< (PAC_WRCTRL) Register Mask */
/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< (PAC_EVCTRL) Event control Reset Value */
#define PAC_EVCTRL_ERREO_Pos _U_(0) /**< (PAC_EVCTRL) Peripheral acess error event output Position */
#define PAC_EVCTRL_ERREO_Msk (_U_(0x1) << PAC_EVCTRL_ERREO_Pos) /**< (PAC_EVCTRL) Peripheral acess error event output Mask */
#define PAC_EVCTRL_ERREO(value) (PAC_EVCTRL_ERREO_Msk & ((value) << PAC_EVCTRL_ERREO_Pos))
#define PAC_EVCTRL_Msk _U_(0x01) /**< (PAC_EVCTRL) Register Mask */
/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< (PAC_INTENCLR) Interrupt enable clear Reset Value */
#define PAC_INTENCLR_ERR_Pos _U_(0) /**< (PAC_INTENCLR) Peripheral access error interrupt disable Position */
#define PAC_INTENCLR_ERR_Msk (_U_(0x1) << PAC_INTENCLR_ERR_Pos) /**< (PAC_INTENCLR) Peripheral access error interrupt disable Mask */
#define PAC_INTENCLR_ERR(value) (PAC_INTENCLR_ERR_Msk & ((value) << PAC_INTENCLR_ERR_Pos))
#define PAC_INTENCLR_Msk _U_(0x01) /**< (PAC_INTENCLR) Register Mask */
/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< (PAC_INTENSET) Interrupt enable set Reset Value */
#define PAC_INTENSET_ERR_Pos _U_(0) /**< (PAC_INTENSET) Peripheral access error interrupt enable Position */
#define PAC_INTENSET_ERR_Msk (_U_(0x1) << PAC_INTENSET_ERR_Pos) /**< (PAC_INTENSET) Peripheral access error interrupt enable Mask */
#define PAC_INTENSET_ERR(value) (PAC_INTENSET_ERR_Msk & ((value) << PAC_INTENSET_ERR_Pos))
#define PAC_INTENSET_Msk _U_(0x01) /**< (PAC_INTENSET) Register Mask */
/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00) /**< (PAC_INTFLAGAHB) Bridge interrupt flag status Reset Value */
#define PAC_INTFLAGAHB_FLASH_Pos _U_(0) /**< (PAC_INTFLAGAHB) FLASH Position */
#define PAC_INTFLAGAHB_FLASH_Msk (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) /**< (PAC_INTFLAGAHB) FLASH Mask */
#define PAC_INTFLAGAHB_FLASH(value) (PAC_INTFLAGAHB_FLASH_Msk & ((value) << PAC_INTFLAGAHB_FLASH_Pos))
#define PAC_INTFLAGAHB_FLASH_ALT_Pos _U_(1) /**< (PAC_INTFLAGAHB) FLASH_ALT Position */
#define PAC_INTFLAGAHB_FLASH_ALT_Msk (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos) /**< (PAC_INTFLAGAHB) FLASH_ALT Mask */
#define PAC_INTFLAGAHB_FLASH_ALT(value) (PAC_INTFLAGAHB_FLASH_ALT_Msk & ((value) << PAC_INTFLAGAHB_FLASH_ALT_Pos))
#define PAC_INTFLAGAHB_SEEPROM_Pos _U_(2) /**< (PAC_INTFLAGAHB) SEEPROM Position */
#define PAC_INTFLAGAHB_SEEPROM_Msk (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos) /**< (PAC_INTFLAGAHB) SEEPROM Mask */
#define PAC_INTFLAGAHB_SEEPROM(value) (PAC_INTFLAGAHB_SEEPROM_Msk & ((value) << PAC_INTFLAGAHB_SEEPROM_Pos))
#define PAC_INTFLAGAHB_RAMCM4S_Pos _U_(3) /**< (PAC_INTFLAGAHB) RAMCM4S Position */
#define PAC_INTFLAGAHB_RAMCM4S_Msk (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos) /**< (PAC_INTFLAGAHB) RAMCM4S Mask */
#define PAC_INTFLAGAHB_RAMCM4S(value) (PAC_INTFLAGAHB_RAMCM4S_Msk & ((value) << PAC_INTFLAGAHB_RAMCM4S_Pos))
#define PAC_INTFLAGAHB_RAMPPPDSU_Pos _U_(4) /**< (PAC_INTFLAGAHB) RAMPPPDSU Position */
#define PAC_INTFLAGAHB_RAMPPPDSU_Msk (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos) /**< (PAC_INTFLAGAHB) RAMPPPDSU Mask */
#define PAC_INTFLAGAHB_RAMPPPDSU(value) (PAC_INTFLAGAHB_RAMPPPDSU_Msk & ((value) << PAC_INTFLAGAHB_RAMPPPDSU_Pos))
#define PAC_INTFLAGAHB_RAMDMAWR_Pos _U_(5) /**< (PAC_INTFLAGAHB) RAMDMAWR Position */
#define PAC_INTFLAGAHB_RAMDMAWR_Msk (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos) /**< (PAC_INTFLAGAHB) RAMDMAWR Mask */
#define PAC_INTFLAGAHB_RAMDMAWR(value) (PAC_INTFLAGAHB_RAMDMAWR_Msk & ((value) << PAC_INTFLAGAHB_RAMDMAWR_Pos))
#define PAC_INTFLAGAHB_RAMDMACICM_Pos _U_(6) /**< (PAC_INTFLAGAHB) RAMDMACICM Position */
#define PAC_INTFLAGAHB_RAMDMACICM_Msk (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos) /**< (PAC_INTFLAGAHB) RAMDMACICM Mask */
#define PAC_INTFLAGAHB_RAMDMACICM(value) (PAC_INTFLAGAHB_RAMDMACICM_Msk & ((value) << PAC_INTFLAGAHB_RAMDMACICM_Pos))
#define PAC_INTFLAGAHB_HPB0_Pos _U_(7) /**< (PAC_INTFLAGAHB) HPB0 Position */
#define PAC_INTFLAGAHB_HPB0_Msk (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) /**< (PAC_INTFLAGAHB) HPB0 Mask */
#define PAC_INTFLAGAHB_HPB0(value) (PAC_INTFLAGAHB_HPB0_Msk & ((value) << PAC_INTFLAGAHB_HPB0_Pos))
#define PAC_INTFLAGAHB_HPB1_Pos _U_(8) /**< (PAC_INTFLAGAHB) HPB1 Position */
#define PAC_INTFLAGAHB_HPB1_Msk (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) /**< (PAC_INTFLAGAHB) HPB1 Mask */
#define PAC_INTFLAGAHB_HPB1(value) (PAC_INTFLAGAHB_HPB1_Msk & ((value) << PAC_INTFLAGAHB_HPB1_Pos))
#define PAC_INTFLAGAHB_HPB2_Pos _U_(9) /**< (PAC_INTFLAGAHB) HPB2 Position */
#define PAC_INTFLAGAHB_HPB2_Msk (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) /**< (PAC_INTFLAGAHB) HPB2 Mask */
#define PAC_INTFLAGAHB_HPB2(value) (PAC_INTFLAGAHB_HPB2_Msk & ((value) << PAC_INTFLAGAHB_HPB2_Pos))
#define PAC_INTFLAGAHB_HPB3_Pos _U_(10) /**< (PAC_INTFLAGAHB) HPB3 Position */
#define PAC_INTFLAGAHB_HPB3_Msk (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos) /**< (PAC_INTFLAGAHB) HPB3 Mask */
#define PAC_INTFLAGAHB_HPB3(value) (PAC_INTFLAGAHB_HPB3_Msk & ((value) << PAC_INTFLAGAHB_HPB3_Pos))
#define PAC_INTFLAGAHB_PUKCC_Pos _U_(11) /**< (PAC_INTFLAGAHB) PUKCC Position */
#define PAC_INTFLAGAHB_PUKCC_Msk (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos) /**< (PAC_INTFLAGAHB) PUKCC Mask */
#define PAC_INTFLAGAHB_PUKCC(value) (PAC_INTFLAGAHB_PUKCC_Msk & ((value) << PAC_INTFLAGAHB_PUKCC_Pos))
#define PAC_INTFLAGAHB_SDHC0_Pos _U_(12) /**< (PAC_INTFLAGAHB) SDHC0 Position */
#define PAC_INTFLAGAHB_SDHC0_Msk (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos) /**< (PAC_INTFLAGAHB) SDHC0 Mask */
#define PAC_INTFLAGAHB_SDHC0(value) (PAC_INTFLAGAHB_SDHC0_Msk & ((value) << PAC_INTFLAGAHB_SDHC0_Pos))
#define PAC_INTFLAGAHB_SDHC1_Pos _U_(13) /**< (PAC_INTFLAGAHB) SDHC1 Position */
#define PAC_INTFLAGAHB_SDHC1_Msk (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos) /**< (PAC_INTFLAGAHB) SDHC1 Mask */
#define PAC_INTFLAGAHB_SDHC1(value) (PAC_INTFLAGAHB_SDHC1_Msk & ((value) << PAC_INTFLAGAHB_SDHC1_Pos))
#define PAC_INTFLAGAHB_QSPI_Pos _U_(14) /**< (PAC_INTFLAGAHB) QSPI Position */
#define PAC_INTFLAGAHB_QSPI_Msk (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos) /**< (PAC_INTFLAGAHB) QSPI Mask */
#define PAC_INTFLAGAHB_QSPI(value) (PAC_INTFLAGAHB_QSPI_Msk & ((value) << PAC_INTFLAGAHB_QSPI_Pos))
#define PAC_INTFLAGAHB_BKUPRAM_Pos _U_(15) /**< (PAC_INTFLAGAHB) BKUPRAM Position */
#define PAC_INTFLAGAHB_BKUPRAM_Msk (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos) /**< (PAC_INTFLAGAHB) BKUPRAM Mask */
#define PAC_INTFLAGAHB_BKUPRAM(value) (PAC_INTFLAGAHB_BKUPRAM_Msk & ((value) << PAC_INTFLAGAHB_BKUPRAM_Pos))
#define PAC_INTFLAGAHB_Msk _U_(0x0000FFFF) /**< (PAC_INTFLAGAHB) Register Mask */
#define PAC_INTFLAGAHB_HPB_Pos _U_(7) /**< (PAC_INTFLAGAHB Position) HPBx */
#define PAC_INTFLAGAHB_HPB_Msk (_U_(0xF) << PAC_INTFLAGAHB_HPB_Pos) /**< (PAC_INTFLAGAHB Mask) HPB */
#define PAC_INTFLAGAHB_HPB(value) (PAC_INTFLAGAHB_HPB_Msk & ((value) << PAC_INTFLAGAHB_HPB_Pos))
#define PAC_INTFLAGAHB_SDHC_Pos _U_(12) /**< (PAC_INTFLAGAHB Position) SDHCx */
#define PAC_INTFLAGAHB_SDHC_Msk (_U_(0x3) << PAC_INTFLAGAHB_SDHC_Pos) /**< (PAC_INTFLAGAHB Mask) SDHC */
#define PAC_INTFLAGAHB_SDHC(value) (PAC_INTFLAGAHB_SDHC_Msk & ((value) << PAC_INTFLAGAHB_SDHC_Pos))
/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
#define PAC_INTFLAGA_RESETVALUE _U_(0x00) /**< (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A Reset Value */
#define PAC_INTFLAGA_PAC_Pos _U_(0) /**< (PAC_INTFLAGA) PAC Position */
#define PAC_INTFLAGA_PAC_Msk (_U_(0x1) << PAC_INTFLAGA_PAC_Pos) /**< (PAC_INTFLAGA) PAC Mask */
#define PAC_INTFLAGA_PAC(value) (PAC_INTFLAGA_PAC_Msk & ((value) << PAC_INTFLAGA_PAC_Pos))
#define PAC_INTFLAGA_PM_Pos _U_(1) /**< (PAC_INTFLAGA) PM Position */
#define PAC_INTFLAGA_PM_Msk (_U_(0x1) << PAC_INTFLAGA_PM_Pos) /**< (PAC_INTFLAGA) PM Mask */
#define PAC_INTFLAGA_PM(value) (PAC_INTFLAGA_PM_Msk & ((value) << PAC_INTFLAGA_PM_Pos))
#define PAC_INTFLAGA_MCLK_Pos _U_(2) /**< (PAC_INTFLAGA) MCLK Position */
#define PAC_INTFLAGA_MCLK_Msk (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos) /**< (PAC_INTFLAGA) MCLK Mask */
#define PAC_INTFLAGA_MCLK(value) (PAC_INTFLAGA_MCLK_Msk & ((value) << PAC_INTFLAGA_MCLK_Pos))
#define PAC_INTFLAGA_RSTC_Pos _U_(3) /**< (PAC_INTFLAGA) RSTC Position */
#define PAC_INTFLAGA_RSTC_Msk (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos) /**< (PAC_INTFLAGA) RSTC Mask */
#define PAC_INTFLAGA_RSTC(value) (PAC_INTFLAGA_RSTC_Msk & ((value) << PAC_INTFLAGA_RSTC_Pos))
#define PAC_INTFLAGA_OSCCTRL_Pos _U_(4) /**< (PAC_INTFLAGA) OSCCTRL Position */
#define PAC_INTFLAGA_OSCCTRL_Msk (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) /**< (PAC_INTFLAGA) OSCCTRL Mask */
#define PAC_INTFLAGA_OSCCTRL(value) (PAC_INTFLAGA_OSCCTRL_Msk & ((value) << PAC_INTFLAGA_OSCCTRL_Pos))
#define PAC_INTFLAGA_OSC32KCTRL_Pos _U_(5) /**< (PAC_INTFLAGA) OSC32KCTRL Position */
#define PAC_INTFLAGA_OSC32KCTRL_Msk (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) /**< (PAC_INTFLAGA) OSC32KCTRL Mask */
#define PAC_INTFLAGA_OSC32KCTRL(value) (PAC_INTFLAGA_OSC32KCTRL_Msk & ((value) << PAC_INTFLAGA_OSC32KCTRL_Pos))
#define PAC_INTFLAGA_SUPC_Pos _U_(6) /**< (PAC_INTFLAGA) SUPC Position */
#define PAC_INTFLAGA_SUPC_Msk (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos) /**< (PAC_INTFLAGA) SUPC Mask */
#define PAC_INTFLAGA_SUPC(value) (PAC_INTFLAGA_SUPC_Msk & ((value) << PAC_INTFLAGA_SUPC_Pos))
#define PAC_INTFLAGA_GCLK_Pos _U_(7) /**< (PAC_INTFLAGA) GCLK Position */
#define PAC_INTFLAGA_GCLK_Msk (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos) /**< (PAC_INTFLAGA) GCLK Mask */
#define PAC_INTFLAGA_GCLK(value) (PAC_INTFLAGA_GCLK_Msk & ((value) << PAC_INTFLAGA_GCLK_Pos))
#define PAC_INTFLAGA_WDT_Pos _U_(8) /**< (PAC_INTFLAGA) WDT Position */
#define PAC_INTFLAGA_WDT_Msk (_U_(0x1) << PAC_INTFLAGA_WDT_Pos) /**< (PAC_INTFLAGA) WDT Mask */
#define PAC_INTFLAGA_WDT(value) (PAC_INTFLAGA_WDT_Msk & ((value) << PAC_INTFLAGA_WDT_Pos))
#define PAC_INTFLAGA_RTC_Pos _U_(9) /**< (PAC_INTFLAGA) RTC Position */
#define PAC_INTFLAGA_RTC_Msk (_U_(0x1) << PAC_INTFLAGA_RTC_Pos) /**< (PAC_INTFLAGA) RTC Mask */
#define PAC_INTFLAGA_RTC(value) (PAC_INTFLAGA_RTC_Msk & ((value) << PAC_INTFLAGA_RTC_Pos))
#define PAC_INTFLAGA_EIC_Pos _U_(10) /**< (PAC_INTFLAGA) EIC Position */
#define PAC_INTFLAGA_EIC_Msk (_U_(0x1) << PAC_INTFLAGA_EIC_Pos) /**< (PAC_INTFLAGA) EIC Mask */
#define PAC_INTFLAGA_EIC(value) (PAC_INTFLAGA_EIC_Msk & ((value) << PAC_INTFLAGA_EIC_Pos))
#define PAC_INTFLAGA_FREQM_Pos _U_(11) /**< (PAC_INTFLAGA) FREQM Position */
#define PAC_INTFLAGA_FREQM_Msk (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos) /**< (PAC_INTFLAGA) FREQM Mask */
#define PAC_INTFLAGA_FREQM(value) (PAC_INTFLAGA_FREQM_Msk & ((value) << PAC_INTFLAGA_FREQM_Pos))
#define PAC_INTFLAGA_SERCOM0_Pos _U_(12) /**< (PAC_INTFLAGA) SERCOM0 Position */
#define PAC_INTFLAGA_SERCOM0_Msk (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos) /**< (PAC_INTFLAGA) SERCOM0 Mask */
#define PAC_INTFLAGA_SERCOM0(value) (PAC_INTFLAGA_SERCOM0_Msk & ((value) << PAC_INTFLAGA_SERCOM0_Pos))
#define PAC_INTFLAGA_SERCOM1_Pos _U_(13) /**< (PAC_INTFLAGA) SERCOM1 Position */
#define PAC_INTFLAGA_SERCOM1_Msk (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos) /**< (PAC_INTFLAGA) SERCOM1 Mask */
#define PAC_INTFLAGA_SERCOM1(value) (PAC_INTFLAGA_SERCOM1_Msk & ((value) << PAC_INTFLAGA_SERCOM1_Pos))
#define PAC_INTFLAGA_TC0_Pos _U_(14) /**< (PAC_INTFLAGA) TC0 Position */
#define PAC_INTFLAGA_TC0_Msk (_U_(0x1) << PAC_INTFLAGA_TC0_Pos) /**< (PAC_INTFLAGA) TC0 Mask */
#define PAC_INTFLAGA_TC0(value) (PAC_INTFLAGA_TC0_Msk & ((value) << PAC_INTFLAGA_TC0_Pos))
#define PAC_INTFLAGA_TC1_Pos _U_(15) /**< (PAC_INTFLAGA) TC1 Position */
#define PAC_INTFLAGA_TC1_Msk (_U_(0x1) << PAC_INTFLAGA_TC1_Pos) /**< (PAC_INTFLAGA) TC1 Mask */
#define PAC_INTFLAGA_TC1(value) (PAC_INTFLAGA_TC1_Msk & ((value) << PAC_INTFLAGA_TC1_Pos))
#define PAC_INTFLAGA_Msk _U_(0x0000FFFF) /**< (PAC_INTFLAGA) Register Mask */
#define PAC_INTFLAGA_SERCOM_Pos _U_(12) /**< (PAC_INTFLAGA Position) SERCOMx */
#define PAC_INTFLAGA_SERCOM_Msk (_U_(0x3) << PAC_INTFLAGA_SERCOM_Pos) /**< (PAC_INTFLAGA Mask) SERCOM */
#define PAC_INTFLAGA_SERCOM(value) (PAC_INTFLAGA_SERCOM_Msk & ((value) << PAC_INTFLAGA_SERCOM_Pos))
#define PAC_INTFLAGA_TC_Pos _U_(14) /**< (PAC_INTFLAGA Position) TCx */
#define PAC_INTFLAGA_TC_Msk (_U_(0x3) << PAC_INTFLAGA_TC_Pos) /**< (PAC_INTFLAGA Mask) TC */
#define PAC_INTFLAGA_TC(value) (PAC_INTFLAGA_TC_Msk & ((value) << PAC_INTFLAGA_TC_Pos))
/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
#define PAC_INTFLAGB_RESETVALUE _U_(0x00) /**< (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B Reset Value */
#define PAC_INTFLAGB_USB_Pos _U_(0) /**< (PAC_INTFLAGB) USB Position */
#define PAC_INTFLAGB_USB_Msk (_U_(0x1) << PAC_INTFLAGB_USB_Pos) /**< (PAC_INTFLAGB) USB Mask */
#define PAC_INTFLAGB_USB(value) (PAC_INTFLAGB_USB_Msk & ((value) << PAC_INTFLAGB_USB_Pos))
#define PAC_INTFLAGB_DSU_Pos _U_(1) /**< (PAC_INTFLAGB) DSU Position */
#define PAC_INTFLAGB_DSU_Msk (_U_(0x1) << PAC_INTFLAGB_DSU_Pos) /**< (PAC_INTFLAGB) DSU Mask */
#define PAC_INTFLAGB_DSU(value) (PAC_INTFLAGB_DSU_Msk & ((value) << PAC_INTFLAGB_DSU_Pos))
#define PAC_INTFLAGB_NVMCTRL_Pos _U_(2) /**< (PAC_INTFLAGB) NVMCTRL Position */
#define PAC_INTFLAGB_NVMCTRL_Msk (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) /**< (PAC_INTFLAGB) NVMCTRL Mask */
#define PAC_INTFLAGB_NVMCTRL(value) (PAC_INTFLAGB_NVMCTRL_Msk & ((value) << PAC_INTFLAGB_NVMCTRL_Pos))
#define PAC_INTFLAGB_CMCC_Pos _U_(3) /**< (PAC_INTFLAGB) CMCC Position */
#define PAC_INTFLAGB_CMCC_Msk (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos) /**< (PAC_INTFLAGB) CMCC Mask */
#define PAC_INTFLAGB_CMCC(value) (PAC_INTFLAGB_CMCC_Msk & ((value) << PAC_INTFLAGB_CMCC_Pos))
#define PAC_INTFLAGB_PORT_Pos _U_(4) /**< (PAC_INTFLAGB) PORT Position */
#define PAC_INTFLAGB_PORT_Msk (_U_(0x1) << PAC_INTFLAGB_PORT_Pos) /**< (PAC_INTFLAGB) PORT Mask */
#define PAC_INTFLAGB_PORT(value) (PAC_INTFLAGB_PORT_Msk & ((value) << PAC_INTFLAGB_PORT_Pos))
#define PAC_INTFLAGB_DMAC_Pos _U_(5) /**< (PAC_INTFLAGB) DMAC Position */
#define PAC_INTFLAGB_DMAC_Msk (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos) /**< (PAC_INTFLAGB) DMAC Mask */
#define PAC_INTFLAGB_DMAC(value) (PAC_INTFLAGB_DMAC_Msk & ((value) << PAC_INTFLAGB_DMAC_Pos))
#define PAC_INTFLAGB_HMATRIX_Pos _U_(6) /**< (PAC_INTFLAGB) HMATRIX Position */
#define PAC_INTFLAGB_HMATRIX_Msk (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos) /**< (PAC_INTFLAGB) HMATRIX Mask */
#define PAC_INTFLAGB_HMATRIX(value) (PAC_INTFLAGB_HMATRIX_Msk & ((value) << PAC_INTFLAGB_HMATRIX_Pos))
#define PAC_INTFLAGB_EVSYS_Pos _U_(7) /**< (PAC_INTFLAGB) EVSYS Position */
#define PAC_INTFLAGB_EVSYS_Msk (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos) /**< (PAC_INTFLAGB) EVSYS Mask */
#define PAC_INTFLAGB_EVSYS(value) (PAC_INTFLAGB_EVSYS_Msk & ((value) << PAC_INTFLAGB_EVSYS_Pos))
#define PAC_INTFLAGB_SERCOM2_Pos _U_(9) /**< (PAC_INTFLAGB) SERCOM2 Position */
#define PAC_INTFLAGB_SERCOM2_Msk (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos) /**< (PAC_INTFLAGB) SERCOM2 Mask */
#define PAC_INTFLAGB_SERCOM2(value) (PAC_INTFLAGB_SERCOM2_Msk & ((value) << PAC_INTFLAGB_SERCOM2_Pos))
#define PAC_INTFLAGB_SERCOM3_Pos _U_(10) /**< (PAC_INTFLAGB) SERCOM3 Position */
#define PAC_INTFLAGB_SERCOM3_Msk (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos) /**< (PAC_INTFLAGB) SERCOM3 Mask */
#define PAC_INTFLAGB_SERCOM3(value) (PAC_INTFLAGB_SERCOM3_Msk & ((value) << PAC_INTFLAGB_SERCOM3_Pos))
#define PAC_INTFLAGB_TCC0_Pos _U_(11) /**< (PAC_INTFLAGB) TCC0 Position */
#define PAC_INTFLAGB_TCC0_Msk (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos) /**< (PAC_INTFLAGB) TCC0 Mask */
#define PAC_INTFLAGB_TCC0(value) (PAC_INTFLAGB_TCC0_Msk & ((value) << PAC_INTFLAGB_TCC0_Pos))
#define PAC_INTFLAGB_TCC1_Pos _U_(12) /**< (PAC_INTFLAGB) TCC1 Position */
#define PAC_INTFLAGB_TCC1_Msk (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos) /**< (PAC_INTFLAGB) TCC1 Mask */
#define PAC_INTFLAGB_TCC1(value) (PAC_INTFLAGB_TCC1_Msk & ((value) << PAC_INTFLAGB_TCC1_Pos))
#define PAC_INTFLAGB_TC2_Pos _U_(13) /**< (PAC_INTFLAGB) TC2 Position */
#define PAC_INTFLAGB_TC2_Msk (_U_(0x1) << PAC_INTFLAGB_TC2_Pos) /**< (PAC_INTFLAGB) TC2 Mask */
#define PAC_INTFLAGB_TC2(value) (PAC_INTFLAGB_TC2_Msk & ((value) << PAC_INTFLAGB_TC2_Pos))
#define PAC_INTFLAGB_TC3_Pos _U_(14) /**< (PAC_INTFLAGB) TC3 Position */
#define PAC_INTFLAGB_TC3_Msk (_U_(0x1) << PAC_INTFLAGB_TC3_Pos) /**< (PAC_INTFLAGB) TC3 Mask */
#define PAC_INTFLAGB_TC3(value) (PAC_INTFLAGB_TC3_Msk & ((value) << PAC_INTFLAGB_TC3_Pos))
#define PAC_INTFLAGB_RAMECC_Pos _U_(16) /**< (PAC_INTFLAGB) RAMECC Position */
#define PAC_INTFLAGB_RAMECC_Msk (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos) /**< (PAC_INTFLAGB) RAMECC Mask */
#define PAC_INTFLAGB_RAMECC(value) (PAC_INTFLAGB_RAMECC_Msk & ((value) << PAC_INTFLAGB_RAMECC_Pos))
#define PAC_INTFLAGB_Msk _U_(0x00017EFF) /**< (PAC_INTFLAGB) Register Mask */
#define PAC_INTFLAGB_SERCOM_Pos _U_(9) /**< (PAC_INTFLAGB Position) SERCOM2 */
#define PAC_INTFLAGB_SERCOM_Msk (_U_(0x3) << PAC_INTFLAGB_SERCOM_Pos) /**< (PAC_INTFLAGB Mask) SERCOM */
#define PAC_INTFLAGB_SERCOM(value) (PAC_INTFLAGB_SERCOM_Msk & ((value) << PAC_INTFLAGB_SERCOM_Pos))
#define PAC_INTFLAGB_TCC_Pos _U_(11) /**< (PAC_INTFLAGB Position) TCCx */
#define PAC_INTFLAGB_TCC_Msk (_U_(0x3) << PAC_INTFLAGB_TCC_Pos) /**< (PAC_INTFLAGB Mask) TCC */
#define PAC_INTFLAGB_TCC(value) (PAC_INTFLAGB_TCC_Msk & ((value) << PAC_INTFLAGB_TCC_Pos))
#define PAC_INTFLAGB_TC_Pos _U_(13) /**< (PAC_INTFLAGB Position) TC2 */
#define PAC_INTFLAGB_TC_Msk (_U_(0x3) << PAC_INTFLAGB_TC_Pos) /**< (PAC_INTFLAGB Mask) TC */
#define PAC_INTFLAGB_TC(value) (PAC_INTFLAGB_TC_Msk & ((value) << PAC_INTFLAGB_TC_Pos))
/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
#define PAC_INTFLAGC_RESETVALUE _U_(0x00) /**< (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C Reset Value */
#define PAC_INTFLAGC_TCC2_Pos _U_(3) /**< (PAC_INTFLAGC) TCC2 Position */
#define PAC_INTFLAGC_TCC2_Msk (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos) /**< (PAC_INTFLAGC) TCC2 Mask */
#define PAC_INTFLAGC_TCC2(value) (PAC_INTFLAGC_TCC2_Msk & ((value) << PAC_INTFLAGC_TCC2_Pos))
#define PAC_INTFLAGC_TCC3_Pos _U_(4) /**< (PAC_INTFLAGC) TCC3 Position */
#define PAC_INTFLAGC_TCC3_Msk (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos) /**< (PAC_INTFLAGC) TCC3 Mask */
#define PAC_INTFLAGC_TCC3(value) (PAC_INTFLAGC_TCC3_Msk & ((value) << PAC_INTFLAGC_TCC3_Pos))
#define PAC_INTFLAGC_TC4_Pos _U_(5) /**< (PAC_INTFLAGC) TC4 Position */
#define PAC_INTFLAGC_TC4_Msk (_U_(0x1) << PAC_INTFLAGC_TC4_Pos) /**< (PAC_INTFLAGC) TC4 Mask */
#define PAC_INTFLAGC_TC4(value) (PAC_INTFLAGC_TC4_Msk & ((value) << PAC_INTFLAGC_TC4_Pos))
#define PAC_INTFLAGC_TC5_Pos _U_(6) /**< (PAC_INTFLAGC) TC5 Position */
#define PAC_INTFLAGC_TC5_Msk (_U_(0x1) << PAC_INTFLAGC_TC5_Pos) /**< (PAC_INTFLAGC) TC5 Mask */
#define PAC_INTFLAGC_TC5(value) (PAC_INTFLAGC_TC5_Msk & ((value) << PAC_INTFLAGC_TC5_Pos))
#define PAC_INTFLAGC_PDEC_Pos _U_(7) /**< (PAC_INTFLAGC) PDEC Position */
#define PAC_INTFLAGC_PDEC_Msk (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos) /**< (PAC_INTFLAGC) PDEC Mask */
#define PAC_INTFLAGC_PDEC(value) (PAC_INTFLAGC_PDEC_Msk & ((value) << PAC_INTFLAGC_PDEC_Pos))
#define PAC_INTFLAGC_AC_Pos _U_(8) /**< (PAC_INTFLAGC) AC Position */
#define PAC_INTFLAGC_AC_Msk (_U_(0x1) << PAC_INTFLAGC_AC_Pos) /**< (PAC_INTFLAGC) AC Mask */
#define PAC_INTFLAGC_AC(value) (PAC_INTFLAGC_AC_Msk & ((value) << PAC_INTFLAGC_AC_Pos))
#define PAC_INTFLAGC_AES_Pos _U_(9) /**< (PAC_INTFLAGC) AES Position */
#define PAC_INTFLAGC_AES_Msk (_U_(0x1) << PAC_INTFLAGC_AES_Pos) /**< (PAC_INTFLAGC) AES Mask */
#define PAC_INTFLAGC_AES(value) (PAC_INTFLAGC_AES_Msk & ((value) << PAC_INTFLAGC_AES_Pos))
#define PAC_INTFLAGC_TRNG_Pos _U_(10) /**< (PAC_INTFLAGC) TRNG Position */
#define PAC_INTFLAGC_TRNG_Msk (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos) /**< (PAC_INTFLAGC) TRNG Mask */
#define PAC_INTFLAGC_TRNG(value) (PAC_INTFLAGC_TRNG_Msk & ((value) << PAC_INTFLAGC_TRNG_Pos))
#define PAC_INTFLAGC_ICM_Pos _U_(11) /**< (PAC_INTFLAGC) ICM Position */
#define PAC_INTFLAGC_ICM_Msk (_U_(0x1) << PAC_INTFLAGC_ICM_Pos) /**< (PAC_INTFLAGC) ICM Mask */
#define PAC_INTFLAGC_ICM(value) (PAC_INTFLAGC_ICM_Msk & ((value) << PAC_INTFLAGC_ICM_Pos))
#define PAC_INTFLAGC_PUKCC_Pos _U_(12) /**< (PAC_INTFLAGC) PUKCC Position */
#define PAC_INTFLAGC_PUKCC_Msk (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos) /**< (PAC_INTFLAGC) PUKCC Mask */
#define PAC_INTFLAGC_PUKCC(value) (PAC_INTFLAGC_PUKCC_Msk & ((value) << PAC_INTFLAGC_PUKCC_Pos))
#define PAC_INTFLAGC_QSPI_Pos _U_(13) /**< (PAC_INTFLAGC) QSPI Position */
#define PAC_INTFLAGC_QSPI_Msk (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos) /**< (PAC_INTFLAGC) QSPI Mask */
#define PAC_INTFLAGC_QSPI(value) (PAC_INTFLAGC_QSPI_Msk & ((value) << PAC_INTFLAGC_QSPI_Pos))
#define PAC_INTFLAGC_CCL_Pos _U_(14) /**< (PAC_INTFLAGC) CCL Position */
#define PAC_INTFLAGC_CCL_Msk (_U_(0x1) << PAC_INTFLAGC_CCL_Pos) /**< (PAC_INTFLAGC) CCL Mask */
#define PAC_INTFLAGC_CCL(value) (PAC_INTFLAGC_CCL_Msk & ((value) << PAC_INTFLAGC_CCL_Pos))
#define PAC_INTFLAGC_Msk _U_(0x00007FF8) /**< (PAC_INTFLAGC) Register Mask */
#define PAC_INTFLAGC_TCC_Pos _U_(3) /**< (PAC_INTFLAGC Position) TCC2 */
#define PAC_INTFLAGC_TCC_Msk (_U_(0x3) << PAC_INTFLAGC_TCC_Pos) /**< (PAC_INTFLAGC Mask) TCC */
#define PAC_INTFLAGC_TCC(value) (PAC_INTFLAGC_TCC_Msk & ((value) << PAC_INTFLAGC_TCC_Pos))
#define PAC_INTFLAGC_TC_Pos _U_(5) /**< (PAC_INTFLAGC Position) TC4 */
#define PAC_INTFLAGC_TC_Msk (_U_(0x3) << PAC_INTFLAGC_TC_Pos) /**< (PAC_INTFLAGC Mask) TC */
#define PAC_INTFLAGC_TC(value) (PAC_INTFLAGC_TC_Msk & ((value) << PAC_INTFLAGC_TC_Pos))
/* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
#define PAC_INTFLAGD_RESETVALUE _U_(0x00) /**< (PAC_INTFLAGD) Peripheral interrupt flag status - Bridge D Reset Value */
#define PAC_INTFLAGD_SERCOM4_Pos _U_(0) /**< (PAC_INTFLAGD) SERCOM4 Position */
#define PAC_INTFLAGD_SERCOM4_Msk (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos) /**< (PAC_INTFLAGD) SERCOM4 Mask */
#define PAC_INTFLAGD_SERCOM4(value) (PAC_INTFLAGD_SERCOM4_Msk & ((value) << PAC_INTFLAGD_SERCOM4_Pos))
#define PAC_INTFLAGD_SERCOM5_Pos _U_(1) /**< (PAC_INTFLAGD) SERCOM5 Position */
#define PAC_INTFLAGD_SERCOM5_Msk (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos) /**< (PAC_INTFLAGD) SERCOM5 Mask */
#define PAC_INTFLAGD_SERCOM5(value) (PAC_INTFLAGD_SERCOM5_Msk & ((value) << PAC_INTFLAGD_SERCOM5_Pos))
#define PAC_INTFLAGD_SERCOM6_Pos _U_(2) /**< (PAC_INTFLAGD) SERCOM6 Position */
#define PAC_INTFLAGD_SERCOM6_Msk (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos) /**< (PAC_INTFLAGD) SERCOM6 Mask */
#define PAC_INTFLAGD_SERCOM6(value) (PAC_INTFLAGD_SERCOM6_Msk & ((value) << PAC_INTFLAGD_SERCOM6_Pos))
#define PAC_INTFLAGD_SERCOM7_Pos _U_(3) /**< (PAC_INTFLAGD) SERCOM7 Position */
#define PAC_INTFLAGD_SERCOM7_Msk (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos) /**< (PAC_INTFLAGD) SERCOM7 Mask */
#define PAC_INTFLAGD_SERCOM7(value) (PAC_INTFLAGD_SERCOM7_Msk & ((value) << PAC_INTFLAGD_SERCOM7_Pos))
#define PAC_INTFLAGD_TCC4_Pos _U_(4) /**< (PAC_INTFLAGD) TCC4 Position */
#define PAC_INTFLAGD_TCC4_Msk (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos) /**< (PAC_INTFLAGD) TCC4 Mask */
#define PAC_INTFLAGD_TCC4(value) (PAC_INTFLAGD_TCC4_Msk & ((value) << PAC_INTFLAGD_TCC4_Pos))
#define PAC_INTFLAGD_TC6_Pos _U_(5) /**< (PAC_INTFLAGD) TC6 Position */
#define PAC_INTFLAGD_TC6_Msk (_U_(0x1) << PAC_INTFLAGD_TC6_Pos) /**< (PAC_INTFLAGD) TC6 Mask */
#define PAC_INTFLAGD_TC6(value) (PAC_INTFLAGD_TC6_Msk & ((value) << PAC_INTFLAGD_TC6_Pos))
#define PAC_INTFLAGD_TC7_Pos _U_(6) /**< (PAC_INTFLAGD) TC7 Position */
#define PAC_INTFLAGD_TC7_Msk (_U_(0x1) << PAC_INTFLAGD_TC7_Pos) /**< (PAC_INTFLAGD) TC7 Mask */
#define PAC_INTFLAGD_TC7(value) (PAC_INTFLAGD_TC7_Msk & ((value) << PAC_INTFLAGD_TC7_Pos))
#define PAC_INTFLAGD_ADC0_Pos _U_(7) /**< (PAC_INTFLAGD) ADC0 Position */
#define PAC_INTFLAGD_ADC0_Msk (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos) /**< (PAC_INTFLAGD) ADC0 Mask */
#define PAC_INTFLAGD_ADC0(value) (PAC_INTFLAGD_ADC0_Msk & ((value) << PAC_INTFLAGD_ADC0_Pos))
#define PAC_INTFLAGD_ADC1_Pos _U_(8) /**< (PAC_INTFLAGD) ADC1 Position */
#define PAC_INTFLAGD_ADC1_Msk (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos) /**< (PAC_INTFLAGD) ADC1 Mask */
#define PAC_INTFLAGD_ADC1(value) (PAC_INTFLAGD_ADC1_Msk & ((value) << PAC_INTFLAGD_ADC1_Pos))
#define PAC_INTFLAGD_DAC_Pos _U_(9) /**< (PAC_INTFLAGD) DAC Position */
#define PAC_INTFLAGD_DAC_Msk (_U_(0x1) << PAC_INTFLAGD_DAC_Pos) /**< (PAC_INTFLAGD) DAC Mask */
#define PAC_INTFLAGD_DAC(value) (PAC_INTFLAGD_DAC_Msk & ((value) << PAC_INTFLAGD_DAC_Pos))
#define PAC_INTFLAGD_I2S_Pos _U_(10) /**< (PAC_INTFLAGD) I2S Position */
#define PAC_INTFLAGD_I2S_Msk (_U_(0x1) << PAC_INTFLAGD_I2S_Pos) /**< (PAC_INTFLAGD) I2S Mask */
#define PAC_INTFLAGD_I2S(value) (PAC_INTFLAGD_I2S_Msk & ((value) << PAC_INTFLAGD_I2S_Pos))
#define PAC_INTFLAGD_PCC_Pos _U_(11) /**< (PAC_INTFLAGD) PCC Position */
#define PAC_INTFLAGD_PCC_Msk (_U_(0x1) << PAC_INTFLAGD_PCC_Pos) /**< (PAC_INTFLAGD) PCC Mask */
#define PAC_INTFLAGD_PCC(value) (PAC_INTFLAGD_PCC_Msk & ((value) << PAC_INTFLAGD_PCC_Pos))
#define PAC_INTFLAGD_Msk _U_(0x00000FFF) /**< (PAC_INTFLAGD) Register Mask */
#define PAC_INTFLAGD_SERCOM_Pos _U_(0) /**< (PAC_INTFLAGD Position) SERCOM4 */
#define PAC_INTFLAGD_SERCOM_Msk (_U_(0xF) << PAC_INTFLAGD_SERCOM_Pos) /**< (PAC_INTFLAGD Mask) SERCOM */
#define PAC_INTFLAGD_SERCOM(value) (PAC_INTFLAGD_SERCOM_Msk & ((value) << PAC_INTFLAGD_SERCOM_Pos))
#define PAC_INTFLAGD_TCC_Pos _U_(4) /**< (PAC_INTFLAGD Position) TCC4 */
#define PAC_INTFLAGD_TCC_Msk (_U_(0x1) << PAC_INTFLAGD_TCC_Pos) /**< (PAC_INTFLAGD Mask) TCC */
#define PAC_INTFLAGD_TCC(value) (PAC_INTFLAGD_TCC_Msk & ((value) << PAC_INTFLAGD_TCC_Pos))
#define PAC_INTFLAGD_TC_Pos _U_(5) /**< (PAC_INTFLAGD Position) TC6 */
#define PAC_INTFLAGD_TC_Msk (_U_(0x3) << PAC_INTFLAGD_TC_Pos) /**< (PAC_INTFLAGD Mask) TC */
#define PAC_INTFLAGD_TC(value) (PAC_INTFLAGD_TC_Msk & ((value) << PAC_INTFLAGD_TC_Pos))
#define PAC_INTFLAGD_ADC_Pos _U_(7) /**< (PAC_INTFLAGD Position) ADCx */
#define PAC_INTFLAGD_ADC_Msk (_U_(0x3) << PAC_INTFLAGD_ADC_Pos) /**< (PAC_INTFLAGD Mask) ADC */
#define PAC_INTFLAGD_ADC(value) (PAC_INTFLAGD_ADC_Msk & ((value) << PAC_INTFLAGD_ADC_Pos))
/* -------- PAC_STATUSA : (PAC Offset: 0x34) ( R/ 32) Peripheral write protection status - Bridge A -------- */
#define PAC_STATUSA_RESETVALUE _U_(0x10000) /**< (PAC_STATUSA) Peripheral write protection status - Bridge A Reset Value */
#define PAC_STATUSA_PAC_Pos _U_(0) /**< (PAC_STATUSA) PAC APB Protect Enable Position */
#define PAC_STATUSA_PAC_Msk (_U_(0x1) << PAC_STATUSA_PAC_Pos) /**< (PAC_STATUSA) PAC APB Protect Enable Mask */
#define PAC_STATUSA_PAC(value) (PAC_STATUSA_PAC_Msk & ((value) << PAC_STATUSA_PAC_Pos))
#define PAC_STATUSA_PM_Pos _U_(1) /**< (PAC_STATUSA) PM APB Protect Enable Position */
#define PAC_STATUSA_PM_Msk (_U_(0x1) << PAC_STATUSA_PM_Pos) /**< (PAC_STATUSA) PM APB Protect Enable Mask */
#define PAC_STATUSA_PM(value) (PAC_STATUSA_PM_Msk & ((value) << PAC_STATUSA_PM_Pos))
#define PAC_STATUSA_MCLK_Pos _U_(2) /**< (PAC_STATUSA) MCLK APB Protect Enable Position */
#define PAC_STATUSA_MCLK_Msk (_U_(0x1) << PAC_STATUSA_MCLK_Pos) /**< (PAC_STATUSA) MCLK APB Protect Enable Mask */
#define PAC_STATUSA_MCLK(value) (PAC_STATUSA_MCLK_Msk & ((value) << PAC_STATUSA_MCLK_Pos))
#define PAC_STATUSA_RSTC_Pos _U_(3) /**< (PAC_STATUSA) RSTC APB Protect Enable Position */
#define PAC_STATUSA_RSTC_Msk (_U_(0x1) << PAC_STATUSA_RSTC_Pos) /**< (PAC_STATUSA) RSTC APB Protect Enable Mask */
#define PAC_STATUSA_RSTC(value) (PAC_STATUSA_RSTC_Msk & ((value) << PAC_STATUSA_RSTC_Pos))
#define PAC_STATUSA_OSCCTRL_Pos _U_(4) /**< (PAC_STATUSA) OSCCTRL APB Protect Enable Position */
#define PAC_STATUSA_OSCCTRL_Msk (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos) /**< (PAC_STATUSA) OSCCTRL APB Protect Enable Mask */
#define PAC_STATUSA_OSCCTRL(value) (PAC_STATUSA_OSCCTRL_Msk & ((value) << PAC_STATUSA_OSCCTRL_Pos))
#define PAC_STATUSA_OSC32KCTRL_Pos _U_(5) /**< (PAC_STATUSA) OSC32KCTRL APB Protect Enable Position */
#define PAC_STATUSA_OSC32KCTRL_Msk (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) /**< (PAC_STATUSA) OSC32KCTRL APB Protect Enable Mask */
#define PAC_STATUSA_OSC32KCTRL(value) (PAC_STATUSA_OSC32KCTRL_Msk & ((value) << PAC_STATUSA_OSC32KCTRL_Pos))
#define PAC_STATUSA_SUPC_Pos _U_(6) /**< (PAC_STATUSA) SUPC APB Protect Enable Position */
#define PAC_STATUSA_SUPC_Msk (_U_(0x1) << PAC_STATUSA_SUPC_Pos) /**< (PAC_STATUSA) SUPC APB Protect Enable Mask */
#define PAC_STATUSA_SUPC(value) (PAC_STATUSA_SUPC_Msk & ((value) << PAC_STATUSA_SUPC_Pos))
#define PAC_STATUSA_GCLK_Pos _U_(7) /**< (PAC_STATUSA) GCLK APB Protect Enable Position */
#define PAC_STATUSA_GCLK_Msk (_U_(0x1) << PAC_STATUSA_GCLK_Pos) /**< (PAC_STATUSA) GCLK APB Protect Enable Mask */
#define PAC_STATUSA_GCLK(value) (PAC_STATUSA_GCLK_Msk & ((value) << PAC_STATUSA_GCLK_Pos))
#define PAC_STATUSA_WDT_Pos _U_(8) /**< (PAC_STATUSA) WDT APB Protect Enable Position */
#define PAC_STATUSA_WDT_Msk (_U_(0x1) << PAC_STATUSA_WDT_Pos) /**< (PAC_STATUSA) WDT APB Protect Enable Mask */
#define PAC_STATUSA_WDT(value) (PAC_STATUSA_WDT_Msk & ((value) << PAC_STATUSA_WDT_Pos))
#define PAC_STATUSA_RTC_Pos _U_(9) /**< (PAC_STATUSA) RTC APB Protect Enable Position */
#define PAC_STATUSA_RTC_Msk (_U_(0x1) << PAC_STATUSA_RTC_Pos) /**< (PAC_STATUSA) RTC APB Protect Enable Mask */
#define PAC_STATUSA_RTC(value) (PAC_STATUSA_RTC_Msk & ((value) << PAC_STATUSA_RTC_Pos))
#define PAC_STATUSA_EIC_Pos _U_(10) /**< (PAC_STATUSA) EIC APB Protect Enable Position */
#define PAC_STATUSA_EIC_Msk (_U_(0x1) << PAC_STATUSA_EIC_Pos) /**< (PAC_STATUSA) EIC APB Protect Enable Mask */
#define PAC_STATUSA_EIC(value) (PAC_STATUSA_EIC_Msk & ((value) << PAC_STATUSA_EIC_Pos))
#define PAC_STATUSA_FREQM_Pos _U_(11) /**< (PAC_STATUSA) FREQM APB Protect Enable Position */
#define PAC_STATUSA_FREQM_Msk (_U_(0x1) << PAC_STATUSA_FREQM_Pos) /**< (PAC_STATUSA) FREQM APB Protect Enable Mask */
#define PAC_STATUSA_FREQM(value) (PAC_STATUSA_FREQM_Msk & ((value) << PAC_STATUSA_FREQM_Pos))
#define PAC_STATUSA_SERCOM0_Pos _U_(12) /**< (PAC_STATUSA) SERCOM0 APB Protect Enable Position */
#define PAC_STATUSA_SERCOM0_Msk (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos) /**< (PAC_STATUSA) SERCOM0 APB Protect Enable Mask */
#define PAC_STATUSA_SERCOM0(value) (PAC_STATUSA_SERCOM0_Msk & ((value) << PAC_STATUSA_SERCOM0_Pos))
#define PAC_STATUSA_SERCOM1_Pos _U_(13) /**< (PAC_STATUSA) SERCOM1 APB Protect Enable Position */
#define PAC_STATUSA_SERCOM1_Msk (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos) /**< (PAC_STATUSA) SERCOM1 APB Protect Enable Mask */
#define PAC_STATUSA_SERCOM1(value) (PAC_STATUSA_SERCOM1_Msk & ((value) << PAC_STATUSA_SERCOM1_Pos))
#define PAC_STATUSA_TC0_Pos _U_(14) /**< (PAC_STATUSA) TC0 APB Protect Enable Position */
#define PAC_STATUSA_TC0_Msk (_U_(0x1) << PAC_STATUSA_TC0_Pos) /**< (PAC_STATUSA) TC0 APB Protect Enable Mask */
#define PAC_STATUSA_TC0(value) (PAC_STATUSA_TC0_Msk & ((value) << PAC_STATUSA_TC0_Pos))
#define PAC_STATUSA_TC1_Pos _U_(15) /**< (PAC_STATUSA) TC1 APB Protect Enable Position */
#define PAC_STATUSA_TC1_Msk (_U_(0x1) << PAC_STATUSA_TC1_Pos) /**< (PAC_STATUSA) TC1 APB Protect Enable Mask */
#define PAC_STATUSA_TC1(value) (PAC_STATUSA_TC1_Msk & ((value) << PAC_STATUSA_TC1_Pos))
#define PAC_STATUSA_Msk _U_(0x0000FFFF) /**< (PAC_STATUSA) Register Mask */
#define PAC_STATUSA_SERCOM_Pos _U_(12) /**< (PAC_STATUSA Position) SERCOMx APB Protect Enable */
#define PAC_STATUSA_SERCOM_Msk (_U_(0x3) << PAC_STATUSA_SERCOM_Pos) /**< (PAC_STATUSA Mask) SERCOM */
#define PAC_STATUSA_SERCOM(value) (PAC_STATUSA_SERCOM_Msk & ((value) << PAC_STATUSA_SERCOM_Pos))
#define PAC_STATUSA_TC_Pos _U_(14) /**< (PAC_STATUSA Position) TCx APB Protect Enable */
#define PAC_STATUSA_TC_Msk (_U_(0x3) << PAC_STATUSA_TC_Pos) /**< (PAC_STATUSA Mask) TC */
#define PAC_STATUSA_TC(value) (PAC_STATUSA_TC_Msk & ((value) << PAC_STATUSA_TC_Pos))
/* -------- PAC_STATUSB : (PAC Offset: 0x38) ( R/ 32) Peripheral write protection status - Bridge B -------- */
#define PAC_STATUSB_RESETVALUE _U_(0x02) /**< (PAC_STATUSB) Peripheral write protection status - Bridge B Reset Value */
#define PAC_STATUSB_USB_Pos _U_(0) /**< (PAC_STATUSB) USB APB Protect Enable Position */
#define PAC_STATUSB_USB_Msk (_U_(0x1) << PAC_STATUSB_USB_Pos) /**< (PAC_STATUSB) USB APB Protect Enable Mask */
#define PAC_STATUSB_USB(value) (PAC_STATUSB_USB_Msk & ((value) << PAC_STATUSB_USB_Pos))
#define PAC_STATUSB_DSU_Pos _U_(1) /**< (PAC_STATUSB) DSU APB Protect Enable Position */
#define PAC_STATUSB_DSU_Msk (_U_(0x1) << PAC_STATUSB_DSU_Pos) /**< (PAC_STATUSB) DSU APB Protect Enable Mask */
#define PAC_STATUSB_DSU(value) (PAC_STATUSB_DSU_Msk & ((value) << PAC_STATUSB_DSU_Pos))
#define PAC_STATUSB_NVMCTRL_Pos _U_(2) /**< (PAC_STATUSB) NVMCTRL APB Protect Enable Position */
#define PAC_STATUSB_NVMCTRL_Msk (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos) /**< (PAC_STATUSB) NVMCTRL APB Protect Enable Mask */
#define PAC_STATUSB_NVMCTRL(value) (PAC_STATUSB_NVMCTRL_Msk & ((value) << PAC_STATUSB_NVMCTRL_Pos))
#define PAC_STATUSB_CMCC_Pos _U_(3) /**< (PAC_STATUSB) CMCC APB Protect Enable Position */
#define PAC_STATUSB_CMCC_Msk (_U_(0x1) << PAC_STATUSB_CMCC_Pos) /**< (PAC_STATUSB) CMCC APB Protect Enable Mask */
#define PAC_STATUSB_CMCC(value) (PAC_STATUSB_CMCC_Msk & ((value) << PAC_STATUSB_CMCC_Pos))
#define PAC_STATUSB_PORT_Pos _U_(4) /**< (PAC_STATUSB) PORT APB Protect Enable Position */
#define PAC_STATUSB_PORT_Msk (_U_(0x1) << PAC_STATUSB_PORT_Pos) /**< (PAC_STATUSB) PORT APB Protect Enable Mask */
#define PAC_STATUSB_PORT(value) (PAC_STATUSB_PORT_Msk & ((value) << PAC_STATUSB_PORT_Pos))
#define PAC_STATUSB_DMAC_Pos _U_(5) /**< (PAC_STATUSB) DMAC APB Protect Enable Position */
#define PAC_STATUSB_DMAC_Msk (_U_(0x1) << PAC_STATUSB_DMAC_Pos) /**< (PAC_STATUSB) DMAC APB Protect Enable Mask */
#define PAC_STATUSB_DMAC(value) (PAC_STATUSB_DMAC_Msk & ((value) << PAC_STATUSB_DMAC_Pos))
#define PAC_STATUSB_HMATRIX_Pos _U_(6) /**< (PAC_STATUSB) HMATRIX APB Protect Enable Position */
#define PAC_STATUSB_HMATRIX_Msk (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos) /**< (PAC_STATUSB) HMATRIX APB Protect Enable Mask */
#define PAC_STATUSB_HMATRIX(value) (PAC_STATUSB_HMATRIX_Msk & ((value) << PAC_STATUSB_HMATRIX_Pos))
#define PAC_STATUSB_EVSYS_Pos _U_(7) /**< (PAC_STATUSB) EVSYS APB Protect Enable Position */
#define PAC_STATUSB_EVSYS_Msk (_U_(0x1) << PAC_STATUSB_EVSYS_Pos) /**< (PAC_STATUSB) EVSYS APB Protect Enable Mask */
#define PAC_STATUSB_EVSYS(value) (PAC_STATUSB_EVSYS_Msk & ((value) << PAC_STATUSB_EVSYS_Pos))
#define PAC_STATUSB_SERCOM2_Pos _U_(9) /**< (PAC_STATUSB) SERCOM2 APB Protect Enable Position */
#define PAC_STATUSB_SERCOM2_Msk (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos) /**< (PAC_STATUSB) SERCOM2 APB Protect Enable Mask */
#define PAC_STATUSB_SERCOM2(value) (PAC_STATUSB_SERCOM2_Msk & ((value) << PAC_STATUSB_SERCOM2_Pos))
#define PAC_STATUSB_SERCOM3_Pos _U_(10) /**< (PAC_STATUSB) SERCOM3 APB Protect Enable Position */
#define PAC_STATUSB_SERCOM3_Msk (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos) /**< (PAC_STATUSB) SERCOM3 APB Protect Enable Mask */
#define PAC_STATUSB_SERCOM3(value) (PAC_STATUSB_SERCOM3_Msk & ((value) << PAC_STATUSB_SERCOM3_Pos))
#define PAC_STATUSB_TCC0_Pos _U_(11) /**< (PAC_STATUSB) TCC0 APB Protect Enable Position */
#define PAC_STATUSB_TCC0_Msk (_U_(0x1) << PAC_STATUSB_TCC0_Pos) /**< (PAC_STATUSB) TCC0 APB Protect Enable Mask */
#define PAC_STATUSB_TCC0(value) (PAC_STATUSB_TCC0_Msk & ((value) << PAC_STATUSB_TCC0_Pos))
#define PAC_STATUSB_TCC1_Pos _U_(12) /**< (PAC_STATUSB) TCC1 APB Protect Enable Position */
#define PAC_STATUSB_TCC1_Msk (_U_(0x1) << PAC_STATUSB_TCC1_Pos) /**< (PAC_STATUSB) TCC1 APB Protect Enable Mask */
#define PAC_STATUSB_TCC1(value) (PAC_STATUSB_TCC1_Msk & ((value) << PAC_STATUSB_TCC1_Pos))
#define PAC_STATUSB_TC2_Pos _U_(13) /**< (PAC_STATUSB) TC2 APB Protect Enable Position */
#define PAC_STATUSB_TC2_Msk (_U_(0x1) << PAC_STATUSB_TC2_Pos) /**< (PAC_STATUSB) TC2 APB Protect Enable Mask */
#define PAC_STATUSB_TC2(value) (PAC_STATUSB_TC2_Msk & ((value) << PAC_STATUSB_TC2_Pos))
#define PAC_STATUSB_TC3_Pos _U_(14) /**< (PAC_STATUSB) TC3 APB Protect Enable Position */
#define PAC_STATUSB_TC3_Msk (_U_(0x1) << PAC_STATUSB_TC3_Pos) /**< (PAC_STATUSB) TC3 APB Protect Enable Mask */
#define PAC_STATUSB_TC3(value) (PAC_STATUSB_TC3_Msk & ((value) << PAC_STATUSB_TC3_Pos))
#define PAC_STATUSB_RAMECC_Pos _U_(16) /**< (PAC_STATUSB) RAMECC APB Protect Enable Position */
#define PAC_STATUSB_RAMECC_Msk (_U_(0x1) << PAC_STATUSB_RAMECC_Pos) /**< (PAC_STATUSB) RAMECC APB Protect Enable Mask */
#define PAC_STATUSB_RAMECC(value) (PAC_STATUSB_RAMECC_Msk & ((value) << PAC_STATUSB_RAMECC_Pos))
#define PAC_STATUSB_Msk _U_(0x00017EFF) /**< (PAC_STATUSB) Register Mask */
#define PAC_STATUSB_SERCOM_Pos _U_(9) /**< (PAC_STATUSB Position) SERCOM2 APB Protect Enable */
#define PAC_STATUSB_SERCOM_Msk (_U_(0x3) << PAC_STATUSB_SERCOM_Pos) /**< (PAC_STATUSB Mask) SERCOM */
#define PAC_STATUSB_SERCOM(value) (PAC_STATUSB_SERCOM_Msk & ((value) << PAC_STATUSB_SERCOM_Pos))
#define PAC_STATUSB_TCC_Pos _U_(11) /**< (PAC_STATUSB Position) TCCx APB Protect Enable */
#define PAC_STATUSB_TCC_Msk (_U_(0x3) << PAC_STATUSB_TCC_Pos) /**< (PAC_STATUSB Mask) TCC */
#define PAC_STATUSB_TCC(value) (PAC_STATUSB_TCC_Msk & ((value) << PAC_STATUSB_TCC_Pos))
#define PAC_STATUSB_TC_Pos _U_(13) /**< (PAC_STATUSB Position) TC2 APB Protect Enable */
#define PAC_STATUSB_TC_Msk (_U_(0x3) << PAC_STATUSB_TC_Pos) /**< (PAC_STATUSB Mask) TC */
#define PAC_STATUSB_TC(value) (PAC_STATUSB_TC_Msk & ((value) << PAC_STATUSB_TC_Pos))
/* -------- PAC_STATUSC : (PAC Offset: 0x3C) ( R/ 32) Peripheral write protection status - Bridge C -------- */
#define PAC_STATUSC_RESETVALUE _U_(0x00) /**< (PAC_STATUSC) Peripheral write protection status - Bridge C Reset Value */
#define PAC_STATUSC_TCC2_Pos _U_(3) /**< (PAC_STATUSC) TCC2 APB Protect Enable Position */
#define PAC_STATUSC_TCC2_Msk (_U_(0x1) << PAC_STATUSC_TCC2_Pos) /**< (PAC_STATUSC) TCC2 APB Protect Enable Mask */
#define PAC_STATUSC_TCC2(value) (PAC_STATUSC_TCC2_Msk & ((value) << PAC_STATUSC_TCC2_Pos))
#define PAC_STATUSC_TCC3_Pos _U_(4) /**< (PAC_STATUSC) TCC3 APB Protect Enable Position */
#define PAC_STATUSC_TCC3_Msk (_U_(0x1) << PAC_STATUSC_TCC3_Pos) /**< (PAC_STATUSC) TCC3 APB Protect Enable Mask */
#define PAC_STATUSC_TCC3(value) (PAC_STATUSC_TCC3_Msk & ((value) << PAC_STATUSC_TCC3_Pos))
#define PAC_STATUSC_TC4_Pos _U_(5) /**< (PAC_STATUSC) TC4 APB Protect Enable Position */
#define PAC_STATUSC_TC4_Msk (_U_(0x1) << PAC_STATUSC_TC4_Pos) /**< (PAC_STATUSC) TC4 APB Protect Enable Mask */
#define PAC_STATUSC_TC4(value) (PAC_STATUSC_TC4_Msk & ((value) << PAC_STATUSC_TC4_Pos))
#define PAC_STATUSC_TC5_Pos _U_(6) /**< (PAC_STATUSC) TC5 APB Protect Enable Position */
#define PAC_STATUSC_TC5_Msk (_U_(0x1) << PAC_STATUSC_TC5_Pos) /**< (PAC_STATUSC) TC5 APB Protect Enable Mask */
#define PAC_STATUSC_TC5(value) (PAC_STATUSC_TC5_Msk & ((value) << PAC_STATUSC_TC5_Pos))
#define PAC_STATUSC_PDEC_Pos _U_(7) /**< (PAC_STATUSC) PDEC APB Protect Enable Position */
#define PAC_STATUSC_PDEC_Msk (_U_(0x1) << PAC_STATUSC_PDEC_Pos) /**< (PAC_STATUSC) PDEC APB Protect Enable Mask */
#define PAC_STATUSC_PDEC(value) (PAC_STATUSC_PDEC_Msk & ((value) << PAC_STATUSC_PDEC_Pos))
#define PAC_STATUSC_AC_Pos _U_(8) /**< (PAC_STATUSC) AC APB Protect Enable Position */
#define PAC_STATUSC_AC_Msk (_U_(0x1) << PAC_STATUSC_AC_Pos) /**< (PAC_STATUSC) AC APB Protect Enable Mask */
#define PAC_STATUSC_AC(value) (PAC_STATUSC_AC_Msk & ((value) << PAC_STATUSC_AC_Pos))
#define PAC_STATUSC_AES_Pos _U_(9) /**< (PAC_STATUSC) AES APB Protect Enable Position */
#define PAC_STATUSC_AES_Msk (_U_(0x1) << PAC_STATUSC_AES_Pos) /**< (PAC_STATUSC) AES APB Protect Enable Mask */
#define PAC_STATUSC_AES(value) (PAC_STATUSC_AES_Msk & ((value) << PAC_STATUSC_AES_Pos))
#define PAC_STATUSC_TRNG_Pos _U_(10) /**< (PAC_STATUSC) TRNG APB Protect Enable Position */
#define PAC_STATUSC_TRNG_Msk (_U_(0x1) << PAC_STATUSC_TRNG_Pos) /**< (PAC_STATUSC) TRNG APB Protect Enable Mask */
#define PAC_STATUSC_TRNG(value) (PAC_STATUSC_TRNG_Msk & ((value) << PAC_STATUSC_TRNG_Pos))
#define PAC_STATUSC_ICM_Pos _U_(11) /**< (PAC_STATUSC) ICM APB Protect Enable Position */
#define PAC_STATUSC_ICM_Msk (_U_(0x1) << PAC_STATUSC_ICM_Pos) /**< (PAC_STATUSC) ICM APB Protect Enable Mask */
#define PAC_STATUSC_ICM(value) (PAC_STATUSC_ICM_Msk & ((value) << PAC_STATUSC_ICM_Pos))
#define PAC_STATUSC_PUKCC_Pos _U_(12) /**< (PAC_STATUSC) PUKCC APB Protect Enable Position */
#define PAC_STATUSC_PUKCC_Msk (_U_(0x1) << PAC_STATUSC_PUKCC_Pos) /**< (PAC_STATUSC) PUKCC APB Protect Enable Mask */
#define PAC_STATUSC_PUKCC(value) (PAC_STATUSC_PUKCC_Msk & ((value) << PAC_STATUSC_PUKCC_Pos))
#define PAC_STATUSC_QSPI_Pos _U_(13) /**< (PAC_STATUSC) QSPI APB Protect Enable Position */
#define PAC_STATUSC_QSPI_Msk (_U_(0x1) << PAC_STATUSC_QSPI_Pos) /**< (PAC_STATUSC) QSPI APB Protect Enable Mask */
#define PAC_STATUSC_QSPI(value) (PAC_STATUSC_QSPI_Msk & ((value) << PAC_STATUSC_QSPI_Pos))
#define PAC_STATUSC_CCL_Pos _U_(14) /**< (PAC_STATUSC) CCL APB Protect Enable Position */
#define PAC_STATUSC_CCL_Msk (_U_(0x1) << PAC_STATUSC_CCL_Pos) /**< (PAC_STATUSC) CCL APB Protect Enable Mask */
#define PAC_STATUSC_CCL(value) (PAC_STATUSC_CCL_Msk & ((value) << PAC_STATUSC_CCL_Pos))
#define PAC_STATUSC_Msk _U_(0x00007FF8) /**< (PAC_STATUSC) Register Mask */
#define PAC_STATUSC_TCC_Pos _U_(3) /**< (PAC_STATUSC Position) TCC2 APB Protect Enable */
#define PAC_STATUSC_TCC_Msk (_U_(0x3) << PAC_STATUSC_TCC_Pos) /**< (PAC_STATUSC Mask) TCC */
#define PAC_STATUSC_TCC(value) (PAC_STATUSC_TCC_Msk & ((value) << PAC_STATUSC_TCC_Pos))
#define PAC_STATUSC_TC_Pos _U_(5) /**< (PAC_STATUSC Position) TC4 APB Protect Enable */
#define PAC_STATUSC_TC_Msk (_U_(0x3) << PAC_STATUSC_TC_Pos) /**< (PAC_STATUSC Mask) TC */
#define PAC_STATUSC_TC(value) (PAC_STATUSC_TC_Msk & ((value) << PAC_STATUSC_TC_Pos))
/* -------- PAC_STATUSD : (PAC Offset: 0x40) ( R/ 32) Peripheral write protection status - Bridge D -------- */
#define PAC_STATUSD_RESETVALUE _U_(0x00) /**< (PAC_STATUSD) Peripheral write protection status - Bridge D Reset Value */
#define PAC_STATUSD_SERCOM4_Pos _U_(0) /**< (PAC_STATUSD) SERCOM4 APB Protect Enable Position */
#define PAC_STATUSD_SERCOM4_Msk (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos) /**< (PAC_STATUSD) SERCOM4 APB Protect Enable Mask */
#define PAC_STATUSD_SERCOM4(value) (PAC_STATUSD_SERCOM4_Msk & ((value) << PAC_STATUSD_SERCOM4_Pos))
#define PAC_STATUSD_SERCOM5_Pos _U_(1) /**< (PAC_STATUSD) SERCOM5 APB Protect Enable Position */
#define PAC_STATUSD_SERCOM5_Msk (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos) /**< (PAC_STATUSD) SERCOM5 APB Protect Enable Mask */
#define PAC_STATUSD_SERCOM5(value) (PAC_STATUSD_SERCOM5_Msk & ((value) << PAC_STATUSD_SERCOM5_Pos))
#define PAC_STATUSD_SERCOM6_Pos _U_(2) /**< (PAC_STATUSD) SERCOM6 APB Protect Enable Position */
#define PAC_STATUSD_SERCOM6_Msk (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos) /**< (PAC_STATUSD) SERCOM6 APB Protect Enable Mask */
#define PAC_STATUSD_SERCOM6(value) (PAC_STATUSD_SERCOM6_Msk & ((value) << PAC_STATUSD_SERCOM6_Pos))
#define PAC_STATUSD_SERCOM7_Pos _U_(3) /**< (PAC_STATUSD) SERCOM7 APB Protect Enable Position */
#define PAC_STATUSD_SERCOM7_Msk (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos) /**< (PAC_STATUSD) SERCOM7 APB Protect Enable Mask */
#define PAC_STATUSD_SERCOM7(value) (PAC_STATUSD_SERCOM7_Msk & ((value) << PAC_STATUSD_SERCOM7_Pos))
#define PAC_STATUSD_TCC4_Pos _U_(4) /**< (PAC_STATUSD) TCC4 APB Protect Enable Position */
#define PAC_STATUSD_TCC4_Msk (_U_(0x1) << PAC_STATUSD_TCC4_Pos) /**< (PAC_STATUSD) TCC4 APB Protect Enable Mask */
#define PAC_STATUSD_TCC4(value) (PAC_STATUSD_TCC4_Msk & ((value) << PAC_STATUSD_TCC4_Pos))
#define PAC_STATUSD_TC6_Pos _U_(5) /**< (PAC_STATUSD) TC6 APB Protect Enable Position */
#define PAC_STATUSD_TC6_Msk (_U_(0x1) << PAC_STATUSD_TC6_Pos) /**< (PAC_STATUSD) TC6 APB Protect Enable Mask */
#define PAC_STATUSD_TC6(value) (PAC_STATUSD_TC6_Msk & ((value) << PAC_STATUSD_TC6_Pos))
#define PAC_STATUSD_TC7_Pos _U_(6) /**< (PAC_STATUSD) TC7 APB Protect Enable Position */
#define PAC_STATUSD_TC7_Msk (_U_(0x1) << PAC_STATUSD_TC7_Pos) /**< (PAC_STATUSD) TC7 APB Protect Enable Mask */
#define PAC_STATUSD_TC7(value) (PAC_STATUSD_TC7_Msk & ((value) << PAC_STATUSD_TC7_Pos))
#define PAC_STATUSD_ADC0_Pos _U_(7) /**< (PAC_STATUSD) ADC0 APB Protect Enable Position */
#define PAC_STATUSD_ADC0_Msk (_U_(0x1) << PAC_STATUSD_ADC0_Pos) /**< (PAC_STATUSD) ADC0 APB Protect Enable Mask */
#define PAC_STATUSD_ADC0(value) (PAC_STATUSD_ADC0_Msk & ((value) << PAC_STATUSD_ADC0_Pos))
#define PAC_STATUSD_ADC1_Pos _U_(8) /**< (PAC_STATUSD) ADC1 APB Protect Enable Position */
#define PAC_STATUSD_ADC1_Msk (_U_(0x1) << PAC_STATUSD_ADC1_Pos) /**< (PAC_STATUSD) ADC1 APB Protect Enable Mask */
#define PAC_STATUSD_ADC1(value) (PAC_STATUSD_ADC1_Msk & ((value) << PAC_STATUSD_ADC1_Pos))
#define PAC_STATUSD_DAC_Pos _U_(9) /**< (PAC_STATUSD) DAC APB Protect Enable Position */
#define PAC_STATUSD_DAC_Msk (_U_(0x1) << PAC_STATUSD_DAC_Pos) /**< (PAC_STATUSD) DAC APB Protect Enable Mask */
#define PAC_STATUSD_DAC(value) (PAC_STATUSD_DAC_Msk & ((value) << PAC_STATUSD_DAC_Pos))
#define PAC_STATUSD_I2S_Pos _U_(10) /**< (PAC_STATUSD) I2S APB Protect Enable Position */
#define PAC_STATUSD_I2S_Msk (_U_(0x1) << PAC_STATUSD_I2S_Pos) /**< (PAC_STATUSD) I2S APB Protect Enable Mask */
#define PAC_STATUSD_I2S(value) (PAC_STATUSD_I2S_Msk & ((value) << PAC_STATUSD_I2S_Pos))
#define PAC_STATUSD_PCC_Pos _U_(11) /**< (PAC_STATUSD) PCC APB Protect Enable Position */
#define PAC_STATUSD_PCC_Msk (_U_(0x1) << PAC_STATUSD_PCC_Pos) /**< (PAC_STATUSD) PCC APB Protect Enable Mask */
#define PAC_STATUSD_PCC(value) (PAC_STATUSD_PCC_Msk & ((value) << PAC_STATUSD_PCC_Pos))
#define PAC_STATUSD_Msk _U_(0x00000FFF) /**< (PAC_STATUSD) Register Mask */
#define PAC_STATUSD_SERCOM_Pos _U_(0) /**< (PAC_STATUSD Position) SERCOM4 APB Protect Enable */
#define PAC_STATUSD_SERCOM_Msk (_U_(0xF) << PAC_STATUSD_SERCOM_Pos) /**< (PAC_STATUSD Mask) SERCOM */
#define PAC_STATUSD_SERCOM(value) (PAC_STATUSD_SERCOM_Msk & ((value) << PAC_STATUSD_SERCOM_Pos))
#define PAC_STATUSD_TCC_Pos _U_(4) /**< (PAC_STATUSD Position) TCC4 APB Protect Enable */
#define PAC_STATUSD_TCC_Msk (_U_(0x1) << PAC_STATUSD_TCC_Pos) /**< (PAC_STATUSD Mask) TCC */
#define PAC_STATUSD_TCC(value) (PAC_STATUSD_TCC_Msk & ((value) << PAC_STATUSD_TCC_Pos))
#define PAC_STATUSD_TC_Pos _U_(5) /**< (PAC_STATUSD Position) TC6 APB Protect Enable */
#define PAC_STATUSD_TC_Msk (_U_(0x3) << PAC_STATUSD_TC_Pos) /**< (PAC_STATUSD Mask) TC */
#define PAC_STATUSD_TC(value) (PAC_STATUSD_TC_Msk & ((value) << PAC_STATUSD_TC_Pos))
#define PAC_STATUSD_ADC_Pos _U_(7) /**< (PAC_STATUSD Position) ADCx APB Protect Enable */
#define PAC_STATUSD_ADC_Msk (_U_(0x3) << PAC_STATUSD_ADC_Pos) /**< (PAC_STATUSD Mask) ADC */
#define PAC_STATUSD_ADC(value) (PAC_STATUSD_ADC_Msk & ((value) << PAC_STATUSD_ADC_Pos))
/** \brief PAC register offsets definitions */
#define PAC_WRCTRL_REG_OFST (0x00) /**< (PAC_WRCTRL) Write control Offset */
#define PAC_EVCTRL_REG_OFST (0x04) /**< (PAC_EVCTRL) Event control Offset */
#define PAC_INTENCLR_REG_OFST (0x08) /**< (PAC_INTENCLR) Interrupt enable clear Offset */
#define PAC_INTENSET_REG_OFST (0x09) /**< (PAC_INTENSET) Interrupt enable set Offset */
#define PAC_INTFLAGAHB_REG_OFST (0x10) /**< (PAC_INTFLAGAHB) Bridge interrupt flag status Offset */
#define PAC_INTFLAGA_REG_OFST (0x14) /**< (PAC_INTFLAGA) Peripheral interrupt flag status - Bridge A Offset */
#define PAC_INTFLAGB_REG_OFST (0x18) /**< (PAC_INTFLAGB) Peripheral interrupt flag status - Bridge B Offset */
#define PAC_INTFLAGC_REG_OFST (0x1C) /**< (PAC_INTFLAGC) Peripheral interrupt flag status - Bridge C Offset */
#define PAC_INTFLAGD_REG_OFST (0x20) /**< (PAC_INTFLAGD) Peripheral interrupt flag status - Bridge D Offset */
#define PAC_STATUSA_REG_OFST (0x34) /**< (PAC_STATUSA) Peripheral write protection status - Bridge A Offset */
#define PAC_STATUSB_REG_OFST (0x38) /**< (PAC_STATUSB) Peripheral write protection status - Bridge B Offset */
#define PAC_STATUSC_REG_OFST (0x3C) /**< (PAC_STATUSC) Peripheral write protection status - Bridge C Offset */
#define PAC_STATUSD_REG_OFST (0x40) /**< (PAC_STATUSD) Peripheral write protection status - Bridge D Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief PAC register API structure */
typedef struct
{ /* Peripheral Access Controller */
__IO uint32_t PAC_WRCTRL; /**< Offset: 0x00 (R/W 32) Write control */
__IO uint8_t PAC_EVCTRL; /**< Offset: 0x04 (R/W 8) Event control */
__I uint8_t Reserved1[0x03];
__IO uint8_t PAC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt enable clear */
__IO uint8_t PAC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt enable set */
__I uint8_t Reserved2[0x06];
__IO uint32_t PAC_INTFLAGAHB; /**< Offset: 0x10 (R/W 32) Bridge interrupt flag status */
__IO uint32_t PAC_INTFLAGA; /**< Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
__IO uint32_t PAC_INTFLAGB; /**< Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
__IO uint32_t PAC_INTFLAGC; /**< Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
__IO uint32_t PAC_INTFLAGD; /**< Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */
__I uint8_t Reserved3[0x10];
__I uint32_t PAC_STATUSA; /**< Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
__I uint32_t PAC_STATUSB; /**< Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
__I uint32_t PAC_STATUSC; /**< Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
__I uint32_t PAC_STATUSD; /**< Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */
} pac_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PAC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/pcc.h
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/**
* \brief Component description for PCC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PCC_COMPONENT_H_
#define _SAMD51_PCC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PCC */
/* ************************************************************************** */
/* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
#define PCC_MR_RESETVALUE _U_(0x00) /**< (PCC_MR) Mode Register Reset Value */
#define PCC_MR_PCEN_Pos _U_(0) /**< (PCC_MR) Parallel Capture Enable Position */
#define PCC_MR_PCEN_Msk (_U_(0x1) << PCC_MR_PCEN_Pos) /**< (PCC_MR) Parallel Capture Enable Mask */
#define PCC_MR_PCEN(value) (PCC_MR_PCEN_Msk & ((value) << PCC_MR_PCEN_Pos))
#define PCC_MR_DSIZE_Pos _U_(4) /**< (PCC_MR) Data size Position */
#define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos) /**< (PCC_MR) Data size Mask */
#define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
#define PCC_MR_SCALE_Pos _U_(8) /**< (PCC_MR) Scale data Position */
#define PCC_MR_SCALE_Msk (_U_(0x1) << PCC_MR_SCALE_Pos) /**< (PCC_MR) Scale data Mask */
#define PCC_MR_SCALE(value) (PCC_MR_SCALE_Msk & ((value) << PCC_MR_SCALE_Pos))
#define PCC_MR_ALWYS_Pos _U_(9) /**< (PCC_MR) Always Sampling Position */
#define PCC_MR_ALWYS_Msk (_U_(0x1) << PCC_MR_ALWYS_Pos) /**< (PCC_MR) Always Sampling Mask */
#define PCC_MR_ALWYS(value) (PCC_MR_ALWYS_Msk & ((value) << PCC_MR_ALWYS_Pos))
#define PCC_MR_HALFS_Pos _U_(10) /**< (PCC_MR) Half Sampling Position */
#define PCC_MR_HALFS_Msk (_U_(0x1) << PCC_MR_HALFS_Pos) /**< (PCC_MR) Half Sampling Mask */
#define PCC_MR_HALFS(value) (PCC_MR_HALFS_Msk & ((value) << PCC_MR_HALFS_Pos))
#define PCC_MR_FRSTS_Pos _U_(11) /**< (PCC_MR) First sample Position */
#define PCC_MR_FRSTS_Msk (_U_(0x1) << PCC_MR_FRSTS_Pos) /**< (PCC_MR) First sample Mask */
#define PCC_MR_FRSTS(value) (PCC_MR_FRSTS_Msk & ((value) << PCC_MR_FRSTS_Pos))
#define PCC_MR_ISIZE_Pos _U_(16) /**< (PCC_MR) Input Data Size Position */
#define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos) /**< (PCC_MR) Input Data Size Mask */
#define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
#define PCC_MR_CID_Pos _U_(30) /**< (PCC_MR) Clear If Disabled Position */
#define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos) /**< (PCC_MR) Clear If Disabled Mask */
#define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
#define PCC_MR_Msk _U_(0xC0070F31) /**< (PCC_MR) Register Mask */
/* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
#define PCC_IER_RESETVALUE _U_(0x00) /**< (PCC_IER) Interrupt Enable Register Reset Value */
#define PCC_IER_DRDY_Pos _U_(0) /**< (PCC_IER) Data Ready Interrupt Enable Position */
#define PCC_IER_DRDY_Msk (_U_(0x1) << PCC_IER_DRDY_Pos) /**< (PCC_IER) Data Ready Interrupt Enable Mask */
#define PCC_IER_DRDY(value) (PCC_IER_DRDY_Msk & ((value) << PCC_IER_DRDY_Pos))
#define PCC_IER_OVRE_Pos _U_(1) /**< (PCC_IER) Overrun Error Interrupt Enable Position */
#define PCC_IER_OVRE_Msk (_U_(0x1) << PCC_IER_OVRE_Pos) /**< (PCC_IER) Overrun Error Interrupt Enable Mask */
#define PCC_IER_OVRE(value) (PCC_IER_OVRE_Msk & ((value) << PCC_IER_OVRE_Pos))
#define PCC_IER_Msk _U_(0x00000003) /**< (PCC_IER) Register Mask */
/* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
#define PCC_IDR_RESETVALUE _U_(0x00) /**< (PCC_IDR) Interrupt Disable Register Reset Value */
#define PCC_IDR_DRDY_Pos _U_(0) /**< (PCC_IDR) Data Ready Interrupt Disable Position */
#define PCC_IDR_DRDY_Msk (_U_(0x1) << PCC_IDR_DRDY_Pos) /**< (PCC_IDR) Data Ready Interrupt Disable Mask */
#define PCC_IDR_DRDY(value) (PCC_IDR_DRDY_Msk & ((value) << PCC_IDR_DRDY_Pos))
#define PCC_IDR_OVRE_Pos _U_(1) /**< (PCC_IDR) Overrun Error Interrupt Disable Position */
#define PCC_IDR_OVRE_Msk (_U_(0x1) << PCC_IDR_OVRE_Pos) /**< (PCC_IDR) Overrun Error Interrupt Disable Mask */
#define PCC_IDR_OVRE(value) (PCC_IDR_OVRE_Msk & ((value) << PCC_IDR_OVRE_Pos))
#define PCC_IDR_Msk _U_(0x00000003) /**< (PCC_IDR) Register Mask */
/* -------- PCC_IMR : (PCC Offset: 0x0C) ( R/ 32) Interrupt Mask Register -------- */
#define PCC_IMR_RESETVALUE _U_(0x00) /**< (PCC_IMR) Interrupt Mask Register Reset Value */
#define PCC_IMR_DRDY_Pos _U_(0) /**< (PCC_IMR) Data Ready Interrupt Mask Position */
#define PCC_IMR_DRDY_Msk (_U_(0x1) << PCC_IMR_DRDY_Pos) /**< (PCC_IMR) Data Ready Interrupt Mask Mask */
#define PCC_IMR_DRDY(value) (PCC_IMR_DRDY_Msk & ((value) << PCC_IMR_DRDY_Pos))
#define PCC_IMR_OVRE_Pos _U_(1) /**< (PCC_IMR) Overrun Error Interrupt Mask Position */
#define PCC_IMR_OVRE_Msk (_U_(0x1) << PCC_IMR_OVRE_Pos) /**< (PCC_IMR) Overrun Error Interrupt Mask Mask */
#define PCC_IMR_OVRE(value) (PCC_IMR_OVRE_Msk & ((value) << PCC_IMR_OVRE_Pos))
#define PCC_IMR_Msk _U_(0x00000003) /**< (PCC_IMR) Register Mask */
/* -------- PCC_ISR : (PCC Offset: 0x10) ( R/ 32) Interrupt Status Register -------- */
#define PCC_ISR_RESETVALUE _U_(0x00) /**< (PCC_ISR) Interrupt Status Register Reset Value */
#define PCC_ISR_DRDY_Pos _U_(0) /**< (PCC_ISR) Data Ready Interrupt Status Position */
#define PCC_ISR_DRDY_Msk (_U_(0x1) << PCC_ISR_DRDY_Pos) /**< (PCC_ISR) Data Ready Interrupt Status Mask */
#define PCC_ISR_DRDY(value) (PCC_ISR_DRDY_Msk & ((value) << PCC_ISR_DRDY_Pos))
#define PCC_ISR_OVRE_Pos _U_(1) /**< (PCC_ISR) Overrun Error Interrupt Status Position */
#define PCC_ISR_OVRE_Msk (_U_(0x1) << PCC_ISR_OVRE_Pos) /**< (PCC_ISR) Overrun Error Interrupt Status Mask */
#define PCC_ISR_OVRE(value) (PCC_ISR_OVRE_Msk & ((value) << PCC_ISR_OVRE_Pos))
#define PCC_ISR_Msk _U_(0x00000003) /**< (PCC_ISR) Register Mask */
/* -------- PCC_RHR : (PCC Offset: 0x14) ( R/ 32) Reception Holding Register -------- */
#define PCC_RHR_RESETVALUE _U_(0x00) /**< (PCC_RHR) Reception Holding Register Reset Value */
#define PCC_RHR_RDATA_Pos _U_(0) /**< (PCC_RHR) Reception Data Position */
#define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos) /**< (PCC_RHR) Reception Data Mask */
#define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
#define PCC_RHR_Msk _U_(0xFFFFFFFF) /**< (PCC_RHR) Register Mask */
/* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
#define PCC_WPMR_RESETVALUE _U_(0x00) /**< (PCC_WPMR) Write Protection Mode Register Reset Value */
#define PCC_WPMR_WPEN_Pos _U_(0) /**< (PCC_WPMR) Write Protection Enable Position */
#define PCC_WPMR_WPEN_Msk (_U_(0x1) << PCC_WPMR_WPEN_Pos) /**< (PCC_WPMR) Write Protection Enable Mask */
#define PCC_WPMR_WPEN(value) (PCC_WPMR_WPEN_Msk & ((value) << PCC_WPMR_WPEN_Pos))
#define PCC_WPMR_WPKEY_Pos _U_(8) /**< (PCC_WPMR) Write Protection Key Position */
#define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos) /**< (PCC_WPMR) Write Protection Key Mask */
#define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
#define PCC_WPMR_Msk _U_(0xFFFFFF01) /**< (PCC_WPMR) Register Mask */
/* -------- PCC_WPSR : (PCC Offset: 0xE4) ( R/ 32) Write Protection Status Register -------- */
#define PCC_WPSR_RESETVALUE _U_(0x00) /**< (PCC_WPSR) Write Protection Status Register Reset Value */
#define PCC_WPSR_WPVS_Pos _U_(0) /**< (PCC_WPSR) Write Protection Violation Source Position */
#define PCC_WPSR_WPVS_Msk (_U_(0x1) << PCC_WPSR_WPVS_Pos) /**< (PCC_WPSR) Write Protection Violation Source Mask */
#define PCC_WPSR_WPVS(value) (PCC_WPSR_WPVS_Msk & ((value) << PCC_WPSR_WPVS_Pos))
#define PCC_WPSR_WPVSRC_Pos _U_(8) /**< (PCC_WPSR) Write Protection Violation Status Position */
#define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos) /**< (PCC_WPSR) Write Protection Violation Status Mask */
#define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
#define PCC_WPSR_Msk _U_(0x00FFFF01) /**< (PCC_WPSR) Register Mask */
/** \brief PCC register offsets definitions */
#define PCC_MR_REG_OFST (0x00) /**< (PCC_MR) Mode Register Offset */
#define PCC_IER_REG_OFST (0x04) /**< (PCC_IER) Interrupt Enable Register Offset */
#define PCC_IDR_REG_OFST (0x08) /**< (PCC_IDR) Interrupt Disable Register Offset */
#define PCC_IMR_REG_OFST (0x0C) /**< (PCC_IMR) Interrupt Mask Register Offset */
#define PCC_ISR_REG_OFST (0x10) /**< (PCC_ISR) Interrupt Status Register Offset */
#define PCC_RHR_REG_OFST (0x14) /**< (PCC_RHR) Reception Holding Register Offset */
#define PCC_WPMR_REG_OFST (0xE0) /**< (PCC_WPMR) Write Protection Mode Register Offset */
#define PCC_WPSR_REG_OFST (0xE4) /**< (PCC_WPSR) Write Protection Status Register Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief PCC register API structure */
typedef struct
{ /* Parallel Capture Controller */
__IO uint32_t PCC_MR; /**< Offset: 0x00 (R/W 32) Mode Register */
__O uint32_t PCC_IER; /**< Offset: 0x04 ( /W 32) Interrupt Enable Register */
__O uint32_t PCC_IDR; /**< Offset: 0x08 ( /W 32) Interrupt Disable Register */
__I uint32_t PCC_IMR; /**< Offset: 0x0C (R/ 32) Interrupt Mask Register */
__I uint32_t PCC_ISR; /**< Offset: 0x10 (R/ 32) Interrupt Status Register */
__I uint32_t PCC_RHR; /**< Offset: 0x14 (R/ 32) Reception Holding Register */
__I uint8_t Reserved1[0xC8];
__IO uint32_t PCC_WPMR; /**< Offset: 0xE0 (R/W 32) Write Protection Mode Register */
__I uint32_t PCC_WPSR; /**< Offset: 0xE4 (R/ 32) Write Protection Status Register */
} pcc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PCC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/pdec.h
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/**
* \brief Component description for PDEC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PDEC_COMPONENT_H_
#define _SAMD51_PDEC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PDEC */
/* ************************************************************************** */
/* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
#define PDEC_CTRLA_RESETVALUE _U_(0x00) /**< (PDEC_CTRLA) Control A Reset Value */
#define PDEC_CTRLA_SWRST_Pos _U_(0) /**< (PDEC_CTRLA) Software Reset Position */
#define PDEC_CTRLA_SWRST_Msk (_U_(0x1) << PDEC_CTRLA_SWRST_Pos) /**< (PDEC_CTRLA) Software Reset Mask */
#define PDEC_CTRLA_SWRST(value) (PDEC_CTRLA_SWRST_Msk & ((value) << PDEC_CTRLA_SWRST_Pos))
#define PDEC_CTRLA_ENABLE_Pos _U_(1) /**< (PDEC_CTRLA) Enable Position */
#define PDEC_CTRLA_ENABLE_Msk (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos) /**< (PDEC_CTRLA) Enable Mask */
#define PDEC_CTRLA_ENABLE(value) (PDEC_CTRLA_ENABLE_Msk & ((value) << PDEC_CTRLA_ENABLE_Pos))
#define PDEC_CTRLA_MODE_Pos _U_(2) /**< (PDEC_CTRLA) Operation Mode Position */
#define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) Operation Mode Mask */
#define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
#define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0) /**< (PDEC_CTRLA) QDEC operating mode */
#define PDEC_CTRLA_MODE_HALL_Val _U_(0x1) /**< (PDEC_CTRLA) HALL operating mode */
#define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2) /**< (PDEC_CTRLA) COUNTER operating mode */
#define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) QDEC operating mode Position */
#define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) HALL operating mode Position */
#define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos) /**< (PDEC_CTRLA) COUNTER operating mode Position */
#define PDEC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (PDEC_CTRLA) Run in Standby Position */
#define PDEC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos) /**< (PDEC_CTRLA) Run in Standby Mask */
#define PDEC_CTRLA_RUNSTDBY(value) (PDEC_CTRLA_RUNSTDBY_Msk & ((value) << PDEC_CTRLA_RUNSTDBY_Pos))
#define PDEC_CTRLA_CONF_Pos _U_(8) /**< (PDEC_CTRLA) PDEC Configuration Position */
#define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) PDEC Configuration Mask */
#define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
#define PDEC_CTRLA_CONF_X4_Val _U_(0x0) /**< (PDEC_CTRLA) Quadrature decoder direction */
#define PDEC_CTRLA_CONF_X4S_Val _U_(0x1) /**< (PDEC_CTRLA) Secure Quadrature decoder direction */
#define PDEC_CTRLA_CONF_X2_Val _U_(0x2) /**< (PDEC_CTRLA) Decoder direction */
#define PDEC_CTRLA_CONF_X2S_Val _U_(0x3) /**< (PDEC_CTRLA) Secure decoder direction */
#define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4) /**< (PDEC_CTRLA) Auto correction mode */
#define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Quadrature decoder direction Position */
#define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Secure Quadrature decoder direction Position */
#define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Decoder direction Position */
#define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Secure decoder direction Position */
#define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos) /**< (PDEC_CTRLA) Auto correction mode Position */
#define PDEC_CTRLA_ALOCK_Pos _U_(11) /**< (PDEC_CTRLA) Auto Lock Position */
#define PDEC_CTRLA_ALOCK_Msk (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos) /**< (PDEC_CTRLA) Auto Lock Mask */
#define PDEC_CTRLA_ALOCK(value) (PDEC_CTRLA_ALOCK_Msk & ((value) << PDEC_CTRLA_ALOCK_Pos))
#define PDEC_CTRLA_SWAP_Pos _U_(14) /**< (PDEC_CTRLA) PDEC Phase A and B Swap Position */
#define PDEC_CTRLA_SWAP_Msk (_U_(0x1) << PDEC_CTRLA_SWAP_Pos) /**< (PDEC_CTRLA) PDEC Phase A and B Swap Mask */
#define PDEC_CTRLA_SWAP(value) (PDEC_CTRLA_SWAP_Msk & ((value) << PDEC_CTRLA_SWAP_Pos))
#define PDEC_CTRLA_PEREN_Pos _U_(15) /**< (PDEC_CTRLA) Period Enable Position */
#define PDEC_CTRLA_PEREN_Msk (_U_(0x1) << PDEC_CTRLA_PEREN_Pos) /**< (PDEC_CTRLA) Period Enable Mask */
#define PDEC_CTRLA_PEREN(value) (PDEC_CTRLA_PEREN_Msk & ((value) << PDEC_CTRLA_PEREN_Pos))
#define PDEC_CTRLA_PINEN0_Pos _U_(16) /**< (PDEC_CTRLA) PDEC Input From Pin 0 Enable Position */
#define PDEC_CTRLA_PINEN0_Msk (_U_(0x1) << PDEC_CTRLA_PINEN0_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 0 Enable Mask */
#define PDEC_CTRLA_PINEN0(value) (PDEC_CTRLA_PINEN0_Msk & ((value) << PDEC_CTRLA_PINEN0_Pos))
#define PDEC_CTRLA_PINEN1_Pos _U_(17) /**< (PDEC_CTRLA) PDEC Input From Pin 1 Enable Position */
#define PDEC_CTRLA_PINEN1_Msk (_U_(0x1) << PDEC_CTRLA_PINEN1_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 1 Enable Mask */
#define PDEC_CTRLA_PINEN1(value) (PDEC_CTRLA_PINEN1_Msk & ((value) << PDEC_CTRLA_PINEN1_Pos))
#define PDEC_CTRLA_PINEN2_Pos _U_(18) /**< (PDEC_CTRLA) PDEC Input From Pin 2 Enable Position */
#define PDEC_CTRLA_PINEN2_Msk (_U_(0x1) << PDEC_CTRLA_PINEN2_Pos) /**< (PDEC_CTRLA) PDEC Input From Pin 2 Enable Mask */
#define PDEC_CTRLA_PINEN2(value) (PDEC_CTRLA_PINEN2_Msk & ((value) << PDEC_CTRLA_PINEN2_Pos))
#define PDEC_CTRLA_PINVEN0_Pos _U_(20) /**< (PDEC_CTRLA) IO Pin 0 Invert Enable Position */
#define PDEC_CTRLA_PINVEN0_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN0_Pos) /**< (PDEC_CTRLA) IO Pin 0 Invert Enable Mask */
#define PDEC_CTRLA_PINVEN0(value) (PDEC_CTRLA_PINVEN0_Msk & ((value) << PDEC_CTRLA_PINVEN0_Pos))
#define PDEC_CTRLA_PINVEN1_Pos _U_(21) /**< (PDEC_CTRLA) IO Pin 1 Invert Enable Position */
#define PDEC_CTRLA_PINVEN1_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN1_Pos) /**< (PDEC_CTRLA) IO Pin 1 Invert Enable Mask */
#define PDEC_CTRLA_PINVEN1(value) (PDEC_CTRLA_PINVEN1_Msk & ((value) << PDEC_CTRLA_PINVEN1_Pos))
#define PDEC_CTRLA_PINVEN2_Pos _U_(22) /**< (PDEC_CTRLA) IO Pin 2 Invert Enable Position */
#define PDEC_CTRLA_PINVEN2_Msk (_U_(0x1) << PDEC_CTRLA_PINVEN2_Pos) /**< (PDEC_CTRLA) IO Pin 2 Invert Enable Mask */
#define PDEC_CTRLA_PINVEN2(value) (PDEC_CTRLA_PINVEN2_Msk & ((value) << PDEC_CTRLA_PINVEN2_Pos))
#define PDEC_CTRLA_ANGULAR_Pos _U_(24) /**< (PDEC_CTRLA) Angular Counter Length Position */
#define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos) /**< (PDEC_CTRLA) Angular Counter Length Mask */
#define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
#define PDEC_CTRLA_MAXCMP_Pos _U_(28) /**< (PDEC_CTRLA) Maximum Consecutive Missing Pulses Position */
#define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos) /**< (PDEC_CTRLA) Maximum Consecutive Missing Pulses Mask */
#define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
#define PDEC_CTRLA_Msk _U_(0xF777CF4F) /**< (PDEC_CTRLA) Register Mask */
#define PDEC_CTRLA_PINEN_Pos _U_(16) /**< (PDEC_CTRLA Position) PDEC Input From Pin x Enable */
#define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos) /**< (PDEC_CTRLA Mask) PINEN */
#define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
#define PDEC_CTRLA_PINVEN_Pos _U_(20) /**< (PDEC_CTRLA Position) IO Pin x Invert Enable */
#define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos) /**< (PDEC_CTRLA Mask) PINVEN */
#define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
/* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
#define PDEC_CTRLBCLR_RESETVALUE _U_(0x00) /**< (PDEC_CTRLBCLR) Control B Clear Reset Value */
#define PDEC_CTRLBCLR_LUPD_Pos _U_(1) /**< (PDEC_CTRLBCLR) Lock Update Position */
#define PDEC_CTRLBCLR_LUPD_Msk (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos) /**< (PDEC_CTRLBCLR) Lock Update Mask */
#define PDEC_CTRLBCLR_LUPD(value) (PDEC_CTRLBCLR_LUPD_Msk & ((value) << PDEC_CTRLBCLR_LUPD_Pos))
#define PDEC_CTRLBCLR_CMD_Pos _U_(5) /**< (PDEC_CTRLBCLR) Command Position */
#define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Command Mask */
#define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
#define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< (PDEC_CTRLBCLR) No action */
#define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< (PDEC_CTRLBCLR) Force a counter restart or retrigger */
#define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2) /**< (PDEC_CTRLBCLR) Force update of double buffered registers */
#define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3) /**< (PDEC_CTRLBCLR) Force a read synchronization of COUNT */
#define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4) /**< (PDEC_CTRLBCLR) Start QDEC/HALL */
#define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5) /**< (PDEC_CTRLBCLR) Stop QDEC/HALL */
#define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) No action Position */
#define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force a counter restart or retrigger Position */
#define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force update of double buffered registers Position */
#define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Force a read synchronization of COUNT Position */
#define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Start QDEC/HALL Position */
#define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos) /**< (PDEC_CTRLBCLR) Stop QDEC/HALL Position */
#define PDEC_CTRLBCLR_Msk _U_(0xE2) /**< (PDEC_CTRLBCLR) Register Mask */
/* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
#define PDEC_CTRLBSET_RESETVALUE _U_(0x00) /**< (PDEC_CTRLBSET) Control B Set Reset Value */
#define PDEC_CTRLBSET_LUPD_Pos _U_(1) /**< (PDEC_CTRLBSET) Lock Update Position */
#define PDEC_CTRLBSET_LUPD_Msk (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos) /**< (PDEC_CTRLBSET) Lock Update Mask */
#define PDEC_CTRLBSET_LUPD(value) (PDEC_CTRLBSET_LUPD_Msk & ((value) << PDEC_CTRLBSET_LUPD_Pos))
#define PDEC_CTRLBSET_CMD_Pos _U_(5) /**< (PDEC_CTRLBSET) Command Position */
#define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Command Mask */
#define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
#define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< (PDEC_CTRLBSET) No action */
#define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< (PDEC_CTRLBSET) Force a counter restart or retrigger */
#define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2) /**< (PDEC_CTRLBSET) Force update of double buffered registers */
#define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3) /**< (PDEC_CTRLBSET) Force a read synchronization of COUNT */
#define PDEC_CTRLBSET_CMD_START_Val _U_(0x4) /**< (PDEC_CTRLBSET) Start QDEC/HALL */
#define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5) /**< (PDEC_CTRLBSET) Stop QDEC/HALL */
#define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) No action Position */
#define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force a counter restart or retrigger Position */
#define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force update of double buffered registers Position */
#define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Force a read synchronization of COUNT Position */
#define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Start QDEC/HALL Position */
#define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos) /**< (PDEC_CTRLBSET) Stop QDEC/HALL Position */
#define PDEC_CTRLBSET_Msk _U_(0xE2) /**< (PDEC_CTRLBSET) Register Mask */
/* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
#define PDEC_EVCTRL_RESETVALUE _U_(0x00) /**< (PDEC_EVCTRL) Event Control Reset Value */
#define PDEC_EVCTRL_EVACT_Pos _U_(0) /**< (PDEC_EVCTRL) Event Action Position */
#define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Event Action Mask */
#define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
#define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< (PDEC_EVCTRL) Event action disabled */
#define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< (PDEC_EVCTRL) Start, restart or retrigger on event */
#define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< (PDEC_EVCTRL) Count on event */
#define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Event action disabled Position */
#define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Start, restart or retrigger on event Position */
#define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos) /**< (PDEC_EVCTRL) Count on event Position */
#define PDEC_EVCTRL_EVINV_Pos _U_(2) /**< (PDEC_EVCTRL) Inverted Event Input Enable Position */
#define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos) /**< (PDEC_EVCTRL) Inverted Event Input Enable Mask */
#define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
#define PDEC_EVCTRL_EVEI_Pos _U_(5) /**< (PDEC_EVCTRL) Event Input Enable Position */
#define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos) /**< (PDEC_EVCTRL) Event Input Enable Mask */
#define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
#define PDEC_EVCTRL_OVFEO_Pos _U_(8) /**< (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Position */
#define PDEC_EVCTRL_OVFEO_Msk (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos) /**< (PDEC_EVCTRL) Overflow/Underflow Output Event Enable Mask */
#define PDEC_EVCTRL_OVFEO(value) (PDEC_EVCTRL_OVFEO_Msk & ((value) << PDEC_EVCTRL_OVFEO_Pos))
#define PDEC_EVCTRL_ERREO_Pos _U_(9) /**< (PDEC_EVCTRL) Error Output Event Enable Position */
#define PDEC_EVCTRL_ERREO_Msk (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos) /**< (PDEC_EVCTRL) Error Output Event Enable Mask */
#define PDEC_EVCTRL_ERREO(value) (PDEC_EVCTRL_ERREO_Msk & ((value) << PDEC_EVCTRL_ERREO_Pos))
#define PDEC_EVCTRL_DIREO_Pos _U_(10) /**< (PDEC_EVCTRL) Direction Output Event Enable Position */
#define PDEC_EVCTRL_DIREO_Msk (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos) /**< (PDEC_EVCTRL) Direction Output Event Enable Mask */
#define PDEC_EVCTRL_DIREO(value) (PDEC_EVCTRL_DIREO_Msk & ((value) << PDEC_EVCTRL_DIREO_Pos))
#define PDEC_EVCTRL_VLCEO_Pos _U_(11) /**< (PDEC_EVCTRL) Velocity Output Event Enable Position */
#define PDEC_EVCTRL_VLCEO_Msk (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos) /**< (PDEC_EVCTRL) Velocity Output Event Enable Mask */
#define PDEC_EVCTRL_VLCEO(value) (PDEC_EVCTRL_VLCEO_Msk & ((value) << PDEC_EVCTRL_VLCEO_Pos))
#define PDEC_EVCTRL_MCEO0_Pos _U_(12) /**< (PDEC_EVCTRL) Match Channel 0 Event Output Enable Position */
#define PDEC_EVCTRL_MCEO0_Msk (_U_(0x1) << PDEC_EVCTRL_MCEO0_Pos) /**< (PDEC_EVCTRL) Match Channel 0 Event Output Enable Mask */
#define PDEC_EVCTRL_MCEO0(value) (PDEC_EVCTRL_MCEO0_Msk & ((value) << PDEC_EVCTRL_MCEO0_Pos))
#define PDEC_EVCTRL_MCEO1_Pos _U_(13) /**< (PDEC_EVCTRL) Match Channel 1 Event Output Enable Position */
#define PDEC_EVCTRL_MCEO1_Msk (_U_(0x1) << PDEC_EVCTRL_MCEO1_Pos) /**< (PDEC_EVCTRL) Match Channel 1 Event Output Enable Mask */
#define PDEC_EVCTRL_MCEO1(value) (PDEC_EVCTRL_MCEO1_Msk & ((value) << PDEC_EVCTRL_MCEO1_Pos))
#define PDEC_EVCTRL_Msk _U_(0x3FFF) /**< (PDEC_EVCTRL) Register Mask */
#define PDEC_EVCTRL_MCEO_Pos _U_(12) /**< (PDEC_EVCTRL Position) Match Channel x Event Output Enable */
#define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos) /**< (PDEC_EVCTRL Mask) MCEO */
#define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
/* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#define PDEC_INTENCLR_RESETVALUE _U_(0x00) /**< (PDEC_INTENCLR) Interrupt Enable Clear Reset Value */
#define PDEC_INTENCLR_OVF_Pos _U_(0) /**< (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Position */
#define PDEC_INTENCLR_OVF_Msk (_U_(0x1) << PDEC_INTENCLR_OVF_Pos) /**< (PDEC_INTENCLR) Overflow/Underflow Interrupt Disable Mask */
#define PDEC_INTENCLR_OVF(value) (PDEC_INTENCLR_OVF_Msk & ((value) << PDEC_INTENCLR_OVF_Pos))
#define PDEC_INTENCLR_ERR_Pos _U_(1) /**< (PDEC_INTENCLR) Error Interrupt Disable Position */
#define PDEC_INTENCLR_ERR_Msk (_U_(0x1) << PDEC_INTENCLR_ERR_Pos) /**< (PDEC_INTENCLR) Error Interrupt Disable Mask */
#define PDEC_INTENCLR_ERR(value) (PDEC_INTENCLR_ERR_Msk & ((value) << PDEC_INTENCLR_ERR_Pos))
#define PDEC_INTENCLR_DIR_Pos _U_(2) /**< (PDEC_INTENCLR) Direction Interrupt Disable Position */
#define PDEC_INTENCLR_DIR_Msk (_U_(0x1) << PDEC_INTENCLR_DIR_Pos) /**< (PDEC_INTENCLR) Direction Interrupt Disable Mask */
#define PDEC_INTENCLR_DIR(value) (PDEC_INTENCLR_DIR_Msk & ((value) << PDEC_INTENCLR_DIR_Pos))
#define PDEC_INTENCLR_VLC_Pos _U_(3) /**< (PDEC_INTENCLR) Velocity Interrupt Disable Position */
#define PDEC_INTENCLR_VLC_Msk (_U_(0x1) << PDEC_INTENCLR_VLC_Pos) /**< (PDEC_INTENCLR) Velocity Interrupt Disable Mask */
#define PDEC_INTENCLR_VLC(value) (PDEC_INTENCLR_VLC_Msk & ((value) << PDEC_INTENCLR_VLC_Pos))
#define PDEC_INTENCLR_MC0_Pos _U_(4) /**< (PDEC_INTENCLR) Channel 0 Compare Match Disable Position */
#define PDEC_INTENCLR_MC0_Msk (_U_(0x1) << PDEC_INTENCLR_MC0_Pos) /**< (PDEC_INTENCLR) Channel 0 Compare Match Disable Mask */
#define PDEC_INTENCLR_MC0(value) (PDEC_INTENCLR_MC0_Msk & ((value) << PDEC_INTENCLR_MC0_Pos))
#define PDEC_INTENCLR_MC1_Pos _U_(5) /**< (PDEC_INTENCLR) Channel 1 Compare Match Disable Position */
#define PDEC_INTENCLR_MC1_Msk (_U_(0x1) << PDEC_INTENCLR_MC1_Pos) /**< (PDEC_INTENCLR) Channel 1 Compare Match Disable Mask */
#define PDEC_INTENCLR_MC1(value) (PDEC_INTENCLR_MC1_Msk & ((value) << PDEC_INTENCLR_MC1_Pos))
#define PDEC_INTENCLR_Msk _U_(0x3F) /**< (PDEC_INTENCLR) Register Mask */
#define PDEC_INTENCLR_MC_Pos _U_(4) /**< (PDEC_INTENCLR Position) Channel x Compare Match Disable */
#define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos) /**< (PDEC_INTENCLR Mask) MC */
#define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
/* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#define PDEC_INTENSET_RESETVALUE _U_(0x00) /**< (PDEC_INTENSET) Interrupt Enable Set Reset Value */
#define PDEC_INTENSET_OVF_Pos _U_(0) /**< (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Position */
#define PDEC_INTENSET_OVF_Msk (_U_(0x1) << PDEC_INTENSET_OVF_Pos) /**< (PDEC_INTENSET) Overflow/Underflow Interrupt Enable Mask */
#define PDEC_INTENSET_OVF(value) (PDEC_INTENSET_OVF_Msk & ((value) << PDEC_INTENSET_OVF_Pos))
#define PDEC_INTENSET_ERR_Pos _U_(1) /**< (PDEC_INTENSET) Error Interrupt Enable Position */
#define PDEC_INTENSET_ERR_Msk (_U_(0x1) << PDEC_INTENSET_ERR_Pos) /**< (PDEC_INTENSET) Error Interrupt Enable Mask */
#define PDEC_INTENSET_ERR(value) (PDEC_INTENSET_ERR_Msk & ((value) << PDEC_INTENSET_ERR_Pos))
#define PDEC_INTENSET_DIR_Pos _U_(2) /**< (PDEC_INTENSET) Direction Interrupt Enable Position */
#define PDEC_INTENSET_DIR_Msk (_U_(0x1) << PDEC_INTENSET_DIR_Pos) /**< (PDEC_INTENSET) Direction Interrupt Enable Mask */
#define PDEC_INTENSET_DIR(value) (PDEC_INTENSET_DIR_Msk & ((value) << PDEC_INTENSET_DIR_Pos))
#define PDEC_INTENSET_VLC_Pos _U_(3) /**< (PDEC_INTENSET) Velocity Interrupt Enable Position */
#define PDEC_INTENSET_VLC_Msk (_U_(0x1) << PDEC_INTENSET_VLC_Pos) /**< (PDEC_INTENSET) Velocity Interrupt Enable Mask */
#define PDEC_INTENSET_VLC(value) (PDEC_INTENSET_VLC_Msk & ((value) << PDEC_INTENSET_VLC_Pos))
#define PDEC_INTENSET_MC0_Pos _U_(4) /**< (PDEC_INTENSET) Channel 0 Compare Match Enable Position */
#define PDEC_INTENSET_MC0_Msk (_U_(0x1) << PDEC_INTENSET_MC0_Pos) /**< (PDEC_INTENSET) Channel 0 Compare Match Enable Mask */
#define PDEC_INTENSET_MC0(value) (PDEC_INTENSET_MC0_Msk & ((value) << PDEC_INTENSET_MC0_Pos))
#define PDEC_INTENSET_MC1_Pos _U_(5) /**< (PDEC_INTENSET) Channel 1 Compare Match Enable Position */
#define PDEC_INTENSET_MC1_Msk (_U_(0x1) << PDEC_INTENSET_MC1_Pos) /**< (PDEC_INTENSET) Channel 1 Compare Match Enable Mask */
#define PDEC_INTENSET_MC1(value) (PDEC_INTENSET_MC1_Msk & ((value) << PDEC_INTENSET_MC1_Pos))
#define PDEC_INTENSET_Msk _U_(0x3F) /**< (PDEC_INTENSET) Register Mask */
#define PDEC_INTENSET_MC_Pos _U_(4) /**< (PDEC_INTENSET Position) Channel x Compare Match Enable */
#define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos) /**< (PDEC_INTENSET Mask) MC */
#define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
/* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#define PDEC_INTFLAG_RESETVALUE _U_(0x00) /**< (PDEC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define PDEC_INTFLAG_OVF_Pos _U_(0) /**< (PDEC_INTFLAG) Overflow/Underflow Position */
#define PDEC_INTFLAG_OVF_Msk (_U_(0x1) << PDEC_INTFLAG_OVF_Pos) /**< (PDEC_INTFLAG) Overflow/Underflow Mask */
#define PDEC_INTFLAG_OVF(value) (PDEC_INTFLAG_OVF_Msk & ((value) << PDEC_INTFLAG_OVF_Pos))
#define PDEC_INTFLAG_ERR_Pos _U_(1) /**< (PDEC_INTFLAG) Error Position */
#define PDEC_INTFLAG_ERR_Msk (_U_(0x1) << PDEC_INTFLAG_ERR_Pos) /**< (PDEC_INTFLAG) Error Mask */
#define PDEC_INTFLAG_ERR(value) (PDEC_INTFLAG_ERR_Msk & ((value) << PDEC_INTFLAG_ERR_Pos))
#define PDEC_INTFLAG_DIR_Pos _U_(2) /**< (PDEC_INTFLAG) Direction Change Position */
#define PDEC_INTFLAG_DIR_Msk (_U_(0x1) << PDEC_INTFLAG_DIR_Pos) /**< (PDEC_INTFLAG) Direction Change Mask */
#define PDEC_INTFLAG_DIR(value) (PDEC_INTFLAG_DIR_Msk & ((value) << PDEC_INTFLAG_DIR_Pos))
#define PDEC_INTFLAG_VLC_Pos _U_(3) /**< (PDEC_INTFLAG) Velocity Position */
#define PDEC_INTFLAG_VLC_Msk (_U_(0x1) << PDEC_INTFLAG_VLC_Pos) /**< (PDEC_INTFLAG) Velocity Mask */
#define PDEC_INTFLAG_VLC(value) (PDEC_INTFLAG_VLC_Msk & ((value) << PDEC_INTFLAG_VLC_Pos))
#define PDEC_INTFLAG_MC0_Pos _U_(4) /**< (PDEC_INTFLAG) Channel 0 Compare Match Position */
#define PDEC_INTFLAG_MC0_Msk (_U_(0x1) << PDEC_INTFLAG_MC0_Pos) /**< (PDEC_INTFLAG) Channel 0 Compare Match Mask */
#define PDEC_INTFLAG_MC0(value) (PDEC_INTFLAG_MC0_Msk & ((value) << PDEC_INTFLAG_MC0_Pos))
#define PDEC_INTFLAG_MC1_Pos _U_(5) /**< (PDEC_INTFLAG) Channel 1 Compare Match Position */
#define PDEC_INTFLAG_MC1_Msk (_U_(0x1) << PDEC_INTFLAG_MC1_Pos) /**< (PDEC_INTFLAG) Channel 1 Compare Match Mask */
#define PDEC_INTFLAG_MC1(value) (PDEC_INTFLAG_MC1_Msk & ((value) << PDEC_INTFLAG_MC1_Pos))
#define PDEC_INTFLAG_Msk _U_(0x3F) /**< (PDEC_INTFLAG) Register Mask */
#define PDEC_INTFLAG_MC_Pos _U_(4) /**< (PDEC_INTFLAG Position) Channel x Compare Match */
#define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos) /**< (PDEC_INTFLAG Mask) MC */
#define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
/* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
#define PDEC_STATUS_RESETVALUE _U_(0x40) /**< (PDEC_STATUS) Status Reset Value */
#define PDEC_STATUS_QERR_Pos _U_(0) /**< (PDEC_STATUS) Quadrature Error Flag Position */
#define PDEC_STATUS_QERR_Msk (_U_(0x1) << PDEC_STATUS_QERR_Pos) /**< (PDEC_STATUS) Quadrature Error Flag Mask */
#define PDEC_STATUS_QERR(value) (PDEC_STATUS_QERR_Msk & ((value) << PDEC_STATUS_QERR_Pos))
#define PDEC_STATUS_IDXERR_Pos _U_(1) /**< (PDEC_STATUS) Index Error Flag Position */
#define PDEC_STATUS_IDXERR_Msk (_U_(0x1) << PDEC_STATUS_IDXERR_Pos) /**< (PDEC_STATUS) Index Error Flag Mask */
#define PDEC_STATUS_IDXERR(value) (PDEC_STATUS_IDXERR_Msk & ((value) << PDEC_STATUS_IDXERR_Pos))
#define PDEC_STATUS_MPERR_Pos _U_(2) /**< (PDEC_STATUS) Missing Pulse Error flag Position */
#define PDEC_STATUS_MPERR_Msk (_U_(0x1) << PDEC_STATUS_MPERR_Pos) /**< (PDEC_STATUS) Missing Pulse Error flag Mask */
#define PDEC_STATUS_MPERR(value) (PDEC_STATUS_MPERR_Msk & ((value) << PDEC_STATUS_MPERR_Pos))
#define PDEC_STATUS_WINERR_Pos _U_(4) /**< (PDEC_STATUS) Window Error Flag Position */
#define PDEC_STATUS_WINERR_Msk (_U_(0x1) << PDEC_STATUS_WINERR_Pos) /**< (PDEC_STATUS) Window Error Flag Mask */
#define PDEC_STATUS_WINERR(value) (PDEC_STATUS_WINERR_Msk & ((value) << PDEC_STATUS_WINERR_Pos))
#define PDEC_STATUS_HERR_Pos _U_(5) /**< (PDEC_STATUS) Hall Error Flag Position */
#define PDEC_STATUS_HERR_Msk (_U_(0x1) << PDEC_STATUS_HERR_Pos) /**< (PDEC_STATUS) Hall Error Flag Mask */
#define PDEC_STATUS_HERR(value) (PDEC_STATUS_HERR_Msk & ((value) << PDEC_STATUS_HERR_Pos))
#define PDEC_STATUS_STOP_Pos _U_(6) /**< (PDEC_STATUS) Stop Position */
#define PDEC_STATUS_STOP_Msk (_U_(0x1) << PDEC_STATUS_STOP_Pos) /**< (PDEC_STATUS) Stop Mask */
#define PDEC_STATUS_STOP(value) (PDEC_STATUS_STOP_Msk & ((value) << PDEC_STATUS_STOP_Pos))
#define PDEC_STATUS_DIR_Pos _U_(7) /**< (PDEC_STATUS) Direction Status Flag Position */
#define PDEC_STATUS_DIR_Msk (_U_(0x1) << PDEC_STATUS_DIR_Pos) /**< (PDEC_STATUS) Direction Status Flag Mask */
#define PDEC_STATUS_DIR(value) (PDEC_STATUS_DIR_Msk & ((value) << PDEC_STATUS_DIR_Pos))
#define PDEC_STATUS_PRESCBUFV_Pos _U_(8) /**< (PDEC_STATUS) Prescaler Buffer Valid Position */
#define PDEC_STATUS_PRESCBUFV_Msk (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos) /**< (PDEC_STATUS) Prescaler Buffer Valid Mask */
#define PDEC_STATUS_PRESCBUFV(value) (PDEC_STATUS_PRESCBUFV_Msk & ((value) << PDEC_STATUS_PRESCBUFV_Pos))
#define PDEC_STATUS_FILTERBUFV_Pos _U_(9) /**< (PDEC_STATUS) Filter Buffer Valid Position */
#define PDEC_STATUS_FILTERBUFV_Msk (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos) /**< (PDEC_STATUS) Filter Buffer Valid Mask */
#define PDEC_STATUS_FILTERBUFV(value) (PDEC_STATUS_FILTERBUFV_Msk & ((value) << PDEC_STATUS_FILTERBUFV_Pos))
#define PDEC_STATUS_CCBUFV0_Pos _U_(12) /**< (PDEC_STATUS) Compare Channel 0 Buffer Valid Position */
#define PDEC_STATUS_CCBUFV0_Msk (_U_(0x1) << PDEC_STATUS_CCBUFV0_Pos) /**< (PDEC_STATUS) Compare Channel 0 Buffer Valid Mask */
#define PDEC_STATUS_CCBUFV0(value) (PDEC_STATUS_CCBUFV0_Msk & ((value) << PDEC_STATUS_CCBUFV0_Pos))
#define PDEC_STATUS_CCBUFV1_Pos _U_(13) /**< (PDEC_STATUS) Compare Channel 1 Buffer Valid Position */
#define PDEC_STATUS_CCBUFV1_Msk (_U_(0x1) << PDEC_STATUS_CCBUFV1_Pos) /**< (PDEC_STATUS) Compare Channel 1 Buffer Valid Mask */
#define PDEC_STATUS_CCBUFV1(value) (PDEC_STATUS_CCBUFV1_Msk & ((value) << PDEC_STATUS_CCBUFV1_Pos))
#define PDEC_STATUS_Msk _U_(0x33F7) /**< (PDEC_STATUS) Register Mask */
#define PDEC_STATUS_CCBUFV_Pos _U_(12) /**< (PDEC_STATUS Position) Compare Channel x Buffer Valid */
#define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos) /**< (PDEC_STATUS Mask) CCBUFV */
#define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
/* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
#define PDEC_DBGCTRL_RESETVALUE _U_(0x00) /**< (PDEC_DBGCTRL) Debug Control Reset Value */
#define PDEC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (PDEC_DBGCTRL) Debug Run Mode Position */
#define PDEC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos) /**< (PDEC_DBGCTRL) Debug Run Mode Mask */
#define PDEC_DBGCTRL_DBGRUN(value) (PDEC_DBGCTRL_DBGRUN_Msk & ((value) << PDEC_DBGCTRL_DBGRUN_Pos))
#define PDEC_DBGCTRL_Msk _U_(0x01) /**< (PDEC_DBGCTRL) Register Mask */
/* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) ( R/ 32) Synchronization Status -------- */
#define PDEC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (PDEC_SYNCBUSY) Synchronization Status Reset Value */
#define PDEC_SYNCBUSY_SWRST_Pos _U_(0) /**< (PDEC_SYNCBUSY) Software Reset Synchronization Busy Position */
#define PDEC_SYNCBUSY_SWRST_Msk (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos) /**< (PDEC_SYNCBUSY) Software Reset Synchronization Busy Mask */
#define PDEC_SYNCBUSY_SWRST(value) (PDEC_SYNCBUSY_SWRST_Msk & ((value) << PDEC_SYNCBUSY_SWRST_Pos))
#define PDEC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (PDEC_SYNCBUSY) Enable Synchronization Busy Position */
#define PDEC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos) /**< (PDEC_SYNCBUSY) Enable Synchronization Busy Mask */
#define PDEC_SYNCBUSY_ENABLE(value) (PDEC_SYNCBUSY_ENABLE_Msk & ((value) << PDEC_SYNCBUSY_ENABLE_Pos))
#define PDEC_SYNCBUSY_CTRLB_Pos _U_(2) /**< (PDEC_SYNCBUSY) Control B Synchronization Busy Position */
#define PDEC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos) /**< (PDEC_SYNCBUSY) Control B Synchronization Busy Mask */
#define PDEC_SYNCBUSY_CTRLB(value) (PDEC_SYNCBUSY_CTRLB_Msk & ((value) << PDEC_SYNCBUSY_CTRLB_Pos))
#define PDEC_SYNCBUSY_STATUS_Pos _U_(3) /**< (PDEC_SYNCBUSY) Status Synchronization Busy Position */
#define PDEC_SYNCBUSY_STATUS_Msk (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos) /**< (PDEC_SYNCBUSY) Status Synchronization Busy Mask */
#define PDEC_SYNCBUSY_STATUS(value) (PDEC_SYNCBUSY_STATUS_Msk & ((value) << PDEC_SYNCBUSY_STATUS_Pos))
#define PDEC_SYNCBUSY_PRESC_Pos _U_(4) /**< (PDEC_SYNCBUSY) Prescaler Synchronization Busy Position */
#define PDEC_SYNCBUSY_PRESC_Msk (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos) /**< (PDEC_SYNCBUSY) Prescaler Synchronization Busy Mask */
#define PDEC_SYNCBUSY_PRESC(value) (PDEC_SYNCBUSY_PRESC_Msk & ((value) << PDEC_SYNCBUSY_PRESC_Pos))
#define PDEC_SYNCBUSY_FILTER_Pos _U_(5) /**< (PDEC_SYNCBUSY) Filter Synchronization Busy Position */
#define PDEC_SYNCBUSY_FILTER_Msk (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos) /**< (PDEC_SYNCBUSY) Filter Synchronization Busy Mask */
#define PDEC_SYNCBUSY_FILTER(value) (PDEC_SYNCBUSY_FILTER_Msk & ((value) << PDEC_SYNCBUSY_FILTER_Pos))
#define PDEC_SYNCBUSY_COUNT_Pos _U_(6) /**< (PDEC_SYNCBUSY) Count Synchronization Busy Position */
#define PDEC_SYNCBUSY_COUNT_Msk (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos) /**< (PDEC_SYNCBUSY) Count Synchronization Busy Mask */
#define PDEC_SYNCBUSY_COUNT(value) (PDEC_SYNCBUSY_COUNT_Msk & ((value) << PDEC_SYNCBUSY_COUNT_Pos))
#define PDEC_SYNCBUSY_CC0_Pos _U_(7) /**< (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Position */
#define PDEC_SYNCBUSY_CC0_Msk (_U_(0x1) << PDEC_SYNCBUSY_CC0_Pos) /**< (PDEC_SYNCBUSY) Compare Channel 0 Synchronization Busy Mask */
#define PDEC_SYNCBUSY_CC0(value) (PDEC_SYNCBUSY_CC0_Msk & ((value) << PDEC_SYNCBUSY_CC0_Pos))
#define PDEC_SYNCBUSY_CC1_Pos _U_(8) /**< (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Position */
#define PDEC_SYNCBUSY_CC1_Msk (_U_(0x1) << PDEC_SYNCBUSY_CC1_Pos) /**< (PDEC_SYNCBUSY) Compare Channel 1 Synchronization Busy Mask */
#define PDEC_SYNCBUSY_CC1(value) (PDEC_SYNCBUSY_CC1_Msk & ((value) << PDEC_SYNCBUSY_CC1_Pos))
#define PDEC_SYNCBUSY_Msk _U_(0x000001FF) /**< (PDEC_SYNCBUSY) Register Mask */
#define PDEC_SYNCBUSY_CC_Pos _U_(7) /**< (PDEC_SYNCBUSY Position) Compare Channel x Synchronization Busy */
#define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos) /**< (PDEC_SYNCBUSY Mask) CC */
#define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
/* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
#define PDEC_PRESC_RESETVALUE _U_(0x00) /**< (PDEC_PRESC) Prescaler Value Reset Value */
#define PDEC_PRESC_PRESC_Pos _U_(0) /**< (PDEC_PRESC) Prescaler Value Position */
#define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Prescaler Value Mask */
#define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
#define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0) /**< (PDEC_PRESC) No division */
#define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1) /**< (PDEC_PRESC) Divide by 2 */
#define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2) /**< (PDEC_PRESC) Divide by 4 */
#define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3) /**< (PDEC_PRESC) Divide by 8 */
#define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4) /**< (PDEC_PRESC) Divide by 16 */
#define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5) /**< (PDEC_PRESC) Divide by 32 */
#define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6) /**< (PDEC_PRESC) Divide by 64 */
#define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7) /**< (PDEC_PRESC) Divide by 128 */
#define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8) /**< (PDEC_PRESC) Divide by 256 */
#define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9) /**< (PDEC_PRESC) Divide by 512 */
#define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA) /**< (PDEC_PRESC) Divide by 1024 */
#define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) No division Position */
#define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 2 Position */
#define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 4 Position */
#define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 8 Position */
#define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 16 Position */
#define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 32 Position */
#define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 64 Position */
#define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 128 Position */
#define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 256 Position */
#define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 512 Position */
#define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos) /**< (PDEC_PRESC) Divide by 1024 Position */
#define PDEC_PRESC_Msk _U_(0x0F) /**< (PDEC_PRESC) Register Mask */
/* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
#define PDEC_FILTER_RESETVALUE _U_(0x00) /**< (PDEC_FILTER) Filter Value Reset Value */
#define PDEC_FILTER_FILTER_Pos _U_(0) /**< (PDEC_FILTER) Filter Value Position */
#define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos) /**< (PDEC_FILTER) Filter Value Mask */
#define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
#define PDEC_FILTER_Msk _U_(0xFF) /**< (PDEC_FILTER) Register Mask */
/* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
#define PDEC_PRESCBUF_RESETVALUE _U_(0x00) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Reset Value */
#define PDEC_PRESCBUF_PRESCBUF_Pos _U_(0) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Position */
#define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Mask */
#define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
#define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0) /**< (PDEC_PRESCBUF) No division */
#define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1) /**< (PDEC_PRESCBUF) Divide by 2 */
#define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2) /**< (PDEC_PRESCBUF) Divide by 4 */
#define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3) /**< (PDEC_PRESCBUF) Divide by 8 */
#define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4) /**< (PDEC_PRESCBUF) Divide by 16 */
#define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5) /**< (PDEC_PRESCBUF) Divide by 32 */
#define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6) /**< (PDEC_PRESCBUF) Divide by 64 */
#define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7) /**< (PDEC_PRESCBUF) Divide by 128 */
#define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8) /**< (PDEC_PRESCBUF) Divide by 256 */
#define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9) /**< (PDEC_PRESCBUF) Divide by 512 */
#define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA) /**< (PDEC_PRESCBUF) Divide by 1024 */
#define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) No division Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 2 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 4 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 8 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 16 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 32 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 64 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 128 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 256 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 512 Position */
#define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos) /**< (PDEC_PRESCBUF) Divide by 1024 Position */
#define PDEC_PRESCBUF_Msk _U_(0x0F) /**< (PDEC_PRESCBUF) Register Mask */
/* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
#define PDEC_FILTERBUF_RESETVALUE _U_(0x00) /**< (PDEC_FILTERBUF) Filter Buffer Value Reset Value */
#define PDEC_FILTERBUF_FILTERBUF_Pos _U_(0) /**< (PDEC_FILTERBUF) Filter Buffer Value Position */
#define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos) /**< (PDEC_FILTERBUF) Filter Buffer Value Mask */
#define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
#define PDEC_FILTERBUF_Msk _U_(0xFF) /**< (PDEC_FILTERBUF) Register Mask */
/* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
#define PDEC_COUNT_RESETVALUE _U_(0x00) /**< (PDEC_COUNT) Counter Value Reset Value */
#define PDEC_COUNT_COUNT_Pos _U_(0) /**< (PDEC_COUNT) Counter Value Position */
#define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos) /**< (PDEC_COUNT) Counter Value Mask */
#define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
#define PDEC_COUNT_Msk _U_(0x0000FFFF) /**< (PDEC_COUNT) Register Mask */
/* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
#define PDEC_CC_RESETVALUE _U_(0x00) /**< (PDEC_CC) Channel n Compare Value Reset Value */
#define PDEC_CC_CC_Pos _U_(0) /**< (PDEC_CC) Channel Compare Value Position */
#define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos) /**< (PDEC_CC) Channel Compare Value Mask */
#define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
#define PDEC_CC_Msk _U_(0x0000FFFF) /**< (PDEC_CC) Register Mask */
/* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
#define PDEC_CCBUF_RESETVALUE _U_(0x00) /**< (PDEC_CCBUF) Channel Compare Buffer Value Reset Value */
#define PDEC_CCBUF_CCBUF_Pos _U_(0) /**< (PDEC_CCBUF) Channel Compare Buffer Value Position */
#define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos) /**< (PDEC_CCBUF) Channel Compare Buffer Value Mask */
#define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
#define PDEC_CCBUF_Msk _U_(0x0000FFFF) /**< (PDEC_CCBUF) Register Mask */
/** \brief PDEC register offsets definitions */
#define PDEC_CTRLA_REG_OFST (0x00) /**< (PDEC_CTRLA) Control A Offset */
#define PDEC_CTRLBCLR_REG_OFST (0x04) /**< (PDEC_CTRLBCLR) Control B Clear Offset */
#define PDEC_CTRLBSET_REG_OFST (0x05) /**< (PDEC_CTRLBSET) Control B Set Offset */
#define PDEC_EVCTRL_REG_OFST (0x06) /**< (PDEC_EVCTRL) Event Control Offset */
#define PDEC_INTENCLR_REG_OFST (0x08) /**< (PDEC_INTENCLR) Interrupt Enable Clear Offset */
#define PDEC_INTENSET_REG_OFST (0x09) /**< (PDEC_INTENSET) Interrupt Enable Set Offset */
#define PDEC_INTFLAG_REG_OFST (0x0A) /**< (PDEC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define PDEC_STATUS_REG_OFST (0x0C) /**< (PDEC_STATUS) Status Offset */
#define PDEC_DBGCTRL_REG_OFST (0x0F) /**< (PDEC_DBGCTRL) Debug Control Offset */
#define PDEC_SYNCBUSY_REG_OFST (0x10) /**< (PDEC_SYNCBUSY) Synchronization Status Offset */
#define PDEC_PRESC_REG_OFST (0x14) /**< (PDEC_PRESC) Prescaler Value Offset */
#define PDEC_FILTER_REG_OFST (0x15) /**< (PDEC_FILTER) Filter Value Offset */
#define PDEC_PRESCBUF_REG_OFST (0x18) /**< (PDEC_PRESCBUF) Prescaler Buffer Value Offset */
#define PDEC_FILTERBUF_REG_OFST (0x19) /**< (PDEC_FILTERBUF) Filter Buffer Value Offset */
#define PDEC_COUNT_REG_OFST (0x1C) /**< (PDEC_COUNT) Counter Value Offset */
#define PDEC_CC_REG_OFST (0x20) /**< (PDEC_CC) Channel n Compare Value Offset */
#define PDEC_CCBUF_REG_OFST (0x30) /**< (PDEC_CCBUF) Channel Compare Buffer Value Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief PDEC register API structure */
typedef struct
{ /* Quadrature Decodeur */
__IO uint32_t PDEC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t PDEC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
__IO uint8_t PDEC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
__IO uint16_t PDEC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */
__IO uint8_t PDEC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO uint8_t PDEC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO uint8_t PDEC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t Reserved1[0x01];
__IO uint16_t PDEC_STATUS; /**< Offset: 0x0C (R/W 16) Status */
__I uint8_t Reserved2[0x01];
__IO uint8_t PDEC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
__I uint32_t PDEC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */
__IO uint8_t PDEC_PRESC; /**< Offset: 0x14 (R/W 8) Prescaler Value */
__IO uint8_t PDEC_FILTER; /**< Offset: 0x15 (R/W 8) Filter Value */
__I uint8_t Reserved3[0x02];
__IO uint8_t PDEC_PRESCBUF; /**< Offset: 0x18 (R/W 8) Prescaler Buffer Value */
__IO uint8_t PDEC_FILTERBUF; /**< Offset: 0x19 (R/W 8) Filter Buffer Value */
__I uint8_t Reserved4[0x02];
__IO uint32_t PDEC_COUNT; /**< Offset: 0x1C (R/W 32) Counter Value */
__IO uint32_t PDEC_CC[2]; /**< Offset: 0x20 (R/W 32) Channel n Compare Value */
__I uint8_t Reserved5[0x08];
__IO uint32_t PDEC_CCBUF[2]; /**< Offset: 0x30 (R/W 32) Channel Compare Buffer Value */
} pdec_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PDEC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/pm.h
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/**
* \brief Component description for PM
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PM_COMPONENT_H_
#define _SAMD51_PM_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PM */
/* ************************************************************************** */
/* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
#define PM_CTRLA_RESETVALUE _U_(0x00) /**< (PM_CTRLA) Control A Reset Value */
#define PM_CTRLA_IORET_Pos _U_(2) /**< (PM_CTRLA) I/O Retention Position */
#define PM_CTRLA_IORET_Msk (_U_(0x1) << PM_CTRLA_IORET_Pos) /**< (PM_CTRLA) I/O Retention Mask */
#define PM_CTRLA_IORET(value) (PM_CTRLA_IORET_Msk & ((value) << PM_CTRLA_IORET_Pos))
#define PM_CTRLA_Msk _U_(0x04) /**< (PM_CTRLA) Register Mask */
/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
#define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< (PM_SLEEPCFG) Sleep Configuration Reset Value */
#define PM_SLEEPCFG_SLEEPMODE_Pos _U_(0) /**< (PM_SLEEPCFG) Sleep Mode Position */
#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) Sleep Mode Mask */
#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
#define PM_SLEEPCFG_SLEEPMODE_IDLE_Val _U_(0x2) /**< (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF */
#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< (PM_SLEEPCFG) All Clocks are OFF */
#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5) /**< (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs */
#define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6) /**< (PM_SLEEPCFG) Only Backup domain is powered ON */
#define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7) /**< (PM_SLEEPCFG) All power domains are powered OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) CPU, AHBx, and APBx clocks are OFF Position */
#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) All Clocks are OFF Position */
#define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs Position */
#define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) Only Backup domain is powered ON Position */
#define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) All power domains are powered OFF Position */
#define PM_SLEEPCFG_Msk _U_(0x07) /**< (PM_SLEEPCFG) Register Mask */
/* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#define PM_INTENCLR_RESETVALUE _U_(0x00) /**< (PM_INTENCLR) Interrupt Enable Clear Reset Value */
#define PM_INTENCLR_SLEEPRDY_Pos _U_(0) /**< (PM_INTENCLR) Sleep Mode Entry Ready Enable Position */
#define PM_INTENCLR_SLEEPRDY_Msk (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos) /**< (PM_INTENCLR) Sleep Mode Entry Ready Enable Mask */
#define PM_INTENCLR_SLEEPRDY(value) (PM_INTENCLR_SLEEPRDY_Msk & ((value) << PM_INTENCLR_SLEEPRDY_Pos))
#define PM_INTENCLR_Msk _U_(0x01) /**< (PM_INTENCLR) Register Mask */
/* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#define PM_INTENSET_RESETVALUE _U_(0x00) /**< (PM_INTENSET) Interrupt Enable Set Reset Value */
#define PM_INTENSET_SLEEPRDY_Pos _U_(0) /**< (PM_INTENSET) Sleep Mode Entry Ready Enable Position */
#define PM_INTENSET_SLEEPRDY_Msk (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos) /**< (PM_INTENSET) Sleep Mode Entry Ready Enable Mask */
#define PM_INTENSET_SLEEPRDY(value) (PM_INTENSET_SLEEPRDY_Msk & ((value) << PM_INTENSET_SLEEPRDY_Pos))
#define PM_INTENSET_Msk _U_(0x01) /**< (PM_INTENSET) Register Mask */
/* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#define PM_INTFLAG_RESETVALUE _U_(0x00) /**< (PM_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define PM_INTFLAG_SLEEPRDY_Pos _U_(0) /**< (PM_INTFLAG) Sleep Mode Entry Ready Position */
#define PM_INTFLAG_SLEEPRDY_Msk (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos) /**< (PM_INTFLAG) Sleep Mode Entry Ready Mask */
#define PM_INTFLAG_SLEEPRDY(value) (PM_INTFLAG_SLEEPRDY_Msk & ((value) << PM_INTFLAG_SLEEPRDY_Pos))
#define PM_INTFLAG_Msk _U_(0x01) /**< (PM_INTFLAG) Register Mask */
/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
#define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< (PM_STDBYCFG) Standby Configuration Reset Value */
#define PM_STDBYCFG_RAMCFG_Pos _U_(0) /**< (PM_STDBYCFG) Ram Configuration Position */
#define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos) /**< (PM_STDBYCFG) Ram Configuration Mask */
#define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
#define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0) /**< (PM_STDBYCFG) All the system RAM is retained */
#define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< (PM_STDBYCFG) Only the first 32Kbytes of the system RAM is retained */
#define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2) /**< (PM_STDBYCFG) All the system RAM is turned OFF */
#define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos) /**< (PM_STDBYCFG) All the system RAM is retained Position */
#define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos) /**< (PM_STDBYCFG) Only the first 32Kbytes of the system RAM is retained Position */
#define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos) /**< (PM_STDBYCFG) All the system RAM is turned OFF Position */
#define PM_STDBYCFG_FASTWKUP_Pos _U_(4) /**< (PM_STDBYCFG) Fast Wakeup Position */
#define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos) /**< (PM_STDBYCFG) Fast Wakeup Mask */
#define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
#define PM_STDBYCFG_FASTWKUP_NO_Val _U_(0x0) /**< (PM_STDBYCFG) Fast Wakeup is disabled */
#define PM_STDBYCFG_FASTWKUP_NVM_Val _U_(0x1) /**< (PM_STDBYCFG) Fast Wakeup is enabled on NVM */
#define PM_STDBYCFG_FASTWKUP_MAINVREG_Val _U_(0x2) /**< (PM_STDBYCFG) Fast Wakeup is enabled on the main voltage regulator (MAINVREG) */
#define PM_STDBYCFG_FASTWKUP_BOTH_Val _U_(0x3) /**< (PM_STDBYCFG) Fast Wakeup is enabled on both NVM and MAINVREG */
#define PM_STDBYCFG_FASTWKUP_NO (PM_STDBYCFG_FASTWKUP_NO_Val << PM_STDBYCFG_FASTWKUP_Pos) /**< (PM_STDBYCFG) Fast Wakeup is disabled Position */
#define PM_STDBYCFG_FASTWKUP_NVM (PM_STDBYCFG_FASTWKUP_NVM_Val << PM_STDBYCFG_FASTWKUP_Pos) /**< (PM_STDBYCFG) Fast Wakeup is enabled on NVM Position */
#define PM_STDBYCFG_FASTWKUP_MAINVREG (PM_STDBYCFG_FASTWKUP_MAINVREG_Val << PM_STDBYCFG_FASTWKUP_Pos) /**< (PM_STDBYCFG) Fast Wakeup is enabled on the main voltage regulator (MAINVREG) Position */
#define PM_STDBYCFG_FASTWKUP_BOTH (PM_STDBYCFG_FASTWKUP_BOTH_Val << PM_STDBYCFG_FASTWKUP_Pos) /**< (PM_STDBYCFG) Fast Wakeup is enabled on both NVM and MAINVREG Position */
#define PM_STDBYCFG_Msk _U_(0x33) /**< (PM_STDBYCFG) Register Mask */
/* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
#define PM_HIBCFG_RESETVALUE _U_(0x00) /**< (PM_HIBCFG) Hibernate Configuration Reset Value */
#define PM_HIBCFG_RAMCFG_Pos _U_(0) /**< (PM_HIBCFG) Ram Configuration Position */
#define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos) /**< (PM_HIBCFG) Ram Configuration Mask */
#define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
#define PM_HIBCFG_RAMCFG_RET_Val _U_(0x0) /**< (PM_HIBCFG) All the system RAM is retained */
#define PM_HIBCFG_RAMCFG_PARTIAL_Val _U_(0x1) /**< (PM_HIBCFG) Only the first 32Kbytes of the system RAM is retained */
#define PM_HIBCFG_RAMCFG_OFF_Val _U_(0x2) /**< (PM_HIBCFG) All the system RAM is turned OFF */
#define PM_HIBCFG_RAMCFG_RET (PM_HIBCFG_RAMCFG_RET_Val << PM_HIBCFG_RAMCFG_Pos) /**< (PM_HIBCFG) All the system RAM is retained Position */
#define PM_HIBCFG_RAMCFG_PARTIAL (PM_HIBCFG_RAMCFG_PARTIAL_Val << PM_HIBCFG_RAMCFG_Pos) /**< (PM_HIBCFG) Only the first 32Kbytes of the system RAM is retained Position */
#define PM_HIBCFG_RAMCFG_OFF (PM_HIBCFG_RAMCFG_OFF_Val << PM_HIBCFG_RAMCFG_Pos) /**< (PM_HIBCFG) All the system RAM is turned OFF Position */
#define PM_HIBCFG_BRAMCFG_Pos _U_(2) /**< (PM_HIBCFG) Backup Ram Configuration Position */
#define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos) /**< (PM_HIBCFG) Backup Ram Configuration Mask */
#define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
#define PM_HIBCFG_BRAMCFG_RET_Val _U_(0x0) /**< (PM_HIBCFG) All the backup RAM is retained */
#define PM_HIBCFG_BRAMCFG_PARTIAL_Val _U_(0x1) /**< (PM_HIBCFG) Only the first 4Kbytes of the backup RAM is retained */
#define PM_HIBCFG_BRAMCFG_OFF_Val _U_(0x2) /**< (PM_HIBCFG) All the backup RAM is turned OFF */
#define PM_HIBCFG_BRAMCFG_RET (PM_HIBCFG_BRAMCFG_RET_Val << PM_HIBCFG_BRAMCFG_Pos) /**< (PM_HIBCFG) All the backup RAM is retained Position */
#define PM_HIBCFG_BRAMCFG_PARTIAL (PM_HIBCFG_BRAMCFG_PARTIAL_Val << PM_HIBCFG_BRAMCFG_Pos) /**< (PM_HIBCFG) Only the first 4Kbytes of the backup RAM is retained Position */
#define PM_HIBCFG_BRAMCFG_OFF (PM_HIBCFG_BRAMCFG_OFF_Val << PM_HIBCFG_BRAMCFG_Pos) /**< (PM_HIBCFG) All the backup RAM is turned OFF Position */
#define PM_HIBCFG_Msk _U_(0x0F) /**< (PM_HIBCFG) Register Mask */
/* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
#define PM_BKUPCFG_RESETVALUE _U_(0x00) /**< (PM_BKUPCFG) Backup Configuration Reset Value */
#define PM_BKUPCFG_BRAMCFG_Pos _U_(0) /**< (PM_BKUPCFG) Ram Configuration Position */
#define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos) /**< (PM_BKUPCFG) Ram Configuration Mask */
#define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
#define PM_BKUPCFG_BRAMCFG_RET_Val _U_(0x0) /**< (PM_BKUPCFG) All the backup RAM is retained */
#define PM_BKUPCFG_BRAMCFG_PARTIAL_Val _U_(0x1) /**< (PM_BKUPCFG) Only the first 4Kbytes of the backup RAM is retained */
#define PM_BKUPCFG_BRAMCFG_OFF_Val _U_(0x2) /**< (PM_BKUPCFG) All the backup RAM is turned OFF */
#define PM_BKUPCFG_BRAMCFG_RET (PM_BKUPCFG_BRAMCFG_RET_Val << PM_BKUPCFG_BRAMCFG_Pos) /**< (PM_BKUPCFG) All the backup RAM is retained Position */
#define PM_BKUPCFG_BRAMCFG_PARTIAL (PM_BKUPCFG_BRAMCFG_PARTIAL_Val << PM_BKUPCFG_BRAMCFG_Pos) /**< (PM_BKUPCFG) Only the first 4Kbytes of the backup RAM is retained Position */
#define PM_BKUPCFG_BRAMCFG_OFF (PM_BKUPCFG_BRAMCFG_OFF_Val << PM_BKUPCFG_BRAMCFG_Pos) /**< (PM_BKUPCFG) All the backup RAM is turned OFF Position */
#define PM_BKUPCFG_Msk _U_(0x03) /**< (PM_BKUPCFG) Register Mask */
/* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
#define PM_PWSAKDLY_RESETVALUE _U_(0x00) /**< (PM_PWSAKDLY) Power Switch Acknowledge Delay Reset Value */
#define PM_PWSAKDLY_DLYVAL_Pos _U_(0) /**< (PM_PWSAKDLY) Delay Value Position */
#define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos) /**< (PM_PWSAKDLY) Delay Value Mask */
#define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
#define PM_PWSAKDLY_IGNACK_Pos _U_(7) /**< (PM_PWSAKDLY) Ignore Acknowledge Position */
#define PM_PWSAKDLY_IGNACK_Msk (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos) /**< (PM_PWSAKDLY) Ignore Acknowledge Mask */
#define PM_PWSAKDLY_IGNACK(value) (PM_PWSAKDLY_IGNACK_Msk & ((value) << PM_PWSAKDLY_IGNACK_Pos))
#define PM_PWSAKDLY_Msk _U_(0xFF) /**< (PM_PWSAKDLY) Register Mask */
/** \brief PM register offsets definitions */
#define PM_CTRLA_REG_OFST (0x00) /**< (PM_CTRLA) Control A Offset */
#define PM_SLEEPCFG_REG_OFST (0x01) /**< (PM_SLEEPCFG) Sleep Configuration Offset */
#define PM_INTENCLR_REG_OFST (0x04) /**< (PM_INTENCLR) Interrupt Enable Clear Offset */
#define PM_INTENSET_REG_OFST (0x05) /**< (PM_INTENSET) Interrupt Enable Set Offset */
#define PM_INTFLAG_REG_OFST (0x06) /**< (PM_INTFLAG) Interrupt Flag Status and Clear Offset */
#define PM_STDBYCFG_REG_OFST (0x08) /**< (PM_STDBYCFG) Standby Configuration Offset */
#define PM_HIBCFG_REG_OFST (0x09) /**< (PM_HIBCFG) Hibernate Configuration Offset */
#define PM_BKUPCFG_REG_OFST (0x0A) /**< (PM_BKUPCFG) Backup Configuration Offset */
#define PM_PWSAKDLY_REG_OFST (0x12) /**< (PM_PWSAKDLY) Power Switch Acknowledge Delay Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief PM register API structure */
typedef struct
{ /* Power Manager */
__IO uint8_t PM_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__IO uint8_t PM_SLEEPCFG; /**< Offset: 0x01 (R/W 8) Sleep Configuration */
__I uint8_t Reserved1[0x02];
__IO uint8_t PM_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO uint8_t PM_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO uint8_t PM_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t Reserved2[0x01];
__IO uint8_t PM_STDBYCFG; /**< Offset: 0x08 (R/W 8) Standby Configuration */
__IO uint8_t PM_HIBCFG; /**< Offset: 0x09 (R/W 8) Hibernate Configuration */
__IO uint8_t PM_BKUPCFG; /**< Offset: 0x0A (R/W 8) Backup Configuration */
__I uint8_t Reserved3[0x07];
__IO uint8_t PM_PWSAKDLY; /**< Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay */
} pm_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PM_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/port.h
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/**
* \brief Component description for PORT
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PORT_COMPONENT_H_
#define _SAMD51_PORT_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PORT */
/* ************************************************************************** */
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
#define PORT_DIR_RESETVALUE _U_(0x00) /**< (PORT_DIR) Data Direction Reset Value */
#define PORT_DIR_DIR_Pos _U_(0) /**< (PORT_DIR) Port Data Direction Position */
#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) /**< (PORT_DIR) Port Data Direction Mask */
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
#define PORT_DIR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIR) Register Mask */
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
#define PORT_DIRCLR_RESETVALUE _U_(0x00) /**< (PORT_DIRCLR) Data Direction Clear Reset Value */
#define PORT_DIRCLR_DIRCLR_Pos _U_(0) /**< (PORT_DIRCLR) Port Data Direction Clear Position */
#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) /**< (PORT_DIRCLR) Port Data Direction Clear Mask */
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
#define PORT_DIRCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRCLR) Register Mask */
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
#define PORT_DIRSET_RESETVALUE _U_(0x00) /**< (PORT_DIRSET) Data Direction Set Reset Value */
#define PORT_DIRSET_DIRSET_Pos _U_(0) /**< (PORT_DIRSET) Port Data Direction Set Position */
#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) /**< (PORT_DIRSET) Port Data Direction Set Mask */
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
#define PORT_DIRSET_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRSET) Register Mask */
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
#define PORT_DIRTGL_RESETVALUE _U_(0x00) /**< (PORT_DIRTGL) Data Direction Toggle Reset Value */
#define PORT_DIRTGL_DIRTGL_Pos _U_(0) /**< (PORT_DIRTGL) Port Data Direction Toggle Position */
#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) /**< (PORT_DIRTGL) Port Data Direction Toggle Mask */
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
#define PORT_DIRTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_DIRTGL) Register Mask */
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
#define PORT_OUT_RESETVALUE _U_(0x00) /**< (PORT_OUT) Data Output Value Reset Value */
#define PORT_OUT_OUT_Pos _U_(0) /**< (PORT_OUT) PORT Data Output Value Position */
#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) /**< (PORT_OUT) PORT Data Output Value Mask */
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
#define PORT_OUT_Msk _U_(0xFFFFFFFF) /**< (PORT_OUT) Register Mask */
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
#define PORT_OUTCLR_RESETVALUE _U_(0x00) /**< (PORT_OUTCLR) Data Output Value Clear Reset Value */
#define PORT_OUTCLR_OUTCLR_Pos _U_(0) /**< (PORT_OUTCLR) PORT Data Output Value Clear Position */
#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) /**< (PORT_OUTCLR) PORT Data Output Value Clear Mask */
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
#define PORT_OUTCLR_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTCLR) Register Mask */
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
#define PORT_OUTSET_RESETVALUE _U_(0x00) /**< (PORT_OUTSET) Data Output Value Set Reset Value */
#define PORT_OUTSET_OUTSET_Pos _U_(0) /**< (PORT_OUTSET) PORT Data Output Value Set Position */
#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) /**< (PORT_OUTSET) PORT Data Output Value Set Mask */
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
#define PORT_OUTSET_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTSET) Register Mask */
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
#define PORT_OUTTGL_RESETVALUE _U_(0x00) /**< (PORT_OUTTGL) Data Output Value Toggle Reset Value */
#define PORT_OUTTGL_OUTTGL_Pos _U_(0) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Position */
#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) /**< (PORT_OUTTGL) PORT Data Output Value Toggle Mask */
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
#define PORT_OUTTGL_Msk _U_(0xFFFFFFFF) /**< (PORT_OUTTGL) Register Mask */
/* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
#define PORT_IN_RESETVALUE _U_(0x00) /**< (PORT_IN) Data Input Value Reset Value */
#define PORT_IN_IN_Pos _U_(0) /**< (PORT_IN) PORT Data Input Value Position */
#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos) /**< (PORT_IN) PORT Data Input Value Mask */
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
#define PORT_IN_Msk _U_(0xFFFFFFFF) /**< (PORT_IN) Register Mask */
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
#define PORT_CTRL_RESETVALUE _U_(0x00) /**< (PORT_CTRL) Control Reset Value */
#define PORT_CTRL_SAMPLING_Pos _U_(0) /**< (PORT_CTRL) Input Sampling Mode Position */
#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) /**< (PORT_CTRL) Input Sampling Mode Mask */
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
#define PORT_CTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_CTRL) Register Mask */
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
#define PORT_WRCONFIG_RESETVALUE _U_(0x00) /**< (PORT_WRCONFIG) Write Configuration Reset Value */
#define PORT_WRCONFIG_PINMASK_Pos _U_(0) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
#define PORT_WRCONFIG_PMUXEN_Pos _U_(16) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
#define PORT_WRCONFIG_PMUXEN_Msk (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
#define PORT_WRCONFIG_PMUXEN(value) (PORT_WRCONFIG_PMUXEN_Msk & ((value) << PORT_WRCONFIG_PMUXEN_Pos))
#define PORT_WRCONFIG_INEN_Pos _U_(17) /**< (PORT_WRCONFIG) Input Enable Position */
#define PORT_WRCONFIG_INEN_Msk (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) /**< (PORT_WRCONFIG) Input Enable Mask */
#define PORT_WRCONFIG_INEN(value) (PORT_WRCONFIG_INEN_Msk & ((value) << PORT_WRCONFIG_INEN_Pos))
#define PORT_WRCONFIG_PULLEN_Pos _U_(18) /**< (PORT_WRCONFIG) Pull Enable Position */
#define PORT_WRCONFIG_PULLEN_Msk (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) /**< (PORT_WRCONFIG) Pull Enable Mask */
#define PORT_WRCONFIG_PULLEN(value) (PORT_WRCONFIG_PULLEN_Msk & ((value) << PORT_WRCONFIG_PULLEN_Pos))
#define PORT_WRCONFIG_DRVSTR_Pos _U_(22) /**< (PORT_WRCONFIG) Output Driver Strength Selection Position */
#define PORT_WRCONFIG_DRVSTR_Msk (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) /**< (PORT_WRCONFIG) Output Driver Strength Selection Mask */
#define PORT_WRCONFIG_DRVSTR(value) (PORT_WRCONFIG_DRVSTR_Msk & ((value) << PORT_WRCONFIG_DRVSTR_Pos))
#define PORT_WRCONFIG_PMUX_Pos _U_(24) /**< (PORT_WRCONFIG) Peripheral Multiplexing Position */
#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) /**< (PORT_WRCONFIG) Peripheral Multiplexing Mask */
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
#define PORT_WRCONFIG_WRPMUX_Pos _U_(28) /**< (PORT_WRCONFIG) Write PMUX Position */
#define PORT_WRCONFIG_WRPMUX_Msk (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) /**< (PORT_WRCONFIG) Write PMUX Mask */
#define PORT_WRCONFIG_WRPMUX(value) (PORT_WRCONFIG_WRPMUX_Msk & ((value) << PORT_WRCONFIG_WRPMUX_Pos))
#define PORT_WRCONFIG_WRPINCFG_Pos _U_(30) /**< (PORT_WRCONFIG) Write PINCFG Position */
#define PORT_WRCONFIG_WRPINCFG_Msk (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) /**< (PORT_WRCONFIG) Write PINCFG Mask */
#define PORT_WRCONFIG_WRPINCFG(value) (PORT_WRCONFIG_WRPINCFG_Msk & ((value) << PORT_WRCONFIG_WRPINCFG_Pos))
#define PORT_WRCONFIG_HWSEL_Pos _U_(31) /**< (PORT_WRCONFIG) Half-Word Select Position */
#define PORT_WRCONFIG_HWSEL_Msk (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) /**< (PORT_WRCONFIG) Half-Word Select Mask */
#define PORT_WRCONFIG_HWSEL(value) (PORT_WRCONFIG_HWSEL_Msk & ((value) << PORT_WRCONFIG_HWSEL_Pos))
#define PORT_WRCONFIG_Msk _U_(0xDF47FFFF) /**< (PORT_WRCONFIG) Register Mask */
/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) Event Input Control -------- */
#define PORT_EVCTRL_RESETVALUE _U_(0x00) /**< (PORT_EVCTRL) Event Input Control Reset Value */
#define PORT_EVCTRL_PID0_Pos _U_(0) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Position */
#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 0 Mask */
#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
#define PORT_EVCTRL_EVACT0_Pos _U_(5) /**< (PORT_EVCTRL) PORT Event Action 0 Position */
#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) PORT Event Action 0 Mask */
#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< (PORT_EVCTRL) Event output to pin */
#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< (PORT_EVCTRL) Set output register of pin on event */
#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< (PORT_EVCTRL) Clear output register of pin on event */
#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< (PORT_EVCTRL) Toggle output register of pin on event */
#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Event output to pin Position */
#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Set output register of pin on event Position */
#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Clear output register of pin on event Position */
#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) /**< (PORT_EVCTRL) Toggle output register of pin on event Position */
#define PORT_EVCTRL_PORTEI0_Pos _U_(7) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Position */
#define PORT_EVCTRL_PORTEI0_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 0 Mask */
#define PORT_EVCTRL_PORTEI0(value) (PORT_EVCTRL_PORTEI0_Msk & ((value) << PORT_EVCTRL_PORTEI0_Pos))
#define PORT_EVCTRL_PID1_Pos _U_(8) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Position */
#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 1 Mask */
#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
#define PORT_EVCTRL_EVACT1_Pos _U_(13) /**< (PORT_EVCTRL) PORT Event Action 1 Position */
#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) /**< (PORT_EVCTRL) PORT Event Action 1 Mask */
#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
#define PORT_EVCTRL_PORTEI1_Pos _U_(15) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Position */
#define PORT_EVCTRL_PORTEI1_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 1 Mask */
#define PORT_EVCTRL_PORTEI1(value) (PORT_EVCTRL_PORTEI1_Msk & ((value) << PORT_EVCTRL_PORTEI1_Pos))
#define PORT_EVCTRL_PID2_Pos _U_(16) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Position */
#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 2 Mask */
#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
#define PORT_EVCTRL_EVACT2_Pos _U_(21) /**< (PORT_EVCTRL) PORT Event Action 2 Position */
#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) /**< (PORT_EVCTRL) PORT Event Action 2 Mask */
#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
#define PORT_EVCTRL_PORTEI2_Pos _U_(23) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Position */
#define PORT_EVCTRL_PORTEI2_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 2 Mask */
#define PORT_EVCTRL_PORTEI2(value) (PORT_EVCTRL_PORTEI2_Msk & ((value) << PORT_EVCTRL_PORTEI2_Pos))
#define PORT_EVCTRL_PID3_Pos _U_(24) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Position */
#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) /**< (PORT_EVCTRL) PORT Event Pin Identifier 3 Mask */
#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
#define PORT_EVCTRL_EVACT3_Pos _U_(29) /**< (PORT_EVCTRL) PORT Event Action 3 Position */
#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) /**< (PORT_EVCTRL) PORT Event Action 3 Mask */
#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
#define PORT_EVCTRL_PORTEI3_Pos _U_(31) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Position */
#define PORT_EVCTRL_PORTEI3_Msk (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) /**< (PORT_EVCTRL) PORT Event Input Enable 3 Mask */
#define PORT_EVCTRL_PORTEI3(value) (PORT_EVCTRL_PORTEI3_Msk & ((value) << PORT_EVCTRL_PORTEI3_Pos))
#define PORT_EVCTRL_Msk _U_(0xFFFFFFFF) /**< (PORT_EVCTRL) Register Mask */
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing -------- */
#define PORT_PMUX_RESETVALUE _U_(0x00) /**< (PORT_PMUX) Peripheral Multiplexing Reset Value */
#define PORT_PMUX_PMUXE_Pos _U_(0) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Position */
#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin Mask */
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
#define PORT_PMUX_PMUXO_Pos _U_(4) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Position */
#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) /**< (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin Mask */
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
#define PORT_PMUX_Msk _U_(0xFF) /**< (PORT_PMUX) Register Mask */
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration -------- */
#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< (PORT_PINCFG) Pin Configuration Reset Value */
#define PORT_PINCFG_PMUXEN_Pos _U_(0) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Position */
#define PORT_PINCFG_PMUXEN_Msk (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) /**< (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
#define PORT_PINCFG_PMUXEN(value) (PORT_PINCFG_PMUXEN_Msk & ((value) << PORT_PINCFG_PMUXEN_Pos))
#define PORT_PINCFG_INEN_Pos _U_(1) /**< (PORT_PINCFG) Input Enable Position */
#define PORT_PINCFG_INEN_Msk (_U_(0x1) << PORT_PINCFG_INEN_Pos) /**< (PORT_PINCFG) Input Enable Mask */
#define PORT_PINCFG_INEN(value) (PORT_PINCFG_INEN_Msk & ((value) << PORT_PINCFG_INEN_Pos))
#define PORT_PINCFG_PULLEN_Pos _U_(2) /**< (PORT_PINCFG) Pull Enable Position */
#define PORT_PINCFG_PULLEN_Msk (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) /**< (PORT_PINCFG) Pull Enable Mask */
#define PORT_PINCFG_PULLEN(value) (PORT_PINCFG_PULLEN_Msk & ((value) << PORT_PINCFG_PULLEN_Pos))
#define PORT_PINCFG_DRVSTR_Pos _U_(6) /**< (PORT_PINCFG) Output Driver Strength Selection Position */
#define PORT_PINCFG_DRVSTR_Msk (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) /**< (PORT_PINCFG) Output Driver Strength Selection Mask */
#define PORT_PINCFG_DRVSTR(value) (PORT_PINCFG_DRVSTR_Msk & ((value) << PORT_PINCFG_DRVSTR_Pos))
#define PORT_PINCFG_Msk _U_(0x47) /**< (PORT_PINCFG) Register Mask */
/** \brief PORT register offsets definitions */
#define PORT_DIR_REG_OFST (0x00) /**< (PORT_DIR) Data Direction Offset */
#define PORT_DIRCLR_REG_OFST (0x04) /**< (PORT_DIRCLR) Data Direction Clear Offset */
#define PORT_DIRSET_REG_OFST (0x08) /**< (PORT_DIRSET) Data Direction Set Offset */
#define PORT_DIRTGL_REG_OFST (0x0C) /**< (PORT_DIRTGL) Data Direction Toggle Offset */
#define PORT_OUT_REG_OFST (0x10) /**< (PORT_OUT) Data Output Value Offset */
#define PORT_OUTCLR_REG_OFST (0x14) /**< (PORT_OUTCLR) Data Output Value Clear Offset */
#define PORT_OUTSET_REG_OFST (0x18) /**< (PORT_OUTSET) Data Output Value Set Offset */
#define PORT_OUTTGL_REG_OFST (0x1C) /**< (PORT_OUTTGL) Data Output Value Toggle Offset */
#define PORT_IN_REG_OFST (0x20) /**< (PORT_IN) Data Input Value Offset */
#define PORT_CTRL_REG_OFST (0x24) /**< (PORT_CTRL) Control Offset */
#define PORT_WRCONFIG_REG_OFST (0x28) /**< (PORT_WRCONFIG) Write Configuration Offset */
#define PORT_EVCTRL_REG_OFST (0x2C) /**< (PORT_EVCTRL) Event Input Control Offset */
#define PORT_PMUX_REG_OFST (0x30) /**< (PORT_PMUX) Peripheral Multiplexing Offset */
#define PORT_PINCFG_REG_OFST (0x40) /**< (PORT_PINCFG) Pin Configuration Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief GROUP register API structure */
typedef struct
{
__IO uint32_t PORT_DIR; /**< Offset: 0x00 (R/W 32) Data Direction */
__IO uint32_t PORT_DIRCLR; /**< Offset: 0x04 (R/W 32) Data Direction Clear */
__IO uint32_t PORT_DIRSET; /**< Offset: 0x08 (R/W 32) Data Direction Set */
__IO uint32_t PORT_DIRTGL; /**< Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO uint32_t PORT_OUT; /**< Offset: 0x10 (R/W 32) Data Output Value */
__IO uint32_t PORT_OUTCLR; /**< Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO uint32_t PORT_OUTSET; /**< Offset: 0x18 (R/W 32) Data Output Value Set */
__IO uint32_t PORT_OUTTGL; /**< Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I uint32_t PORT_IN; /**< Offset: 0x20 (R/ 32) Data Input Value */
__IO uint32_t PORT_CTRL; /**< Offset: 0x24 (R/W 32) Control */
__O uint32_t PORT_WRCONFIG; /**< Offset: 0x28 ( /W 32) Write Configuration */
__IO uint32_t PORT_EVCTRL; /**< Offset: 0x2C (R/W 32) Event Input Control */
__IO uint8_t PORT_PMUX[16]; /**< Offset: 0x30 (R/W 8) Peripheral Multiplexing */
__IO uint8_t PORT_PINCFG[32]; /**< Offset: 0x40 (R/W 8) Pin Configuration */
__I uint8_t Reserved1[0x20];
} port_group_registers_t;
#define PORT_GROUP_NUMBER _U_(4)
/** \brief PORT register API structure */
typedef struct
{ /* Port Module */
port_group_registers_t GROUP[PORT_GROUP_NUMBER]; /**< Offset: 0x00 */
} port_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PORT_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/pukcc.h
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/**
* \brief Component description for PUKCC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_PUKCC_COMPONENT_H_
#define _SAMD51_PUKCC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR PUKCC */
/* ************************************************************************** */
/** \brief PUKCC register offsets definitions */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief No register API structure defined for PUKCC */
typedef void Pukcc;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_PUKCC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/qspi.h
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/**
* \brief Component description for QSPI
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_QSPI_COMPONENT_H_
#define _SAMD51_QSPI_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR QSPI */
/* ************************************************************************** */
/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
#define QSPI_CTRLA_RESETVALUE _U_(0x00) /**< (QSPI_CTRLA) Control A Reset Value */
#define QSPI_CTRLA_SWRST_Pos _U_(0) /**< (QSPI_CTRLA) Software Reset Position */
#define QSPI_CTRLA_SWRST_Msk (_U_(0x1) << QSPI_CTRLA_SWRST_Pos) /**< (QSPI_CTRLA) Software Reset Mask */
#define QSPI_CTRLA_SWRST(value) (QSPI_CTRLA_SWRST_Msk & ((value) << QSPI_CTRLA_SWRST_Pos))
#define QSPI_CTRLA_ENABLE_Pos _U_(1) /**< (QSPI_CTRLA) Enable Position */
#define QSPI_CTRLA_ENABLE_Msk (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos) /**< (QSPI_CTRLA) Enable Mask */
#define QSPI_CTRLA_ENABLE(value) (QSPI_CTRLA_ENABLE_Msk & ((value) << QSPI_CTRLA_ENABLE_Pos))
#define QSPI_CTRLA_LASTXFER_Pos _U_(24) /**< (QSPI_CTRLA) Last Transfer Position */
#define QSPI_CTRLA_LASTXFER_Msk (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos) /**< (QSPI_CTRLA) Last Transfer Mask */
#define QSPI_CTRLA_LASTXFER(value) (QSPI_CTRLA_LASTXFER_Msk & ((value) << QSPI_CTRLA_LASTXFER_Pos))
#define QSPI_CTRLA_Msk _U_(0x01000003) /**< (QSPI_CTRLA) Register Mask */
/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
#define QSPI_CTRLB_RESETVALUE _U_(0x00) /**< (QSPI_CTRLB) Control B Reset Value */
#define QSPI_CTRLB_MODE_Pos _U_(0) /**< (QSPI_CTRLB) Serial Memory Mode Position */
#define QSPI_CTRLB_MODE_Msk (_U_(0x1) << QSPI_CTRLB_MODE_Pos) /**< (QSPI_CTRLB) Serial Memory Mode Mask */
#define QSPI_CTRLB_MODE(value) (QSPI_CTRLB_MODE_Msk & ((value) << QSPI_CTRLB_MODE_Pos))
#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) /**< (QSPI_CTRLB) SPI operating mode */
#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) /**< (QSPI_CTRLB) Serial Memory operating mode */
#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos) /**< (QSPI_CTRLB) SPI operating mode Position */
#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos) /**< (QSPI_CTRLB) Serial Memory operating mode Position */
#define QSPI_CTRLB_LOOPEN_Pos _U_(1) /**< (QSPI_CTRLB) Local Loopback Enable Position */
#define QSPI_CTRLB_LOOPEN_Msk (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos) /**< (QSPI_CTRLB) Local Loopback Enable Mask */
#define QSPI_CTRLB_LOOPEN(value) (QSPI_CTRLB_LOOPEN_Msk & ((value) << QSPI_CTRLB_LOOPEN_Pos))
#define QSPI_CTRLB_LOOPEN_DISABLED_Val _U_(0x0) /**< (QSPI_CTRLB) Local Loopback is disabled */
#define QSPI_CTRLB_LOOPEN_ENABLED_Val _U_(0x1) /**< (QSPI_CTRLB) Local Loopback is enabled */
#define QSPI_CTRLB_LOOPEN_DISABLED (QSPI_CTRLB_LOOPEN_DISABLED_Val << QSPI_CTRLB_LOOPEN_Pos) /**< (QSPI_CTRLB) Local Loopback is disabled Position */
#define QSPI_CTRLB_LOOPEN_ENABLED (QSPI_CTRLB_LOOPEN_ENABLED_Val << QSPI_CTRLB_LOOPEN_Pos) /**< (QSPI_CTRLB) Local Loopback is enabled Position */
#define QSPI_CTRLB_WDRBT_Pos _U_(2) /**< (QSPI_CTRLB) Wait Data Read Before Transfer Position */
#define QSPI_CTRLB_WDRBT_Msk (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos) /**< (QSPI_CTRLB) Wait Data Read Before Transfer Mask */
#define QSPI_CTRLB_WDRBT(value) (QSPI_CTRLB_WDRBT_Msk & ((value) << QSPI_CTRLB_WDRBT_Pos))
#define QSPI_CTRLB_SMEMREG_Pos _U_(3) /**< (QSPI_CTRLB) Serial Memory reg Position */
#define QSPI_CTRLB_SMEMREG_Msk (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos) /**< (QSPI_CTRLB) Serial Memory reg Mask */
#define QSPI_CTRLB_SMEMREG(value) (QSPI_CTRLB_SMEMREG_Msk & ((value) << QSPI_CTRLB_SMEMREG_Pos))
#define QSPI_CTRLB_CSMODE_Pos _U_(4) /**< (QSPI_CTRLB) Chip Select Mode Position */
#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos) /**< (QSPI_CTRLB) Chip Select Mode Mask */
#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) /**< (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) /**< (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) /**< (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. */
#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos) /**< (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. Position */
#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos) /**< (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. Position */
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos) /**< (QSPI_CTRLB) The chip select is deasserted systematically after each transfer. Position */
#define QSPI_CTRLB_DATALEN_Pos _U_(8) /**< (QSPI_CTRLB) Data Length Position */
#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) Data Length Mask */
#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) /**< (QSPI_CTRLB) 8-bits transfer */
#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) /**< (QSPI_CTRLB) 9 bits transfer */
#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) /**< (QSPI_CTRLB) 10-bits transfer */
#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) /**< (QSPI_CTRLB) 11-bits transfer */
#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) /**< (QSPI_CTRLB) 12-bits transfer */
#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) /**< (QSPI_CTRLB) 13-bits transfer */
#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) /**< (QSPI_CTRLB) 14-bits transfer */
#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) /**< (QSPI_CTRLB) 15-bits transfer */
#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) /**< (QSPI_CTRLB) 16-bits transfer */
#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 8-bits transfer Position */
#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 9 bits transfer Position */
#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 10-bits transfer Position */
#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 11-bits transfer Position */
#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 12-bits transfer Position */
#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 13-bits transfer Position */
#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 14-bits transfer Position */
#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 15-bits transfer Position */
#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos) /**< (QSPI_CTRLB) 16-bits transfer Position */
#define QSPI_CTRLB_DLYBCT_Pos _U_(16) /**< (QSPI_CTRLB) Delay Between Consecutive Transfers Position */
#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos) /**< (QSPI_CTRLB) Delay Between Consecutive Transfers Mask */
#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
#define QSPI_CTRLB_DLYCS_Pos _U_(24) /**< (QSPI_CTRLB) Minimum Inactive CS Delay Position */
#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos) /**< (QSPI_CTRLB) Minimum Inactive CS Delay Mask */
#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
#define QSPI_CTRLB_Msk _U_(0xFFFF0F3F) /**< (QSPI_CTRLB) Register Mask */
/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
#define QSPI_BAUD_RESETVALUE _U_(0x00) /**< (QSPI_BAUD) Baud Rate Reset Value */
#define QSPI_BAUD_CPOL_Pos _U_(0) /**< (QSPI_BAUD) Clock Polarity Position */
#define QSPI_BAUD_CPOL_Msk (_U_(0x1) << QSPI_BAUD_CPOL_Pos) /**< (QSPI_BAUD) Clock Polarity Mask */
#define QSPI_BAUD_CPOL(value) (QSPI_BAUD_CPOL_Msk & ((value) << QSPI_BAUD_CPOL_Pos))
#define QSPI_BAUD_CPHA_Pos _U_(1) /**< (QSPI_BAUD) Clock Phase Position */
#define QSPI_BAUD_CPHA_Msk (_U_(0x1) << QSPI_BAUD_CPHA_Pos) /**< (QSPI_BAUD) Clock Phase Mask */
#define QSPI_BAUD_CPHA(value) (QSPI_BAUD_CPHA_Msk & ((value) << QSPI_BAUD_CPHA_Pos))
#define QSPI_BAUD_BAUD_Pos _U_(8) /**< (QSPI_BAUD) Serial Clock Baud Rate Position */
#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos) /**< (QSPI_BAUD) Serial Clock Baud Rate Mask */
#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
#define QSPI_BAUD_DLYBS_Pos _U_(16) /**< (QSPI_BAUD) Delay Before SCK Position */
#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos) /**< (QSPI_BAUD) Delay Before SCK Mask */
#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
#define QSPI_BAUD_Msk _U_(0x00FFFF03) /**< (QSPI_BAUD) Register Mask */
/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) ( R/ 32) Receive Data -------- */
#define QSPI_RXDATA_RESETVALUE _U_(0x00) /**< (QSPI_RXDATA) Receive Data Reset Value */
#define QSPI_RXDATA_DATA_Pos _U_(0) /**< (QSPI_RXDATA) Receive Data Position */
#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos) /**< (QSPI_RXDATA) Receive Data Mask */
#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
#define QSPI_RXDATA_Msk _U_(0x0000FFFF) /**< (QSPI_RXDATA) Register Mask */
/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
#define QSPI_TXDATA_RESETVALUE _U_(0x00) /**< (QSPI_TXDATA) Transmit Data Reset Value */
#define QSPI_TXDATA_DATA_Pos _U_(0) /**< (QSPI_TXDATA) Transmit Data Position */
#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos) /**< (QSPI_TXDATA) Transmit Data Mask */
#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
#define QSPI_TXDATA_Msk _U_(0x0000FFFF) /**< (QSPI_TXDATA) Register Mask */
/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
#define QSPI_INTENCLR_RESETVALUE _U_(0x00) /**< (QSPI_INTENCLR) Interrupt Enable Clear Reset Value */
#define QSPI_INTENCLR_RXC_Pos _U_(0) /**< (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable Position */
#define QSPI_INTENCLR_RXC_Msk (_U_(0x1) << QSPI_INTENCLR_RXC_Pos) /**< (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable Mask */
#define QSPI_INTENCLR_RXC(value) (QSPI_INTENCLR_RXC_Msk & ((value) << QSPI_INTENCLR_RXC_Pos))
#define QSPI_INTENCLR_DRE_Pos _U_(1) /**< (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable Position */
#define QSPI_INTENCLR_DRE_Msk (_U_(0x1) << QSPI_INTENCLR_DRE_Pos) /**< (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable Mask */
#define QSPI_INTENCLR_DRE(value) (QSPI_INTENCLR_DRE_Msk & ((value) << QSPI_INTENCLR_DRE_Pos))
#define QSPI_INTENCLR_TXC_Pos _U_(2) /**< (QSPI_INTENCLR) Transmission Complete Interrupt Disable Position */
#define QSPI_INTENCLR_TXC_Msk (_U_(0x1) << QSPI_INTENCLR_TXC_Pos) /**< (QSPI_INTENCLR) Transmission Complete Interrupt Disable Mask */
#define QSPI_INTENCLR_TXC(value) (QSPI_INTENCLR_TXC_Msk & ((value) << QSPI_INTENCLR_TXC_Pos))
#define QSPI_INTENCLR_ERROR_Pos _U_(3) /**< (QSPI_INTENCLR) Overrun Error Interrupt Disable Position */
#define QSPI_INTENCLR_ERROR_Msk (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos) /**< (QSPI_INTENCLR) Overrun Error Interrupt Disable Mask */
#define QSPI_INTENCLR_ERROR(value) (QSPI_INTENCLR_ERROR_Msk & ((value) << QSPI_INTENCLR_ERROR_Pos))
#define QSPI_INTENCLR_CSRISE_Pos _U_(8) /**< (QSPI_INTENCLR) Chip Select Rise Interrupt Disable Position */
#define QSPI_INTENCLR_CSRISE_Msk (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos) /**< (QSPI_INTENCLR) Chip Select Rise Interrupt Disable Mask */
#define QSPI_INTENCLR_CSRISE(value) (QSPI_INTENCLR_CSRISE_Msk & ((value) << QSPI_INTENCLR_CSRISE_Pos))
#define QSPI_INTENCLR_INSTREND_Pos _U_(10) /**< (QSPI_INTENCLR) Instruction End Interrupt Disable Position */
#define QSPI_INTENCLR_INSTREND_Msk (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos) /**< (QSPI_INTENCLR) Instruction End Interrupt Disable Mask */
#define QSPI_INTENCLR_INSTREND(value) (QSPI_INTENCLR_INSTREND_Msk & ((value) << QSPI_INTENCLR_INSTREND_Pos))
#define QSPI_INTENCLR_Msk _U_(0x0000050F) /**< (QSPI_INTENCLR) Register Mask */
/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
#define QSPI_INTENSET_RESETVALUE _U_(0x00) /**< (QSPI_INTENSET) Interrupt Enable Set Reset Value */
#define QSPI_INTENSET_RXC_Pos _U_(0) /**< (QSPI_INTENSET) Receive Data Register Full Interrupt Enable Position */
#define QSPI_INTENSET_RXC_Msk (_U_(0x1) << QSPI_INTENSET_RXC_Pos) /**< (QSPI_INTENSET) Receive Data Register Full Interrupt Enable Mask */
#define QSPI_INTENSET_RXC(value) (QSPI_INTENSET_RXC_Msk & ((value) << QSPI_INTENSET_RXC_Pos))
#define QSPI_INTENSET_DRE_Pos _U_(1) /**< (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable Position */
#define QSPI_INTENSET_DRE_Msk (_U_(0x1) << QSPI_INTENSET_DRE_Pos) /**< (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable Mask */
#define QSPI_INTENSET_DRE(value) (QSPI_INTENSET_DRE_Msk & ((value) << QSPI_INTENSET_DRE_Pos))
#define QSPI_INTENSET_TXC_Pos _U_(2) /**< (QSPI_INTENSET) Transmission Complete Interrupt Enable Position */
#define QSPI_INTENSET_TXC_Msk (_U_(0x1) << QSPI_INTENSET_TXC_Pos) /**< (QSPI_INTENSET) Transmission Complete Interrupt Enable Mask */
#define QSPI_INTENSET_TXC(value) (QSPI_INTENSET_TXC_Msk & ((value) << QSPI_INTENSET_TXC_Pos))
#define QSPI_INTENSET_ERROR_Pos _U_(3) /**< (QSPI_INTENSET) Overrun Error Interrupt Enable Position */
#define QSPI_INTENSET_ERROR_Msk (_U_(0x1) << QSPI_INTENSET_ERROR_Pos) /**< (QSPI_INTENSET) Overrun Error Interrupt Enable Mask */
#define QSPI_INTENSET_ERROR(value) (QSPI_INTENSET_ERROR_Msk & ((value) << QSPI_INTENSET_ERROR_Pos))
#define QSPI_INTENSET_CSRISE_Pos _U_(8) /**< (QSPI_INTENSET) Chip Select Rise Interrupt Enable Position */
#define QSPI_INTENSET_CSRISE_Msk (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos) /**< (QSPI_INTENSET) Chip Select Rise Interrupt Enable Mask */
#define QSPI_INTENSET_CSRISE(value) (QSPI_INTENSET_CSRISE_Msk & ((value) << QSPI_INTENSET_CSRISE_Pos))
#define QSPI_INTENSET_INSTREND_Pos _U_(10) /**< (QSPI_INTENSET) Instruction End Interrupt Enable Position */
#define QSPI_INTENSET_INSTREND_Msk (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos) /**< (QSPI_INTENSET) Instruction End Interrupt Enable Mask */
#define QSPI_INTENSET_INSTREND(value) (QSPI_INTENSET_INSTREND_Msk & ((value) << QSPI_INTENSET_INSTREND_Pos))
#define QSPI_INTENSET_Msk _U_(0x0000050F) /**< (QSPI_INTENSET) Register Mask */
/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
#define QSPI_INTFLAG_RESETVALUE _U_(0x00) /**< (QSPI_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define QSPI_INTFLAG_RXC_Pos _U_(0) /**< (QSPI_INTFLAG) Receive Data Register Full Position */
#define QSPI_INTFLAG_RXC_Msk (_U_(0x1) << QSPI_INTFLAG_RXC_Pos) /**< (QSPI_INTFLAG) Receive Data Register Full Mask */
#define QSPI_INTFLAG_RXC(value) (QSPI_INTFLAG_RXC_Msk & ((value) << QSPI_INTFLAG_RXC_Pos))
#define QSPI_INTFLAG_DRE_Pos _U_(1) /**< (QSPI_INTFLAG) Transmit Data Register Empty Position */
#define QSPI_INTFLAG_DRE_Msk (_U_(0x1) << QSPI_INTFLAG_DRE_Pos) /**< (QSPI_INTFLAG) Transmit Data Register Empty Mask */
#define QSPI_INTFLAG_DRE(value) (QSPI_INTFLAG_DRE_Msk & ((value) << QSPI_INTFLAG_DRE_Pos))
#define QSPI_INTFLAG_TXC_Pos _U_(2) /**< (QSPI_INTFLAG) Transmission Complete Position */
#define QSPI_INTFLAG_TXC_Msk (_U_(0x1) << QSPI_INTFLAG_TXC_Pos) /**< (QSPI_INTFLAG) Transmission Complete Mask */
#define QSPI_INTFLAG_TXC(value) (QSPI_INTFLAG_TXC_Msk & ((value) << QSPI_INTFLAG_TXC_Pos))
#define QSPI_INTFLAG_ERROR_Pos _U_(3) /**< (QSPI_INTFLAG) Overrun Error Position */
#define QSPI_INTFLAG_ERROR_Msk (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos) /**< (QSPI_INTFLAG) Overrun Error Mask */
#define QSPI_INTFLAG_ERROR(value) (QSPI_INTFLAG_ERROR_Msk & ((value) << QSPI_INTFLAG_ERROR_Pos))
#define QSPI_INTFLAG_CSRISE_Pos _U_(8) /**< (QSPI_INTFLAG) Chip Select Rise Position */
#define QSPI_INTFLAG_CSRISE_Msk (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos) /**< (QSPI_INTFLAG) Chip Select Rise Mask */
#define QSPI_INTFLAG_CSRISE(value) (QSPI_INTFLAG_CSRISE_Msk & ((value) << QSPI_INTFLAG_CSRISE_Pos))
#define QSPI_INTFLAG_INSTREND_Pos _U_(10) /**< (QSPI_INTFLAG) Instruction End Position */
#define QSPI_INTFLAG_INSTREND_Msk (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos) /**< (QSPI_INTFLAG) Instruction End Mask */
#define QSPI_INTFLAG_INSTREND(value) (QSPI_INTFLAG_INSTREND_Msk & ((value) << QSPI_INTFLAG_INSTREND_Pos))
#define QSPI_INTFLAG_Msk _U_(0x0000050F) /**< (QSPI_INTFLAG) Register Mask */
/* -------- QSPI_STATUS : (QSPI Offset: 0x20) ( R/ 32) Status Register -------- */
#define QSPI_STATUS_RESETVALUE _U_(0x200) /**< (QSPI_STATUS) Status Register Reset Value */
#define QSPI_STATUS_ENABLE_Pos _U_(1) /**< (QSPI_STATUS) Enable Position */
#define QSPI_STATUS_ENABLE_Msk (_U_(0x1) << QSPI_STATUS_ENABLE_Pos) /**< (QSPI_STATUS) Enable Mask */
#define QSPI_STATUS_ENABLE(value) (QSPI_STATUS_ENABLE_Msk & ((value) << QSPI_STATUS_ENABLE_Pos))
#define QSPI_STATUS_CSSTATUS_Pos _U_(9) /**< (QSPI_STATUS) Chip Select Position */
#define QSPI_STATUS_CSSTATUS_Msk (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos) /**< (QSPI_STATUS) Chip Select Mask */
#define QSPI_STATUS_CSSTATUS(value) (QSPI_STATUS_CSSTATUS_Msk & ((value) << QSPI_STATUS_CSSTATUS_Pos))
#define QSPI_STATUS_Msk _U_(0x00000202) /**< (QSPI_STATUS) Register Mask */
/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
#define QSPI_INSTRADDR_RESETVALUE _U_(0x00) /**< (QSPI_INSTRADDR) Instruction Address Reset Value */
#define QSPI_INSTRADDR_ADDR_Pos _U_(0) /**< (QSPI_INSTRADDR) Instruction Address Position */
#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos) /**< (QSPI_INSTRADDR) Instruction Address Mask */
#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
#define QSPI_INSTRADDR_Msk _U_(0xFFFFFFFF) /**< (QSPI_INSTRADDR) Register Mask */
/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00) /**< (QSPI_INSTRCTRL) Instruction Code Reset Value */
#define QSPI_INSTRCTRL_INSTR_Pos _U_(0) /**< (QSPI_INSTRCTRL) Instruction Code Position */
#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos) /**< (QSPI_INSTRCTRL) Instruction Code Mask */
#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
#define QSPI_INSTRCTRL_OPTCODE_Pos _U_(16) /**< (QSPI_INSTRCTRL) Option Code Position */
#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos) /**< (QSPI_INSTRCTRL) Option Code Mask */
#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
#define QSPI_INSTRCTRL_Msk _U_(0x00FF00FF) /**< (QSPI_INSTRCTRL) Register Mask */
/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00) /**< (QSPI_INSTRFRAME) Instruction Frame Reset Value */
#define QSPI_INSTRFRAME_WIDTH_Pos _U_(0) /**< (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width Position */
#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width Mask */
#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) /**< (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) /**< (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI Position */
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI Position */
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI Position */
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI Position */
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI Position */
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI Position */
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos) /**< (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI Position */
#define QSPI_INSTRFRAME_INSTREN_Pos _U_(4) /**< (QSPI_INSTRFRAME) Instruction Enable Position */
#define QSPI_INSTRFRAME_INSTREN_Msk (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos) /**< (QSPI_INSTRFRAME) Instruction Enable Mask */
#define QSPI_INSTRFRAME_INSTREN(value) (QSPI_INSTRFRAME_INSTREN_Msk & ((value) << QSPI_INSTRFRAME_INSTREN_Pos))
#define QSPI_INSTRFRAME_ADDREN_Pos _U_(5) /**< (QSPI_INSTRFRAME) Address Enable Position */
#define QSPI_INSTRFRAME_ADDREN_Msk (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos) /**< (QSPI_INSTRFRAME) Address Enable Mask */
#define QSPI_INSTRFRAME_ADDREN(value) (QSPI_INSTRFRAME_ADDREN_Msk & ((value) << QSPI_INSTRFRAME_ADDREN_Pos))
#define QSPI_INSTRFRAME_OPTCODEEN_Pos _U_(6) /**< (QSPI_INSTRFRAME) Option Enable Position */
#define QSPI_INSTRFRAME_OPTCODEEN_Msk (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos) /**< (QSPI_INSTRFRAME) Option Enable Mask */
#define QSPI_INSTRFRAME_OPTCODEEN(value) (QSPI_INSTRFRAME_OPTCODEEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODEEN_Pos))
#define QSPI_INSTRFRAME_DATAEN_Pos _U_(7) /**< (QSPI_INSTRFRAME) Data Enable Position */
#define QSPI_INSTRFRAME_DATAEN_Msk (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos) /**< (QSPI_INSTRFRAME) Data Enable Mask */
#define QSPI_INSTRFRAME_DATAEN(value) (QSPI_INSTRFRAME_DATAEN_Msk & ((value) << QSPI_INSTRFRAME_DATAEN_Pos))
#define QSPI_INSTRFRAME_OPTCODELEN_Pos _U_(8) /**< (QSPI_INSTRFRAME) Option Code Length Position */
#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos) /**< (QSPI_INSTRFRAME) Option Code Length Mask */
#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) /**< (QSPI_INSTRFRAME) 1-bit length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) /**< (QSPI_INSTRFRAME) 2-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) /**< (QSPI_INSTRFRAME) 4-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) /**< (QSPI_INSTRFRAME) 8-bits length option code */
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /**< (QSPI_INSTRFRAME) 1-bit length option code Position */
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /**< (QSPI_INSTRFRAME) 2-bits length option code Position */
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /**< (QSPI_INSTRFRAME) 4-bits length option code Position */
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos) /**< (QSPI_INSTRFRAME) 8-bits length option code Position */
#define QSPI_INSTRFRAME_ADDRLEN_Pos _U_(10) /**< (QSPI_INSTRFRAME) Address Length Position */
#define QSPI_INSTRFRAME_ADDRLEN_Msk (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos) /**< (QSPI_INSTRFRAME) Address Length Mask */
#define QSPI_INSTRFRAME_ADDRLEN(value) (QSPI_INSTRFRAME_ADDRLEN_Msk & ((value) << QSPI_INSTRFRAME_ADDRLEN_Pos))
#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) /**< (QSPI_INSTRFRAME) 24-bits address length */
#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) /**< (QSPI_INSTRFRAME) 32-bits address length */
#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos) /**< (QSPI_INSTRFRAME) 24-bits address length Position */
#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos) /**< (QSPI_INSTRFRAME) 32-bits address length Position */
#define QSPI_INSTRFRAME_TFRTYPE_Pos _U_(12) /**< (QSPI_INSTRFRAME) Data Transfer Type Position */
#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos) /**< (QSPI_INSTRFRAME) Data Transfer Type Mask */
#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) /**< (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. */
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) /**< (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. */
#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) /**< (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. */
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) /**< (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. */
#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /**< (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. Position */
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /**< (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. Position */
#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /**< (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed. Position */
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos) /**< (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed. Position */
#define QSPI_INSTRFRAME_CRMODE_Pos _U_(14) /**< (QSPI_INSTRFRAME) Continuous Read Mode Position */
#define QSPI_INSTRFRAME_CRMODE_Msk (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos) /**< (QSPI_INSTRFRAME) Continuous Read Mode Mask */
#define QSPI_INSTRFRAME_CRMODE(value) (QSPI_INSTRFRAME_CRMODE_Msk & ((value) << QSPI_INSTRFRAME_CRMODE_Pos))
#define QSPI_INSTRFRAME_DDREN_Pos _U_(15) /**< (QSPI_INSTRFRAME) Double Data Rate Enable Position */
#define QSPI_INSTRFRAME_DDREN_Msk (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos) /**< (QSPI_INSTRFRAME) Double Data Rate Enable Mask */
#define QSPI_INSTRFRAME_DDREN(value) (QSPI_INSTRFRAME_DDREN_Msk & ((value) << QSPI_INSTRFRAME_DDREN_Pos))
#define QSPI_INSTRFRAME_DUMMYLEN_Pos _U_(16) /**< (QSPI_INSTRFRAME) Dummy Cycles Length Position */
#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos) /**< (QSPI_INSTRFRAME) Dummy Cycles Length Mask */
#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
#define QSPI_INSTRFRAME_Msk _U_(0x001FF7F7) /**< (QSPI_INSTRFRAME) Register Mask */
/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00) /**< (QSPI_SCRAMBCTRL) Scrambling Mode Reset Value */
#define QSPI_SCRAMBCTRL_ENABLE_Pos _U_(0) /**< (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable Position */
#define QSPI_SCRAMBCTRL_ENABLE_Msk (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos) /**< (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable Mask */
#define QSPI_SCRAMBCTRL_ENABLE(value) (QSPI_SCRAMBCTRL_ENABLE_Msk & ((value) << QSPI_SCRAMBCTRL_ENABLE_Pos))
#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos _U_(1) /**< (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable Position */
#define QSPI_SCRAMBCTRL_RANDOMDIS_Msk (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos) /**< (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable Mask */
#define QSPI_SCRAMBCTRL_RANDOMDIS(value) (QSPI_SCRAMBCTRL_RANDOMDIS_Msk & ((value) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos))
#define QSPI_SCRAMBCTRL_Msk _U_(0x00000003) /**< (QSPI_SCRAMBCTRL) Register Mask */
/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00) /**< (QSPI_SCRAMBKEY) Scrambling Key Reset Value */
#define QSPI_SCRAMBKEY_KEY_Pos _U_(0) /**< (QSPI_SCRAMBKEY) Scrambling User Key Position */
#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos) /**< (QSPI_SCRAMBKEY) Scrambling User Key Mask */
#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
#define QSPI_SCRAMBKEY_Msk _U_(0xFFFFFFFF) /**< (QSPI_SCRAMBKEY) Register Mask */
/** \brief QSPI register offsets definitions */
#define QSPI_CTRLA_REG_OFST (0x00) /**< (QSPI_CTRLA) Control A Offset */
#define QSPI_CTRLB_REG_OFST (0x04) /**< (QSPI_CTRLB) Control B Offset */
#define QSPI_BAUD_REG_OFST (0x08) /**< (QSPI_BAUD) Baud Rate Offset */
#define QSPI_RXDATA_REG_OFST (0x0C) /**< (QSPI_RXDATA) Receive Data Offset */
#define QSPI_TXDATA_REG_OFST (0x10) /**< (QSPI_TXDATA) Transmit Data Offset */
#define QSPI_INTENCLR_REG_OFST (0x14) /**< (QSPI_INTENCLR) Interrupt Enable Clear Offset */
#define QSPI_INTENSET_REG_OFST (0x18) /**< (QSPI_INTENSET) Interrupt Enable Set Offset */
#define QSPI_INTFLAG_REG_OFST (0x1C) /**< (QSPI_INTFLAG) Interrupt Flag Status and Clear Offset */
#define QSPI_STATUS_REG_OFST (0x20) /**< (QSPI_STATUS) Status Register Offset */
#define QSPI_INSTRADDR_REG_OFST (0x30) /**< (QSPI_INSTRADDR) Instruction Address Offset */
#define QSPI_INSTRCTRL_REG_OFST (0x34) /**< (QSPI_INSTRCTRL) Instruction Code Offset */
#define QSPI_INSTRFRAME_REG_OFST (0x38) /**< (QSPI_INSTRFRAME) Instruction Frame Offset */
#define QSPI_SCRAMBCTRL_REG_OFST (0x40) /**< (QSPI_SCRAMBCTRL) Scrambling Mode Offset */
#define QSPI_SCRAMBKEY_REG_OFST (0x44) /**< (QSPI_SCRAMBKEY) Scrambling Key Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief QSPI register API structure */
typedef struct
{ /* Quad SPI interface */
__IO uint32_t QSPI_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint32_t QSPI_CTRLB; /**< Offset: 0x04 (R/W 32) Control B */
__IO uint32_t QSPI_BAUD; /**< Offset: 0x08 (R/W 32) Baud Rate */
__I uint32_t QSPI_RXDATA; /**< Offset: 0x0C (R/ 32) Receive Data */
__O uint32_t QSPI_TXDATA; /**< Offset: 0x10 ( /W 32) Transmit Data */
__IO uint32_t QSPI_INTENCLR; /**< Offset: 0x14 (R/W 32) Interrupt Enable Clear */
__IO uint32_t QSPI_INTENSET; /**< Offset: 0x18 (R/W 32) Interrupt Enable Set */
__IO uint32_t QSPI_INTFLAG; /**< Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear */
__I uint32_t QSPI_STATUS; /**< Offset: 0x20 (R/ 32) Status Register */
__I uint8_t Reserved1[0x0C];
__IO uint32_t QSPI_INSTRADDR; /**< Offset: 0x30 (R/W 32) Instruction Address */
__IO uint32_t QSPI_INSTRCTRL; /**< Offset: 0x34 (R/W 32) Instruction Code */
__IO uint32_t QSPI_INSTRFRAME; /**< Offset: 0x38 (R/W 32) Instruction Frame */
__I uint8_t Reserved2[0x04];
__IO uint32_t QSPI_SCRAMBCTRL; /**< Offset: 0x40 (R/W 32) Scrambling Mode */
__O uint32_t QSPI_SCRAMBKEY; /**< Offset: 0x44 ( /W 32) Scrambling Key */
} qspi_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_QSPI_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/ramecc.h
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/**
* \brief Component description for RAMECC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_RAMECC_COMPONENT_H_
#define _SAMD51_RAMECC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR RAMECC */
/* ************************************************************************** */
/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x00) (R/W 8) Interrupt Enable Clear -------- */
#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< (RAMECC_INTENCLR) Interrupt Enable Clear Reset Value */
#define RAMECC_INTENCLR_SINGLEE_Pos _U_(0) /**< (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Position */
#define RAMECC_INTENCLR_SINGLEE_Msk (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos) /**< (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Mask */
#define RAMECC_INTENCLR_SINGLEE(value) (RAMECC_INTENCLR_SINGLEE_Msk & ((value) << RAMECC_INTENCLR_SINGLEE_Pos))
#define RAMECC_INTENCLR_DUALE_Pos _U_(1) /**< (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Position */
#define RAMECC_INTENCLR_DUALE_Msk (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos) /**< (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Mask */
#define RAMECC_INTENCLR_DUALE(value) (RAMECC_INTENCLR_DUALE_Msk & ((value) << RAMECC_INTENCLR_DUALE_Pos))
#define RAMECC_INTENCLR_Msk _U_(0x03) /**< (RAMECC_INTENCLR) Register Mask */
/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x01) (R/W 8) Interrupt Enable Set -------- */
#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< (RAMECC_INTENSET) Interrupt Enable Set Reset Value */
#define RAMECC_INTENSET_SINGLEE_Pos _U_(0) /**< (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Position */
#define RAMECC_INTENSET_SINGLEE_Msk (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos) /**< (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Mask */
#define RAMECC_INTENSET_SINGLEE(value) (RAMECC_INTENSET_SINGLEE_Msk & ((value) << RAMECC_INTENSET_SINGLEE_Pos))
#define RAMECC_INTENSET_DUALE_Pos _U_(1) /**< (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Position */
#define RAMECC_INTENSET_DUALE_Msk (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos) /**< (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Mask */
#define RAMECC_INTENSET_DUALE(value) (RAMECC_INTENSET_DUALE_Msk & ((value) << RAMECC_INTENSET_DUALE_Pos))
#define RAMECC_INTENSET_Msk _U_(0x03) /**< (RAMECC_INTENSET) Register Mask */
/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x02) (R/W 8) Interrupt Flag -------- */
#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< (RAMECC_INTFLAG) Interrupt Flag Reset Value */
#define RAMECC_INTFLAG_SINGLEE_Pos _U_(0) /**< (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Position */
#define RAMECC_INTFLAG_SINGLEE_Msk (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos) /**< (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Mask */
#define RAMECC_INTFLAG_SINGLEE(value) (RAMECC_INTFLAG_SINGLEE_Msk & ((value) << RAMECC_INTFLAG_SINGLEE_Pos))
#define RAMECC_INTFLAG_DUALE_Pos _U_(1) /**< (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Position */
#define RAMECC_INTFLAG_DUALE_Msk (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos) /**< (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Mask */
#define RAMECC_INTFLAG_DUALE(value) (RAMECC_INTFLAG_DUALE_Msk & ((value) << RAMECC_INTFLAG_DUALE_Pos))
#define RAMECC_INTFLAG_Msk _U_(0x03) /**< (RAMECC_INTFLAG) Register Mask */
/* -------- RAMECC_STATUS : (RAMECC Offset: 0x03) ( R/ 8) Status -------- */
#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< (RAMECC_STATUS) Status Reset Value */
#define RAMECC_STATUS_ECCDIS_Pos _U_(0) /**< (RAMECC_STATUS) ECC Disable Position */
#define RAMECC_STATUS_ECCDIS_Msk (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos) /**< (RAMECC_STATUS) ECC Disable Mask */
#define RAMECC_STATUS_ECCDIS(value) (RAMECC_STATUS_ECCDIS_Msk & ((value) << RAMECC_STATUS_ECCDIS_Pos))
#define RAMECC_STATUS_Msk _U_(0x01) /**< (RAMECC_STATUS) Register Mask */
/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x04) ( R/ 32) Error Address -------- */
#define RAMECC_ERRADDR_RESETVALUE _U_(0x00) /**< (RAMECC_ERRADDR) Error Address Reset Value */
#define RAMECC_ERRADDR_ERRADDR_Pos _U_(0) /**< (RAMECC_ERRADDR) Error Address Position */
#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos) /**< (RAMECC_ERRADDR) Error Address Mask */
#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
#define RAMECC_ERRADDR_Msk _U_(0x0001FFFF) /**< (RAMECC_ERRADDR) Register Mask */
/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0x0F) (R/W 8) Debug Control -------- */
#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< (RAMECC_DBGCTRL) Debug Control Reset Value */
#define RAMECC_DBGCTRL_ECCDIS_Pos _U_(0) /**< (RAMECC_DBGCTRL) ECC Disable Position */
#define RAMECC_DBGCTRL_ECCDIS_Msk (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos) /**< (RAMECC_DBGCTRL) ECC Disable Mask */
#define RAMECC_DBGCTRL_ECCDIS(value) (RAMECC_DBGCTRL_ECCDIS_Msk & ((value) << RAMECC_DBGCTRL_ECCDIS_Pos))
#define RAMECC_DBGCTRL_ECCELOG_Pos _U_(1) /**< (RAMECC_DBGCTRL) ECC Error Log Position */
#define RAMECC_DBGCTRL_ECCELOG_Msk (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos) /**< (RAMECC_DBGCTRL) ECC Error Log Mask */
#define RAMECC_DBGCTRL_ECCELOG(value) (RAMECC_DBGCTRL_ECCELOG_Msk & ((value) << RAMECC_DBGCTRL_ECCELOG_Pos))
#define RAMECC_DBGCTRL_Msk _U_(0x03) /**< (RAMECC_DBGCTRL) Register Mask */
/** \brief RAMECC register offsets definitions */
#define RAMECC_INTENCLR_REG_OFST (0x00) /**< (RAMECC_INTENCLR) Interrupt Enable Clear Offset */
#define RAMECC_INTENSET_REG_OFST (0x01) /**< (RAMECC_INTENSET) Interrupt Enable Set Offset */
#define RAMECC_INTFLAG_REG_OFST (0x02) /**< (RAMECC_INTFLAG) Interrupt Flag Offset */
#define RAMECC_STATUS_REG_OFST (0x03) /**< (RAMECC_STATUS) Status Offset */
#define RAMECC_ERRADDR_REG_OFST (0x04) /**< (RAMECC_ERRADDR) Error Address Offset */
#define RAMECC_DBGCTRL_REG_OFST (0x0F) /**< (RAMECC_DBGCTRL) Debug Control Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief RAMECC register API structure */
typedef struct
{ /* RAM ECC */
__IO uint8_t RAMECC_INTENCLR; /**< Offset: 0x00 (R/W 8) Interrupt Enable Clear */
__IO uint8_t RAMECC_INTENSET; /**< Offset: 0x01 (R/W 8) Interrupt Enable Set */
__IO uint8_t RAMECC_INTFLAG; /**< Offset: 0x02 (R/W 8) Interrupt Flag */
__I uint8_t RAMECC_STATUS; /**< Offset: 0x03 (R/ 8) Status */
__I uint32_t RAMECC_ERRADDR; /**< Offset: 0x04 (R/ 32) Error Address */
__I uint8_t Reserved1[0x07];
__IO uint8_t RAMECC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
} ramecc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_RAMECC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/rstc.h
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/**
* \brief Component description for RSTC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_RSTC_COMPONENT_H_
#define _SAMD51_RSTC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR RSTC */
/* ************************************************************************** */
/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) ( R/ 8) Reset Cause -------- */
#define RSTC_RCAUSE_POR_Pos _U_(0) /**< (RSTC_RCAUSE) Power On Reset Position */
#define RSTC_RCAUSE_POR_Msk (_U_(0x1) << RSTC_RCAUSE_POR_Pos) /**< (RSTC_RCAUSE) Power On Reset Mask */
#define RSTC_RCAUSE_POR(value) (RSTC_RCAUSE_POR_Msk & ((value) << RSTC_RCAUSE_POR_Pos))
#define RSTC_RCAUSE_BODCORE_Pos _U_(1) /**< (RSTC_RCAUSE) Brown Out CORE Detector Reset Position */
#define RSTC_RCAUSE_BODCORE_Msk (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos) /**< (RSTC_RCAUSE) Brown Out CORE Detector Reset Mask */
#define RSTC_RCAUSE_BODCORE(value) (RSTC_RCAUSE_BODCORE_Msk & ((value) << RSTC_RCAUSE_BODCORE_Pos))
#define RSTC_RCAUSE_BODVDD_Pos _U_(2) /**< (RSTC_RCAUSE) Brown Out VDD Detector Reset Position */
#define RSTC_RCAUSE_BODVDD_Msk (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos) /**< (RSTC_RCAUSE) Brown Out VDD Detector Reset Mask */
#define RSTC_RCAUSE_BODVDD(value) (RSTC_RCAUSE_BODVDD_Msk & ((value) << RSTC_RCAUSE_BODVDD_Pos))
#define RSTC_RCAUSE_NVM_Pos _U_(3) /**< (RSTC_RCAUSE) NVM Reset Position */
#define RSTC_RCAUSE_NVM_Msk (_U_(0x1) << RSTC_RCAUSE_NVM_Pos) /**< (RSTC_RCAUSE) NVM Reset Mask */
#define RSTC_RCAUSE_NVM(value) (RSTC_RCAUSE_NVM_Msk & ((value) << RSTC_RCAUSE_NVM_Pos))
#define RSTC_RCAUSE_EXT_Pos _U_(4) /**< (RSTC_RCAUSE) External Reset Position */
#define RSTC_RCAUSE_EXT_Msk (_U_(0x1) << RSTC_RCAUSE_EXT_Pos) /**< (RSTC_RCAUSE) External Reset Mask */
#define RSTC_RCAUSE_EXT(value) (RSTC_RCAUSE_EXT_Msk & ((value) << RSTC_RCAUSE_EXT_Pos))
#define RSTC_RCAUSE_WDT_Pos _U_(5) /**< (RSTC_RCAUSE) Watchdog Reset Position */
#define RSTC_RCAUSE_WDT_Msk (_U_(0x1) << RSTC_RCAUSE_WDT_Pos) /**< (RSTC_RCAUSE) Watchdog Reset Mask */
#define RSTC_RCAUSE_WDT(value) (RSTC_RCAUSE_WDT_Msk & ((value) << RSTC_RCAUSE_WDT_Pos))
#define RSTC_RCAUSE_SYST_Pos _U_(6) /**< (RSTC_RCAUSE) System Reset Request Position */
#define RSTC_RCAUSE_SYST_Msk (_U_(0x1) << RSTC_RCAUSE_SYST_Pos) /**< (RSTC_RCAUSE) System Reset Request Mask */
#define RSTC_RCAUSE_SYST(value) (RSTC_RCAUSE_SYST_Msk & ((value) << RSTC_RCAUSE_SYST_Pos))
#define RSTC_RCAUSE_BACKUP_Pos _U_(7) /**< (RSTC_RCAUSE) Backup Reset Position */
#define RSTC_RCAUSE_BACKUP_Msk (_U_(0x1) << RSTC_RCAUSE_BACKUP_Pos) /**< (RSTC_RCAUSE) Backup Reset Mask */
#define RSTC_RCAUSE_BACKUP(value) (RSTC_RCAUSE_BACKUP_Msk & ((value) << RSTC_RCAUSE_BACKUP_Pos))
#define RSTC_RCAUSE_Msk _U_(0xFF) /**< (RSTC_RCAUSE) Register Mask */
/* -------- RSTC_BKUPEXIT : (RSTC Offset: 0x02) ( R/ 8) Backup Exit Source -------- */
#define RSTC_BKUPEXIT_RESETVALUE _U_(0x00) /**< (RSTC_BKUPEXIT) Backup Exit Source Reset Value */
#define RSTC_BKUPEXIT_RTC_Pos _U_(1) /**< (RSTC_BKUPEXIT) Real Timer Counter Interrupt Position */
#define RSTC_BKUPEXIT_RTC_Msk (_U_(0x1) << RSTC_BKUPEXIT_RTC_Pos) /**< (RSTC_BKUPEXIT) Real Timer Counter Interrupt Mask */
#define RSTC_BKUPEXIT_RTC(value) (RSTC_BKUPEXIT_RTC_Msk & ((value) << RSTC_BKUPEXIT_RTC_Pos))
#define RSTC_BKUPEXIT_BBPS_Pos _U_(2) /**< (RSTC_BKUPEXIT) Battery Backup Power Switch Position */
#define RSTC_BKUPEXIT_BBPS_Msk (_U_(0x1) << RSTC_BKUPEXIT_BBPS_Pos) /**< (RSTC_BKUPEXIT) Battery Backup Power Switch Mask */
#define RSTC_BKUPEXIT_BBPS(value) (RSTC_BKUPEXIT_BBPS_Msk & ((value) << RSTC_BKUPEXIT_BBPS_Pos))
#define RSTC_BKUPEXIT_HIB_Pos _U_(7) /**< (RSTC_BKUPEXIT) Hibernate Position */
#define RSTC_BKUPEXIT_HIB_Msk (_U_(0x1) << RSTC_BKUPEXIT_HIB_Pos) /**< (RSTC_BKUPEXIT) Hibernate Mask */
#define RSTC_BKUPEXIT_HIB(value) (RSTC_BKUPEXIT_HIB_Msk & ((value) << RSTC_BKUPEXIT_HIB_Pos))
#define RSTC_BKUPEXIT_Msk _U_(0x86) /**< (RSTC_BKUPEXIT) Register Mask */
/** \brief RSTC register offsets definitions */
#define RSTC_RCAUSE_REG_OFST (0x00) /**< (RSTC_RCAUSE) Reset Cause Offset */
#define RSTC_BKUPEXIT_REG_OFST (0x02) /**< (RSTC_BKUPEXIT) Backup Exit Source Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief RSTC register API structure */
typedef struct
{ /* Reset Controller */
__I uint8_t RSTC_RCAUSE; /**< Offset: 0x00 (R/ 8) Reset Cause */
__I uint8_t Reserved1[0x01];
__I uint8_t RSTC_BKUPEXIT; /**< Offset: 0x02 (R/ 8) Backup Exit Source */
} rstc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_RSTC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/supc.h
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/**
* \brief Component description for SUPC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_SUPC_COMPONENT_H_
#define _SAMD51_SUPC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR SUPC */
/* ************************************************************************** */
/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#define SUPC_INTENCLR_RESETVALUE _U_(0x00) /**< (SUPC_INTENCLR) Interrupt Enable Clear Reset Value */
#define SUPC_INTENCLR_BOD33RDY_Pos _U_(0) /**< (SUPC_INTENCLR) BOD33 Ready Position */
#define SUPC_INTENCLR_BOD33RDY_Msk (_U_(0x1) << SUPC_INTENCLR_BOD33RDY_Pos) /**< (SUPC_INTENCLR) BOD33 Ready Mask */
#define SUPC_INTENCLR_BOD33RDY(value) (SUPC_INTENCLR_BOD33RDY_Msk & ((value) << SUPC_INTENCLR_BOD33RDY_Pos))
#define SUPC_INTENCLR_BOD33DET_Pos _U_(1) /**< (SUPC_INTENCLR) BOD33 Detection Position */
#define SUPC_INTENCLR_BOD33DET_Msk (_U_(0x1) << SUPC_INTENCLR_BOD33DET_Pos) /**< (SUPC_INTENCLR) BOD33 Detection Mask */
#define SUPC_INTENCLR_BOD33DET(value) (SUPC_INTENCLR_BOD33DET_Msk & ((value) << SUPC_INTENCLR_BOD33DET_Pos))
#define SUPC_INTENCLR_B33SRDY_Pos _U_(2) /**< (SUPC_INTENCLR) BOD33 Synchronization Ready Position */
#define SUPC_INTENCLR_B33SRDY_Msk (_U_(0x1) << SUPC_INTENCLR_B33SRDY_Pos) /**< (SUPC_INTENCLR) BOD33 Synchronization Ready Mask */
#define SUPC_INTENCLR_B33SRDY(value) (SUPC_INTENCLR_B33SRDY_Msk & ((value) << SUPC_INTENCLR_B33SRDY_Pos))
#define SUPC_INTENCLR_VREGRDY_Pos _U_(8) /**< (SUPC_INTENCLR) Voltage Regulator Ready Position */
#define SUPC_INTENCLR_VREGRDY_Msk (_U_(0x1) << SUPC_INTENCLR_VREGRDY_Pos) /**< (SUPC_INTENCLR) Voltage Regulator Ready Mask */
#define SUPC_INTENCLR_VREGRDY(value) (SUPC_INTENCLR_VREGRDY_Msk & ((value) << SUPC_INTENCLR_VREGRDY_Pos))
#define SUPC_INTENCLR_VCORERDY_Pos _U_(10) /**< (SUPC_INTENCLR) VDDCORE Ready Position */
#define SUPC_INTENCLR_VCORERDY_Msk (_U_(0x1) << SUPC_INTENCLR_VCORERDY_Pos) /**< (SUPC_INTENCLR) VDDCORE Ready Mask */
#define SUPC_INTENCLR_VCORERDY(value) (SUPC_INTENCLR_VCORERDY_Msk & ((value) << SUPC_INTENCLR_VCORERDY_Pos))
#define SUPC_INTENCLR_Msk _U_(0x00000507) /**< (SUPC_INTENCLR) Register Mask */
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#define SUPC_INTENSET_RESETVALUE _U_(0x00) /**< (SUPC_INTENSET) Interrupt Enable Set Reset Value */
#define SUPC_INTENSET_BOD33RDY_Pos _U_(0) /**< (SUPC_INTENSET) BOD33 Ready Position */
#define SUPC_INTENSET_BOD33RDY_Msk (_U_(0x1) << SUPC_INTENSET_BOD33RDY_Pos) /**< (SUPC_INTENSET) BOD33 Ready Mask */
#define SUPC_INTENSET_BOD33RDY(value) (SUPC_INTENSET_BOD33RDY_Msk & ((value) << SUPC_INTENSET_BOD33RDY_Pos))
#define SUPC_INTENSET_BOD33DET_Pos _U_(1) /**< (SUPC_INTENSET) BOD33 Detection Position */
#define SUPC_INTENSET_BOD33DET_Msk (_U_(0x1) << SUPC_INTENSET_BOD33DET_Pos) /**< (SUPC_INTENSET) BOD33 Detection Mask */
#define SUPC_INTENSET_BOD33DET(value) (SUPC_INTENSET_BOD33DET_Msk & ((value) << SUPC_INTENSET_BOD33DET_Pos))
#define SUPC_INTENSET_B33SRDY_Pos _U_(2) /**< (SUPC_INTENSET) BOD33 Synchronization Ready Position */
#define SUPC_INTENSET_B33SRDY_Msk (_U_(0x1) << SUPC_INTENSET_B33SRDY_Pos) /**< (SUPC_INTENSET) BOD33 Synchronization Ready Mask */
#define SUPC_INTENSET_B33SRDY(value) (SUPC_INTENSET_B33SRDY_Msk & ((value) << SUPC_INTENSET_B33SRDY_Pos))
#define SUPC_INTENSET_VREGRDY_Pos _U_(8) /**< (SUPC_INTENSET) Voltage Regulator Ready Position */
#define SUPC_INTENSET_VREGRDY_Msk (_U_(0x1) << SUPC_INTENSET_VREGRDY_Pos) /**< (SUPC_INTENSET) Voltage Regulator Ready Mask */
#define SUPC_INTENSET_VREGRDY(value) (SUPC_INTENSET_VREGRDY_Msk & ((value) << SUPC_INTENSET_VREGRDY_Pos))
#define SUPC_INTENSET_VCORERDY_Pos _U_(10) /**< (SUPC_INTENSET) VDDCORE Ready Position */
#define SUPC_INTENSET_VCORERDY_Msk (_U_(0x1) << SUPC_INTENSET_VCORERDY_Pos) /**< (SUPC_INTENSET) VDDCORE Ready Mask */
#define SUPC_INTENSET_VCORERDY(value) (SUPC_INTENSET_VCORERDY_Msk & ((value) << SUPC_INTENSET_VCORERDY_Pos))
#define SUPC_INTENSET_Msk _U_(0x00000507) /**< (SUPC_INTENSET) Register Mask */
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#define SUPC_INTFLAG_RESETVALUE _U_(0x00) /**< (SUPC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define SUPC_INTFLAG_BOD33RDY_Pos _U_(0) /**< (SUPC_INTFLAG) BOD33 Ready Position */
#define SUPC_INTFLAG_BOD33RDY_Msk (_U_(0x1) << SUPC_INTFLAG_BOD33RDY_Pos) /**< (SUPC_INTFLAG) BOD33 Ready Mask */
#define SUPC_INTFLAG_BOD33RDY(value) (SUPC_INTFLAG_BOD33RDY_Msk & ((value) << SUPC_INTFLAG_BOD33RDY_Pos))
#define SUPC_INTFLAG_BOD33DET_Pos _U_(1) /**< (SUPC_INTFLAG) BOD33 Detection Position */
#define SUPC_INTFLAG_BOD33DET_Msk (_U_(0x1) << SUPC_INTFLAG_BOD33DET_Pos) /**< (SUPC_INTFLAG) BOD33 Detection Mask */
#define SUPC_INTFLAG_BOD33DET(value) (SUPC_INTFLAG_BOD33DET_Msk & ((value) << SUPC_INTFLAG_BOD33DET_Pos))
#define SUPC_INTFLAG_B33SRDY_Pos _U_(2) /**< (SUPC_INTFLAG) BOD33 Synchronization Ready Position */
#define SUPC_INTFLAG_B33SRDY_Msk (_U_(0x1) << SUPC_INTFLAG_B33SRDY_Pos) /**< (SUPC_INTFLAG) BOD33 Synchronization Ready Mask */
#define SUPC_INTFLAG_B33SRDY(value) (SUPC_INTFLAG_B33SRDY_Msk & ((value) << SUPC_INTFLAG_B33SRDY_Pos))
#define SUPC_INTFLAG_VREGRDY_Pos _U_(8) /**< (SUPC_INTFLAG) Voltage Regulator Ready Position */
#define SUPC_INTFLAG_VREGRDY_Msk (_U_(0x1) << SUPC_INTFLAG_VREGRDY_Pos) /**< (SUPC_INTFLAG) Voltage Regulator Ready Mask */
#define SUPC_INTFLAG_VREGRDY(value) (SUPC_INTFLAG_VREGRDY_Msk & ((value) << SUPC_INTFLAG_VREGRDY_Pos))
#define SUPC_INTFLAG_VCORERDY_Pos _U_(10) /**< (SUPC_INTFLAG) VDDCORE Ready Position */
#define SUPC_INTFLAG_VCORERDY_Msk (_U_(0x1) << SUPC_INTFLAG_VCORERDY_Pos) /**< (SUPC_INTFLAG) VDDCORE Ready Mask */
#define SUPC_INTFLAG_VCORERDY(value) (SUPC_INTFLAG_VCORERDY_Msk & ((value) << SUPC_INTFLAG_VCORERDY_Pos))
#define SUPC_INTFLAG_Msk _U_(0x00000507) /**< (SUPC_INTFLAG) Register Mask */
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */
#define SUPC_STATUS_RESETVALUE _U_(0x00) /**< (SUPC_STATUS) Power and Clocks Status Reset Value */
#define SUPC_STATUS_BOD33RDY_Pos _U_(0) /**< (SUPC_STATUS) BOD33 Ready Position */
#define SUPC_STATUS_BOD33RDY_Msk (_U_(0x1) << SUPC_STATUS_BOD33RDY_Pos) /**< (SUPC_STATUS) BOD33 Ready Mask */
#define SUPC_STATUS_BOD33RDY(value) (SUPC_STATUS_BOD33RDY_Msk & ((value) << SUPC_STATUS_BOD33RDY_Pos))
#define SUPC_STATUS_BOD33DET_Pos _U_(1) /**< (SUPC_STATUS) BOD33 Detection Position */
#define SUPC_STATUS_BOD33DET_Msk (_U_(0x1) << SUPC_STATUS_BOD33DET_Pos) /**< (SUPC_STATUS) BOD33 Detection Mask */
#define SUPC_STATUS_BOD33DET(value) (SUPC_STATUS_BOD33DET_Msk & ((value) << SUPC_STATUS_BOD33DET_Pos))
#define SUPC_STATUS_B33SRDY_Pos _U_(2) /**< (SUPC_STATUS) BOD33 Synchronization Ready Position */
#define SUPC_STATUS_B33SRDY_Msk (_U_(0x1) << SUPC_STATUS_B33SRDY_Pos) /**< (SUPC_STATUS) BOD33 Synchronization Ready Mask */
#define SUPC_STATUS_B33SRDY(value) (SUPC_STATUS_B33SRDY_Msk & ((value) << SUPC_STATUS_B33SRDY_Pos))
#define SUPC_STATUS_VREGRDY_Pos _U_(8) /**< (SUPC_STATUS) Voltage Regulator Ready Position */
#define SUPC_STATUS_VREGRDY_Msk (_U_(0x1) << SUPC_STATUS_VREGRDY_Pos) /**< (SUPC_STATUS) Voltage Regulator Ready Mask */
#define SUPC_STATUS_VREGRDY(value) (SUPC_STATUS_VREGRDY_Msk & ((value) << SUPC_STATUS_VREGRDY_Pos))
#define SUPC_STATUS_VCORERDY_Pos _U_(10) /**< (SUPC_STATUS) VDDCORE Ready Position */
#define SUPC_STATUS_VCORERDY_Msk (_U_(0x1) << SUPC_STATUS_VCORERDY_Pos) /**< (SUPC_STATUS) VDDCORE Ready Mask */
#define SUPC_STATUS_VCORERDY(value) (SUPC_STATUS_VCORERDY_Msk & ((value) << SUPC_STATUS_VCORERDY_Pos))
#define SUPC_STATUS_Msk _U_(0x00000507) /**< (SUPC_STATUS) Register Mask */
/* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */
#define SUPC_BOD33_RESETVALUE _U_(0x00) /**< (SUPC_BOD33) BOD33 Control Reset Value */
#define SUPC_BOD33_ENABLE_Pos _U_(1) /**< (SUPC_BOD33) Enable Position */
#define SUPC_BOD33_ENABLE_Msk (_U_(0x1) << SUPC_BOD33_ENABLE_Pos) /**< (SUPC_BOD33) Enable Mask */
#define SUPC_BOD33_ENABLE(value) (SUPC_BOD33_ENABLE_Msk & ((value) << SUPC_BOD33_ENABLE_Pos))
#define SUPC_BOD33_ACTION_Pos _U_(2) /**< (SUPC_BOD33) Action when Threshold Crossed Position */
#define SUPC_BOD33_ACTION_Msk (_U_(0x3) << SUPC_BOD33_ACTION_Pos) /**< (SUPC_BOD33) Action when Threshold Crossed Mask */
#define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))
#define SUPC_BOD33_ACTION_NONE_Val _U_(0x0) /**< (SUPC_BOD33) No action */
#define SUPC_BOD33_ACTION_RESET_Val _U_(0x1) /**< (SUPC_BOD33) The BOD33 generates a reset */
#define SUPC_BOD33_ACTION_INT_Val _U_(0x2) /**< (SUPC_BOD33) The BOD33 generates an interrupt */
#define SUPC_BOD33_ACTION_BKUP_Val _U_(0x3) /**< (SUPC_BOD33) The BOD33 puts the device in backup sleep mode */
#define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) /**< (SUPC_BOD33) No action Position */
#define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) /**< (SUPC_BOD33) The BOD33 generates a reset Position */
#define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) /**< (SUPC_BOD33) The BOD33 generates an interrupt Position */
#define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) /**< (SUPC_BOD33) The BOD33 puts the device in backup sleep mode Position */
#define SUPC_BOD33_STDBYCFG_Pos _U_(4) /**< (SUPC_BOD33) Configuration in Standby mode Position */
#define SUPC_BOD33_STDBYCFG_Msk (_U_(0x1) << SUPC_BOD33_STDBYCFG_Pos) /**< (SUPC_BOD33) Configuration in Standby mode Mask */
#define SUPC_BOD33_STDBYCFG(value) (SUPC_BOD33_STDBYCFG_Msk & ((value) << SUPC_BOD33_STDBYCFG_Pos))
#define SUPC_BOD33_RUNSTDBY_Pos _U_(5) /**< (SUPC_BOD33) Run in Standby mode Position */
#define SUPC_BOD33_RUNSTDBY_Msk (_U_(0x1) << SUPC_BOD33_RUNSTDBY_Pos) /**< (SUPC_BOD33) Run in Standby mode Mask */
#define SUPC_BOD33_RUNSTDBY(value) (SUPC_BOD33_RUNSTDBY_Msk & ((value) << SUPC_BOD33_RUNSTDBY_Pos))
#define SUPC_BOD33_RUNHIB_Pos _U_(6) /**< (SUPC_BOD33) Run in Hibernate mode Position */
#define SUPC_BOD33_RUNHIB_Msk (_U_(0x1) << SUPC_BOD33_RUNHIB_Pos) /**< (SUPC_BOD33) Run in Hibernate mode Mask */
#define SUPC_BOD33_RUNHIB(value) (SUPC_BOD33_RUNHIB_Msk & ((value) << SUPC_BOD33_RUNHIB_Pos))
#define SUPC_BOD33_RUNBKUP_Pos _U_(7) /**< (SUPC_BOD33) Run in Backup mode Position */
#define SUPC_BOD33_RUNBKUP_Msk (_U_(0x1) << SUPC_BOD33_RUNBKUP_Pos) /**< (SUPC_BOD33) Run in Backup mode Mask */
#define SUPC_BOD33_RUNBKUP(value) (SUPC_BOD33_RUNBKUP_Msk & ((value) << SUPC_BOD33_RUNBKUP_Pos))
#define SUPC_BOD33_HYST_Pos _U_(8) /**< (SUPC_BOD33) Hysteresis value Position */
#define SUPC_BOD33_HYST_Msk (_U_(0xF) << SUPC_BOD33_HYST_Pos) /**< (SUPC_BOD33) Hysteresis value Mask */
#define SUPC_BOD33_HYST(value) (SUPC_BOD33_HYST_Msk & ((value) << SUPC_BOD33_HYST_Pos))
#define SUPC_BOD33_PSEL_Pos _U_(12) /**< (SUPC_BOD33) Prescaler Select Position */
#define SUPC_BOD33_PSEL_Msk (_U_(0x7) << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Prescaler Select Mask */
#define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))
#define SUPC_BOD33_PSEL_NODIV_Val _U_(0x0) /**< (SUPC_BOD33) Not divided */
#define SUPC_BOD33_PSEL_DIV4_Val _U_(0x1) /**< (SUPC_BOD33) Divide clock by 4 */
#define SUPC_BOD33_PSEL_DIV8_Val _U_(0x2) /**< (SUPC_BOD33) Divide clock by 8 */
#define SUPC_BOD33_PSEL_DIV16_Val _U_(0x3) /**< (SUPC_BOD33) Divide clock by 16 */
#define SUPC_BOD33_PSEL_DIV32_Val _U_(0x4) /**< (SUPC_BOD33) Divide clock by 32 */
#define SUPC_BOD33_PSEL_DIV64_Val _U_(0x5) /**< (SUPC_BOD33) Divide clock by 64 */
#define SUPC_BOD33_PSEL_DIV128_Val _U_(0x6) /**< (SUPC_BOD33) Divide clock by 128 */
#define SUPC_BOD33_PSEL_DIV256_Val _U_(0x7) /**< (SUPC_BOD33) Divide clock by 256 */
#define SUPC_BOD33_PSEL_NODIV (SUPC_BOD33_PSEL_NODIV_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Not divided Position */
#define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 4 Position */
#define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 8 Position */
#define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 16 Position */
#define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 32 Position */
#define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 64 Position */
#define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 128 Position */
#define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) /**< (SUPC_BOD33) Divide clock by 256 Position */
#define SUPC_BOD33_LEVEL_Pos _U_(16) /**< (SUPC_BOD33) Threshold Level for VDD Position */
#define SUPC_BOD33_LEVEL_Msk (_U_(0xFF) << SUPC_BOD33_LEVEL_Pos) /**< (SUPC_BOD33) Threshold Level for VDD Mask */
#define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))
#define SUPC_BOD33_VBATLEVEL_Pos _U_(24) /**< (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT Position */
#define SUPC_BOD33_VBATLEVEL_Msk (_U_(0xFF) << SUPC_BOD33_VBATLEVEL_Pos) /**< (SUPC_BOD33) Threshold Level in battery backup sleep mode for VBAT Mask */
#define SUPC_BOD33_VBATLEVEL(value) (SUPC_BOD33_VBATLEVEL_Msk & ((value) << SUPC_BOD33_VBATLEVEL_Pos))
#define SUPC_BOD33_Msk _U_(0xFFFF7FFE) /**< (SUPC_BOD33) Register Mask */
/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
#define SUPC_VREG_RESETVALUE _U_(0x02) /**< (SUPC_VREG) VREG Control Reset Value */
#define SUPC_VREG_ENABLE_Pos _U_(1) /**< (SUPC_VREG) Enable Position */
#define SUPC_VREG_ENABLE_Msk (_U_(0x1) << SUPC_VREG_ENABLE_Pos) /**< (SUPC_VREG) Enable Mask */
#define SUPC_VREG_ENABLE(value) (SUPC_VREG_ENABLE_Msk & ((value) << SUPC_VREG_ENABLE_Pos))
#define SUPC_VREG_SEL_Pos _U_(2) /**< (SUPC_VREG) Voltage Regulator Selection Position */
#define SUPC_VREG_SEL_Msk (_U_(0x1) << SUPC_VREG_SEL_Pos) /**< (SUPC_VREG) Voltage Regulator Selection Mask */
#define SUPC_VREG_SEL(value) (SUPC_VREG_SEL_Msk & ((value) << SUPC_VREG_SEL_Pos))
#define SUPC_VREG_SEL_LDO_Val _U_(0x0) /**< (SUPC_VREG) LDO selection */
#define SUPC_VREG_SEL_BUCK_Val _U_(0x1) /**< (SUPC_VREG) Buck selection */
#define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) /**< (SUPC_VREG) LDO selection Position */
#define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) /**< (SUPC_VREG) Buck selection Position */
#define SUPC_VREG_RUNBKUP_Pos _U_(7) /**< (SUPC_VREG) Run in Backup mode Position */
#define SUPC_VREG_RUNBKUP_Msk (_U_(0x1) << SUPC_VREG_RUNBKUP_Pos) /**< (SUPC_VREG) Run in Backup mode Mask */
#define SUPC_VREG_RUNBKUP(value) (SUPC_VREG_RUNBKUP_Msk & ((value) << SUPC_VREG_RUNBKUP_Pos))
#define SUPC_VREG_VSEN_Pos _U_(16) /**< (SUPC_VREG) Voltage Scaling Enable Position */
#define SUPC_VREG_VSEN_Msk (_U_(0x1) << SUPC_VREG_VSEN_Pos) /**< (SUPC_VREG) Voltage Scaling Enable Mask */
#define SUPC_VREG_VSEN(value) (SUPC_VREG_VSEN_Msk & ((value) << SUPC_VREG_VSEN_Pos))
#define SUPC_VREG_VSPER_Pos _U_(24) /**< (SUPC_VREG) Voltage Scaling Period Position */
#define SUPC_VREG_VSPER_Msk (_U_(0x7) << SUPC_VREG_VSPER_Pos) /**< (SUPC_VREG) Voltage Scaling Period Mask */
#define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))
#define SUPC_VREG_Msk _U_(0x07010086) /**< (SUPC_VREG) Register Mask */
/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
#define SUPC_VREF_RESETVALUE _U_(0x00) /**< (SUPC_VREF) VREF Control Reset Value */
#define SUPC_VREF_TSEN_Pos _U_(1) /**< (SUPC_VREF) Temperature Sensor Output Enable Position */
#define SUPC_VREF_TSEN_Msk (_U_(0x1) << SUPC_VREF_TSEN_Pos) /**< (SUPC_VREF) Temperature Sensor Output Enable Mask */
#define SUPC_VREF_TSEN(value) (SUPC_VREF_TSEN_Msk & ((value) << SUPC_VREF_TSEN_Pos))
#define SUPC_VREF_VREFOE_Pos _U_(2) /**< (SUPC_VREF) Voltage Reference Output Enable Position */
#define SUPC_VREF_VREFOE_Msk (_U_(0x1) << SUPC_VREF_VREFOE_Pos) /**< (SUPC_VREF) Voltage Reference Output Enable Mask */
#define SUPC_VREF_VREFOE(value) (SUPC_VREF_VREFOE_Msk & ((value) << SUPC_VREF_VREFOE_Pos))
#define SUPC_VREF_TSSEL_Pos _U_(3) /**< (SUPC_VREF) Temperature Sensor Selection Position */
#define SUPC_VREF_TSSEL_Msk (_U_(0x1) << SUPC_VREF_TSSEL_Pos) /**< (SUPC_VREF) Temperature Sensor Selection Mask */
#define SUPC_VREF_TSSEL(value) (SUPC_VREF_TSSEL_Msk & ((value) << SUPC_VREF_TSSEL_Pos))
#define SUPC_VREF_RUNSTDBY_Pos _U_(6) /**< (SUPC_VREF) Run during Standby Position */
#define SUPC_VREF_RUNSTDBY_Msk (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos) /**< (SUPC_VREF) Run during Standby Mask */
#define SUPC_VREF_RUNSTDBY(value) (SUPC_VREF_RUNSTDBY_Msk & ((value) << SUPC_VREF_RUNSTDBY_Pos))
#define SUPC_VREF_ONDEMAND_Pos _U_(7) /**< (SUPC_VREF) On Demand Contrl Position */
#define SUPC_VREF_ONDEMAND_Msk (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos) /**< (SUPC_VREF) On Demand Contrl Mask */
#define SUPC_VREF_ONDEMAND(value) (SUPC_VREF_ONDEMAND_Msk & ((value) << SUPC_VREF_ONDEMAND_Pos))
#define SUPC_VREF_SEL_Pos _U_(16) /**< (SUPC_VREF) Voltage Reference Selection Position */
#define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) Voltage Reference Selection Mask */
#define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
#define SUPC_VREF_SEL_1V0_Val _U_(0x0) /**< (SUPC_VREF) 1.0V voltage reference typical value */
#define SUPC_VREF_SEL_1V1_Val _U_(0x1) /**< (SUPC_VREF) 1.1V voltage reference typical value */
#define SUPC_VREF_SEL_1V2_Val _U_(0x2) /**< (SUPC_VREF) 1.2V voltage reference typical value */
#define SUPC_VREF_SEL_1V25_Val _U_(0x3) /**< (SUPC_VREF) 1.25V voltage reference typical value */
#define SUPC_VREF_SEL_2V0_Val _U_(0x4) /**< (SUPC_VREF) 2.0V voltage reference typical value */
#define SUPC_VREF_SEL_2V2_Val _U_(0x5) /**< (SUPC_VREF) 2.2V voltage reference typical value */
#define SUPC_VREF_SEL_2V4_Val _U_(0x6) /**< (SUPC_VREF) 2.4V voltage reference typical value */
#define SUPC_VREF_SEL_2V5_Val _U_(0x7) /**< (SUPC_VREF) 2.5V voltage reference typical value */
#define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 1.0V voltage reference typical value Position */
#define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 1.1V voltage reference typical value Position */
#define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 1.2V voltage reference typical value Position */
#define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 1.25V voltage reference typical value Position */
#define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 2.0V voltage reference typical value Position */
#define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 2.2V voltage reference typical value Position */
#define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 2.4V voltage reference typical value Position */
#define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) /**< (SUPC_VREF) 2.5V voltage reference typical value Position */
#define SUPC_VREF_Msk _U_(0x000F00CE) /**< (SUPC_VREF) Register Mask */
/* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */
#define SUPC_BBPS_RESETVALUE _U_(0x00) /**< (SUPC_BBPS) Battery Backup Power Switch Reset Value */
#define SUPC_BBPS_CONF_Pos _U_(0) /**< (SUPC_BBPS) Battery Backup Configuration Position */
#define SUPC_BBPS_CONF_Msk (_U_(0x1) << SUPC_BBPS_CONF_Pos) /**< (SUPC_BBPS) Battery Backup Configuration Mask */
#define SUPC_BBPS_CONF(value) (SUPC_BBPS_CONF_Msk & ((value) << SUPC_BBPS_CONF_Pos))
#define SUPC_BBPS_CONF_BOD33_Val _U_(0x0) /**< (SUPC_BBPS) The power switch is handled by the BOD33 */
#define SUPC_BBPS_CONF_FORCED_Val _U_(0x1) /**< (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power */
#define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) /**< (SUPC_BBPS) The power switch is handled by the BOD33 Position */
#define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) /**< (SUPC_BBPS) In Backup Domain, the backup domain is always supplied by battery backup power Position */
#define SUPC_BBPS_WAKEEN_Pos _U_(2) /**< (SUPC_BBPS) Wake Enable Position */
#define SUPC_BBPS_WAKEEN_Msk (_U_(0x1) << SUPC_BBPS_WAKEEN_Pos) /**< (SUPC_BBPS) Wake Enable Mask */
#define SUPC_BBPS_WAKEEN(value) (SUPC_BBPS_WAKEEN_Msk & ((value) << SUPC_BBPS_WAKEEN_Pos))
#define SUPC_BBPS_Msk _U_(0x00000005) /**< (SUPC_BBPS) Register Mask */
/* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */
#define SUPC_BKOUT_RESETVALUE _U_(0x00) /**< (SUPC_BKOUT) Backup Output Control Reset Value */
#define SUPC_BKOUT_ENOUT0_Pos _U_(0) /**< (SUPC_BKOUT) Enable OUT0 Position */
#define SUPC_BKOUT_ENOUT0_Msk (_U_(0x1) << SUPC_BKOUT_ENOUT0_Pos) /**< (SUPC_BKOUT) Enable OUT0 Mask */
#define SUPC_BKOUT_ENOUT0(value) (SUPC_BKOUT_ENOUT0_Msk & ((value) << SUPC_BKOUT_ENOUT0_Pos))
#define SUPC_BKOUT_ENOUT1_Pos _U_(1) /**< (SUPC_BKOUT) Enable OUT1 Position */
#define SUPC_BKOUT_ENOUT1_Msk (_U_(0x1) << SUPC_BKOUT_ENOUT1_Pos) /**< (SUPC_BKOUT) Enable OUT1 Mask */
#define SUPC_BKOUT_ENOUT1(value) (SUPC_BKOUT_ENOUT1_Msk & ((value) << SUPC_BKOUT_ENOUT1_Pos))
#define SUPC_BKOUT_CLROUT0_Pos _U_(8) /**< (SUPC_BKOUT) Clear OUT0 Position */
#define SUPC_BKOUT_CLROUT0_Msk (_U_(0x1) << SUPC_BKOUT_CLROUT0_Pos) /**< (SUPC_BKOUT) Clear OUT0 Mask */
#define SUPC_BKOUT_CLROUT0(value) (SUPC_BKOUT_CLROUT0_Msk & ((value) << SUPC_BKOUT_CLROUT0_Pos))
#define SUPC_BKOUT_CLROUT1_Pos _U_(9) /**< (SUPC_BKOUT) Clear OUT1 Position */
#define SUPC_BKOUT_CLROUT1_Msk (_U_(0x1) << SUPC_BKOUT_CLROUT1_Pos) /**< (SUPC_BKOUT) Clear OUT1 Mask */
#define SUPC_BKOUT_CLROUT1(value) (SUPC_BKOUT_CLROUT1_Msk & ((value) << SUPC_BKOUT_CLROUT1_Pos))
#define SUPC_BKOUT_SETOUT0_Pos _U_(16) /**< (SUPC_BKOUT) Set OUT0 Position */
#define SUPC_BKOUT_SETOUT0_Msk (_U_(0x1) << SUPC_BKOUT_SETOUT0_Pos) /**< (SUPC_BKOUT) Set OUT0 Mask */
#define SUPC_BKOUT_SETOUT0(value) (SUPC_BKOUT_SETOUT0_Msk & ((value) << SUPC_BKOUT_SETOUT0_Pos))
#define SUPC_BKOUT_SETOUT1_Pos _U_(17) /**< (SUPC_BKOUT) Set OUT1 Position */
#define SUPC_BKOUT_SETOUT1_Msk (_U_(0x1) << SUPC_BKOUT_SETOUT1_Pos) /**< (SUPC_BKOUT) Set OUT1 Mask */
#define SUPC_BKOUT_SETOUT1(value) (SUPC_BKOUT_SETOUT1_Msk & ((value) << SUPC_BKOUT_SETOUT1_Pos))
#define SUPC_BKOUT_RTCTGLOUT0_Pos _U_(24) /**< (SUPC_BKOUT) RTC Toggle OUT0 Position */
#define SUPC_BKOUT_RTCTGLOUT0_Msk (_U_(0x1) << SUPC_BKOUT_RTCTGLOUT0_Pos) /**< (SUPC_BKOUT) RTC Toggle OUT0 Mask */
#define SUPC_BKOUT_RTCTGLOUT0(value) (SUPC_BKOUT_RTCTGLOUT0_Msk & ((value) << SUPC_BKOUT_RTCTGLOUT0_Pos))
#define SUPC_BKOUT_RTCTGLOUT1_Pos _U_(25) /**< (SUPC_BKOUT) RTC Toggle OUT1 Position */
#define SUPC_BKOUT_RTCTGLOUT1_Msk (_U_(0x1) << SUPC_BKOUT_RTCTGLOUT1_Pos) /**< (SUPC_BKOUT) RTC Toggle OUT1 Mask */
#define SUPC_BKOUT_RTCTGLOUT1(value) (SUPC_BKOUT_RTCTGLOUT1_Msk & ((value) << SUPC_BKOUT_RTCTGLOUT1_Pos))
#define SUPC_BKOUT_Msk _U_(0x03030303) /**< (SUPC_BKOUT) Register Mask */
#define SUPC_BKOUT_ENOUT_Pos _U_(0) /**< (SUPC_BKOUT Position) Enable OUTx */
#define SUPC_BKOUT_ENOUT_Msk (_U_(0x3) << SUPC_BKOUT_ENOUT_Pos) /**< (SUPC_BKOUT Mask) ENOUT */
#define SUPC_BKOUT_ENOUT(value) (SUPC_BKOUT_ENOUT_Msk & ((value) << SUPC_BKOUT_ENOUT_Pos))
#define SUPC_BKOUT_CLROUT_Pos _U_(8) /**< (SUPC_BKOUT Position) Clear OUTx */
#define SUPC_BKOUT_CLROUT_Msk (_U_(0x3) << SUPC_BKOUT_CLROUT_Pos) /**< (SUPC_BKOUT Mask) CLROUT */
#define SUPC_BKOUT_CLROUT(value) (SUPC_BKOUT_CLROUT_Msk & ((value) << SUPC_BKOUT_CLROUT_Pos))
#define SUPC_BKOUT_SETOUT_Pos _U_(16) /**< (SUPC_BKOUT Position) Set OUTx */
#define SUPC_BKOUT_SETOUT_Msk (_U_(0x3) << SUPC_BKOUT_SETOUT_Pos) /**< (SUPC_BKOUT Mask) SETOUT */
#define SUPC_BKOUT_SETOUT(value) (SUPC_BKOUT_SETOUT_Msk & ((value) << SUPC_BKOUT_SETOUT_Pos))
#define SUPC_BKOUT_RTCTGLOUT_Pos _U_(24) /**< (SUPC_BKOUT Position) RTC Toggle OUTx */
#define SUPC_BKOUT_RTCTGLOUT_Msk (_U_(0x3) << SUPC_BKOUT_RTCTGLOUT_Pos) /**< (SUPC_BKOUT Mask) RTCTGLOUT */
#define SUPC_BKOUT_RTCTGLOUT(value) (SUPC_BKOUT_RTCTGLOUT_Msk & ((value) << SUPC_BKOUT_RTCTGLOUT_Pos))
/* -------- SUPC_BKIN : (SUPC Offset: 0x28) ( R/ 32) Backup Input Control -------- */
#define SUPC_BKIN_RESETVALUE _U_(0x00) /**< (SUPC_BKIN) Backup Input Control Reset Value */
#define SUPC_BKIN_BKIN0_Pos _U_(0) /**< (SUPC_BKIN) Backup Input 0 Position */
#define SUPC_BKIN_BKIN0_Msk (_U_(0x1) << SUPC_BKIN_BKIN0_Pos) /**< (SUPC_BKIN) Backup Input 0 Mask */
#define SUPC_BKIN_BKIN0(value) (SUPC_BKIN_BKIN0_Msk & ((value) << SUPC_BKIN_BKIN0_Pos))
#define SUPC_BKIN_BKIN1_Pos _U_(1) /**< (SUPC_BKIN) Backup Input 1 Position */
#define SUPC_BKIN_BKIN1_Msk (_U_(0x1) << SUPC_BKIN_BKIN1_Pos) /**< (SUPC_BKIN) Backup Input 1 Mask */
#define SUPC_BKIN_BKIN1(value) (SUPC_BKIN_BKIN1_Msk & ((value) << SUPC_BKIN_BKIN1_Pos))
#define SUPC_BKIN_Msk _U_(0x00000003) /**< (SUPC_BKIN) Register Mask */
#define SUPC_BKIN_BKIN_Pos _U_(0) /**< (SUPC_BKIN Position) Backup Input x */
#define SUPC_BKIN_BKIN_Msk (_U_(0x3) << SUPC_BKIN_BKIN_Pos) /**< (SUPC_BKIN Mask) BKIN */
#define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))
/** \brief SUPC register offsets definitions */
#define SUPC_INTENCLR_REG_OFST (0x00) /**< (SUPC_INTENCLR) Interrupt Enable Clear Offset */
#define SUPC_INTENSET_REG_OFST (0x04) /**< (SUPC_INTENSET) Interrupt Enable Set Offset */
#define SUPC_INTFLAG_REG_OFST (0x08) /**< (SUPC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define SUPC_STATUS_REG_OFST (0x0C) /**< (SUPC_STATUS) Power and Clocks Status Offset */
#define SUPC_BOD33_REG_OFST (0x10) /**< (SUPC_BOD33) BOD33 Control Offset */
#define SUPC_VREG_REG_OFST (0x18) /**< (SUPC_VREG) VREG Control Offset */
#define SUPC_VREF_REG_OFST (0x1C) /**< (SUPC_VREF) VREF Control Offset */
#define SUPC_BBPS_REG_OFST (0x20) /**< (SUPC_BBPS) Battery Backup Power Switch Offset */
#define SUPC_BKOUT_REG_OFST (0x24) /**< (SUPC_BKOUT) Backup Output Control Offset */
#define SUPC_BKIN_REG_OFST (0x28) /**< (SUPC_BKIN) Backup Input Control Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief SUPC register API structure */
typedef struct
{ /* Supply Controller */
__IO uint32_t SUPC_INTENCLR; /**< Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO uint32_t SUPC_INTENSET; /**< Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO uint32_t SUPC_INTFLAG; /**< Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I uint32_t SUPC_STATUS; /**< Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO uint32_t SUPC_BOD33; /**< Offset: 0x10 (R/W 32) BOD33 Control */
__I uint8_t Reserved1[0x04];
__IO uint32_t SUPC_VREG; /**< Offset: 0x18 (R/W 32) VREG Control */
__IO uint32_t SUPC_VREF; /**< Offset: 0x1C (R/W 32) VREF Control */
__IO uint32_t SUPC_BBPS; /**< Offset: 0x20 (R/W 32) Battery Backup Power Switch */
__IO uint32_t SUPC_BKOUT; /**< Offset: 0x24 (R/W 32) Backup Output Control */
__I uint32_t SUPC_BKIN; /**< Offset: 0x28 (R/ 32) Backup Input Control */
} supc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_SUPC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/tc.h
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/**
* \brief Component description for TC
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_TC_COMPONENT_H_
#define _SAMD51_TC_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR TC */
/* ************************************************************************** */
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
#define TC_CTRLA_RESETVALUE _U_(0x00) /**< (TC_CTRLA) Control A Reset Value */
#define TC_CTRLA_SWRST_Pos _U_(0) /**< (TC_CTRLA) Software Reset Position */
#define TC_CTRLA_SWRST_Msk (_U_(0x1) << TC_CTRLA_SWRST_Pos) /**< (TC_CTRLA) Software Reset Mask */
#define TC_CTRLA_SWRST(value) (TC_CTRLA_SWRST_Msk & ((value) << TC_CTRLA_SWRST_Pos))
#define TC_CTRLA_ENABLE_Pos _U_(1) /**< (TC_CTRLA) Enable Position */
#define TC_CTRLA_ENABLE_Msk (_U_(0x1) << TC_CTRLA_ENABLE_Pos) /**< (TC_CTRLA) Enable Mask */
#define TC_CTRLA_ENABLE(value) (TC_CTRLA_ENABLE_Msk & ((value) << TC_CTRLA_ENABLE_Pos))
#define TC_CTRLA_MODE_Pos _U_(2) /**< (TC_CTRLA) Timer Counter Mode Position */
#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Timer Counter Mode Mask */
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< (TC_CTRLA) Counter in 16-bit mode */
#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< (TC_CTRLA) Counter in 8-bit mode */
#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< (TC_CTRLA) Counter in 32-bit mode */
#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 16-bit mode Position */
#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 8-bit mode Position */
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) /**< (TC_CTRLA) Counter in 32-bit mode Position */
#define TC_CTRLA_PRESCSYNC_Pos _U_(4) /**< (TC_CTRLA) Prescaler and Counter Synchronization Position */
#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Prescaler and Counter Synchronization Mask */
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< (TC_CTRLA) Reload or reset the counter on next generic clock */
#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock */
#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock Position */
#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock Position */
#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter Position */
#define TC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (TC_CTRLA) Run during Standby Position */
#define TC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos) /**< (TC_CTRLA) Run during Standby Mask */
#define TC_CTRLA_RUNSTDBY(value) (TC_CTRLA_RUNSTDBY_Msk & ((value) << TC_CTRLA_RUNSTDBY_Pos))
#define TC_CTRLA_ONDEMAND_Pos _U_(7) /**< (TC_CTRLA) Clock On Demand Position */
#define TC_CTRLA_ONDEMAND_Msk (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos) /**< (TC_CTRLA) Clock On Demand Mask */
#define TC_CTRLA_ONDEMAND(value) (TC_CTRLA_ONDEMAND_Msk & ((value) << TC_CTRLA_ONDEMAND_Pos))
#define TC_CTRLA_PRESCALER_Pos _U_(8) /**< (TC_CTRLA) Prescaler Position */
#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler Mask */
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< (TC_CTRLA) Prescaler: GCLK_TC */
#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< (TC_CTRLA) Prescaler: GCLK_TC/2 */
#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< (TC_CTRLA) Prescaler: GCLK_TC/4 */
#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< (TC_CTRLA) Prescaler: GCLK_TC/8 */
#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< (TC_CTRLA) Prescaler: GCLK_TC/16 */
#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (TC_CTRLA) Prescaler: GCLK_TC/64 */
#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< (TC_CTRLA) Prescaler: GCLK_TC/256 */
#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< (TC_CTRLA) Prescaler: GCLK_TC/1024 */
#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC Position */
#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/2 Position */
#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/4 Position */
#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/8 Position */
#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/16 Position */
#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/64 Position */
#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/256 Position */
#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/1024 Position */
#define TC_CTRLA_ALOCK_Pos _U_(11) /**< (TC_CTRLA) Auto Lock Position */
#define TC_CTRLA_ALOCK_Msk (_U_(0x1) << TC_CTRLA_ALOCK_Pos) /**< (TC_CTRLA) Auto Lock Mask */
#define TC_CTRLA_ALOCK(value) (TC_CTRLA_ALOCK_Msk & ((value) << TC_CTRLA_ALOCK_Pos))
#define TC_CTRLA_CAPTEN0_Pos _U_(16) /**< (TC_CTRLA) Capture Channel 0 Enable Position */
#define TC_CTRLA_CAPTEN0_Msk (_U_(0x1) << TC_CTRLA_CAPTEN0_Pos) /**< (TC_CTRLA) Capture Channel 0 Enable Mask */
#define TC_CTRLA_CAPTEN0(value) (TC_CTRLA_CAPTEN0_Msk & ((value) << TC_CTRLA_CAPTEN0_Pos))
#define TC_CTRLA_CAPTEN1_Pos _U_(17) /**< (TC_CTRLA) Capture Channel 1 Enable Position */
#define TC_CTRLA_CAPTEN1_Msk (_U_(0x1) << TC_CTRLA_CAPTEN1_Pos) /**< (TC_CTRLA) Capture Channel 1 Enable Mask */
#define TC_CTRLA_CAPTEN1(value) (TC_CTRLA_CAPTEN1_Msk & ((value) << TC_CTRLA_CAPTEN1_Pos))
#define TC_CTRLA_COPEN0_Pos _U_(20) /**< (TC_CTRLA) Capture On Pin 0 Enable Position */
#define TC_CTRLA_COPEN0_Msk (_U_(0x1) << TC_CTRLA_COPEN0_Pos) /**< (TC_CTRLA) Capture On Pin 0 Enable Mask */
#define TC_CTRLA_COPEN0(value) (TC_CTRLA_COPEN0_Msk & ((value) << TC_CTRLA_COPEN0_Pos))
#define TC_CTRLA_COPEN1_Pos _U_(21) /**< (TC_CTRLA) Capture On Pin 1 Enable Position */
#define TC_CTRLA_COPEN1_Msk (_U_(0x1) << TC_CTRLA_COPEN1_Pos) /**< (TC_CTRLA) Capture On Pin 1 Enable Mask */
#define TC_CTRLA_COPEN1(value) (TC_CTRLA_COPEN1_Msk & ((value) << TC_CTRLA_COPEN1_Pos))
#define TC_CTRLA_CAPTMODE0_Pos _U_(24) /**< (TC_CTRLA) Capture Mode Channel 0 Position */
#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos) /**< (TC_CTRLA) Capture Mode Channel 0 Mask */
#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0) /**< (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1) /**< (TC_CTRLA) Minimum capture */
#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2) /**< (TC_CTRLA) Maximum capture */
#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos) /**< (TC_CTRLA) Default capture Position */
#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos) /**< (TC_CTRLA) Minimum capture Position */
#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos) /**< (TC_CTRLA) Maximum capture Position */
#define TC_CTRLA_CAPTMODE1_Pos _U_(27) /**< (TC_CTRLA) Capture mode Channel 1 Position */
#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos) /**< (TC_CTRLA) Capture mode Channel 1 Mask */
#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0) /**< (TC_CTRLA) Default capture */
#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1) /**< (TC_CTRLA) Minimum capture */
#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2) /**< (TC_CTRLA) Maximum capture */
#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos) /**< (TC_CTRLA) Default capture Position */
#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos) /**< (TC_CTRLA) Minimum capture Position */
#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos) /**< (TC_CTRLA) Maximum capture Position */
#define TC_CTRLA_Msk _U_(0x1B330FFF) /**< (TC_CTRLA) Register Mask */
#define TC_CTRLA_CAPTEN_Pos _U_(16) /**< (TC_CTRLA Position) Capture Channel x Enable */
#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos) /**< (TC_CTRLA Mask) CAPTEN */
#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
#define TC_CTRLA_COPEN_Pos _U_(20) /**< (TC_CTRLA Position) Capture On Pin x Enable */
#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos) /**< (TC_CTRLA Mask) COPEN */
#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< (TC_CTRLBCLR) Control B Clear Reset Value */
#define TC_CTRLBCLR_DIR_Pos _U_(0) /**< (TC_CTRLBCLR) Counter Direction Position */
#define TC_CTRLBCLR_DIR_Msk (_U_(0x1) << TC_CTRLBCLR_DIR_Pos) /**< (TC_CTRLBCLR) Counter Direction Mask */
#define TC_CTRLBCLR_DIR(value) (TC_CTRLBCLR_DIR_Msk & ((value) << TC_CTRLBCLR_DIR_Pos))
#define TC_CTRLBCLR_LUPD_Pos _U_(1) /**< (TC_CTRLBCLR) Lock Update Position */
#define TC_CTRLBCLR_LUPD_Msk (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos) /**< (TC_CTRLBCLR) Lock Update Mask */
#define TC_CTRLBCLR_LUPD(value) (TC_CTRLBCLR_LUPD_Msk & ((value) << TC_CTRLBCLR_LUPD_Pos))
#define TC_CTRLBCLR_ONESHOT_Pos _U_(2) /**< (TC_CTRLBCLR) One-Shot on Counter Position */
#define TC_CTRLBCLR_ONESHOT_Msk (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos) /**< (TC_CTRLBCLR) One-Shot on Counter Mask */
#define TC_CTRLBCLR_ONESHOT(value) (TC_CTRLBCLR_ONESHOT_Msk & ((value) << TC_CTRLBCLR_ONESHOT_Pos))
#define TC_CTRLBCLR_CMD_Pos _U_(5) /**< (TC_CTRLBCLR) Command Position */
#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Command Mask */
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< (TC_CTRLBCLR) No action */
#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< (TC_CTRLBCLR) Force a start, restart or retrigger */
#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< (TC_CTRLBCLR) Force a stop */
#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< (TC_CTRLBCLR) Force update of double-buffered register */
#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< (TC_CTRLBCLR) Force a read synchronization of COUNT */
#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< (TC_CTRLBCLR) One-shot DMA trigger */
#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) No action Position */
#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a start, restart or retrigger Position */
#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a stop Position */
#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force update of double-buffered register Position */
#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a read synchronization of COUNT Position */
#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) One-shot DMA trigger Position */
#define TC_CTRLBCLR_Msk _U_(0xE7) /**< (TC_CTRLBCLR) Register Mask */
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< (TC_CTRLBSET) Control B Set Reset Value */
#define TC_CTRLBSET_DIR_Pos _U_(0) /**< (TC_CTRLBSET) Counter Direction Position */
#define TC_CTRLBSET_DIR_Msk (_U_(0x1) << TC_CTRLBSET_DIR_Pos) /**< (TC_CTRLBSET) Counter Direction Mask */
#define TC_CTRLBSET_DIR(value) (TC_CTRLBSET_DIR_Msk & ((value) << TC_CTRLBSET_DIR_Pos))
#define TC_CTRLBSET_LUPD_Pos _U_(1) /**< (TC_CTRLBSET) Lock Update Position */
#define TC_CTRLBSET_LUPD_Msk (_U_(0x1) << TC_CTRLBSET_LUPD_Pos) /**< (TC_CTRLBSET) Lock Update Mask */
#define TC_CTRLBSET_LUPD(value) (TC_CTRLBSET_LUPD_Msk & ((value) << TC_CTRLBSET_LUPD_Pos))
#define TC_CTRLBSET_ONESHOT_Pos _U_(2) /**< (TC_CTRLBSET) One-Shot on Counter Position */
#define TC_CTRLBSET_ONESHOT_Msk (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos) /**< (TC_CTRLBSET) One-Shot on Counter Mask */
#define TC_CTRLBSET_ONESHOT(value) (TC_CTRLBSET_ONESHOT_Msk & ((value) << TC_CTRLBSET_ONESHOT_Pos))
#define TC_CTRLBSET_CMD_Pos _U_(5) /**< (TC_CTRLBSET) Command Position */
#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Command Mask */
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< (TC_CTRLBSET) No action */
#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< (TC_CTRLBSET) Force a start, restart or retrigger */
#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< (TC_CTRLBSET) Force a stop */
#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< (TC_CTRLBSET) Force update of double-buffered register */
#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< (TC_CTRLBSET) Force a read synchronization of COUNT */
#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< (TC_CTRLBSET) One-shot DMA trigger */
#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) No action Position */
#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a start, restart or retrigger Position */
#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a stop Position */
#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force update of double-buffered register Position */
#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a read synchronization of COUNT Position */
#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) One-shot DMA trigger Position */
#define TC_CTRLBSET_Msk _U_(0xE7) /**< (TC_CTRLBSET) Register Mask */
/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
#define TC_EVCTRL_RESETVALUE _U_(0x00) /**< (TC_EVCTRL) Event Control Reset Value */
#define TC_EVCTRL_EVACT_Pos _U_(0) /**< (TC_EVCTRL) Event Action Position */
#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Event Action Mask */
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< (TC_EVCTRL) Event action disabled */
#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< (TC_EVCTRL) Start, restart or retrigger TC on event */
#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< (TC_EVCTRL) Count on event */
#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< (TC_EVCTRL) Start TC on event */
#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< (TC_EVCTRL) Time stamp capture */
#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< (TC_EVCTRL) Pulse width capture */
#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Event action disabled Position */
#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Start, restart or retrigger TC on event Position */
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Count on event Position */
#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Start TC on event Position */
#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Time stamp capture Position */
#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Period catured in CC0, pulse width in CC1 Position */
#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Period catured in CC1, pulse width in CC0 Position */
#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Pulse width capture Position */
#define TC_EVCTRL_TCINV_Pos _U_(4) /**< (TC_EVCTRL) TC Event Input Polarity Position */
#define TC_EVCTRL_TCINV_Msk (_U_(0x1) << TC_EVCTRL_TCINV_Pos) /**< (TC_EVCTRL) TC Event Input Polarity Mask */
#define TC_EVCTRL_TCINV(value) (TC_EVCTRL_TCINV_Msk & ((value) << TC_EVCTRL_TCINV_Pos))
#define TC_EVCTRL_TCEI_Pos _U_(5) /**< (TC_EVCTRL) TC Event Enable Position */
#define TC_EVCTRL_TCEI_Msk (_U_(0x1) << TC_EVCTRL_TCEI_Pos) /**< (TC_EVCTRL) TC Event Enable Mask */
#define TC_EVCTRL_TCEI(value) (TC_EVCTRL_TCEI_Msk & ((value) << TC_EVCTRL_TCEI_Pos))
#define TC_EVCTRL_OVFEO_Pos _U_(8) /**< (TC_EVCTRL) Event Output Enable Position */
#define TC_EVCTRL_OVFEO_Msk (_U_(0x1) << TC_EVCTRL_OVFEO_Pos) /**< (TC_EVCTRL) Event Output Enable Mask */
#define TC_EVCTRL_OVFEO(value) (TC_EVCTRL_OVFEO_Msk & ((value) << TC_EVCTRL_OVFEO_Pos))
#define TC_EVCTRL_MCEO0_Pos _U_(12) /**< (TC_EVCTRL) MC Event Output Enable 0 Position */
#define TC_EVCTRL_MCEO0_Msk (_U_(0x1) << TC_EVCTRL_MCEO0_Pos) /**< (TC_EVCTRL) MC Event Output Enable 0 Mask */
#define TC_EVCTRL_MCEO0(value) (TC_EVCTRL_MCEO0_Msk & ((value) << TC_EVCTRL_MCEO0_Pos))
#define TC_EVCTRL_MCEO1_Pos _U_(13) /**< (TC_EVCTRL) MC Event Output Enable 1 Position */
#define TC_EVCTRL_MCEO1_Msk (_U_(0x1) << TC_EVCTRL_MCEO1_Pos) /**< (TC_EVCTRL) MC Event Output Enable 1 Mask */
#define TC_EVCTRL_MCEO1(value) (TC_EVCTRL_MCEO1_Msk & ((value) << TC_EVCTRL_MCEO1_Pos))
#define TC_EVCTRL_Msk _U_(0x3137) /**< (TC_EVCTRL) Register Mask */
#define TC_EVCTRL_MCEO_Pos _U_(12) /**< (TC_EVCTRL Position) MC Event Output Enable x */
#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos) /**< (TC_EVCTRL Mask) MCEO */
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< (TC_INTENCLR) Interrupt Enable Clear Reset Value */
#define TC_INTENCLR_OVF_Pos _U_(0) /**< (TC_INTENCLR) OVF Interrupt Disable Position */
#define TC_INTENCLR_OVF_Msk (_U_(0x1) << TC_INTENCLR_OVF_Pos) /**< (TC_INTENCLR) OVF Interrupt Disable Mask */
#define TC_INTENCLR_OVF(value) (TC_INTENCLR_OVF_Msk & ((value) << TC_INTENCLR_OVF_Pos))
#define TC_INTENCLR_ERR_Pos _U_(1) /**< (TC_INTENCLR) ERR Interrupt Disable Position */
#define TC_INTENCLR_ERR_Msk (_U_(0x1) << TC_INTENCLR_ERR_Pos) /**< (TC_INTENCLR) ERR Interrupt Disable Mask */
#define TC_INTENCLR_ERR(value) (TC_INTENCLR_ERR_Msk & ((value) << TC_INTENCLR_ERR_Pos))
#define TC_INTENCLR_MC0_Pos _U_(4) /**< (TC_INTENCLR) MC Interrupt Disable 0 Position */
#define TC_INTENCLR_MC0_Msk (_U_(0x1) << TC_INTENCLR_MC0_Pos) /**< (TC_INTENCLR) MC Interrupt Disable 0 Mask */
#define TC_INTENCLR_MC0(value) (TC_INTENCLR_MC0_Msk & ((value) << TC_INTENCLR_MC0_Pos))
#define TC_INTENCLR_MC1_Pos _U_(5) /**< (TC_INTENCLR) MC Interrupt Disable 1 Position */
#define TC_INTENCLR_MC1_Msk (_U_(0x1) << TC_INTENCLR_MC1_Pos) /**< (TC_INTENCLR) MC Interrupt Disable 1 Mask */
#define TC_INTENCLR_MC1(value) (TC_INTENCLR_MC1_Msk & ((value) << TC_INTENCLR_MC1_Pos))
#define TC_INTENCLR_Msk _U_(0x33) /**< (TC_INTENCLR) Register Mask */
#define TC_INTENCLR_MC_Pos _U_(4) /**< (TC_INTENCLR Position) MC Interrupt Disable x */
#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos) /**< (TC_INTENCLR Mask) MC */
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#define TC_INTENSET_RESETVALUE _U_(0x00) /**< (TC_INTENSET) Interrupt Enable Set Reset Value */
#define TC_INTENSET_OVF_Pos _U_(0) /**< (TC_INTENSET) OVF Interrupt Enable Position */
#define TC_INTENSET_OVF_Msk (_U_(0x1) << TC_INTENSET_OVF_Pos) /**< (TC_INTENSET) OVF Interrupt Enable Mask */
#define TC_INTENSET_OVF(value) (TC_INTENSET_OVF_Msk & ((value) << TC_INTENSET_OVF_Pos))
#define TC_INTENSET_ERR_Pos _U_(1) /**< (TC_INTENSET) ERR Interrupt Enable Position */
#define TC_INTENSET_ERR_Msk (_U_(0x1) << TC_INTENSET_ERR_Pos) /**< (TC_INTENSET) ERR Interrupt Enable Mask */
#define TC_INTENSET_ERR(value) (TC_INTENSET_ERR_Msk & ((value) << TC_INTENSET_ERR_Pos))
#define TC_INTENSET_MC0_Pos _U_(4) /**< (TC_INTENSET) MC Interrupt Enable 0 Position */
#define TC_INTENSET_MC0_Msk (_U_(0x1) << TC_INTENSET_MC0_Pos) /**< (TC_INTENSET) MC Interrupt Enable 0 Mask */
#define TC_INTENSET_MC0(value) (TC_INTENSET_MC0_Msk & ((value) << TC_INTENSET_MC0_Pos))
#define TC_INTENSET_MC1_Pos _U_(5) /**< (TC_INTENSET) MC Interrupt Enable 1 Position */
#define TC_INTENSET_MC1_Msk (_U_(0x1) << TC_INTENSET_MC1_Pos) /**< (TC_INTENSET) MC Interrupt Enable 1 Mask */
#define TC_INTENSET_MC1(value) (TC_INTENSET_MC1_Msk & ((value) << TC_INTENSET_MC1_Pos))
#define TC_INTENSET_Msk _U_(0x33) /**< (TC_INTENSET) Register Mask */
#define TC_INTENSET_MC_Pos _U_(4) /**< (TC_INTENSET Position) MC Interrupt Enable x */
#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos) /**< (TC_INTENSET Mask) MC */
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< (TC_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define TC_INTFLAG_OVF_Pos _U_(0) /**< (TC_INTFLAG) OVF Interrupt Flag Position */
#define TC_INTFLAG_OVF_Msk (_U_(0x1) << TC_INTFLAG_OVF_Pos) /**< (TC_INTFLAG) OVF Interrupt Flag Mask */
#define TC_INTFLAG_OVF(value) (TC_INTFLAG_OVF_Msk & ((value) << TC_INTFLAG_OVF_Pos))
#define TC_INTFLAG_ERR_Pos _U_(1) /**< (TC_INTFLAG) ERR Interrupt Flag Position */
#define TC_INTFLAG_ERR_Msk (_U_(0x1) << TC_INTFLAG_ERR_Pos) /**< (TC_INTFLAG) ERR Interrupt Flag Mask */
#define TC_INTFLAG_ERR(value) (TC_INTFLAG_ERR_Msk & ((value) << TC_INTFLAG_ERR_Pos))
#define TC_INTFLAG_MC0_Pos _U_(4) /**< (TC_INTFLAG) MC Interrupt Flag 0 Position */
#define TC_INTFLAG_MC0_Msk (_U_(0x1) << TC_INTFLAG_MC0_Pos) /**< (TC_INTFLAG) MC Interrupt Flag 0 Mask */
#define TC_INTFLAG_MC0(value) (TC_INTFLAG_MC0_Msk & ((value) << TC_INTFLAG_MC0_Pos))
#define TC_INTFLAG_MC1_Pos _U_(5) /**< (TC_INTFLAG) MC Interrupt Flag 1 Position */
#define TC_INTFLAG_MC1_Msk (_U_(0x1) << TC_INTFLAG_MC1_Pos) /**< (TC_INTFLAG) MC Interrupt Flag 1 Mask */
#define TC_INTFLAG_MC1(value) (TC_INTFLAG_MC1_Msk & ((value) << TC_INTFLAG_MC1_Pos))
#define TC_INTFLAG_Msk _U_(0x33) /**< (TC_INTFLAG) Register Mask */
#define TC_INTFLAG_MC_Pos _U_(4) /**< (TC_INTFLAG Position) MC Interrupt Flag x */
#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos) /**< (TC_INTFLAG Mask) MC */
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
#define TC_STATUS_RESETVALUE _U_(0x01) /**< (TC_STATUS) Status Reset Value */
#define TC_STATUS_STOP_Pos _U_(0) /**< (TC_STATUS) Stop Status Flag Position */
#define TC_STATUS_STOP_Msk (_U_(0x1) << TC_STATUS_STOP_Pos) /**< (TC_STATUS) Stop Status Flag Mask */
#define TC_STATUS_STOP(value) (TC_STATUS_STOP_Msk & ((value) << TC_STATUS_STOP_Pos))
#define TC_STATUS_SLAVE_Pos _U_(1) /**< (TC_STATUS) Slave Status Flag Position */
#define TC_STATUS_SLAVE_Msk (_U_(0x1) << TC_STATUS_SLAVE_Pos) /**< (TC_STATUS) Slave Status Flag Mask */
#define TC_STATUS_SLAVE(value) (TC_STATUS_SLAVE_Msk & ((value) << TC_STATUS_SLAVE_Pos))
#define TC_STATUS_PERBUFV_Pos _U_(3) /**< (TC_STATUS) Synchronization Busy Status Position */
#define TC_STATUS_PERBUFV_Msk (_U_(0x1) << TC_STATUS_PERBUFV_Pos) /**< (TC_STATUS) Synchronization Busy Status Mask */
#define TC_STATUS_PERBUFV(value) (TC_STATUS_PERBUFV_Msk & ((value) << TC_STATUS_PERBUFV_Pos))
#define TC_STATUS_CCBUFV0_Pos _U_(4) /**< (TC_STATUS) Compare channel buffer 0 valid Position */
#define TC_STATUS_CCBUFV0_Msk (_U_(0x1) << TC_STATUS_CCBUFV0_Pos) /**< (TC_STATUS) Compare channel buffer 0 valid Mask */
#define TC_STATUS_CCBUFV0(value) (TC_STATUS_CCBUFV0_Msk & ((value) << TC_STATUS_CCBUFV0_Pos))
#define TC_STATUS_CCBUFV1_Pos _U_(5) /**< (TC_STATUS) Compare channel buffer 1 valid Position */
#define TC_STATUS_CCBUFV1_Msk (_U_(0x1) << TC_STATUS_CCBUFV1_Pos) /**< (TC_STATUS) Compare channel buffer 1 valid Mask */
#define TC_STATUS_CCBUFV1(value) (TC_STATUS_CCBUFV1_Msk & ((value) << TC_STATUS_CCBUFV1_Pos))
#define TC_STATUS_Msk _U_(0x3B) /**< (TC_STATUS) Register Mask */
#define TC_STATUS_CCBUFV_Pos _U_(4) /**< (TC_STATUS Position) Compare channel buffer x valid */
#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos) /**< (TC_STATUS Mask) CCBUFV */
#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
#define TC_WAVE_RESETVALUE _U_(0x00) /**< (TC_WAVE) Waveform Generation Control Reset Value */
#define TC_WAVE_WAVEGEN_Pos _U_(0) /**< (TC_WAVE) Waveform Generation Mode Position */
#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos) /**< (TC_WAVE) Waveform Generation Mode Mask */
#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< (TC_WAVE) Normal frequency */
#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< (TC_WAVE) Match frequency */
#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< (TC_WAVE) Normal PWM */
#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< (TC_WAVE) Match PWM */
#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) /**< (TC_WAVE) Normal frequency Position */
#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) /**< (TC_WAVE) Match frequency Position */
#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) /**< (TC_WAVE) Normal PWM Position */
#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) /**< (TC_WAVE) Match PWM Position */
#define TC_WAVE_Msk _U_(0x03) /**< (TC_WAVE) Register Mask */
/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< (TC_DRVCTRL) Control C Reset Value */
#define TC_DRVCTRL_INVEN0_Pos _U_(0) /**< (TC_DRVCTRL) Output Waveform Invert Enable 0 Position */
#define TC_DRVCTRL_INVEN0_Msk (_U_(0x1) << TC_DRVCTRL_INVEN0_Pos) /**< (TC_DRVCTRL) Output Waveform Invert Enable 0 Mask */
#define TC_DRVCTRL_INVEN0(value) (TC_DRVCTRL_INVEN0_Msk & ((value) << TC_DRVCTRL_INVEN0_Pos))
#define TC_DRVCTRL_INVEN1_Pos _U_(1) /**< (TC_DRVCTRL) Output Waveform Invert Enable 1 Position */
#define TC_DRVCTRL_INVEN1_Msk (_U_(0x1) << TC_DRVCTRL_INVEN1_Pos) /**< (TC_DRVCTRL) Output Waveform Invert Enable 1 Mask */
#define TC_DRVCTRL_INVEN1(value) (TC_DRVCTRL_INVEN1_Msk & ((value) << TC_DRVCTRL_INVEN1_Pos))
#define TC_DRVCTRL_Msk _U_(0x03) /**< (TC_DRVCTRL) Register Mask */
#define TC_DRVCTRL_INVEN_Pos _U_(0) /**< (TC_DRVCTRL Position) Output Waveform Invert Enable x */
#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos) /**< (TC_DRVCTRL Mask) INVEN */
#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< (TC_DBGCTRL) Debug Control Reset Value */
#define TC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (TC_DBGCTRL) Run During Debug Position */
#define TC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos) /**< (TC_DBGCTRL) Run During Debug Mask */
#define TC_DBGCTRL_DBGRUN(value) (TC_DBGCTRL_DBGRUN_Msk & ((value) << TC_DBGCTRL_DBGRUN_Pos))
#define TC_DBGCTRL_Msk _U_(0x01) /**< (TC_DBGCTRL) Register Mask */
/* -------- TC_SYNCBUSY : (TC Offset: 0x10) ( R/ 32) Synchronization Status -------- */
#define TC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (TC_SYNCBUSY) Synchronization Status Reset Value */
#define TC_SYNCBUSY_SWRST_Pos _U_(0) /**< (TC_SYNCBUSY) swrst Position */
#define TC_SYNCBUSY_SWRST_Msk (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos) /**< (TC_SYNCBUSY) swrst Mask */
#define TC_SYNCBUSY_SWRST(value) (TC_SYNCBUSY_SWRST_Msk & ((value) << TC_SYNCBUSY_SWRST_Pos))
#define TC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (TC_SYNCBUSY) enable Position */
#define TC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos) /**< (TC_SYNCBUSY) enable Mask */
#define TC_SYNCBUSY_ENABLE(value) (TC_SYNCBUSY_ENABLE_Msk & ((value) << TC_SYNCBUSY_ENABLE_Pos))
#define TC_SYNCBUSY_CTRLB_Pos _U_(2) /**< (TC_SYNCBUSY) CTRLB Position */
#define TC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos) /**< (TC_SYNCBUSY) CTRLB Mask */
#define TC_SYNCBUSY_CTRLB(value) (TC_SYNCBUSY_CTRLB_Msk & ((value) << TC_SYNCBUSY_CTRLB_Pos))
#define TC_SYNCBUSY_STATUS_Pos _U_(3) /**< (TC_SYNCBUSY) STATUS Position */
#define TC_SYNCBUSY_STATUS_Msk (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos) /**< (TC_SYNCBUSY) STATUS Mask */
#define TC_SYNCBUSY_STATUS(value) (TC_SYNCBUSY_STATUS_Msk & ((value) << TC_SYNCBUSY_STATUS_Pos))
#define TC_SYNCBUSY_COUNT_Pos _U_(4) /**< (TC_SYNCBUSY) Counter Position */
#define TC_SYNCBUSY_COUNT_Msk (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos) /**< (TC_SYNCBUSY) Counter Mask */
#define TC_SYNCBUSY_COUNT(value) (TC_SYNCBUSY_COUNT_Msk & ((value) << TC_SYNCBUSY_COUNT_Pos))
#define TC_SYNCBUSY_PER_Pos _U_(5) /**< (TC_SYNCBUSY) Period Position */
#define TC_SYNCBUSY_PER_Msk (_U_(0x1) << TC_SYNCBUSY_PER_Pos) /**< (TC_SYNCBUSY) Period Mask */
#define TC_SYNCBUSY_PER(value) (TC_SYNCBUSY_PER_Msk & ((value) << TC_SYNCBUSY_PER_Pos))
#define TC_SYNCBUSY_CC0_Pos _U_(6) /**< (TC_SYNCBUSY) Compare Channel 0 Position */
#define TC_SYNCBUSY_CC0_Msk (_U_(0x1) << TC_SYNCBUSY_CC0_Pos) /**< (TC_SYNCBUSY) Compare Channel 0 Mask */
#define TC_SYNCBUSY_CC0(value) (TC_SYNCBUSY_CC0_Msk & ((value) << TC_SYNCBUSY_CC0_Pos))
#define TC_SYNCBUSY_CC1_Pos _U_(7) /**< (TC_SYNCBUSY) Compare Channel 1 Position */
#define TC_SYNCBUSY_CC1_Msk (_U_(0x1) << TC_SYNCBUSY_CC1_Pos) /**< (TC_SYNCBUSY) Compare Channel 1 Mask */
#define TC_SYNCBUSY_CC1(value) (TC_SYNCBUSY_CC1_Msk & ((value) << TC_SYNCBUSY_CC1_Pos))
#define TC_SYNCBUSY_Msk _U_(0x000000FF) /**< (TC_SYNCBUSY) Register Mask */
#define TC_SYNCBUSY_CC_Pos _U_(6) /**< (TC_SYNCBUSY Position) Compare Channel x */
#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos) /**< (TC_SYNCBUSY Mask) CC */
#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 Count -------- */
#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT8_COUNT) COUNT8 Count Reset Value */
#define TC_COUNT8_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT8_COUNT) Counter Value Position */
#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) /**< (TC_COUNT8_COUNT) Counter Value Mask */
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
#define TC_COUNT8_COUNT_Msk _U_(0xFF) /**< (TC_COUNT8_COUNT) Register Mask */
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 Count -------- */
#define TC_COUNT16_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT16_COUNT) COUNT16 Count Reset Value */
#define TC_COUNT16_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT16_COUNT) Counter Value Position */
#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) /**< (TC_COUNT16_COUNT) Counter Value Mask */
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
#define TC_COUNT16_COUNT_Msk _U_(0xFFFF) /**< (TC_COUNT16_COUNT) Register Mask */
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 Count -------- */
#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00) /**< (TC_COUNT32_COUNT) COUNT32 Count Reset Value */
#define TC_COUNT32_COUNT_COUNT_Pos _U_(0) /**< (TC_COUNT32_COUNT) Counter Value Position */
#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) /**< (TC_COUNT32_COUNT) Counter Value Mask */
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
#define TC_COUNT32_COUNT_Msk _U_(0xFFFFFFFF) /**< (TC_COUNT32_COUNT) Register Mask */
/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 Period -------- */
#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< (TC_COUNT8_PER) COUNT8 Period Reset Value */
#define TC_COUNT8_PER_PER_Pos _U_(0) /**< (TC_COUNT8_PER) Period Value Position */
#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos) /**< (TC_COUNT8_PER) Period Value Mask */
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
#define TC_COUNT8_PER_Msk _U_(0xFF) /**< (TC_COUNT8_PER) Register Mask */
/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 Compare and Capture -------- */
#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT8_CC) COUNT8 Compare and Capture Reset Value */
#define TC_COUNT8_CC_CC_Pos _U_(0) /**< (TC_COUNT8_CC) Counter/Compare Value Position */
#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos) /**< (TC_COUNT8_CC) Counter/Compare Value Mask */
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
#define TC_COUNT8_CC_Msk _U_(0xFF) /**< (TC_COUNT8_CC) Register Mask */
/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 Compare and Capture -------- */
#define TC_COUNT16_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT16_CC) COUNT16 Compare and Capture Reset Value */
#define TC_COUNT16_CC_CC_Pos _U_(0) /**< (TC_COUNT16_CC) Counter/Compare Value Position */
#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos) /**< (TC_COUNT16_CC) Counter/Compare Value Mask */
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
#define TC_COUNT16_CC_Msk _U_(0xFFFF) /**< (TC_COUNT16_CC) Register Mask */
/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 Compare and Capture -------- */
#define TC_COUNT32_CC_RESETVALUE _U_(0x00) /**< (TC_COUNT32_CC) COUNT32 Compare and Capture Reset Value */
#define TC_COUNT32_CC_CC_Pos _U_(0) /**< (TC_COUNT32_CC) Counter/Compare Value Position */
#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) /**< (TC_COUNT32_CC) Counter/Compare Value Mask */
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
#define TC_COUNT32_CC_Msk _U_(0xFFFFFFFF) /**< (TC_COUNT32_CC) Register Mask */
/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 Period Buffer -------- */
#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< (TC_COUNT8_PERBUF) COUNT8 Period Buffer Reset Value */
#define TC_COUNT8_PERBUF_PERBUF_Pos _U_(0) /**< (TC_COUNT8_PERBUF) Period Buffer Value Position */
#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos) /**< (TC_COUNT8_PERBUF) Period Buffer Value Mask */
#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
#define TC_COUNT8_PERBUF_Msk _U_(0xFF) /**< (TC_COUNT8_PERBUF) Register Mask */
/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 Compare and Capture Buffer -------- */
#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< (TC_COUNT8_CCBUF) COUNT8 Compare and Capture Buffer Reset Value */
#define TC_COUNT8_CCBUF_CCBUF_Pos _U_(0) /**< (TC_COUNT8_CCBUF) Counter/Compare Buffer Value Position */
#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos) /**< (TC_COUNT8_CCBUF) Counter/Compare Buffer Value Mask */
#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
#define TC_COUNT8_CCBUF_Msk _U_(0xFF) /**< (TC_COUNT8_CCBUF) Register Mask */
/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 Compare and Capture Buffer -------- */
#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x00) /**< (TC_COUNT16_CCBUF) COUNT16 Compare and Capture Buffer Reset Value */
#define TC_COUNT16_CCBUF_CCBUF_Pos _U_(0) /**< (TC_COUNT16_CCBUF) Counter/Compare Buffer Value Position */
#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos) /**< (TC_COUNT16_CCBUF) Counter/Compare Buffer Value Mask */
#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
#define TC_COUNT16_CCBUF_Msk _U_(0xFFFF) /**< (TC_COUNT16_CCBUF) Register Mask */
/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 Compare and Capture Buffer -------- */
#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00) /**< (TC_COUNT32_CCBUF) COUNT32 Compare and Capture Buffer Reset Value */
#define TC_COUNT32_CCBUF_CCBUF_Pos _U_(0) /**< (TC_COUNT32_CCBUF) Counter/Compare Buffer Value Position */
#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos) /**< (TC_COUNT32_CCBUF) Counter/Compare Buffer Value Mask */
#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
#define TC_COUNT32_CCBUF_Msk _U_(0xFFFFFFFF) /**< (TC_COUNT32_CCBUF) Register Mask */
/** \brief TC register offsets definitions */
#define TC_CTRLA_REG_OFST (0x00) /**< (TC_CTRLA) Control A Offset */
#define TC_CTRLBCLR_REG_OFST (0x04) /**< (TC_CTRLBCLR) Control B Clear Offset */
#define TC_CTRLBSET_REG_OFST (0x05) /**< (TC_CTRLBSET) Control B Set Offset */
#define TC_EVCTRL_REG_OFST (0x06) /**< (TC_EVCTRL) Event Control Offset */
#define TC_INTENCLR_REG_OFST (0x08) /**< (TC_INTENCLR) Interrupt Enable Clear Offset */
#define TC_INTENSET_REG_OFST (0x09) /**< (TC_INTENSET) Interrupt Enable Set Offset */
#define TC_INTFLAG_REG_OFST (0x0A) /**< (TC_INTFLAG) Interrupt Flag Status and Clear Offset */
#define TC_STATUS_REG_OFST (0x0B) /**< (TC_STATUS) Status Offset */
#define TC_WAVE_REG_OFST (0x0C) /**< (TC_WAVE) Waveform Generation Control Offset */
#define TC_DRVCTRL_REG_OFST (0x0D) /**< (TC_DRVCTRL) Control C Offset */
#define TC_DBGCTRL_REG_OFST (0x0F) /**< (TC_DBGCTRL) Debug Control Offset */
#define TC_SYNCBUSY_REG_OFST (0x10) /**< (TC_SYNCBUSY) Synchronization Status Offset */
#define TC_COUNT8_COUNT_REG_OFST (0x14) /**< (TC_COUNT8_COUNT) COUNT8 Count Offset */
#define TC_COUNT16_COUNT_REG_OFST (0x14) /**< (TC_COUNT16_COUNT) COUNT16 Count Offset */
#define TC_COUNT32_COUNT_REG_OFST (0x14) /**< (TC_COUNT32_COUNT) COUNT32 Count Offset */
#define TC_COUNT8_PER_REG_OFST (0x1B) /**< (TC_COUNT8_PER) COUNT8 Period Offset */
#define TC_COUNT8_CC_REG_OFST (0x1C) /**< (TC_COUNT8_CC) COUNT8 Compare and Capture Offset */
#define TC_COUNT16_CC_REG_OFST (0x1C) /**< (TC_COUNT16_CC) COUNT16 Compare and Capture Offset */
#define TC_COUNT32_CC_REG_OFST (0x1C) /**< (TC_COUNT32_CC) COUNT32 Compare and Capture Offset */
#define TC_COUNT8_PERBUF_REG_OFST (0x2F) /**< (TC_COUNT8_PERBUF) COUNT8 Period Buffer Offset */
#define TC_COUNT8_CCBUF_REG_OFST (0x30) /**< (TC_COUNT8_CCBUF) COUNT8 Compare and Capture Buffer Offset */
#define TC_COUNT16_CCBUF_REG_OFST (0x30) /**< (TC_COUNT16_CCBUF) COUNT16 Compare and Capture Buffer Offset */
#define TC_COUNT32_CCBUF_REG_OFST (0x30) /**< (TC_COUNT32_CCBUF) COUNT32 Compare and Capture Buffer Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief TC register API structure */
typedef struct
{ /* Basic Timer Counter */
__IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
__IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */
__IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */
__IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */
__I uint8_t Reserved1[0x01];
__IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
__I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */
__IO uint8_t TC_COUNT; /**< Offset: 0x14 (R/W 8) COUNT8 Count */
__I uint8_t Reserved2[0x06];
__IO uint8_t TC_PER; /**< Offset: 0x1B (R/W 8) COUNT8 Period */
__IO uint8_t TC_CC[2]; /**< Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
__I uint8_t Reserved3[0x11];
__IO uint8_t TC_PERBUF; /**< Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
__IO uint8_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
} tc_count8_registers_t;
/** \brief TC register API structure */
typedef struct
{ /* Basic Timer Counter */
__IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
__IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */
__IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */
__IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */
__I uint8_t Reserved1[0x01];
__IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
__I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */
__IO uint16_t TC_COUNT; /**< Offset: 0x14 (R/W 16) COUNT16 Count */
__I uint8_t Reserved2[0x06];
__IO uint16_t TC_CC[2]; /**< Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
__I uint8_t Reserved3[0x10];
__IO uint16_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
} tc_count16_registers_t;
/** \brief TC register API structure */
typedef struct
{ /* Basic Timer Counter */
__IO uint32_t TC_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t TC_CTRLBCLR; /**< Offset: 0x04 (R/W 8) Control B Clear */
__IO uint8_t TC_CTRLBSET; /**< Offset: 0x05 (R/W 8) Control B Set */
__IO uint16_t TC_EVCTRL; /**< Offset: 0x06 (R/W 16) Event Control */
__IO uint8_t TC_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO uint8_t TC_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO uint8_t TC_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO uint8_t TC_STATUS; /**< Offset: 0x0B (R/W 8) Status */
__IO uint8_t TC_WAVE; /**< Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO uint8_t TC_DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */
__I uint8_t Reserved1[0x01];
__IO uint8_t TC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
__I uint32_t TC_SYNCBUSY; /**< Offset: 0x10 (R/ 32) Synchronization Status */
__IO uint32_t TC_COUNT; /**< Offset: 0x14 (R/W 32) COUNT32 Count */
__I uint8_t Reserved2[0x04];
__IO uint32_t TC_CC[2]; /**< Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
__I uint8_t Reserved3[0x0C];
__IO uint32_t TC_CCBUF[2]; /**< Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
} tc_count32_registers_t;
/** \brief TC hardware registers */
typedef union
{ /* Basic Timer Counter */
tc_count8_registers_t COUNT8; /**< 8-bit Counter Mode */
tc_count16_registers_t COUNT16; /**< 16-bit Counter Mode */
tc_count32_registers_t COUNT32; /**< 32-bit Counter Mode */
} tc_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_TC_COMPONENT_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/component/tcc.h
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arch/arm/SAMD51/SAMD51A/mcu/inc/component/trng.h
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/**
* \brief Component description for TRNG
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_TRNG_COMPONENT_H_
#define _SAMD51_TRNG_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR TRNG */
/* ************************************************************************** */
/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< (TRNG_CTRLA) Control A Reset Value */
#define TRNG_CTRLA_ENABLE_Pos _U_(1) /**< (TRNG_CTRLA) Enable Position */
#define TRNG_CTRLA_ENABLE_Msk (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos) /**< (TRNG_CTRLA) Enable Mask */
#define TRNG_CTRLA_ENABLE(value) (TRNG_CTRLA_ENABLE_Msk & ((value) << TRNG_CTRLA_ENABLE_Pos))
#define TRNG_CTRLA_RUNSTDBY_Pos _U_(6) /**< (TRNG_CTRLA) Run in Standby Position */
#define TRNG_CTRLA_RUNSTDBY_Msk (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos) /**< (TRNG_CTRLA) Run in Standby Mask */
#define TRNG_CTRLA_RUNSTDBY(value) (TRNG_CTRLA_RUNSTDBY_Msk & ((value) << TRNG_CTRLA_RUNSTDBY_Pos))
#define TRNG_CTRLA_Msk _U_(0x42) /**< (TRNG_CTRLA) Register Mask */
/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< (TRNG_EVCTRL) Event Control Reset Value */
#define TRNG_EVCTRL_DATARDYEO_Pos _U_(0) /**< (TRNG_EVCTRL) Data Ready Event Output Position */
#define TRNG_EVCTRL_DATARDYEO_Msk (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos) /**< (TRNG_EVCTRL) Data Ready Event Output Mask */
#define TRNG_EVCTRL_DATARDYEO(value) (TRNG_EVCTRL_DATARDYEO_Msk & ((value) << TRNG_EVCTRL_DATARDYEO_Pos))
#define TRNG_EVCTRL_Msk _U_(0x01) /**< (TRNG_EVCTRL) Register Mask */
/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< (TRNG_INTENCLR) Interrupt Enable Clear Reset Value */
#define TRNG_INTENCLR_DATARDY_Pos _U_(0) /**< (TRNG_INTENCLR) Data Ready Interrupt Enable Position */
#define TRNG_INTENCLR_DATARDY_Msk (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos) /**< (TRNG_INTENCLR) Data Ready Interrupt Enable Mask */
#define TRNG_INTENCLR_DATARDY(value) (TRNG_INTENCLR_DATARDY_Msk & ((value) << TRNG_INTENCLR_DATARDY_Pos))
#define TRNG_INTENCLR_Msk _U_(0x01) /**< (TRNG_INTENCLR) Register Mask */
/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< (TRNG_INTENSET) Interrupt Enable Set Reset Value */
#define TRNG_INTENSET_DATARDY_Pos _U_(0) /**< (TRNG_INTENSET) Data Ready Interrupt Enable Position */
#define TRNG_INTENSET_DATARDY_Msk (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos) /**< (TRNG_INTENSET) Data Ready Interrupt Enable Mask */
#define TRNG_INTENSET_DATARDY(value) (TRNG_INTENSET_DATARDY_Msk & ((value) << TRNG_INTENSET_DATARDY_Pos))
#define TRNG_INTENSET_Msk _U_(0x01) /**< (TRNG_INTENSET) Register Mask */
/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< (TRNG_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define TRNG_INTFLAG_DATARDY_Pos _U_(0) /**< (TRNG_INTFLAG) Data Ready Interrupt Flag Position */
#define TRNG_INTFLAG_DATARDY_Msk (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos) /**< (TRNG_INTFLAG) Data Ready Interrupt Flag Mask */
#define TRNG_INTFLAG_DATARDY(value) (TRNG_INTFLAG_DATARDY_Msk & ((value) << TRNG_INTFLAG_DATARDY_Pos))
#define TRNG_INTFLAG_Msk _U_(0x01) /**< (TRNG_INTFLAG) Register Mask */
/* -------- TRNG_DATA : (TRNG Offset: 0x20) ( R/ 32) Output Data -------- */
#define TRNG_DATA_RESETVALUE _U_(0x00) /**< (TRNG_DATA) Output Data Reset Value */
#define TRNG_DATA_DATA_Pos _U_(0) /**< (TRNG_DATA) Output Data Position */
#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos) /**< (TRNG_DATA) Output Data Mask */
#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
#define TRNG_DATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_DATA) Register Mask */
/** \brief TRNG register offsets definitions */
#define TRNG_CTRLA_REG_OFST (0x00) /**< (TRNG_CTRLA) Control A Offset */
#define TRNG_EVCTRL_REG_OFST (0x04) /**< (TRNG_EVCTRL) Event Control Offset */
#define TRNG_INTENCLR_REG_OFST (0x08) /**< (TRNG_INTENCLR) Interrupt Enable Clear Offset */
#define TRNG_INTENSET_REG_OFST (0x09) /**< (TRNG_INTENSET) Interrupt Enable Set Offset */
#define TRNG_INTFLAG_REG_OFST (0x0A) /**< (TRNG_INTFLAG) Interrupt Flag Status and Clear Offset */
#define TRNG_DATA_REG_OFST (0x20) /**< (TRNG_DATA) Output Data Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief TRNG register API structure */
typedef struct
{ /* True Random Generator */
__IO uint8_t TRNG_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
__I uint8_t Reserved1[0x03];
__IO uint8_t TRNG_EVCTRL; /**< Offset: 0x04 (R/W 8) Event Control */
__I uint8_t Reserved2[0x03];
__IO uint8_t TRNG_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO uint8_t TRNG_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO uint8_t TRNG_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t Reserved3[0x15];
__I uint32_t TRNG_DATA; /**< Offset: 0x20 (R/ 32) Output Data */
} trng_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_TRNG_COMPONENT_H_ */

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/**
* \brief Component description for WDT
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:45:00Z */
#ifndef _SAMD51_WDT_COMPONENT_H_
#define _SAMD51_WDT_COMPONENT_H_
/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR WDT */
/* ************************************************************************** */
/* -------- WDT_CTRLA : (WDT Offset: 0x00) (R/W 8) Control -------- */
#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< (WDT_CTRLA) Control Reset Value */
#define WDT_CTRLA_ENABLE_Pos _U_(1) /**< (WDT_CTRLA) Enable Position */
#define WDT_CTRLA_ENABLE_Msk (_U_(0x1) << WDT_CTRLA_ENABLE_Pos) /**< (WDT_CTRLA) Enable Mask */
#define WDT_CTRLA_ENABLE(value) (WDT_CTRLA_ENABLE_Msk & ((value) << WDT_CTRLA_ENABLE_Pos))
#define WDT_CTRLA_WEN_Pos _U_(2) /**< (WDT_CTRLA) Watchdog Timer Window Mode Enable Position */
#define WDT_CTRLA_WEN_Msk (_U_(0x1) << WDT_CTRLA_WEN_Pos) /**< (WDT_CTRLA) Watchdog Timer Window Mode Enable Mask */
#define WDT_CTRLA_WEN(value) (WDT_CTRLA_WEN_Msk & ((value) << WDT_CTRLA_WEN_Pos))
#define WDT_CTRLA_ALWAYSON_Pos _U_(7) /**< (WDT_CTRLA) Always-On Position */
#define WDT_CTRLA_ALWAYSON_Msk (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos) /**< (WDT_CTRLA) Always-On Mask */
#define WDT_CTRLA_ALWAYSON(value) (WDT_CTRLA_ALWAYSON_Msk & ((value) << WDT_CTRLA_ALWAYSON_Pos))
#define WDT_CTRLA_Msk _U_(0x86) /**< (WDT_CTRLA) Register Mask */
/* -------- WDT_CONFIG : (WDT Offset: 0x01) (R/W 8) Configuration -------- */
#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< (WDT_CONFIG) Configuration Reset Value */
#define WDT_CONFIG_PER_Pos _U_(0) /**< (WDT_CONFIG) Time-Out Period Position */
#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) Time-Out Period Mask */
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 8 clock cycles Position */
#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 16 clock cycles Position */
#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 32 clock cycles Position */
#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 64 clock cycles Position */
#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 128 clock cycles Position */
#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 256 clock cycles Position */
#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 512 clock cycles Position */
#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 1024 clock cycles Position */
#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 2048 clock cycles Position */
#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 4096 clock cycles Position */
#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 8192 clock cycles Position */
#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos) /**< (WDT_CONFIG) 16384 clock cycles Position */
#define WDT_CONFIG_WINDOW_Pos _U_(4) /**< (WDT_CONFIG) Window Mode Time-Out Period Position */
#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) Window Mode Time-Out Period Mask */
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 8 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 16 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 32 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 64 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 128 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 256 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 512 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 1024 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 2048 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 4096 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 8192 clock cycles Position */
#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 16384 clock cycles Position */
#define WDT_CONFIG_Msk _U_(0xFF) /**< (WDT_CONFIG) Register Mask */
/* -------- WDT_EWCTRL : (WDT Offset: 0x02) (R/W 8) Early Warning Interrupt Control -------- */
#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< (WDT_EWCTRL) Early Warning Interrupt Control Reset Value */
#define WDT_EWCTRL_EWOFFSET_Pos _U_(0) /**< (WDT_EWCTRL) Early Warning Interrupt Time Offset Position */
#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) Early Warning Interrupt Time Offset Mask */
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< (WDT_EWCTRL) 8 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< (WDT_EWCTRL) 16 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< (WDT_EWCTRL) 32 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< (WDT_EWCTRL) 64 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< (WDT_EWCTRL) 128 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< (WDT_EWCTRL) 256 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< (WDT_EWCTRL) 512 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< (WDT_EWCTRL) 1024 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< (WDT_EWCTRL) 2048 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< (WDT_EWCTRL) 4096 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< (WDT_EWCTRL) 8192 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< (WDT_EWCTRL) 16384 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 8 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 16 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 32 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 64 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 128 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 256 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 512 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 1024 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 2048 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 4096 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 8192 clock cycles Position */
#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 16384 clock cycles Position */
#define WDT_EWCTRL_Msk _U_(0x0F) /**< (WDT_EWCTRL) Register Mask */
/* -------- WDT_INTENCLR : (WDT Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< (WDT_INTENCLR) Interrupt Enable Clear Reset Value */
#define WDT_INTENCLR_EW_Pos _U_(0) /**< (WDT_INTENCLR) Early Warning Interrupt Enable Position */
#define WDT_INTENCLR_EW_Msk (_U_(0x1) << WDT_INTENCLR_EW_Pos) /**< (WDT_INTENCLR) Early Warning Interrupt Enable Mask */
#define WDT_INTENCLR_EW(value) (WDT_INTENCLR_EW_Msk & ((value) << WDT_INTENCLR_EW_Pos))
#define WDT_INTENCLR_Msk _U_(0x01) /**< (WDT_INTENCLR) Register Mask */
/* -------- WDT_INTENSET : (WDT Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< (WDT_INTENSET) Interrupt Enable Set Reset Value */
#define WDT_INTENSET_EW_Pos _U_(0) /**< (WDT_INTENSET) Early Warning Interrupt Enable Position */
#define WDT_INTENSET_EW_Msk (_U_(0x1) << WDT_INTENSET_EW_Pos) /**< (WDT_INTENSET) Early Warning Interrupt Enable Mask */
#define WDT_INTENSET_EW(value) (WDT_INTENSET_EW_Msk & ((value) << WDT_INTENSET_EW_Pos))
#define WDT_INTENSET_Msk _U_(0x01) /**< (WDT_INTENSET) Register Mask */
/* -------- WDT_INTFLAG : (WDT Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< (WDT_INTFLAG) Interrupt Flag Status and Clear Reset Value */
#define WDT_INTFLAG_EW_Pos _U_(0) /**< (WDT_INTFLAG) Early Warning Position */
#define WDT_INTFLAG_EW_Msk (_U_(0x1) << WDT_INTFLAG_EW_Pos) /**< (WDT_INTFLAG) Early Warning Mask */
#define WDT_INTFLAG_EW(value) (WDT_INTFLAG_EW_Msk & ((value) << WDT_INTFLAG_EW_Pos))
#define WDT_INTFLAG_Msk _U_(0x01) /**< (WDT_INTFLAG) Register Mask */
/* -------- WDT_SYNCBUSY : (WDT Offset: 0x08) ( R/ 32) Synchronization Busy -------- */
#define WDT_SYNCBUSY_RESETVALUE _U_(0x00) /**< (WDT_SYNCBUSY) Synchronization Busy Reset Value */
#define WDT_SYNCBUSY_ENABLE_Pos _U_(1) /**< (WDT_SYNCBUSY) Enable Synchronization Busy Position */
#define WDT_SYNCBUSY_ENABLE_Msk (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos) /**< (WDT_SYNCBUSY) Enable Synchronization Busy Mask */
#define WDT_SYNCBUSY_ENABLE(value) (WDT_SYNCBUSY_ENABLE_Msk & ((value) << WDT_SYNCBUSY_ENABLE_Pos))
#define WDT_SYNCBUSY_WEN_Pos _U_(2) /**< (WDT_SYNCBUSY) Window Enable Synchronization Busy Position */
#define WDT_SYNCBUSY_WEN_Msk (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos) /**< (WDT_SYNCBUSY) Window Enable Synchronization Busy Mask */
#define WDT_SYNCBUSY_WEN(value) (WDT_SYNCBUSY_WEN_Msk & ((value) << WDT_SYNCBUSY_WEN_Pos))
#define WDT_SYNCBUSY_ALWAYSON_Pos _U_(3) /**< (WDT_SYNCBUSY) Always-On Synchronization Busy Position */
#define WDT_SYNCBUSY_ALWAYSON_Msk (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos) /**< (WDT_SYNCBUSY) Always-On Synchronization Busy Mask */
#define WDT_SYNCBUSY_ALWAYSON(value) (WDT_SYNCBUSY_ALWAYSON_Msk & ((value) << WDT_SYNCBUSY_ALWAYSON_Pos))
#define WDT_SYNCBUSY_CLEAR_Pos _U_(4) /**< (WDT_SYNCBUSY) Clear Synchronization Busy Position */
#define WDT_SYNCBUSY_CLEAR_Msk (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos) /**< (WDT_SYNCBUSY) Clear Synchronization Busy Mask */
#define WDT_SYNCBUSY_CLEAR(value) (WDT_SYNCBUSY_CLEAR_Msk & ((value) << WDT_SYNCBUSY_CLEAR_Pos))
#define WDT_SYNCBUSY_Msk _U_(0x0000001E) /**< (WDT_SYNCBUSY) Register Mask */
/* -------- WDT_CLEAR : (WDT Offset: 0x0C) ( /W 8) Clear -------- */
#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< (WDT_CLEAR) Clear Reset Value */
#define WDT_CLEAR_CLEAR_Pos _U_(0) /**< (WDT_CLEAR) Watchdog Clear Position */
#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos) /**< (WDT_CLEAR) Watchdog Clear Mask */
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< (WDT_CLEAR) Clear Key */
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) /**< (WDT_CLEAR) Clear Key Position */
#define WDT_CLEAR_Msk _U_(0xFF) /**< (WDT_CLEAR) Register Mask */
/** \brief WDT register offsets definitions */
#define WDT_CTRLA_REG_OFST (0x00) /**< (WDT_CTRLA) Control Offset */
#define WDT_CONFIG_REG_OFST (0x01) /**< (WDT_CONFIG) Configuration Offset */
#define WDT_EWCTRL_REG_OFST (0x02) /**< (WDT_EWCTRL) Early Warning Interrupt Control Offset */
#define WDT_INTENCLR_REG_OFST (0x04) /**< (WDT_INTENCLR) Interrupt Enable Clear Offset */
#define WDT_INTENSET_REG_OFST (0x05) /**< (WDT_INTENSET) Interrupt Enable Set Offset */
#define WDT_INTFLAG_REG_OFST (0x06) /**< (WDT_INTFLAG) Interrupt Flag Status and Clear Offset */
#define WDT_SYNCBUSY_REG_OFST (0x08) /**< (WDT_SYNCBUSY) Synchronization Busy Offset */
#define WDT_CLEAR_REG_OFST (0x0C) /**< (WDT_CLEAR) Clear Offset */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief WDT register API structure */
typedef struct
{ /* Watchdog Timer */
__IO uint8_t WDT_CTRLA; /**< Offset: 0x00 (R/W 8) Control */
__IO uint8_t WDT_CONFIG; /**< Offset: 0x01 (R/W 8) Configuration */
__IO uint8_t WDT_EWCTRL; /**< Offset: 0x02 (R/W 8) Early Warning Interrupt Control */
__I uint8_t Reserved1[0x01];
__IO uint8_t WDT_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO uint8_t WDT_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO uint8_t WDT_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I uint8_t Reserved2[0x01];
__I uint32_t WDT_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */
__O uint8_t WDT_CLEAR; /**< Offset: 0x0C ( /W 8) Clear */
} wdt_registers_t;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD51_WDT_COMPONENT_H_ */

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/**
* \file
*
* \brief Top level header file
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _SAM_
#define _SAM_
#if defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
#include "samd51p20a.h"
#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
#include "samd51n20a.h"
#elif defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__)
#include "samd51g18a.h"
#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__)
#include "samd51g19a.h"
#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
#include "samd51p19a.h"
#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
#include "samd51j19a.h"
#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
#include "samd51j20a.h"
#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
#include "samd51n19a.h"
#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
#include "samd51j18a.h"
#else
#error Library does not support the specified device
#endif
#endif /* _SAM_ */

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/**
* \brief Header file for ATSAMD51G18A
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:44:34Z */
#ifndef _SAMD51G18A_H_
#define _SAMD51G18A_H_
// Header version uses Semantic Versioning 2.0.0 (https://semver.org/)
#define HEADER_FORMAT_VERSION "2.0.0"
#define HEADER_FORMAT_VERSION_MAJOR (2)
#define HEADER_FORMAT_VERSION_MINOR (0)
/** \addtogroup SAMD51G18A_definitions SAMD51G18A definitions
This file defines all structures and symbols for SAMD51G18A:
- registers and bitfields
- peripheral base address
- peripheral ID
- PIO definitions
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
# include <stdint.h>
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !defined(SKIP_INTEGER_LITERALS)
# if defined(_U_) || defined(_L_) || defined(_UL_)
# error "Integer Literals macros already defined elsewhere"
# endif
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */
# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */
# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
# define _L_(x) x /**< Assembler: Long integer literal constant value */
# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/** @} end of Atmel Global Defines */
/* ************************************************************************** */
/* CMSIS DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** CORTEX-M4 Processor Exceptions Numbers ******************************/
Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */
PendSV_IRQn = -2, /**< -2 Pendable request for system service */
SysTick_IRQn = -1, /**< -1 System Tick Timer */
/****** SAMD51G18A specific Interrupt Numbers ***********************************/
PM_IRQn = 0, /**< 0 Power Manager (PM) */
MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */
OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */
OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */
OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */
OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */
OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */
OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */
SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */
SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */
WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */
RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */
EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */
EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */
EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */
EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */
EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */
EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */
EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */
EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */
EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */
EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */
EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */
EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */
EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */
EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */
EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */
EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */
FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */
NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */
NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */
DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */
DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */
DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */
DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */
DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */
EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */
EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */
EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */
EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */
EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */
PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */
RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */
SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */
SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */
SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */
SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */
SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */
SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */
SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */
SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */
SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */
SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */
SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */
SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */
SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */
SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */
SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */
SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */
SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */
SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */
SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */
SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */
SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */
SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */
SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */
SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */
USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */
USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */
USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */
USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */
TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */
TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */
TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */
TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */
TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */
TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */
TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */
TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */
TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */
TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */
TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */
TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */
TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */
TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */
TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */
TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */
TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */
TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */
TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */
TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */
PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */
PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */
PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */
ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */
ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */
ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */
ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */
AC_IRQn = 122, /**< 122 Analog Comparators (AC) */
DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */
DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */
DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */
DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */
DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */
PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */
AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */
TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */
ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */
PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */
QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */
SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */
PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */
} IRQn_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* CORTEX-M4 handlers */
void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */
void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */
void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */
void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */
void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
void* pvReservedC9;
void* pvReservedC8;
void* pvReservedC7;
void* pvReservedC6;
void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */
void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */
void* pvReservedC3;
void* pfnPendSV_Handler; /* -2 Pendable request for system service */
void* pfnSysTick_Handler; /* -1 System Tick Timer */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager (PM) */
void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */
void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */
void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */
void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */
void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */
void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */
void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */
void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */
void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */
void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */
void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */
void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */
void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */
void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */
void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */
void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */
void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */
void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */
void* pvReserved42;
void* pvReserved43;
void* pvReserved44;
void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */
void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */
void* pvReserved70;
void* pvReserved71;
void* pvReserved72;
void* pvReserved73;
void* pvReserved74;
void* pvReserved75;
void* pvReserved76;
void* pvReserved77;
void* pvReserved78;
void* pvReserved79;
void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */
void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */
void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */
void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */
void* pvReserved84;
void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */
void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */
void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */
void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */
void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */
void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */
void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */
void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */
void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */
void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */
void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */
void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */
void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */
void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */
void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */
void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */
void* pvReserved101;
void* pvReserved102;
void* pvReserved103;
void* pvReserved104;
void* pvReserved105;
void* pvReserved106;
void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */
void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */
void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */
void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */
void* pvReserved111;
void* pvReserved112;
void* pvReserved113;
void* pvReserved114;
void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */
void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */
void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */
void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */
void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */
void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */
void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */
void* pfnAC_Handler; /* 122 Analog Comparators (AC) */
void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */
void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */
void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */
void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */
void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */
void* pvReserved128;
void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */
void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */
void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */
void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */
void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */
void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */
void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */
} DeviceVectors;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
/* CORTEX-M4 exception handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void MemoryManagement_Handler ( void );
void BusFault_Handler ( void );
void UsageFault_Handler ( void );
void SVCall_Handler ( void );
void DebugMonitor_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
/* Peripherals interrupt handlers */
void PM_Handler ( void );
void MCLK_Handler ( void );
void OSCCTRL_XOSC0_Handler ( void );
void OSCCTRL_XOSC1_Handler ( void );
void OSCCTRL_DFLL_Handler ( void );
void OSCCTRL_DPLL0_Handler ( void );
void OSCCTRL_DPLL1_Handler ( void );
void OSC32KCTRL_Handler ( void );
void SUPC_OTHER_Handler ( void );
void SUPC_BODDET_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_EXTINT_0_Handler ( void );
void EIC_EXTINT_1_Handler ( void );
void EIC_EXTINT_2_Handler ( void );
void EIC_EXTINT_3_Handler ( void );
void EIC_EXTINT_4_Handler ( void );
void EIC_EXTINT_5_Handler ( void );
void EIC_EXTINT_6_Handler ( void );
void EIC_EXTINT_7_Handler ( void );
void EIC_EXTINT_8_Handler ( void );
void EIC_EXTINT_9_Handler ( void );
void EIC_EXTINT_10_Handler ( void );
void EIC_EXTINT_11_Handler ( void );
void EIC_EXTINT_12_Handler ( void );
void EIC_EXTINT_13_Handler ( void );
void EIC_EXTINT_14_Handler ( void );
void EIC_EXTINT_15_Handler ( void );
void FREQM_Handler ( void );
void NVMCTRL_0_Handler ( void );
void NVMCTRL_1_Handler ( void );
void DMAC_0_Handler ( void );
void DMAC_1_Handler ( void );
void DMAC_2_Handler ( void );
void DMAC_3_Handler ( void );
void DMAC_OTHER_Handler ( void );
void EVSYS_0_Handler ( void );
void EVSYS_1_Handler ( void );
void EVSYS_2_Handler ( void );
void EVSYS_3_Handler ( void );
void EVSYS_OTHER_Handler ( void );
void PAC_Handler ( void );
void RAMECC_Handler ( void );
void SERCOM0_0_Handler ( void );
void SERCOM0_1_Handler ( void );
void SERCOM0_2_Handler ( void );
void SERCOM0_OTHER_Handler ( void );
void SERCOM1_0_Handler ( void );
void SERCOM1_1_Handler ( void );
void SERCOM1_2_Handler ( void );
void SERCOM1_OTHER_Handler ( void );
void SERCOM2_0_Handler ( void );
void SERCOM2_1_Handler ( void );
void SERCOM2_2_Handler ( void );
void SERCOM2_OTHER_Handler ( void );
void SERCOM3_0_Handler ( void );
void SERCOM3_1_Handler ( void );
void SERCOM3_2_Handler ( void );
void SERCOM3_OTHER_Handler ( void );
void SERCOM4_0_Handler ( void );
void SERCOM4_1_Handler ( void );
void SERCOM4_2_Handler ( void );
void SERCOM4_OTHER_Handler ( void );
void SERCOM5_0_Handler ( void );
void SERCOM5_1_Handler ( void );
void SERCOM5_2_Handler ( void );
void SERCOM5_OTHER_Handler ( void );
void USB_OTHER_Handler ( void );
void USB_SOF_HSOF_Handler ( void );
void USB_TRCPT0_Handler ( void );
void USB_TRCPT1_Handler ( void );
void TCC0_OTHER_Handler ( void );
void TCC0_MC0_Handler ( void );
void TCC0_MC1_Handler ( void );
void TCC0_MC2_Handler ( void );
void TCC0_MC3_Handler ( void );
void TCC0_MC4_Handler ( void );
void TCC0_MC5_Handler ( void );
void TCC1_OTHER_Handler ( void );
void TCC1_MC0_Handler ( void );
void TCC1_MC1_Handler ( void );
void TCC1_MC2_Handler ( void );
void TCC1_MC3_Handler ( void );
void TCC2_OTHER_Handler ( void );
void TCC2_MC0_Handler ( void );
void TCC2_MC1_Handler ( void );
void TCC2_MC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void PDEC_OTHER_Handler ( void );
void PDEC_MC0_Handler ( void );
void PDEC_MC1_Handler ( void );
void ADC0_OTHER_Handler ( void );
void ADC0_RESRDY_Handler ( void );
void ADC1_OTHER_Handler ( void );
void ADC1_RESRDY_Handler ( void );
void AC_Handler ( void );
void DAC_OTHER_Handler ( void );
void DAC_EMPTY_0_Handler ( void );
void DAC_EMPTY_1_Handler ( void );
void DAC_RESRDY_0_Handler ( void );
void DAC_RESRDY_1_Handler ( void );
void PCC_Handler ( void );
void AES_Handler ( void );
void TRNG_Handler ( void );
void ICM_Handler ( void );
void PUKCC_Handler ( void );
void QSPI_Handler ( void );
void SDHC0_Handler ( void );
#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */
#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */
#define __DEBUG_LVL 3 /**< Debug Level */
#define __FPU_PRESENT 1 /**< FPU present or not */
#define __MPU_PRESENT 1 /**< MPU present or not */
#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
#define __TRACE_LVL 2 /**< Trace Level */
#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
#define __ARCH_ARM 1
#define __ARCH_ARM_CORTEX_M 1
/*
* \brief CMSIS includes
*/
#include "core_cm4.h"
#if defined USE_CMSIS_INIT
#include "system_samd51.h"
#endif /* USE_CMSIS_INIT */
/** \defgroup SAMD51G18A_api Peripheral Software API
* @{
*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */
/* ************************************************************************** */
#include "component/ac.h"
#include "component/adc.h"
#include "component/aes.h"
#include "component/ccl.h"
#include "component/cmcc.h"
#include "component/dac.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/icm.h"
#include "component/mclk.h"
#include "component/nvmctrl.h"
#include "component/osc32kctrl.h"
#include "component/oscctrl.h"
#include "component/pac.h"
#include "component/pcc.h"
#include "component/pdec.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/pukcc.h"
#include "component/qspi.h"
#include "component/ramecc.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdhc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/trng.h"
#include "component/usb.h"
#include "component/wdt.h"
/** @} end of Peripheral Software API */
/** \addtogroup SAMD51G18A_id Peripheral Ids Definitions
* @{
*/
/* ************************************************************************** */
/* PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM ( 1) /**< \brief Power Manager (PM) */
#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */
#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */
#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */
#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */
#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */
#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */
#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */
#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */
#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */
#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */
#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */
#define ID_PORT ( 36) /**< \brief Port Module (PORT) */
#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */
#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */
#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */
#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */
#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */
#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */
#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */
#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */
#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */
#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */
#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */
#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */
#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */
#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */
#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */
#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */
#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */
#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */
#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */
#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */
#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */
#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */
#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */
/** @} end of Peripheral Ids Definitions */
/** \addtogroup SAMD51G18A_base Peripheral Base Address Definitions
* @{
*/
/* ************************************************************************** */
/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */
#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */
#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */
#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */
#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */
#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */
#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */
#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */
#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */
#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */
#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */
#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */
#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */
#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */
#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */
#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */
#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */
#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */
#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */
#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */
#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */
#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */
#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */
#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */
#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */
#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */
#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */
#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */
#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */
#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */
#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */
#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */
#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */
#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */
#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */
#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */
#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */
#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */
#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */
#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */
#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */
#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */
#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */
#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */
#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */
#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Peripheral Base Address Definitions */
/** \addtogroup SAMD51G18A_base Peripheral Base Address Definitions
* @{
*/
/* ************************************************************************** */
/* BASE ADDRESS DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */
#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */
#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */
#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */
#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */
#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */
#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */
#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */
#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */
#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */
#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */
#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */
#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */
#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */
#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */
#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */
#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */
#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */
#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */
#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */
#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */
#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */
#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */
#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */
#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */
#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */
#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */
#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */
#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */
#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */
#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */
#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */
#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */
#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */
#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */
#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */
#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */
#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */
#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */
#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */
#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */
#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */
#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */
#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */
#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */
#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */
/** @} end of Peripheral Base Address Definitions */
/** \addtogroup SAMD51G18A_pio Peripheral Pio Definitions
* @{
*/
/* ************************************************************************** */
/* PIO DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#include "pio/samd51g18a.h"
/** @} end of Peripheral Pio Definitions */
/* ************************************************************************** */
/* MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00040000) /* 256kB Memory segment type: flash */
#define FLASH_PAGE_SIZE _UL_( 512)
#define FLASH_NB_OF_PAGES _UL_( 512)
#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */
#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */
#define TEMP_LOG_PAGE_SIZE _UL_( 512)
#define TEMP_LOG_NB_OF_PAGES _UL_( 1)
#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */
#define USER_PAGE_PAGE_SIZE _UL_( 512)
#define USER_PAGE_NB_OF_PAGES _UL_( 1)
#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */
#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */
#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */
#define HSRAM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: ram */
#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */
#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */
#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */
#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */
#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */
#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */
#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */
#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */
#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/
#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/
#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/
#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/
#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/
#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/
#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/
#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/
#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/
#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/
#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/
#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/
#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/
#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/
#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/
#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/
/* ************************************************************************** */
/** DEVICE SIGNATURES FOR SAMD51G18A */
/* ************************************************************************** */
#define CHIP_DSU_DID _UL_(0X60060308)
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */
/* ************************************************************************** */
/* ************************************************************************** */
/** Event Generator IDs for SAMD51G18A */
/* ************************************************************************** */
#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */
#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */
#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */
#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */
#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */
#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */
#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */
#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */
#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */
#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */
#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */
#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */
#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */
#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */
#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */
#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */
#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */
#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */
#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */
#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */
#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */
#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */
#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */
#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */
#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */
#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */
#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */
#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */
#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */
#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */
#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */
#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */
#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */
#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */
#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */
#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */
#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */
#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */
#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */
#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */
#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */
#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */
#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */
#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */
#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */
#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */
#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */
#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */
#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */
#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */
#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */
#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */
#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */
#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */
#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */
#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */
#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */
#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */
#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */
#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */
#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */
#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */
#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */
#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */
#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */
#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */
#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */
#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */
#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */
#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */
#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */
#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */
#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */
#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */
#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */
#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */
#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */
#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */
#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */
#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */
#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */
#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */
#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */
#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */
#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */
#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */
#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */
#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */
#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */
#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */
#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */
#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */
#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */
#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */
/* ************************************************************************** */
/** Event User IDs for SAMD51G18A */
/* ************************************************************************** */
#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */
#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */
#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */
#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */
#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */
#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */
#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */
#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */
#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */
#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */
#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */
#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */
#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */
#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */
#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */
#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */
#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */
#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */
#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */
#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */
#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */
#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */
#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */
#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */
#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */
#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */
#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */
#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */
#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */
#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */
#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */
#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */
#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */
#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */
#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */
#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */
#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */
#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */
#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */
#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */
#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */
#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */
#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */
#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */
#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */
#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */
#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */
#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */
#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */
#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */
#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */
#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */
#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */
#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */
#ifdef __cplusplus
}
#endif
/** @} end of SAMD51G18A definitions */
#endif /* _SAMD51G18A_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/samd51g19a.h
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/**
* \brief Header file for ATSAMD51G19A
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/
/* file generated from device description version 2020-09-28T13:44:39Z */
#ifndef _SAMD51G19A_H_
#define _SAMD51G19A_H_
// Header version uses Semantic Versioning 2.0.0 (https://semver.org/)
#define HEADER_FORMAT_VERSION "2.0.0"
#define HEADER_FORMAT_VERSION_MAJOR (2)
#define HEADER_FORMAT_VERSION_MINOR (0)
/** \addtogroup SAMD51G19A_definitions SAMD51G19A definitions
This file defines all structures and symbols for SAMD51G19A:
- registers and bitfields
- peripheral base address
- peripheral ID
- PIO definitions
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
# include <stdint.h>
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !defined(SKIP_INTEGER_LITERALS)
# if defined(_U_) || defined(_L_) || defined(_UL_)
# error "Integer Literals macros already defined elsewhere"
# endif
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */
# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */
# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
# define _L_(x) x /**< Assembler: Long integer literal constant value */
# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/** @} end of Atmel Global Defines */
/* ************************************************************************** */
/* CMSIS DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** CORTEX-M4 Processor Exceptions Numbers ******************************/
Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */
PendSV_IRQn = -2, /**< -2 Pendable request for system service */
SysTick_IRQn = -1, /**< -1 System Tick Timer */
/****** SAMD51G19A specific Interrupt Numbers ***********************************/
PM_IRQn = 0, /**< 0 Power Manager (PM) */
MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */
OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */
OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */
OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */
OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */
OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */
OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */
SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */
SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */
WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */
RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */
EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */
EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */
EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */
EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */
EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */
EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */
EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */
EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */
EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */
EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */
EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */
EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */
EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */
EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */
EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */
EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */
FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */
NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */
NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */
DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */
DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */
DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */
DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */
DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */
EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */
EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */
EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */
EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */
EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */
PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */
RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */
SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */
SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */
SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */
SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */
SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */
SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */
SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */
SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */
SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */
SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */
SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */
SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */
SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */
SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */
SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */
SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */
SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */
SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */
SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */
SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */
SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */
SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */
SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */
SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */
USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */
USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */
USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */
USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */
TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */
TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */
TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */
TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */
TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */
TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */
TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */
TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */
TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */
TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */
TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */
TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */
TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */
TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */
TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */
TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */
TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */
TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */
TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */
TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */
PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */
PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */
PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */
ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */
ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */
ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */
ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */
AC_IRQn = 122, /**< 122 Analog Comparators (AC) */
DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */
DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */
DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */
DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */
DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */
PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */
AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */
TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */
ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */
PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */
QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */
SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */
PERIPH_MAX_IRQn = 135 /**< Max peripheral ID */
} IRQn_Type;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* CORTEX-M4 handlers */
void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */
void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */
void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */
void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */
void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
void* pvReservedC9;
void* pvReservedC8;
void* pvReservedC7;
void* pvReservedC6;
void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */
void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */
void* pvReservedC3;
void* pfnPendSV_Handler; /* -2 Pendable request for system service */
void* pfnSysTick_Handler; /* -1 System Tick Timer */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager (PM) */
void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */
void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */
void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */
void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */
void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */
void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */
void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */
void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */
void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */
void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */
void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */
void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */
void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */
void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */
void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */
void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */
void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */
void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */
void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */
void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */
void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */
void* pvReserved42;
void* pvReserved43;
void* pvReserved44;
void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */
void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */
void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */
void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */
void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */
void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */
void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */
void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */
void* pvReserved70;
void* pvReserved71;
void* pvReserved72;
void* pvReserved73;
void* pvReserved74;
void* pvReserved75;
void* pvReserved76;
void* pvReserved77;
void* pvReserved78;
void* pvReserved79;
void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */
void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */
void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */
void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */
void* pvReserved84;
void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */
void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */
void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */
void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */
void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */
void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */
void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */
void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */
void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */
void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */
void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */
void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */
void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */
void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */
void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */
void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */
void* pvReserved101;
void* pvReserved102;
void* pvReserved103;
void* pvReserved104;
void* pvReserved105;
void* pvReserved106;
void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */
void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */
void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */
void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */
void* pvReserved111;
void* pvReserved112;
void* pvReserved113;
void* pvReserved114;
void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */
void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */
void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */
void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */
void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */
void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */
void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */
void* pfnAC_Handler; /* 122 Analog Comparators (AC) */
void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */
void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */
void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */
void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */
void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */
void* pvReserved128;
void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */
void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */
void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */
void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */
void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */
void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */
void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */
} DeviceVectors;
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
/* CORTEX-M4 exception handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void MemoryManagement_Handler ( void );
void BusFault_Handler ( void );
void UsageFault_Handler ( void );
void SVCall_Handler ( void );
void DebugMonitor_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
/* Peripherals interrupt handlers */
void PM_Handler ( void );
void MCLK_Handler ( void );
void OSCCTRL_XOSC0_Handler ( void );
void OSCCTRL_XOSC1_Handler ( void );
void OSCCTRL_DFLL_Handler ( void );
void OSCCTRL_DPLL0_Handler ( void );
void OSCCTRL_DPLL1_Handler ( void );
void OSC32KCTRL_Handler ( void );
void SUPC_OTHER_Handler ( void );
void SUPC_BODDET_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_EXTINT_0_Handler ( void );
void EIC_EXTINT_1_Handler ( void );
void EIC_EXTINT_2_Handler ( void );
void EIC_EXTINT_3_Handler ( void );
void EIC_EXTINT_4_Handler ( void );
void EIC_EXTINT_5_Handler ( void );
void EIC_EXTINT_6_Handler ( void );
void EIC_EXTINT_7_Handler ( void );
void EIC_EXTINT_8_Handler ( void );
void EIC_EXTINT_9_Handler ( void );
void EIC_EXTINT_10_Handler ( void );
void EIC_EXTINT_11_Handler ( void );
void EIC_EXTINT_12_Handler ( void );
void EIC_EXTINT_13_Handler ( void );
void EIC_EXTINT_14_Handler ( void );
void EIC_EXTINT_15_Handler ( void );
void FREQM_Handler ( void );
void NVMCTRL_0_Handler ( void );
void NVMCTRL_1_Handler ( void );
void DMAC_0_Handler ( void );
void DMAC_1_Handler ( void );
void DMAC_2_Handler ( void );
void DMAC_3_Handler ( void );
void DMAC_OTHER_Handler ( void );
void EVSYS_0_Handler ( void );
void EVSYS_1_Handler ( void );
void EVSYS_2_Handler ( void );
void EVSYS_3_Handler ( void );
void EVSYS_OTHER_Handler ( void );
void PAC_Handler ( void );
void RAMECC_Handler ( void );
void SERCOM0_0_Handler ( void );
void SERCOM0_1_Handler ( void );
void SERCOM0_2_Handler ( void );
void SERCOM0_OTHER_Handler ( void );
void SERCOM1_0_Handler ( void );
void SERCOM1_1_Handler ( void );
void SERCOM1_2_Handler ( void );
void SERCOM1_OTHER_Handler ( void );
void SERCOM2_0_Handler ( void );
void SERCOM2_1_Handler ( void );
void SERCOM2_2_Handler ( void );
void SERCOM2_OTHER_Handler ( void );
void SERCOM3_0_Handler ( void );
void SERCOM3_1_Handler ( void );
void SERCOM3_2_Handler ( void );
void SERCOM3_OTHER_Handler ( void );
void SERCOM4_0_Handler ( void );
void SERCOM4_1_Handler ( void );
void SERCOM4_2_Handler ( void );
void SERCOM4_OTHER_Handler ( void );
void SERCOM5_0_Handler ( void );
void SERCOM5_1_Handler ( void );
void SERCOM5_2_Handler ( void );
void SERCOM5_OTHER_Handler ( void );
void USB_OTHER_Handler ( void );
void USB_SOF_HSOF_Handler ( void );
void USB_TRCPT0_Handler ( void );
void USB_TRCPT1_Handler ( void );
void TCC0_OTHER_Handler ( void );
void TCC0_MC0_Handler ( void );
void TCC0_MC1_Handler ( void );
void TCC0_MC2_Handler ( void );
void TCC0_MC3_Handler ( void );
void TCC0_MC4_Handler ( void );
void TCC0_MC5_Handler ( void );
void TCC1_OTHER_Handler ( void );
void TCC1_MC0_Handler ( void );
void TCC1_MC1_Handler ( void );
void TCC1_MC2_Handler ( void );
void TCC1_MC3_Handler ( void );
void TCC2_OTHER_Handler ( void );
void TCC2_MC0_Handler ( void );
void TCC2_MC1_Handler ( void );
void TCC2_MC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void PDEC_OTHER_Handler ( void );
void PDEC_MC0_Handler ( void );
void PDEC_MC1_Handler ( void );
void ADC0_OTHER_Handler ( void );
void ADC0_RESRDY_Handler ( void );
void ADC1_OTHER_Handler ( void );
void ADC1_RESRDY_Handler ( void );
void AC_Handler ( void );
void DAC_OTHER_Handler ( void );
void DAC_EMPTY_0_Handler ( void );
void DAC_EMPTY_1_Handler ( void );
void DAC_RESRDY_0_Handler ( void );
void DAC_RESRDY_1_Handler ( void );
void PCC_Handler ( void );
void AES_Handler ( void );
void TRNG_Handler ( void );
void ICM_Handler ( void );
void PUKCC_Handler ( void );
void QSPI_Handler ( void );
void SDHC0_Handler ( void );
#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief Configuration of the CORTEX-M4 Processor and Core Peripherals */
#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */
#define __DEBUG_LVL 3 /**< Debug Level */
#define __FPU_PRESENT 1 /**< FPU present or not */
#define __MPU_PRESENT 1 /**< MPU present or not */
#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
#define __TRACE_LVL 2 /**< Trace Level */
#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
#define __ARCH_ARM 1
#define __ARCH_ARM_CORTEX_M 1
/*
* \brief CMSIS includes
*/
#include "core_cm4.h"
#if defined USE_CMSIS_INIT
#include "system_samd51.h"
#endif /* USE_CMSIS_INIT */
/** \defgroup SAMD51G19A_api Peripheral Software API
* @{
*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */
/* ************************************************************************** */
#include "component/ac.h"
#include "component/adc.h"
#include "component/aes.h"
#include "component/ccl.h"
#include "component/cmcc.h"
#include "component/dac.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/icm.h"
#include "component/mclk.h"
#include "component/nvmctrl.h"
#include "component/osc32kctrl.h"
#include "component/oscctrl.h"
#include "component/pac.h"
#include "component/pcc.h"
#include "component/pdec.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/pukcc.h"
#include "component/qspi.h"
#include "component/ramecc.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdhc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/trng.h"
#include "component/usb.h"
#include "component/wdt.h"
/** @} end of Peripheral Software API */
/** \addtogroup SAMD51G19A_id Peripheral Ids Definitions
* @{
*/
/* ************************************************************************** */
/* PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM ( 1) /**< \brief Power Manager (PM) */
#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */
#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */
#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */
#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */
#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */
#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */
#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */
#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */
#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */
#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */
#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */
#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */
#define ID_PORT ( 36) /**< \brief Port Module (PORT) */
#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */
#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */
#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */
#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */
#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */
#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */
#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */
#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */
#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */
#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */
#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */
#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */
#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */
#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */
#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */
#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */
#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */
#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */
#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */
#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */
#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */
#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */
#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */
#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */
/** @} end of Peripheral Ids Definitions */
/** \addtogroup SAMD51G19A_base Peripheral Base Address Definitions
* @{
*/
/* ************************************************************************** */
/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */
#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */
#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */
#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */
#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */
#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */
#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */
#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */
#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */
#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */
#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */
#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */
#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */
#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */
#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */
#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */
#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */
#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */
#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */
#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */
#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */
#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */
#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */
#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */
#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */
#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */
#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */
#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */
#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */
#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */
#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */
#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */
#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */
#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */
#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */
#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */
#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */
#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */
#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */
#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */
#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */
#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */
#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */
#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */
#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */
#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
/** @} end of Peripheral Base Address Definitions */
/** \addtogroup SAMD51G19A_base Peripheral Base Address Definitions
* @{
*/
/* ************************************************************************** */
/* BASE ADDRESS DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */
#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */
#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */
#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */
#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */
#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */
#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */
#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */
#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */
#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */
#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */
#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */
#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */
#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */
#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */
#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */
#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */
#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */
#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */
#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */
#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */
#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */
#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */
#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */
#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */
#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */
#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */
#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */
#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */
#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */
#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */
#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */
#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */
#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */
#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */
#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */
#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */
#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */
#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */
#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */
#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */
#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */
#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */
#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */
#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */
#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */
/** @} end of Peripheral Base Address Definitions */
/** \addtogroup SAMD51G19A_pio Peripheral Pio Definitions
* @{
*/
/* ************************************************************************** */
/* PIO DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#include "pio/samd51g19a.h"
/** @} end of Peripheral Pio Definitions */
/* ************************************************************************** */
/* MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */
#define FLASH_PAGE_SIZE _UL_( 512)
#define FLASH_NB_OF_PAGES _UL_( 1024)
#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */
#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */
#define TEMP_LOG_PAGE_SIZE _UL_( 512)
#define TEMP_LOG_NB_OF_PAGES _UL_( 1)
#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */
#define USER_PAGE_PAGE_SIZE _UL_( 512)
#define USER_PAGE_NB_OF_PAGES _UL_( 1)
#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */
#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */
#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */
#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */
#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */
#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */
#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */
#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */
#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */
#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */
#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */
#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */
#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */
#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/
#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/
#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/
#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/
#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/
#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/
#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/
#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/
#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/
#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/
#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/
#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/
#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/
#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/
#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/
#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/
/* ************************************************************************** */
/** DEVICE SIGNATURES FOR SAMD51G19A */
/* ************************************************************************** */
#define CHIP_DSU_DID _UL_(0X60060307)
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */
/* ************************************************************************** */
/* ************************************************************************** */
/** Event Generator IDs for SAMD51G19A */
/* ************************************************************************** */
#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */
#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */
#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */
#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */
#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */
#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */
#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */
#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */
#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */
#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */
#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */
#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */
#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */
#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */
#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */
#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */
#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */
#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */
#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */
#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */
#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */
#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */
#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */
#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */
#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */
#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */
#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */
#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */
#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */
#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */
#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */
#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */
#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */
#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */
#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */
#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */
#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */
#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */
#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */
#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */
#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */
#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */
#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */
#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */
#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */
#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */
#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */
#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */
#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */
#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */
#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */
#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */
#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */
#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */
#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */
#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */
#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */
#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */
#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */
#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */
#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */
#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */
#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */
#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */
#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */
#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */
#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */
#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */
#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */
#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */
#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */
#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */
#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */
#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */
#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */
#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */
#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */
#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */
#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */
#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */
#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */
#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */
#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */
#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */
#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */
#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */
#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */
#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */
#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */
#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */
#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */
#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */
#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */
#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */
/* ************************************************************************** */
/** Event User IDs for SAMD51G19A */
/* ************************************************************************** */
#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */
#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */
#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */
#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */
#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */
#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */
#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */
#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */
#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */
#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */
#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */
#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */
#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */
#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */
#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */
#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */
#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */
#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */
#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */
#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */
#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */
#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */
#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */
#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */
#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */
#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */
#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */
#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */
#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */
#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */
#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */
#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */
#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */
#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */
#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */
#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */
#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */
#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */
#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */
#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */
#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */
#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */
#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */
#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */
#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */
#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */
#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */
#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */
#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */
#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */
#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */
#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */
#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */
#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */
#ifdef __cplusplus
}
#endif
/** @} end of SAMD51G19A definitions */
#endif /* _SAMD51G19A_H_ */

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arch/arm/SAMD51/SAMD51A/mcu/inc/system_samd51.h
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/**
* \file
*
* \brief Low-level initialization functions called upon device startup
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _SYSTEM_SAMD51_H_INCLUDED_
#define _SYSTEM_SAMD51_H_INCLUDED_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
void SystemInit(void);
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_SAMD51_H_INCLUDED */

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arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g18a.c
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/**
* \file
*
* \brief GCC startup file for ATSAMD51G18A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51g18a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

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arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51g19a.c
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@ -0,0 +1,385 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51G19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51g19a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pvReserved101 = (void*) (0UL), /* 101 Reserved */
.pvReserved102 = (void*) (0UL), /* 102 Reserved */
.pvReserved103 = (void*) (0UL), /* 103 Reserved */
.pvReserved104 = (void*) (0UL), /* 104 Reserved */
.pvReserved105 = (void*) (0UL), /* 105 Reserved */
.pvReserved106 = (void*) (0UL), /* 106 Reserved */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pvReserved111 = (void*) (0UL), /* 111 Reserved */
.pvReserved112 = (void*) (0UL), /* 112 Reserved */
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pvReserved128 = (void*) (0UL), /* 128 Reserved */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

394
arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j18a.c
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@ -0,0 +1,394 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51J18A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j18a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

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arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j19a.c
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@ -0,0 +1,394 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51J19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j19a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

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arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51j20a.c
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@ -0,0 +1,394 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51J20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j20a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pvReserved70 = (void*) (0UL), /* 70 Reserved */
.pvReserved71 = (void*) (0UL), /* 71 Reserved */
.pvReserved72 = (void*) (0UL), /* 72 Reserved */
.pvReserved73 = (void*) (0UL), /* 73 Reserved */
.pvReserved74 = (void*) (0UL), /* 74 Reserved */
.pvReserved75 = (void*) (0UL), /* 75 Reserved */
.pvReserved76 = (void*) (0UL), /* 76 Reserved */
.pvReserved77 = (void*) (0UL), /* 77 Reserved */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pvReserved113 = (void*) (0UL), /* 113 Reserved */
.pvReserved114 = (void*) (0UL), /* 114 Reserved */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler /* 135 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

406
arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n19a.c
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@ -0,0 +1,406 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51N19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51n19a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */
.pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */
.pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

406
arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51n20a.c
Unescape Escape View File

@ -0,0 +1,406 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51N20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51n20a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */
.pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */
.pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

406
arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p19a.c
Unescape Escape View File

@ -0,0 +1,406 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51P19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51p19a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */
.pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */
.pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

406
arch/arm/SAMD51/SAMD51A/mcu/src/startup_samd51p20a.c
Unescape Escape View File

@ -0,0 +1,406 @@
/**
* \file
*
* \brief GCC startup file for ATSAMD51P20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51p20a.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Reset handler */
void Reset_Handler(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M4 core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler,
.pfnBusFault_Handler = (void*) BusFault_Handler,
.pfnUsageFault_Handler = (void*) UsageFault_Handler,
.pvReservedC9 = (void*) (0UL), /* Reserved */
.pvReservedC8 = (void*) (0UL), /* Reserved */
.pvReservedC7 = (void*) (0UL), /* Reserved */
.pvReservedC6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler,
.pvReservedC3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */
.pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */
.pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */
.pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */
.pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */
.pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */
.pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */
.pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */
.pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */
.pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */
.pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */
.pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */
.pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */
.pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */
.pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */
.pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */
.pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */
.pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */
.pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */
.pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */
.pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */
.pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */
.pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */
.pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */
.pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */
.pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */
.pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */
.pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */
.pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */
.pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */
.pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */
.pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */
.pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */
.pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */
.pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */
.pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */
.pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */
.pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */
.pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */
.pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */
.pvReserved42 = (void*) (0UL), /* 42 Reserved */
.pvReserved43 = (void*) (0UL), /* 43 Reserved */
.pvReserved44 = (void*) (0UL), /* 44 Reserved */
.pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */
.pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */
.pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */
.pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */
.pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */
.pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */
.pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */
.pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */
.pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */
.pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */
.pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */
.pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */
.pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */
.pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */
.pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */
.pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */
.pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */
.pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */
.pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */
.pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */
.pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */
.pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */
.pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */
.pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */
.pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */
.pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */
.pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */
.pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */
.pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */
.pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */
.pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */
.pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */
.pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */
.pvReserved78 = (void*) (0UL), /* 78 Reserved */
.pvReserved79 = (void*) (0UL), /* 79 Reserved */
.pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */
.pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */
.pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */
.pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */
.pvReserved84 = (void*) (0UL), /* 84 Reserved */
.pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */
.pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */
.pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */
.pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */
.pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */
.pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */
.pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */
.pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */
.pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */
.pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */
.pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */
.pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */
.pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */
.pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */
.pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */
.pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */
.pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */
.pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */
.pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */
.pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */
.pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */
.pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */
.pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */
.pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */
.pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */
.pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */
.pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */
.pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */
.pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */
.pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */
.pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */
.pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */
.pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */
.pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */
.pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */
.pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */
.pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */
.pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */
.pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */
.pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */
.pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */
.pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */
.pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */
.pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */
.pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */
.pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */
.pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */
.pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */
.pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */
.pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g18a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51G18A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51g18a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51g19a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51G19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51g19a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j18a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51J18A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j18a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j19a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51J19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j19a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51j20a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51J20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51j20a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n19a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51N19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51n19a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51n20a.c
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@ -0,0 +1,80 @@
/**
* \file
*
* \brief System configuration file for ATSAMD51N20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51n20a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p19a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51P19A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51p19a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

80
arch/arm/SAMD51/SAMD51A/mcu/src/system_samd51p20a.c
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/**
* \file
*
* \brief System configuration file for ATSAMD51P20A
*
* Copyright (c) 2020 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#include "samd51p20a.h"
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
extern "C" {
#endif
/* *INDENT-ON* */
/** \endcond */
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (48000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* \brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/** \cond 0 */
/* *INDENT-OFF* */
#ifdef __cplusplus
}
#endif
/* *INDENT-ON* */
/** \endcond */

163
arch/arm/SAME54/ld/same54n19a_flash.ld
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/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAME54/ld/same54n19a_sram.ld
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@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAME54/ld/same54n20a_flash.ld
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@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

162
arch/arm/SAME54/ld/same54n20a_sram.ld
Unescape Escape View File

@ -0,0 +1,162 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

163
arch/arm/SAME54/ld/same54p19a_flash.ld
Unescape Escape View File

@ -0,0 +1,163 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54P19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

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